8341 files changed, 279903 insertions, 0 deletions

diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/121127.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/121127.c
new file mode 100644
index 000000000..a7dca09fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/121127.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-g -femit-struct-debug-baseonly" } */
+
+typedef __builtin_va_list __gnuc_va_list;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp
new file mode 100644
index 000000000..195f977c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/aapcs64.exp
@@ -0,0 +1,67 @@
+#  Copyright (C) 2009-2014 Free Software Foundation, Inc.
+#  Contributed by ARM Ltd.
+#
+#  This file is part of GCC.
+#
+#  GCC is free software; you can redistribute it and/or modify it
+#  under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 3, or (at your option)
+#  any later version.
+#
+#  GCC is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with GCC; see the file COPYING3.  If not see
+#  <http://www.gnu.org/licenses/>.  */
+
+load_lib c-torture.exp
+load_lib target-supports.exp
+load_lib torture-options.exp
+
+if { ![istarget aarch64*-*-*] } then {
+  return
+}
+
+torture-init
+set-torture-options $C_TORTURE_OPTIONS
+set additional_flags "-W -Wall -Wno-abi"
+
+# Test parameter passing.
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/abitest.S] \
+				    $additional_flags
+    }
+}
+
+# Test unnamed argument retrieval via the va_arg macro.
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/va_arg-*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/abitest.S] \
+				    $additional_flags
+    }
+}
+
+# Test function return value.
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/func-ret-*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/abitest.S] \
+				    $additional_flags
+    }
+}
+
+# Test no internal compiler errors.
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/ice_*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	    c-torture [list $src] \
+			    $additional_flags
+    }
+}
+
+torture-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h
new file mode 100644
index 000000000..c56e7cc67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-2.h
@@ -0,0 +1,101 @@
+/* This header file should be included for the purpose of function return
+   value testing.  */
+
+#include "abitest-common.h"
+#include "validate_memory.h"
+
+void (*testfunc_ptr)(char* stack);
+
+/* Helper macros to generate function name.  Example of the function name:
+   func_return_val_1.  */
+#define FUNC_BASE_NAME func_return_val_
+#define FUNC_NAME_COMBINE(base,suffix) base ## suffix
+#define FUNC_NAME_1(base,suffix) FUNC_NAME_COMBINE(base,suffix)
+#define FUNC_NAME(suffix) FUNC_NAME_1(FUNC_BASE_NAME,suffix)
+#define TEST_FUNC_BASE_NAME testfunc_
+#define TEST_FUNC_NAME(suffix) FUNC_NAME_1(TEST_FUNC_BASE_NAME,suffix)
+
+#undef DUMP_STATUS
+#ifdef DUMP_ENABLED
+#define DUMP_STATUS(type,val) printf ("### Checking "#type" "#val"\n");
+#else
+#define DUMP_STATUS(type,val)
+#endif
+
+/* Generate code to do memcmp to check if the returned value is in the
+   correct location and has the expected value.
+   Note that for value that is returned in the caller-allocated memory
+   block, we get the address from the saved x8 register.  x8 is saved
+   just after the callee is returned; we assume that x8 has not been
+   clobbered at then, although there is no requirement for the callee
+   preserve the value stored in x8.  Luckily, all test cases here are
+   simple enough that x8 doesn't normally get clobbered (although not
+   guaranteed).  */
+#undef FUNC_VAL_CHECK
+#define FUNC_VAL_CHECK(id, type, val, offset, layout)			\
+void TEST_FUNC_NAME(id)(char* stack)					\
+{									\
+  type __x = val;							\
+  char* addr;								\
+  DUMP_STATUS(type,val)							\
+  if (offset != X8)							\
+    addr = stack + offset;						\
+  else									\
+    addr = *(char **)(stack + X8);					\
+  if (validate_memory (&__x, addr, sizeof (type), layout) != 0)		\
+    abort();								\
+}
+
+/* Composite larger than 16 bytes is replaced by a pointer to a copy prepared
+   by the caller, so here we extrat the pointer, deref it and compare the
+   content with that of the original one.  */
+#define PTR(type, val, offset, ...) {					\
+  type * ptr;								\
+  DUMP_ARG(type,val)							\
+  ptr = *(type **)(stack + offset);					\
+  if (memcmp (ptr, &val, sizeof (type)) != 0) abort ();			\
+}
+
+#include TESTFILE
+
+MYFUNCTYPE myfunc () PCSATTR;
+
+/* Define the function to return VAL of type TYPE.  I and D in the
+   parameter list are two dummy parameters to help improve the detection
+   of bugs like a short vector being returned in X0 after copied from V0.  */
+#undef FUNC_VAL_CHECK
+#define FUNC_VAL_CHECK(id, type, var, offset, layout)			  \
+__attribute__ ((noinline)) type FUNC_NAME (id) (int i, double d, type t)  \
+  {									  \
+    asm (""::"r" (i),"r" (d)); /* asm prevents function from getting      \
+				  optimized away.  Using i and d prevents \
+				  warnings about unused parameters.	  \
+			       */					  \
+    return t;								  \
+  }
+#include TESTFILE
+
+
+/* Call the function to return value and call the checking function
+   to validate.  See the comment above for the reason of having 0 and 0.0
+   in the function argument list.  */
+#undef FUNC_VAL_CHECK
+#define FUNC_VAL_CHECK(id, type, var, offset, layout)			\
+  {									\
+    testfunc_ptr = TEST_FUNC_NAME(id);					\
+    FUNC_NAME(id) (0, 0.0, var);					\
+    myfunc ();								\
+  }
+
+int main()
+{
+  which_kind_of_test = TK_RETURN;
+
+#ifdef HAS_DATA_INIT_FUNC
+  init_data ();
+#endif
+
+#include TESTFILE
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h
new file mode 100644
index 000000000..4e2ef0dac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest-common.h
@@ -0,0 +1,139 @@
+#undef __AAPCS64_BIG_ENDIAN__
+#ifdef __GNUC__
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#define __AAPCS64_BIG_ENDIAN__
+#endif
+#else
+#error unknown compiler
+#endif
+
+#define IN_FRAMEWORK
+
+#define D0	0
+#define D1	8
+#define D2	16
+#define D3	24
+#define D4	32
+#define D5	40
+#define D6	48
+#define D7	56
+
+#define S0	64
+#define S1	68
+#define S2	72
+#define S3	76
+#define S4	80
+#define S5	84
+#define S6	88
+#define S7	92
+
+#define W0      96
+#define W1     100
+#define W2     104
+#define W3     108
+#define W4     112
+#define W5     116
+#define W6     120
+#define W7     124
+
+#define X0     128
+#define X1     136
+#define X2     144
+#define X3     152
+#define X4     160
+#define X5     168
+#define X6     176
+#define X7     184
+
+#define Q0     192
+#define Q1     208
+#define Q2     224
+#define Q3     240
+#define Q4     256
+#define Q5     272
+#define Q6     288
+#define Q7     304
+
+#define X8     320
+#define X9     328
+
+#define STACK  336
+
+/* The type of test.  'myfunc' in abitest.S needs to know which kind of
+   test it is running to decide what to do at the runtime.  Keep the
+   related code in abitest.S synchronized if anything is changed here.  */
+enum aapcs64_test_kind
+{
+  TK_PARAM = 0,	/* Test parameter passing.  */
+  TK_VA_ARG,	/* Test va_arg code generation.  */
+  TK_RETURN	/* Test function return value.  */
+};
+
+int which_kind_of_test;
+
+extern int printf (const char*, ...);
+extern void abort (void);
+extern void dumpregs () __asm("myfunc");
+
+#ifndef MYFUNCTYPE
+#define MYFUNCTYPE void
+#endif
+
+#ifndef PCSATTR
+#define PCSATTR
+#endif
+
+
+#ifdef RUNTIME_ENDIANNESS_CHECK
+#ifndef RUNTIME_ENDIANNESS_CHECK_FUNCTION_DEFINED
+/* This helper function defined to detect whether there is any incompatibility
+   issue on endianness between compilation time and run-time environments.
+   TODO: review the implementation when the work of big-endian support in A64
+   GCC starts.
+   */
+static void rt_endian_check ()
+{
+  const char* msg_endian[2] = {"little-endian", "big-endian"};
+  const char* msg_env[2] = {"compile-time", "run-time"};
+  union
+  {
+    unsigned int ui;
+    unsigned char ch[4];
+  } u;
+  int flag = -1;
+
+  u.ui = 0xCAFEBABE;
+
+  printf ("u.ui=0x%X, u.ch[0]=0x%X\n", u.ui, u.ch[0]);
+
+  if (u.ch[0] == 0xBE)
+    {
+      /* Little-Endian at run-time */
+#ifdef __AAPCS64_BIG_ENDIAN__
+      /* Big-Endian at compile-time */
+      flag = 1;
+#endif
+    }
+  else
+    {
+      /* Big-Endian at run-time */
+#ifndef __AAPCS64_BIG_ENDIAN__
+      /* Little-Endian at compile-time */
+      flag = 0;
+#endif
+    }
+
+  if (flag != -1)
+    {
+      /* Endianness conflict exists */
+      printf ("Error: endianness conflicts between %s and %s:\n\
+\t%s: %s\n\t%s: %s\n", msg_env[0], msg_env[1], msg_env[0], msg_endian[flag],
+		       msg_env[1], msg_endian[1-flag]);
+      abort ();
+    }
+
+  return;
+}
+#endif
+#define RUNTIME_ENDIANNESS_CHECK_FUNCTION_DEFINED
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.S b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.S
new file mode 100644
index 000000000..86ce7bed7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.S
@@ -0,0 +1,59 @@
+	.global dumpregs
+	.global myfunc
+	.type dumpregs,%function
+	.type myfunc,%function
+dumpregs:
+myfunc:
+      mov	x16, sp
+      mov	x17, sp
+      sub	sp,  sp, 352 // 336 for registers and 16 for old sp and lr
+
+      stp	x8, x9, [x17, #-16]! //320
+
+      stp	q6, q7, [x17, #-32]! //288
+      stp	q4, q5, [x17, #-32]! //256
+      stp	q2, q3, [x17, #-32]! //224
+      stp	q0, q1, [x17, #-32]! //192
+
+      stp	x6, x7, [x17, #-16]! //176
+      stp	x4, x5, [x17, #-16]! //160
+      stp	x2, x3, [x17, #-16]! //144
+      stp	x0, x1, [x17, #-16]! //128
+
+      stp	w6, w7, [x17, #-8]!  //120
+      stp	w4, w5, [x17, #-8]!  //112
+      stp	w2, w3, [x17, #-8]!  //104
+      stp	w0, w1, [x17, #-8]!  // 96
+
+      stp	s6, s7, [x17, #-8]!  // 88
+      stp	s4, s5, [x17, #-8]!  // 80
+      stp	s2, s3, [x17, #-8]!  // 72
+      stp	s0, s1, [x17, #-8]!  // 64
+
+      stp	d6, d7, [x17, #-16]! // 48
+      stp	d4, d5, [x17, #-16]! // 32
+      stp	d2, d3, [x17, #-16]! // 16
+      stp	d0, d1, [x17, #-16]! //  0
+
+      add	x0, sp,  #16
+      stp	x16, x30, [x17, #-16]!
+
+      adrp	x9, which_kind_of_test		// determine the type of test
+      add	x9, x9, :lo12:which_kind_of_test
+      ldr	w9, [x9, #0]
+      cmp	w9, #1
+      bgt	LABEL_TEST_FUNC_RETURN
+      bl	testfunc			// parameter passing test or va_arg code gen test
+      b		LABEL_RET
+LABEL_TEST_FUNC_RETURN:
+      adrp	x9, testfunc_ptr
+      add	x9, x9, :lo12:testfunc_ptr
+      ldr	x9, [x9, #0]
+      blr	x9				// function return value test
+LABEL_RET:
+      ldp	x0, x30, [sp]
+      mov	sp, x0
+      ret
+
+.weak	testfunc
+.weak	testfunc_ptr
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h
new file mode 100644
index 000000000..af70937e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/abitest.h
@@ -0,0 +1,159 @@
+/* This header file should be included for the purpose of parameter passing
+   testing and va_arg code gen testing.
+
+   To test va_arg code gen, #define AAPCS64_TEST_STDARG in the test case.
+
+   The parameter passing test is done by passing variables/constants to
+   'myfunc', which pushes its incoming arguments to a memory block on the
+   stack and then passes the memory block address to 'testfunc'.  It is inside
+   'testfunc' that the real parameter passing check is carried out.
+
+   The function body of 'myfunc' is in abitest.S.  The declaration of 'myfunc'
+   is constructed during the pre-processing stage.
+
+   The va_arg code gen test has a similar workflow, apart from an extra set-up
+   step before calling 'myfunc'.  All arguments are passed to 'stdarg_func'
+   first, which assigned these arguments to its local variables via either
+   direct assignment or va_arg macro, depending on whether an argument is named
+   or not.  Afterwards, 'stdarg_func' calls 'myfunc' with the aforementioned
+   local variables as the arguments to finish the remaining steps.  */
+
+#include "abitest-common.h"
+#include "validate_memory.h"
+
+#ifdef AAPCS64_TEST_STDARG
+/* Generate va_start (ap, last_named_arg).  Note that this requires
+   LAST_NAMED_ARG_ID to be defined/used correctly in the test file.  */
+#ifndef LAST_NAMED_ARG_ID
+#define LAST_NAMED_ARG_ID 65535
+#endif
+#ifndef VA_START
+#undef VA_START_1
+#define VA_START_1(ap, id) va_start (ap, _f##id);
+#define VA_START(ap, id) VA_START_1 (ap, id);
+#endif
+#endif /* AAPCS64_TEST_STDARG */
+
+/* Some debugging facility.  */
+#undef DUMP_ARG
+#ifdef DUMP_ENABLED
+#define DUMP_ARG(type,val) printf ("### Checking ARG "#type" "#val"\n")
+#else
+#define DUMP_ARG(type,val)
+#endif
+
+
+/* Function called from myfunc (defined in abitest.S) to check the arguments
+   passed to myfunc.  myfunc has pushed all the arguments into the memory
+   block pointed by STACK.  */
+void testfunc(char* stack)
+{
+#define AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+  return;
+}
+
+
+#ifndef AAPCS64_TEST_STDARG
+/* Test parameter passing.  */
+
+/* Function declaration of myfunc.  */
+MYFUNCTYPE myfunc(
+#define AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+) PCSATTR;
+
+#else /* AAPCS64_TEST_STDARG */
+/* Test stdarg macros, e.g. va_arg.  */
+#include <stdarg.h>
+
+/* Dummy function to help reset parameter passing registers, i.e. X0-X7
+   and V0-V7 (by being passed 0 in W0-W7 and 0.f in S0-S7).  */
+__attribute__ ((noinline)) void
+dummy_func (int w0, int w1, int w2, int w3, int w4, int w5, int w6, int w7,
+	    float s0, float s1, float s2, float s3, float s4, float s5,
+	    float s6, float s7)
+{
+  asm (""); /* Prevent function from getting optimized away */
+  return;
+}
+
+/* Function declaration of myfunc.  */
+MYFUNCTYPE myfunc(
+#define AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+) PCSATTR;
+
+/* Function definition of stdarg_func.
+   stdarg_func is a variadic function; it retrieves all of its arguments,
+   both named and unnamed, and passes them to myfunc in the identical
+   order.  myfunc will carry out the check on the passed values.  Remember
+   that myfunc is not a variadic function.  */
+MYFUNCTYPE stdarg_func(
+#define AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+) PCSATTR
+{
+  /* Start of the function body of stdarg_func.  */
+  va_list ap;
+
+  VA_START (ap, LAST_NAMED_ARG_ID)
+  /* Zeroize the content of X0-X7 and V0-V7 to make sure that any va_arg
+     failure will not be hidden by the old data being in these registers.  */
+  dummy_func (0, 0, 0, 0, 0, 0, 0, 0, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f, 0.f);
+  /* A full memory barrier to ensure that compiler won't optimize away
+     va_arg code gen.  */
+  __sync_synchronize ();
+    {
+      /* Assign all the function incoming arguments to local variables. */
+#define AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+
+      /* Call myfunc and pass in the local variables prepared above.  */
+      myfunc (
+#define AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+);
+    }
+  va_end (ap);
+}
+
+#endif /* AAPCS64_TEST_STDARG */
+
+
+int main()
+{
+#ifdef RUNTIME_ENDIANNESS_CHECK
+  rt_endian_check();
+#endif
+#ifdef HAS_DATA_INIT_FUNC
+  init_data ();
+#endif
+
+#ifndef AAPCS64_TEST_STDARG
+  which_kind_of_test = TK_PARAM;
+  myfunc(
+#else
+  which_kind_of_test = TK_VA_ARG;
+  stdarg_func(
+#endif
+#define AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+#include "macro-def.h"
+#include TESTFILE
+#undef AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+);
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c
new file mode 100644
index 000000000..16b5c1efd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-1.c
@@ -0,0 +1,44 @@
+/* Test AAPCS64 function result return.
+
+   This test covers most fundamental data types as specified in
+   AAPCS64 \S 4.1.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-additional-sources "abitest.S" } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "func-ret-1.c"
+#include "type-def.h"
+
+vf2_t vf2 = (vf2_t){ 17.f, 18.f };
+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead };
+union int128_t qword;
+
+int *int_ptr = (int *)0xabcdef0123456789ULL;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  /* Init signed quad-word integer.  */
+  qword.l64 = 0xfdb9753102468aceLL;
+  qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest-2.h"
+#else
+FUNC_VAL_CHECK (0, unsigned char , 0xfe      , X0, i8in64)
+FUNC_VAL_CHECK (1,   signed char , 0xed      , X0, i8in64)
+FUNC_VAL_CHECK (2, unsigned short, 0xdcba    , X0, i16in64)
+FUNC_VAL_CHECK (3,   signed short, 0xcba9    , X0, i16in64)
+FUNC_VAL_CHECK (4, unsigned int  , 0xdeadbeef, X0, i32in64)
+FUNC_VAL_CHECK (5,   signed int  , 0xcafebabe, X0, i32in64)
+FUNC_VAL_CHECK (6, unsigned long long, 0xba98765432101234ULL, X0, flat)
+FUNC_VAL_CHECK (7,   signed long long, 0xa987654321012345LL, X0, flat)
+FUNC_VAL_CHECK (8,       __int128, qword.i, X0, flat)
+FUNC_VAL_CHECK (9,          float, 65432.12345f, S0, flat)
+FUNC_VAL_CHECK (10,        double, 9876543.212345, D0, flat)
+FUNC_VAL_CHECK (11,   long double, 98765432123456789.987654321L, Q0, flat)
+FUNC_VAL_CHECK (12,         vf2_t,        vf2, D0, f32in64)
+FUNC_VAL_CHECK (13,         vi4_t,        vi4, Q0, i32in128)
+FUNC_VAL_CHECK (14,         int *,    int_ptr, X0, flat)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c
new file mode 100644
index 000000000..6b171c46f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-2.c
@@ -0,0 +1,71 @@
+/* Test AAPCS64 function result return.
+
+   This test covers most composite types as described in AAPCS64 \S 4.3.
+   Homogeneous floating-point aggregate types are covered in func-ret-3.c.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-additional-sources "abitest.S" } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "func-ret-2.c"
+
+struct x0
+{
+  char ch;
+  int i;
+} ys0 = { 'a', 12345 };
+
+struct x1
+{
+  int a;
+  unsigned int b;
+  unsigned int c;
+  unsigned int d;
+} ys1 = { 0xdeadbeef, 0xcafebabe, 0x87654321, 0xbcedf975 };
+
+struct x2
+{
+  long long a;
+  long long b;
+  char ch;
+} y2 = { 0x12, 0x34, 0x56 };
+
+union x3
+{
+  char ch;
+  int i;
+  long long ll;
+} y3;
+
+union x4
+{
+  int i;
+  struct x2 y2;
+} y4;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  /* Init small union.  */
+  y3.ll = 0xfedcba98LL;
+
+  /* Init big union.  */
+  y4.y2.a = 0x78;
+  y4.y2.b = 0x89;
+  y4.y2.ch= 0x9a;
+}
+
+
+#include "abitest-2.h"
+#else
+  /* Composite smaller than or equal to 16 bytes returned in X0 and X1.  */
+FUNC_VAL_CHECK ( 0, struct x0, ys0, X0, flat)
+FUNC_VAL_CHECK ( 1, struct x1, ys1, X0, flat)
+FUNC_VAL_CHECK ( 2, union  x3, y3, X0, flat)
+
+  /* Composite larger than 16 bytes returned in the caller-reserved memory
+     block of which the address is passed as an additional argument to the
+     function in X8.  */
+FUNC_VAL_CHECK (10, struct x2, y2, X8, flat)
+FUNC_VAL_CHECK (11, union  x4, y4, X8, flat)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c
new file mode 100644
index 000000000..ff9b7e6d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-3.c
@@ -0,0 +1,93 @@
+/* Test AAPCS64 function result return.
+
+   This test covers homogeneous floating-point aggregate types as described
+   in AAPCS64 \S 4.3.5.  */
+
+/* { dg-do run { target aarch64-*-* } } */
+/* { dg-additional-sources "abitest.S" } */
+/* { dg-require-effective-target aarch64_big_endian } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "func-ret-3.c"
+#include "type-def.h"
+
+struct hfa_fx1_t hfa_fx1 = {12.345f};
+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f};
+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678};
+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456};
+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012};
+struct non_hfa_fx5_t non_hfa_fx5 = {456.789f, 567.890f, 678.901f, 789.012f, 890.123f};
+struct hfa_ffs_t hfa_ffs;
+struct non_hfa_ffs_t non_hfa_ffs;
+struct non_hfa_ffs_2_t non_hfa_ffs_2;
+struct hva_vf2x1_t hva_vf2x1;
+struct hva_vi4x1_t hva_vi4x1;
+struct non_hfa_ffd_t non_hfa_ffd = {23.f, 24.f, 25.0};
+struct non_hfa_ii_t non_hfa_ii = {26, 27};
+struct non_hfa_c_t non_hfa_c = {28};
+struct non_hfa_ffvf2_t non_hfa_ffvf2;
+struct non_hfa_fffd_t non_hfa_fffd = {33.f, 34.f, 35.f, 36.0};
+union hfa_union_t hfa_union;
+union non_hfa_union_t non_hfa_union;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  hva_vf2x1.a = (vf2_t){17.f, 18.f};
+  hva_vi4x1.a = (vi4_t){19, 20, 21, 22};
+
+  non_hfa_ffvf2.a = 29.f;
+  non_hfa_ffvf2.b = 30.f;
+  non_hfa_ffvf2.c = (vf2_t){31.f, 32.f};
+
+  hfa_union.s.a = 37.f;
+  hfa_union.s.b = 38.f;
+  hfa_union.c   = 39.f;
+
+  non_hfa_union.a = 40.0;
+  non_hfa_union.b = 41.f;
+
+  hfa_ffs.a = 42.f;
+  hfa_ffs.b = 43.f;
+  hfa_ffs.c.a = 44.f;
+  hfa_ffs.c.b = 45.f;
+
+  non_hfa_ffs.a = 46.f;
+  non_hfa_ffs.b = 47.f;
+  non_hfa_ffs.c.a = 48.0;
+  non_hfa_ffs.c.b = 49.0;
+
+  non_hfa_ffs_2.s.a = 50;
+  non_hfa_ffs_2.s.b = 51;
+  non_hfa_ffs_2.c = 52.f;
+  non_hfa_ffs_2.d = 53.f;
+}
+
+#include "abitest-2.h"
+#else
+  /* HFA returned in fp/simd registers.  */
+
+FUNC_VAL_CHECK ( 0, struct hfa_fx1_t , hfa_fx1  , S0, flat)
+FUNC_VAL_CHECK ( 1, struct hfa_fx2_t , hfa_fx2  , S0, flat)
+FUNC_VAL_CHECK ( 2, struct hfa_dx2_t , hfa_dx2  , D0, flat)
+
+FUNC_VAL_CHECK ( 3, struct hfa_dx4_t , hfa_dx4  , D0, flat)
+FUNC_VAL_CHECK ( 4, struct hfa_ldx3_t, hfa_ldx3 , Q0, flat)
+FUNC_VAL_CHECK ( 5, struct hfa_ffs_t , hfa_ffs  , S0, flat)
+FUNC_VAL_CHECK ( 6, union hfa_union_t, hfa_union, S0, flat)
+
+FUNC_VAL_CHECK ( 7, struct hva_vf2x1_t, hva_vf2x1, D0, flat)
+FUNC_VAL_CHECK ( 8, struct hva_vi4x1_t, hva_vi4x1, Q0, flat)
+
+  /* Non-HFA returned in general registers or via a pointer in X8.  */
+FUNC_VAL_CHECK (10, struct non_hfa_fx5_t  , non_hfa_fx5  , X8, flat)
+FUNC_VAL_CHECK (13, struct non_hfa_ffd_t  , non_hfa_ffd  , X0, flat)
+FUNC_VAL_CHECK (14, struct non_hfa_ii_t   , non_hfa_ii   , X0, flat)
+FUNC_VAL_CHECK (15, struct non_hfa_c_t    , non_hfa_c    , X0, flat)
+FUNC_VAL_CHECK (16, struct non_hfa_ffvf2_t, non_hfa_ffvf2, X0, flat)
+FUNC_VAL_CHECK (17, struct non_hfa_fffd_t , non_hfa_fffd , X8, flat)
+FUNC_VAL_CHECK (18, struct non_hfa_ffs_t  , non_hfa_ffs  , X8, flat)
+FUNC_VAL_CHECK (19, struct non_hfa_ffs_2_t, non_hfa_ffs_2, X0, flat)
+FUNC_VAL_CHECK (20, union  non_hfa_union_t, non_hfa_union, X0, flat)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c
new file mode 100644
index 000000000..af05fbe9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/func-ret-4.c
@@ -0,0 +1,27 @@
+/* Test AAPCS64 function result return.
+
+   This test covers complex types.  Complex floating-point types are treated
+   as homogeneous floating-point aggregates, while complex integral types
+   are treated as general composite types.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-additional-sources "abitest.S" } */
+/* { dg-require-effective-target aarch64_big_endian } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "func-ret-4.c"
+
+#include "abitest-2.h"
+#else
+  /* Complex floating-point types are passed in fp/simd registers.  */
+FUNC_VAL_CHECK ( 0, _Complex float , 12.3f + 23.4fi, S0, flat)
+FUNC_VAL_CHECK ( 1, _Complex double, 34.56 + 45.67i, D0, flat)
+FUNC_VAL_CHECK ( 2, _Complex long double, 56789.01234 + 67890.12345i, Q0, flat)
+
+  /* Complex integral types are passed in general registers or via a pointer in
+     X8.  */
+FUNC_VAL_CHECK (10, _Complex short , 12345 + 23456i, X0, flat)
+FUNC_VAL_CHECK (11, _Complex int   , 34567 + 45678i, X0, flat)
+FUNC_VAL_CHECK (12, _Complex __int128, 567890 + 678901i, X8, flat)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_1.c
new file mode 100644
index 000000000..906ccebf6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_1.c
@@ -0,0 +1,21 @@
+/* Test AAPCS layout
+
+   Empty, i.e. zero-sized, small struct passing used to cause Internal Compiler
+   Error.  */
+
+/* { dg-do compile { target aarch64*-*-* } } */
+
+struct AAAA
+{
+
+} aaaa;
+
+
+void named (int, struct AAAA);
+void unnamed (int, ...);
+
+void foo ()
+{
+  name (0, aaaa);
+  unnamed (0, aaaa);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_2.c
new file mode 100644
index 000000000..8d34f270d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_2.c
@@ -0,0 +1,13 @@
+/* Test AAPCS layout
+
+   Larger than machine-supported vector size.  The behaviour is unspecified by
+   the AAPCS64 document; the implementation opts for pass by reference.  */
+
+/* { dg-do compile { target aarch64*-*-* } } */
+
+typedef char A __attribute__ ((vector_size (64)));
+
+void
+foo (A a)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_3.c
new file mode 100644
index 000000000..fb6816f42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_3.c
@@ -0,0 +1,16 @@
+/* Test AAPCS layout
+
+/* { dg-do compile { target aarch64*-*-* } } */
+
+#define vector __attribute__((vector_size(16)))
+
+void
+foo(int a, ...);
+
+int
+main(void)
+{
+  foo (1, (vector unsigned int){10,11,12,13},
+       2, (vector unsigned int){20,21,22,23});
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_4.c
new file mode 100644
index 000000000..44af079af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_4.c
@@ -0,0 +1,9 @@
+/* Test AAPCS layout
+
+/* { dg-do compile { target aarch64*-*-* } } */
+
+__complex__ long int
+ctest_long_int(__complex__ long int x)
+{
+    return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_5.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_5.c
new file mode 100644
index 000000000..da24ba8c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/ice_5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target aarch64*-*-* } } */
+
+struct S
+{
+  union
+    {
+      long double b;
+    } a;
+};
+
+struct S s;
+
+extern struct S a[5];
+extern struct S check (struct S, struct S *, struct S);
+extern void checkx (struct S);
+
+void test (void)
+{
+  checkx (check (s, &a[1], a[2]));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h
new file mode 100644
index 000000000..72a470676
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/macro-def.h
@@ -0,0 +1,286 @@
+/* This header file defines a set of macros to be used in the construction
+   of parameter passing and/or va_arg code gen tests during the
+   pre-processing stage.  It is included inside abitest.h.
+
+   The following macros are defined here:
+
+     LAST_ARG
+     ARG
+     DOTS
+     ANON
+     LAST_ANON
+     PTR
+     PTR_ANON
+     LAST_ANONPTR
+
+  These macros are given different definitions depending on which one of
+  the following macros is defined.
+
+    AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+    AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+    AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+    AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+    AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+    AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+    AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+
+  Do not define more than one of the above macros.  */
+
+
+/* AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+   Define macros to check the incoming arguments.  */
+
+#ifdef AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate memcmp to check if the incoming args have the expected values.  */
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...)		\
+{									\
+  type __x = val;							\
+  DUMP_ARG(type,val);							\
+  if (validate_memory (&__x, stack + offset, sizeof (type), layout) != 0) \
+    abort();								\
+}
+#define LAST_ARG(type,val,offset,...) LAST_ARG_NONFLAT (type, val, offset, \
+							flat,__VA_ARGS__)
+#define ARG_NONFLAT(type,val,offset,layout,...) LAST_ARG_NONFLAT (type, val, \
+								  offset, \
+								  layout, \
+								  __VA_ARGS__)
+#define ARG(type,val,offset,...) LAST_ARG_NONFLAT(type, val, offset, \
+						  flat, __VA_ARGS__)
+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...)	\
+  ANON(type_promoted, val_promoted, offset, __VA_ARGS__)
+/* Composite larger than 16 bytes is replaced by a pointer to a copy prepared
+   by the caller, so here we extrat the pointer, deref it and compare the
+   content with that of the original one.  */
+#define PTR(type, val, offset, ...) {					\
+  type * ptr;								\
+  DUMP_ARG(type,val);							\
+  ptr = *(type **)(stack + offset);					\
+  if (memcmp (ptr, &val, sizeof (type)) != 0) abort ();			\
+}
+#define PTR_ANON(type, val, offset, ...) PTR(type, val, offset, __VA_ARGS__)
+#define LAST_ANONPTR(type, val, offset, ...) PTR(type, val, offset, __VA_ARGS__)
+#define DOTS
+
+#endif /* AARCH64_MACRO_DEF_CHECK_INCOMING_ARGS */
+
+
+/* AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+   Define macros to generate parameter type list.  */
+
+#ifdef AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+
+/* Generate parameter type list (without identifiers).  */
+#define LAST_ARG(type,val,offset) type
+#define LAST_ARG_NONFLAT(type, val, offset, layout) type
+#define ARG(type,val,offset) LAST_ARG(type, val, offset),
+#define ARG_NONFLAT(type, val, offset, layout) LAST_ARG (type, val, offset),
+#define DOTS ...
+#define ANON(type,val, offset)
+#define LAST_ANON(type,val, offset)
+#define PTR(type, val, offset) LAST_ARG(type, val, offset),
+#define PTR_ANON(type, val, offset)
+#define LAST_ANONPTR(type, val, offset)
+
+#endif /* AARCH64_MACRO_DEF_GEN_PARAM_TYPE_LIST */
+
+
+/* AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+   Define macros to generate argument list.  */
+
+#ifdef AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate the argument list; use VAL as the argument name.  */
+#define LAST_ARG(type,val,offset,...) val
+#define LAST_ARG_NONFLAT(type,val,offset,layout,...) val
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define ARG_NONFLAT(type, val, offset, layout,...) LAST_ARG (type, val, \
+							     offset, \
+							     __VA_ARGS__),
+#define DOTS
+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR_ANON(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...)	\
+  LAST_ARG(type, val, offset, __VA_ARGS__),
+
+#endif /* AARCH64_MACRO_DEF_GEN_ARGUMENT_LIST */
+
+
+/* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+   Define variadic macros to generate parameter type list.  */
+
+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate parameter type list (without identifiers).  */
+#define LAST_ARG(type,val,offset,...) type
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) type
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define ARG_NONFLAT(type, val, offset, layout, ...) LAST_ARG (type, val, \
+							      offset, \
+							      __VA_ARGS__),
+#define DOTS
+#define ANON(type,val, offset,...) ARG(type,val,offset, __VA_ARGS__)
+#define LAST_ANON(type,val, offset,...) LAST_ARG(type,val, offset, __VA_ARGS__)
+#define PTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR_ANON(type, val, offset,...) PTR(type, val, offset, __VA_ARGS__)
+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...)	\
+  LAST_ARG(type_promoted, val_promoted, offset, __VA_ARGS__),
+
+#endif /*  AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST  */
+
+
+/* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+   Define variadic macros to generate parameter type list with
+   identifiers.  */
+
+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate parameter type list (with identifiers).
+   The identifiers are named with prefix _f and suffix of the value of
+   __VA_ARGS__.  */
+#define LAST_ARG(type,val,offset,...) type _f##__VA_ARGS__
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) type _f##__VA_ARGS__
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define ARG_NONFLAT(type, val, offset, layout, ...) LAST_ARG (type, val, \
+							      offset, \
+							      __VA_ARGS__),
+#define DOTS ...
+#define ANON(type,val, offset,...)
+#define LAST_ANON(type,val, offset,...)
+#define PTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR_ANON(type, val, offset,...)
+#define LAST_ANONPTR(type, val, offset,...)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...)
+
+#endif /* AARCH64_VARIADIC_MACRO_DEF_GEN_PARAM_TYPE_LIST_WITH_IDENT */
+
+
+/* AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+   Define variadic macros to generate assignment from the function
+   incoming arguments to local variables.  */
+
+#ifdef AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate assignment statements.  For named args, direct assignment from
+   the formal parameter is generated; for unnamed args, va_arg is used.
+   The names of the local variables start with _x and end with the value of
+   __VA_ARGS__.  */
+#define LAST_ARG(type,val,offset,...) type _x##__VA_ARGS__ = _f##__VA_ARGS__;
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) \
+  type _x##__VA_ARGS__ = _f##__VA_ARGS__;
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ARG_NONFLAT(type,val,offset,layout,...) \
+  LAST_ARG (type, val, offset, __VA_ARGS__)
+#define ANON(type,val,offset,...) type _x##__VA_ARGS__ = va_arg (ap, type);
+#define LAST_ANON(type,val,offset,...) ANON(type, val, offset, __VA_ARGS__)
+#define PTR(type, val,offset,...)  ARG(type, val, offset, __VA_ARGS__)
+#define PTR_ANON(type, val, offset,...) ANON(type, val,offset, __VA_ARGS__)
+#define LAST_ANONPTR(type, val, offset,...) ANON(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...)	\
+  ANON(type_promoted, val_promoted, offset, __VA_ARGS__)
+
+#define DOTS
+
+#endif /* AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS */
+
+
+/* AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+   Define variadic macros to generate argument list using the variables
+   generated during AARCH64_VARIADIC_MACRO_DEF_ASSIGN_LOCAL_VARS_WITH_ARGS.  */
+
+#ifdef AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#undef PTR
+#undef PTR_ANON
+#undef LAST_ANONPTR
+#undef ANON_PROMOTED
+
+/* Generate the argument list; the names start with _x and end with the value of
+   __VA_ARGS__.  All arguments (named or unnamed) in stdarg_func are passed to
+   myfunc as named arguments.  */
+#define LAST_ARG(type,val,offset,...) _x##__VA_ARGS__
+#define LAST_ARG_NONFLAT(type, val, offset, layout, ...) _x##__VA_ARGS__
+#define ARG(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define ARG_NONFLAT(type, val, offset, layout, ...) \
+  LAST_ARG_NONFLAT (type, val, offset, layout, __VA_ARGS__),
+#define DOTS
+#define LAST_ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON(type,val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define PTR_ANON(type, val,offset,...) LAST_ARG(type, val, offset, __VA_ARGS__),
+#define LAST_ANONPTR(type, val, offset,...) LAST_ARG(type, val, offset, __VA_ARGS__)
+#define ANON_PROMOTED(type,val,type_promoted, val_promoted, offset,...)	\
+  ANON(type_promoted, val_promoted, offset, __VA_ARGS__)
+
+#endif /* AARCH64_VARIADIC_MACRO_DEF_GEN_ARGUMENT_LIST */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c
new file mode 100644
index 000000000..545b05685
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_1.c
@@ -0,0 +1,31 @@
+/* Test AAPCS64 layout */
+
+/* C.7  If the argument is an Integral Type, the size of the argument is
+	less than or equal to 8 bytes and the NGRN is less than 8, the
+	argument is copied to the least significant bits in x[NGRN].  The
+	NGRN is incremented by one.  The argument has now been allocated.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_1.c"
+/* TODO: review if we need this */
+#define RUNTIME_ENDIANNESS_CHECK
+#include "abitest.h"
+#else
+  ARG(int, 4, W0)
+  ARG(double, 4.0, D0)
+  ARG(int, 3, W1)
+  /* TODO: review the way of memcpy char, short, etc.  */
+#ifndef __AAPCS64_BIG_ENDIAN__
+  ARG(char, 0xEF, X2)
+  ARG(short, 0xBEEF, X3)
+  ARG(int, 0xDEADBEEF, X4)
+#else
+  /* TODO: need the model/qemu to be big-endian as well  */
+  ARG(char, 0xEF, X2+7)
+  ARG(short, 0xBEEF, X3+6)
+  ARG(int, 0xDEADBEEF, X4+4)
+#endif
+  LAST_ARG(long long, 0xDEADBEEFCAFEBABELL, X5)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_10.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_10.c
new file mode 100644
index 000000000..c2f48154a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_10.c
@@ -0,0 +1,26 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_10.c"
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+
+  ARG(int, 7, W0)
+  DOTS
+  ANON(struct z, a, D0)
+  ANON(struct z, b, D4)
+  ANON(double, 0.5, STACK)
+  LAST_ANON(double, 1.5, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_11.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_11.c
new file mode 100644
index 000000000..34cbe0303
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_11.c
@@ -0,0 +1,34 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_11.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(double, 11.0, D0)
+  DOTS
+  ANON(struct z, a, D1)
+  ANON(struct z, b, STACK)
+  LAST_ANON(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_12.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_12.c
new file mode 100644
index 000000000..d07bef8b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_12.c
@@ -0,0 +1,44 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_12.c"
+
+
+struct y
+{
+  long p;
+  long q;
+  long r;
+  long s;
+} v = { 1, 2, 3, 4 };
+
+struct y1
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v1 = { 1, 2, 3, 4 };
+
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#define MYFUNCTYPE struct y
+
+#include "abitest.h"
+#else
+  ARG(int, 7, W0)
+  ARG(struct y1, v1, X1)
+  ARG(struct z, a, D0)
+  ARG(struct z, b, D4)
+  LAST_ARG(double, 0.5, STACK)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_13.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_13.c
new file mode 100644
index 000000000..c73e6f2f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_13.c
@@ -0,0 +1,34 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+
+#define TESTFILE "test_13.c"
+
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 7, W0)
+  ARG(struct y, v, X1)
+  ARG(struct z, a, D0)
+  ARG(double, 1.0, D4)
+  ARG(struct z, b, STACK)
+  LAST_ARG(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_14.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_14.c
new file mode 100644
index 000000000..3c22b8a04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_14.c
@@ -0,0 +1,35 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_14.c"
+
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 7, W0)
+  ARG(int, 9, W1)
+  ARG(struct z, a, D0)
+  ARG(double, 1.0, D4)
+  ARG(struct z, b, STACK)
+  ARG(int, 4, W2)
+  LAST_ARG(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_15.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_15.c
new file mode 100644
index 000000000..1a869ad77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_15.c
@@ -0,0 +1,21 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_15.c"
+
+#include "abitest.h"
+#else
+  ARG(double, 1.0, D0)
+  ARG(double, 2.0, D1)
+  ARG(double, 3.0, D2)
+  ARG(double, 4.0, D3)
+  ARG(double, 5.0, D4)
+  ARG(double, 6.0, D5)
+  ARG(double, 7.0, D6)
+  ARG(double, 8.0, D7)
+  ARG(double, 9.0, STACK)
+  LAST_ARG(double, 10.0, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_16.c
new file mode 100644
index 000000000..1aa9725fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_16.c
@@ -0,0 +1,32 @@
+/* Test AAPCS layout */
+/* C.5 If the argument is a Half- or Single- precision Floating-point type,
+   then the size of the argument is set to 8 bytes.  The effect is as if
+   the argument had been copied to the least significant bits of a 64-bit
+   register and the remaining bits filled with unspecified values.  */
+/* TODO: add the check of half-precision floating-point when it is supported
+   by the A64 GCC.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_16.c"
+
+#include "abitest.h"
+#else
+  ARG(float, 1.0, S0)
+  ARG(float, 2.0, S1)
+  ARG(float, 3.0, S2)
+  ARG(float, 4.0, S3)
+  ARG(float, 5.0, S4)
+  ARG(float, 6.0, S5)
+  ARG(float, 7.0, S6)
+  ARG(float, 8.0, S7)
+#ifndef __AAPCS64_BIG_ENDIAN__
+  ARG(float, 9.0, STACK)
+  LAST_ARG(float, 10.0, STACK+8)
+#else
+  ARG(float, 9.0, STACK+4)
+  LAST_ARG(float, 10.0, STACK+12)
+#endif
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c
new file mode 100644
index 000000000..348ea2847
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_17.c
@@ -0,0 +1,37 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_17.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+float f1 = 25.0;
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(double, 11.0, D0)
+  DOTS
+  ANON(struct z, a, D1)
+  ANON(struct z, b, STACK)
+  ANON(int , 5, W0)
+  ANON(double, f1, STACK+32)
+  LAST_ANON(double, 0.5, STACK+40)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
new file mode 100644
index 000000000..2ebecee63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
@@ -0,0 +1,34 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+
+#define TESTFILE "test_18.c"
+
+
+struct y
+{
+  long long p;
+  long long q;
+  long long r;
+  long long s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 7, W0)
+  PTR(struct y, v, X1)
+  ARG(struct z, a, D0)
+  ARG(double, 1.0, D4)
+  ARG(struct z, b, STACK)
+  LAST_ARG(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c
new file mode 100644
index 000000000..1a3f873b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_19.c
@@ -0,0 +1,35 @@
+/* Test AAPCS64 layout.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_19.c"
+
+struct y
+{
+  int p1;
+  int p2;
+  float q;
+  int r1;
+  int r2;
+  char x;
+} v = { -1, 1, 2.0f, 3, 18, 19, 20};
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 7, W0)
+  DOTS
+  ANON(double, 4.0, D0)
+  ANON(struct z, a, D1)
+  ANON(struct z, b, STACK)
+  PTR_ANON(struct y, v, X1)
+  LAST_ANON(int, 10, W2)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c
new file mode 100644
index 000000000..94817ede3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_2.c
@@ -0,0 +1,16 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_2.c"
+#include "abitest.h"
+
+#else
+  ARG(float, 1.0f, S0)
+  ARG(double, 4.0, D1)
+  ARG(float, 2.0f, S2)
+  ARG(double, 5.0, D3)
+  LAST_ARG(int, 3, W0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c
new file mode 100644
index 000000000..e4cc1a1b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_20.c
@@ -0,0 +1,22 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_20.c"
+
+#include "abitest.h"
+
+#else
+  ARG(int, 8, W0)
+  ARG(double, 1.0, D0)
+  ARG(double, 2.0, D1)
+  ARG(double, 3.0, D2)
+  ARG(double, 4.0, D3)
+  ARG(double, 5.0, D4)
+  ARG(double, 6.0, D5)
+  ARG(double, 7.0, D6)
+  DOTS
+  ANON(_Complex double, 1234.0 + 567.0i, STACK)
+  LAST_ANON(double, -987.0, STACK+16)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c
new file mode 100644
index 000000000..b3a75e025
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_21.c
@@ -0,0 +1,21 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_21.c"
+
+#include "abitest.h"
+
+#else
+  ARG(int, 8, W0)
+  ARG(double, 1.0, D0)
+  ARG(double, 2.0, D1)
+  ARG(double, 3.0, D2)
+  ARG(double, 4.0, D3)
+  ARG(double, 5.0, D4)
+  ARG(double, 6.0, D5)
+  ARG(double, 7.0, D6)
+  ARG(_Complex double, 1234.0 + 567.0i, STACK)
+  LAST_ARG(double, -987.0, STACK+16)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c
new file mode 100644
index 000000000..cb8a8abc0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_22.c
@@ -0,0 +1,19 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_22.c"
+
+struct y
+{
+  float p;
+  float q;
+} v = { 345.0f, 678.0f };
+
+#include "abitest.h"
+#else
+  ARG(float, 123.0f, S0)
+  ARG(struct y, v, S1)
+  LAST_ARG(float, 901.0f, S3)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c
new file mode 100644
index 000000000..6993884c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_23.c
@@ -0,0 +1,42 @@
+/* Test AAPCS64 layout.
+
+   Larger than machine-supported vector size.  The behaviour is unspecified by
+   the AAPCS64 document; the implementation opts for pass by reference.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_23.c"
+
+typedef char A __attribute__ ((vector_size (64)));
+
+struct y
+{
+  double df[8];
+};
+
+union u
+{
+  struct y x;
+  A a;
+} u;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  u.x.df[0] = 1.0;
+  u.x.df[1] = 2.0;
+  u.x.df[2] = 3.0;
+  u.x.df[3] = 4.0;
+  u.x.df[4] = 5.0;
+  u.x.df[5] = 6.0;
+  u.x.df[6] = 7.0;
+  u.x.df[7] = 8.0;
+}
+
+#include "abitest.h"
+#else
+ARG (float, 123.0f, S0)
+PTR (A, u.a, X0)
+LAST_ARG_NONFLAT (int, 0xdeadbeef, X1, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c
new file mode 100644
index 000000000..8655f6f3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_24.c
@@ -0,0 +1,22 @@
+/* Test AAPCS64 layout.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_24.c"
+
+typedef long double TFtype;
+
+#include "abitest.h"
+#else
+  ARG(TFtype, 1.0, Q0)
+  ARG(TFtype, 2.0, Q1)
+  ARG(TFtype, 3.0, Q2)
+  ARG(TFtype, 4.0, Q3)
+  ARG(TFtype, 5.0, Q4)
+  ARG(TFtype, 6.0, Q5)
+  ARG(TFtype, 7.0, Q6)
+  ARG(TFtype, 8.0, Q7)
+  ARG(double, 9.0, STACK)
+  LAST_ARG(TFtype, 10.0, STACK+16)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c
new file mode 100644
index 000000000..2f942ff4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_25.c
@@ -0,0 +1,61 @@
+/* Test AAPCS64 layout
+
+   Test homogeneous floating-point aggregates and homogeneous short-vector
+   aggregates, which should be passed in SIMD/FP registers or via the
+   stack.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_25.c"
+
+typedef float vf2_t __attribute__((vector_size (8)));
+struct x0
+{
+  vf2_t v;
+} s0;
+struct x3
+{
+  vf2_t v[2];
+} s3;
+struct x4
+{
+  vf2_t v[3];
+} s4;
+
+typedef float vf4_t __attribute__((vector_size(16)));
+struct x1
+{
+  vf4_t v;
+} s1;
+
+struct x2
+{
+  double df[3];
+} s2;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  s0.v = (vf2_t){ 17.f, 18.f };
+  s1.v = (vf4_t){ 567.890f, 678.901f, 789.012f, 890.123f };
+  s2.df[0] = 123.456;
+  s2.df[1] = 234.567;
+  s2.df[2] = 345.678;
+  s3.v[0] = (vf2_t){ 19.f, 20.f, 21.f, 22.f };
+  s3.v[1] = (vf2_t){ 23.f, 24.f, 25.f, 26.f };
+  s4.v[0] = (vf2_t){ 27.f, 28.f, 29.f, 30.f };
+  s4.v[1] = (vf2_t){ 31.f, 32.f, 33.f, 34.f };
+  s4.v[2] = (vf2_t){ 35.f, 36.f, 37.f, 38.f };
+}
+
+#include "abitest.h"
+#else
+ARG_NONFLAT (struct x0, s0, Q0, f32in64)
+ARG (struct x2, s2, D1)
+ARG (struct x1, s1, Q4)
+ARG (struct x3, s3, D5)
+ARG (struct x4, s4, STACK)
+ARG_NONFLAT (int, 0xdeadbeef, X0, i32in64)
+LAST_ARG (double, 456.789, STACK+24)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c
new file mode 100644
index 000000000..9b9a3a480
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_26.c
@@ -0,0 +1,54 @@
+/* Test AAPCS64 layout.
+
+   Test some small structures that should be passed in GPRs.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_26.c"
+
+struct y0
+{
+  char ch;
+} c0 = { 'A' };
+
+struct y2
+{
+  long long ll[2];
+} c2 = { 0xDEADBEEF, 0xCAFEBABE };
+
+struct y3
+{
+  int i[3];
+} c3 = { 56789, 67890, 78901 };
+
+typedef float vf2_t __attribute__((vector_size (8)));
+struct x0
+{
+  vf2_t v;
+} s0;
+
+typedef short vh4_t __attribute__((vector_size (8)));
+
+struct x1
+{
+  vh4_t v[2];
+} s1;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  s0.v = (vf2_t){ 17.f, 18.f };
+  s1.v[0] = (vh4_t){ 345, 456, 567, 678 };
+  s1.v[1] = (vh4_t){ 789, 890, 901, 123 };
+}
+
+#include "abitest.h"
+#else
+ARG (struct y0, c0, X0)
+ARG (struct y2, c2, X1)
+ARG (struct y3, c3, X3)
+ARG_NONFLAT (struct x0, s0, D0, f32in64)
+ARG (struct x1, s1, D1)
+LAST_ARG_NONFLAT (int, 89012, X5, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c
new file mode 100644
index 000000000..f05b8e659
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_3.c
@@ -0,0 +1,18 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_3.c"
+
+__complex__ x = 1.0+2.0i;
+
+#include "abitest.h"
+#else
+ARG (float, 1.0f, S0)
+ARG (__complex__ double, x, D1)
+ARG (float, 2.0f, S3)
+ARG (double, 5.0, D4)
+LAST_ARG_NONFLAT (int, 3, X0, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c
new file mode 100644
index 000000000..a37db569b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_4.c
@@ -0,0 +1,20 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_4.c"
+
+__complex__ float x = 1.0f + 2.0fi;
+#include "abitest.h"
+#else
+ARG (float, 1.0f, S0)
+ARG (__complex__ float, x, S1)
+ARG (float, 2.0f, S3)
+ARG (double, 5.0, D4)
+LAST_ARG_NONFLAT (int, 3, X0, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c
new file mode 100644
index 000000000..674efd8c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_5.c
@@ -0,0 +1,24 @@
+/* Test AAPCS64 layout */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_5.c"
+
+__complex__ float x = 1.0+2.0i;
+
+struct y
+{
+  long p;
+  long q;
+} v = { 1, 2};
+
+#include "abitest.h"
+#else
+  ARG(float, 1.0f, S0)
+  ARG(__complex__ float, x, S1)
+  ARG(float, 2.0f, S3)
+  ARG(double, 5.0, D4)
+  LAST_ARG(struct y, v, X0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c
new file mode 100644
index 000000000..95d44e923
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_6.c
@@ -0,0 +1,26 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_6.c"
+
+__complex__ double x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+#include "abitest.h"
+#else
+  ARG(struct y, v, X0)
+  ARG(float, 1.0f, S0)
+  ARG(__complex__ double, x, D1)
+  ARG(float, 2.0f, S3)
+  ARG(double, 5.0, D4)
+  LAST_ARG(int, 3, W2)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c
new file mode 100644
index 000000000..4fb1feeaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_7.c
@@ -0,0 +1,30 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_7.c"
+
+__complex__ float x = 1.0f + 2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 }, v1 = {5, 6, 7, 8}, v2 = {9, 10, 11, 12};
+
+#include "abitest.h"
+#else
+ARG (struct y, v, X0)
+ARG (struct y, v1, X2)
+ARG (struct y, v2, X4)
+ARG (int, 4, W6)
+ARG (float, 1.0f, S0)
+ARG (__complex__ float, x, S1)
+ARG (float, 2.0f, S3)
+ARG (double, 5.0, D4)
+ARG (int, 3, W7)
+LAST_ARG_NONFLAT (int, 5, STACK, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c
new file mode 100644
index 000000000..3d67ff508
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_8.c
@@ -0,0 +1,24 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_8.c"
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(struct z, a, D0)
+  ARG(struct z, b, D4)
+  ARG(double, 0.5, STACK)
+  ARG(int, 7, W0)
+  LAST_ARG(int, 8, W1) 
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c
new file mode 100644
index 000000000..fbe42456c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_9.c
@@ -0,0 +1,32 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "test_9.c"
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 7, W0)
+  ARG(struct y, v, X1)
+  ARG(struct z, a, D0)
+  ARG(struct z, b, D4)
+  LAST_ARG(double, 0.5, STACK)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c
new file mode 100644
index 000000000..f22fca6de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-1.c
@@ -0,0 +1,126 @@
+/* Test AAPCS64 layout.
+
+   Test the comformance to the alignment and padding requirements.
+
+   B.4  If the argument type is a Composite Type then the size of the
+        argument is rounded up to the nearest multiple of 8 bytes.
+   C.4  If the argument is an HFA, a Quad-precision Floating-point or Short
+	Vector Type then the NSAA is rounded up to the larger of 8 or the
+	Natural Alignment of the argument's type.
+   C.12 The NSAA is rounded up to the larger of 8 or the Natural Alignment
+	of the argument's type.
+   C.14 If the size of the argument is less than 8 bytes then the size of
+	the argument is set ot 8 bytes.  The effect is as if the argument
+	was copied to the least significant bits of a 64-bit register and
+	the remaining bits filled with unspecified values.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_align-1.c"
+#include "type-def.h"
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+};
+
+struct y v1 = { 1, 2, 3, 4 };
+struct y v2 = { 5, 6, 7, 8 };
+struct y v3 = { 9, 10, 11, 12 };
+struct y v4 = { 13, 14, 15, 16 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+vf4_t c = { 13.f, 14.f, 15.f, 16.f };
+
+struct x
+{
+  vf4_t v;
+} w;
+
+char ch='a';
+short sh=13;
+int i=14;
+long long ll=15;
+
+struct s1
+{
+  short sh[3];
+} s1;
+
+struct s2
+{
+  int i[2];
+  char c;
+} s2;
+
+struct ldx2_t
+{
+  long double ld[2];
+} ldx2 = { 12345.67890L, 23456.78901L };
+
+union u_t
+{
+  long double ld;
+  double d[2];
+} u;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  w.v = (vf4_t){ 17.f, 18.f, 19.f, 20.f };
+  s1.sh[0] = 16;
+  s1.sh[1] = 17;
+  s1.sh[2] = 18;
+  s2.i[0] = 19;
+  s2.i[1] = 20;
+  s2.c = 21;
+  u.ld = 34567.89012L;
+}
+
+#include "abitest.h"
+#else
+
+  ARG(struct y, v1, X0)
+  ARG(struct y, v2, X2)
+  ARG(struct y, v3, X4)
+  ARG(struct y, v4, X6)
+  ARG(struct z, a, D0)
+  ARG(struct z, b, D4)
+  ARG(double, 12.5, STACK)
+  ARG(vf4_t, c, STACK+16)       /* [C.4] 16-byte aligned short vector */
+  ARG(double, 17.0, STACK+32)
+  ARG(struct x, w, STACK+48)    /* [C.12] 16-byte aligned small struct */
+#ifndef __AAPCS64_BIG_ENDIAN__
+  ARG(char, ch, STACK+64)       /* [C.14] char  padded to the size of 8 bytes */
+  ARG(short, sh, STACK+72)      /* [C.14] short padded to the size of 8 bytes */
+  ARG(int, i, STACK+80)         /* [C.14] int   padded to the size of 8 bytes */
+#else
+  ARG(char, ch, STACK+71)
+  ARG(short, sh, STACK+78)
+  ARG(int, i, STACK+84)
+#endif
+  ARG(long long, ll, STACK+88)
+  ARG(struct s1, s1, STACK+96)  /* [B.4] small struct padded to the size of 8 bytes */
+  ARG(double, 18.0, STACK+104)
+  ARG(struct s2, s2, STACK+112) /* [B.4] small struct padded to the size of 16 bytes */
+  ARG(double, 19.0, STACK+128)
+  ARG(long double, 30.0L, STACK+144)  /* [C.4] 16-byte aligned quad-precision */
+  ARG(double, 31.0, STACK+160)
+  ARG(struct ldx2_t, ldx2, STACK+176) /* [C.4] 16-byte aligned HFA */
+  ARG(double, 32.0, STACK+208)
+  ARG(__int128, 33, STACK+224)  /* [C.12] 16-byte aligned 128-bit integer */
+  ARG(double, 34.0, STACK+240)
+  ARG(union u_t, u, STACK+256)  /* [C.12] 16-byte aligned small composite (union in this case) */
+  LAST_ARG_NONFLAT (int, 35.0, STACK+272, i32in64)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c
new file mode 100644
index 000000000..6c61948b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-2.c
@@ -0,0 +1,42 @@
+/* Test AAPCS64 layout.
+
+   C.8  If the argument has an alignment of 16 then the NGRN is rounded up
+	the next even number.
+
+   The case of a small struture containing only one 16-byte aligned
+   quad-word integer is covered in this test.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_align-2.c"
+#include "type-def.h"
+
+struct y
+{
+  union int128_t v;
+} w;
+
+struct x
+{
+  long long p;
+  int q;
+} s = {0xDEADBEEFCAFEBABELL, 0xFEEBDAED};
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  /* Init signed quad-word integer.  */
+  w.v.l64 = 0xfdb9753102468aceLL;
+  w.v.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+  ARG(int, 0xAB, W0)
+  ARG(struct y, w, X2)
+  ARG(int, 0xCD, W4)
+  ARG(struct x, s, X5)
+  LAST_ARG(int, 0xFF00FF00, W7)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c
new file mode 100644
index 000000000..bf8bc7468
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-3.c
@@ -0,0 +1,46 @@
+/* Test AAPCS64 layout.
+
+   C.8  If the argument has an alignment of 16 then the NGRN is rounded up
+	the next even number.
+   C.9  If the argument is an Integral Type, the size of the argument is
+	equal to 16 and the NGRN is less than 7, the argument is copied
+	to x[NGRN] and x[NGRN+1]. x[NGRN] shall contain the lower addressed
+	double-word of the memory representation of the argument.  The
+	NGRN is incremented by two.  The argument has now been allocated.
+
+   The case of passing a 128-bit integer in two general registers is covered
+   in this test.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_align-3.c"
+#include "type-def.h"
+
+union int128_t qword;
+
+int gInt[4];
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  /* Initialize the quadword integer via the union.  */
+  qword.l64 = 0xDEADBEEFCAFEBABELL;
+  qword.h64 = 0x123456789ABCDEF0LL;
+
+  gInt[0] = 12345;
+  gInt[1] = 23456;
+  gInt[2] = 34567;
+  gInt[3] = 45678;
+}
+
+
+#include "abitest.h"
+#else
+  ARG(int, gInt[0], W0)
+  ARG(int, gInt[1], W1)
+  ARG(int, gInt[2], W2)
+  ARG(__int128, qword.i, X4)
+  LAST_ARG(int, gInt[3], W6)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c
new file mode 100644
index 000000000..7834ed87e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_align-4.c
@@ -0,0 +1,42 @@
+/* Test AAPCS64 layout.
+
+   C.3 If the argument is an HFA then the NSRN is set to 8 and the size
+   of the argument is rounded up to the nearest multiple of 8 bytes.
+
+   TODO: add the check of an HFA containing half-precision floating-point
+   when __f16 is supported in A64 GCC.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_align-4.c"
+
+struct z1
+{
+  double x[4];
+};
+
+struct z1 a = { 5.0, 6.0, 7.0, 8.0 };
+
+struct z2
+{
+  float x[3];
+};
+
+struct z2 b = { 13.f, 14.f, 15.f };
+struct z2 c = { 16.f, 17.f, 18.f };
+
+#include "abitest.h"
+#else
+
+  ARG(struct z1, a, D0)
+  ARG(double, 9.0, D4)
+  ARG(double, 10.0, D5)
+  ARG(struct z2, b, STACK)       /* [C.3] on stack and size padded to 16 bytes */
+#ifndef __AAPCS64_BIG_ENDIAN__
+  ARG(float, 15.5f, STACK+16)    /* [C.3] NSRN has been set to 8 */
+#else
+  ARG(float, 15.5f, STACK+20)
+#endif
+  LAST_ARG(struct z2, c, STACK+24)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c
new file mode 100644
index 000000000..6bf9721cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_complex.c
@@ -0,0 +1,18 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_complex.c"
+
+__complex__ float x = 1.0+2.0i;
+__complex__ int y = 5 + 6i;
+__complex__ double z = 2.0 + 3.0i;
+
+#include "abitest.h"
+#else
+  ARG(__complex__ float, x, S0)
+  ARG(__complex__ int, y, X0)
+  ARG(__complex__ double, z, D2)
+  LAST_ARG (int, 5, W1)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_int128.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_int128.c
new file mode 100644
index 000000000..9df344f29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_int128.c
@@ -0,0 +1,17 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_int128.c"
+
+typedef int TItype __attribute__ ((mode (TI)));
+
+TItype x = 0xcafecafecafecfeacfeacfea;
+TItype y = 0xcfeacfeacfeacafecafecafe;
+
+#include "abitest.h"
+#else
+  ARG (TItype, x, X0)
+  LAST_ARG (TItype, y, X2)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c
new file mode 100644
index 000000000..109cea0b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/test_quad_double.c
@@ -0,0 +1,26 @@
+/* Test AAPCS64 layout.
+
+   Test parameter passing of floating-point quad precision types.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define TESTFILE "test_quad_double.c"
+
+typedef long double TFtype;
+typedef _Complex long double CTFtype;
+
+TFtype x = 1.0;
+TFtype y = 2.0;
+
+CTFtype cx = 3.0 + 4.0i;
+CTFtype cy = 5.0 + 6.0i;
+
+#include "abitest.h"
+#else
+  ARG       ( TFtype,  x, Q0)
+  ARG       (CTFtype, cx, Q1)
+  DOTS
+  ANON      (CTFtype, cy, Q3)
+  LAST_ANON ( TFtype,  y, Q5)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
new file mode 100644
index 000000000..a95d06aa2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h
@@ -0,0 +1,157 @@
+/* This header file defines some types that are used in the AAPCS64 tests.  */
+
+
+/* 64-bit vector of 2 floats.  */
+typedef float vf2_t __attribute__((vector_size (8)));
+
+/* 128-bit vector of 4 floats.  */
+typedef float vf4_t __attribute__((vector_size (16)));
+
+/* 128-bit vector of 4 ints.  */
+typedef int vi4_t __attribute__((vector_size (16)));
+
+/* signed quad-word (in an union for the convenience of initialization).  */
+union int128_t
+{
+  __int128 i;
+  struct
+    {
+      signed long long l64;
+      signed long long h64;
+    };
+};
+
+/* Homogeneous floating-point composite types.  */
+
+struct hfa_fx1_t
+{
+  float a;
+};
+
+struct hfa_fx2_t
+{
+  float a;
+  float b;
+};
+
+struct hfa_dx2_t
+{
+  double a;
+  double b;
+};
+
+struct hfa_dx4_t
+{
+  double a;
+  double b;
+  double c;
+  double d;
+};
+
+struct hfa_ldx3_t
+{
+  long double a;
+  long double b;
+  long double c;
+};
+
+struct hfa_ffs_t
+{
+  float a;
+  float b;
+  struct hfa_fx2_t c;
+};
+
+union hfa_union_t
+{
+  struct
+    {
+      float a;
+      float b;
+    } s;
+  float c;
+};
+
+/* Non homogeneous floating-point-composite types.  */
+
+struct non_hfa_fx5_t
+{
+  float a;
+  float b;
+  float c;
+  float d;
+  float e;
+};
+
+struct non_hfa_ffs_t
+{
+  float a;
+  float b;
+  struct hfa_dx2_t c;
+};
+
+struct non_hfa_ffs_2_t
+{
+  struct
+    {
+      int a;
+      int b;
+    } s;
+  float c;
+  float d;
+};
+
+struct hva_vf2x1_t
+{
+  vf2_t a;
+};
+
+struct hva_vf2x2_t
+{
+  vf2_t a;
+  vf2_t b;
+};
+
+struct hva_vi4x1_t
+{
+  vi4_t a;
+};
+
+struct non_hfa_ffd_t
+{
+  float a;
+  float b;
+  double c;
+};
+
+struct non_hfa_ii_t
+{
+  int a;
+  int b;
+};
+
+struct non_hfa_c_t
+{
+  char a;
+};
+
+struct non_hfa_ffvf2_t
+{
+  float a;
+  float b;
+  vf2_t c;
+};
+
+struct non_hfa_fffd_t
+{
+  float a;
+  float b;
+  float c;
+  double d;
+};
+
+union non_hfa_union_t
+{
+  double a;
+  float b;
+};
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c
new file mode 100644
index 000000000..4eb569e8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-1.c
@@ -0,0 +1,50 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   This test covers fundamental data types as specified in AAPCS64 \S 4.1.
+   It is focus on unnamed parameter passed in registers.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-1.c"
+#include "type-def.h"
+
+vf2_t vf2 = (vf2_t){ 17.f, 18.f };
+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead };
+union int128_t qword;
+signed char sc = 0xed;
+signed int sc_promoted = 0xffffffed;
+signed short ss = 0xcba9;
+signed int ss_promoted = 0xffffcba9;
+float fp = 65432.12345f;
+double fp_promoted = (double)65432.12345f;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  /* Init signed quad-word integer.  */
+  qword.l64 = 0xfdb9753102468aceLL;
+  qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+  ARG          (         int      , 0xff  ,                            X0, LAST_NAMED_ARG_ID)
+  DOTS
+  ANON_PROMOTED(unsigned char     , 0xfe  , unsigned int, 0xfe       , X1,       1)
+  ANON_PROMOTED(  signed char     , sc    ,   signed int, sc_promoted, X2,       2)
+  ANON_PROMOTED(unsigned short    , 0xdcba, unsigned int, 0xdcba     , X3,       3)
+  ANON_PROMOTED(  signed short    , ss    ,   signed int, ss_promoted, X4,       4)
+  ANON         (unsigned int      , 0xdeadbeef,                        X5,       5)
+  ANON         (  signed int      , 0xcafebabe,                        X6,       6)
+  ANON         (unsigned long long, 0xba98765432101234ULL,             X7,       7)
+  ANON         (  signed long long, 0xa987654321012345LL ,             STACK,    8)
+  ANON         (          __int128, qword.i              ,             STACK+16, 9)
+  ANON_PROMOTED(         float    , fp    ,       double, fp_promoted, D0,      10)
+  ANON         (         double   , 9876543.212345,                    D1,      11)
+  ANON         (    long double   , 98765432123456789.987654321L,      Q2,      12)
+  ANON         (             vf2_t, vf2   ,                            D3,      13)
+  ANON         (             vi4_t, vi4   ,                            Q4,      14)
+  LAST_ANON    (         int      , 0xeeee,                            STACK+32,15)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-10.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-10.c
new file mode 100644
index 000000000..50b77005b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-10.c
@@ -0,0 +1,29 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   Miscellaneous test: Anonymous arguments passed on the stack.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-10.c"
+
+struct z
+{
+  double x[4];
+};
+
+double d1 = 25.0;
+double d2 = 103.0;
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(struct z, a, D0, 0)
+  ARG(struct z, b, D4, LAST_NAMED_ARG_ID)
+  DOTS
+  ANON(double, d1, STACK, 2)
+  LAST_ANON(double, d2, STACK+8, 3)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-11.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-11.c
new file mode 100644
index 000000000..c1f1f8f9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-11.c
@@ -0,0 +1,32 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   Miscellaneous test: Anonymous arguments passed on the stack.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-11.c"
+
+struct z
+{
+  double x[2];
+};
+
+double d1 = 25.0;
+struct z a = { 5.0, 6.0 };
+
+#include "abitest.h"
+#else
+  ARG(double, 1.0, D0, 0)
+  ARG(double, 2.0, D1, 1)
+  ARG(double, 3.0, D2, 2)
+  ARG(double, 4.0, D3, 3)
+  ARG(double, 5.0, D4, 4)
+  ARG(double, 6.0, D5, 5)
+  ARG(double, 7.0, D6, LAST_NAMED_ARG_ID)
+  DOTS
+  ANON(struct z, a, STACK, 8)
+  LAST_ANON(double, d1, STACK+16, 9)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-12.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-12.c
new file mode 100644
index 000000000..a12ccfd8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-12.c
@@ -0,0 +1,60 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   Pass by reference.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-12.c"
+
+struct z
+{
+  char c;
+  short s;
+  int ia[4];
+};
+
+struct z a, b, c;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  a.c = 0x11;
+  a.s = 0x2222;
+  a.ia[0] = 0x33333333;
+  a.ia[1] = 0x44444444;
+  a.ia[2] = 0x55555555;
+  a.ia[3] = 0x66666666;
+
+  b.c = 0x77;
+  b.s = 0x8888;
+  b.ia[0] = 0x99999999;
+  b.ia[1] = 0xaaaaaaaa;
+  b.ia[2] = 0xbbbbbbbb;
+  b.ia[3] = 0xcccccccc;
+
+  c.c = 0xdd;
+  c.s = 0xeeee;
+  c.ia[0] = 0xffffffff;
+  c.ia[1] = 0x12121212;
+  c.ia[2] = 0x23232323;
+  c.ia[3] = 0x34343434;
+}
+
+#include "abitest.h"
+#else
+  PTR(struct z, a, X0, 0)
+  ARG(int, 0xdeadbeef, X1, 1)
+  ARG(int, 0xcafebabe, X2, 2)
+  ARG(int, 0xdeadbabe, X3, 3)
+  ARG(int, 0xcafebeef, X4, 4)
+  ARG(int, 0xbeefdead, X5, 5)
+  ARG(int, 0xbabecafe, X6, LAST_NAMED_ARG_ID)
+  DOTS
+  PTR_ANON(struct z, b, X7, 7)
+  PTR_ANON(struct z, c, STACK, 8)
+  ANON(int, 0xbabedead, STACK+8, 9)
+  LAST_ANON(double, 123.45, D0, 10)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c
new file mode 100644
index 000000000..b6da677c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-2.c
@@ -0,0 +1,59 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   This test covers fundamental data types as specified in AAPCS64 \S 4.1.
+   It is focus on unnamed parameter passed on stack.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-2.c"
+#include "type-def.h"
+
+vf2_t vf2 = (vf2_t){ 17.f, 18.f };
+vi4_t vi4 = (vi4_t){ 0xdeadbabe, 0xbabecafe, 0xcafebeef, 0xbeefdead };
+union int128_t qword;
+signed char sc = 0xed;
+signed int sc_promoted = 0xffffffed;
+signed short ss = 0xcba9;
+signed int ss_promoted = 0xffffcba9;
+float fp = 65432.12345f;
+double fp_promoted = (double)65432.12345f;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  /* Init signed quad-word integer.  */
+  qword.l64 = 0xfdb9753102468aceLL;
+  qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+  ARG          (         int      , 0xff  ,                            X0,        0)
+  ARG          (         float    , 1.0f  ,                            S0,        1)
+  ARG          (         float    , 1.0f  ,                            S1,        2)
+  ARG          (         float    , 1.0f  ,                            S2,        3)
+  ARG          (         float    , 1.0f  ,                            S3,        4)
+  ARG          (         float    , 1.0f  ,                            S4,        5)
+  ARG          (         float    , 1.0f  ,                            S5,        6)
+  ARG          (         float    , 1.0f  ,                            S6,        7)
+  ARG          (         float    , 1.0f  ,                            S7, LAST_NAMED_ARG_ID)
+  DOTS
+  ANON         (          __int128, qword.i              ,             X2,        8)
+  ANON         (  signed long long, 0xa987654321012345LL ,             X4,        9)
+  ANON         (          __int128, qword.i              ,             X6,       10)
+  ANON_PROMOTED(unsigned char     , 0xfe  , unsigned int, 0xfe       , STACK,    11)
+  ANON_PROMOTED(  signed char     , sc    ,   signed int, sc_promoted, STACK+8,  12)
+  ANON_PROMOTED(unsigned short    , 0xdcba, unsigned int, 0xdcba     , STACK+16, 13)
+  ANON_PROMOTED(  signed short    , ss    ,   signed int, ss_promoted, STACK+24, 14)
+  ANON         (unsigned int      , 0xdeadbeef,                        STACK+32, 15)
+  ANON         (  signed int      , 0xcafebabe,                        STACK+40, 16)
+  ANON         (unsigned long long, 0xba98765432101234ULL,             STACK+48, 17)
+  ANON_PROMOTED(         float    , fp    ,       double, fp_promoted, STACK+56, 18)
+  ANON         (         double   , 9876543.212345,                    STACK+64, 19)
+  ANON         (    long double   , 98765432123456789.987654321L,      STACK+80, 20)
+  ANON         (             vf2_t, vf2   ,                            STACK+96, 21)
+  ANON         (             vi4_t, vi4   ,                            STACK+112,22)
+  LAST_ANON    (         int      , 0xeeee,                            STACK+128,23)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c
new file mode 100644
index 000000000..34978c7e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-3.c
@@ -0,0 +1,86 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   This test covers most composite types as described in AAPCS64 \S 4.3.
+   Homogeneous floating-point aggregate types are covered in other tests.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-3.c"
+#include "type-def.h"
+
+struct x0
+{
+  char ch;
+  int i;
+} y0 = { 'a', 12345 };
+
+struct x1
+{
+  int a;
+  int b;
+  int c;
+  int d;
+} y1 = { 0xdeadbeef, 0xcafebabe, 0x87654321, 0xabcedf975 };
+
+struct x2
+{
+  long long a;
+  long long b;
+  char ch;
+} y2 = { 0x12, 0x34, 0x56 };
+
+union x3
+{
+  char ch;
+  int i;
+  long long ll;
+} y3;
+
+union x4
+{
+  int i;
+  struct x2 y2;
+} y4;
+
+struct x5
+{
+  union int128_t qword;
+} y5;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  /* Init small union.  */
+  y3.ll = 0xfedcba98LL;
+
+  /* Init big union.  */
+  y4.y2.a = 0x78;
+  y4.y2.b = 0x89;
+  y4.y2.ch= 0x9a;
+
+  /* Init signed quad-word integer.  */
+  y5.qword.l64 = 0xfdb9753102468aceLL;
+  y5.qword.h64 = 0xeca8642013579bdfLL;
+}
+
+#include "abitest.h"
+#else
+  ARG      (float   ,1.0f, S0, LAST_NAMED_ARG_ID)
+  DOTS
+  ANON     (struct x0, y0, X0,        1)
+  ANON     (struct x1, y1, X1,        2)
+  PTR_ANON (struct x2, y2, X3,        3)
+  ANON     (union  x3, y3, X4,        4)
+  PTR_ANON (union  x4, y4, X5,        5)
+  ANON     (struct x5, y5, X6,        6)
+  ANON     (struct x0, y0, STACK,     7)
+  ANON     (struct x1, y1, STACK+8,   8)
+  PTR_ANON (struct x2, y2, STACK+24,  9)
+  ANON     (union  x3, y3, STACK+32, 10)
+  PTR_ANON (union  x4, y4, STACK+40, 11)
+  ANON     (int      ,  1, STACK+48, 12)
+  ANON     (struct x5, y5, STACK+64, 13)
+  LAST_ANON(int      ,  2, STACK+80, 14)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c
new file mode 100644
index 000000000..d0e18db54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-4.c
@@ -0,0 +1,93 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   This test covers homogeneous floating-point aggregate types and homogeneous
+   short-vector aggregate types as described in AAPCS64 \S 4.3.5.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-4.c"
+#include "type-def.h"
+
+struct hfa_fx1_t hfa_fx1 = {12.345f};
+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f};
+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678};
+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456};
+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012};
+struct non_hfa_fx5_t non_hfa_fx5 = {456.789f, 567.890f, 678.901f, 789.012f, 890.123f};
+struct hfa_ffs_t hfa_ffs;
+struct non_hfa_ffs_t non_hfa_ffs;
+struct non_hfa_ffs_2_t non_hfa_ffs_2;
+struct hva_vf2x1_t hva_vf2x1;
+struct hva_vf2x2_t hva_vf2x2;
+struct hva_vi4x1_t hva_vi4x1;
+struct non_hfa_ffd_t non_hfa_ffd = {23.f, 24.f, 25.0};
+struct non_hfa_ii_t non_hfa_ii = {26, 27};
+struct non_hfa_c_t non_hfa_c = {28};
+struct non_hfa_ffvf2_t non_hfa_ffvf2;
+struct non_hfa_fffd_t non_hfa_fffd = {33.f, 34.f, 35.f, 36.0};
+union hfa_union_t hfa_union;
+union non_hfa_union_t non_hfa_union;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  hva_vf2x1.a = (vf2_t){17.f, 18.f};
+  hva_vf2x2.a = (vf2_t){19.f, 20.f};
+  hva_vf2x2.b = (vf2_t){21.f, 22.f};
+  hva_vi4x1.a = (vi4_t){19, 20, 21, 22};
+
+  non_hfa_ffvf2.a = 29.f;
+  non_hfa_ffvf2.b = 30.f;
+  non_hfa_ffvf2.c = (vf2_t){31.f, 32.f};
+
+  hfa_union.s.a = 37.f;
+  hfa_union.s.b = 38.f;
+  hfa_union.c   = 39.f;
+
+  non_hfa_union.a = 40.0;
+  non_hfa_union.b = 41.f;
+
+  hfa_ffs.a = 42.f;
+  hfa_ffs.b = 43.f;
+  hfa_ffs.c.a = 44.f;
+  hfa_ffs.c.b = 45.f;
+
+  non_hfa_ffs.a = 46.f;
+  non_hfa_ffs.b = 47.f;
+  non_hfa_ffs.c.a = 48.0;
+  non_hfa_ffs.c.b = 49.0;
+
+  non_hfa_ffs_2.s.a = 50;
+  non_hfa_ffs_2.s.b = 51;
+  non_hfa_ffs_2.c = 52.f;
+  non_hfa_ffs_2.d = 53.f;
+}
+
+#include "abitest.h"
+#else
+  ARG      (int   , 1, X0, LAST_NAMED_ARG_ID)
+  DOTS
+  /* HFA or HVA passed in fp/simd registers or on stack.  */
+  ANON     (struct hfa_fx1_t  , hfa_fx1 ,  S0      , 0)
+  ANON     (struct hfa_fx2_t  , hfa_fx2 ,  S1      , 1)
+  ANON     (struct hfa_dx2_t  , hfa_dx2 ,  D3      , 2)
+  ANON     (struct hva_vf2x1_t, hva_vf2x1, D5      , 11)
+  ANON     (struct hva_vi4x1_t, hva_vi4x1, Q6      , 12)
+  ANON     (struct hfa_dx4_t  , hfa_dx4 ,  STACK   , 3)
+  ANON     (struct hfa_ffs_t  , hfa_ffs  , STACK+32, 4)
+  ANON     (union  hfa_union_t, hfa_union, STACK+48, 5)
+  ANON     (struct hfa_ldx3_t , hfa_ldx3 , STACK+64, 6)
+  /* Non-H[FV]A passed in general registers or on stack or via reference.  */
+  PTR_ANON (struct non_hfa_fx5_t  , non_hfa_fx5  , X1       , 10)
+  ANON     (struct non_hfa_ffd_t  , non_hfa_ffd  , X2       , 13)
+  ANON     (struct non_hfa_ii_t   , non_hfa_ii   , X4       , 14)
+  ANON     (struct non_hfa_c_t    , non_hfa_c    , X5       , 15)
+  ANON     (struct non_hfa_ffvf2_t, non_hfa_ffvf2, X6       , 16)
+  PTR_ANON (struct non_hfa_fffd_t , non_hfa_fffd , STACK+112, 17)
+  PTR_ANON (struct non_hfa_ffs_t  , non_hfa_ffs  , STACK+120, 18)
+  ANON     (struct non_hfa_ffs_2_t, non_hfa_ffs_2, STACK+128, 19)
+  ANON     (union  non_hfa_union_t, non_hfa_union, STACK+144, 20)
+  LAST_ANON(int                   , 2            , STACK+152, 30)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c
new file mode 100644
index 000000000..6b99a6f1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-5.c
@@ -0,0 +1,47 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   This test is focus on certain unnamed homogeneous floating-point aggregate
+   types passed in fp/simd registers.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-5.c"
+#include "type-def.h"
+
+struct hfa_fx1_t hfa_fx1 = {12.345f};
+struct hfa_fx2_t hfa_fx2 = {123.456f, 234.456f};
+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678};
+struct hfa_dx4_t hfa_dx4 = {1234.123, 2345.234, 3456.345, 4567.456};
+struct hfa_ldx3_t hfa_ldx3 = {123456.7890, 234567.8901, 345678.9012};
+struct hfa_ffs_t hfa_ffs;
+union hfa_union_t hfa_union;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  hfa_union.s.a = 37.f;
+  hfa_union.s.b = 38.f;
+  hfa_union.c   = 39.f;
+
+  hfa_ffs.a = 42.f;
+  hfa_ffs.b = 43.f;
+  hfa_ffs.c.a = 44.f;
+  hfa_ffs.c.b = 45.f;
+}
+
+#include "abitest.h"
+#else
+  ARG      (int, 1, X0, LAST_NAMED_ARG_ID)
+  DOTS
+  /* HFA passed in fp/simd registers or on stack.  */
+  ANON     (struct hfa_dx4_t  , hfa_dx4  , D0      , 0)
+  ANON     (struct hfa_ldx3_t , hfa_ldx3 , Q4      , 1)
+  ANON     (struct hfa_ffs_t  , hfa_ffs  , STACK   , 2)
+  ANON     (union  hfa_union_t, hfa_union, STACK+16, 3)
+  ANON     (struct hfa_fx1_t  , hfa_fx1  , STACK+24, 4)
+  ANON     (struct hfa_fx2_t  , hfa_fx2  , STACK+32, 5)
+  ANON     (struct hfa_dx2_t  , hfa_dx2  , STACK+40, 6)
+  LAST_ANON(double            , 1.0      , STACK+56, 7)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c
new file mode 100644
index 000000000..f94a54ab1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-6.c
@@ -0,0 +1,40 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   This test is focus on certain unnamed homogeneous floating-point aggregate
+   types passed in fp/simd registers.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-6.c"
+#include "type-def.h"
+
+struct hfa_fx1_t hfa_fx1 = {12.345f};
+struct hfa_dx2_t hfa_dx2 = {234.567, 345.678};
+struct hfa_ffs_t hfa_ffs;
+union hfa_union_t hfa_union;
+
+#define HAS_DATA_INIT_FUNC
+void init_data ()
+{
+  hfa_union.s.a = 37.f;
+  hfa_union.s.b = 38.f;
+  hfa_union.c   = 39.f;
+
+  hfa_ffs.a = 42.f;
+  hfa_ffs.b = 43.f;
+  hfa_ffs.c.a = 44.f;
+  hfa_ffs.c.b = 45.f;
+}
+
+#include "abitest.h"
+#else
+  ARG      (int, 1, X0, LAST_NAMED_ARG_ID)
+  DOTS
+  ANON     (struct hfa_ffs_t  , hfa_ffs  , S0     , 0)
+  ANON     (union  hfa_union_t, hfa_union, S4     , 1)
+  ANON     (struct hfa_dx2_t  , hfa_dx2  , D6     , 2)
+  ANON     (struct hfa_fx1_t  , hfa_fx1  , STACK  , 3)
+  LAST_ANON(double            , 1.0      , STACK+8, 4)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c
new file mode 100644
index 000000000..b82e7a742
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-7.c
@@ -0,0 +1,31 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   This test covers complex types.  Complex floating-point types are treated
+   as homogeneous floating-point aggregates, while complex integral types
+   are treated as general composite types.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-7.c"
+#include "type-def.h"
+
+_Complex __int128 complex_qword = 567890 + 678901i;
+
+#include "abitest.h"
+#else
+  ARG      (int, 1, X0, LAST_NAMED_ARG_ID)
+  DOTS
+  /* Complex floating-point types are passed in fp/simd registers.  */
+  ANON     (_Complex float      , 12.3f + 23.4fi              , S0,  0)
+  ANON     (_Complex double     , 34.56 + 45.67i              , D2,  1)
+  ANON     (_Complex long double, 56789.01234L + 67890.12345Li, Q4,  2)
+
+  /* Complex integral types are passed in general registers or via reference.  */
+  ANON     (_Complex short      , (short)12345 + (short)23456i, X1, 10)
+  ANON     (_Complex int        , 34567 + 45678i              , X2, 11)
+  PTR_ANON (_Complex __int128   , complex_qword               , X3, 12)
+
+  LAST_ANON(int                 , 1                           , X4, 20)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c
new file mode 100644
index 000000000..d14848298
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-8.c
@@ -0,0 +1,25 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   Miscellaneous test: HFA anonymous parameter passed in SIMD/FP regs.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-8.c"
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 0xdeadbeef, W0, LAST_NAMED_ARG_ID)
+  DOTS
+  ANON(double, 4.0, D0, 1)
+  LAST_ANON(struct z, a, D1, 2)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c
new file mode 100644
index 000000000..a5183bef4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-9.c
@@ -0,0 +1,31 @@
+/* Test AAPCS64 layout and __builtin_va_arg.
+
+   Miscellaneous test: HFA anonymous parameter passed in SIMD/FP regs.  */
+
+/* { dg-do run { target aarch64*-*-* } } */
+
+#ifndef IN_FRAMEWORK
+#define AAPCS64_TEST_STDARG
+#define TESTFILE "va_arg-9.c"
+
+struct z
+{
+  double x[4];
+};
+
+double d1 = 25.0;
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(double, 11.0, D0, LAST_NAMED_ARG_ID)
+  DOTS
+  ANON(int, 8, W0, 1)
+  ANON(struct z, a, D1, 2)
+  ANON(struct z, b, STACK, 3)
+  ANON(int, 5, W1, 4)
+  ANON(double, d1, STACK+32, 5)
+  LAST_ANON(double, 0.5, STACK+40, 6)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/validate_memory.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/validate_memory.h
new file mode 100644
index 000000000..24431c662
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/validate_memory.h
@@ -0,0 +1,81 @@
+/* Memory validation functions for AArch64 procedure call standard.
+   Copyright (C) 2012 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GCC is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef VALIDATE_MEMORY_H
+#define VALIDATE_MEMORY_H
+
+enum structure_type
+{
+  flat = 0,
+  i32in128,
+  f32in64,
+  i8in64,
+  i16in64,
+  i32in64,
+};
+
+/* Some explicit declarations as I can't include files outside the testsuite.
+ */
+typedef long unsigned int size_t;
+int memcmp (void *, void *, size_t);
+
+/* These two arrays contain element size and block size data for the enumeration
+   above.  */
+const int element_size[] =       { 1, 4,  4, 1, 2, 4 };
+const int block_reverse_size[] = { 1, 16, 8, 8, 8, 8 };
+
+int
+validate_memory (void *mem1, char *mem2, size_t size, enum structure_type type)
+{
+  /* In big-endian mode, the data in mem2 will have been byte-reversed in
+     register sized groups, while the data in mem1 will have been byte-reversed
+     according to the true structure of the data.  To compare them, we need to
+     compare chunks of data in reverse order.
+
+     This is only implemented for homogeneous data layouts at the moment.  For
+     hetrogeneous structures a custom compare case will need to be written.  */
+
+  unsigned int i;
+  char *cmem1 = (char *) mem1;
+  switch (type)
+    {
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+    case i8in64:
+    case i16in64:
+    case i32in64:
+      for (i = 0; i < size; i += element_size[type])
+	{
+	  if (memcmp (cmem1 + i,
+		      mem2 + block_reverse_size[type] - i - element_size[type],
+		      element_size[type]))
+	    return 1;
+	}
+      return 0;
+      break;
+#endif
+    case f32in64:
+    case i32in128:
+    default:
+      break;
+    }
+  return memcmp (mem1, mem2, size);
+}
+
+#endif  /* VALIDATE_MEMORY_H.  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aarch64.exp b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aarch64.exp
new file mode 100644
index 000000000..2cd3b805b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aarch64.exp
@@ -0,0 +1,45 @@
+#  Specific regression driver for AArch64.
+#  Copyright (C) 2009-2014 Free Software Foundation, Inc.
+#  Contributed by ARM Ltd.
+#
+#  This file is part of GCC.
+#
+#  GCC is free software; you can redistribute it and/or modify it
+#  under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 3, or (at your option)
+#  any later version.
+#
+#  GCC is distributed in the hope that it will be useful, but
+#  WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with GCC; see the file COPYING3.  If not see
+#  <http://www.gnu.org/licenses/>.  */
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an AArch64 target.
+if {![istarget aarch64*-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/abs_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/abs_1.c
new file mode 100644
index 000000000..938bc84ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/abs_1.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline --save-temps" } */
+
+extern long long llabs (long long);
+extern void abort (void);
+
+long long
+abs64 (long long a)
+{
+  /* { dg-final { scan-assembler "eor\t" } } */
+  /* { dg-final { scan-assembler "sub\t" } } */
+  return llabs (a);
+}
+
+long long
+abs64_in_dreg (long long a)
+{
+  /* { dg-final { scan-assembler "abs\td\[0-9\]+, d\[0-9\]+" } } */
+  register long long x asm ("d8") = a;
+  register long long y asm ("d9");
+  asm volatile ("" : : "w" (x));
+  y = llabs (x);
+  asm volatile ("" : : "w" (y));
+  return y;
+}
+
+int
+main (void)
+{
+  volatile long long ll0 = 0LL, ll1 = 1LL, llm1 = -1LL;
+
+  if (abs64 (ll0) != 0LL)
+    abort ();
+
+  if (abs64 (ll1) != 1LL)
+    abort ();
+
+  if (abs64 (llm1) != 1LL)
+    abort ();
+
+  if (abs64_in_dreg (ll0) != 0LL)
+    abort ();
+
+  if (abs64_in_dreg (ll1) != 1LL)
+    abort ();
+
+  if (abs64_in_dreg (llm1) != 1LL)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-1.c
new file mode 100644
index 000000000..c19920ce5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+volatile unsigned int w0, w1, w2, w3, w4;
+volatile int result;
+
+void test_si() {
+  /* { dg-final { scan-assembler "adc\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+  w0 = w1 + w2 + (w3 >= w4);
+}
+
+volatile unsigned long long int x0, x1, x2, x3, x4;
+
+void test_di() {
+  /* { dg-final { scan-assembler "adc\tx\[0-9\]*, x\[0-9\]*, x\[0-9\]*\n" } } */
+  x0 = x1 + x2 + (x3 >= x4);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-2.c
new file mode 100644
index 000000000..0f1361910
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adc-2.c
@@ -0,0 +1,277 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+/* This series of tests looks for the optimization:
+   x = (a >= b) + c + d
+   =>
+   cmp a, b
+   adc x, c, d
+ */
+
+unsigned long 
+ltu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+  return (a < b) + c + d;
+}
+
+unsigned long 
+gtu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+  return (a > b) + c + d;
+}
+
+unsigned long 
+leu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+  return (a <= b) + c + d;
+}
+
+unsigned long 
+geu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+  return (a >= b) + c + d;
+}
+
+unsigned long 
+equ_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+  return (a == b) + c + d;
+}
+
+unsigned long 
+neu_add (unsigned long a, unsigned long b, unsigned long c, unsigned long d)
+{
+  return (a != b) + c + d;
+}
+
+long 
+lt_add ( long a,  long b,  long c,  long d)
+{
+  return (a < b) + c + d;
+}
+
+long 
+gt_add ( long a,  long b,  long c,  long d)
+{
+  return (a > b) + c + d;
+}
+
+long 
+le_add ( long a,  long b,  long c,  long d)
+{
+  return (a <= b) + c + d;
+}
+
+long 
+ge_add ( long a,  long b,  long c,  long d)
+{
+  return (a >= b) + c + d;
+}
+
+long 
+eq_add ( long a,  long b,  long c,  long d)
+{
+  return (a == b) + c + d;
+}
+
+long 
+ne_add ( long a,  long b,  long c,  long d)
+{
+  return (a != b) + c + d;
+}
+
+
+int
+main ()
+{
+  if (ltu_add(1,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (ltu_add(2,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (ltu_add(3,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (gtu_add(2,1,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (gtu_add(2,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (gtu_add(1,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (leu_add(1,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (leu_add(2,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (leu_add(3,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (leu_add(2,1,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (geu_add(2,1,3,4) != 8)
+    {
+      abort();
+    }
+  if (geu_add(2,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (geu_add(1,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (equ_add(1,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (equ_add(2,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (equ_add(3,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (neu_add(1,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (neu_add(2,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (neu_add(3,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (lt_add(1,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (lt_add(2,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (lt_add(3,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (gt_add(2,1,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (gt_add(2,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (gt_add(1,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (le_add(1,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (le_add(2,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (le_add(3,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (le_add(2,1,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (ge_add(2,1,3,4) != 8)
+    {
+      abort();
+    }
+  if (ge_add(2,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (ge_add(1,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (eq_add(1,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (eq_add(2,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (eq_add(3,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (ne_add(1,2,3,4) != 8)
+    {
+      abort();
+    }
+
+  if (ne_add(2,2,3,4) != 7)
+    {
+      abort();
+    }
+
+  if (ne_add(3,2,3,4) != 8)
+    {
+      abort();
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds.c
new file mode 100644
index 000000000..aa423210d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int z;
+int
+foo (int x, int y)
+{
+  int l = x + y;
+  if (l == 0)
+    return 5;
+
+  /* { dg-final { scan-assembler "adds\tw\[0-9\]" } } */
+  z = l ;
+  return 25;
+}
+
+typedef long long s64;
+
+s64 zz;
+s64
+foo2 (s64 x, s64 y)
+{
+  s64 l = x + y;
+  if (l < 0)
+    return 5;
+
+  /* { dg-final { scan-assembler "adds\tx\[0-9\]" } } */
+  zz = l ;
+  return 25;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds1.c
new file mode 100644
index 000000000..eb19bbfd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds1.c
@@ -0,0 +1,149 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+adds_si_test1 (int a, int b, int c)
+{
+  int d = a + b;
+
+  /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_si_test2 (int a, int b, int c)
+{
+  int d = a + 0xff;
+
+  /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, 255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_si_test3 (int a, int b, int c)
+{
+  int d = a + (b << 3);
+
+  /* { dg-final { scan-assembler "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+adds_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + b;
+
+  /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+adds_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + 0xff;
+
+  /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, 255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+adds_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + (b << 3);
+
+  /* { dg-final { scan-assembler "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = adds_si_test1 (29, 4, 5);
+  if (x != 42)
+    abort ();
+
+  x = adds_si_test1 (5, 2, 20);
+  if (x != 29)
+    abort ();
+
+  x = adds_si_test2 (29, 4, 5);
+  if (x != 293)
+    abort ();
+
+  x = adds_si_test2 (1024, 2, 20);
+  if (x != 1301)
+    abort ();
+
+  x = adds_si_test3 (35, 4, 5);
+  if (x != 76)
+    abort ();
+
+  x = adds_si_test3 (5, 2, 20);
+  if (x != 43)
+    abort ();
+
+  y = adds_di_test1 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+
+  if (y != 0xc75050536)
+    abort ();
+
+  y = adds_di_test1 (0x5000500050005ll,
+		     0x2111211121112ll,
+		     0x0000000002020ll);
+  if (y != 0x9222922294249)
+    abort ();
+
+  y = adds_di_test2 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955050631)
+    abort ();
+
+  y = adds_di_test2 (0x130002900ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955052f08)
+    abort ();
+
+  y = adds_di_test3 (0x130000029ll,
+		     0x064000008ll,
+		     0x505050505ll);
+  if (y != 0x9b9050576)
+    abort ();
+
+  y = adds_di_test3 (0x130002900ll,
+		     0x088000008ll,
+		     0x505050505ll);
+  if (y != 0xafd052e4d)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds2.c
new file mode 100644
index 000000000..bd130a99a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds2.c
@@ -0,0 +1,155 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+adds_si_test1 (int a, int b, int c)
+{
+  int d = a + b;
+
+  /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_si_test2 (int a, int b, int c)
+{
+  int d = a + 0xfff;
+
+  /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, 4095" } } */
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, 4095" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_si_test3 (int a, int b, int c)
+{
+  int d = a + (b << 3);
+
+  /* { dg-final { scan-assembler-not "adds\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+adds_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + b;
+
+  /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+adds_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + 0x1000ll;
+
+  /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, 4096" } } */
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, 4096" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+adds_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a + (b << 3);
+
+  /* { dg-final { scan-assembler-not "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = adds_si_test1 (29, 4, 5);
+  if (x != 42)
+    abort ();
+
+  x = adds_si_test1 (5, 2, 20);
+  if (x != 29)
+    abort ();
+
+  x = adds_si_test2 (29, 4, 5);
+  if (x != 4133)
+    abort ();
+
+  x = adds_si_test2 (1024, 2, 20);
+  if (x != 5141)
+    abort ();
+
+  x = adds_si_test3 (35, 4, 5);
+  if (x != 76)
+    abort ();
+
+  x = adds_si_test3 (5, 2, 20);
+  if (x != 43)
+    abort ();
+
+  y = adds_di_test1 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+
+  if (y != 0xc75050536)
+    abort ();
+
+  y = adds_di_test1 (0x5000500050005ll,
+		     0x2111211121112ll,
+		     0x0000000002020ll);
+  if (y != 0x9222922294249)
+    abort ();
+
+  y = adds_di_test2 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955051532)
+    abort ();
+
+  y = adds_di_test2 (0x540004100ll,
+		     0x320000004ll,
+		     0x805050205ll);
+  if (y != 0x1065055309)
+    abort ();
+
+  y = adds_di_test3 (0x130000029ll,
+		     0x064000008ll,
+		     0x505050505ll);
+  if (y != 0x9b9050576)
+    abort ();
+
+  y = adds_di_test3 (0x130002900ll,
+		     0x088000008ll,
+		     0x505050505ll);
+  if (y != 0xafd052e4d)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds3.c
new file mode 100644
index 000000000..18efd1c21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/adds3.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+typedef long long s64;
+
+int
+adds_ext (s64 a, int b, int c)
+{
+ s64 d = a + b;
+
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+adds_shift_ext (s64 a, int b, int c)
+{
+ s64 d = (a + ((s64)b << 3));
+
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = adds_ext (0x13000002ll, 41, 15);
+  if (x != 318767203)
+    abort ();
+
+  x = adds_ext (0x50505050ll, 29, 4);
+  if (x != 1347440782)
+    abort ();
+
+  x = adds_ext (0x12121212121ll, 2, 14);
+  if (x != 555819315)
+    abort ();
+
+  x = adds_shift_ext (0x123456789ll, 4, 12);
+  if (x != 591751097)
+    abort ();
+
+  x = adds_shift_ext (0x02020202ll, 9, 8);
+  if (x != 33686107)
+    abort ();
+
+  x = adds_shift_ext (0x987987987987ll, 23, 41);
+  if (x != -2020050305)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aes_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aes_1.c
new file mode 100644
index 000000000..5fa61379e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aes_1.c
@@ -0,0 +1,40 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint8x16_t
+test_vaeseq_u8 (uint8x16_t data, uint8x16_t key)
+{
+  return vaeseq_u8 (data, key);
+}
+
+/* { dg-final { scan-assembler-times "aese\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesdq_u8 (uint8x16_t data, uint8x16_t key)
+{
+  return vaesdq_u8 (data, key);
+}
+
+/* { dg-final { scan-assembler-times "aesd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesmcq_u8 (uint8x16_t data)
+{
+  return vaesmcq_u8 (data);
+}
+
+/* { dg-final { scan-assembler-times "aesmc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+uint8x16_t
+test_vaesimcq_u8 (uint8x16_t data)
+{
+  return vaesimcq_u8 (data);
+}
+
+/* { dg-final { scan-assembler-times "aesimc\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_1.c
new file mode 100644
index 000000000..aace0b064
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_1.c
@@ -0,0 +1,151 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+  int d = a & b;
+
+  /* { dg-final { scan-assembler-times "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+ands_si_test2 (int a, int b, int c)
+{
+  int d = a & 0xff;
+
+  /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, 255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+ands_si_test3 (int a, int b, int c)
+{
+  int d = a & (b << 3);
+
+  /* { dg-final { scan-assembler "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+ands_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & b;
+
+  /* { dg-final { scan-assembler-times "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+ands_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & 0xff;
+
+  /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, 255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+ands_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & (b << 3);
+
+  /* { dg-final { scan-assembler "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+main ()
+{
+  int x;
+  s64 y;
+
+  x = ands_si_test1 (29, 4, 5);
+  if (x != 13)
+    abort ();
+
+  x = ands_si_test1 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  x = ands_si_test2 (29, 4, 5);
+  if (x != 38)
+    abort ();
+
+  x = ands_si_test2 (1024, 2, 20);
+  if (x != 1044)
+    abort ();
+
+  x = ands_si_test3 (35, 4, 5);
+  if (x != 41)
+    abort ();
+
+  x = ands_si_test3 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  y = ands_di_test1 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+
+  if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test1 (0x5000500050005ll,
+                     0x2111211121112ll,
+                     0x0000000002020ll);
+  if (y != 0x5000500052025ll)
+    abort ();
+
+  y = ands_di_test2 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & 0xff) + 0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test2 (0x130002900ll,
+                     0x320000004ll,
+                     0x505050505ll);
+  if (y != (0x130002900ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test3 (0x130000029ll,
+                     0x064000008ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & (0x064000008ll << 3))
+	    + 0x064000008ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test3 (0x130002900ll,
+                     0x088000008ll,
+                     0x505050505ll);
+  if (y != (0x130002900ll + 0x505050505ll))
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_2.c
new file mode 100644
index 000000000..1c5b8213e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ands_2.c
@@ -0,0 +1,157 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+ands_si_test1 (int a, int b, int c)
+{
+  int d = a & b;
+
+  /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+ands_si_test2 (int a, int b, int c)
+{
+  int d = a & 0x99999999;
+
+  /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+ands_si_test3 (int a, int b, int c)
+{
+  int d = a & (b << 3);
+
+  /* { dg-final { scan-assembler-not "ands\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+ands_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & b;
+
+  /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+ands_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & 0xaaaaaaaaaaaaaaaall;
+
+  /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+ands_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & (b << 3);
+
+  /* { dg-final { scan-assembler-not "ands\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+main ()
+{
+  int x;
+  s64 y;
+
+  x = ands_si_test1 (29, 4, 5);
+  if (x != 13)
+    abort ();
+
+  x = ands_si_test1 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  x = ands_si_test2 (29, 4, 5);
+  if (x != 34)
+    abort ();
+
+  x = ands_si_test2 (1024, 2, 20);
+  if (x != 1044)
+    abort ();
+
+  x = ands_si_test3 (35, 4, 5);
+  if (x != 41)
+    abort ();
+
+  x = ands_si_test3 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  y = ands_di_test1 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+
+  if (y != ((0x130000029ll & 0x320000004ll) + 0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test1 (0x5000500050005ll,
+                     0x2111211121112ll,
+                     0x0000000002020ll);
+  if (y != 0x5000500052025ll)
+    abort ();
+
+  y = ands_di_test2 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & 0xaaaaaaaaaaaaaaaall) + 0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test2 (0x540004100ll,
+                     0x320000004ll,
+                     0x805050205ll);
+  if (y != (0x540004100ll + 0x805050205ll))
+    abort ();
+
+  y = ands_di_test3 (0x130000029ll,
+                     0x064000008ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & (0x064000008ll << 3))
+	    + 0x064000008ll + 0x505050505ll))
+    abort ();
+
+  y = ands_di_test3 (0x130002900ll,
+                     0x088000008ll,
+                     0x505050505ll);
+  if (y != (0x130002900ll + 0x505050505ll))
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c
new file mode 100644
index 000000000..a0f598252
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-1.c
@@ -0,0 +1,7 @@
+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -march=dummy" } */
+
+void f ()
+{
+  return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c
new file mode 100644
index 000000000..f1f3ea38c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arch-diagnostics-2.c
@@ -0,0 +1,7 @@
+/* { dg-error "missing" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -march=+dummy" } */
+
+void f ()
+{
+  return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c
new file mode 100644
index 000000000..55dd9f66f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/arg-type-diagnostics-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { aarch64*-*-* } } } */
+/* { dg-options "-O2" } */
+
+#include "arm_neon.h"
+
+void foo ()
+{
+  int a;
+  int32x2_t arg1;
+  int32x2_t arg2;
+  int32x2_t result;
+  arg1 = vcreate_s32 (UINT64_C (0x0000ffffffffffff));
+  arg2 = vcreate_s32 (UINT64_C (0x16497fffffffffff));
+  result = __builtin_aarch64_srsra_nv2si (arg1, arg2, a); /* { dg-error "incompatible type for argument" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-1.c
new file mode 100644
index 000000000..bdfa4504f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-1.c
@@ -0,0 +1,15 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+typedef struct
+{
+  int i;
+  int y;
+} __attribute__ ((aligned (16))) struct64_t;
+
+void foo ()
+{
+  struct64_t tmp;
+  asm volatile ("ldr q0, %[value]" : : [value]"m"(tmp));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-clobber-lr.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-clobber-lr.c
new file mode 100644
index 000000000..540c79b01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-clobber-lr.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+int
+adder (int a, int b)
+{
+  int result;
+  __asm__ ("add %w0,%w1,%w2" : "=r"(result) : "r"(a), "r"(b) : "x30");
+  return result;
+}
+
+int
+main (int argc, char** argv)
+{
+  int i;
+  int total = argc;
+  for (i = 0; i < 20; i++)
+    total = adder (total, i);
+
+  if (total != (190 + argc))
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-no-clobber-lr.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-no-clobber-lr.c
new file mode 100644
index 000000000..2543d50e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/asm-adder-no-clobber-lr.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+int
+adder (int a, int b)
+{
+  int result;
+  __asm__ ("add %w0,%w1,%w2" : "=r"(result) : "r"(a), "r"(b) : );
+  return result;
+}
+
+int
+main (int argc, char** argv)
+{
+  int i;
+  int total = argc;
+  for (i = 0; i < 20; i++)
+    total = adder (total, i);
+
+  if (total != (190 + argc))
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
new file mode 100644
index 000000000..9785bca4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-comp-swap-release-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x
new file mode 100644
index 000000000..4403afd64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.x
@@ -0,0 +1,36 @@
+
+#define STRONG 0
+#define WEAK 1
+int v = 0;
+
+int
+atomic_compare_exchange_STRONG_RELEASE_ACQUIRE (int a, int b)
+{
+  return __atomic_compare_exchange (&v, &a, &b,
+				    STRONG, __ATOMIC_RELEASE,
+				    __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_WEAK_RELEASE_ACQUIRE (int a, int b)
+{
+  return __atomic_compare_exchange (&v, &a, &b,
+				    WEAK, __ATOMIC_RELEASE,
+				    __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_n_STRONG_RELEASE_ACQUIRE (int a, int b)
+{
+  return __atomic_compare_exchange_n (&v, &a, b,
+				      STRONG, __ATOMIC_RELEASE,
+				      __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_compare_exchange_n_WEAK_RELEASE_ACQUIRE (int a, int b)
+{
+  return __atomic_compare_exchange_n (&v, &a, b,
+				      WEAK, __ATOMIC_RELEASE,
+				      __ATOMIC_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
new file mode 100644
index 000000000..8569ac0df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-acq_rel.x"
+
+/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x
new file mode 100644
index 000000000..9970bbb25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_ACQ_REL (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_sub_ACQ_REL (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_and_ACQ_REL (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_nand_ACQ_REL (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_xor_ACQ_REL (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_or_ACQ_REL (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_ACQ_REL);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
new file mode 100644
index 000000000..57e6d57d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x
new file mode 100644
index 000000000..7eeb7f845
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_ACQUIRE (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_sub_ACQUIRE (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_and_ACQUIRE (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_nand_ACQUIRE (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_xor_ACQUIRE (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_or_ACQUIRE (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
new file mode 100644
index 000000000..d6c2aa593
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-char.x"
+
+/* { dg-final { scan-assembler-times "ldxrb\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxrb\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x
new file mode 100644
index 000000000..a543aa9e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-char.x
@@ -0,0 +1,37 @@
+char v = 0;
+
+char
+atomic_fetch_add_RELAXED (char a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_sub_RELAXED (char a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_and_RELAXED (char a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_nand_RELAXED (char a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_xor_RELAXED (char a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+char
+atomic_fetch_or_RELAXED (char a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
new file mode 100644
index 000000000..38d6c2cfb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-consume.x"
+
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x
new file mode 100644
index 000000000..c6b0792ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_CONSUME (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_sub_CONSUME (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_and_CONSUME (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_nand_CONSUME (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_xor_CONSUME (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_or_CONSUME (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_CONSUME);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c
new file mode 100644
index 000000000..6c6f7e16d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int v = 0;
+
+int
+atomic_fetch_add_RELAXED ()
+{
+  return __atomic_fetch_add (&v, 4096, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_sub_ACQUIRE ()
+{
+  return __atomic_fetch_sub (&v, 4096, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_fetch_and_SEQ_CST ()
+{
+  return __atomic_fetch_and (&v, 4096, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_nand_ACQ_REL ()
+{
+  return __atomic_fetch_nand (&v, 4096, __ATOMIC_ACQ_REL);
+}
+
+int
+atomic_fetch_xor_CONSUME ()
+{
+  return __atomic_fetch_xor (&v, 4096, __ATOMIC_CONSUME);
+}
+
+int
+atomic_fetch_or_RELAXED ()
+{
+  return __atomic_fetch_or (&v, 4096, __ATOMIC_RELAXED);
+}
+
+int
+atomic_add_fetch_ACQUIRE ()
+{
+  return __atomic_add_fetch (&v, 4096, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_sub_fetch_RELAXED ()
+{
+  return __atomic_sub_fetch (&v, 4096, __ATOMIC_RELAXED);
+}
+
+int
+atomic_and_fetch_SEQ_CST ()
+{
+  return __atomic_and_fetch (&v, 4096, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_nand_fetch_ACQUIRE ()
+{
+  return __atomic_nand_fetch (&v, 4096, __ATOMIC_ACQUIRE);
+}
+
+int
+atomic_xor_fetch_RELEASE ()
+{
+  return __atomic_xor_fetch (&v, 4096, __ATOMIC_RELEASE);
+}
+
+int
+atomic_or_fetch_CONSUME ()
+{
+  return __atomic_or_fetch (&v, 4096, __ATOMIC_CONSUME);
+}
+
+/* { dg-final { scan-assembler-times "\tw\[0-9\]+, w\[0-9\]+, #*4096" 12 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
new file mode 100644
index 000000000..9ad7a794f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-int.x"
+
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x
new file mode 100644
index 000000000..74ab6323c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-int.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_RELAXED (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_sub_RELAXED (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_and_RELAXED (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_nand_RELAXED (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_xor_RELAXED (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_or_RELAXED (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
new file mode 100644
index 000000000..0672d48b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long v = 0;
+
+long
+atomic_fetch_add_RELAXED (long a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_sub_RELAXED (long a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_and_RELAXED (long a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_nand_RELAXED (long a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_xor_RELAXED (long a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+long
+atomic_fetch_or_RELAXED (long a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
+
+/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
new file mode 100644
index 000000000..cd3fe2c3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-relaxed.x"
+
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x
new file mode 100644
index 000000000..74ab6323c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_RELAXED (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_sub_RELAXED (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_and_RELAXED (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_nand_RELAXED (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_xor_RELAXED (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+int
+atomic_fetch_or_RELAXED (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
new file mode 100644
index 000000000..2fc04b210
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-release.x"
+
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x
new file mode 100644
index 000000000..343f09b52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-release.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_RELEASE (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_sub_RELEASE (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_and_RELEASE (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_nand_RELEASE (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_xor_RELEASE (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELEASE);
+}
+
+int
+atomic_fetch_or_RELEASE (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
new file mode 100644
index 000000000..202d471d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-seq_cst.x"
+
+/* { dg-final { scan-assembler-times "ldaxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x
new file mode 100644
index 000000000..e654a74e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.x
@@ -0,0 +1,37 @@
+int v = 0;
+
+int
+atomic_fetch_add_SEQ_CST (int a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_sub_SEQ_CST (int a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_and_SEQ_CST (int a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_nand_SEQ_CST (int a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_xor_SEQ_CST (int a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_SEQ_CST);
+}
+
+int
+atomic_fetch_or_SEQ_CST (int a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
new file mode 100644
index 000000000..39e71c18a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "atomic-op-short.x"
+
+/* { dg-final { scan-assembler-times "ldxrh\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stxrh\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x
new file mode 100644
index 000000000..2fd70f59e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/atomic-op-short.x
@@ -0,0 +1,37 @@
+short v = 0;
+
+short
+atomic_fetch_add_RELAXED (short a)
+{
+  return __atomic_fetch_add (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_sub_RELAXED (short a)
+{
+  return __atomic_fetch_sub (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_and_RELAXED (short a)
+{
+  return __atomic_fetch_and (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_nand_RELAXED (short a)
+{
+  return __atomic_fetch_nand (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_xor_RELAXED (short a)
+{
+  return __atomic_fetch_xor (&v, a, __ATOMIC_RELAXED);
+}
+
+short
+atomic_fetch_or_RELAXED (short a)
+{
+  return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_1.c
new file mode 100644
index 000000000..b16834786
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_1.c
@@ -0,0 +1,40 @@
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+/* { dg-require-effective-target aarch64_little_endian } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+  unsigned short eight1: 8;
+  unsigned short four: 4;
+  unsigned short eight2: 8;
+  unsigned short seven: 7;
+  unsigned int sixteen: 16;
+} bitfield;
+
+bitfield
+bfxil (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfxil\tx\[0-9\]+, x\[0-9\]+, 16, 8" } } */
+  a.eight1 = a.eight2;
+  return a;
+}
+
+int
+main (void)
+{
+  static bitfield a;
+  bitfield b;
+
+  a.eight1 = 9;
+  a.eight2 = 57;
+  b = bfxil (a);
+
+  if (b.eight1 != a.eight2)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_2.c
new file mode 100644
index 000000000..4e4d610c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bfxil_2.c
@@ -0,0 +1,42 @@
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+/* { dg-require-effective-target aarch64_big_endian } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+  unsigned short eight1: 8;
+  unsigned short four: 4;
+  unsigned short eight2: 8;
+  unsigned short seven: 7;
+  unsigned int sixteen: 16;
+  unsigned short eight3: 8;
+  unsigned short eight4: 8;
+} bitfield;
+
+bitfield
+bfxil (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfxil\tx\[0-9\]+, x\[0-9\]+, 40, 8" } } */
+  a.eight4 = a.eight2;
+  return a;
+}
+
+int
+main (void)
+{
+  static bitfield a;
+  bitfield b;
+
+  a.eight4 = 9;
+  a.eight2 = 57;
+  b = bfxil (a);
+
+  if (b.eight4 != a.eight2)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_1.c
new file mode 100644
index 000000000..d62ea9a65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_1.c
@@ -0,0 +1,107 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+bics_si_test1 (int a, int b, int c)
+{
+  int d = a & ~b;
+
+  /* { dg-final { scan-assembler-times "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+bics_si_test2 (int a, int b, int c)
+{
+  int d = a & ~(b << 3);
+
+  /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+bics_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & ~b;
+
+  /* { dg-final { scan-assembler-times "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+bics_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & ~(b << 3);
+
+  /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+main ()
+{
+  int x;
+  s64 y;
+
+  x = bics_si_test1 (29, ~4, 5);
+  if (x != ((29 & 4) + ~4 + 5))
+    abort ();
+
+  x = bics_si_test1 (5, ~2, 20);
+  if (x != 25)
+    abort ();
+
+  x = bics_si_test2 (35, ~4, 5);
+  if (x != ((35 & ~(~4 << 3)) + ~4 + 5))
+    abort ();
+
+  x = bics_si_test2 (96, ~2, 20);
+  if (x != 116)
+    abort ();
+
+  y = bics_di_test1 (0x130000029ll,
+                     ~0x320000004ll,
+                     0x505050505ll);
+
+  if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = bics_di_test1 (0x5000500050005ll,
+                     ~0x2111211121112ll,
+                     0x0000000002020ll);
+  if (y != 0x5000500052025ll)
+    abort ();
+
+  y = bics_di_test2 (0x130000029ll,
+                     ~0x064000008ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & ~(~0x064000008ll << 3))
+	    + ~0x064000008ll + 0x505050505ll))
+    abort ();
+
+  y = bics_di_test2 (0x130002900ll,
+                     ~0x088000008ll,
+                     0x505050505ll);
+  if (y != (0x130002900ll + 0x505050505ll))
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_2.c
new file mode 100644
index 000000000..e33c748ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/bics_2.c
@@ -0,0 +1,111 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+bics_si_test1 (int a, int b, int c)
+{
+  int d = a & ~b;
+
+  /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+bics_si_test2 (int a, int b, int c)
+{
+  int d = a & ~(b << 3);
+
+  /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+bics_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & ~b;
+
+  /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+bics_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & ~(b << 3);
+
+  /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+main ()
+{
+  int x;
+  s64 y;
+
+  x = bics_si_test1 (29, ~4, 5);
+  if (x != ((29 & 4) + ~4 + 5))
+    abort ();
+
+  x = bics_si_test1 (5, ~2, 20);
+  if (x != 25)
+    abort ();
+
+  x = bics_si_test2 (35, ~4, 5);
+  if (x != ((35 & ~(~4 << 3)) + ~4 + 5))
+    abort ();
+
+  x = bics_si_test2 (96, ~2, 20);
+  if (x != 116)
+    abort ();
+
+  y = bics_di_test1 (0x130000029ll,
+                     ~0x320000004ll,
+                     0x505050505ll);
+
+  if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll))
+    abort ();
+
+  y = bics_di_test1 (0x5000500050005ll,
+                     ~0x2111211121112ll,
+                     0x0000000002020ll);
+  if (y != 0x5000500052025ll)
+    abort ();
+
+  y = bics_di_test2 (0x130000029ll,
+                     ~0x064000008ll,
+                     0x505050505ll);
+  if (y != ((0x130000029ll & ~(~0x064000008ll << 3))
+	    + ~0x064000008ll + 0x505050505ll))
+    abort ();
+
+  y = bics_di_test2 (0x130002900ll,
+                     ~0x088000008ll,
+                     0x505050505ll);
+  if (y != (0x130002900ll + 0x505050505ll))
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-1.c
new file mode 100644
index 000000000..a6706e693
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-times "rev16\\t" 2 } }  */
+
+/* rev16 */
+short
+swaps16 (short x)
+{
+  return __builtin_bswap16 (x);
+}
+
+/* rev16 */
+unsigned short
+swapu16 (unsigned short x)
+{
+  return __builtin_bswap16 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-2.c
new file mode 100644
index 000000000..6018b4834
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/builtin-bswap-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-times "rev16\\t" 2 } }  */
+
+/* rev16 */
+unsigned short
+swapu16_1 (unsigned short x)
+{
+  return (x << 8) | (x >> 8);
+}
+
+/* rev16 */
+unsigned short
+swapu16_2 (unsigned short x)
+{
+  return (x >> 8) | (x << 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-2.c
new file mode 100644
index 000000000..ced96d045
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+
+void
+test (void)
+{
+    __asm__ ("@ %c0" : : "S" (test));
+}
+
+/* { dg-final { scan-assembler "@ test" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c
new file mode 100644
index 000000000..c28837cd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-Wno-pointer-arith" } */
+
+void
+test (void)
+{
+    __asm__ ("@ %c0" : : "S" (&test + 4));
+}
+
+/* { dg-final { scan-assembler "@ test\\+4" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template.c
new file mode 100644
index 000000000..1b67c9169
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/c-output-template.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+
+void
+test (void)
+{
+    __asm__ ("@ %c0" : : "i" (42));
+}
+
+/* { dg-final { scan-assembler "@ 42" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clrsb.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clrsb.c
new file mode 100644
index 000000000..ac8d2e051
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clrsb.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest (unsigned int x)
+{
+  return __builtin_clrsb (x);
+}
+
+/* { dg-final { scan-assembler "cls\tw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clz.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clz.c
new file mode 100644
index 000000000..b650b1318
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/clz.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest (unsigned int x)
+{
+  return __builtin_clz (x);
+}
+
+/* { dg-final { scan-assembler "clz\tw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg.c
new file mode 100644
index 000000000..ab264e798
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+void __attribute__ ((noinline))
+foo_s32 (int a, int b)
+{
+  if (a == -b)
+    abort ();
+}
+/* { dg-final { scan-assembler "cmn\tw\[0-9\]" } } */
+
+void __attribute__ ((noinline))
+foo_s64 (long long a, long long b)
+{
+  if (a == -b)
+    abort ();
+}
+/* { dg-final { scan-assembler "cmn\tx\[0-9\]" } } */
+
+
+int
+main (void)
+{
+  int a = 30;
+  int b = 42;
+  foo_s32 (a, b);
+  foo_s64 (a, b);
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg2.c
new file mode 100644
index 000000000..ca45a5343
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn-neg2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+/* It's unsafe to use CMN in these comparisons.  */
+
+void __attribute__ ((noinline))
+foo_s32 (int a, int b)
+{
+  if (a < -b)
+    abort ();
+}
+
+void __attribute__ ((noinline))
+foo_s64 (unsigned long long a, unsigned long long b)
+{
+  if (a > -b)
+    abort ();
+}
+
+
+int
+main (void)
+{
+  int a = 30;
+  int b = 42;
+  foo_s32 (a, b);
+  foo_s64 (a, b);
+  return 0;
+}
+/* { dg-final { scan-assembler-not "cmn\t" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn.c
new file mode 100644
index 000000000..1f06f57ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmn.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int a, int b)
+{
+  if (a + b)
+    return 5;
+  else
+    return 2;
+  /* { dg-final { scan-assembler "cmn\tw\[0-9\]" } } */
+}
+
+typedef long long s64;
+
+s64
+foo2 (s64 a, s64 b)
+{
+  if (a + b)
+    return 5;
+  else
+    return 2;
+  /* { dg-final { scan-assembler "cmn\tx\[0-9\]" } } */
+}  
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp-1.c
new file mode 100644
index 000000000..4c082b484
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int f(int a, int b)
+{
+  if(a<b)
+    return 1;
+  if(a>b)
+    return -1;
+  return 0;
+}
+
+/* We should optimize away the second cmp. */
+/* { dg-final { scan-assembler-times "cmp\tw" 1 } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp.c
new file mode 100644
index 000000000..ee57dd283
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cmp.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+cmp_si_test1 (int a, int b, int c)
+{
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_si_test2 (int a, int b, int c)
+{
+  if ((a >> 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+typedef long long s64;
+
+s64
+cmp_di_test1 (s64 a, s64 b, s64 c)
+{
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+s64
+cmp_di_test2 (s64 a, s64 b, s64 c)
+{
+  if ((a >> 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_di_test3 (int a, s64 b, s64 c)
+{
+  if (a > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+int
+cmp_di_test4 (int a, s64 b, s64 c)
+{
+  if (((s64)a << 3) > b)
+    return a + c;
+  else
+    return a + b + c;
+}
+
+/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c
new file mode 100644
index 000000000..de6b8a7da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-1.c
@@ -0,0 +1,7 @@
+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -mcpu=dummy" } */
+
+void f ()
+{
+  return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
new file mode 100644
index 000000000..2ca006598
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-2.c
@@ -0,0 +1,7 @@
+/* { dg-error "missing" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -mcpu=cortex-a53+no" } */
+
+void f ()
+{
+  return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
new file mode 100644
index 000000000..155def051
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-3.c
@@ -0,0 +1,7 @@
+/* { dg-error "unknown" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -mcpu=cortex-a53+dummy" } */
+
+void f ()
+{
+  return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c
new file mode 100644
index 000000000..4c246eb01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/cpu-diagnostics-4.c
@@ -0,0 +1,7 @@
+/* { dg-error "missing" "" {target "aarch64*-*-*" } } */
+/* { dg-options "-O2 -mcpu=+dummy" } */
+
+void f ()
+{
+  return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-1.c
new file mode 100644
index 000000000..132a0f679
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-1.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int
+test_csinc32_ifcvt(unsigned int w0,
+		   unsigned int w1,
+		   unsigned int w2) {
+  /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*ne" } } */
+  if (w0 == w1)
+    ++ w2;
+
+  return w2;
+}
+
+unsigned int
+test_csinc32_condasn1(unsigned int w0,
+		      unsigned int w1,
+		      unsigned int w2,
+		      unsigned int w3) {
+  unsigned int w4;
+
+  /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*ne" } } */
+  w4 = (w0 == w1) ? (w3 + 1) : w2;
+  return w4;
+}
+
+unsigned int
+test_csinc32_condasn2(unsigned int w0,
+		      unsigned int w1,
+		      unsigned int w2,
+		      unsigned int w3) {
+  unsigned int w4;
+
+  /* { dg-final { scan-assembler "csinc\tw\[0-9\]*.*eq" } } */
+  w4 = (w0 == w1) ? w2 : (w3 + 1);
+  return w4;
+}
+
+unsigned long long
+test_csinc64_ifcvt(unsigned long long x0,
+		   unsigned long long x1,
+		   unsigned long long x2) {
+  /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*ne" } } */
+  if (x0 == x1)
+    ++ x2;
+
+  return x2;
+}
+
+unsigned long long
+test_csinc64_condasn1(unsigned long long x0,
+		      unsigned long long x1,
+		      unsigned long long x2,
+		      unsigned long long x3) {
+  unsigned long long x4;
+
+  /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*ne" } } */
+  x4 = (x0 == x1) ? (x3 + 1) : x2;
+  return x4;
+}
+
+unsigned long long
+test_csinc64_condasn2(unsigned long long x0,
+		      unsigned long long x1,
+		      unsigned long long x2,
+		      unsigned long long x3) {
+  unsigned long long x4;
+
+  /* { dg-final { scan-assembler "csinc\tx\[0-9\]*.*eq" } } */
+  x4 = (x0 == x1) ? x2 : (x3 + 1);
+  return x4;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-2.c
new file mode 100644
index 000000000..9bd6861d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinc-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int a, int b)
+{
+  return (a < b) ? 1 : 7;
+  /* { dg-final { scan-assembler "csinc\tw\[0-9\].*wzr" } } */
+}
+
+typedef long long s64;
+
+s64
+foo2 (s64 a, s64 b)
+{
+  return (a == b) ? 7 : 1;
+  /* { dg-final { scan-assembler "csinc\tx\[0-9\].*xzr" } } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinv-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinv-1.c
new file mode 100644
index 000000000..8d44449f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csinv-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int
+test_csinv32_condasn1(unsigned int w0,
+		      unsigned int w1,
+		      unsigned int w2,
+		      unsigned int w3) {
+  unsigned int w4;
+
+  /* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*ne" } } */
+  w4 = (w0 == w1) ? ~w3 : w2;
+  return w4;
+}
+
+unsigned int
+test_csinv32_condasn2(unsigned int w0,
+		      unsigned int w1,
+		      unsigned int w2,
+		      unsigned int w3) {
+  unsigned int w4;
+
+  /* { dg-final { scan-assembler "csinv\tw\[0-9\]*.*eq" } } */
+  w4 = (w0 == w1) ? w3 : ~w2;
+  return w4;
+}
+
+unsigned long long
+test_csinv64_condasn1(unsigned long long x0,
+		      unsigned long long x1,
+		      unsigned long long x2,
+		      unsigned long long x3) {
+  unsigned long long x4;
+
+  /* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*ne" } } */
+  x4 = (x0 == x1) ? ~x3 : x2;
+  return x4;
+}
+
+unsigned long long
+test_csinv64_condasn2(unsigned long long x0,
+		      unsigned long long x1,
+		      unsigned long long x2,
+		      unsigned long long x3) {
+  unsigned long long x4;
+
+  /* { dg-final { scan-assembler "csinv\tx\[0-9\]*.*eq" } } */
+  x4 = (x0 == x1) ? x3 : ~x2;
+  return x4;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csneg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csneg-1.c
new file mode 100644
index 000000000..08001afd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/csneg-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+test_csneg32_condasn1(int w0,
+		      int w1,
+		      int w2,
+		      int w3) {
+  int w4;
+
+  /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */
+  w4 = (w0 == w1) ? -w3 : w2;
+  return w4;
+}
+
+int
+test_csneg32_condasn2(int w0,
+		      int w1,
+		      int w2,
+		      int w3) {
+  int w4;
+
+  /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*eq" } } */
+  w4 = (w0 == w1) ? w3 : -w2;
+  return w4;
+}
+
+long long
+test_csneg64_condasn1(long long x0,
+		      long long x1,
+		      long long x2,
+		      long long x3) {
+  long long x4;
+
+  /* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*ne" } } */
+  x4 = (x0 == x1) ? -x3 : x2;
+  return x4;
+}
+
+long long
+test_csneg64_condasn2(long long x0,
+		      long long x1,
+		      long long x2,
+		      long long x3) {
+  long long x4;
+
+  /* { dg-final { scan-assembler "csneg\tx\[0-9\]*.*eq" } } */
+  x4 = (x0 == x1) ? x3 : -x2;
+  return x4;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ctz.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ctz.c
new file mode 100644
index 000000000..89d6fb442
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ctz.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest (unsigned int x)
+{
+  return __builtin_ctz (x);
+}
+
+/* { dg-final { scan-assembler "rbit\tw" } } */
+/* { dg-final { scan-assembler "clz\tw" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/dwarf-cfa-reg.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/dwarf-cfa-reg.c
new file mode 100644
index 000000000..cce88155a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/dwarf-cfa-reg.c
@@ -0,0 +1,14 @@
+/* Verify that CFA register is restored to SP after FP is restored.  */
+/* { dg-do compile } */
+/* { dg-options "-O0 -gdwarf-2" } */
+/* { dg-final { scan-assembler ".cfi_restore 30" } } */
+/* { dg-final { scan-assembler ".cfi_restore 29" } } */
+/* { dg-final { scan-assembler ".cfi_def_cfa 31, 0" } } */
+/* { dg-final { scan-assembler "ret" } } */
+
+int bar (unsigned int);
+
+int foo (void)
+{
+  return bar (0xcafe);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extend.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extend.c
new file mode 100644
index 000000000..f399e55ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extend.c
@@ -0,0 +1,170 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+ldr_uxtw (int *arr, unsigned int i)
+{
+  /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw #?2]" } } */
+  return arr[i];
+}
+
+int
+ldr_uxtw0 (char *arr, unsigned int i)
+{
+  /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*uxtw]" } } */
+  return arr[i];
+}
+
+int
+ldr_sxtw (int *arr, int i)
+{
+  /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw #?2]" } } */
+  return arr[i];
+}
+
+int
+ldr_sxtw0 (char *arr, int i)
+{
+  /* { dg-final { scan-assembler "ldr\tw\[0-9\]+,.*sxtw]" } } */
+  return arr[i];
+}
+
+unsigned long long
+adddi_uxtw (unsigned long long a, unsigned int i)
+{
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*uxtw #?3" } } */
+  return a + ((unsigned long long)i << 3);
+}
+
+unsigned long long
+adddi_uxtw0 (unsigned long long a, unsigned int i)
+{
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*uxtw\n" } } */
+  return a + i;
+}
+
+long long
+adddi_sxtw (long long a, int i)
+{
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*sxtw #?3" } } */
+  return a + ((long long)i << 3);
+}
+
+long long
+adddi_sxtw0 (long long a, int i)
+{
+  /* { dg-final { scan-assembler "add\tx\[0-9\]+,.*sxtw\n" } } */
+  return a + i;
+}
+
+unsigned long long
+subdi_uxtw (unsigned long long a, unsigned int i)
+{
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxtw #?3" } } */
+  return a - ((unsigned long long)i << 3);
+}
+
+unsigned long long
+subdi_uxtw0 (unsigned long long a, unsigned int i)
+{
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxtw\n" } } */
+  return a - i;
+}
+
+long long
+subdi_sxtw (long long a, int i)
+{
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxtw #?3" } } */
+  return a - ((long long)i << 3);
+}
+
+long long
+subdi_sxtw0 (long long a, int i)
+{
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxtw\n" } } */
+  return a - (long long)i;
+}
+
+unsigned long long
+subdi_uxth (unsigned long long a, unsigned short i)
+{
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxth #?1" } } */
+  return a - ((unsigned long long)i << 1);
+}
+
+unsigned long long
+subdi_uxth0 (unsigned long long a, unsigned short i)
+{
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*uxth\n" } } */
+  return a - i;
+}
+
+long long
+subdi_sxth (long long a, short i)
+{
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxth #?1" } } */
+  return a - ((long long)i << 1);
+}
+
+long long
+subdi_sxth0 (long long a, short i)
+{
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+,.*sxth\n" } } */
+  return a - (long long)i;
+}
+
+unsigned int
+subsi_uxth (unsigned int a, unsigned short i)
+{
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*uxth #?1" } } */
+  return a - ((unsigned int)i << 1);
+}
+
+unsigned int
+subsi_uxth0 (unsigned int a, unsigned short i)
+{
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*uxth\n" } } */
+  return a - i;
+}
+
+int
+subsi_sxth (int a, short i)
+{
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*sxth #?1" } } */
+  return a - ((int)i << 1);
+}
+
+int
+subsi_sxth0 (int a, short i)
+{
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+,.*sxth\n" } } */
+  return a - (int)i;
+}
+
+unsigned int
+addsi_uxth (unsigned int a, unsigned short i)
+{
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*uxth #?1" } } */
+  return a + ((unsigned int)i << 1);
+}
+
+unsigned int
+addsi_uxth0 (unsigned int a, unsigned short i)
+{
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*uxth\n" } } */
+  return a + i;
+}
+
+int
+addsi_sxth (int a, short i)
+{
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*sxth #?1" } } */
+  return a + ((int)i << 1);
+}
+
+int
+addsi_sxth0 (int a, short i)
+{
+  /* { dg-final { scan-assembler "add\tw\[0-9\]+,.*sxth\n" } } */
+  return a + (int)i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extr.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extr.c
new file mode 100644
index 000000000..a78dd8d60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/extr.c
@@ -0,0 +1,34 @@
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-do run } */
+
+extern void abort (void);
+
+int
+test_si (int a, int b)
+{
+  /* { dg-final { scan-assembler "extr\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, 27\n" } } */
+  return (a << 5) | ((unsigned int) b >> 27);
+}
+
+long long
+test_di (long long a, long long b)
+{
+  /* { dg-final { scan-assembler "extr\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, 45\n" } } */
+  return (a << 19) | ((unsigned long long) b >> 45);
+}
+
+int
+main ()
+{
+  int v;
+  long long w;
+  v = test_si (0x00000004, 0x30000000);
+  if (v != 0x00000086)
+    abort();
+  w = test_di (0x0001040040040004ll, 0x0070050066666666ll);
+  if (w != 0x2002002000200380ll)
+    abort();
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fabd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fabd.c
new file mode 100644
index 000000000..7206d5e95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fabd.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -fno-inline --save-temps" } */
+
+extern double fabs (double);
+extern float fabsf (float);
+extern void abort ();
+extern void exit (int);
+
+void
+fabd_d (double x, double y, double d)
+{
+  if ((fabs (x - y) - d) > 0.00001)
+    abort ();
+}
+
+/* { dg-final { scan-assembler "fabd\td\[0-9\]+" } } */
+
+void
+fabd_f (float x, float y, float d)
+{
+  if ((fabsf (x - y) - d) > 0.00001)
+    abort ();
+}
+
+/* { dg-final { scan-assembler "fabd\ts\[0-9\]+" } } */
+
+int
+main ()
+{
+  fabd_d (10.0, 5.0, 5.0);
+  fabd_d (5.0, 10.0, 5.0);
+  fabd_f (10.0, 5.0, 5.0);
+  fabd_f (5.0, 10.0, 5.0);
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt.x
new file mode 100644
index 000000000..be50ee50f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt.x
@@ -0,0 +1,55 @@
+extern GPF SUFFIX(trunc) (GPF);
+extern GPF SUFFIX(ceil) (GPF);
+extern GPF SUFFIX(floor) (GPF);
+extern GPF SUFFIX(round) (GPF);
+
+GPI test1a (GPF x) {
+  return SUFFIX(__builtin_trunc)(x);
+}
+
+GPI test1b (GPF x)
+{
+  return SUFFIX(trunc)(x);
+}
+
+GPI test2a (GPF x)
+{
+  return SUFFIX(__builtin_lceil)(x);
+}
+
+GPI test2b (GPF x)
+{
+  return SUFFIX(ceil)(x);
+}
+
+GPI test2c (GPF x)
+{
+  return SUFFIX(__builtin_ceil)(x);
+}
+
+GPI test3a (GPF x)
+{
+  return SUFFIX(__builtin_lfloor)(x);
+}
+
+GPI test3b (GPF x)
+{
+  return SUFFIX(floor)(x);
+}
+
+GPI test3c (GPF x)
+{
+  return SUFFIX(__builtin_floor)(x);
+}
+
+GPI test4a (GPF x)
+{
+  return SUFFIX(__builtin_round)(x);
+}
+
+GPI test4b (GPF x)
+{
+  return SUFFIX(round)(x);
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
new file mode 100644
index 000000000..e5399099b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+#define GPI int
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
new file mode 100644
index 000000000..5eb36ff6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+#define GPI long
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
new file mode 100644
index 000000000..59be47512
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+#define GPI unsigned int
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
new file mode 100644
index 000000000..55723cf90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+#define GPI unsigned long
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
new file mode 100644
index 000000000..2e10e2dec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+#define GPI int
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
new file mode 100644
index 000000000..1debf710f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+#define GPI long
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
new file mode 100644
index 000000000..c0b0c693a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+#define GPI unsigned int
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
new file mode 100644
index 000000000..07309e2c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+#define GPI unsigned long
+
+#include "fcvt.x"
+
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ffs.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ffs.c
new file mode 100644
index 000000000..a3447619d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ffs.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned int functest(unsigned int x)
+{
+  return __builtin_ffs(x);
+}
+
+/* { dg-final { scan-assembler "cmp\tw" } } */
+/* { dg-final { scan-assembler "rbit\tw" } } */
+/* { dg-final { scan-assembler "clz\tw" } } */
+/* { dg-final { scan-assembler "csinc\tw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmadd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmadd.c
new file mode 100644
index 000000000..39975dbae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmadd.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern double fma (double, double, double);
+extern float fmaf (float, float, float);
+
+double test_fma1 (double x, double y, double z)
+{
+  return fma (x, y, z);
+}
+
+float test_fma2 (float x, float y, float z)
+{
+  return fmaf (x, y, z);
+}
+
+double test_fnma1 (double x, double y, double z)
+{
+  return fma (-x, y, z);
+}
+
+float test_fnma2 (float x, float y, float z)
+{
+  return fmaf (-x, y, z);
+}
+
+double test_fms1 (double x, double y, double z)
+{
+  return fma (x, y, -z);
+}
+
+float test_fms2 (float x, float y, float z)
+{
+  return fmaf (x, y, -z);
+}
+
+double test_fnms1 (double x, double y, double z)
+{
+  return fma (-x, y, -z);
+}
+
+float test_fnms2 (float x, float y, float z)
+{
+  return fmaf (-x, y, -z);
+}
+
+/* { dg-final { scan-assembler-times "fmadd\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fmadd\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fmsub\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fmsub\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmsub\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmsub\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmadd\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmadd\ts\[0-9\]" 1 } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
new file mode 100644
index 000000000..0bf1b86b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+#define DELTA 0.0001
+
+extern double fabs (double);
+
+extern void abort (void);
+
+#define TEST_VMLA(q1, q2, size, in1_lanes, in2_lanes)			\
+static void								\
+test_vfma##q1##_lane##q2##_f##size (float##size##_t * res,		\
+				   const float##size##_t *in1,		\
+				   const float##size##_t *in2)		\
+{									\
+  float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res);		\
+  float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1);		\
+  float##size##x##in2_lanes##_t c;					\
+  if (in2_lanes > 1)							\
+    {									\
+      c = vld1##q2##_f##size (in2);					\
+      a = vfma##q1##_lane##q2##_f##size (a, b, c, 1);			\
+    }									\
+  else									\
+    {									\
+      c = vld1##q2##_f##size (in2 + 1);					\
+      a = vfma##q1##_lane##q2##_f##size (a, b, c, 0);			\
+    }									\
+  vst1##q1##_f##size (res, a);						\
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes)		\
+TEST_VMLA ( ,  , width, n_half_lanes, n_half_lanes)		\
+TEST_VMLA (q,  , width, n_lanes, n_half_lanes)			\
+TEST_VMLA ( , q, width, n_half_lanes, n_lanes)			\
+TEST_VMLA (q, q, width, n_lanes, n_lanes)			\
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (64, 2, 1)
+
+#define POOL2 {0.0, 1.0}
+#define POOL4 {0.0, 1.0, 2.0, 3.0}
+#define EMPTY2 {0.0, 0.0}
+#define EMPTY4 {0.0, 0.0, 0.0, 0.0}
+
+#define BUILD_TEST(size, lanes)					\
+static void							\
+test_f##size (void)						\
+{								\
+  int i;							\
+  float##size##_t pool[lanes] = POOL##lanes;			\
+  float##size##_t res[lanes] = EMPTY##lanes;			\
+  float##size##_t res2[lanes] = EMPTY##lanes;			\
+  float##size##_t res3[lanes] = EMPTY##lanes;			\
+  float##size##_t res4[lanes] = EMPTY##lanes;			\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vfma_lane_f##size (res, pool, pool);			\
+  for (i = 0; i < lanes / 2; i++)				\
+    if (fabs (res[i] - pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vfmaq_lane_f##size (res2, pool, pool);			\
+  for (i = 0; i < lanes; i++)					\
+    if (fabs (res2[i] - pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vfma_laneq_f##size (res3, pool, pool);			\
+  for (i = 0; i < lanes / 2; i++)				\
+    if (fabs (res3[i] - pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vfmaq_laneq_f##size (res4, pool, pool);			\
+  for (i = 0; i < lanes; i++)					\
+    if (fabs (res4[i] - pool[i]) > DELTA)			\
+      abort ();							\
+}
+
+BUILD_TEST (32, 4)
+BUILD_TEST (64, 2)
+
+int
+main (int argc, char **argv)
+{
+  test_f32 ();
+  test_f64 ();
+  return 0;
+}
+
+/* vfma_laneq_f32.
+   vfma_lane_f32.  */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vfmaq_lane_f32.
+   vfmaq_laneq_f32.  */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vfma_lane_f64.  */
+/* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
+
+/* vfmaq_lane_f64.
+   vfma_laneq_f64.
+   vfmaq_laneq_f64.  */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
new file mode 100644
index 000000000..8cc2942f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
@@ -0,0 +1,117 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+#define DELTA 0.0001
+
+extern double fabs (double);
+
+extern void abort (void);
+
+#define TEST_VMLS(q1, q2, size, in1_lanes, in2_lanes)			\
+static void								\
+test_vfms##q1##_lane##q2##_f##size (float##size##_t * res,		\
+				   const float##size##_t *in1,		\
+				   const float##size##_t *in2)		\
+{									\
+  float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res);		\
+  float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1);		\
+  float##size##x##in2_lanes##_t c;					\
+  if (in2_lanes > 1)							\
+    {									\
+      c = vld1##q2##_f##size (in2);					\
+      a = vfms##q1##_lane##q2##_f##size (a, b, c, 1);			\
+    }									\
+  else									\
+    {									\
+      c = vld1##q2##_f##size (in2 + 1);					\
+      a = vfms##q1##_lane##q2##_f##size (a, b, c, 0);			\
+    }									\
+  vst1##q1##_f##size (res, a);						\
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes)		\
+TEST_VMLS ( ,  , width, n_half_lanes, n_half_lanes)		\
+TEST_VMLS (q,  , width, n_lanes, n_half_lanes)			\
+TEST_VMLS ( , q, width, n_half_lanes, n_lanes)			\
+TEST_VMLS (q, q, width, n_lanes, n_lanes)			\
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (64, 2, 1)
+
+#define POOL2 {0.0, 1.0}
+#define POOL4 {0.0, 1.0, 2.0, 3.0}
+#define EMPTY2 {0.0, 0.0}
+#define EMPTY4 {0.0, 0.0, 0.0, 0.0}
+
+#define BUILD_TEST(size, lanes)					\
+static void							\
+test_f##size (void)						\
+{								\
+  int i;							\
+  float##size##_t pool[lanes] = POOL##lanes;			\
+  float##size##_t res[lanes] = EMPTY##lanes;			\
+  float##size##_t res2[lanes] = EMPTY##lanes;			\
+  float##size##_t res3[lanes] = EMPTY##lanes;			\
+  float##size##_t res4[lanes] = EMPTY##lanes;			\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vfms_lane_f##size (res, pool, pool);			\
+  asm volatile ("" : :"Q" (res) : "memory");			\
+  for (i = 0; i < lanes / 2; i++)				\
+    if (fabs (res[i] + pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  test_vfmsq_lane_f##size (res2, pool, pool);			\
+  asm volatile ("" : :"Q" (res2) : "memory");			\
+  for (i = 0; i < lanes; i++)					\
+    if (fabs (res2[i] + pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  test_vfms_laneq_f##size (res3, pool, pool);			\
+  asm volatile ("" : :"Q" (res3) : "memory");			\
+  for (i = 0; i < lanes / 2; i++)				\
+    if (fabs (res3[i] + pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  test_vfmsq_laneq_f##size (res4, pool, pool);			\
+  asm volatile ("" : :"Q" (res4) : "memory");			\
+  for (i = 0; i < lanes; i++)					\
+    if (fabs (res4[i] + pool[i]) > DELTA)			\
+      abort ();							\
+}
+
+BUILD_TEST (32, 4)
+BUILD_TEST (64, 2)
+
+int
+main (int argc, char **argv)
+{
+  test_f32 ();
+  test_f64 ();
+  return 0;
+}
+
+/* vfms_laneq_f32.
+   vfms_lane_f32.  */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vfmsq_lane_f32.
+   vfmsq_laneq_f32.  */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vfms_lane_f64.  */
+/* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
+
+/* vfmsq_lane_f64.
+   vfms_laneq_f64.
+   vfmsq_laneq_f64.  */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c
new file mode 100644
index 000000000..7e4590afe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd-zero.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (double *output)
+{
+  *output = 0.0;
+}
+
+/* { dg-final { scan-assembler "fmov\\td\[0-9\]+, xzr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd.c
new file mode 100644
index 000000000..c50e74e3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovd.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (double *output)
+{
+  *output = 4.25;
+}
+
+/* { dg-final { scan-assembler "fmov\\td\[0-9\]+, 4\\.25" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c
new file mode 100644
index 000000000..5050ac310
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf-zero.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (float *output)
+{
+  *output = 0.0;
+}
+
+/* { dg-final { scan-assembler "fmov\\ts\[0-9\]+, wzr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf.c
new file mode 100644
index 000000000..0a9e21517
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmovf.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (float *output)
+{
+  *output = 4.25;
+}
+
+/* { dg-final { scan-assembler "fmov\\ts\[0-9\]+, 4\\.25" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c
new file mode 100644
index 000000000..f6e32f4bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+#define DELTA 0.0001
+extern void abort (void);
+extern double fabs (double);
+
+#define TEST_VMUL(q1, q2, size, in1_lanes, in2_lanes)			\
+static void								\
+test_vmul##q1##_lane##q2##_f##size (float##size##_t * res,		\
+				   const float##size##_t *in1,		\
+				   const float##size##_t *in2)		\
+{									\
+  float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res);		\
+  float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1);		\
+  float##size##x##in2_lanes##_t c;					\
+  if (in2_lanes > 1)							\
+    {									\
+      c = vld1##q2##_f##size (in2);					\
+      a = vmul##q1##_lane##q2##_f##size (b, c, 1);			\
+    }									\
+  else									\
+    {									\
+      c = vld1##q2##_f##size (in2 + 1);					\
+      a = vmul##q1##_lane##q2##_f##size (b, c, 0);			\
+    }									\
+  vst1##q1##_f##size (res, a);						\
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes)		\
+TEST_VMUL ( ,  , width, n_half_lanes, n_half_lanes)		\
+TEST_VMUL (q,  , width, n_lanes, n_half_lanes)			\
+TEST_VMUL ( , q, width, n_half_lanes, n_lanes)			\
+TEST_VMUL (q, q, width, n_lanes, n_lanes)
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (64, 2, 1)
+
+#define POOL2 {0.0, 1.0}
+#define POOL4 {0.0, 1.0, 2.0, 3.0}
+#define EMPTY2 {0.0, 0.0}
+#define EMPTY4 {0.0, 0.0, 0.0, 0.0}
+
+#define BUILD_TEST(size, lanes)					\
+static void							\
+test_f##size (void)						\
+{								\
+  int i;							\
+  float##size##_t pool[lanes] = POOL##lanes;			\
+  float##size##_t res[lanes] = EMPTY##lanes;			\
+  float##size##_t res2[lanes] = EMPTY##lanes;			\
+  float##size##_t res3[lanes] = EMPTY##lanes;			\
+  float##size##_t res4[lanes] = EMPTY##lanes;			\
+								\
+  /* Avoid constant folding the multiplication.  */		\
+  asm volatile ("" : : : "memory");				\
+  test_vmul_lane_f##size (res, pool, pool);			\
+  /* Avoid fusing multiplication and subtraction.  */		\
+  asm volatile ("" : :"Q" (res) : "memory");			\
+  for (i = 0; i < lanes / 2; i++)				\
+    if (fabs (res[i] - pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  test_vmulq_lane_f##size (res2, pool, pool);			\
+  /* Avoid fusing multiplication and subtraction.  */		\
+  asm volatile ("" : :"Q" (res2) : "memory");			\
+  for (i = 0; i < lanes; i++)					\
+    if (fabs (res2[i] - pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  test_vmul_laneq_f##size (res3, pool, pool);			\
+  /* Avoid fusing multiplication and subtraction.  */		\
+  asm volatile ("" : :"Q" (res3) : "memory");			\
+  for (i = 0; i < lanes / 2; i++)				\
+    if (fabs (res3[i] - pool[i]) > DELTA)			\
+      abort ();							\
+								\
+  test_vmulq_laneq_f##size (res4, pool, pool);			\
+  /* Avoid fusing multiplication and subtraction.  */		\
+  asm volatile ("" : :"Q" (res4) : "memory");			\
+  for (i = 0; i < lanes; i++)					\
+    if (fabs (res4[i] - pool[i]) > DELTA)			\
+      abort ();							\
+}
+
+BUILD_TEST (32, 4)
+BUILD_TEST (64, 2)
+
+int
+main (int argc, char **argv)
+{
+  test_f32 ();
+  test_f64 ();
+  return 0;
+}
+
+/* vmul_laneq_f32.
+   vmul_lane_f32.  */
+/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vmulq_lane_f32.
+   vmulq_laneq_f32.  */
+/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
+
+/* vmul_lane_f64.  */
+/* { dg-final { scan-assembler-times "fmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+/* vmul_laneq_f64.
+   vmulq_lane_f64.
+   vmulq_laneq_f64.  */
+/* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c
new file mode 100644
index 000000000..9c115df08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/fnmadd-fastmath.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+extern double fma (double, double, double);
+extern float fmaf (float, float, float);
+
+double test_fma1 (double x, double y, double z)
+{
+  return - fma (x, y, z);
+}
+
+float test_fma2 (float x, float y, float z)
+{
+  return - fmaf (x, y, z);
+}
+
+/* { dg-final { scan-assembler-times "fnmadd\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fnmadd\ts\[0-9\]" 1 } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint.x
new file mode 100644
index 000000000..140374068
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint.x
@@ -0,0 +1,66 @@
+extern GPF SUFFIX(trunc) (GPF);
+extern GPF SUFFIX(ceil) (GPF);
+extern GPF SUFFIX(floor) (GPF);
+extern GPF SUFFIX(nearbyint) (GPF);
+extern GPF SUFFIX(rint) (GPF);
+extern GPF SUFFIX(round) (GPF);
+
+GPF test1a (GPF x)
+{
+  return SUFFIX(__builtin_trunc)(x);
+}
+
+GPF test1b (GPF x)
+{
+  return SUFFIX(trunc)(x);
+}
+
+GPF test2a (GPF x)
+{
+  return SUFFIX(__builtin_ceil)(x);
+}
+
+GPF test2b (GPF x)
+{
+  return SUFFIX(ceil)(x);
+}
+
+GPF test3a (GPF x)
+{
+  return SUFFIX(__builtin_floor)(x);
+}
+
+GPF test3b (GPF x)
+{
+  return SUFFIX(floor)(x);
+}
+
+GPF test4a (GPF x)
+{
+  return SUFFIX(__builtin_nearbyint)(x);
+}
+
+GPF test4b (GPF x)
+{
+  return SUFFIX(nearbyint)(x);
+}
+
+GPF test5a (GPF x)
+{
+  return SUFFIX(__builtin_rint)(x);
+}
+
+GPF test5b (GPF x)
+{
+  return SUFFIX(rint)(x);
+}
+
+GPF test6a (GPF x)
+{
+  return SUFFIX(__builtin_round)(x);
+}
+
+GPF test6b (GPF x)
+{
+  return SUFFIX(round)(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_double.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_double.c
new file mode 100644
index 000000000..96139496c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_double.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF double
+#define SUFFIX(x) x
+
+#include "frint.x"
+
+/* { dg-final { scan-assembler-times "frintz\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintp\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintm\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frinti\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintx\td\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frinta\td\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_float.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_float.c
new file mode 100644
index 000000000..493ec37f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/frint_float.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define GPF float
+#define SUFFIX(x) x##f
+
+#include "frint.x"
+
+/* { dg-final { scan-assembler-times "frintz\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintp\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintm\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frinti\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frintx\ts\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "frinta\ts\[0-9\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/index.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/index.c
new file mode 100644
index 000000000..582771ba1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/index.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\[us\]xtw\t" } } */
+/* { dg-final { scan-assembler-not "\[us\]bfiz\t" } } */
+/* { dg-final { scan-assembler-not "lsl\t" } } */
+
+int
+load_scaled_sxtw (int *arr, int i)
+{
+  return arr[arr[i]];
+}
+
+unsigned int
+load_scaled_uxtw (unsigned int *arr, unsigned int i)
+{
+  return arr[arr[i]];
+}
+
+void
+store_scaled_sxtw (int *arr, int i)
+{
+  arr[arr[i]] = 0;
+}
+
+void
+store_scaled_uxtw (unsigned int *arr, unsigned int i)
+{
+  arr[arr[i]] = 0;
+}
+
+int
+load_unscaled_sxtw (signed char *arr, int i)
+{
+  return arr[arr[i]];
+}
+
+unsigned int
+load_unscaled_uxtw (unsigned char *arr, unsigned int i)
+{
+  return arr[arr[i]];
+}
+
+void
+store_unscaled_sxtw (signed char *arr, int i)
+{
+  arr[arr[i]] = 0;
+}
+
+void
+store_unscaled_uxtw (unsigned char *arr, unsigned int i)
+{
+  arr[arr[i]] = 0;
+}
+
+
+
+int
+load_scaled_tmp_sxtw (int *arr, int i)
+{
+  int j = arr[i];
+  return arr[j];
+}
+
+unsigned int
+load_scaled_tmp_uxtw (unsigned int *arr, unsigned int i)
+{
+  unsigned int j = arr[i];
+  return arr[j];
+}
+
+void
+store_scaled_tmp_sxtw (int *arr, int i)
+{
+  int j = arr[i];
+  arr[j] = 0;
+}
+
+void
+store_scaled_tmp_uxtw (unsigned int *arr, unsigned int i)
+{
+  unsigned int j = arr[i];
+  arr[j] = 0;
+}
+
+int
+load_unscaled_tmp_sxtw (signed char *arr, int i)
+{
+  signed char j = arr[i];
+  return arr[j];
+}
+
+unsigned int
+load_unscaled_tmp_uxtw (unsigned char *arr, unsigned int i)
+{
+  unsigned char j = arr[i];
+  return arr[j];
+}
+
+void
+store_unscaled_tmp_sxtw (signed char *arr, int i)
+{
+  signed char j = arr[i];
+  arr[j] = 0;
+}
+
+void
+store_unscaled_tmp_uxtw (unsigned char *arr, unsigned int i)
+{
+  unsigned char j = arr[i];
+  arr[j] = 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_1.c
new file mode 100644
index 000000000..6e3c7f0e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_1.c
@@ -0,0 +1,85 @@
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+/* { dg-require-effective-target aarch64_little_endian } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+  unsigned short eight: 8;
+  unsigned short four: 4;
+  unsigned short five: 5;
+  unsigned short seven: 7;
+  unsigned int sixteen: 16;
+} bitfield;
+
+bitfield
+bfi1 (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 0, 8" } } */
+  a.eight = 3;
+  return a;
+}
+
+bitfield
+bfi2 (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 16, 5" } } */
+  a.five = 7;
+  return a;
+}
+
+bitfield
+movk (bitfield a)
+{
+  /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 32" } } */
+  a.sixteen = 7531;
+  return a;
+}
+
+bitfield
+set1 (bitfield a)
+{
+  /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 2031616" } } */
+  a.five = 0x1f;
+  return a;
+}
+
+bitfield
+set0 (bitfield a)
+{
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -2031617" } } */
+  a.five = 0;
+  return a;
+}
+
+
+int
+main (int argc, char** argv)
+{
+  static bitfield a;
+  bitfield b = bfi1 (a);
+  bitfield c = bfi2 (b);
+  bitfield d = movk (c);
+
+  if (d.eight != 3)
+    abort ();
+
+  if (d.five != 7)
+    abort ();
+
+  if (d.sixteen != 7531)
+    abort ();
+
+  d = set1 (d);
+  if (d.five != 0x1f)
+    abort ();
+
+  d = set0 (d);
+  if (d.five != 0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_2.c
new file mode 100644
index 000000000..a7691a32f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/insv_2.c
@@ -0,0 +1,85 @@
+/* { dg-do run { target aarch64*-*-* } } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+/* { dg-require-effective-target aarch64_big_endian } */
+
+extern void abort (void);
+
+typedef struct bitfield
+{
+  unsigned short eight: 8;
+  unsigned short four: 4;
+  unsigned short five: 5;
+  unsigned short seven: 7;
+  unsigned int sixteen: 16;
+} bitfield;
+
+bitfield
+bfi1 (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 56, 8" } } */
+  a.eight = 3;
+  return a;
+}
+
+bitfield
+bfi2 (bitfield a)
+{
+  /* { dg-final { scan-assembler "bfi\tx\[0-9\]+, x\[0-9\]+, 43, 5" } } */
+  a.five = 7;
+  return a;
+}
+
+bitfield
+movk (bitfield a)
+{
+  /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x1d6b, lsl 16" } } */
+  a.sixteen = 7531;
+  return a;
+}
+
+bitfield
+set1 (bitfield a)
+{
+  /* { dg-final { scan-assembler "orr\tx\[0-9\]+, x\[0-9\]+, 272678883688448" } } */
+  a.five = 0x1f;
+  return a;
+}
+
+bitfield
+set0 (bitfield a)
+{
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -272678883688449" } } */
+  a.five = 0;
+  return a;
+}
+
+
+int
+main (int argc, char** argv)
+{
+  static bitfield a;
+  bitfield b = bfi1 (a);
+  bitfield c = bfi2 (b);
+  bitfield d = movk (c);
+
+  if (d.eight != 3)
+    abort ();
+
+  if (d.five != 7)
+    abort ();
+
+  if (d.sixteen != 7531)
+    abort ();
+
+  d = set1 (d);
+  if (d.five != 0x1f)
+    abort ();
+
+  d = set0 (d);
+  if (d.five != 0)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
new file mode 100644
index 000000000..fce413873
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define MAPs(size, xx) int##size##xx##_t
+#define MAPu(size, xx) uint##size##xx##_t
+
+
+#define TEST_VMLA(q, su, size, in1_lanes, in2_lanes)		\
+static void							\
+test_vmlaq_lane##q##_##su##size (MAP##su (size, ) * res,	\
+				 const MAP##su(size, ) *in1,	\
+				 const MAP##su(size, ) *in2)	\
+{								\
+  MAP##su (size, x##in1_lanes) a = vld1q_##su##size (res);	\
+  MAP##su (size, x##in1_lanes) b = vld1q_##su##size (in1);	\
+  MAP##su (size, x##in2_lanes) c = vld1##q##_##su##size (in2);	\
+  a = vmlaq_lane##q##_##su##size (a, b, c, 1);			\
+  vst1q_##su##size (res, a);					\
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes)		\
+TEST_VMLA (, s, width, n_lanes, n_half_lanes)			\
+TEST_VMLA (q, s, width, n_lanes, n_lanes)			\
+TEST_VMLA (, u, width, n_lanes, n_half_lanes)			\
+TEST_VMLA (q, u, width, n_lanes, n_lanes)			\
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (16, 8, 4)
+
+#define POOL4 {0, 1, 2, 3}
+#define POOL8 {0, 1, 2, 3, 4, 5, 6, 7}
+#define EMPTY4 {0, 0, 0, 0}
+#define EMPTY8 {0, 0, 0, 0, 0, 0, 0, 0}
+
+#define BUILD_TEST(su, size, lanes)				\
+static void							\
+test_##su##size (void)						\
+{								\
+  int i;							\
+  MAP##su (size,) pool[lanes] = POOL##lanes;			\
+  MAP##su (size,) res[lanes] = EMPTY##lanes;			\
+  MAP##su (size,) res2[lanes] = EMPTY##lanes;			\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vmlaq_lane_##su##size (res, pool, pool);			\
+  for (i = 0; i < lanes; i++)					\
+    if (res[i] != pool[i])					\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vmlaq_laneq_##su##size (res2, pool, pool);		\
+  for (i = 0; i < lanes; i++)					\
+    if (res2[i] != pool[i])					\
+      abort ();							\
+}
+
+#undef BUILD_VARS
+#define BUILD_VARS(size, lanes)					\
+BUILD_TEST (s, size, lanes)					\
+BUILD_TEST (u, size, lanes)
+
+BUILD_VARS (32, 4)
+BUILD_VARS (16, 8)
+
+int
+main (int argc, char **argv)
+{
+  test_s32 ();
+  test_u32 ();
+  test_s16 ();
+  test_u16 ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
new file mode 100644
index 000000000..8bf95b641
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
@@ -0,0 +1,89 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define MAPs(size, xx) int##size##xx##_t
+#define MAPu(size, xx) uint##size##xx##_t
+
+
+#define TEST_VMLS(q, su, size, in1_lanes, in2_lanes)		\
+static void							\
+test_vmlsq_lane##q##_##su##size (MAP##su (size, ) * res,	\
+				 const MAP##su(size, ) *in1,	\
+				 const MAP##su(size, ) *in2)	\
+{								\
+  MAP##su (size, x##in1_lanes) a = vld1q_##su##size (res);	\
+  MAP##su (size, x##in1_lanes) b = vld1q_##su##size (in1);	\
+  MAP##su (size, x##in2_lanes) c = vld1##q##_##su##size (in2);	\
+  a = vmlsq_lane##q##_##su##size (a, b, c, 1);			\
+  vst1q_##su##size (res, a);					\
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes)		\
+TEST_VMLS (, s, width, n_lanes, n_half_lanes)			\
+TEST_VMLS (q, s, width, n_lanes, n_lanes)			\
+TEST_VMLS (, u, width, n_lanes, n_half_lanes)			\
+TEST_VMLS (q, u, width, n_lanes, n_lanes)			\
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (16, 8, 4)
+
+#define MAP_OPs +
+#define MAP_OPu -
+
+#define POOL4 {0, 1, 2, 3}
+#define POOL8 {0, 1, 2, 3, 4, 5, 6, 7}
+#define EMPTY4s {0, 0, 0, 0}
+#define EMPTY8s {0, 0, 0, 0, 0, 0, 0, 0}
+#define EMPTY4u {0, 2, 4, 6}
+#define EMPTY8u {0, 2, 4, 6, 8, 10, 12, 14}
+
+#define BUILD_TEST(su, size, lanes)				\
+static void							\
+test_##su##size (void)						\
+{								\
+  int i;							\
+  MAP##su (size,) pool[lanes] = POOL##lanes;			\
+  MAP##su (size,) res[lanes] = EMPTY##lanes##su;		\
+  MAP##su (size,) res2[lanes] = EMPTY##lanes##su;		\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vmlsq_lane_##su##size (res, pool, pool);			\
+  for (i = 0; i < lanes; i++)					\
+    if (res[i] MAP_OP##su pool[i] != 0)				\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vmlsq_laneq_##su##size (res2, pool, pool);		\
+  for (i = 0; i < lanes; i++)					\
+    if (res2[i] MAP_OP##su pool[i] != 0)			\
+      abort ();							\
+}
+
+#undef BUILD_VARS
+#define BUILD_VARS(size, lanes)					\
+BUILD_TEST (s, size, lanes)					\
+BUILD_TEST (u, size, lanes)
+
+BUILD_VARS (32, 4)
+BUILD_VARS (16, 8)
+
+int
+main (int argc, char **argv)
+{
+  test_s32 ();
+  test_u32 ();
+  test_s16 ();
+  test_u16 ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-1.c
new file mode 100644
index 000000000..618854a6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int r;
+
+void test (int a, int b)
+{
+  /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+  r = (-a) * b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-2.c
new file mode 100644
index 000000000..25f817b9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int r;
+
+void test (int a, int b)
+{
+  /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+  r = a * (-b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-3.c
new file mode 100644
index 000000000..d9a135465
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mneg-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int r;
+
+void test (int a, int b)
+{
+  /* { dg-final { scan-assembler "mneg\tw\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+  r = - (a * b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-1.c
new file mode 100644
index 000000000..b45debbc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long long r;
+
+void test_signed (int a, int b)
+{
+  /* { dg-final { scan-assembler "smnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+  r = (-((long long) a)) * ((long long) b);
+}
+
+void test_unsigned (unsigned int a, unsigned int b)
+{
+  /* { dg-final { scan-assembler "umnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+  r = (-((long long) a)) * ((long long) b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-2.c
new file mode 100644
index 000000000..1c5dc7581
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mnegl-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long long r;
+
+void test_signed (int a, int b)
+{
+  /* { dg-final { scan-assembler "smnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+  r = ((long long) a) * (-((long long) b));
+}
+
+void test_unsigned (unsigned int a, unsigned int b)
+{
+  /* { dg-final { scan-assembler "umnegl\tx\[0-9\]*, w\[0-9\]*, w\[0-9\]*\n" } } */
+  r = ((long long) a) * (-((long long) b));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movdi_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movdi_1.c
new file mode 100644
index 000000000..a22378db0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movdi_1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-inline" } */
+
+#include <arm_neon.h>
+
+void
+foo1 (uint64_t *a)
+{
+  uint64x1_t val18;
+  uint32x2_t val19;
+  uint64x1_t val20;
+  val19 = vcreate_u32 (0x800000004cf3dffbUL);
+  val20 = vrsra_n_u64 (val18, vreinterpret_u64_u32 (val19), 34);
+  vst1_u64 (a, val20);
+}
+
+void
+foo2 (uint64_t *a)
+{
+  uint64x1_t val18;
+  uint32x2_t val19;
+  uint64x1_t val20;
+  val19 = vcreate_u32 (0xdffbUL);
+  val20 = vrsra_n_u64 (val18, vreinterpret_u64_u32 (val19), 34);
+  vst1_u64 (a, val20);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movi_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movi_1.c
new file mode 100644
index 000000000..e2842b39e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movi_1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+dummy (short* b)
+{
+  /* { dg-final { scan-assembler "movi\tv\[0-9\]+\.4h, 0x4, lsl 8" } } */
+  /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 0x400" } } */
+  /* { dg-final { scan-assembler-not "movi\tv\[0-9\]+\.4h, 1024" } } */
+  register short x asm ("h8") = 1024;
+  asm volatile ("" : : "w" (x));
+  *b = x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movk.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movk.c
new file mode 100644
index 000000000..e4b22098c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/movk.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+long long int
+dummy_number_generator ()
+{
+  /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xefff, lsl 16" } } */
+  /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xc4cc, lsl 32" } } */
+  /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0xfffe, lsl 48" } } */
+  return -346565474575675;
+}
+
+int
+main (void)
+{
+
+  long long int num = dummy_number_generator ();
+  if (num > 0)
+    abort ();
+
+  /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x4667, lsl 16" } } */
+  /* { dg-final { scan-assembler "movk\tx\[0-9\]+, 0x7a3d, lsl 32" } } */
+  if (num / 69313094915135 != -5)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mul_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mul_intrinsic_1.c
new file mode 100644
index 000000000..dabe10e15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/mul_intrinsic_1.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define MAPs(size, xx) int##size##xx##_t
+#define MAPu(size, xx) uint##size##xx##_t
+
+
+#define TEST_VMUL(q, su, size, in1_lanes, in2_lanes)		\
+static void							\
+test_vmulq_lane##q##_##su##size (MAP##su (size, ) * res,	\
+				 const MAP##su(size, ) *in1,	\
+				 const MAP##su(size, ) *in2)	\
+{								\
+  MAP##su (size, x##in1_lanes) a = vld1q_##su##size (in1);	\
+  MAP##su (size, x##in2_lanes) b = vld1##q##_##su##size (in2);	\
+  a = vmulq_lane##q##_##su##size (a, b, 1);			\
+  vst1q_##su##size (res, a);					\
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes)		\
+TEST_VMUL (, s, width, n_lanes, n_half_lanes)			\
+TEST_VMUL (q, s, width, n_lanes, n_lanes)			\
+TEST_VMUL (, u, width, n_lanes, n_half_lanes)			\
+TEST_VMUL (q, u, width, n_lanes, n_lanes)			\
+
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (16, 8, 4)
+
+#define POOL4 {0, 1, 2, 3}
+#define POOL8 {0, 1, 2, 3, 4, 5, 6, 7}
+#define EMPTY4 {0, 0, 0, 0}
+#define EMPTY8 {0, 0, 0, 0, 0, 0, 0, 0}
+
+#define BUILD_TEST(su, size, lanes)				\
+static void							\
+test_##su##size (void)						\
+{								\
+  int i;							\
+  MAP##su (size,) pool[lanes] = POOL##lanes;			\
+  MAP##su (size,) res[lanes] = EMPTY##lanes;			\
+  MAP##su (size,) res2[lanes] = EMPTY##lanes;			\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vmulq_lane_##su##size (res, pool, pool);			\
+  for (i = 0; i < lanes; i++)					\
+    if (res[i] != pool[i])					\
+      abort ();							\
+								\
+  /* Forecfully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vmulq_laneq_##su##size (res2, pool, pool);		\
+  for (i = 0; i < lanes; i++)					\
+    if (res2[i] != pool[i])					\
+      abort ();							\
+}
+
+#undef BUILD_VARS
+#define BUILD_VARS(size, lanes)					\
+BUILD_TEST (s, size, lanes)					\
+BUILD_TEST (u, size, lanes)
+
+BUILD_VARS (32, 4)
+BUILD_VARS (16, 8)
+
+int
+main (int argc, char **argv)
+{
+  test_s32 ();
+  test_u32 ();
+  test_s16 ();
+  test_u16 ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "mul\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mul\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c
new file mode 100644
index 000000000..0f23cc9c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/narrow_high-intrinsics.c
@@ -0,0 +1,125 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+#define TWO(name, rettype, rmwtype, intype, fs) \
+  rettype test_ ## name ## _ ## fs \
+		(rmwtype a, intype b, intype c) \
+	{ \
+		return name ## _ ## fs (a, b, c); \
+	}
+
+TWO (vsubhn_high, int8x16_t, int8x8_t, int16x8_t,  s16)
+TWO (vsubhn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+TWO (vsubhn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+TWO (vsubhn_high, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+TWO (vsubhn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWO (vsubhn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWO (vaddhn_high, int8x16_t, int8x8_t, int16x8_t,  s16)
+TWO (vaddhn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+TWO (vaddhn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+TWO (vaddhn_high, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+TWO (vaddhn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWO (vaddhn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWO (vrsubhn_high, int8x16_t, int8x8_t, int16x8_t,  s16)
+TWO (vrsubhn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+TWO (vrsubhn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+TWO (vrsubhn_high, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+TWO (vrsubhn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWO (vrsubhn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWO (vraddhn_high, int8x16_t, int8x8_t, int16x8_t,  s16)
+TWO (vraddhn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+TWO (vraddhn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+TWO (vraddhn_high, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+TWO (vraddhn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWO (vraddhn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+#define TWOn(name, rettype, rmwtype, intype, fs) \
+  rettype test_ ## name ## _ ## fs \
+		(rmwtype a, intype b) \
+	{ \
+		return name ## _ ## fs (a, b, 4); \
+	}
+
+TWOn (vrshrn_high_n, int8x16_t, int8x8_t, int16x8_t,  s16)
+TWOn (vrshrn_high_n, int16x8_t, int16x4_t, int32x4_t, s32)
+TWOn (vrshrn_high_n, int32x4_t, int32x2_t, int64x2_t, s64)
+TWOn (vrshrn_high_n, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+TWOn (vrshrn_high_n, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWOn (vrshrn_high_n, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWOn (vshrn_high_n, int8x16_t, int8x8_t, int16x8_t,  s16)
+TWOn (vshrn_high_n, int16x8_t, int16x4_t, int32x4_t, s32)
+TWOn (vshrn_high_n, int32x4_t, int32x2_t, int64x2_t, s64)
+TWOn (vshrn_high_n, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+TWOn (vshrn_high_n, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWOn (vshrn_high_n, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWOn (vqshrun_high_n, uint8x16_t, uint8x8_t, int16x8_t,  s16)
+TWOn (vqshrun_high_n, uint16x8_t, uint16x4_t, int32x4_t, s32)
+TWOn (vqshrun_high_n, uint32x4_t, uint32x2_t, int64x2_t, s64)
+
+TWOn (vqrshrun_high_n, uint8x16_t, uint8x8_t, int16x8_t,  s16)
+TWOn (vqrshrun_high_n, uint16x8_t, uint16x4_t, int32x4_t, s32)
+TWOn (vqrshrun_high_n, uint32x4_t, uint32x2_t, int64x2_t, s64)
+
+TWOn (vqshrn_high_n, int8x16_t, int8x8_t, int16x8_t,  s16)
+TWOn (vqshrn_high_n, int16x8_t, int16x4_t, int32x4_t, s32)
+TWOn (vqshrn_high_n, int32x4_t, int32x2_t, int64x2_t, s64)
+TWOn (vqshrn_high_n, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+TWOn (vqshrn_high_n, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWOn (vqshrn_high_n, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+TWOn (vqrshrn_high_n, int8x16_t, int8x8_t, int16x8_t,  s16)
+TWOn (vqrshrn_high_n, int16x8_t, int16x4_t, int32x4_t, s32)
+TWOn (vqrshrn_high_n, int32x4_t, int32x2_t, int64x2_t, s64)
+TWOn (vqrshrn_high_n, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+TWOn (vqrshrn_high_n, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+TWOn (vqrshrn_high_n, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+#define ONE(name, rettype, rmwtype, intype, fs) \
+  rettype test_ ## name ## _ ## fs \
+		(rmwtype a, intype b) \
+	{ \
+		return name ## _ ## fs (a, b); \
+	}
+
+ONE (vqmovn_high, int8x16_t, int8x8_t, int16x8_t,  s16)
+ONE (vqmovn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+ONE (vqmovn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+ONE (vqmovn_high, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+ONE (vqmovn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+ONE (vqmovn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+ONE (vqmovun_high, uint8x16_t, uint8x8_t, int16x8_t,  s16)
+ONE (vqmovun_high, uint16x8_t, uint16x4_t, int32x4_t, s32)
+ONE (vqmovun_high, uint32x4_t, uint32x2_t, int64x2_t, s64)
+
+ONE (vmovn_high, int8x16_t, int8x8_t, int16x8_t,  s16)
+ONE (vmovn_high, int16x8_t, int16x4_t, int32x4_t, s32)
+ONE (vmovn_high, int32x4_t, int32x2_t, int64x2_t, s64)
+ONE (vmovn_high, uint8x16_t, uint8x8_t, uint16x8_t,  u16)
+ONE (vmovn_high, uint16x8_t, uint16x4_t, uint32x4_t, u32)
+ONE (vmovn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
+
+
+/* { dg-final { scan-assembler-times "\\tsubhn2 v" 6} }  */
+/* { dg-final { scan-assembler-times "\\taddhn2\\tv" 6} }  */
+/* { dg-final { scan-assembler-times "rsubhn2 v" 6} }  */
+/* { dg-final { scan-assembler-times "raddhn2\\tv" 6} }  */
+/* { dg-final { scan-assembler-times "\\trshrn2 v" 6} }  */
+/* { dg-final { scan-assembler-times "\\tshrn2 v" 6} }  */
+/* { dg-final { scan-assembler-times "sqshrun2 v" 3} }  */
+/* { dg-final { scan-assembler-times "sqrshrun2 v" 3} }  */
+/* { dg-final { scan-assembler-times "sqshrn2 v" 3} }  */
+/* { dg-final { scan-assembler-times "uqshrn2 v" 3} }  */
+/* { dg-final { scan-assembler-times "sqrshrn2 v" 3} }  */
+/* { dg-final { scan-assembler-times "uqrshrn2 v" 3} }  */
+/* { dg-final { scan-assembler-times "uqxtn2 v" 3} }  */
+/* { dg-final { scan-assembler-times "sqxtn2 v" 3} }  */
+/* { dg-final { scan-assembler-times "sqxtun2 v" 3} }  */
+/* { dg-final { scan-assembler-times "\\txtn2 v" 6} }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/neg_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/neg_1.c
new file mode 100644
index 000000000..04b0fdd23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/neg_1.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline --save-temps" } */
+
+extern void abort (void);
+
+long long
+neg64 (long long a)
+{
+  /* { dg-final { scan-assembler "neg\tx\[0-9\]+" } } */
+  return 0 - a;
+}
+
+long long
+neg64_in_dreg (long long a)
+{
+  /* { dg-final { scan-assembler "neg\td\[0-9\]+, d\[0-9\]+" } } */
+  register long long x asm ("d8") = a;
+  register long long y asm ("d9");
+  asm volatile ("" : : "w" (x));
+  y = 0 - x;
+  asm volatile ("" : : "w" (y));
+  return y;
+}
+
+int
+neg32 (int a)
+{
+  /* { dg-final { scan-assembler "neg\tw\[0-9\]+" } } */
+  return 0 - a;
+}
+
+int
+neg32_in_sreg (int a)
+{
+  /* { dg-final { scan-assembler "neg\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+  register int x asm ("s8") = a;
+  register int y asm ("s9");
+  asm volatile ("" : : "w" (x));
+  y = 0 - x;
+  asm volatile ("" : : "w" (y));
+  return y;
+}
+
+int
+main (void)
+{
+  long long a;
+  int b;
+  a = 61;
+  b = 313;
+
+  if (neg64 (a) != -61)
+    abort ();
+
+  if (neg64_in_dreg (a) != -61)
+    abort ();
+
+  if (neg32 (b) != -313)
+    abort ();
+
+  if (neg32_in_sreg (b) != -313)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/negs.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/negs.c
new file mode 100644
index 000000000..1c23041ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/negs.c
@@ -0,0 +1,108 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+int z;
+
+int
+negs_si_test1 (int a, int b, int c)
+{
+  int d = -b;
+
+  /* { dg-final { scan-assembler "negs\tw\[0-9\]+, w\[0-9\]+" } } */
+  if (d < 0)
+    return a + c;
+
+  z = d;
+    return b + c + d;
+}
+
+int
+negs_si_test3 (int a, int b, int c)
+{
+  int d = -(b) << 3;
+
+  /* { dg-final { scan-assembler "negs\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+
+  z = d;
+    return b + c + d;
+}
+
+typedef long long s64;
+s64 zz;
+
+s64
+negs_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = -b;
+
+  /* { dg-final { scan-assembler "negs\tx\[0-9\]+, x\[0-9\]+" } } */
+  if (d < 0)
+    return a + c;
+
+  zz = d;
+    return b + c + d;
+}
+
+s64
+negs_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = -(b) << 3;
+
+  /* { dg-final { scan-assembler "negs\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+
+  zz = d;
+    return b + c + d;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = negs_si_test1 (2, 12, 5);
+  if (x != 7)
+    abort ();
+
+  x = negs_si_test1 (1, 2, 32);
+  if (x != 33)
+    abort ();
+
+  x = negs_si_test3 (13, 14, 5);
+  if (x != -93)
+    abort ();
+
+  x = negs_si_test3 (15, 21, 2);
+  if (x != -145)
+    abort ();
+
+  y = negs_di_test1 (0x20202020ll,
+		     0x65161611ll,
+		     0x42434243ll);
+  if (y != 0x62636263ll)
+    abort ();
+
+  y = negs_di_test1 (0x1010101010101ll,
+		     0x123456789abcdll,
+		     0x5555555555555ll);
+  if (y != 0x6565656565656ll)
+    abort ();
+
+  y = negs_di_test3 (0x62523781ll,
+		     0x64234978ll,
+		     0x12345123ll);
+  if (y != 0xfffffffd553d4edbll)
+    abort ();
+
+  y = negs_di_test3 (0x763526268ll,
+		     0x101010101ll,
+		     0x222222222ll);
+  if (y != 0xfffffffb1b1b1b1bll)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ngc.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ngc.c
new file mode 100644
index 000000000..336432160
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ngc.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+typedef unsigned int u32;
+
+u32
+ngc_si (u32 a, u32 b, u32 c, u32 d)
+{
+  a = -b - (c < d);
+  return a;
+}
+
+typedef unsigned long long u64;
+
+u64
+ngc_si_tst (u64 a, u32 b, u32 c, u32 d)
+{
+  a = -b - (c < d);
+  return a;
+}
+
+u64
+ngc_di (u64 a, u64 b, u64 c, u64 d)
+{
+  a = -b - (c < d);
+  return a;
+}
+
+int
+main ()
+{
+  int x;
+  u64 y;
+
+  x = ngc_si (29, 4, 5, 4);
+  if (x != -4)
+    abort ();
+
+  x = ngc_si (1024, 2, 20, 13);
+  if (x != -2)
+    abort ();
+
+  y = ngc_si_tst (0x130000029ll, 32, 50, 12);
+  if (y != 0xffffffe0)
+    abort ();
+
+  y = ngc_si_tst (0x5000500050005ll, 21, 2, 14);
+  if (y != 0xffffffea)
+    abort ();
+
+  y = ngc_di (0x130000029ll, 0x320000004ll, 0x505050505ll, 0x123123123ll);
+  if (y != 0xfffffffcdffffffc)
+    abort ();
+
+  y = ngc_di (0x5000500050005ll,
+	      0x2111211121112ll, 0x0000000002020ll, 0x1414575046477ll);
+  if (y != 0xfffdeeedeeedeeed)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "ngc\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler-times "ngc\tx\[0-9\]+, x\[0-9\]+" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c
new file mode 100644
index 000000000..3109d9d4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-constantpool1.c
@@ -0,0 +1,30 @@
+/* { dg-options "-O2 -mcmodel=small -fPIC" }  */
+/* { dg-do compile } */
+
+extern int __finite (double __value) __attribute__ ((__nothrow__)) __attribute__ ((__const__));
+int
+__ecvt_r (value, ndigit, decpt, sign, buf, len)
+     double value;
+     int ndigit, *decpt, *sign;
+     char *buf;
+{
+  if ((sizeof (value) == sizeof (float) ? __finitef (value) : __finite (value)) && value != 0.0)
+    {
+      double d;
+      double f = 1.0;
+      d = -value;
+      if (d < 1.0e-307)
+	{
+	  do
+	    {
+	      f *= 10.0;
+	    }
+	  while (d * f < 1.0);
+	}
+    }
+  if (ndigit <= 0 && len > 0)
+    {
+      buf[0] = '\0';
+      *sign = (sizeof (value) == sizeof (float) ? __finitef (value) : __finite (value)) ? (sizeof (value) == sizeof (float) ? __signbitf (value) : __signbit (value)) != 0 : 0;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c
new file mode 100644
index 000000000..f277a5285
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pic-symrefplus.c
@@ -0,0 +1,128 @@
+/* { dg-options "-O2 -mcmodel=small -fPIC -fno-builtin" }  */
+/* { dg-do compile } */
+
+typedef long unsigned int size_t;
+enum
+{
+  __LC_TIME = 2,
+};
+enum
+{
+  ABDAY_1 = (((__LC_TIME) << 16) | (0)),
+  DAY_1,
+  ABMON_1,
+  MON_1,
+  D_T_FMT,
+};
+typedef struct __locale_struct
+{
+  struct locale_data *__locales[13];
+} *__locale_t;
+struct tm
+{
+  int tm_sec;
+  int tm_min;
+  int tm_hour;
+};
+struct locale_data
+{
+  const char *name;
+  struct
+  {
+    const char *string;
+  }
+  values [];
+};
+extern const struct locale_data _nl_C_LC_TIME __attribute__ ((visibility ("hidden")));
+char *
+__strptime_internal (rp, fmt, tmp, statep , locale)
+     const char *rp;
+     const char *fmt;
+     __locale_t locale;
+     void *statep;
+{
+  struct locale_data *const current = locale->__locales[__LC_TIME];
+  const char *rp_backup;
+  const char *rp_longest;
+  int cnt;
+  size_t val;
+  enum ptime_locale_status { not, loc, raw } decided_longest;
+  struct __strptime_state
+  {
+    enum ptime_locale_status decided : 2;
+  } s;
+  struct tm tmb;
+  struct tm *tm;
+  if (statep == ((void *)0))
+    {
+      memset (&s, 0, sizeof (s));
+    }
+    {
+      tm = &tmb;
+    }
+  while (*fmt != '\0')
+    {
+      if (*fmt != '%')
+ {
+   if (*fmt++ != *rp++) return ((void *)0);
+   continue;
+ }
+      if (statep != ((void *)0))
+ {
+     ++fmt;
+ }
+      rp_backup = rp;
+      switch (*fmt++)
+ {
+ case '%':
+   for (cnt = 0; cnt < 7; ++cnt)
+     {
+       const char *trp;
+       if (s.decided !=raw)
+  {
+    if (({ size_t len = strlen ((current->values[((int) (DAY_1 + cnt) & 0xffff)].string)); int result = __strncasecmp_l (((current->values[((int) (DAY_1 + cnt) & 0xffff)].string)), (trp), len, locale) == 0; if (result) (trp) += len; result; })
+        && trp > rp_longest)
+      {
+      }
+    if (({ size_t len = strlen ((current->values[((int) (ABDAY_1 + cnt) & 0xffff)].string)); int result = __strncasecmp_l (((current->values[((int) (ABDAY_1 + cnt) & 0xffff)].string)), (trp), len, locale) == 0; if (result) (trp) += len; result; })
+        && trp > rp_longest)
+      {
+      }
+  }
+       if (s.decided != loc
+    && (((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (DAY_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (DAY_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; }))
+         && trp > rp_longest)
+        || ((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (ABDAY_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (ABDAY_1) & 0xffff)].string)[cnt]), (rp), len, locale) == 0; if (result) (rp) += len; result; }))
+     && trp > rp_longest)))
+  {
+  }
+     }
+     {
+       const char *trp;
+       if (s.decided != loc
+    && (((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (MON_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (MON_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; }))
+         && trp > rp_longest)
+        || ((trp = rp, ({ size_t len = strlen ((&_nl_C_LC_TIME.values[((int) (ABMON_1) & 0xffff)].string)[cnt]); int result = __strncasecmp_l (((&_nl_C_LC_TIME.values[((int) (ABMON_1) & 0xffff)].string)[cnt]), (trp), len, locale) == 0; if (result) (trp) += len; result; }))
+     && trp > rp_longest)))
+  {
+  }
+     }
+ case 'c':
+     {
+       if (!(*((current->values[((int) (D_T_FMT) & 0xffff)].string)) != '\0' && (rp = __strptime_internal (rp, ((current->values[((int) (D_T_FMT) & 0xffff)].string)), tm, &s , locale)) != ((void *)0)))
+  {
+      rp = rp_backup;
+  }
+     }
+ case 'C':
+   do { int __n = 2; val = 0; while (*rp == ' ') ++rp; if (*rp < '0' || *rp > '9') return ((void *)0); do { val *= 10; val += *rp++ - '0'; } while (--__n > 0 && val * 10 <= 99 && *rp >= '0' && *rp <= '9'); if (val < 0 || val > 99) return ((void *)0); } while (0);
+ case 'F':
+   if (!(*("%Y-%m-%d") != '\0' && (rp = __strptime_internal (rp, ("%Y-%m-%d"), tm, &s , locale)) != ((void *)0)))
+   tm->tm_hour = val % 12;
+ }
+    }
+}
+char *
+__strptime_l (buf, format, tm , locale)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pmull_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pmull_1.c
new file mode 100644
index 000000000..bccaec175
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pmull_1.c
@@ -0,0 +1,23 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+poly128_t
+test_vmull_p64 (poly64_t a, poly64_t b)
+{
+  return vmull_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "pmull\\tv" 1 } } */
+
+poly128_t
+test_vmull_high_p64 (poly64x2_t a, poly64x2_t b)
+{
+  return vmull_high_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "pmull2\\tv" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr58460.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr58460.c
new file mode 100644
index 000000000..a7e149a37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr58460.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+extern unsigned long x1;
+
+char *
+f (char *a, char *b)
+{
+  return a;
+}
+
+int
+g (char *a)
+{
+  return 2;
+}
+
+void
+h (char *p[])
+{
+  char n[x1][512];
+  char *l = f (p[1], " ");
+  if (g (p[0]))
+    n[0][0] = '\0';
+  while (l && *l)
+    {
+    }
+}
+
+unsigned long x1;
+
+int
+main ()
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_large.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_large.c
new file mode 100644
index 000000000..0d7d4da47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_large.c
@@ -0,0 +1,7 @@
+/* { dg-skip-if "Code model already defined" { aarch64_tiny || aarch64_small } } */
+
+#ifdef __AARCH64_CMODEL_LARGE__
+  int dummy;
+#else
+  #error
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_small.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_small.c
new file mode 100644
index 000000000..b1362845c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_small.c
@@ -0,0 +1,7 @@
+/* { dg-skip-if "Code model already defined" { aarch64_tiny || aarch64_large } } */
+
+#ifdef __AARCH64_CMODEL_SMALL__
+  int dummy;
+#else
+  #error
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_tiny.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_tiny.c
new file mode 100644
index 000000000..d2c844bac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/predefine_tiny.c
@@ -0,0 +1,7 @@
+/* { dg-skip-if "Code model already defined" { aarch64_small || aarch64_large } } */
+
+#ifdef __AARCH64_CMODEL_TINY__
+  int dummy;
+#else
+  #error
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
new file mode 100644
index 000000000..b44e56023
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/reload-valid-spoff.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcmodel=large -fno-builtin" }  */
+/* { dg-skip-if "-mcmodel=large -fPIC not currently supported" { aarch64-*-* }  { "-fPIC" } { "" } } */
+
+typedef long unsigned int size_t;
+typedef unsigned short int sa_family_t;
+
+struct sockaddr
+{
+  sa_family_t sa_family;
+  char sa_data[14];
+};
+struct arpreq
+{
+  int arp_flags;
+  struct sockaddr arp_netmask;
+};
+typedef struct _IO_FILE FILE;
+extern char *fgets (char *__restrict __s, int __n, FILE *__restrict __stream);
+extern struct _IO_FILE *stderr;
+extern int optind;
+struct aftype {
+  int (*input) (int type, char *bufp, struct sockaddr *);
+};
+struct aftype *ap;
+static int arp_set(char **args)
+{
+  char host[128];
+  struct arpreq req;
+  struct sockaddr sa;
+  memset((char *) &req, 0, sizeof(req));
+  if (*args == ((void *)0)) {
+    fprintf(stderr, ("arp: need host name\n"));
+  }
+  safe_strncpy(host, *args++, (sizeof host));
+  if (ap->input(0, host, &sa) < 0) {
+  }
+  while (*args != ((void *)0)) {
+    if (!__extension__ ({ size_t __s1_len, __s2_len; (__builtin_constant_p (*args) && __builtin_constant_p ("netmask") && (__s1_len = strlen (*args), __s2_len = strlen ("netmask"), (!((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) || __s1_len >= 4) && (!((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) || __s2_len >= 4)) ? __builtin_strcmp (*args, "netmask") : (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) && (__s1_len = strlen (*args), __s1_len < 4) ? (__builtin_constant_p ("netmask") && ((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) ? __builtin_strcmp (*args, "netmask") : (__extension__ ({ __const unsigned char *__s2 = (__const unsigned char *) (__const char *) ("netmask"); register int __result = (((__const unsigned char *) (__const char *) (*args))[0] - __s2[0]); if (__s1_len > 0 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[1] - __s2[1]); if (__s1_len > 1 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[2] - __s2[2]); if (__s1_len > 2 && __result == 0) __result = (((__const unsigned char *) (__const char *) (*args))[3] - __s2[3]); } } __result; }))) : (__builtin_constant_p ("netmask") && ((size_t)(const void *)(("netmask") + 1) - (size_t)(const void *)("netmask") == 1) && (__s2_len = strlen ("netmask"), __s2_len < 4) ? (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) ? __builtin_strcmp (*args, "netmask") : (__extension__ ({ __const unsigned char *__s1 = (__const unsigned char *) (__const char *) (*args); register int __result = __s1[0] - ((__const unsigned char *) (__const char *) ("netmask"))[0]; if (__s2_len > 0 && __result == 0) { __result = (__s1[1] - ((__const unsigned char *) (__const char *) ("netmask"))[1]); if (__s2_len > 1 && __result == 0) { __result = (__s1[2] - ((__const unsigned char *) (__const char *) ("netmask"))[2]); if (__s2_len > 2 && __result == 0) __result = (__s1[3] - ((__const unsigned char *) (__const char *) ("netmask"))[3]); } } __result; }))) : __builtin_strcmp (*args, "netmask")))); })) {
+      if (__extension__ ({ size_t __s1_len, __s2_len; (__builtin_constant_p (*args) && __builtin_constant_p ("255.255.255.255") && (__s1_len = strlen (*args), __s2_len = strlen ("255.255.255.255"), (!((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) || __s1_len >= 4) && (!((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) || __s2_len >= 4)) ? __builtin_strcmp (*args, "255.255.255.255") : (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) && (__s1_len = strlen (*args), __s1_len < 4) ? (__builtin_constant_p ("255.255.255.255") && ((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) ? __builtin_strcmp (*args, "255.255.255.255") : (__extension__ ({ __const unsigned char *__s2 = (__const unsigned char *) (__const char *) ("255.255.255.255"); register int __result = (((__const unsigned char *) (__const char *) (*args))[0] - __s2[0]); if (__s1_len > 0 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[1] - __s2[1]); if (__s1_len > 1 && __result == 0) { __result = (((__const unsigned char *) (__const char *) (*args))[2] - __s2[2]); if (__s1_len > 2 && __result == 0) __result = (((__const unsigned char *) (__const char *) (*args))[3] - __s2[3]); } } __result; }))) : (__builtin_constant_p ("255.255.255.255") && ((size_t)(const void *)(("255.255.255.255") + 1) - (size_t)(const void *)("255.255.255.255") == 1) && (__s2_len = strlen ("255.255.255.255"), __s2_len < 4) ? (__builtin_constant_p (*args) && ((size_t)(const void *)((*args) + 1) - (size_t)(const void *)(*args) == 1) ? __builtin_strcmp (*args, "255.255.255.255") : (__extension__ ({ __const unsigned char *__s1 = (__const unsigned char *) (__const char *) (*args); register int __result = __s1[0] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[0]; if (__s2_len > 0 && __result == 0) { __result = (__s1[1] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[1]); if (__s2_len > 1 && __result == 0) { __result = (__s1[2] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[2]); if (__s2_len > 2 && __result == 0) __result = (__s1[3] - ((__const unsigned char *) (__const char *) ("255.255.255.255"))[3]); } } __result; }))) : __builtin_strcmp (*args, "255.255.255.255")))); }) != 0) {
+	memcpy((char *) &req.arp_netmask, (char *) &sa,
+	       sizeof(struct sockaddr));
+      }
+    }
+  }
+}
+static int arp_file(char *name)
+{
+  char buff[1024];
+  char *sp, *args[32];
+  int linenr, argc;
+  FILE *fp;
+  while (fgets(buff, sizeof(buff), fp) != (char *) ((void *)0)) {
+    if (arp_set(args) != 0)
+      fprintf(stderr, ("arp: cannot set entry on line %u on line %u of etherfile %s !\n"),
+	      linenr, name);
+  }
+}
+int main(int argc, char **argv)
+{
+  int i, lop, what;
+  switch (what) {
+  case 0:
+    what = arp_file(argv[optind] ? argv[optind] : "/etc/ethers");
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ror.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ror.c
new file mode 100644
index 000000000..4d266f004
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ror.c
@@ -0,0 +1,34 @@
+/* { dg-options "-O2 --save-temps" } */
+/* { dg-do run } */
+
+extern void abort (void);
+
+int
+test_si (int a)
+{
+  /* { dg-final { scan-assembler "ror\tw\[0-9\]+, w\[0-9\]+, 27\n" } } */
+  return (a << 5) | ((unsigned int) a >> 27);
+}
+
+long long
+test_di (long long a)
+{
+  /* { dg-final { scan-assembler "ror\tx\[0-9\]+, x\[0-9\]+, 45\n" } } */
+  return (a << 19) | ((unsigned long long) a >> 45);
+}
+
+int
+main ()
+{
+  int v;
+  long long w;
+  v = test_si (0x0203050);
+  if (v != 0x4060a00)
+    abort();
+  w = test_di (0x0000020506010304ll);
+  if (w != 0x1028300818200000ll)
+    abort();
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sbc.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sbc.c
new file mode 100644
index 000000000..e479910bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sbc.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps" } */
+
+extern void abort (void);
+
+typedef unsigned int u32int;
+typedef unsigned long long u64int;
+
+u32int
+test_si (u32int w1, u32int w2, u32int w3, u32int w4)
+{
+  u32int w0;
+  /* { dg-final { scan-assembler "sbc\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+\n" } } */
+  w0 = w1 - w2 - (w3 < w4);
+  return w0;
+}
+
+u64int
+test_di (u64int x1, u64int x2, u64int x3, u64int x4)
+{
+  u64int x0;
+  /* { dg-final { scan-assembler "sbc\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+\n" } } */
+  x0 = x1 - x2 - (x3 < x4);
+  return x0;
+}
+
+int
+main ()
+{
+  u32int x;
+  u64int y;
+  x = test_si (7, 8, 12, 15);
+  if (x != -2)
+    abort();
+  y = test_di (0x987654321ll, 0x123456789ll, 0x345345345ll, 0x123123123ll);
+  if (y != 0x8641fdb98ll)
+    abort();
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-mov.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-mov.c
new file mode 100644
index 000000000..5e53d87a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-mov.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-g -mgeneral-regs-only" } */
+
+void
+foo (const char *c, ...)
+{
+  char buf[256];
+  buf[256 - 1] = '\0';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-vca.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-vca.c
new file mode 100644
index 000000000..b1188146c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar-vca.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+#define NUM_TESTS 8
+
+float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f};
+float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f};
+double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5};
+double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5};
+
+#define TEST(TEST, CMP, SUFFIX, WIDTH, F)				\
+int									\
+test_fca##TEST##SUFFIX##_float##WIDTH##_t (void)			\
+{									\
+  int ret = 0;								\
+  int i = 0;								\
+  uint##WIDTH##_t output[NUM_TESTS];					\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    {									\
+      float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]);		\
+      float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]);		\
+      /* Inhibit optimization of our linear test loop.  */		\
+      asm volatile ("" : : : "memory");					\
+      output[i] = f1 CMP f2 ? -1 : 0;					\
+    }									\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    {									\
+      output[i] = vca##TEST##SUFFIX##_f##WIDTH (input_##SUFFIX##1[i],	\
+						input_##SUFFIX##2[i])	\
+						  ^ output[i];		\
+      /* Inhibit autovectorization of our scalar test loop.  */		\
+      asm volatile ("" : : : "memory");					\
+    }									\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    ret |= output[i];							\
+									\
+  return ret;								\
+}
+
+TEST (ge, >=, s, 32, f)
+/* { dg-final { scan-assembler "facge\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */
+TEST (ge, >=, d, 64, )
+/* { dg-final { scan-assembler "facge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */
+TEST (gt, >, s, 32, f)
+/* { dg-final { scan-assembler "facgt\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */
+TEST (gt, >, d, 64, )
+/* { dg-final { scan-assembler "facgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */
+
+int
+main (int argc, char **argv)
+{
+  if (test_fcages_float32_t ())
+    abort ();
+  if (test_fcaged_float64_t ())
+    abort ();
+  if (test_fcagts_float32_t ())
+    abort ();
+  if (test_fcagtd_float64_t ())
+    abort ();
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
new file mode 100644
index 000000000..aa041cc2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -0,0 +1,1301 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -dp" } */
+
+#include <arm_neon.h>
+
+/* Used to force a variable to a SIMD register.  */
+#define force_simd(V1)   asm volatile ("mov %d0, %1.d[0]"	\
+	   : "=w"(V1)						\
+	   : "w"(V1)						\
+	   : /* No clobbers */);
+
+/* { dg-final { scan-assembler-times "\\tadd\\tx\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vaddd_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vaddd_u64 (a, b);
+}
+
+int64x1_t
+test_vaddd_s64 (int64x1_t a, int64x1_t b)
+{
+  return vaddd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tadd\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vaddd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d)
+{
+  return vqaddd_s64 (vaddd_s64 (vqaddd_s64 (a, b), vqaddd_s64 (c, d)),
+		     vqaddd_s64 (a, d));
+}
+
+/* { dg-final { scan-assembler-times "\\tabs\\td\[0-9\]+, d\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vabs_s64 (int64x1_t a)
+{
+  uint64x1_t res;
+  force_simd (a);
+  res = vabs_s64 (a);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vceqd_s64 (int64x1_t a, int64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vceqd_s64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmeq\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vceqzd_s64 (int64x1_t a)
+{
+  uint64x1_t res;
+  force_simd (a);
+  res = vceqzd_s64 (a);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmge\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vcged_s64 (int64x1_t a, int64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vcged_s64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+uint64x1_t
+test_vcled_s64 (int64x1_t a, int64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vcled_s64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+/* Idiom recognition will cause this testcase not to generate
+   the expected cmge instruction, so do not check for it.  */
+
+uint64x1_t
+test_vcgezd_s64 (int64x1_t a)
+{
+  uint64x1_t res;
+  force_simd (a);
+  res = vcgezd_s64 (a);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmhs\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vcged_u64 (uint64x1_t a, uint64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vcged_u64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vcgtd_s64 (int64x1_t a, int64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vcgtd_s64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+uint64x1_t
+test_vcltd_s64 (int64x1_t a, int64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vcltd_s64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmgt\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vcgtzd_s64 (int64x1_t a)
+{
+  uint64x1_t res;
+  force_simd (a);
+  res = vcgtzd_s64 (a);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmhi\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vcgtd_u64 (uint64x1_t a, uint64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vcgtd_u64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmle\\td\[0-9\]+, d\[0-9\]+, #?0" 1 } } */
+
+uint64x1_t
+test_vclezd_s64 (int64x1_t a)
+{
+  uint64x1_t res;
+  force_simd (a);
+  res = vclezd_s64 (a);
+  force_simd (res);
+  return res;
+}
+
+/* Idiom recognition will cause this testcase not to generate
+   the expected cmlt instruction, so do not check for it.  */
+
+uint64x1_t
+test_vcltzd_s64 (int64x1_t a)
+{
+  uint64x1_t res;
+  force_simd (a);
+  res = vcltzd_s64 (a);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "aarch64_get_lanev16qi" 2 } } */
+
+int8x1_t
+test_vdupb_lane_s8 (int8x16_t a)
+{
+  int8x1_t res;
+  force_simd (a);
+  res = vdupb_laneq_s8 (a, 2);
+  force_simd (res);
+  return res;
+}
+
+uint8x1_t
+test_vdupb_lane_u8 (uint8x16_t a)
+{
+  uint8x1_t res;
+  force_simd (a);
+  res = vdupb_laneq_u8 (a, 2);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "aarch64_get_lanev8hi" 2 } } */
+
+int16x1_t
+test_vduph_lane_s16 (int16x8_t a)
+{
+  int16x1_t res;
+  force_simd (a);
+  res = vduph_laneq_s16 (a, 2);
+  force_simd (res);
+  return res;
+}
+
+uint16x1_t
+test_vduph_lane_u16 (uint16x8_t a)
+{
+  uint16x1_t res;
+  force_simd (a);
+  res = vduph_laneq_u16 (a, 2);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "aarch64_get_lanev4si" 2 } } */
+
+int32x1_t
+test_vdups_lane_s32 (int32x4_t a)
+{
+  int32x1_t res;
+  force_simd (a);
+  res = vdups_laneq_s32 (a, 2);
+  force_simd (res);
+  return res;
+}
+
+uint32x1_t
+test_vdups_lane_u32 (uint32x4_t a)
+{
+  uint32x1_t res;
+  force_simd (a);
+  res = vdups_laneq_u32 (a, 2);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "aarch64_get_lanev2di" 2 } } */
+
+int64x1_t
+test_vdupd_lane_s64 (int64x2_t a)
+{
+  int64x1_t res;
+  force_simd (a);
+  res = vdupd_laneq_s64 (a, 1);
+  force_simd (res);
+  return res;
+}
+
+uint64x1_t
+test_vdupd_lane_u64 (uint64x2_t a)
+{
+  uint64x1_t res;
+  force_simd (a);
+  res = vdupd_laneq_u64 (a, 1);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\tcmtst\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vtst_s64 (int64x1_t a, int64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vtstd_s64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+uint64x1_t
+test_vtst_u64 (uint64x1_t a, uint64x1_t b)
+{
+  uint64x1_t res;
+  force_simd (a);
+  force_simd (b);
+  res = vtstd_s64 (a, b);
+  force_simd (res);
+  return res;
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\td\[0-9\]+, v\[0-9\]+\.2d" 1 } } */
+
+test_vpaddd_s64 (int64x2_t a)
+{
+  return vpaddd_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqaddd_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vqaddd_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqadds_u32 (uint32x1_t a, uint32x1_t b)
+{
+  return vqadds_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqaddh_u16 (uint16x1_t a, uint16x1_t b)
+{
+  return vqaddh_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqadd\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqaddb_u8 (uint8x1_t a, uint8x1_t b)
+{
+  return vqaddb_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\td\[0-9\]+" 5 } } */
+
+int64x1_t
+test_vqaddd_s64 (int64x1_t a, int64x1_t b)
+{
+  return vqaddd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\ts\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqadds_s32 (int32x1_t a, int32x1_t b)
+{
+  return vqadds_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\th\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqaddh_s16 (int16x1_t a, int16x1_t b)
+{
+  return vqaddh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqadd\\tb\[0-9\]+, b\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqaddb_s8 (int8x1_t a, int8x1_t b)
+{
+  return vqaddb_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqdmlalh_s16 (int32x1_t a, int16x1_t b, int16x1_t c)
+{
+  return vqdmlalh_s16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c)
+{
+  return vqdmlalh_lane_s16 (a, b, c, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
+{
+  return vqdmlals_s32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int64x1_t
+test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c)
+{
+  return vqdmlals_lane_s32 (a, b, c, 1);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqdmlslh_s16 (int32x1_t a, int16x1_t b, int16x1_t c)
+{
+  return vqdmlslh_s16 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c)
+{
+  return vqdmlslh_lane_s16 (a, b, c, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c)
+{
+  return vqdmlsls_s32 (a, b, c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int64x1_t
+test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c)
+{
+  return vqdmlsls_lane_s32 (a, b, c, 1);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqdmulhh_s16 (int16x1_t a, int16x1_t b)
+{
+  return vqdmulhh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int16x1_t
+test_vqdmulhh_lane_s16 (int16x1_t a, int16x8_t b)
+{
+  return vqdmulhh_lane_s16 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqdmulhs_s32 (int32x1_t a, int32x1_t b)
+{
+  return vqdmulhs_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqdmulhs_lane_s32 (int32x1_t a, int32x4_t b)
+{
+  return vqdmulhs_lane_s32 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqdmullh_s16 (int16x1_t a, int16x1_t b)
+{
+  return vqdmullh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqdmullh_lane_s16 (int16x1_t a, int16x8_t b)
+{
+  return vqdmullh_lane_s16 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqdmulls_s32 (int32x1_t a, int32x1_t b)
+{
+  return vqdmulls_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int64x1_t
+test_vqdmulls_lane_s32 (int32x1_t a, int32x4_t b)
+{
+  return vqdmulls_lane_s32 (a, b, 1);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqrdmulhh_s16 (int16x1_t a, int16x1_t b)
+{
+  return vqrdmulhh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */
+
+int16x1_t
+test_vqrdmulhh_lane_s16 (int16x1_t a, int16x8_t b)
+{
+  return vqrdmulhh_lane_s16 (a, b, 6);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqrdmulhs_s32 (int32x1_t a, int32x1_t b)
+{
+  return vqrdmulhs_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */
+
+int32x1_t
+test_vqrdmulhs_lane_s32 (int32x1_t a, int32x4_t b)
+{
+  return vqrdmulhs_lane_s32 (a, b, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vuqaddb_s8 (int8x1_t a, int8x1_t b)
+{
+  return vuqaddb_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vuqaddh_s16 (int16x1_t a, int8x1_t b)
+{
+  return vuqaddh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vuqadds_s32 (int32x1_t a, int8x1_t b)
+{
+  return vuqadds_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsuqadd\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vuqaddd_s64 (int64x1_t a, int8x1_t b)
+{
+  return vuqaddd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vsqaddb_u8 (uint8x1_t a, int8x1_t b)
+{
+  return vsqaddb_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vsqaddh_u16 (uint16x1_t a, int8x1_t b)
+{
+  return vsqaddh_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vsqadds_u32 (uint32x1_t a, int8x1_t b)
+{
+  return vsqadds_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tusqadd\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vsqaddd_u64 (uint64x1_t a, int8x1_t b)
+{
+  return vsqaddd_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqabs\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqabsb_s8 (int8x1_t a)
+{
+  return vqabsb_s8 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqabs\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqabsh_s16 (int16x1_t a)
+{
+  return vqabsh_s16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqabs\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqabss_s32 (int32x1_t a)
+{
+  return vqabss_s32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqneg\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqnegb_s8 (int8x1_t a)
+{
+  return vqnegb_s8 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqneg\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqnegh_s16 (int16x1_t a)
+{
+  return vqnegh_s16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqneg\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqnegs_s32 (int32x1_t a)
+{
+  return vqnegs_s32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtun\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqmovunh_s16 (int16x1_t a)
+{
+  return vqmovunh_s16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtun\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqmovuns_s32 (int32x1_t a)
+{
+  return vqmovuns_s32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtun\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqmovund_s64 (int64x1_t a)
+{
+  return vqmovund_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtn\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqmovnh_s16 (int16x1_t a)
+{
+  return vqmovnh_s16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtn\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqmovns_s32 (int32x1_t a)
+{
+  return vqmovns_s32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqxtn\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqmovnd_s64 (int64x1_t a)
+{
+  return vqmovnd_s64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqxtn\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqmovnh_u16 (uint16x1_t a)
+{
+  return vqmovnh_u16 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqxtn\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqmovns_u32 (uint32x1_t a)
+{
+  return vqmovns_u32 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqxtn\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqmovnd_u64 (uint64x1_t a)
+{
+  return vqmovnd_u64 (a);
+}
+
+/* { dg-final { scan-assembler-times "\\tsub\\tx\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vsubd_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vsubd_u64 (a, b);
+}
+
+int64x1_t
+test_vsubd_s64 (int64x1_t a, int64x1_t b)
+{
+  return vsubd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsub\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vsubd_s64_2 (int64x1_t a, int64x1_t b, int64x1_t c, int64x1_t d)
+{
+  return vqsubd_s64 (vsubd_s64 (vqsubd_s64 (a, b), vqsubd_s64 (c, d)),
+		     vqsubd_s64 (a, d));
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqsubd_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vqsubd_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqsubs_u32 (uint32x1_t a, uint32x1_t b)
+{
+  return vqsubs_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqsubh_u16 (uint16x1_t a, uint16x1_t b)
+{
+  return vqsubh_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqsub\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqsubb_u8 (uint8x1_t a, uint8x1_t b)
+{
+  return vqsubb_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\td\[0-9\]+" 5 } } */
+
+int64x1_t
+test_vqsubd_s64 (int64x1_t a, int64x1_t b)
+{
+  return vqsubd_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqsubs_s32 (int32x1_t a, int32x1_t b)
+{
+  return vqsubs_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqsubh_s16 (int16x1_t a, int16x1_t b)
+{
+  return vqsubh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqsub\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqsubb_s8 (int8x1_t a, int8x1_t b)
+{
+  return vqsubb_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vshld_s64 (int64x1_t a, int64x1_t b)
+{
+  return vshld_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tushl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vshld_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vshld_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrshld_s64 (int64x1_t a, int64x1_t b)
+{
+  return vrshld_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\turshl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrshld_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vrshld_u64 (a, b);
+}
+
+/* Other intrinsics can generate an asr instruction (vcltzd, vcgezd),
+   so we cannot check scan-assembler-times.  */
+
+/* { dg-final { scan-assembler "\\tasr\\tx\[0-9\]+" } } */
+
+int64x1_t
+test_vshrd_n_s64 (int64x1_t a)
+{
+  return vshrd_n_s64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tlsr\\tx\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vshrd_n_u64 (uint64x1_t a)
+{
+  return vshrd_n_u64 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tssra\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vsrad_n_s64 (int64x1_t a, int64x1_t b)
+{
+  return vsrad_n_s64 (a, b, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tusra\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vsrad_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vsrad_n_u64 (a, b, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrshr\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrshrd_n_s64 (int64x1_t a)
+{
+  return vrshrd_n_s64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\turshr\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrshrd_n_u64 (uint64x1_t a)
+{
+  return vrshrd_n_u64 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vrsrad_n_s64 (int64x1_t a, int64x1_t b)
+{
+  return vrsrad_n_s64 (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsrsra\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vrsrad_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vrsrad_n_u64 (a, b, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqrshlb_s8 (int8x1_t a, int8x1_t b)
+{
+  return vqrshlb_s8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqrshlh_s16 (int16x1_t a, int16x1_t b)
+{
+  return vqrshlh_s16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqrshls_s32 (int32x1_t a, int32x1_t b)
+{
+  return vqrshls_s32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshl\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqrshld_s64 (int64x1_t a, int64x1_t b)
+{
+  return vqrshld_s64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqrshlb_u8 (uint8x1_t a, uint8x1_t b)
+{
+  return vqrshlb_u8 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqrshlh_u16 (uint16x1_t a, uint16x1_t b)
+{
+  return vqrshlh_u16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqrshls_u32 (uint32x1_t a, uint32x1_t b)
+{
+  return vqrshls_u32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshl\\td\[0-9\]+" 1 } } */
+
+uint64x1_t
+test_vqrshld_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vqrshld_u64 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqshlub_n_s8 (int8x1_t a)
+{
+  return vqshlub_n_s8 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqshluh_n_s16 (int16x1_t a)
+{
+  return vqshluh_n_s16 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqshlus_n_s32 (int32x1_t a)
+{
+  return vqshlus_n_s32 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshlu\\td\[0-9\]+" 1 } } */
+
+int64x1_t
+test_vqshlud_n_s64 (int64x1_t a)
+{
+  return vqshlud_n_s64 (a, 6);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\tb\[0-9\]+" 2 } } */
+
+int8x1_t
+test_vqshlb_s8 (int8x1_t a, int8x1_t b)
+{
+  return vqshlb_s8 (a, b);
+}
+
+int8x1_t
+test_vqshlb_n_s8 (int8x1_t a)
+{
+  return vqshlb_n_s8 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\th\[0-9\]+" 2 } } */
+
+int16x1_t
+test_vqshlh_s16 (int16x1_t a, int16x1_t b)
+{
+  return vqshlh_s16 (a, b);
+}
+
+int16x1_t
+test_vqshlh_n_s16 (int16x1_t a)
+{
+  return vqshlh_n_s16 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\ts\[0-9\]+" 2 } } */
+
+int32x1_t
+test_vqshls_s32 (int32x1_t a, int32x1_t b)
+{
+  return vqshls_s32 (a, b);
+}
+
+int32x1_t
+test_vqshls_n_s32 (int32x1_t a)
+{
+  return vqshls_n_s32 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshl\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vqshld_s64 (int64x1_t a, int64x1_t b)
+{
+  return vqshld_s64 (a, b);
+}
+
+int64x1_t
+test_vqshld_n_s64 (int64x1_t a)
+{
+  return vqshld_n_s64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\tb\[0-9\]+" 2 } } */
+
+uint8x1_t
+test_vqshlb_u8 (uint8x1_t a, uint8x1_t b)
+{
+  return vqshlb_u8 (a, b);
+}
+
+uint8x1_t
+test_vqshlb_n_u8 (uint8x1_t a)
+{
+  return vqshlb_n_u8 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\th\[0-9\]+" 2 } } */
+
+uint16x1_t
+test_vqshlh_u16 (uint16x1_t a, uint16x1_t b)
+{
+  return vqshlh_u16 (a, b);
+}
+
+uint16x1_t
+test_vqshlh_n_u16 (uint16x1_t a)
+{
+  return vqshlh_n_u16 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\ts\[0-9\]+" 2 } } */
+
+uint32x1_t
+test_vqshls_u32 (uint32x1_t a, uint32x1_t b)
+{
+  return vqshls_u32 (a, b);
+}
+
+uint32x1_t
+test_vqshls_n_u32 (uint32x1_t a)
+{
+  return vqshls_n_u32 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshl\\td\[0-9\]+" 2 } } */
+
+uint64x1_t
+test_vqshld_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vqshld_u64 (a, b);
+}
+
+uint64x1_t
+test_vqshld_n_u64 (uint64x1_t a)
+{
+  return vqshld_n_u64 (a, 5);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrun\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqshrunh_n_s16 (int16x1_t a)
+{
+  return vqshrunh_n_s16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrun\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqshruns_n_s32 (int32x1_t a)
+{
+  return vqshruns_n_s32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrun\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqshrund_n_s64 (int64x1_t a)
+{
+  return vqshrund_n_s64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrun\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqrshrunh_n_s16 (int16x1_t a)
+{
+  return vqrshrunh_n_s16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrun\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqrshruns_n_s32 (int32x1_t a)
+{
+  return vqrshruns_n_s32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrun\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqrshrund_n_s64 (int64x1_t a)
+{
+  return vqrshrund_n_s64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrn\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqshrnh_n_s16 (int16x1_t a)
+{
+  return vqshrnh_n_s16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrn\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqshrns_n_s32 (int32x1_t a)
+{
+  return vqshrns_n_s32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqshrn\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqshrnd_n_s64 (int64x1_t a)
+{
+  return vqshrnd_n_s64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshrn\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqshrnh_n_u16 (uint16x1_t a)
+{
+  return vqshrnh_n_u16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshrn\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqshrns_n_u32 (uint32x1_t a)
+{
+  return vqshrns_n_u32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqshrn\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqshrnd_n_u64 (uint64x1_t a)
+{
+  return vqshrnd_n_u64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrn\\tb\[0-9\]+" 1 } } */
+
+int8x1_t
+test_vqrshrnh_n_s16 (int16x1_t a)
+{
+  return vqrshrnh_n_s16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrn\\th\[0-9\]+" 1 } } */
+
+int16x1_t
+test_vqrshrns_n_s32 (int32x1_t a)
+{
+  return vqrshrns_n_s32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqrshrn\\ts\[0-9\]+" 1 } } */
+
+int32x1_t
+test_vqrshrnd_n_s64 (int64x1_t a)
+{
+  return vqrshrnd_n_s64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshrn\\tb\[0-9\]+" 1 } } */
+
+uint8x1_t
+test_vqrshrnh_n_u16 (uint16x1_t a)
+{
+  return vqrshrnh_n_u16 (a, 2);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshrn\\th\[0-9\]+" 1 } } */
+
+uint16x1_t
+test_vqrshrns_n_u32 (uint32x1_t a)
+{
+  return vqrshrns_n_u32 (a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tuqrshrn\\ts\[0-9\]+" 1 } } */
+
+uint32x1_t
+test_vqrshrnd_n_u64 (uint64x1_t a)
+{
+  return vqrshrnd_n_u64 (a, 4);
+}
+
+/* { dg-final { scan-assembler-times "\\tlsl\\tx\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vshl_n_s64 (int64x1_t a)
+{
+  return vshld_n_s64 (a, 9);
+}
+
+uint64x1_t
+test_vshl_n_u64 (uint64x1_t a)
+{
+  return vshld_n_u64 (a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tsli\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vsli_n_s64 (int64x1_t a, int64x1_t b)
+{
+  return vslid_n_s64 (a, b, 9);
+}
+
+uint64x1_t
+test_vsli_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vslid_n_u64 (a, b, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tsri\\td\[0-9\]+" 2 } } */
+
+int64x1_t
+test_vsri_n_s64 (int64x1_t a, int64x1_t b)
+{
+  return vsrid_n_s64 (a, b, 9);
+}
+
+uint64x1_t
+test_vsri_n_u64 (uint64x1_t a, uint64x1_t b)
+{
+  return vsrid_n_u64 (a, b, 9);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
new file mode 100644
index 000000000..7cb17f89c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
@@ -0,0 +1,263 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline -save-temps" } */
+
+extern void abort ();
+
+#define force_simd_di(v) asm volatile ("mov %d0, %1.d[0]" :"=w" (v) :"w" (v) :)
+#define force_simd_si(v) asm volatile ("mov %s0, %1.s[0]" :"=w" (v) :"w" (v) :)
+
+typedef unsigned long long int UInt64x1;
+typedef long long int Int64x1;
+typedef unsigned int UInt32x1;
+typedef int Int32x1;
+
+UInt64x1
+test_lshift_left_sisd_di (UInt64x1 b, UInt64x1 c)
+{
+  UInt64x1 a;
+
+  force_simd_di (b);
+  force_simd_di (c);
+  a = b << 8;
+  a = a << c;
+  force_simd_di (a);
+  return a;
+}
+/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
+/* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+
+UInt32x1
+test_lshift_left_sisd_si (UInt32x1 b, UInt32x1 c)
+{
+  UInt32x1 a;
+
+  force_simd_si (b);
+  force_simd_si (c);
+  a = b << 4;
+  a = a << c;
+  force_simd_si (a);
+  return a;
+}
+/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
+/* "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" (counted later) */
+
+UInt64x1
+test_lshift_right_sisd_di (UInt64x1 b, UInt64x1 c)
+{
+  UInt64x1 a;
+
+  force_simd_di (b);
+  force_simd_di (c);
+  a = b >> 8;
+  a = a >> c;
+  force_simd_di (a);
+  return a;
+}
+/* { dg-final { scan-assembler "ushr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
+/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
+/* { dg-final { scan-assembler "ushl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+
+UInt64x1
+test_lshift_right_sisd_si (UInt32x1 b, UInt32x1 c)
+{
+  UInt32x1 a;
+
+  force_simd_si (b);
+  force_simd_si (c);
+  a = b >> 4;
+  a = a >> c;
+  force_simd_si (a);
+  return a;
+}
+/* { dg-final { scan-assembler "ushr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
+/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
+/* { dg-final { scan-assembler-times "ushl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 2 } } */
+
+Int64x1
+test_ashift_right_sisd_di (Int64x1 b, Int64x1 c)
+{
+  Int64x1 a;
+
+  force_simd_di (b);
+  force_simd_di (c);
+  a = b >> 8;
+  a = a >> c;
+  force_simd_di (a);
+  return a;
+}
+/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 8" } } */
+/* "neg\td\[0-9\]+,\ d\[0-9\]+" (counted later) */
+/* { dg-final { scan-assembler "sshl\td\[0-9\]+,\ d\[0-9\]+,\ d\[0-9\]+" } } */
+
+Int32x1
+test_ashift_right_sisd_si (Int32x1 b, Int32x1 c)
+{
+  Int32x1 a;
+
+  force_simd_si (b);
+  force_simd_si (c);
+  a = b >> 4;
+  a = a >> c;
+  force_simd_si (a);
+  return a;
+}
+/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 4" } } */
+/* { dg-final { scan-assembler-times "neg\td\[0-9\]+,\ d\[0-9\]+" 4 } } */
+/* { dg-final { scan-assembler "sshl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */
+
+
+/* The following are to make sure if the integer instructions lsl/lsr/asr are
+   generated in non-vector scenarios */
+
+UInt64x1
+test_lshift_left_int_di (UInt64x1 b, UInt64x1 c)
+{
+  UInt64x1 a;
+
+  a = b << 8;
+  a = a << c;
+  return a;
+}
+/* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
+/* { dg-final { scan-assembler "lsl\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+
+UInt32x1
+test_lshift_left_int_si (UInt32x1 b, UInt32x1 c)
+{
+  UInt32x1 a;
+
+  a = b << 4;
+  a = a << c;
+  return a;
+}
+/* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
+/* { dg-final { scan-assembler "lsl\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+
+UInt64x1
+test_lshift_right_int_di (UInt64x1 b, UInt64x1 c)
+{
+  UInt64x1 a;
+
+  a = b >> 8;
+  a = a >> c;
+  return a;
+}
+/* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
+/* { dg-final { scan-assembler "lsr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+
+UInt32x1
+test_lshift_right_int_si (UInt32x1 b, UInt32x1 c)
+{
+  UInt32x1 a;
+
+  a = b >> 4;
+  a = a >> c;
+  return a;
+}
+/* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
+/* { dg-final { scan-assembler "lsr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+
+Int64x1
+test_ashift_right_int_di (Int64x1 b, Int64x1 c)
+{
+  Int64x1 a;
+
+  a = b >> 8;
+  a = a >> c;
+  return a;
+}
+/* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ 8" } } */
+/* { dg-final { scan-assembler "asr\tx\[0-9\]+,\ x\[0-9\]+,\ x\[0-9\]+" } } */
+
+Int32x1
+test_ashift_right_int_si (Int32x1 b, Int32x1 c)
+{
+  Int32x1 a;
+
+  a = b >> 4;
+  a = a >> c;
+  return a;
+}
+/* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
+/* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
+
+Int64x1
+test_corners_sisd_di (Int64x1 b)
+{
+  force_simd_di (b);
+  b = b >> 63;
+  b = b >> 0;
+  b += b >> 65; /* { dg-warning "right shift count >= width of type" } */
+  force_simd_di (b);
+
+  return b;
+}
+/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */
+/* { dg-final { scan-assembler "shl\td\[0-9\]+,\ d\[0-9\]+,\ 1" } } */
+
+Int32x1
+test_corners_sisd_si (Int32x1 b)
+{
+  force_simd_si (b);
+  b = b >> 31;
+  b = b >> 0;
+  b += b >> 33; /* { dg-warning "right shift count >= width of type" } */
+  force_simd_si (b);
+
+  return b;
+}
+/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */
+/* { dg-final { scan-assembler "shl\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 1" } } */
+
+
+
+#define CHECK(var,val) \
+do                     \
+  {                    \
+    if (var != val)    \
+      abort();         \
+  }                    \
+while(0)
+
+UInt64x1 x = 0xC01dDeadBeefFaceull;
+UInt32x1 y = 0xDeadBeef;
+
+int
+main ()
+{
+  x = test_lshift_left_sisd_di (x, 8);
+  CHECK (x, 0xdeadbeefface0000ull);
+  x = test_lshift_right_int_di (x, 8);
+  CHECK (x, 0x0000deadbeeffaceull);
+  x = test_lshift_right_sisd_di (x, 8);
+  CHECK (x, 0x00000000deadbeefull);
+  x = test_lshift_left_int_di (x, 8);
+  CHECK (x, 0x0000deadbeef0000ull);
+  x = ~x;
+  x = test_ashift_right_int_di (x, 8);
+  CHECK (x, 0xffffffff21524110ull);
+  x = test_ashift_right_sisd_di (x, 8);
+  CHECK (x, 0xffffffffffff2152ull);
+  x = test_corners_sisd_di (x);
+  CHECK (x, 0xfffffffffffffffeull);
+
+  y = test_lshift_left_sisd_si (y, 4);
+  CHECK (y, 0xadbeef00);
+  y = test_lshift_right_int_si (y, 4);
+  CHECK (y, 0x00adbeef);
+  y = test_lshift_right_sisd_si (y, 4);
+  CHECK (y, 0x0000adbe);
+  y = test_lshift_left_int_si (y, 4);
+  CHECK (y, 0x00adbe00);
+  y = ~y;
+  y = test_ashift_right_int_si (y, 4);
+  CHECK (y, 0xffff5241);
+  y = test_ashift_right_sisd_si (y, 4);
+  CHECK (y, 0xffffff52);
+  y = test_corners_sisd_si (y);
+  CHECK (y, 0xfffffffe);
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha1_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha1_1.c
new file mode 100644
index 000000000..776753dcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha1_1.c
@@ -0,0 +1,55 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint32x4_t
+test_vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+  return vsha1cq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1c\\tq" 1 } } */
+
+uint32x4_t
+test_vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+  return vsha1mq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1m\\tq" 1 } } */
+
+uint32x4_t
+test_vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
+{
+  return vsha1pq_u32 (hash_abcd, hash_e, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha1p\\tq" 1 } } */
+
+uint32_t
+test_vsha1h_u32 (uint32_t hash_e)
+{
+  return vsha1h_u32 (hash_e);
+}
+
+/* { dg-final { scan-assembler-times "sha1h\\ts" 1 } } */
+
+uint32x4_t
+test_vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
+{
+  return vsha1su0q_u32 (w0_3, w4_7, w8_11);
+}
+
+/* { dg-final { scan-assembler-times "sha1su0\\tv" 1 } } */
+
+uint32x4_t
+test_vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)
+{
+  return vsha1su1q_u32 (tw0_3, w12_15);
+}
+
+/* { dg-final { scan-assembler-times "sha1su1\\tv" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha256_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha256_1.c
new file mode 100644
index 000000000..569817eb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sha256_1.c
@@ -0,0 +1,40 @@
+
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+crypto" } */
+
+#include "arm_neon.h"
+
+uint32x4_t
+test_vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
+{
+  return vsha256hq_u32 (hash_abcd, hash_efgh, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha256h\\tq" 1 } } */
+
+uint32x4_t
+test_vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
+{
+  return vsha256h2q_u32 (hash_efgh, hash_abcd, wk);
+}
+
+/* { dg-final { scan-assembler-times "sha256h2\\tq" 1 } } */
+
+uint32x4_t
+test_vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)
+{
+  return vsha256su0q_u32 (w0_3, w4_7);
+}
+
+/* { dg-final { scan-assembler-times "sha256su0\\tv" 1 } } */
+
+uint32x4_t
+test_vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)
+{
+  return vsha256su1q_u32 (tw0_3, w8_11, w12_15);
+}
+
+/* { dg-final { scan-assembler-times "sha256su1\\tv" 1 } } */
+
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sshr64_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sshr64_1.c
new file mode 100644
index 000000000..89c6096ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/sshr64_1.c
@@ -0,0 +1,115 @@
+/* Test SIMD shift works correctly.  */
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_sshr64 ()
+{
+  int64x1_t arg;
+  int64x1_t result;
+  int64_t got;
+  int64_t exp;
+  arg = vcreate_s64 (0x0000000080000000);
+  result = vshr_n_s64 (arg, 64);
+  got = vget_lane_s64 (result, 0);
+  exp = 0;
+  /* Expect: "result" = 0000000000000000.  */
+  if (exp != got)
+    return 1;
+  return 0;
+}
+
+int __attribute__ ((noinline))
+test_sshr64_neg ()
+{
+  int64x1_t arg;
+  int64x1_t result;
+  int64_t got;
+  int64_t exp;
+  arg = vcreate_s64 (0xffffffff80000000);
+  result = vshr_n_s64 (arg, 64);
+  got = vget_lane_s64 (result, 0);
+  exp = 0xffffffffffffffff;
+  /* Expect: "result" = -1.  */
+  if (exp != got)
+    return 1;
+  return 0;
+}
+
+int
+__attribute__ ((noinline))
+test_other ()
+{
+  int64x1_t arg;
+  int64x1_t result;
+  int64_t got;
+  int64_t exp;
+  arg = vcreate_s64 (0x0000000080000000);
+  result = vshr_n_s64 (arg, 4);
+  got = vget_lane_s64 (result, 0);
+  exp = 0x0000000008000000;
+  /* Expect: "result" = 0x0000000008000000.  */
+  if (exp != got)
+    return 1;
+  return 0;
+}
+
+int __attribute__ ((noinline))
+test_other_neg ()
+{
+  int64x1_t arg;
+  int64x1_t result;
+  int64_t got;
+  int64_t exp;
+  arg = vcreate_s64 (0xffffffff80000000);
+  result = vshr_n_s64 (arg, 4);
+  got = vget_lane_s64 (result, 0);
+  exp = 0xfffffffff8000000;
+  /* Expect: "result" = 0xfffffffff8000000.  */
+  if (exp != got)
+    return 1;
+  return 0;
+}
+
+int __attribute__ ((noinline))
+test_no_sshr0 ()
+{
+  int64x1_t arg;
+  int64x1_t result;
+  int64_t got;
+  int64_t exp;
+  arg = vcreate_s64 (0x0000000080000000);
+  result = vshr_n_s64 (arg, 0);
+  got = vget_lane_s64 (result, 0);
+  exp = 0x0000000080000000;
+  /* Expect: "result" = 0x0000000080000000.  */
+  if (exp != got)
+    return 1;
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "sshr\\td\[0-9\]+, d\[0-9\]+, 0" } } */
+int
+main ()
+{
+  if (test_sshr64 ())
+    abort ();
+  if (test_other ())
+    abort ();
+
+  if (test_sshr64_neg ())
+    abort ();
+  if (test_other_neg ())
+    abort ();
+
+  if (test_no_sshr0 ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs.c
new file mode 100644
index 000000000..2bf197585
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int z;
+int
+foo (int x, int y)
+{
+  int l = x - y;
+  if (l == 0)
+    return 5;
+
+  /* { dg-final { scan-assembler "subs\tw\[0-9\]" } } */
+  z = l ;
+  return 25;
+}
+
+typedef long long s64;
+
+s64 zz;
+s64
+foo2 (s64 x, s64 y)
+{
+  s64 l = x - y;
+  if (l < 0)
+    return 5;
+
+  /* { dg-final { scan-assembler "subs\tx\[0-9\]" } } */
+  zz = l ;
+  return 25;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs1.c
new file mode 100644
index 000000000..7e4b2b812
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs1.c
@@ -0,0 +1,149 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+subs_si_test1 (int a, int b, int c)
+{
+  int d = a - c;
+
+  /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_si_test2 (int a, int b, int c)
+{
+  int d = a - 0xff;
+
+  /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, #255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_si_test3 (int a, int b, int c)
+{
+  int d = a - (b << 3);
+
+  /* { dg-final { scan-assembler "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+subs_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - c;
+
+  /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+subs_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - 0xff;
+
+  /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, #255" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+subs_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - (b << 3);
+
+  /* { dg-final { scan-assembler "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = subs_si_test1 (29, 4, 5);
+  if (x != 33)
+    abort ();
+
+  x = subs_si_test1 (5, 2, 20);
+  if (x != 7)
+    abort ();
+
+  x = subs_si_test2 (29, 4, 5);
+  if (x != -217)
+    abort ();
+
+  x = subs_si_test2 (1024, 2, 20);
+  if (x != 791)
+    abort ();
+
+  x = subs_si_test3 (35, 4, 5);
+  if (x != 12)
+    abort ();
+
+  x = subs_si_test3 (5, 2, 20);
+  if (x != 11)
+    abort ();
+
+  y = subs_di_test1 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+
+  if (y != 0x45000002d)
+    abort ();
+
+  y = subs_di_test1 (0x5000500050005ll,
+		     0x2111211121112ll,
+		     0x0000000002020ll);
+  if (y != 0x7111711171117)
+    abort ();
+
+  y = subs_di_test2 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955050433)
+    abort ();
+
+  y = subs_di_test2 (0x130002900ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x955052d0a)
+    abort ();
+
+  y = subs_di_test3 (0x130000029ll,
+		     0x064000008ll,
+		     0x505050505ll);
+  if (y != 0x3790504f6)
+    abort ();
+
+  y = subs_di_test3 (0x130002900ll,
+		     0x088000008ll,
+		     0x505050505ll);
+  if (y != 0x27d052dcd)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs2.c
new file mode 100644
index 000000000..d90ead514
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs2.c
@@ -0,0 +1,155 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+subs_si_test1 (int a, int b, int c)
+{
+  int d = a - b;
+
+  /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_si_test2 (int a, int b, int c)
+{
+  int d = a - 0xfff;
+
+  /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, #4095" } } */
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, #4095" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_si_test3 (int a, int b, int c)
+{
+  int d = a - (b << 3);
+
+  /* { dg-final { scan-assembler-not "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "sub\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+subs_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - b;
+
+  /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+subs_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - 0x1000ll;
+
+  /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, #4096" } } */
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, #4096" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+s64
+subs_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a - (b << 3);
+
+  /* { dg-final { scan-assembler-not "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "sub\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = subs_si_test1 (29, 4, 5);
+  if (x != 34)
+    abort ();
+
+  x = subs_si_test1 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  x = subs_si_test2 (29, 4, 5);
+  if (x != 34)
+    abort ();
+
+  x = subs_si_test2 (1024, 2, 20);
+  if (x != 1044)
+    abort ();
+
+  x = subs_si_test3 (35, 4, 5);
+  if (x != 12)
+    abort ();
+
+  x = subs_si_test3 (5, 2, 20);
+  if (x != 25)
+    abort ();
+
+  y = subs_di_test1 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+
+  if (y != 0x63505052e)
+    abort ();
+
+  y = subs_di_test1 (0x5000500050005ll,
+		     0x2111211121112ll,
+		     0x0000000002020ll);
+  if (y != 0x5000500052025)
+    abort ();
+
+  y = subs_di_test2 (0x130000029ll,
+		     0x320000004ll,
+		     0x505050505ll);
+  if (y != 0x95504f532)
+    abort ();
+
+  y = subs_di_test2 (0x540004100ll,
+		     0x320000004ll,
+		     0x805050205ll);
+  if (y != 0x1065053309)
+    abort ();
+
+  y = subs_di_test3 (0x130000029ll,
+		     0x064000008ll,
+		     0x505050505ll);
+  if (y != 0x63505052e)
+    abort ();
+
+  y = subs_di_test3 (0x130002900ll,
+		     0x088000008ll,
+		     0x505050505ll);
+  if (y != 0x635052e05)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs3.c
new file mode 100644
index 000000000..90f20b843
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/subs3.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+typedef long long s64;
+
+int
+subs_ext (s64 a, int b, int c)
+{
+ s64 d = a - b;
+
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int
+subs_shift_ext (s64 a, int b, int c)
+{
+ s64 d = (a - ((s64)b << 3));
+
+  if (d == 0)
+    return a + c;
+  else
+    return b + d + c;
+}
+
+int main ()
+{
+  int x;
+  s64 y;
+
+  x = subs_ext (0x13000002ll, 41, 15);
+  if (x != 318767121)
+    abort ();
+
+  x = subs_ext (0x50505050ll, 29, 4);
+  if (x != 1347440724)
+    abort ();
+
+  x = subs_ext (0x12121212121ll, 2, 14);
+  if (x != 555819311)
+    abort ();
+
+  x = subs_shift_ext (0x123456789ll, 4, 12);
+  if (x != 591751033)
+    abort ();
+
+  x = subs_shift_ext (0x02020202ll, 9, 8);
+  if (x != 33685963)
+    abort ();
+
+  x = subs_shift_ext (0x987987987987ll, 23, 41);
+  if (x != -2020050673)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/table-intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/table-intrinsics.c
new file mode 100644
index 000000000..6281cdae7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/table-intrinsics.c
@@ -0,0 +1,439 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+int8x8_t
+tbl_tests8_ (int8x8_t tab, int8x8_t idx)
+{
+  return vtbl1_s8 (tab, idx);
+}
+
+uint8x8_t
+tbl_testu8_ (uint8x8_t tab, uint8x8_t idx)
+{
+  return vtbl1_u8 (tab, idx);
+}
+
+poly8x8_t
+tbl_testp8_ (poly8x8_t tab, uint8x8_t idx)
+{
+  return vtbl1_p8 (tab, idx);
+}
+
+int8x8_t
+tbl_tests8_2 (int8x8x2_t tab, int8x8_t idx)
+{
+  return vtbl2_s8 (tab, idx);
+}
+
+uint8x8_t
+tbl_testu8_2 (uint8x8x2_t tab, uint8x8_t idx)
+{
+  return vtbl2_u8 (tab, idx);
+}
+
+poly8x8_t
+tbl_testp8_2 (poly8x8x2_t tab, uint8x8_t idx)
+{
+  return vtbl2_p8 (tab, idx);
+}
+
+int8x8_t
+tbl_tests8_3 (int8x8x3_t tab, int8x8_t idx)
+{
+  return vtbl3_s8 (tab, idx);
+}
+
+uint8x8_t
+tbl_testu8_3 (uint8x8x3_t tab, uint8x8_t idx)
+{
+  return vtbl3_u8 (tab, idx);
+}
+
+poly8x8_t
+tbl_testp8_3 (poly8x8x3_t tab, uint8x8_t idx)
+{
+  return vtbl3_p8 (tab, idx);
+}
+
+int8x8_t
+tbl_tests8_4 (int8x8x4_t tab, int8x8_t idx)
+{
+  return vtbl4_s8 (tab, idx);
+}
+
+uint8x8_t
+tbl_testu8_4 (uint8x8x4_t tab, uint8x8_t idx)
+{
+  return vtbl4_u8 (tab, idx);
+}
+
+poly8x8_t
+tbl_testp8_4 (poly8x8x4_t tab, uint8x8_t idx)
+{
+  return vtbl4_p8 (tab, idx);
+}
+
+int8x8_t
+tb_tests8_ (int8x8_t r, int8x8_t tab, int8x8_t idx)
+{
+  return vtbx1_s8 (r, tab, idx);
+}
+
+uint8x8_t
+tb_testu8_ (uint8x8_t r, uint8x8_t tab, uint8x8_t idx)
+{
+  return vtbx1_u8 (r, tab, idx);
+}
+
+poly8x8_t
+tb_testp8_ (poly8x8_t r, poly8x8_t tab, uint8x8_t idx)
+{
+  return vtbx1_p8 (r, tab, idx);
+}
+
+int8x8_t
+tb_tests8_2 (int8x8_t r, int8x8x2_t tab, int8x8_t idx)
+{
+  return vtbx2_s8 (r, tab, idx);
+}
+
+uint8x8_t
+tb_testu8_2 (uint8x8_t r, uint8x8x2_t tab, uint8x8_t idx)
+{
+  return vtbx2_u8 (r, tab, idx);
+}
+
+poly8x8_t
+tb_testp8_2 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx)
+{
+  return vtbx2_p8 (r, tab, idx);
+}
+
+int8x8_t
+tb_tests8_3 (int8x8_t r, int8x8x3_t tab, int8x8_t idx)
+{
+  return vtbx3_s8 (r, tab, idx);
+}
+
+uint8x8_t
+tb_testu8_3 (uint8x8_t r, uint8x8x3_t tab, uint8x8_t idx)
+{
+  return vtbx3_u8 (r, tab, idx);
+}
+
+poly8x8_t
+tb_testp8_3 (poly8x8_t r, poly8x8x3_t tab, uint8x8_t idx)
+{
+  return vtbx3_p8 (r, tab, idx);
+}
+
+int8x8_t
+tb_tests8_4 (int8x8_t r, int8x8x4_t tab, int8x8_t idx)
+{
+  return vtbx4_s8 (r, tab, idx);
+}
+
+uint8x8_t
+tb_testu8_4 (uint8x8_t r, uint8x8x4_t tab, uint8x8_t idx)
+{
+  return vtbx4_u8 (r, tab, idx);
+}
+
+poly8x8_t
+tb_testp8_4 (poly8x8_t r, poly8x8x4_t tab, uint8x8_t idx)
+{
+  return vtbx4_p8 (r, tab, idx);
+}
+
+int8x8_t
+qtbl_tests8_ (int8x16_t tab, uint8x8_t idx)
+{
+  return vqtbl1_s8 (tab, idx);
+}
+
+uint8x8_t
+qtbl_testu8_ (uint8x16_t tab, uint8x8_t idx)
+{
+  return vqtbl1_u8 (tab, idx);
+}
+
+poly8x8_t
+qtbl_testp8_ (poly8x16_t tab, uint8x8_t idx)
+{
+  return vqtbl1_p8 (tab, idx);
+}
+
+int8x8_t
+qtbl_tests8_2 (int8x16x2_t tab, uint8x8_t idx)
+{
+  return vqtbl2_s8 (tab, idx);
+}
+
+uint8x8_t
+qtbl_testu8_2 (uint8x16x2_t tab, uint8x8_t idx)
+{
+  return vqtbl2_u8 (tab, idx);
+}
+
+poly8x8_t
+qtbl_testp8_2 (poly8x16x2_t tab, uint8x8_t idx)
+{
+  return vqtbl2_p8 (tab, idx);
+}
+
+int8x8_t
+qtbl_tests8_3 (int8x16x3_t tab, uint8x8_t idx)
+{
+  return vqtbl3_s8 (tab, idx);
+}
+
+uint8x8_t
+qtbl_testu8_3 (uint8x16x3_t tab, uint8x8_t idx)
+{
+  return vqtbl3_u8 (tab, idx);
+}
+
+poly8x8_t
+qtbl_testp8_3 (poly8x16x3_t tab, uint8x8_t idx)
+{
+  return vqtbl3_p8 (tab, idx);
+}
+
+int8x8_t
+qtbl_tests8_4 (int8x16x4_t tab, uint8x8_t idx)
+{
+  return vqtbl4_s8 (tab, idx);
+}
+
+uint8x8_t
+qtbl_testu8_4 (uint8x16x4_t tab, uint8x8_t idx)
+{
+  return vqtbl4_u8 (tab, idx);
+}
+
+poly8x8_t
+qtbl_testp8_4 (poly8x16x4_t tab, uint8x8_t idx)
+{
+  return vqtbl4_p8 (tab, idx);
+}
+
+int8x8_t
+qtb_tests8_ (int8x8_t r, int8x16_t tab, uint8x8_t idx)
+{
+  return vqtbx1_s8 (r, tab, idx);
+}
+
+uint8x8_t
+qtb_testu8_ (uint8x8_t r, uint8x16_t tab, uint8x8_t idx)
+{
+  return vqtbx1_u8 (r, tab, idx);
+}
+
+poly8x8_t
+qtb_testp8_ (poly8x8_t r, poly8x16_t tab, uint8x8_t idx)
+{
+  return vqtbx1_p8 (r, tab, idx);
+}
+
+int8x8_t
+qtb_tests8_2 (int8x8_t r, int8x16x2_t tab, uint8x8_t idx)
+{
+  return vqtbx2_s8 (r, tab, idx);
+}
+
+uint8x8_t
+qtb_testu8_2 (uint8x8_t r, uint8x16x2_t tab, uint8x8_t idx)
+{
+  return vqtbx2_u8 (r, tab, idx);
+}
+
+poly8x8_t
+qtb_testp8_2 (poly8x8_t r, poly8x16x2_t tab, uint8x8_t idx)
+{
+  return vqtbx2_p8 (r, tab, idx);
+}
+
+int8x8_t
+qtb_tests8_3 (int8x8_t r, int8x16x3_t tab, uint8x8_t idx)
+{
+  return vqtbx3_s8 (r, tab, idx);
+}
+
+uint8x8_t
+qtb_testu8_3 (uint8x8_t r, uint8x16x3_t tab, uint8x8_t idx)
+{
+  return vqtbx3_u8 (r, tab, idx);
+}
+
+poly8x8_t
+qtb_testp8_3 (poly8x8_t r, poly8x16x3_t tab, uint8x8_t idx)
+{
+  return vqtbx3_p8 (r, tab, idx);
+}
+
+int8x8_t
+qtb_tests8_4 (int8x8_t r, int8x16x4_t tab, uint8x8_t idx)
+{
+  return vqtbx4_s8 (r, tab, idx);
+}
+
+uint8x8_t
+qtb_testu8_4 (uint8x8_t r, uint8x16x4_t tab, uint8x8_t idx)
+{
+  return vqtbx4_u8 (r, tab, idx);
+}
+
+poly8x8_t
+qtb_testp8_4 (poly8x8_t r, poly8x16x4_t tab, uint8x8_t idx)
+{
+  return vqtbx4_p8 (r, tab, idx);
+}
+
+int8x16_t
+qtblq_tests8_ (int8x16_t tab, uint8x16_t idx)
+{
+  return vqtbl1q_s8 (tab, idx);
+}
+
+uint8x16_t
+qtblq_testu8_ (uint8x16_t tab, uint8x16_t idx)
+{
+  return vqtbl1q_u8 (tab, idx);
+}
+
+poly8x16_t
+qtblq_testp8_ (poly8x16_t tab, uint8x16_t idx)
+{
+  return vqtbl1q_p8 (tab, idx);
+}
+
+int8x16_t
+qtblq_tests8_2 (int8x16x2_t tab, uint8x16_t idx)
+{
+  return vqtbl2q_s8 (tab, idx);
+}
+
+uint8x16_t
+qtblq_testu8_2 (uint8x16x2_t tab, uint8x16_t idx)
+{
+  return vqtbl2q_u8 (tab, idx);
+}
+
+poly8x16_t
+qtblq_testp8_2 (poly8x16x2_t tab, uint8x16_t idx)
+{
+  return vqtbl2q_p8 (tab, idx);
+}
+
+int8x16_t
+qtblq_tests8_3 (int8x16x3_t tab, uint8x16_t idx)
+{
+  return vqtbl3q_s8 (tab, idx);
+}
+
+uint8x16_t
+qtblq_testu8_3 (uint8x16x3_t tab, uint8x16_t idx)
+{
+  return vqtbl3q_u8 (tab, idx);
+}
+
+poly8x16_t
+qtblq_testp8_3 (poly8x16x3_t tab, uint8x16_t idx)
+{
+  return vqtbl3q_p8 (tab, idx);
+}
+
+int8x16_t
+qtblq_tests8_4 (int8x16x4_t tab, uint8x16_t idx)
+{
+  return vqtbl4q_s8 (tab, idx);
+}
+
+uint8x16_t
+qtblq_testu8_4 (uint8x16x4_t tab, uint8x16_t idx)
+{
+  return vqtbl4q_u8 (tab, idx);
+}
+
+poly8x16_t
+qtblq_testp8_4 (poly8x16x4_t tab, uint8x16_t idx)
+{
+  return vqtbl4q_p8 (tab, idx);
+}
+
+int8x16_t
+qtbxq_tests8_ (int8x16_t r, int8x16_t tab, uint8x16_t idx)
+{
+  return vqtbx1q_s8 (r, tab, idx);
+}
+
+uint8x16_t
+qtbxq_testu8_ (uint8x16_t r, uint8x16_t tab, uint8x16_t idx)
+{
+  return vqtbx1q_u8 (r, tab, idx);
+}
+
+poly8x16_t
+qtbxq_testp8_ (poly8x16_t r, poly8x16_t tab, uint8x16_t idx)
+{
+  return vqtbx1q_p8 (r, tab, idx);
+}
+
+int8x16_t
+qtbxq_tests8_2 (int8x16_t r, int8x16x2_t tab, uint8x16_t idx)
+{
+  return vqtbx2q_s8 (r, tab, idx);
+}
+
+uint8x16_t
+qtbxq_testu8_2 (uint8x16_t r, uint8x16x2_t tab, uint8x16_t idx)
+{
+  return vqtbx2q_u8 (r, tab, idx);
+}
+
+poly8x16_t
+qtbxq_testp8_2 (poly8x16_t r, poly8x16x2_t tab, uint8x16_t idx)
+{
+  return vqtbx2q_p8 (r, tab, idx);
+}
+
+int8x16_t
+qtbxq_tests8_3 (int8x16_t r, int8x16x3_t tab, uint8x16_t idx)
+{
+  return vqtbx3q_s8 (r, tab, idx);
+}
+
+uint8x16_t
+qtbxq_testu8_3 (uint8x16_t r, uint8x16x3_t tab, uint8x16_t idx)
+{
+  return vqtbx3q_u8 (r, tab, idx);
+}
+
+poly8x16_t
+qtbxq_testp8_3 (poly8x16_t r, poly8x16x3_t tab, uint8x16_t idx)
+{
+  return vqtbx3q_p8 (r, tab, idx);
+}
+
+int8x16_t
+qtbxq_tests8_4 (int8x16_t r, int8x16x4_t tab, uint8x16_t idx)
+{
+  return vqtbx4q_s8 (r, tab, idx);
+}
+
+uint8x16_t
+qtbxq_testu8_4 (uint8x16_t r, uint8x16x4_t tab, uint8x16_t idx)
+{
+  return vqtbx4q_u8 (r, tab, idx);
+}
+
+poly8x16_t
+qtbxq_testp8_4 (poly8x16_t r, poly8x16x4_t tab, uint8x16_t idx)
+{
+  return vqtbx4q_p8 (r, tab, idx);
+}
+
+/* { dg-final { scan-assembler-times "tbl v" 42} }  */
+/* { dg-final { scan-assembler-times "tbx v" 30} }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-1.c
new file mode 100644
index 000000000..e44ca6d4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-1.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-no-clobber-lr.c"
+
+/* omit-frame-pointer is FALSE.
+   omit-leaf-frame-pointer is FALSE.
+   LR is not being clobbered in the leaf.
+
+   With no frame pointer omissions, we expect a frame record
+   for main and the leaf.  */
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-2.c
new file mode 100644
index 000000000..40e483526
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-2.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-no-clobber-lr.c"
+
+/* omit-frame-pointer is TRUE.
+   omit-leaf-frame-pointer is false, but irrelevant due to omit-frame-pointer.
+   LR is not being clobbered in the leaf.
+
+   Since we asked to have no frame pointers anywhere, we expect no frame
+   record in main or the leaf.  */
+
+/* { dg-final { scan-assembler-not "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-3.c
new file mode 100644
index 000000000..98cb2e0b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-3.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-no-clobber-lr.c"
+
+/* omit-frame-pointer is TRUE.
+   omit-leaf-frame-pointer is true, but irrelevant due to omit-frame-pointer.
+   LR is not being clobbered in the leaf.
+
+   Since we asked to have no frame pointers anywhere, we expect no frame
+   record in main or the leaf.  */
+
+/* { dg-final { scan-assembler-not "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-4.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-4.c
new file mode 100644
index 000000000..4143a7a9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-4.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -momit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-no-clobber-lr.c"
+
+/* omit-frame-pointer is FALSE.
+   omit-leaf-frame-pointer is TRUE.
+   LR is not being clobbered in the leaf.
+
+   Unless we are removing all frame records, it's OK to remove the frame
+   record for a leaf where LR is not clobbered.  Therefore, we expect a
+   frame record only in main.  */
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 1 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-5.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-5.c
new file mode 100644
index 000000000..c22bdc304
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-5.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-clobber-lr.c"
+
+/* omit-frame-pointer is FALSE.
+   omit-leaf-frame-pointer is FALSE.
+   LR is being clobbered in the leaf.
+
+   With no frame pointer omissions, we expect a frame record for main
+   and the leaf.  */
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-6.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-6.c
new file mode 100644
index 000000000..e08ee43e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-6.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-clobber-lr.c"
+
+/* omit-frame-pointer is TRUE.
+   omit-leaf-frame-pointer is false, but irrelevant due to omit-frame-pointer.
+   LR is being clobbered in the leaf.
+
+   Since we asked to have no frame pointers anywhere, we expect no frame
+   record in main or the leaf.  */
+
+/* { dg-final { scan-assembler-not "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-7.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-7.c
new file mode 100644
index 000000000..e8f7cabe7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-7.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-clobber-lr.c"
+
+/* omit-frame-pointer is TRUE.
+   omit-leaf-frame-pointer is true, but irrelevant due to omit-frame-pointer.
+   LR is being clobbered in the leaf.
+
+   Since we asked to have no frame pointers anywhere, we expect no frame
+   record in main or the leaf.  */
+
+/* { dg-final { scan-assembler-not "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-8.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-8.c
new file mode 100644
index 000000000..c09b68759
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-framepointer-8.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -momit-leaf-frame-pointer -fno-inline --save-temps" } */
+
+#include "asm-adder-clobber-lr.c"
+
+/* omit-frame-pointer is FALSE.
+   omit-leaf-frame-pointer is TRUE.
+   LR is being clobbered in the leaf.
+
+   Unless we are removing all frame records (which we aren't), it's
+   not OK to remove the frame record for a leaf where LR is clobbered.
+   Therefore, we expect a frame record in main and leaf.  */
+
+/* { dg-final { scan-assembler-times "stp\tx29, x30, \\\[sp, -\[0-9\]+\\\]!" 2 } } */
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c
new file mode 100644
index 000000000..bb68e0a56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/test-ptr-arg-on-stack-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline" } */
+
+/* Test pass-by-reference and pointer-typed argument passing on stack.
+   This test shall pass on any of the following four combinitions:
+    {big-endian, little-endian} {LP64, ILP32}.  */
+
+struct s5
+{
+  double a;
+  double b;
+  double c;
+  double d;
+  double e;
+} gS = {1.0, 2.0, 3.0, 4.0, 5.0};
+
+double  __attribute__ ((noinline))
+foo (struct s5 p1, struct s5 p2, struct s5 p3, struct s5 p4,
+     struct s5 p5, struct s5 p6, struct s5 p7, struct s5 p8,
+     struct s5 p9)
+{
+  asm ("");
+  return p9.c;
+}
+
+void abort (void);
+int printf (const char *, ...);
+
+int main (void)
+{
+  printf ("Here we print out some values and more importantly hope that"
+	  " the stack is getting a bit dirty for the bug to manifest itself"
+	  "\n\t%f, %f, %f, %f, %f\n", gS.a, gS.b, gS.c, gS.d, gS.e);
+
+  if (foo (gS, gS, gS, gS, gS, gS, gS, gS, gS) != 3.0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst-1.c
new file mode 100644
index 000000000..b37c522e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst-1.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+volatile unsigned int w0, w1;
+volatile int result;
+
+void test_si() {
+  /* { dg-final { scan-assembler "tst\tw\[0-9\]*, w\[0-9\]*\n" } } */
+  result = !(w0 & w1);
+  /* { dg-final { scan-assembler "tst\tw\[0-9\]*, \(0x\[0-9a-fA-F\]+\)|\(\[0-9\]+\)" } } */
+  result = !(w0 & 0x00f0);
+  /* { dg-final { scan-assembler "tst\tw\[0-9\]*.*lsl 4" } } */
+  result = !(w0 & (w1 << 4));
+}
+
+void test_si_tbnz() {
+  /* { dg-final { scan-assembler "tbnz\t\[wx\]\[0-9\]*" } } */
+jumpto:
+  if (w0 & 0x08) goto jumpto;
+}
+
+void test_si_tbz() {
+  /* { dg-final { scan-assembler "tbz\t\[wx\]\[0-9\]*" } } */
+jumpto:
+  if (!(w1 & 0x08)) goto jumpto;
+}
+
+volatile unsigned long long x0, x1;
+
+void test_di() {
+  /* { dg-final { scan-assembler "tst\tx\[0-9\]*, x\[0-9\]*\n" } } */
+  result = !(x0 & x1);
+  /* { dg-final { scan-assembler "tst\tx\[0-9\]*, \(0x\[0-9a-fA-F\]+\)|\(\[0-9\]+\)" } } */
+  result = !(x0 & 0x00f0);
+  /* { dg-final { scan-assembler "tst\tx\[0-9\]*.*lsl 4" } } */
+  result = !(x0 & (x1 << 4));
+}
+
+void test_di_tbnz() {
+  /* { dg-final { scan-assembler "tbnz\tx\[0-9\]*" } } */
+jumpto:
+  if (x0 & 0x08) goto jumpto;
+}
+
+void test_di_tbz() {
+  /* { dg-final { scan-assembler "tbz\tx\[0-9\]*" } } */
+jumpto:
+  if (!(x1 & 0x08)) goto jumpto;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_1.c
new file mode 100644
index 000000000..4838b1bf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_1.c
@@ -0,0 +1,150 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+tst_si_test1 (int a, int b, int c)
+{
+  int d = a & b;
+
+  /* { dg-final { scan-assembler-times "tst\tw\[0-9\]+, w\[0-9\]+" 2 } } */
+  if (d == 0)
+    return 12;
+  else
+    return 18;
+}
+
+int
+tst_si_test2 (int a, int b, int c)
+{
+  int d = a & 0x99999999;
+
+  /* { dg-final { scan-assembler "tst\tw\[0-9\]+, -1717986919" } } */
+  if (d == 0)
+    return 12;
+  else
+    return 18;
+}
+
+int
+tst_si_test3 (int a, int b, int c)
+{
+  int d = a & (b << 3);
+
+  /* { dg-final { scan-assembler "tst\tw\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return 12;
+  else
+    return 18;
+}
+
+typedef long long s64;
+
+s64
+tst_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & b;
+
+  /* { dg-final { scan-assembler-times "tst\tx\[0-9\]+, x\[0-9\]+" 2 } } */
+  if (d == 0)
+    return 12;
+  else
+    return 18;
+}
+
+s64
+tst_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & 0xaaaaaaaaaaaaaaaall;
+
+  /* { dg-final { scan-assembler "tst\tx\[0-9\]+, -6148914691236517206" } } */
+  if (d == 0)
+    return 12;
+  else
+    return 18;
+}
+
+s64
+tst_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & (b << 3);
+
+  /* { dg-final { scan-assembler "tst\tx\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d == 0)
+    return 12;
+  else
+    return 18;
+}
+
+int
+main ()
+{
+  int x;
+  s64 y;
+
+  x = tst_si_test1 (29, 4, 5);
+  if (x != 18)
+    abort ();
+
+  x = tst_si_test1 (5, 2, 20);
+  if (x != 12)
+    abort ();
+
+  x = tst_si_test2 (29, 4, 5);
+  if (x != 18)
+    abort ();
+
+  x = tst_si_test2 (1024, 2, 20);
+  if (x != 12)
+    abort ();
+
+  x = tst_si_test3 (35, 4, 5);
+  if (x != 18)
+    abort ();
+
+  x = tst_si_test3 (5, 2, 20);
+  if (x != 12)
+    abort ();
+
+  y = tst_di_test1 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+
+  if (y != 18)
+    abort ();
+
+  y = tst_di_test1 (0x5000500050005ll,
+                     0x2111211121112ll,
+                     0x0000000002020ll);
+  if (y != 12)
+    abort ();
+
+  y = tst_di_test2 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+  if (y != 18)
+    abort ();
+
+  y = tst_di_test2 (0x540004100ll,
+                     0x320000004ll,
+                     0x805050205ll);
+  if (y != 12)
+    abort ();
+
+  y = tst_di_test3 (0x130000029ll,
+                     0x064000008ll,
+                     0x505050505ll);
+  if (y != 18)
+    abort ();
+
+  y = tst_di_test3 (0x130002900ll,
+                     0x088000008ll,
+                     0x505050505ll);
+  if (y != 12)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_2.c
new file mode 100644
index 000000000..1e8090464
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/tst_2.c
@@ -0,0 +1,156 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+tst_si_test1 (int a, int b, int c)
+{
+  int d = a & b;
+
+  /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+  /* { dg-final { scan-assembler-times "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */
+  if (d <= 0)
+    return 12;
+  else
+    return 18;
+}
+
+int
+tst_si_test2 (int a, int b, int c)
+{
+  int d = a & 0x99999999;
+
+  /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, -1717986919" } } */
+  if (d <= 0)
+    return 12;
+  else
+    return 18;
+}
+
+int
+tst_si_test3 (int a, int b, int c)
+{
+  int d = a & (b << 3);
+
+  /* { dg-final { scan-assembler-not "tst\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return 12;
+  else
+    return 18;
+}
+
+typedef long long s64;
+
+s64
+tst_di_test1 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & b;
+
+  /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+  /* { dg-final { scan-assembler-times "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */
+  if (d <= 0)
+    return 12;
+  else
+    return 18;
+}
+
+s64
+tst_di_test2 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & 0xaaaaaaaaaaaaaaaall;
+
+  /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, -6148914691236517206" } } */
+  if (d <= 0)
+    return 12;
+  else
+    return 18;
+}
+
+s64
+tst_di_test3 (s64 a, s64 b, s64 c)
+{
+  s64 d = a & (b << 3);
+
+  /* { dg-final { scan-assembler-not "tst\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  /* { dg-final { scan-assembler "and\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */
+  if (d <= 0)
+    return 12;
+  else
+    return 18;
+}
+
+int
+main ()
+{
+  int x;
+  s64 y;
+
+  x = tst_si_test1 (29, 4, 5);
+  if (x != 18)
+    abort ();
+
+  x = tst_si_test1 (5, 2, 20);
+  if (x != 12)
+    abort ();
+
+  x = tst_si_test2 (29, 4, 5);
+  if (x != 18)
+    abort ();
+
+  x = tst_si_test2 (1024, 2, 20);
+  if (x != 12)
+    abort ();
+
+  x = tst_si_test3 (35, 4, 5);
+  if (x != 18)
+    abort ();
+
+  x = tst_si_test3 (5, 2, 20);
+  if (x != 12)
+    abort ();
+
+  y = tst_di_test1 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+
+  if (y != 18)
+    abort ();
+
+  y = tst_di_test1 (0x5000500050005ll,
+                     0x2111211121112ll,
+                     0x0000000002020ll);
+  if (y != 12)
+    abort ();
+
+  y = tst_di_test2 (0x130000029ll,
+                     0x320000004ll,
+                     0x505050505ll);
+  if (y != 18)
+    abort ();
+
+  y = tst_di_test2 (0x540004100ll,
+                     0x320000004ll,
+                     0x805050205ll);
+  if (y != 12)
+    abort ();
+
+  y = tst_di_test3 (0x130000029ll,
+                     0x064000008ll,
+                     0x505050505ll);
+  if (y != 18)
+    abort ();
+
+  y = tst_di_test3 (0x130002900ll,
+                     0x088000008ll,
+                     0x505050505ll);
+  if (y != 12)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ushr64_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
new file mode 100644
index 000000000..b1c741dac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/ushr64_1.c
@@ -0,0 +1,84 @@
+/* Test logical SIMD shift works correctly.  */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_64 (uint64x1_t passed, uint64_t expected)
+{
+  return vget_lane_u64 (vshr_n_u64 (passed, 64), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_4 (uint64x1_t passed, uint64_t expected)
+{
+  return vget_lane_u64 (vshr_n_u64 (passed, 4), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshr_n_u64_0 (uint64x1_t passed, uint64_t expected)
+{
+  return vget_lane_u64 (vshr_n_u64 (passed, 0), 0) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_64 (uint64_t passed, uint64_t expected)
+{
+  return vshrd_n_u64 (passed, 64) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_4 (uint64_t passed, uint64_t expected)
+{
+  return vshrd_n_u64 (passed, 4) != expected;
+}
+
+int __attribute__ ((noinline))
+test_vshrd_n_u64_0 (uint64_t passed, uint64_t expected)
+{
+  return vshrd_n_u64 (passed, 0) != expected;
+}
+
+/* { dg-final { scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 64" 2 } } */
+/* { dg-final { (scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 4" 2)  || \
+   (scan-assembler-times "lsr\\tx\[0-9\]+, x\[0-9\]+, 4" 2) } } */
+/* { dg-final { scan-assembler-not "ushr\\td\[0-9\]+, d\[0-9\]+, 0" } } */
+
+int
+main (int argc, char *argv[])
+{
+  /* Testing vshr_n_u64.  */
+  if (test_vshr_n_u64_64 (vcreate_u64 (0x0000000080000000), 0))
+    abort ();
+  if (test_vshr_n_u64_64 (vcreate_u64 (0xffffffff80000000), 0))
+    abort ();
+
+  if (test_vshr_n_u64_4 (vcreate_u64 (0x0000000080000000), 0x0000000008000000))
+    abort ();
+  if (test_vshr_n_u64_4 (vcreate_u64 (0xffffffff80000000), 0x0ffffffff8000000))
+    abort ();
+
+  if (test_vshr_n_u64_0 (vcreate_u64 (0x0000000080000000), 0x0000000080000000))
+    abort ();
+
+  /* Testing vshrd_n_u64.  */
+  if (test_vshrd_n_u64_64 (0x0000000080000000, 0))
+    abort ();
+  if (test_vshrd_n_u64_64 (0xffffffff80000000, 0))
+    abort ();
+
+  if (test_vshrd_n_u64_4 (0x0000000080000000, 0x0000000008000000))
+    abort ();
+  if (test_vshrd_n_u64_4 (0xffffffff80000000, 0x0ffffffff8000000))
+    abort ();
+
+  if (test_vshrd_n_u64_0 (0x0000000080000000, 0x0000000080000000))
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c
new file mode 100644
index 000000000..b34738c00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c
@@ -0,0 +1,101 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define ETYPE(size) int##size##_t
+#define VTYPE(size, lanes) int##size##x##lanes##_t
+
+#define TEST_VABS(q, size, lanes)				\
+static void							\
+test_vabs##q##_##size (ETYPE (size) * res,			\
+			const ETYPE (size) *in1)		\
+{								\
+  VTYPE (size, lanes) a = vld1##q##_s##size (res);		\
+  VTYPE (size, lanes) b = vld1##q##_s##size (in1);		\
+  a = vabs##q##_s##size (b);					\
+  vst1##q##_s##size (res, a);					\
+}
+
+#define BUILD_VARS(width, n_lanes, n_half_lanes)		\
+TEST_VABS (, width, n_half_lanes)				\
+TEST_VABS (q, width, n_lanes)					\
+
+BUILD_VARS (64, 2, 1)
+BUILD_VARS (32, 4, 2)
+BUILD_VARS (16, 8, 4)
+BUILD_VARS (8, 16, 8)
+
+#define POOL1  {-10}
+#define POOL2  {2, -10}
+#define POOL4  {0, -10, 2, -3}
+#define POOL8  {0, -10, 2, -3, 4, -50, 6, -70}
+#define POOL16 {0, -10, 2, -3, 4, -50, 6, -70,			\
+		-5, 10, -2, 3, -4, 50, -6, 70}
+
+#define EXPECTED1  {10}
+#define EXPECTED2  {2, 10}
+#define EXPECTED4  {0, 10, 2, 3}
+#define EXPECTED8  {0, 10, 2, 3, 4, 50, 6, 70}
+#define EXPECTED16 {0, 10, 2, 3, 4, 50, 6, 70,			\
+		    5, 10, 2, 3, 4, 50, 6, 70}
+
+#define BUILD_TEST(size, lanes_64, lanes_128)			\
+static void							\
+test_##size (void)						\
+{								\
+  int i;							\
+  ETYPE (size) pool1[lanes_64] = POOL##lanes_64;		\
+  ETYPE (size) res1[lanes_64] = {0};				\
+  ETYPE (size) expected1[lanes_64] = EXPECTED##lanes_64;	\
+  ETYPE (size) pool2[lanes_128] = POOL##lanes_128;		\
+  ETYPE (size) res2[lanes_128] = {0};				\
+  ETYPE (size) expected2[lanes_128] = EXPECTED##lanes_128;	\
+								\
+  /* Forcefully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vabs_##size (res1, pool1);				\
+  for (i = 0; i < lanes_64; i++)				\
+    if (res1[i] != expected1[i])				\
+      abort ();							\
+								\
+  /* Forcefully avoid optimization.  */				\
+  asm volatile ("" : : : "memory");				\
+  test_vabsq_##size (res2, pool2);				\
+  for (i = 0; i < lanes_128; i++)				\
+    if (res2[i] != expected2[i])				\
+      abort ();							\
+}
+
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+BUILD_TEST (8 , 8, 16)
+
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+BUILD_TEST (16, 4, 8)
+
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+BUILD_TEST (32, 2, 4)
+
+/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+BUILD_TEST (64, 1, 2)
+
+#undef BUILD_TEST
+
+#define BUILD_TEST(size) test_##size ()
+
+int
+main (int argc, char **argv)
+{
+  BUILD_TEST (8);
+  BUILD_TEST (16);
+  BUILD_TEST (32);
+  BUILD_TEST (64);
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vadd_f64.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vadd_f64.c
new file mode 100644
index 000000000..c3bf73495
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vadd_f64.c
@@ -0,0 +1,114 @@
+/* Test vadd works correctly.  */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include <arm_neon.h>
+
+#define FLT_EPSILON __FLT_EPSILON__
+#define DBL_EPSILON __DBL_EPSILON__
+
+#define TESTA0 0.33333
+#define TESTA1 -1.7777
+#define TESTA2 0
+#define TESTA3 1.23456
+/* 2^54, double has 53 significand bits
+   according to Double-precision floating-point format.  */
+#define TESTA4 18014398509481984
+#define TESTA5 (1.0 / TESTA4)
+
+#define TESTB0 0.66667
+#define TESTB1 2
+#define TESTB2 0
+#define TESTB3 -2
+#define TESTB4 1.0
+#define TESTB5 2.0
+
+#define ANSW0 1
+#define ANSW1 0.2223
+#define ANSW2 0
+#define ANSW3 -0.76544
+#define ANSW4 TESTA4
+#define ANSW5 2.0
+
+extern void abort (void);
+
+#define EPSILON __DBL_EPSILON__
+#define ABS(a) __builtin_fabs (a)
+#define ISNAN(a) __builtin_isnan (a)
+#define FP_equals(a, b, epsilon)			\
+  (							\
+   ((a) == (b))						\
+    || (ISNAN (a) && ISNAN (b))				\
+    || (ABS (a - b) < epsilon)				\
+   )
+
+int
+test_vadd_f64 ()
+{
+  float64x1_t a;
+  float64x1_t b;
+  float64x1_t c;
+
+  a = TESTA0;
+  b = TESTB0;
+  c = ANSW0;
+
+  a = vadd_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA1;
+  b = TESTB1;
+  c = ANSW1;
+
+  a = vadd_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA2;
+  b = TESTB2;
+  c = ANSW2;
+
+  a = vadd_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA3;
+  b = TESTB3;
+  c = ANSW3;
+
+  a = vadd_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA4;
+  b = TESTB4;
+  c = ANSW4;
+
+  a = vadd_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA5;
+  b = TESTB5;
+  c = ANSW5;
+
+  a = vadd_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fadd\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 6 } } */
+
+int
+main (int argc, char **argv)
+{
+  if (test_vadd_f64 ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c
new file mode 100644
index 000000000..11fa98420
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic-compile.c
@@ -0,0 +1,11 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+#include "vaddv-intrinsic.x"
+
+/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+"} } */
+/* { dg-final { scan-assembler-times "faddp\\tv\[0-9\]+\.4s" 2} } */
+/* { dg-final { scan-assembler "faddp\\td\[0-9\]+"} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c
new file mode 100644
index 000000000..f6e0829a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.c
@@ -0,0 +1,28 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+#include "vaddv-intrinsic.x"
+
+int
+main (void)
+{
+  const float32_t pool_v2sf[] = {4.0f, 9.0f};
+  const float32_t pool_v4sf[] = {4.0f, 9.0f, 16.0f, 25.0f};
+  const float64_t pool_v2df[] = {4.0, 9.0};
+
+  if (test_vaddv_v2sf (pool_v2sf) != 13.0f)
+    abort ();
+
+  if (test_vaddv_v4sf (pool_v4sf) != 54.0f)
+    abort ();
+
+  if (test_vaddv_v2df (pool_v2df) != 13.0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x
new file mode 100644
index 000000000..7bf38ca0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vaddv-intrinsic.x
@@ -0,0 +1,27 @@
+
+float32_t
+test_vaddv_v2sf (const float32_t *pool)
+{
+  float32x2_t val;
+
+  val = vld1_f32 (pool);
+  return vaddv_f32 (val);
+}
+
+float32_t
+test_vaddv_v4sf (const float32_t *pool)
+{
+  float32x4_t val;
+
+  val = vld1q_f32 (pool);
+  return vaddvq_f32 (val);
+}
+
+float64_t
+test_vaddv_v2df (const float64_t *pool)
+{
+  float64x2_t val;
+
+  val = vld1q_f64 (pool);
+  return vaddvq_f64 (val);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vclz.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vclz.c
new file mode 100644
index 000000000..006f80d77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vclz.c
@@ -0,0 +1,574 @@
+/* Test vclz works correctly.  */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -O3 -Wno-div-by-zero --save-temps" } */
+#include <arm_neon.h>
+
+extern void abort (void);
+
+/* Tests in binary should look like:
+   0
+   1
+   10
+   101
+   1010
+   10101
+   etc.  */
+
+#define TEST0 0
+#define TEST1 0x1
+#define TEST2 0x2
+#define TEST3 0x5
+#define TEST4 0xa
+#define TEST5 0x15
+#define TEST6 0x2a
+#define TEST7 0x55
+#define TEST8 0xaa
+#define TEST9 0x155
+#define TEST10 0x2aa
+#define TEST11 0x555
+#define TEST12 0xaaa
+#define TEST13 0x1555
+#define TEST14 0x2aaa
+#define TEST15 0x5555
+#define TEST16 0xaaaa
+#define TEST17 0x15555
+#define TEST18 0x2aaaa
+#define TEST19 0x55555
+#define TEST20 0xaaaaa
+#define TEST21 0x155555
+#define TEST22 0x2aaaaa
+#define TEST23 0x555555
+#define TEST24 0xaaaaaa
+#define TEST25 0x1555555
+#define TEST26 0x2aaaaaa
+#define TEST27 0x5555555
+#define TEST28 0xaaaaaaa
+#define TEST29 0x15555555
+#define TEST30 0x2aaaaaaa
+#define TEST31 0x55555555
+#define TEST32 0xaaaaaaaa
+
+#define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
+
+#define CONCAT(a, b) a##b
+#define CONCAT1(a, b) CONCAT (a, b)
+#define REG_INFEX64 _
+#define REG_INFEX128 q_
+#define SIGNED0 u
+#define SIGNED1 s
+#define SIGNED(x) SIGNED##x
+#define REG_INFEX(reg_len) REG_INFEX##reg_len
+#define POSTFIX(reg_len, data_len, is_signed) \
+  CONCAT1 (REG_INFEX (reg_len), CONCAT1 (SIGNED (is_signed), data_len))
+#define DATA_TYPE(data_len) DATA_TYPE_##data_len
+#define LOAD_INST(reg_len, data_len, is_signed) \
+  CONCAT1 (vld1, POSTFIX (reg_len, data_len, is_signed))
+#define CLZ_INST(reg_len, data_len, is_signed) \
+  CONCAT1 (vclz, POSTFIX (reg_len, data_len, is_signed))
+
+#define RUN_TEST(test_set, answ_set, reg_len, data_len, is_signed, n)	\
+  a = LOAD_INST (reg_len, data_len, is_signed) (test_set);		\
+  b = LOAD_INST (reg_len, data_len, is_signed) (answ_set);	        \
+  INHIB_OPTIMIZATION;							\
+  a = CLZ_INST (reg_len, data_len, is_signed) (a);			\
+  for (i = 0; i < n; i++)						\
+    {									\
+      INHIB_OPTIMIZATION;						\
+      if (a [i] != b [i])						\
+        {								\
+          return 1;							\
+        }								\
+    }
+
+int
+test_vclz_s8 ()
+{
+  int i;
+  int8x8_t a;
+  int8x8_t b;
+
+  int8_t test_set0[8] = {
+    TEST0, TEST1, TEST2, TEST3,
+    TEST4, TEST5, TEST6, TEST7
+  };
+  int8_t test_set1[8] = {
+    TEST8, TEST8, TEST8, TEST8,
+    TEST8, TEST8, TEST8, TEST8
+  };
+  int8_t answ_set0[8] = {
+    8, 7, 6, 5,
+    4, 3, 2, 1
+  };
+  int8_t answ_set1[8] = {
+    0, 0, 0, 0,
+    0, 0, 0, 0
+  };
+  RUN_TEST (test_set0, answ_set0, 64, 8, 1, 8);
+  RUN_TEST (test_set1, answ_set1, 64, 8, 1, 1);
+
+  return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions.  */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 4 } } */
+
+int
+test_vclz_s16 ()
+{
+  int i;
+  int16x4_t a;
+  int16x4_t b;
+
+  int16_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+  int16_t test_set1[4] = { TEST4, TEST5, TEST6, TEST7 };
+  int16_t test_set2[4] = { TEST8, TEST9, TEST10, TEST11 };
+  int16_t test_set3[4] = { TEST12, TEST13, TEST14, TEST15 };
+  int16_t test_set4[4] = { TEST16, TEST16, TEST16, TEST16 };
+
+  int16_t answ_set0[4] = { 16, 15, 14, 13 };
+  int16_t answ_set1[4] = { 12, 11, 10, 9 };
+  int16_t answ_set2[4] = { 8, 7, 6, 5 };
+  int16_t answ_set3[4] = { 4, 3, 2, 1 };
+  int16_t answ_set4[4] = { 0, 0, 0, 0 };
+
+  RUN_TEST (test_set0, answ_set0, 64, 16, 1, 4);
+  RUN_TEST (test_set1, answ_set1, 64, 16, 1, 4);
+  RUN_TEST (test_set2, answ_set2, 64, 16, 1, 4);
+  RUN_TEST (test_set3, answ_set3, 64, 16, 1, 4);
+  RUN_TEST (test_set4, answ_set4, 64, 16, 1, 1);
+
+  return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions.  */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 10} } */
+
+int
+test_vclz_s32 ()
+{
+  int i;
+  int32x2_t a;
+  int32x2_t b;
+
+  int32_t test_set0[2] = { TEST0, TEST1 };
+  int32_t test_set1[2] = { TEST2, TEST3 };
+  int32_t test_set2[2] = { TEST4, TEST5 };
+  int32_t test_set3[2] = { TEST6, TEST7 };
+  int32_t test_set4[2] = { TEST8, TEST9 };
+  int32_t test_set5[2] = { TEST10, TEST11 };
+  int32_t test_set6[2] = { TEST12, TEST13 };
+  int32_t test_set7[2] = { TEST14, TEST15 };
+  int32_t test_set8[2] = { TEST16, TEST17 };
+  int32_t test_set9[2] = { TEST18, TEST19 };
+  int32_t test_set10[2] = { TEST20, TEST21 };
+  int32_t test_set11[2] = { TEST22, TEST23 };
+  int32_t test_set12[2] = { TEST24, TEST25 };
+  int32_t test_set13[2] = { TEST26, TEST27 };
+  int32_t test_set14[2] = { TEST28, TEST29 };
+  int32_t test_set15[2] = { TEST30, TEST31 };
+  int32_t test_set16[2] = { TEST32, TEST32 };
+
+  int32_t answ_set0[2] = { 32, 31 };
+  int32_t answ_set1[2] = { 30, 29 };
+  int32_t answ_set2[2] = { 28, 27 };
+  int32_t answ_set3[2] = { 26, 25 };
+  int32_t answ_set4[2] = { 24, 23 };
+  int32_t answ_set5[2] = { 22, 21 };
+  int32_t answ_set6[2] = { 20, 19 };
+  int32_t answ_set7[2] = { 18, 17 };
+  int32_t answ_set8[2] = { 16, 15 };
+  int32_t answ_set9[2] = { 14, 13 };
+  int32_t answ_set10[2] = { 12, 11 };
+  int32_t answ_set11[2] = { 10, 9 };
+  int32_t answ_set12[2] = { 8, 7 };
+  int32_t answ_set13[2] = { 6, 5 };
+  int32_t answ_set14[2] = { 4, 3 };
+  int32_t answ_set15[2] = { 2, 1 };
+  int32_t answ_set16[2] = { 0, 0 };
+
+  RUN_TEST (test_set0, answ_set0, 64, 32, 1, 2);
+  RUN_TEST (test_set1, answ_set1, 64, 32, 1, 2);
+  RUN_TEST (test_set2, answ_set2, 64, 32, 1, 2);
+  RUN_TEST (test_set3, answ_set3, 64, 32, 1, 2);
+  RUN_TEST (test_set4, answ_set4, 64, 32, 1, 2);
+  RUN_TEST (test_set5, answ_set5, 64, 32, 1, 2);
+  RUN_TEST (test_set6, answ_set6, 64, 32, 1, 2);
+  RUN_TEST (test_set7, answ_set7, 64, 32, 1, 2);
+  RUN_TEST (test_set8, answ_set8, 64, 32, 1, 2);
+  RUN_TEST (test_set9, answ_set9, 64, 32, 1, 2);
+  RUN_TEST (test_set10, answ_set10, 64, 32, 1, 2);
+  RUN_TEST (test_set11, answ_set11, 64, 32, 1, 2);
+  RUN_TEST (test_set12, answ_set12, 64, 32, 1, 2);
+  RUN_TEST (test_set13, answ_set13, 64, 32, 1, 2);
+  RUN_TEST (test_set14, answ_set14, 64, 32, 1, 2);
+  RUN_TEST (test_set15, answ_set15, 64, 32, 1, 2);
+  RUN_TEST (test_set16, answ_set16, 64, 32, 1, 1);
+
+  return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions.  */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 34 } } */
+
+int
+test_vclzq_s8 ()
+{
+  int i;
+  int8x16_t a;
+  int8x16_t b;
+
+  int8_t test_set0[16] = {
+    TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7,
+    TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8
+  };
+  int8_t answ_set0[16] = {
+    8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0
+  };
+  RUN_TEST (test_set0, answ_set0, 128, 8, 1, 9);
+  return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions.  */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
+
+int
+test_vclzq_s16 ()
+{
+  int i;
+  int16x8_t a;
+  int16x8_t b;
+
+  int16_t test_set0[8] = {
+    TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7
+  };
+  int16_t test_set1[8] = {
+    TEST8, TEST9, TEST10, TEST11, TEST12, TEST13, TEST14, TEST15
+  };
+  int16_t test_set2[8] = {
+    TEST16, TEST16, TEST16, TEST16, TEST16, TEST16, TEST16, TEST16
+  };
+
+  int16_t answ_set0[8] = {
+    16, 15, 14, 13, 12, 11, 10, 9
+  };
+  int16_t answ_set1[8] = {
+    8, 7, 6, 5, 4, 3, 2, 1
+  };
+  int16_t answ_set2[8] = {
+    0, 0, 0, 0, 0, 0, 0, 0
+  };
+  RUN_TEST (test_set0, answ_set0, 128, 16, 1, 8);
+  RUN_TEST (test_set1, answ_set1, 128, 16, 1, 8);
+  RUN_TEST (test_set2, answ_set2, 128, 16, 1, 1);
+
+  return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions.  */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 6 } } */
+
+int
+test_vclzq_s32 ()
+{
+  int i;
+  int32x4_t a;
+  int32x4_t b;
+
+  int32_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+  int32_t test_set1[4] = { TEST4, TEST5, TEST6, TEST7 };
+  int32_t test_set2[4] = { TEST8, TEST9, TEST10, TEST11 };
+  int32_t test_set3[4] = { TEST12, TEST13, TEST14, TEST15 };
+  int32_t test_set4[4] = { TEST16, TEST17, TEST18, TEST19 };
+  int32_t test_set5[4] = { TEST20, TEST21, TEST22, TEST23 };
+  int32_t test_set6[4] = { TEST24, TEST25, TEST26, TEST27 };
+  int32_t test_set7[4] = { TEST28, TEST29, TEST30, TEST31 };
+  int32_t test_set8[4] = { TEST32, TEST32, TEST32, TEST32 };
+
+  int32_t answ_set0[4] = { 32, 31, 30, 29 };
+  int32_t answ_set1[4] = { 28, 27, 26, 25 };
+  int32_t answ_set2[4] = { 24, 23, 22, 21 };
+  int32_t answ_set3[4] = { 20, 19, 18, 17 };
+  int32_t answ_set4[4] = { 16, 15, 14, 13 };
+  int32_t answ_set5[4] = { 12, 11, 10, 9 };
+  int32_t answ_set6[4] = { 8, 7, 6, 5 };
+  int32_t answ_set7[4] = { 4, 3, 2, 1 };
+  int32_t answ_set8[4] = { 0, 0, 0, 0 };
+
+  RUN_TEST (test_set0, answ_set0, 128, 32, 1, 4);
+  RUN_TEST (test_set1, answ_set1, 128, 32, 1, 4);
+  RUN_TEST (test_set2, answ_set2, 128, 32, 1, 4);
+  RUN_TEST (test_set3, answ_set3, 128, 32, 1, 4);
+  RUN_TEST (test_set4, answ_set4, 128, 32, 1, 1);
+
+  return 0;
+}
+
+/* Double scan-assembler-times to take account of unsigned functions.  */
+/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 10 } } */
+
+/* Unsigned versions.  */
+
+int
+test_vclz_u8 ()
+{
+  int i;
+  uint8x8_t a;
+  uint8x8_t b;
+
+  uint8_t test_set0[8] = {
+    TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7
+  };
+  uint8_t test_set1[8] = {
+    TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8
+  };
+  uint8_t answ_set0[8] = {
+    8, 7, 6, 5, 4, 3, 2, 1
+  };
+  uint8_t answ_set1[8] = {
+    0, 0, 0, 0, 0, 0, 0, 0
+  };
+
+  RUN_TEST (test_set0, answ_set0, 64, 8, 0, 8);
+  RUN_TEST (test_set1, answ_set1, 64, 8, 0, 1);
+
+  return 0;
+}
+
+/* ASM scan near test for signed version.  */
+
+int
+test_vclz_u16 ()
+{
+  int i;
+  uint16x4_t a;
+  uint16x4_t b;
+
+  uint16_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+  uint16_t test_set1[4] = { TEST4, TEST5, TEST6, TEST7 };
+  uint16_t test_set2[4] = { TEST8, TEST9, TEST10, TEST11 };
+  uint16_t test_set3[4] = { TEST12, TEST13, TEST14, TEST15 };
+  uint16_t test_set4[4] = { TEST16, TEST16, TEST16, TEST16 };
+
+  uint16_t answ_set0[4] = { 16, 15, 14, 13 };
+  uint16_t answ_set1[4] = { 12, 11, 10, 9 };
+  uint16_t answ_set2[4] = { 8, 7, 6, 5 };
+  uint16_t answ_set3[4] = { 4, 3, 2, 1 };
+  uint16_t answ_set4[4] = { 0, 0, 0, 0 };
+
+  RUN_TEST (test_set0, answ_set0, 64, 16, 0, 4);
+  RUN_TEST (test_set1, answ_set1, 64, 16, 0, 4);
+  RUN_TEST (test_set2, answ_set2, 64, 16, 0, 4);
+  RUN_TEST (test_set3, answ_set3, 64, 16, 0, 4);
+  RUN_TEST (test_set4, answ_set4, 64, 16, 0, 1);
+
+  return 0;
+}
+
+/* ASM scan near test for signed version.  */
+
+int
+test_vclz_u32 ()
+{
+  int i;
+  uint32x2_t a;
+  uint32x2_t b;
+
+  uint32_t test_set0[2] = { TEST0, TEST1 };
+  uint32_t test_set1[2] = { TEST2, TEST3 };
+  uint32_t test_set2[2] = { TEST4, TEST5 };
+  uint32_t test_set3[2] = { TEST6, TEST7 };
+  uint32_t test_set4[2] = { TEST8, TEST9 };
+  uint32_t test_set5[2] = { TEST10, TEST11 };
+  uint32_t test_set6[2] = { TEST12, TEST13 };
+  uint32_t test_set7[2] = { TEST14, TEST15 };
+  uint32_t test_set8[2] = { TEST16, TEST17 };
+  uint32_t test_set9[2] = { TEST18, TEST19 };
+  uint32_t test_set10[2] = { TEST20, TEST21 };
+  uint32_t test_set11[2] = { TEST22, TEST23 };
+  uint32_t test_set12[2] = { TEST24, TEST25 };
+  uint32_t test_set13[2] = { TEST26, TEST27 };
+  uint32_t test_set14[2] = { TEST28, TEST29 };
+  uint32_t test_set15[2] = { TEST30, TEST31 };
+  uint32_t test_set16[2] = { TEST32, TEST32 };
+
+  uint32_t answ_set0[2] = { 32, 31 };
+  uint32_t answ_set1[2] = { 30, 29 };
+  uint32_t answ_set2[2] = { 28, 27 };
+  uint32_t answ_set3[2] = { 26, 25 };
+  uint32_t answ_set4[2] = { 24, 23 };
+  uint32_t answ_set5[2] = { 22, 21 };
+  uint32_t answ_set6[2] = { 20, 19 };
+  uint32_t answ_set7[2] = { 18, 17 };
+  uint32_t answ_set8[2] = { 16, 15 };
+  uint32_t answ_set9[2] = { 14, 13 };
+  uint32_t answ_set10[2] = { 12, 11 };
+  uint32_t answ_set11[2] = { 10, 9 };
+  uint32_t answ_set12[2] = { 8, 7 };
+  uint32_t answ_set13[2] = { 6, 5 };
+  uint32_t answ_set14[2] = { 4, 3 };
+  uint32_t answ_set15[2] = { 2, 1 };
+  uint32_t answ_set16[2] = { 0, 0 };
+
+  RUN_TEST (test_set0, answ_set0, 64, 32, 0, 2);
+  RUN_TEST (test_set1, answ_set1, 64, 32, 0, 2);
+  RUN_TEST (test_set2, answ_set2, 64, 32, 0, 2);
+  RUN_TEST (test_set3, answ_set3, 64, 32, 0, 2);
+  RUN_TEST (test_set4, answ_set4, 64, 32, 0, 2);
+  RUN_TEST (test_set5, answ_set5, 64, 32, 0, 2);
+  RUN_TEST (test_set6, answ_set6, 64, 32, 0, 2);
+  RUN_TEST (test_set7, answ_set7, 64, 32, 0, 2);
+  RUN_TEST (test_set8, answ_set8, 64, 32, 0, 2);
+  RUN_TEST (test_set9, answ_set9, 64, 32, 0, 2);
+  RUN_TEST (test_set10, answ_set10, 64, 32, 0, 2);
+  RUN_TEST (test_set11, answ_set11, 64, 32, 0, 2);
+  RUN_TEST (test_set12, answ_set12, 64, 32, 0, 2);
+  RUN_TEST (test_set13, answ_set13, 64, 32, 0, 2);
+  RUN_TEST (test_set14, answ_set14, 64, 32, 0, 2);
+  RUN_TEST (test_set15, answ_set15, 64, 32, 0, 2);
+  RUN_TEST (test_set16, answ_set16, 64, 32, 0, 1);
+
+  return 0;
+}
+
+/* ASM scan near test for signed version.  */
+
+int
+test_vclzq_u8 ()
+{
+  int i;
+  uint8x16_t a;
+  uint8x16_t b;
+
+  uint8_t test_set0[16] = {
+    TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7,
+    TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8, TEST8
+  };
+  uint8_t answ_set0[16] = {
+    8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0
+  };
+  RUN_TEST (test_set0, answ_set0, 128, 8, 0, 9);
+
+  return 0;
+}
+
+/* ASM scan near test for signed version.  */
+
+int
+test_vclzq_u16 ()
+{
+  int i;
+  uint16x8_t a;
+  uint16x8_t b;
+
+  uint16_t test_set0[8] = {
+    TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7
+  };
+  uint16_t test_set1[8] = {
+    TEST8, TEST9, TEST10, TEST11, TEST12, TEST13, TEST14, TEST15
+  };
+  uint16_t test_set2[8] = {
+    TEST16, TEST16, TEST16, TEST16, TEST16, TEST16, TEST16, TEST16
+  };
+
+  uint16_t answ_set0[8] = {
+    16, 15, 14, 13, 12, 11, 10, 9
+  };
+
+  uint16_t answ_set1[8] = {
+    8, 7, 6, 5, 4, 3, 2, 1
+  };
+  uint16_t answ_set2[8] = {
+    0, 0, 0, 0, 0, 0, 0, 0
+  };
+
+  RUN_TEST (test_set0, answ_set0, 128, 16, 0, 8);
+  RUN_TEST (test_set1, answ_set1, 128, 16, 0, 8);
+  RUN_TEST (test_set2, answ_set2, 128, 16, 0, 1);
+
+  return 0;
+}
+
+/* ASM scan near test for signed version.  */
+
+int
+test_vclzq_u32 ()
+{
+  int i;
+  uint32x4_t a;
+  uint32x4_t b;
+
+  uint32_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+  uint32_t test_set1[4] = { TEST4, TEST5, TEST6, TEST7 };
+  uint32_t test_set2[4] = { TEST8, TEST9, TEST10, TEST11 };
+  uint32_t test_set3[4] = { TEST12, TEST13, TEST14, TEST15 };
+  uint32_t test_set4[4] = { TEST16, TEST17, TEST18, TEST19 };
+  uint32_t test_set5[4] = { TEST20, TEST21, TEST22, TEST23 };
+  uint32_t test_set6[4] = { TEST24, TEST25, TEST26, TEST27 };
+  uint32_t test_set7[4] = { TEST28, TEST29, TEST30, TEST31 };
+  uint32_t test_set8[4] = { TEST32, TEST32, TEST32, TEST32 };
+
+  uint32_t answ_set0[4] = { 32, 31, 30, 29 };
+  uint32_t answ_set1[4] = { 28, 27, 26, 25 };
+  uint32_t answ_set2[4] = { 24, 23, 22, 21 };
+  uint32_t answ_set3[4] = { 20, 19, 18, 17 };
+  uint32_t answ_set4[4] = { 16, 15, 14, 13 };
+  uint32_t answ_set5[4] = { 12, 11, 10, 9 };
+  uint32_t answ_set6[4] = { 8, 7, 6, 5 };
+  uint32_t answ_set7[4] = { 4, 3, 2, 1 };
+  uint32_t answ_set8[4] = { 0, 0, 0, 0 };
+
+  RUN_TEST (test_set0, answ_set0, 128, 32, 0, 4);
+  RUN_TEST (test_set1, answ_set1, 128, 32, 0, 4);
+  RUN_TEST (test_set2, answ_set2, 128, 32, 0, 4);
+  RUN_TEST (test_set3, answ_set3, 128, 32, 0, 4);
+  RUN_TEST (test_set4, answ_set4, 128, 32, 0, 1);
+
+  return 0;
+}
+
+/* ASM scan near test for signed version.  */
+
+int
+main (int argc, char **argv)
+{
+
+  if (test_vclz_s8 ())
+    abort ();
+
+  if (test_vclz_s16 ())
+    abort ();
+
+  if (test_vclz_s32 ())
+    abort ();
+
+  if (test_vclzq_s8 ())
+    abort ();
+
+  if (test_vclzq_s16 ())
+    abort ();
+
+  if (test_vclzq_s32 ())
+    abort ();
+
+  if (test_vclz_u8 ())
+    abort ();
+
+  if (test_vclz_u16 ())
+    abort ();
+
+  if (test_vclz_u32 ())
+    abort ();
+
+  if (test_vclzq_u8 ())
+    abort ();
+
+  if (test_vclzq_u16 ())
+    abort ();
+
+  if (test_vclzq_u32 ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vdiv_f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vdiv_f.c
new file mode 100644
index 000000000..cc3a9570c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vdiv_f.c
@@ -0,0 +1,361 @@
+/* Test vdiv works correctly.  */
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+#define FLT_INFINITY (__builtin_inff ())
+#define DBL_INFINITY (__builtin_inf ())
+
+#define NAN (0.0 / 0.0)
+
+#define PI 3.141592653589793
+#define PI_4 0.7853981633974483
+#define SQRT2 1.4142135623730951
+#define SQRT1_2 0.7071067811865475
+
+#define TESTA0 PI
+#define TESTA1 -PI
+#define TESTA2 PI
+#define TESTA3 -PI
+#define TESTA4 1.0
+#define TESTA5 -1.0
+#define TESTA6 1.0
+#define TESTA7 -1.0
+/* 2^25+1, float has 24 significand bits
+   according to Single-precision floating-point format.  */
+#define TESTA8_FLT 33554433
+/* 2^54+1, double has 53 significand bits
+   according to Double-precision floating-point format.  */
+#define TESTA8_DBL 18014398509481985
+#define TESTA9 -TESTA8
+#define TESTA10 TESTA8
+#define TESTA11 -TESTA8
+#define TESTA12 NAN
+#define TESTA13 1.0
+#define TESTA14 INFINITY
+#define TESTA15 -INFINITY
+#define TESTA16 INFINITY
+#define TESTA17 9.0
+#define TESTA18 11.0
+#define TESTA19 13.0
+
+#define TESTB0 4.0
+#define TESTB1 4.0
+#define TESTB2 -4.0
+#define TESTB3 -4.0
+#define TESTB4 SQRT2
+#define TESTB5 SQRT2
+#define TESTB6 -SQRT2
+#define TESTB7 -SQRT2
+#define TESTB8 2.0
+#define TESTB9 2.0
+#define TESTB10 -2.0
+#define TESTB11 -2.0
+#define TESTB12 3.0
+#define TESTB13 NAN
+#define TESTB14 5.0
+#define TESTB15 7.0
+#define TESTB16 INFINITY
+#define TESTB17 INFINITY
+#define TESTB18 -INFINITY
+#define TESTB19 0
+
+#define ANSW0 PI_4
+#define ANSW1 -PI_4
+#define ANSW2 -PI_4
+#define ANSW3 PI_4
+#define ANSW4 SQRT1_2
+#define ANSW5 -SQRT1_2
+#define ANSW6 -SQRT1_2
+#define ANSW7 SQRT1_2
+#define ANSW8_FLT 16777216
+#define ANSW8_DBL 9007199254740992
+#define ANSW9 -ANSW8
+#define ANSW10 -ANSW8
+#define ANSW11 ANSW8
+#define ANSW12 NAN
+#define ANSW13 NAN
+#define ANSW14 INFINITY
+#define ANSW15 -INFINITY
+#define ANSW16 NAN
+#define ANSW17 0
+#define ANSW18 0
+#define ANSW19 INFINITY
+
+#define CONCAT(a, b) a##b
+#define CONCAT1(a, b) CONCAT (a, b)
+#define REG_INFEX64 _
+#define REG_INFEX128 q_
+#define REG_INFEX(reg_len) REG_INFEX##reg_len
+#define POSTFIX(reg_len, data_len) \
+  CONCAT1 (REG_INFEX (reg_len), f##data_len)
+
+#define DATA_TYPE_32 float
+#define DATA_TYPE_64 double
+#define DATA_TYPE(data_len) DATA_TYPE_##data_len
+
+#define EPSILON_32 __FLT_EPSILON__
+#define EPSILON_64 __DBL_EPSILON__
+#define EPSILON(data_len) EPSILON_##data_len
+
+#define INDEX64_32 [i]
+#define INDEX64_64
+#define INDEX128_32 [i]
+#define INDEX128_64 [i]
+#define INDEX(reg_len, data_len) \
+  CONCAT1 (INDEX, reg_len##_##data_len)
+
+#define LOAD_INST(reg_len, data_len) \
+  CONCAT1 (vld1, POSTFIX (reg_len, data_len))
+#define DIV_INST(reg_len, data_len) \
+  CONCAT1 (vdiv, POSTFIX (reg_len, data_len))
+
+#define ABS(a) __builtin_fabs (a)
+#define ISNAN(a) __builtin_isnan (a)
+#define FP_equals(a, b, epsilon)			\
+  (							\
+   ((a) == (b))						\
+    || (ISNAN (a) && ISNAN (b))				\
+    || (ABS (a - b) < epsilon)				\
+  )
+
+#define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
+
+#define RUN_TEST(a, b, c, testseta, testsetb, answset, count,		\
+		 reg_len, data_len, n)					\
+{									\
+  int i;								\
+  INHIB_OPTIMIZATION;							\
+  (a) = LOAD_INST (reg_len, data_len) (testseta[count]);		\
+  (b) = LOAD_INST (reg_len, data_len) (testsetb[count]);		\
+  (c) = LOAD_INST (reg_len, data_len) (answset[count]);			\
+  INHIB_OPTIMIZATION;							\
+  (a) = DIV_INST (reg_len, data_len) (a, b);				\
+  for (i = 0; i < n; i++)						\
+  {									\
+    INHIB_OPTIMIZATION;							\
+    if (!FP_equals ((a) INDEX (reg_len, data_len),			\
+		    (c) INDEX (reg_len, data_len),			\
+		    EPSILON (data_len)))				\
+      return 1;								\
+  }									\
+}
+
+extern void abort (void);
+
+#define TESTA8 TESTA8_FLT
+#define ANSW8 ANSW8_FLT
+#define INFINITY FLT_INFINITY
+
+int
+test_vdiv_f32 ()
+{
+  int count;
+  float32x2_t a;
+  float32x2_t b;
+  float32x2_t c;
+
+  float32_t testseta[10][2] = {
+    { TESTA0, TESTA1 }, { TESTA2, TESTA3 },
+    { TESTA4, TESTA5 }, { TESTA6, TESTA7 },
+    { TESTA8, TESTA9 }, { TESTA10, TESTA11 },
+    { TESTA12, TESTA13 }, { TESTA14, TESTA15 },
+    { TESTA16, TESTA17 }, { TESTA18, TESTA19 }
+  };
+
+  float32_t testsetb[10][2] = {
+    { TESTB0, TESTB1 }, { TESTB2, TESTB3 },
+    { TESTB4, TESTB5 }, { TESTB6, TESTB7 },
+    { TESTB8, TESTB9 }, { TESTB10, TESTB11 },
+    { TESTB12, TESTB13 }, { TESTB14, TESTB15 },
+    { TESTB16, TESTB17 }, { TESTB18, TESTB19 }
+  };
+
+  float32_t answset[10][2] = {
+    { ANSW0, ANSW1 }, { ANSW2, ANSW3 },
+    { ANSW4, ANSW5 }, { ANSW6, ANSW7 },
+    { ANSW8, ANSW9 }, { ANSW10, ANSW11 },
+    { ANSW12, ANSW13 }, { ANSW14, ANSW15 },
+    { ANSW16, ANSW17 }, { ANSW18, ANSW19 }
+  };
+
+  for (count = 0; count < 10; count++)
+    {
+      RUN_TEST (a, b, c, testseta, testsetb, answset, count, 64, 32, 2);
+    }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fdiv\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+
+#undef TESTA8
+#undef ANSW8
+#undef INFINITY
+
+#define TESTA8 TESTA8_DBL
+#define ANSW8 ANSW8_DBL
+#define INFINITY DBL_INFINITY
+
+int
+test_vdiv_f64 ()
+{
+  int count;
+  float64x1_t a;
+  float64x1_t b;
+  float64x1_t c;
+
+  float64_t testseta[20][1] = {
+    { TESTA0 }, { TESTA1 }, { TESTA2 }, { TESTA3 },
+    { TESTA4 }, { TESTA5 }, { TESTA6 }, { TESTA7 },
+    { TESTA8 }, { TESTA9 }, { TESTA10 }, { TESTA11 },
+    { TESTA12 }, { TESTA13 }, { TESTA14 }, { TESTA15 },
+    { TESTA16 }, { TESTA17 }, { TESTA18 }, { TESTA19 }
+  };
+
+  float64_t testsetb[20][1] = {
+    { TESTB0 }, { TESTB1 }, { TESTB2 }, { TESTB3 },
+    { TESTB4 }, { TESTB5 }, { TESTB6 }, { TESTB7 },
+    { TESTB8 }, { TESTB9 }, { TESTB10 }, { TESTB11 },
+    { TESTB12 }, { TESTB13 }, { TESTB14 }, { TESTB15 },
+    { TESTB16 }, { TESTB17 }, { TESTB18 }, { TESTB19 }
+  };
+
+  float64_t answset[20][1] = {
+    { ANSW0 }, { ANSW1 }, { ANSW2 }, { ANSW3 },
+    { ANSW4 }, { ANSW5 }, { ANSW6 }, { ANSW7 },
+    { ANSW8 }, { ANSW9 }, { ANSW10 }, { ANSW11 },
+    { ANSW12 }, { ANSW13 }, { ANSW14 }, { ANSW15 },
+    { ANSW16 }, { ANSW17 }, { ANSW18 }, { ANSW19 }
+  };
+
+  for (count = 0; count < 20; count++)
+    {
+      RUN_TEST (a, b, c, testseta, testsetb, answset, count, 64, 64, 1);
+    }
+  return 0;
+}
+
+/* The following assembly should match 2 more times,
+   in 64bit NAN generation.  */
+/* { dg-final { scan-assembler-times "fdiv\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 3 } } */
+
+#undef TESTA8
+#undef ANSW8
+#undef INFINITY
+
+#define TESTA8 TESTA8_FLT
+#define ANSW8 ANSW8_FLT
+#define INFINITY FLT_INFINITY
+
+int
+test_vdivq_f32 ()
+{
+  int count;
+  float32x4_t a;
+  float32x4_t b;
+  float32x4_t c;
+
+  float32_t testseta[5][4] = {
+    { TESTA0, TESTA1, TESTA2, TESTA3 },
+    { TESTA4, TESTA5, TESTA6, TESTA7 },
+    { TESTA8, TESTA9, TESTA10, TESTA11 },
+    { TESTA12, TESTA13, TESTA14, TESTA15 },
+    { TESTA16, TESTA17, TESTA18, TESTA19 }
+  };
+
+  float32_t testsetb[5][4] = {
+    { TESTB0, TESTB1, TESTB2, TESTB3 },
+    { TESTB4, TESTB5, TESTB6, TESTB7 },
+    { TESTB8, TESTB9, TESTB10, TESTB11 },
+    { TESTB12, TESTB13, TESTB14, TESTB15 },
+    { TESTB16, TESTB17, TESTB18, TESTB19 }
+  };
+
+  float32_t answset[5][4] = {
+    { ANSW0, ANSW1, ANSW2, ANSW3 },
+    { ANSW4, ANSW5, ANSW6, ANSW7 },
+    { ANSW8, ANSW9, ANSW10, ANSW11 },
+    { ANSW12, ANSW13, ANSW14, ANSW15 },
+    { ANSW16, ANSW17, ANSW18, ANSW19 }
+  };
+
+  for (count = 0; count < 5; count++)
+    {
+      RUN_TEST (a, b, c, testseta, testsetb, answset, count, 128, 32, 4);
+    }
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fdiv\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+#undef TESTA8
+#undef ANSW8
+#undef INFINITY
+
+#define TESTA8 TESTA8_DBL
+#define ANSW8 ANSW8_DBL
+#define INFINITY DBL_INFINITY
+
+int
+test_vdivq_f64 ()
+{
+  int count;
+  float64x2_t a;
+  float64x2_t b;
+  float64x2_t c;
+
+  float64_t testseta[10][2] = {
+    { TESTA0, TESTA1 }, { TESTA2, TESTA3 },
+    { TESTA4, TESTA5 }, { TESTA6, TESTA7 },
+    { TESTA8, TESTA9 }, { TESTA10, TESTA11 },
+    { TESTA12, TESTA13 }, { TESTA14, TESTA15 },
+    { TESTA16, TESTA17 }, { TESTA18, TESTA19 }
+  };
+
+  float64_t testsetb[10][2] = {
+    { TESTB0, TESTB1 }, { TESTB2, TESTB3 },
+    { TESTB4, TESTB5 }, { TESTB6, TESTB7 },
+    { TESTB8, TESTB9 }, { TESTB10, TESTB11 },
+    { TESTB12, TESTB13 }, { TESTB14, TESTB15 },
+    { TESTB16, TESTB17 }, { TESTB18, TESTB19 }
+  };
+
+  float64_t answset[10][2] = {
+    { ANSW0, ANSW1 }, { ANSW2, ANSW3 },
+    { ANSW4, ANSW5 }, { ANSW6, ANSW7 },
+    { ANSW8, ANSW9 }, { ANSW10, ANSW11 },
+    { ANSW12, ANSW13 }, { ANSW14, ANSW15 },
+    { ANSW16, ANSW17 }, { ANSW18, ANSW19 }
+  };
+
+  for (count = 0; count < 10; count++)
+    {
+      RUN_TEST (a, b, c, testseta, testsetb, answset, count, 128, 64, 2);
+    }
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fdiv\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
+
+int
+main (int argc, char **argv)
+{
+  if (test_vdiv_f32 ())
+    abort ();
+
+  if (test_vdiv_f64 ())
+    abort ();
+
+  if (test_vdivq_f32 ())
+    abort ();
+
+  if (test_vdivq_f64 ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
new file mode 100644
index 000000000..27146b843
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c
@@ -0,0 +1,12 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 16
+
+#include "vect-abs.x"
+
+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.16b" } } */
+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "abs\\tv\[0-9\]+\.2d" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.c
new file mode 100644
index 000000000..9e0ed99ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.c
@@ -0,0 +1,134 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3 -std=c99" } */
+
+#include "limits.h"
+
+extern void abort (void);
+
+#define N 16
+
+#include "vect-abs.x"
+
+#define SET_VEC(size, type) void set_vector_##size (pRINT##size a) \
+		      	    {				        \
+			      int i;			        \
+			      for (i=0; i<N; i++)	        \
+			        a[i] = (type##_MIN) + (i + 1);  \
+		      	    }
+
+#define SET_RVEC(size, type) void set_rvector_##size (pRINT##size a) \
+		      	     {				      \
+			       int i;			      \
+			       for (i=0; i<N; i++)	      \
+			         a[i] = type##_MAX - i;       \
+		      	     }
+
+#define CHECK_VEC(size) void check_vector_##size (pRINT##size a, \
+						  pRINT##size b) \
+			{				       \
+			  int i;			       \
+			  for (i=0; i<N; i++)		       \
+			    if (a[i] != b[i])  		       \
+			      abort (); 		       \
+			}
+
+
+SET_RVEC (8, SCHAR)
+SET_RVEC (16, SHRT)
+SET_RVEC (32, INT)
+SET_RVEC (64, LLONG)
+
+void
+set_rvector_long (pRLONG a)
+{
+  int i;
+  for (i=0; i<N; i++)
+    a[i] = (LONG_MAX) - i;
+}
+
+SET_VEC (8, SCHAR)
+SET_VEC (16, SHRT)
+SET_VEC (32, INT)
+SET_VEC (64, LLONG)
+
+void
+set_vector_long (long *__restrict__ a)
+{
+  long i;
+  for (i=0; i<N; i++)
+    a[i] = (LONG_MIN) + i + 1;
+}
+
+CHECK_VEC (8)
+CHECK_VEC (16)
+CHECK_VEC (32)
+CHECK_VEC (64)
+
+void
+check_vector_long (long *__restrict__ a, long *__restrict__ b)
+{
+  long i;
+  for (i=0; i<N; i++)
+    if (a[i] != b[i])
+      abort ();
+}
+
+int main (void)
+{
+
+  signed char a8[N];
+  short a16[N];
+  int a32[N];
+  long long a64[N];
+  /* abs () from stdlib.  */
+  int alib32[N];
+  long alibl[N];
+
+
+  signed char b8[N];
+  short b16[N];
+  int b32[N];
+  long long b64[N];
+  /* abs () from stdlib.  */
+  long blibl[N];
+
+  signed char abs_vector_8[N];
+  short abs_vector_16[N];
+  int abs_vector_32[N];
+  long long abs_vector_64[N];
+  long abs_vector_long[N];
+
+  /* Set up result vectors.  */
+  set_rvector_8 (abs_vector_8);
+  set_rvector_16 (abs_vector_16);
+  set_rvector_32 (abs_vector_32);
+  set_rvector_long (abs_vector_long);
+  set_rvector_64 (abs_vector_64);
+
+  /* Set up inputs.  */
+  set_vector_8 (b8);
+  set_vector_16 (b16);
+  set_vector_32 (b32);
+  set_vector_64 (b64);
+  set_vector_long (blibl);
+
+  /* Calculate their absolute values.  */
+  absolute_s8 (a8, b8);
+  absolute_s16 (a16, b16);
+  absolute_s32 (a32, b32);
+  absolute_s64 (a64, b64);
+  /* abs () from stdlib.  */
+  absolute_s32_lib (alib32, b32);
+  absolute_l32_lib (alibl, blibl);
+
+  /* Check.  */
+  check_vector_8 (a8, abs_vector_8);
+  check_vector_16 (a16, abs_vector_16);
+  check_vector_32 (a32, abs_vector_32);
+  check_vector_64 (a64, abs_vector_64);
+  check_vector_32 (alib32, abs_vector_32);
+  check_vector_long (alibl, abs_vector_long);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.x
new file mode 100644
index 000000000..2e67cc296
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-abs.x
@@ -0,0 +1,36 @@
+
+extern int abs (int);
+extern long labs (long);
+
+typedef signed char *__restrict__ pRINT8;
+typedef short *__restrict__ pRINT16;
+typedef int *__restrict__ pRINT32;
+typedef long *__restrict__ pRLONG;
+typedef long long *__restrict__ pRINT64;
+
+#define DEF_ABS(size)  void absolute_s##size (pRINT##size a, pRINT##size b) \
+		       { \
+			 int i;  \
+			 for (i=0; i<N; i++)     \
+			    a[i] = (b[i] > 0 ? b[i] : -b[i]); \
+		       }
+
+DEF_ABS (8);
+DEF_ABS (16);
+DEF_ABS (32);
+DEF_ABS (64);
+
+/* Test abs () vectorization.  */
+void absolute_s32_lib (pRINT32 a, pRINT32 b)
+{
+  int i;
+  for (i=0; i<N; i++)
+    a[i] = abs (b[i]);
+}
+
+void absolute_l32_lib (pRLONG a, pRLONG b)
+{
+  int i;
+  for (i=0; i<N; i++)
+    a[i] = labs (b[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-clz.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-clz.c
new file mode 100644
index 000000000..8f1fe7090
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-clz.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -save-temps -fno-inline" } */
+
+extern void abort ();
+
+void
+count_lz_v4si (unsigned *__restrict a, int *__restrict b)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    b[i] = __builtin_clz (a[i]);
+}
+
+/* { dg-final { scan-assembler "clz\tv\[0-9\]+\.4s" } } */
+
+int
+main ()
+{
+  unsigned int x[4] = { 0x0, 0xFFFF, 0x1FFFF, 0xFFFFFFFF };
+  int r[4] = { 32, 16, 15, 0 };
+  int d[4], i;
+
+  count_lz_v4si (x, d);
+
+  for (i = 0; i < 4; i++)
+    {
+      if (d[i] != r[i])
+	abort ();
+    }
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-compile.c
new file mode 100644
index 000000000..33130aab5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-compile.c
@@ -0,0 +1,22 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "vect.x"
+
+/* { dg-final { scan-assembler "orn\\tv" } } */
+/* { dg-final { scan-assembler "bic\\tv" } } */
+/* { dg-final { scan-assembler "mla\\tv" } } */
+/* { dg-final { scan-assembler "mls\\tv" } } */
+/* { dg-final { scan-assembler "smax\\tv" } } */
+/* { dg-final { scan-assembler "smin\\tv" } } */
+/* { dg-final { scan-assembler "umax\\tv" } } */
+/* { dg-final { scan-assembler "umin\\tv" } } */
+/* { dg-final { scan-assembler "umaxv" } } */
+/* { dg-final { scan-assembler "uminv" } } */
+/* { dg-final { scan-assembler "smaxv" } } */
+/* { dg-final { scan-assembler "sminv" } } */
+/* { dg-final { scan-assembler "sabd" } } */
+/* { dg-final { scan-assembler "saba" } } */
+/* { dg-final { scan-assembler-times "addv" 2} } */
+/* { dg-final { scan-assembler-times "addp" 2} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c
new file mode 100644
index 000000000..cce924034
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv-compile.c
@@ -0,0 +1,7 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -ffast-math" } */
+
+#include "vect-faddv.x"
+
+/* { dg-final { scan-assembler-times "faddp\\tv" 2} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.c
new file mode 100644
index 000000000..f30bde8e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.c
@@ -0,0 +1,31 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3 -ffast-math" } */
+
+extern void abort (void);
+
+#include "vect-faddv.x"
+
+int main (void)
+{
+  float addv_f32_value = -120.0f;
+  double addv_f64_value = 120.0;
+  float af32[16];
+  double af64[16];
+  int i;
+
+  /* Set up input vectors.  */
+  for (i=0; i<16; i++)
+    {
+      af32[i] = (float)-i;
+      af64[i] = (double)i;
+    }
+
+  if (addv_f32 (af32) != addv_f32_value)
+    abort ();
+
+  if (addv_f64 (af64) != addv_f64_value)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.x
new file mode 100644
index 000000000..d99ab2156
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-faddv.x
@@ -0,0 +1,23 @@
+
+typedef float *__restrict__ pRF32;
+typedef double *__restrict__ pRF64;
+
+float addv_f32 (pRF32 a)
+{
+  int i;
+  float s = 0.0;
+  for (i=0; i<16; i++)
+    s += a[i];
+
+  return s;
+}
+
+double addv_f64 (pRF64 a)
+{
+  int i;
+  double  s = 0.0;
+  for (i=0; i<16; i++)
+    s += a[i];
+
+  return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
new file mode 100644
index 000000000..6c2e2c8b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-d.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE double
+#define ITYPE long
+#define OP ==
+#define INV_OP !=
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c
new file mode 100644
index 000000000..5a2109c4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-eq-f.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE float
+#define ITYPE int
+#define OP ==
+#define INV_OP !=
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */
+/* { dg-final { scan-assembler "fcmeq\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
new file mode 100644
index 000000000..8fad79998
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-d.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE double
+#define ITYPE long
+#define OP >=
+#define INV_OP <
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c
new file mode 100644
index 000000000..7aab9e6b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-ge-f.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE float
+#define ITYPE int
+#define OP >=
+#define INV_OP <
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */
+/* { dg-final { scan-assembler "fcmge\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { scan-assembler "fcmlt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
new file mode 100644
index 000000000..d26acaae3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-d.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE double
+#define ITYPE long
+#define OP >
+#define INV_OP <=
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c
new file mode 100644
index 000000000..2797fd1a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm-gt-f.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all -fno-unroll-loops --save-temps -fno-inline" } */
+
+#define FTYPE float
+#define ITYPE int
+#define OP >
+#define INV_OP <=
+
+#include "vect-fcm.x"
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 8 "vect" } } */
+/* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s" } } */
+/* { dg-final { scan-assembler "fcmgt\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { scan-assembler "fcmle\\tv\[0-9\]+\.\[24\]s, v\[0-9\]+\.\[24\]s, 0" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm.x
new file mode 100644
index 000000000..614f0dec0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fcm.x
@@ -0,0 +1,124 @@
+#include <stdlib.h>
+#define N 16
+
+FTYPE input1[N] =
+{2.0, 4.0, 8.0, 16.0,
+ 2.125, 4.25, 8.5, 17.0,
+ -2.0, -4.0, -8.0, -16.0,
+ -2.125, -4.25, -8.5, -17.0};
+
+FTYPE input2[N] =
+{-2.0, 4.0, -8.0, 16.0,
+ 2.125, -4.25, 8.5, -17.0,
+ 2.0, -4.0, 8.0, -16.0,
+ -2.125, 4.25, -8.5, 17.0};
+
+/* Float comparisons, float results.  */
+
+void
+foo (FTYPE *in1, FTYPE *in2, FTYPE *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = (in1[i] OP in2[i]) ? 2.0 : 4.0;
+}
+
+void
+bar (FTYPE *in1, FTYPE *in2, FTYPE *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = (in1[i] INV_OP in2[i]) ? 4.0 : 2.0;
+}
+
+void
+foobar (FTYPE *in1, FTYPE *in2, FTYPE *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = (in1[i] OP 0.0) ? 4.0 : 2.0;
+}
+
+void
+foobarbar (FTYPE *in1, FTYPE *in2, FTYPE *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = (in1[i] INV_OP 0.0) ? 4.0 : 2.0;
+}
+
+/* Float comparisons, int results.  */
+
+void
+foo_int (FTYPE *in1, FTYPE *in2, ITYPE *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = (in1[i] OP in2[i]) ? 2 : 4;
+}
+
+void
+bar_int (FTYPE *in1, FTYPE *in2, ITYPE *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = (in1[i] INV_OP in2[i]) ? 4 : 2;
+}
+
+void
+foobar_int (FTYPE *in1, FTYPE *in2, ITYPE *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = (in1[i] OP 0.0) ? 4 : 2;
+}
+
+void
+foobarbar_int (FTYPE *in1, FTYPE *in2, ITYPE *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = (in1[i] INV_OP 0.0) ? 4 : 2;
+}
+
+int
+main (int argc, char **argv)
+{
+  FTYPE out1[N];
+  FTYPE out2[N];
+  ITYPE outi1[N];
+  ITYPE outi2[N];
+
+  int i = 0;
+  foo (input1, input2, out1);
+  bar (input1, input2, out2);
+  for (i = 0; i < N; i++)
+    if (out1[i] != out2[i])
+      abort ();
+  foobar (input1, input2, out1);
+  foobarbar (input1, input2, out2);
+  for (i = 0; i < N; i++)
+    if (out1[i] == out2[i])
+      abort ();
+
+  foo_int (input1, input2, outi1);
+  bar_int (input1, input2, outi2);
+  for (i = 0; i < N; i++)
+    if (outi1[i] != outi2[i])
+      abort ();
+  foobar_int (input1, input2, outi1);
+  foobarbar_int (input1, input2, outi2);
+  for (i = 0; i < N; i++)
+    if (outi1[i] == outi2[i])
+      abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c
new file mode 100644
index 000000000..1285a5063
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin-compile.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -ffast-math" } */
+
+#include "vect-fmax-fmin.x"
+
+/* { dg-final { scan-assembler "fmaxnm\\tv" } } */
+/* { dg-final { scan-assembler "fminnm\\tv" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c
new file mode 100644
index 000000000..42600b739
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.c
@@ -0,0 +1,105 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -ffast-math" } */
+
+extern void abort (void);
+
+#include "vect-fmax-fmin.x"
+
+#include "vect-fmaxv-fminv.x"
+
+#define DEFN_SETV(type) \
+		set_vector_##type (pR##type a, type n)   \
+		{ 				         \
+		  int i;			         \
+		  for (i=0; i<16; i++)		         \
+		    a[i] = n;				 \
+		}
+
+#define DEFN_CHECKV(type) \
+		void check_vector_##type (pR##type a, pR##type vec) \
+		{						    \
+		  int i;					    \
+		  for (i=0; i<16; i++)				    \
+		    if (a[i] != vec[i])				    \
+		      abort ();					    \
+		}
+
+#define TEST2(fname, type) \
+			set_vector_##type (c##type, 0.0);              \
+			fname##_##type (a##type, b##type);             \
+			check_vector_##type (c##type, fname##_##type##_vector);
+
+#define TEST3(fname, type) \
+			set_vector_##type (c##type, 0.0);              \
+			fname##_##type (a##type, b##type, c##type);    \
+			check_vector_##type (c##type, fname##_##type##_vector);
+
+#define TEST(fname, N) \
+		TEST##N (fname, F32); \
+		TEST##N (fname, F64);
+
+typedef float F32;
+typedef double F64;
+
+DEFN_SETV (F32)
+DEFN_SETV (F64)
+
+DEFN_CHECKV (F32)
+DEFN_CHECKV (F64)
+
+int main (void)
+{
+
+  F32 aF32[16];
+  F32 bF32[16];
+  F32 cF32[16];
+
+  F64 aF64[16];
+  F64 bF64[16];
+  F64 cF64[16];
+  int i;
+
+  /* Golden vectors.  */
+  F32 max_F32_vector[] = { 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0,
+			   8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0 };
+
+  F64 max_F64_vector[] = { 15.0, 14.0, 13.0, 12.0, 11.0, 10.0, 9.0, 8.0,
+			   8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0 };
+
+  F32 min_F32_vector[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0,
+			   7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.0 };
+
+  F64 min_F64_vector[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0,
+			   7.0, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.0 };
+
+  F32 minv_F32_value = 0.0f;
+  F32 maxv_F32_value = 15.0f;
+
+  F64 minv_F64_value = 0.0;
+  F64 maxv_F64_value = 15.0;
+
+  /* Setup input vectors.  */
+  for (i=0; i<16; i++)
+    {
+      aF32[i] = (float)(15-i);
+      bF32[i] = (float)i;
+      aF64[i] = (double)(15-i);
+      bF64[i] = (double)i;
+    }
+
+  TEST (max, 3);
+  TEST (min, 3);
+
+  /* Test across lanes ops.  */
+  if (maxv_f32 (max_F32_vector) != maxv_F32_value)
+    abort ();
+  if (minv_f32 (min_F32_vector) != minv_F32_value)
+    abort ();
+
+  if (maxv_f64 (max_F64_vector) != maxv_F64_value)
+    abort ();
+  if (minv_f64 (min_F64_vector) != minv_F64_value)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x
new file mode 100644
index 000000000..a8948208a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmax-fmin.x
@@ -0,0 +1,32 @@
+
+typedef float *__restrict__ pRF32;
+typedef double *__restrict__ pRF64;
+
+
+void max_F32 (pRF32 a, pRF32 b, pRF32 c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] = (a[i] > b[i] ? a[i] : b[i]);
+}
+
+void min_F32 (pRF32 a, pRF32 b, pRF32 c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] = (a[i] < b[i] ? a[i] : b[i]);
+}
+
+void max_F64 (pRF64 a, pRF64 b, pRF64 c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] = (a[i] > b[i] ? a[i] : b[i]);
+}
+
+void min_F64 (pRF64 a, pRF64 b, pRF64 c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] = (a[i] < b[i] ? a[i] : b[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c
new file mode 100644
index 000000000..975cef9c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv-compile.c
@@ -0,0 +1,10 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -ffast-math -fno-vect-cost-model" } */
+
+#include "vect-fmaxv-fminv.x"
+
+/* { dg-final { scan-assembler "fminnmv" } } */
+/* { dg-final { scan-assembler "fmaxnmv" } } */
+/* { dg-final { scan-assembler "fminnmp" } } */
+/* { dg-final { scan-assembler "fmaxnmp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x
new file mode 100644
index 000000000..0bc6ba494
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmaxv-fminv.x
@@ -0,0 +1,43 @@
+
+typedef float *__restrict__ pRF32;
+typedef double *__restrict__ pRF64;
+
+float maxv_f32 (pRF32 a)
+{
+  int i;
+  float s = a[0];
+  for (i=1;i<8;i++)
+    s = (s > a[i] ? s :  a[i]);
+
+  return s;
+}
+
+float minv_f32 (pRF32 a)
+{
+  int i;
+  float s = a[0];
+  for (i=1;i<16;i++)
+    s = (s < a[i] ? s :  a[i]);
+
+  return s;
+}
+
+double maxv_f64 (pRF64 a)
+{
+  int i;
+  double s = a[0];
+  for (i=1;i<8;i++)
+    s = (s > a[i] ? s :  a[i]);
+
+  return s;
+}
+
+double minv_f64 (pRF64 a)
+{
+  int i;
+  double s = a[0];
+  for (i=1;i<16;i++)
+    s = (s < a[i] ? s :  a[i]);
+
+  return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
new file mode 100644
index 000000000..667d22745
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd-zero.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+
+#define N 32
+
+void
+foo (double *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = 0.0;
+}
+
+/* { dg-final { scan-assembler "movi\\tv\[0-9\]+\\.2d, 0" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
new file mode 100644
index 000000000..a0211c715
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovd.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+
+#define N 32
+
+void
+foo (double *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = 4.25;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-assembler "fmov\\tv\[0-9\]+\\.2d, 4\\.25" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
new file mode 100644
index 000000000..259a9d41f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf-zero.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+
+#define N 32
+
+void
+foo (float *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = 0.0;
+}
+
+/* { dg-final { scan-assembler "movi\\tv\[0-9\]+\\.\[24\]s, 0" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
new file mode 100644
index 000000000..0bd21dc19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fmovf.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+
+#define N 32
+
+void
+foo (float *output)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = 4.25;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-assembler "fmov\\tv\[0-9\]+\\.\[24\]s, 4\\.25" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c
new file mode 100644
index 000000000..47ef100e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c
@@ -0,0 +1,14 @@
+
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#include "vect-fp.x"
+
+/* { dg-final { scan-assembler "fadd\\tv" } } */
+/* { dg-final { scan-assembler "fsub\\tv" } } */
+/* { dg-final { scan-assembler "fmul\\tv" } } */
+/* { dg-final { scan-assembler "fdiv\\tv" } } */
+/* { dg-final { scan-assembler "fneg\\tv" } } */
+/* { dg-final { scan-assembler "fabs\\tv" } } */
+/* { dg-final { scan-assembler "fabd\\tv" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.c
new file mode 100644
index 000000000..bcf9d9d75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.c
@@ -0,0 +1,148 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+
+#include "vect-fp.x"
+
+
+#define DEFN_SETV(type) \
+		set_vector_##type (pR##type a, type n)   \
+		{ 				         \
+		  int i;			         \
+		  for (i=0; i<16; i++)		         \
+		    a[i] = n;				 \
+		}
+
+#define DEFN_CHECKV(type) \
+		void check_vector_##type (pR##type a, pR##type vec) \
+		{						    \
+		  int i;					    \
+		  for (i=0; i<16; i++)				    \
+		    if (a[i] != vec[i])				    \
+		      abort ();					    \
+		}
+
+#define TEST2(fname, type) \
+			set_vector_##type (a##type, 0.0);              \
+			fname##_##type (a##type, b##type);             \
+			check_vector_##type (a##type, fname##_##type##_vector);
+
+#define TEST3(fname, type) \
+			set_vector_##type (a##type, 0.0);              \
+			fname##_##type (a##type, b##type, c##type);    \
+			check_vector_##type (a##type, fname##_##type##_vector);
+
+#define TEST(fname, N) \
+		TEST##N(fname, F32); \
+		TEST##N(fname, F64);
+
+DEFN_SETV (F32)
+DEFN_SETV (F64)
+
+DEFN_CHECKV (F32)
+DEFN_CHECKV (F64)
+
+int main (void)
+{
+  F32 aF32[16];
+  F32 bF32[16];
+  F32 cF32[16];
+
+  F64 aF64[16];
+  F64 bF64[16];
+  F64 cF64[16];
+  int i;
+
+  F32  add_F32_vector[] = { 3.0f, 5.0f, 7.0f, 9.0f, 11.0f,
+			    13.0f, 15.0f, 17.0f, 19.0f,
+			    21.0f, 23.0f, 25.0f, 27.0f,
+			    29.0f, 31.0f, 33.0f };
+
+  F64  add_F64_vector[] = { 3.0, 5.0, 7.0, 9.0, 11.0,
+			    13.0, 15.0, 17.0, 19.0,
+			    21.0, 23.0, 25.0, 27.0,
+			    29.0, 31.0, 33.0 };
+
+  F32  sub_F32_vector[] = { -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
+			    -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
+			    -1.0f, -1.0f, -1.0f, -1.0f, -1.0f,
+			    -1.0f };
+
+  F64  sub_F64_vector[] = { -1.0, -1.0, -1.0, -1.0, -1.0,
+			    -1.0, -1.0, -1.0, -1.0, -1.0,
+			    -1.0, -1.0, -1.0, -1.0, -1.0,
+			    -1.0 };
+
+  F32  mul_F32_vector[] = { 2.0f, 6.0f, 12.0f, 20.0f, 30.0f,
+			    42.0f, 56.0f, 72.0f, 90.0f,
+			    110.0f, 132.0f, 156.0f, 182.0f,
+			    210.0f, 240.0f, 272.0f };
+
+  F64  mul_F64_vector[] = { 2.0, 6.0, 12.0, 20.0, 30.0,
+			    42.0, 56.0, 72.0, 90.0,
+			    110.0, 132.0, 156.0, 182.0,
+			    210.0, 240.0, 272.0 };
+
+  F32  div_F32_vector[] = { 0.5f, (float)(2.0/3.0), 0.75f, 0.8f,
+			    (float)(5.0/6.0), (float)(6.0/7.0), 0.875000f,
+			    (float)(8.0/9.0), 0.900000f, (float)(10.0/11.0),
+			    (float)(11.0/12.0), (float)(12.0/13.0),
+			    (float)(13.0/14.0), (float)(14.0/15.0), 0.937500f,
+			    (float)(16.0/17.0) };
+
+  F64  div_F64_vector[] = { 0.5, (2.0/3.0), 0.75, 0.8, (5.0/6.0),
+			    (6.0/7.0), 0.875000, (8.0/9.0), 0.900000,
+			    (10.0/11.0), (11.0/12.0), (12.0/13.0), (13.0/14.0),
+			    (14.0/15.0), 0.937500, (16.0/17.0) };
+
+  F32  neg_F32_vector[] = { -1.0f, -2.0f, -3.0f, -4.0f,
+			    -5.0f, -6.0f, -7.0f, -8.0f,
+			    -9.0f, -10.0f, -11.0f, -12.0f,
+			    -13.0f, -14.0f, -15.0f, -16.0f };
+
+  F64  neg_F64_vector[] = { -1.0, -2.0, -3.0, -4.0,
+			    -5.0, -6.0, -7.0, -8.0,
+			    -9.0, -10.0, -11.0, -12.0,
+			    -13.0, -14.0, -15.0, -16.0 };
+
+  F32  abs_F32_vector[] = { 1.0f, 2.0f, 3.0f, 4.0f,
+			    5.0f, 6.0f, 7.0f, 8.0f,
+			    9.0f, 10.0f, 11.0f, 12.0f,
+			    13.0f, 14.0f, 15.0f, 16.0f };
+
+  F64  abs_F64_vector[] = { 1.0, 2.0, 3.0, 4.0,
+			    5.0, 6.0, 7.0, 8.0,
+			    9.0, 10.0, 11.0, 12.0,
+			    13.0, 14.0, 15.0, 16.0 };
+
+  F32  fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f,
+			     1.0f, 1.0f, 1.0f, 1.0f,
+			     1.0f, 1.0f, 1.0f, 1.0f,
+			     1.0f, 1.0f, 1.0f, 1.0f };
+
+  F64  fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0,
+			     1.0, 1.0, 1.0, 1.0,
+			     1.0, 1.0, 1.0, 1.0,
+			     1.0, 1.0, 1.0, 1.0 };
+
+  /* Setup input vectors.  */
+  for (i=1; i<=16; i++)
+    {
+      bF32[i-1] = (float)i;
+      cF32[i-1] = (float)(i+1);
+      bF64[i-1] = (double)i;
+      cF64[i-1] = (double)(i+1);
+    }
+
+  TEST (add, 3);
+  TEST (sub, 3);
+  TEST (mul, 3);
+  TEST (div, 3);
+  TEST (neg, 2);
+  TEST (abs, 2);
+  TEST (fabd, 3);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.x
new file mode 100644
index 000000000..82d1b1c50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-fp.x
@@ -0,0 +1,60 @@
+
+typedef float F32;
+typedef double F64;
+typedef float *__restrict__ pRF32;
+typedef double *__restrict__ pRF64;
+
+extern float fabsf (float);
+extern double fabs (double);
+
+#define DEF3a(fname, type, op) \
+			 void  fname##_##type (pR##type a,   \
+					       pR##type b,   \
+					       pR##type c)   \
+			 {				     \
+			   int i;			     \
+			   for (i = 0; i < 16; i++)	     \
+			     a[i] = op (b[i] - c[i]);	     \
+			 }
+
+#define DEF3(fname, type, op) \
+			void  fname##_##type (pR##type a,   \
+					      pR##type b,   \
+					      pR##type c)   \
+			{				    \
+			  int i; 			    \
+			  for (i = 0; i < 16; i++)	    \
+			    a[i] = b[i] op c[i];	    \
+			}
+
+#define DEF2(fname, type, op) \
+			void fname##_##type (pR##type a, \
+					     pR##type b) \
+			{				  \
+			  int i; 			  \
+			  for (i = 0; i < 16; i++)	  \
+			    a[i] = op(b[i]);		  \
+			}
+
+
+#define DEFN3a(fname, op) \
+		 DEF3a (fname, F32, op) \
+		 DEF3a (fname, F64, op)
+
+#define DEFN3(fname, op) \
+		DEF3 (fname, F32, op) \
+		DEF3 (fname, F64, op)
+
+#define DEFN2(fname, op) \
+		DEF2 (fname, F32, op) \
+		DEF2 (fname, F64, op)
+
+DEFN3 (add, +)
+DEFN3 (sub, -)
+DEFN3 (mul, *)
+DEFN3 (div, /)
+DEFN2 (neg, -)
+DEF2 (abs, F32, fabsf)
+DEF2 (abs, F64, fabs)
+DEF3a (fabd, F32, fabsf)
+DEF3a (fabd, F64, fabs)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c
new file mode 100644
index 000000000..66e016855
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-vect-cost-model" } */
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (float)
+DEF (double)
+
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c
new file mode 100644
index 000000000..761777f79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fno-vect-cost-model" } */
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (int8_t)
+DEF (int16_t)
+DEF (int32_t)
+DEF (int64_t)
+
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8b"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.16b"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4h"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */
+/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c
new file mode 100644
index 000000000..5e384e1bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (float)
+DEF (double)
+
+#define FOOD(TYPE) \
+  foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE)
+
+#define FOOQ(TYPE) \
+  foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE)
+
+#define CHECKD(TYPE) \
+  for (i = 0; i < 8 / sizeof (TYPE); i++) \
+    if (output_ ## TYPE[i] != a_ ## TYPE) \
+      abort ()
+
+#define CHECKQ(TYPE) \
+  for (i = 0; i < 32 / sizeof (TYPE); i++) \
+    if (output_ ## TYPE[i] != a_ ## TYPE) \
+      abort ()
+
+#define DECL(TYPE) \
+  TYPE output_ ## TYPE[32]; \
+  TYPE a_ ## TYPE = (TYPE)12.2
+
+int
+main (void)
+{
+
+  DECL(float);
+  DECL(double);
+  int i;
+
+  FOOD (float);
+  CHECKD (float);
+  FOOQ (float);
+  CHECKQ (float);
+
+  FOOD (double);
+  CHECKD (double);
+  FOOQ (double);
+  CHECKQ (double);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c
new file mode 100644
index 000000000..f0571de9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+
+#include "stdint.h"
+#include "vect-ld1r.x"
+
+DEF (int8_t)
+DEF (int16_t)
+DEF (int32_t)
+DEF (int64_t)
+
+#define FOOD(TYPE) \
+  foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE)
+
+#define FOOQ(TYPE) \
+  foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE)
+
+#define CHECKD(TYPE) \
+  for (i = 0; i < 8 / sizeof (TYPE); i++) \
+    if (output_ ## TYPE[i] != a_ ## TYPE) \
+      abort ()
+
+#define CHECKQ(TYPE) \
+  for (i = 0; i < 32 / sizeof (TYPE); i++) \
+    if (output_ ## TYPE[i] != a_ ## TYPE) \
+      abort ()
+
+#define DECL(TYPE) \
+  TYPE output_ ## TYPE[32]; \
+  TYPE a_ ## TYPE = (TYPE)12
+
+int
+main (void)
+{
+
+  DECL(int8_t);
+  DECL(int16_t);
+  DECL(int32_t);
+  DECL(int64_t);
+  int i;
+
+  FOOD (int8_t);
+  CHECKD (int8_t);
+  FOOQ (int8_t);
+  CHECKQ (int8_t);
+
+  FOOD (int16_t);
+  CHECKD (int16_t);
+  FOOQ (int16_t);
+  CHECKQ (int16_t);
+
+  FOOD (int32_t);
+  CHECKD (int32_t);
+  FOOQ (int32_t);
+  CHECKQ (int32_t);
+
+  FOOD (int64_t);
+  CHECKD (int64_t);
+  FOOQ (int64_t);
+  CHECKQ (int64_t);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x
new file mode 100644
index 000000000..680ce4345
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-ld1r.x
@@ -0,0 +1,15 @@
+
+#define DEF(TYPE) \
+  void \
+  foo_ ## TYPE ## _d (TYPE *a, TYPE *output) \
+  { \
+    int i; \
+    for (i = 0; i < 8 / sizeof (TYPE); i++) \
+      output[i] = *a; \
+  } \
+  foo_ ## TYPE ## _q (TYPE *a, TYPE *output) \
+  { \
+    int i; \
+    for (i = 0; i < 32 / sizeof (TYPE); i++) \
+      output[i] = *a; \
+  }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-movi.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-movi.c
new file mode 100644
index 000000000..59a0bd5cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-movi.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+#define N 16
+
+static void
+movi_msl8 (int *__restrict a)
+{
+  int i;
+
+  /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */
+  for (i = 0; i < N; i++)
+    a[i] = 0xabff;
+}
+
+static void
+movi_msl16 (int *__restrict a)
+{
+  int i;
+
+  /* { dg-final { scan-assembler "movi\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */
+  for (i = 0; i < N; i++)
+    a[i] = 0xabffff;
+}
+
+static void
+mvni_msl8 (int *__restrict a)
+{
+  int i;
+
+  /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 8" } } */
+  for (i = 0; i < N; i++)
+    a[i] = 0xffff5400;
+}
+
+static void
+mvni_msl16 (int *__restrict a)
+{
+  int i;
+
+  /* { dg-final { scan-assembler "mvni\\tv\[0-9\]+\.4s, 0xab, msl 16" } } */
+  for (i = 0; i < N; i++)
+    a[i] = 0xff540000;
+}
+
+int
+main (void)
+{
+  int a[N] = { 0 };
+  int i;
+
+#define CHECK_ARRAY(a, val)	\
+  for (i = 0; i < N; i++)	\
+    if (a[i] != val)		\
+      abort ();
+
+  movi_msl8 (a);
+  CHECK_ARRAY (a, 0xabff);
+
+  movi_msl16 (a);
+  CHECK_ARRAY (a, 0xabffff);
+
+  mvni_msl8 (a);
+  CHECK_ARRAY (a, 0xffff5400);
+
+  mvni_msl16 (a);
+  CHECK_ARRAY (a, 0xff540000);
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c
new file mode 100644
index 000000000..e90c97ff3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull-compile.c
@@ -0,0 +1,24 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 16
+
+#include "vect-mull.x"
+
+DEF_MULL2 (DEF_MULLB)
+DEF_MULL2 (DEF_MULLH)
+DEF_MULL2 (DEF_MULLS)
+
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "smull\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "umull\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "smull2\\tv\[0-9\]+\.2d"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.8h"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.4s"} } */
+/* { dg-final { scan-assembler "umull2\\tv\[0-9\]+\.2d"} } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.c
new file mode 100644
index 000000000..62a3552f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.c
@@ -0,0 +1,138 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "limits.h"
+
+extern void abort (void);
+
+#define N 16
+
+#include "vect-mull.x"
+
+#define SET_VEC(size, type, sign)  \
+			    void set_vector_##sign##size \
+						   (pR##sign##INT##size b, \
+						    pR##sign##INT##size c) \
+		      	    {				        \
+			      int i;			        \
+			      for (i=0; i<N; i++)	        \
+			      { \
+			        b[i] = (type)((INT_MAX >> (32 - size)) - i); \
+			        c[i] = (type)((INT_MAX >> (32 - size)) - i * 2); \
+			      } \
+		      	    }
+
+#define CHECK_VEC(size, sign) void check_vector_##sign##size (pR##sign##INT##size a, \
+						  pR##sign##INT##size b) \
+			{				       \
+			  int i;			       \
+			  for (i=0; i<N; i++)		       \
+			    if (a[i] != b[i])  		       \
+			      abort (); 		       \
+			}
+
+SET_VEC (8,  signed char,  S)
+SET_VEC (16, signed short, S)
+SET_VEC (32, signed int,   S)
+
+SET_VEC (8,  unsigned char,  U)
+SET_VEC (16, unsigned short, U)
+SET_VEC (32, unsigned int,   U)
+
+DEF_MULL2 (DEF_MULLB)
+DEF_MULL2 (DEF_MULLH)
+DEF_MULL2 (DEF_MULLS)
+
+CHECK_VEC (8, S)
+CHECK_VEC (8, U)
+CHECK_VEC (16, S)
+CHECK_VEC (16, U)
+CHECK_VEC (32, S)
+CHECK_VEC (32, U)
+CHECK_VEC (64, S)
+CHECK_VEC (64, U)
+
+int main (void)
+{
+
+#define DECL_VAR(name) signed char name##_S8[N]; \
+		       signed short name##_S16[N]; \
+		       signed int name##_S32[N]; \
+		       unsigned char name##_U8[N]; \
+		       unsigned short name##_U16[N]; \
+		       unsigned int name##_U32[N];
+
+  DECL_VAR (output);
+  signed long long output_S64[N];
+  unsigned long long output_U64[N];
+
+  DECL_VAR (input1);
+  DECL_VAR (input2);
+
+  signed short expected_S16[] =
+		    { 16129, 15750, 15375, 15004, 14637, 14274, 13915, 13560,
+		      13209, 12862, 12519, 12180, 11845, 11514, 11187, 10864 };
+
+  signed int expected_S32[] =
+		    { 1073676289, 1073577990, 1073479695, 1073381404, 1073283117,
+		      1073184834, 1073086555, 1072988280, 1072890009, 1072791742,
+		      1072693479, 1072595220, 1072496965, 1072398714, 1072300467,
+		      1072202224 };
+
+  signed long long expected_S64[] =
+		    { 4611686014132420609LL, 4611686007689969670LL,
+		      4611686001247518735LL, 4611685994805067804LL,
+		      4611685988362616877LL, 4611685981920165954LL,
+		      4611685975477715035LL, 4611685969035264120LL,
+		      4611685962592813209LL, 4611685956150362302LL,
+		      4611685949707911399LL, 4611685943265460500LL,
+		      4611685936823009605LL, 4611685930380558714LL,
+		      4611685923938107827LL, 4611685917495656944LL };
+
+  unsigned short expected_U16[] =
+		    { 16129, 15750, 15375, 15004, 14637, 14274, 13915, 13560,
+		      13209, 12862, 12519, 12180, 11845, 11514, 11187, 10864 };
+
+  unsigned int expected_U32[] =
+		    { 1073676289, 1073577990, 1073479695, 1073381404, 1073283117,
+		      1073184834, 1073086555, 1072988280, 1072890009, 1072791742,
+		      1072693479, 1072595220, 1072496965, 1072398714, 1072300467,
+		      1072202224 };
+
+  unsigned long long expected_U64[] =
+		    { 4611686014132420609ULL, 4611686007689969670ULL,
+		      4611686001247518735ULL, 4611685994805067804ULL,
+		      4611685988362616877ULL, 4611685981920165954ULL,
+		      4611685975477715035ULL, 4611685969035264120ULL,
+		      4611685962592813209ULL, 4611685956150362302ULL,
+		      4611685949707911399ULL, 4611685943265460500ULL,
+		      4611685936823009605ULL, 4611685930380558714ULL,
+		      4611685923938107827ULL, 4611685917495656944ULL };
+
+  /* Set up input.  */
+  set_vector_S8 (input1_S8, input2_S8);
+  set_vector_S16 (input1_S16, input2_S16);
+  set_vector_S32 (input1_S32, input2_S32);
+  set_vector_U8 (input1_U8, input2_U8);
+  set_vector_U16 (input1_U16, input2_U16);
+  set_vector_U32 (input1_U32, input2_U32);
+
+  /* Calculate actual results.  */
+  widen_mult_Sb (output_S16, input1_S8, input2_S8);
+  widen_mult_Sh (output_S32, input1_S16, input2_S16);
+  widen_mult_Ss (output_S64, input1_S32, input2_S32);
+  widen_mult_Ub (output_U16, input1_U8, input2_U8);
+  widen_mult_Uh (output_U32, input1_U16, input2_U16);
+  widen_mult_Us (output_U64, input1_U32, input2_U32);
+
+  /* Check actual vs. expected.  */
+  check_vector_S16 (expected_S16, output_S16);
+  check_vector_S32 (expected_S32, output_S32);
+  check_vector_S64 (expected_S64, output_S64);
+  check_vector_U16 (expected_U16, output_U16);
+  check_vector_U32 (expected_U32, output_U32);
+  check_vector_U64 (expected_U64, output_U64);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.x
new file mode 100644
index 000000000..39ec43d77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-mull.x
@@ -0,0 +1,49 @@
+
+typedef signed char *__restrict__ pRSINT8;
+typedef signed short *__restrict__ pRSINT16;
+typedef signed int *__restrict__ pRSINT32;
+typedef signed long long *__restrict__ pRSINT64;
+
+typedef unsigned char *__restrict__ pRUINT8;
+typedef unsigned short *__restrict__ pRUINT16;
+typedef unsigned int *__restrict__ pRUINT32;
+typedef unsigned long long *__restrict__ pRUINT64;
+
+typedef signed short SH;
+typedef unsigned short UH;
+typedef signed int SS;
+typedef unsigned int US;
+typedef signed long long SLL;
+typedef unsigned long long ULL;
+
+#define DEF_MULLB(sign)   \
+		   void widen_mult_##sign##b  (pR##sign##INT##16 a, \
+					       pR##sign##INT##8 b, \
+					       pR##sign##INT##8 c) \
+		   { \
+			int i;  \
+			for (i=0; i<N; i++)     \
+			  a[i] = (sign##H)b[i] * c[i];   \
+		   }
+
+#define DEF_MULLH(sign)   \
+		   void widen_mult_##sign##h (pR##sign##INT##32 a, \
+					      pR##sign##INT##16 b, \
+					      pR##sign##INT##16 c) \
+		   { \
+			int i;  \
+			for (i=0; i<N; i++)     \
+			  a[i] = (sign##S)b[i] * c[i];   \
+		   }
+#define DEF_MULLS(sign)   \
+		   void widen_mult_##sign##s (pR##sign##INT##64 a, \
+					      pR##sign##INT##32 b, \
+					      pR##sign##INT##32 c) \
+		   { \
+			int i;  \
+			for (i=0; i<N; i++)     \
+			  a[i] = (sign##LL)b[i] * c[i];   \
+		   }
+
+#define DEF_MULL2(x) x (S) \
+		     x (U)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c
new file mode 100644
index 000000000..7db12047e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vaddv.c
@@ -0,0 +1,128 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -ffast-math" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+#define NUM_TESTS 16
+#define DELTA 0.000001
+
+int8_t input_int8[] = {1, 56, 2, -9, -90, 23, 54, 76,
+		       -4, 34, 110, -110, 6, 4, 75, -34};
+int16_t input_int16[] = {1, 56, 2, -9, -90, 23, 54, 76,
+			 -4, 34, 110, -110, 6, 4, 75, -34};
+int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76,
+			 -4, 34, 110, -110, 6, 4, 75, -34};
+int64_t input_int64[] = {1, 56, 2, -9, -90, 23, 54, 76,
+			 -4, 34, 110, -110, 6, 4, 75, -34};
+
+uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76,
+			 4, 34, 110, 110, 6, 4, 75, 34};
+uint16_t input_uint16[] = {1, 56, 2, 9, 90, 23, 54, 76,
+			   4, 34, 110, 110, 6, 4, 75, 34};
+uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76,
+			   4, 34, 110, 110, 6, 4, 75, 34};
+
+uint64_t input_uint64[] = {1, 56, 2, 9, 90, 23, 54, 76,
+			   4, 34, 110, 110, 6, 4, 75, 34};
+
+float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f,
+			 200.0f, -800.0f, -13.0f, -0.5f,
+			 7.9f, -870.0f, 10.4f, 310.11f,
+			 0.0f, -865.0f, -2213.0f, -1.5f};
+
+double input_float64[] = {0.1, -0.1, 0.4, 10.3,
+			  200.0, -800.0, -13.0, -0.5,
+			  7.9, -870.0, 10.4, 310.11,
+			  0.0, -865.0, -2213.0, -1.5};
+
+#define EQUALF(a, b) (fabsf (a - b) < DELTA)
+#define EQUALD(a, b) (fabs (a - b) < DELTA)
+#define EQUALL(a, b) (a == b)
+
+#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT)				\
+int									\
+test_vaddv##SUFFIX##_##TYPE##x##LANES##_t (void)			\
+{									\
+  int i, j;								\
+  int moves = (NUM_TESTS - LANES) + 1;					\
+  TYPE##_t out_l[NUM_TESTS];						\
+  TYPE##_t out_v[NUM_TESTS];						\
+									\
+  /* Calculate linearly.  */						\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      out_l[i] = input_##TYPE[i];					\
+      for (j = 1; j < LANES; j++)					\
+	out_l[i] += input_##TYPE[i + j];				\
+    }									\
+									\
+  /* Calculate using vector reduction intrinsics.  */			\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i);	\
+      out_v[i] = vaddv##Q##_##SUFFIX (t1);				\
+    }									\
+									\
+  /* Compare.  */							\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      if (!EQUAL##FLOAT (out_v[i], out_l[i]))				\
+	return 0;							\
+    }									\
+  return 1;								\
+}
+
+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F)	\
+TEST (STYPE,  , TYPE, W32, F)				\
+TEST (STYPE, q, TYPE, W64, F)				\
+
+BUILD_VARIANTS (int8, s8, 8, 16, L)
+BUILD_VARIANTS (uint8, u8, 8, 16, L)
+/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "addv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+BUILD_VARIANTS (int16, s16, 4, 8, L)
+BUILD_VARIANTS (uint16, u16, 4, 8, L)
+/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "addv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+BUILD_VARIANTS (int32, s32, 2, 4, L)
+BUILD_VARIANTS (uint32, u32, 2, 4, L)
+/* { dg-final { scan-assembler "addp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "addv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+TEST (s64, q, int64, 2, D)
+TEST (u64, q, uint64, 2, D)
+/* { dg-final { scan-assembler "addp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */
+
+BUILD_VARIANTS (float32, f32, 2, 4, F)
+/* { dg-final { scan-assembler "faddp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "faddp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+TEST (f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "faddp\\td\[0-9\]+\, v\[0-9\]+\.2d" } } */
+
+#undef TEST
+#define TEST(SUFFIX, Q, TYPE, LANES, FLOAT)		\
+{							\
+  if (!test_vaddv##SUFFIX##_##TYPE##x##LANES##_t ())	\
+    abort ();						\
+}
+
+int
+main (int argc, char **argv)
+{
+BUILD_VARIANTS (int8, s8, 8, 16, L)
+BUILD_VARIANTS (uint8, u8, 8, 16, L)
+BUILD_VARIANTS (int16, s16, 4, 8, L)
+BUILD_VARIANTS (uint16, u16, 4, 8, L)
+BUILD_VARIANTS (int32, s32, 2, 4, L)
+BUILD_VARIANTS (uint32, u32, 2, 4, L)
+
+BUILD_VARIANTS (float32, f32, 2, 4, F)
+TEST (f64, q, float64, 2, D)
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vca.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vca.c
new file mode 100644
index 000000000..c0cf2efdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vca.c
@@ -0,0 +1,89 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+#define NUM_TESTS 8
+
+float input_s1[] = {0.1f, -0.1f, 0.4f, 10.3f, 200.0f, -800.0f, -13.0f, -0.5f};
+float input_s2[] = {-0.2f, 0.4f, 0.04f, -100.3f, 2.0f, -80.0f, 13.0f, -0.5f};
+double input_d1[] = {0.1, -0.1, 0.4, 10.3, 200.0, -800.0, -13.0, -0.5};
+double input_d2[] = {-0.2, 0.4, 0.04, -100.3, 2.0, -80.0, 13.0, -0.5};
+
+#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F)			\
+int									\
+test_vca##T##_float##WIDTH##x##LANES##_t (void)				\
+{									\
+  int ret = 0;								\
+  int i = 0;								\
+  uint##WIDTH##_t output[NUM_TESTS];					\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    {									\
+      float##WIDTH##_t f1 = fabs##F (input_##SUFFIX##1[i]);		\
+      float##WIDTH##_t f2 = fabs##F (input_##SUFFIX##2[i]);		\
+      /* Inhibit optimization of our linear test loop.  */		\
+      asm volatile ("" : : : "memory");					\
+      output[i] = f1 CMP f2 ? -1 : 0;					\
+    }									\
+									\
+  for (i = 0; i < NUM_TESTS; i += LANES)				\
+    {									\
+      float##WIDTH##x##LANES##_t in1 =					\
+	vld1##Q##_f##WIDTH (input_##SUFFIX##1 + i);			\
+      float##WIDTH##x##LANES##_t in2 =					\
+	vld1##Q##_f##WIDTH (input_##SUFFIX##2 + i);			\
+      uint##WIDTH##x##LANES##_t expected_out =				\
+	vld1##Q##_u##WIDTH (output + i);				\
+      uint##WIDTH##x##LANES##_t out =					\
+	veor##Q##_u##WIDTH (vca##T##Q##_f##WIDTH (in1, in2),		\
+			    expected_out);				\
+      vst1##Q##_u##WIDTH (output + i, out);				\
+    }									\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    ret |= output[i];							\
+									\
+  return ret;								\
+}
+
+#define BUILD_VARIANTS(T, CMP)	\
+TEST (T, CMP, s, 32, 2,  , f)	\
+TEST (T, CMP, s, 32, 4, q, f)	\
+TEST (T, CMP, d, 64, 2, q,  )
+
+BUILD_VARIANTS (ge, >=)
+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "facge\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+
+BUILD_VARIANTS (gt, >)
+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "facgt\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+
+/* No need for another scan-assembler as these tests
+   also generate facge, facgt instructions.  */
+BUILD_VARIANTS (le, <=)
+BUILD_VARIANTS (lt, <)
+
+#undef TEST
+#define TEST(T, CMP, SUFFIX, WIDTH, LANES, Q, F)	\
+if (test_vca##T##_float##WIDTH##x##LANES##_t ())	\
+  abort ();
+
+int
+main (int argc, char **argv)
+{
+BUILD_VARIANTS (ge, >=)
+BUILD_VARIANTS (gt, >)
+BUILD_VARIANTS (le, <=)
+BUILD_VARIANTS (lt, <)
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c
new file mode 100644
index 000000000..6066d7d25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vcvt.c
@@ -0,0 +1,132 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -ffast-math" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern double fabs (double);
+
+#define NUM_TESTS 8
+#define DELTA 0.000001
+
+float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f,
+		     200.0f, -800.0f, -13.0f, -0.5f};
+double input_f64[] = {0.1, -0.1, 0.4, 10.3,
+		      200.0, -800.0, -13.0, -0.5};
+
+#define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D)		     		\
+int									\
+test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t (void)		\
+{									\
+  int ret = 1;								\
+  int i = 0;								\
+  int nlanes = LANES;							\
+  U##int##WIDTH##_t expected_out[NUM_TESTS];				\
+  U##int##WIDTH##_t actual_out[NUM_TESTS];				\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    {									\
+      expected_out[i]							\
+	= vcvt##SUFFIX##D##_##S##WIDTH##_f##WIDTH (input_f##WIDTH[i]);	\
+      /* Don't vectorize this.  */					\
+      asm volatile ("" : : : "memory");					\
+    }									\
+									\
+  for (i = 0; i < NUM_TESTS; i+=nlanes)					\
+    {									\
+      U##int##WIDTH##x##LANES##_t out =					\
+	vcvt##SUFFIX##Q##_##S##WIDTH##_f##WIDTH				\
+		(vld1##Q##_f##WIDTH (input_f##WIDTH + i));		\
+      vst1##Q##_##S##WIDTH (actual_out + i, out);			\
+    }									\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    ret &= fabs (expected_out[i] - actual_out[i]) < DELTA;		\
+									\
+  return ret;								\
+}									\
+
+
+#define BUILD_VARIANTS(SUFFIX)			\
+TEST (SUFFIX,  , 32, 2, s, ,s)			\
+TEST (SUFFIX, q, 32, 4, s, ,s)			\
+TEST (SUFFIX, q, 64, 2, s, ,d)			\
+TEST (SUFFIX,  , 32, 2, u,u,s)			\
+TEST (SUFFIX, q, 32, 4, u,u,s)			\
+TEST (SUFFIX, q, 64, 2, u,u,d)			\
+
+BUILD_VARIANTS ( )
+/* { dg-final { scan-assembler "fcvtzs\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzs\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtzs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (a)
+/* { dg-final { scan-assembler "fcvtas\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtas\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtas\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtau\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtau\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtau\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (m)
+/* { dg-final { scan-assembler "fcvtms\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtms\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtms\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtmu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (n)
+/* { dg-final { scan-assembler "fcvtns\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtns\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtns\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtnu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (p)
+/* { dg-final { scan-assembler "fcvtps\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtps\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtps\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tw\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tx\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fcvtpu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+
+#undef TEST
+#define TEST(SUFFIX, Q, WIDTH, LANES, S, U, D)		     		\
+{									\
+  if (!test_vcvt##SUFFIX##_##S##WIDTH##_f##WIDTH##x##LANES##_t ())	\
+    abort ();								\
+}
+
+int
+main (int argc, char **argv)
+{
+  BUILD_VARIANTS ( )
+  BUILD_VARIANTS (a)
+  BUILD_VARIANTS (m)
+  BUILD_VARIANTS (n)
+  BUILD_VARIANTS (p)
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c
new file mode 100644
index 000000000..58a57a118
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vfmaxv.c
@@ -0,0 +1,169 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -ffast-math" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+extern float fabsf (float);
+extern double fabs (double);
+extern int isnan (double);
+extern float fmaxf (float, float);
+extern float fminf (float, float);
+extern double fmax (double, double);
+extern double fmin (double, double);
+
+#define NUM_TESTS 16
+#define DELTA 0.000001
+#define NAN (0.0 / 0.0)
+
+float input_float32[] = {0.1f, -0.1f, 0.4f, 10.3f,
+			 200.0f, -800.0f, -13.0f, -0.5f,
+			 NAN, -870.0f, 10.4f, 310.11f,
+			 0.0f, -865.0f, -2213.0f, -1.5f};
+
+double input_float64[] = {0.1, -0.1, 0.4, 10.3,
+			  200.0, -800.0, -13.0, -0.5,
+			  NAN, -870.0, 10.4, 310.11,
+			  0.0, -865.0, -2213.0, -1.5};
+
+#define EQUALF(a, b) (fabsf (a - b) < DELTA)
+#define EQUALD(a, b) (fabs (a - b) < DELTA)
+
+/* Floating point 'unordered' variants.  */
+
+#undef TEST
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT)		\
+int									\
+test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void)			\
+{									\
+  int i, j;								\
+  int moves = (NUM_TESTS - LANES) + 1;					\
+  TYPE##_t out_l[NUM_TESTS];						\
+  TYPE##_t out_v[NUM_TESTS];						\
+									\
+  /* Calculate linearly.  */						\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      out_l[i] = input_##TYPE[i];					\
+      for (j = 0; j < LANES; j++)					\
+	{								\
+	  if (isnan (out_l[i]))						\
+	    continue;							\
+	  if (isnan (input_##TYPE[i + j])				\
+	      || input_##TYPE[i + j] CMP_OP out_l[i])			\
+	    out_l[i] = input_##TYPE[i + j];				\
+	}								\
+    }									\
+									\
+  /* Calculate using vector reduction intrinsics.  */			\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i);	\
+      out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1);			\
+    }									\
+									\
+  /* Compare.  */							\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      if (!EQUAL##FLOAT (out_v[i], out_l[i])				\
+			 && !(isnan (out_v[i]) && isnan (out_l[i])))	\
+	return 0;							\
+    }									\
+  return 1;								\
+}
+
+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64, F)	\
+TEST (max, >, STYPE,  , TYPE, W32, F)			\
+TEST (max, >, STYPE, q, TYPE, W64, F)			\
+TEST (min, <, STYPE,  , TYPE, W32, F)			\
+TEST (min, <, STYPE, q, TYPE, W64, F)
+
+BUILD_VARIANTS (float32, f32, 2, 4, F)
+/* { dg-final { scan-assembler "fmaxp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fminp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "fmaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "fminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+TEST (max, >, f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "fmaxp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */
+TEST (min, <, f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "fminp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */
+
+/* Floating point 'nm' variants.  */
+
+#undef TEST
+#define TEST(MAXMIN, F, SUFFIX, Q, TYPE, LANES, FLOAT)			\
+int									\
+test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t (void)		\
+{									\
+  int i, j;								\
+  int moves = (NUM_TESTS - LANES) + 1;					\
+  TYPE##_t out_l[NUM_TESTS];						\
+  TYPE##_t out_v[NUM_TESTS];						\
+									\
+  /* Calculate linearly.  */						\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      out_l[i] = input_##TYPE[i];					\
+      for (j = 0; j < LANES; j++)					\
+	out_l[i] = f##MAXMIN##F (input_##TYPE[i + j],  out_l[i]);	\
+    }									\
+									\
+  /* Calculate using vector reduction intrinsics.  */			\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i);	\
+      out_v[i] = v##MAXMIN##nmv##Q##_##SUFFIX (t1);			\
+    }									\
+									\
+  /* Compare.  */							\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      if (!EQUAL##FLOAT (out_v[i], out_l[i]))				\
+	return 0;							\
+    }									\
+  return 1;								\
+}
+
+TEST (max, f, f32, , float32, 2, D)
+/* { dg-final { scan-assembler "fmaxnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+TEST (min, f, f32, , float32, 2, D)
+/* { dg-final { scan-assembler "fminnmp\\ts\[0-9\]+, v\[0-9\]+\.2s" } } */
+TEST (max, f, f32, q, float32, 4, D)
+/* { dg-final { scan-assembler "fmaxnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+TEST (min, f, f32, q, float32, 4, D)
+/* { dg-final { scan-assembler "fminnmv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+TEST (max, , f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "fmaxnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */
+TEST (min, , f64, q, float64, 2, D)
+/* { dg-final { scan-assembler "fminnmp\\td\[0-9\]+, v\[0-9\]+\.2d" } } */
+
+#undef TEST
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT)		\
+{									\
+  if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ())		\
+    abort ();								\
+}
+
+int
+main (int argc, char **argv)
+{
+  BUILD_VARIANTS (float32, f32, 2, 4, F)
+  TEST (max, >, f64, q, float64, 2, D)
+  TEST (min, <, f64, q, float64, 2, D)
+
+#undef TEST
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES, FLOAT)		\
+{									\
+  if (!test_v##MAXMIN##nmv##SUFFIX##_##TYPE##x##LANES##_t ())		\
+    abort ();								\
+}
+
+  BUILD_VARIANTS (float32, f32, 2, 4, F)
+  TEST (max, >, f64, q, float64, 2, D)
+  TEST (min, <, f64, q, float64, 2, D)
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c
new file mode 100644
index 000000000..212e13300
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vmaxv.c
@@ -0,0 +1,117 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps -ffast-math" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define NUM_TESTS 16
+#define DELTA 0.000001
+
+int8_t input_int8[] = {1, 56, 2, -9, -90, 23, 54, 76,
+		       -4, 34, 110, -110, 6, 4, 75, -34};
+int16_t input_int16[] = {1, 56, 2, -9, -90, 23, 54, 76,
+			 -4, 34, 110, -110, 6, 4, 75, -34};
+int32_t input_int32[] = {1, 56, 2, -9, -90, 23, 54, 76,
+			 -4, 34, 110, -110, 6, 4, 75, -34};
+
+uint8_t input_uint8[] = {1, 56, 2, 9, 90, 23, 54, 76,
+			 4, 34, 110, 110, 6, 4, 75, 34};
+uint16_t input_uint16[] = {1, 56, 2, 9, 90, 23, 54, 76,
+			   4, 34, 110, 110, 6, 4, 75, 34};
+uint32_t input_uint32[] = {1, 56, 2, 9, 90, 23, 54, 76,
+			   4, 34, 110, 110, 6, 4, 75, 34};
+
+#define EQUAL(a, b) (a == b)
+
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES)			\
+int									\
+test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t (void)			\
+{									\
+  int i, j;								\
+  int moves = (NUM_TESTS - LANES) + 1;					\
+  TYPE##_t out_l[NUM_TESTS];						\
+  TYPE##_t out_v[NUM_TESTS];						\
+									\
+  /* Calculate linearly.  */						\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      out_l[i] = input_##TYPE[i];					\
+      for (j = 0; j < LANES; j++)					\
+	out_l[i] = input_##TYPE[i + j] CMP_OP out_l[i]  ?		\
+	  input_##TYPE[i + j] : out_l[i];				\
+    }									\
+									\
+  /* Calculate using vector reduction intrinsics.  */			\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      TYPE##x##LANES##_t t1 = vld1##Q##_##SUFFIX (input_##TYPE + i);	\
+      out_v[i] = v##MAXMIN##v##Q##_##SUFFIX (t1);			\
+    }									\
+									\
+  /* Compare.  */							\
+  for (i = 0; i < moves; i++)						\
+    {									\
+      if (!EQUAL (out_v[i], out_l[i]))					\
+	return 0;							\
+    }									\
+  return 1;								\
+}
+
+#define BUILD_VARIANTS(TYPE, STYPE, W32, W64)		\
+TEST (max, >, STYPE,  , TYPE, W32)			\
+TEST (max, >, STYPE, q, TYPE, W64)			\
+TEST (min, <, STYPE,  , TYPE, W32)			\
+TEST (min, <, STYPE, q, TYPE, W64)
+
+BUILD_VARIANTS (int8, s8, 8, 16)
+/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "smaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+/* { dg-final { scan-assembler "sminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+BUILD_VARIANTS (uint8, u8, 8, 16)
+/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "umaxv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+/* { dg-final { scan-assembler "uminv\\tb\[0-9\]+, v\[0-9\]+\.16b" } } */
+BUILD_VARIANTS (int16, s16, 4, 8)
+/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "smaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "sminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+BUILD_VARIANTS (uint16, u16, 4, 8)
+/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "umaxv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "uminv\\th\[0-9\]+, v\[0-9\]+\.8h" } } */
+BUILD_VARIANTS (int32, s32, 2, 4)
+/* { dg-final { scan-assembler "smaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "sminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "smaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "sminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+BUILD_VARIANTS (uint32, u32, 2, 4)
+/* { dg-final { scan-assembler "umaxp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "uminp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "umaxv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "uminv\\ts\[0-9\]+, v\[0-9\]+\.4s" } } */
+
+#undef TEST
+#define TEST(MAXMIN, CMP_OP, SUFFIX, Q, TYPE, LANES)		\
+{								\
+  if (!test_v##MAXMIN##v##SUFFIX##_##TYPE##x##LANES##_t ())	\
+    abort ();							\
+}
+
+int
+main (int argc, char **argv)
+{
+  BUILD_VARIANTS (int8, s8, 8, 16)
+  BUILD_VARIANTS (uint8, u8, 8, 16)
+  BUILD_VARIANTS (int16, s16, 4, 8)
+  BUILD_VARIANTS (uint16, u16, 4, 8)
+  BUILD_VARIANTS (int32, s32, 2, 4)
+  BUILD_VARIANTS (uint32, u32, 2, 4)
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c
new file mode 100644
index 000000000..aa3fd9b40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect-vrnd.c
@@ -0,0 +1,117 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+extern float fabsf (float);
+extern double fabs (double);
+
+extern double trunc (double);
+extern double round (double);
+extern double nearbyint (double);
+extern double floor (double);
+extern double ceil (double);
+extern double rint (double);
+
+extern float truncf (float);
+extern float roundf (float);
+extern float nearbyintf (float);
+extern float floorf (float);
+extern float ceilf (float);
+extern float rintf (float);
+
+#define NUM_TESTS 8
+#define DELTA 0.000001
+
+float input_f32[] = {0.1f, -0.1f, 0.4f, 10.3f,
+		     200.0f, -800.0f, -13.0f, -0.5f};
+double input_f64[] = {0.1, -0.1, 0.4, 10.3,
+		      200.0, -800.0, -13.0, -0.5};
+
+#define TEST(SUFFIX, Q, WIDTH, LANES, C_FN, F)		     		\
+int									\
+test_vrnd##SUFFIX##_float##WIDTH##x##LANES##_t (void)			\
+{									\
+  int ret = 1;								\
+  int i = 0;								\
+  int nlanes = LANES;							\
+  float##WIDTH##_t expected_out[NUM_TESTS];				\
+  float##WIDTH##_t actual_out[NUM_TESTS];				\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    {									\
+      expected_out[i] = C_FN##F (input_f##WIDTH[i]);			\
+      /* Don't vectorize this.  */					\
+      asm volatile ("" : : : "memory");					\
+    }									\
+									\
+  /* Prevent the compiler from noticing these two loops do the same	\
+     thing and optimizing away the comparison.  */			\
+  asm volatile ("" : : : "memory");					\
+									\
+  for (i = 0; i < NUM_TESTS; i+=nlanes)					\
+    {									\
+      float##WIDTH##x##LANES##_t out =					\
+	vrnd##SUFFIX##Q##_f##WIDTH					\
+		(vld1##Q##_f##WIDTH (input_f##WIDTH + i));		\
+      vst1##Q##_f##WIDTH (actual_out + i, out);				\
+    }									\
+									\
+  for (i = 0; i < NUM_TESTS; i++)					\
+    ret &= fabs##F (expected_out[i] - actual_out[i]) < DELTA;		\
+									\
+  return ret;								\
+}									\
+
+
+#define BUILD_VARIANTS(SUFFIX, C_FN)	\
+TEST (SUFFIX,  , 32, 2, C_FN, f)	\
+TEST (SUFFIX, q, 32, 4, C_FN, f)	\
+TEST (SUFFIX, q, 64, 2, C_FN,  )	\
+
+BUILD_VARIANTS ( , trunc)
+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frintz\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (a, round)
+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frinta\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (i, nearbyint)
+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frinti\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (m, floor)
+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frintm\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (p, ceil)
+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frintp\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+BUILD_VARIANTS (x, rint)
+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "frintx\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */
+
+#undef TEST
+#define TEST(SUFFIX, Q, WIDTH, LANES, C_FN, F)			\
+{								\
+  if (!test_vrnd##SUFFIX##_float##WIDTH##x##LANES##_t ())	\
+    abort ();							\
+}
+
+int
+main (int argc, char **argv)
+{
+  BUILD_VARIANTS ( , trunc)
+  BUILD_VARIANTS (a, round)
+  BUILD_VARIANTS (i, nearbyint)
+  BUILD_VARIANTS (m, floor)
+  BUILD_VARIANTS (p, ceil)
+  BUILD_VARIANTS (x, rint)
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.c
new file mode 100644
index 000000000..ff70cae43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.c
@@ -0,0 +1,97 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "vect.x"
+
+extern void abort (void);
+
+void set_vector (int *a, int n)
+{
+  int i;
+  for (i=0; i<16; i++)
+    a[i] = n;
+}
+
+void check_vector (pRINT c, pRINT result, char *str)
+{
+  int i;
+  for (i=0; i<16 ; i++)
+    if (c[i] != result[i])
+      abort ();
+}
+
+#define TEST(func, sign) set_vector (sign##c, 0); \
+		         func (sign##a, sign##b, sign##c);    \
+		         check_vector (sign##c, func##_vector, #func);
+
+
+#define TESTV(func, sign)  \
+                    if (func (sign##a) != func##_value) \
+		      abort ();
+
+#define TESTVLL(func, sign)  \
+                    if (func (ll##sign##a) != func##_value) \
+		      abort ();
+		          
+int main (void)
+{
+  int sa[16];
+  int sb[16];
+  int sc[16];
+  unsigned int ua[16];
+  unsigned int ub[16];
+  unsigned int uc[16];
+  long long llsa[16];
+  unsigned long long llua[16];
+  int i;
+
+  /* Table of standard values to compare against.  */
+  unsigned int test_bic_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  unsigned int test_orn_vector[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1};
+  int mla_vector[] = {0, 1, 4, 9, 16, 25, 36, 49, 64, 81, 100, 121, 144, 169, 196, 225};
+  int mls_vector[] = {0, -1, -4, -9, -16, -25, -36, -49, -64, -81, -100, -121, -144, -169, -196, -225};
+  int smax_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15};
+  int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15};
+  unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+  unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+  int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int reduce_smax_value = 0;
+  int reduce_smin_value = -15;
+  unsigned int reduce_umax_value = 15;
+  unsigned int reduce_umin_value = 0;
+  unsigned int reduce_add_u32_value = 120;
+  int reduce_add_s32_value = -120;
+  long long reduce_add_s64_value = -120;
+  unsigned long long reduce_add_u64_value = 120;
+
+  /* Set up input vectors.  */
+  for (i=0; i < 16; i++)
+    {
+      sa[i] = sb[i] = -i;
+      llsa[i] = (long long)-i;
+      ua[i] = ub[i] = i;
+      llua[i] = (unsigned long long)i;
+    }
+
+  TEST (test_bic, s);
+  TEST (test_orn, s);
+  TEST (mla, s);
+  TEST (mls, s);
+  TEST (smax, s);
+  TEST (smin, s);
+  TEST (umax, u);
+  TEST (umin, u);
+  TEST (sabd, s);
+  TEST (saba, s);
+  TESTV (reduce_smax, s);
+  TESTV (reduce_smin, s);
+  TESTV (reduce_umax, u);
+  TESTV (reduce_umin, u);
+  TESTV (reduce_add_u32, u);
+  TESTV (reduce_add_s32, s);
+  TESTVLL (reduce_add_u64, u);
+  TESTVLL (reduce_add_s64, s);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.x b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.x
new file mode 100644
index 000000000..c0f79b50b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect.x
@@ -0,0 +1,154 @@
+typedef int *__restrict__ pRINT;
+typedef unsigned int *__restrict__ pRUINT;
+typedef long long *__restrict__ pRINT64;
+typedef unsigned long long *__restrict__ pRUINT64;
+
+void test_orn (pRUINT a, pRUINT b, pRUINT c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+     c[i] = a[i] | (~b[i]);
+}
+
+void test_bic (pRUINT a, pRUINT b, pRUINT c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+     c[i] = a[i] & (~b[i]);
+}
+
+void mla (pRINT a, pRINT b, pRINT c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] += a[i] * b[i]; 
+}
+
+void mls (pRINT a, pRINT b, pRINT c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] -= a[i] * b[i];
+}
+
+void smax (pRINT a, pRINT b, pRINT c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] = (a[i] > b[i] ? a[i] : b[i]);
+}
+
+void smin (pRINT a, pRINT b, pRINT c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] = (a[i] < b[i] ? a[i] : b[i]);
+}
+
+void umax (pRUINT a, pRUINT b, pRUINT c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] = (a[i] > b[i] ? a[i] : b[i]);
+}
+
+void umin (pRUINT a, pRUINT b, pRUINT c)
+{
+  int i;
+  for (i=0;i<16;i++)
+    c[i] = (a[i] < b[i] ? a[i] : b[i]);
+}
+
+unsigned int reduce_umax (pRUINT a)
+{
+  int i;
+  unsigned int s = a[0];
+  for (i = 1; i < 16; i++)
+    s = (s > a[i] ? s : a[i]);
+
+  return s;
+}
+
+unsigned int reduce_umin (pRUINT a)
+{
+  int i;
+  unsigned int s = a[0];
+  for (i = 1; i < 16; i++)
+    s = (s < a[i] ? s : a[i]);
+
+  return s;
+}
+
+int reduce_smax (pRINT a)
+{
+  int i;
+  int s = a[0];
+  for (i = 1; i < 16; i++)
+    s = (s > a[i] ? s : a[i]);
+
+  return s;
+}
+
+int reduce_smin (pRINT a)
+{
+  int i;
+  int s = a[0];
+  for (i = 1; i < 16; i++)
+    s = (s < a[i] ? s : a[i]);
+
+  return s;
+}
+
+unsigned int reduce_add_u32 (pRINT a)
+{
+  int i;
+  unsigned int s = 0;
+  for (i = 0; i < 16; i++)
+    s += a[i];
+
+  return s;
+}
+
+int reduce_add_s32 (pRINT a)
+{
+  int i;
+  int s = 0;
+  for (i = 0; i < 16; i++)
+    s += a[i];
+
+  return s;
+}
+
+unsigned long long reduce_add_u64 (pRUINT64 a)
+{
+  int i;
+  unsigned long long s = 0;
+  for (i = 0; i < 16; i++)
+    s += a[i];
+
+  return s;
+}
+
+long long reduce_add_s64 (pRINT64 a)
+{
+  int i;
+  long long s = 0;
+  for (i = 0; i < 16; i++)
+    s += a[i];
+
+  return s;
+}
+
+void sabd (pRINT a, pRINT b, pRINT c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    c[i] = abs (a[i] - b[i]);
+}
+
+void saba (pRINT a, pRINT b, pRINT c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    c[i] += abs (a[i] - b[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c
new file mode 100644
index 000000000..ecbd8a8af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_saddl_1.c
@@ -0,0 +1,315 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model" } */
+
+typedef signed char S8_t;
+typedef signed short S16_t;
+typedef signed int S32_t;
+typedef signed long long S64_t;
+
+typedef signed char *__restrict__ pS8_t;
+typedef signed short *__restrict__ pS16_t;
+typedef signed int *__restrict__ pS32_t;
+typedef signed long long *__restrict__ pS64_t;
+
+typedef unsigned char U8_t;
+typedef unsigned short U16_t;
+typedef unsigned int U32_t;
+typedef unsigned long long U64_t;
+
+typedef unsigned char *__restrict__ pU8_t;
+typedef unsigned short *__restrict__ pU16_t;
+typedef unsigned int *__restrict__ pU32_t;
+typedef unsigned long long *__restrict__ pU64_t;
+
+extern void abort ();
+
+void
+test_addl_S64_S32_4 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = (S64_t) b[i] + (S64_t) c[i];
+}
+/* "saddl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "saddl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+/* a = -b + c => a = c - b */
+void
+test_addl_S64_S32_4_neg0 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = -(S64_t) b[i] + (S64_t) c[i];
+}
+/* "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+/* a = b + -c => a = b - c */
+void
+test_addl_S64_S32_4_neg1 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = (S64_t) b[i] + -(S64_t) c[i];
+}
+/* "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+void
+test_addl_S32_S16_8 (pS32_t a, pS16_t b, pS16_t c)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    a[i] = (S32_t) b[i] + (S32_t) c[i];
+}
+/* { dg-final { scan-assembler "saddl\tv\[0-9\]+\.4s,\ v\[0-9\]+\.4h,\ v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "saddl2\tv\[0-9\]+\.4s,\ v\[0-9\]+\.8h,\ v\[0-9\]+\.8h" } } */
+
+void
+test_addl_S16_S8_16 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = (S16_t) b[i] + (S16_t) c[i];
+}
+/* { dg-final { scan-assembler "saddl\tv\[0-9\]+\.8h,\ v\[0-9\]+\.8b,\ v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "saddl2\tv\[0-9\]+\.8h,\ v\[0-9\]+\.16b,\ v\[0-9\]+\.16b" } } */
+
+void
+test_addl_U64_U32_4 (pU64_t a, pU32_t b, pU32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = (U64_t) b[i] + (U64_t) c[i];
+}
+/* { dg-final { scan-assembler "uaddl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "uaddl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" } } */
+
+void
+test_addl_U32_U16_8 (pU32_t a, pU16_t b, pU16_t c)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    a[i] = (U32_t) b[i] + (U32_t) c[i];
+}
+/* { dg-final { scan-assembler "uaddl\tv\[0-9\]+\.4s,\ v\[0-9\]+\.4h,\ v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "uaddl2\tv\[0-9\]+\.4s,\ v\[0-9\]+\.8h,\ v\[0-9\]+\.8h" } } */
+
+void
+test_addl_U16_U8_16 (pU16_t a, pU8_t b, pU8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = (U16_t) b[i] + (U16_t) c[i];
+}
+/* { dg-final { scan-assembler "uaddl\tv\[0-9\]+\.8h,\ v\[0-9\]+\.8b,\ v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "uaddl2\tv\[0-9\]+\.8h,\ v\[0-9\]+\.16b,\ v\[0-9\]+\.16b" } } */
+
+void
+test_subl_S64_S32_4 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = (S64_t) b[i] - (S64_t) c[i];
+}
+/* "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+/* a = b - -c => a = b + c */
+void
+test_subl_S64_S32_4_neg0 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = (S64_t) b[i] - -(S64_t) c[i];
+}
+/* { dg-final { scan-assembler-times "saddl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 2 } } */
+/* { dg-final { scan-assembler-times "saddl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" 2 } } */
+
+/* a = -b - -c => a = c - b */
+void
+test_subl_S64_S32_4_neg1 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = -(S64_t) b[i] - -(S64_t) c[i];
+}
+/* "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" */
+/* "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" */
+
+/* a = -(b - c) => a = c - b */
+void
+test_subl_S64_S32_4_neg2 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = -((S64_t) b[i] - (S64_t) c[i]);
+}
+/* { dg-final { scan-assembler-times "ssubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" 5 } } */
+/* { dg-final { scan-assembler-times "ssubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" 5 } } */
+
+void
+test_subl_S32_S16_8 (pS32_t a, pS16_t b, pS16_t c)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    a[i] = (S32_t) b[i] - (S32_t) c[i];
+}
+/* { dg-final { scan-assembler "ssubl\tv\[0-9\]+\.4s,\ v\[0-9\]+\.4h,\ v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "ssubl2\tv\[0-9\]+\.4s,\ v\[0-9\]+\.8h,\ v\[0-9\]+\.8h" } } */
+
+void
+test_subl_S16_S8_16 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = (S16_t) b[i] - (S16_t) c[i];
+}
+/* { dg-final { scan-assembler "ssubl\tv\[0-9\]+\.8h,\ v\[0-9\]+\.8b,\ v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "ssubl2\tv\[0-9\]+\.8h,\ v\[0-9\]+\.16b,\ v\[0-9\]+\.16b" } } */
+
+void
+test_subl_U64_U32_4 (pU64_t a, pU32_t b, pU32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] = (U64_t) b[i] - (U64_t) c[i];
+}
+/* { dg-final { scan-assembler "usubl\tv\[0-9\]+\.2d,\ v\[0-9\]+\.2s,\ v\[0-9\]+\.2s" } } */
+/* { dg-final { scan-assembler "usubl2\tv\[0-9\]+\.2d,\ v\[0-9\]+\.4s,\ v\[0-9\]+\.4s" } } */
+
+void
+test_subl_U32_U16_8 (pU32_t a, pU16_t b, pU16_t c)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    a[i] = (U32_t) b[i] - (U32_t) c[i];
+}
+/* { dg-final { scan-assembler "usubl\tv\[0-9\]+\.4s,\ v\[0-9\]+\.4h,\ v\[0-9\]+\.4h" } } */
+/* { dg-final { scan-assembler "usubl2\tv\[0-9\]+\.4s,\ v\[0-9\]+\.8h,\ v\[0-9\]+\.8h" } } */
+
+void
+test_subl_U16_U8_16 (pU16_t a, pU8_t b, pU8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = (U16_t) b[i] - (U16_t) c[i];
+}
+/* { dg-final { scan-assembler "usubl\tv\[0-9\]+\.8h,\ v\[0-9\]+\.8b,\ v\[0-9\]+\.8b" } } */
+/* { dg-final { scan-assembler "usubl2\tv\[0-9\]+\.8h,\ v\[0-9\]+\.16b,\ v\[0-9\]+\.16b" } } */
+
+/* input values */
+
+S64_t S64_ta[4];
+S32_t S32_tb[4] = { 0, 1, 2, 3 };
+S32_t S32_tc[4] = { 2, 2, -2, -2 };
+
+S32_t S32_ta[8];
+S16_t S16_tb[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+S16_t S16_tc[8] = { 2, 2, -2, -2, 2, 2, -2, -2 };
+
+S16_t S16_ta[16];
+S8_t S8_tb[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+S8_t S8_tc[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
+
+/* expected output */
+
+S64_t addl_rS64[] = { 2, 3, 0, 1 };
+S64_t neg_r[] = { 2, 1, -4, -5 };
+S32_t addl_rS32[] = { 2, 3, 0, 1, 6, 7, 4, 5 };
+S16_t addl_rS16[] = { 2, 3, 0, 1, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13 };
+S64_t subl_rS64[] = { -2, -1, 4, 5 };
+S32_t subl_rS32[] = { -2, -1, 4, 5, 2, 3, 8, 9 };
+S16_t subl_rS16[] =
+  { -2, -1, 4, 5, 2, 3, 8, 9, 6, 7, 12, 13, 10, 11, 16, 17 };
+U64_t addl_rU64[] = { 2, 3, 0x100000000, 0x100000001 };
+U32_t addl_rU32[] = { 2, 3, 0x10000, 0x10001, 6, 7, 0x10004, 0x10005 };
+U16_t addl_rU16[] =
+{
+  0x0002, 0x0003, 0x0100, 0x0101, 0x0006, 0x0007, 0x0104, 0x0105,
+  0x000a, 0x000b, 0x0108, 0x0109, 0x000e, 0x000f, 0x010c, 0x010d
+};
+U64_t subl_rU64[] =
+{
+  0xfffffffffffffffe, 0xffffffffffffffff,
+  0xffffffff00000004, 0xffffffff00000005
+};
+U32_t subl_rU32[] =
+{
+  0xfffffffe, 0xffffffff, 0xffff0004, 0xffff0005,
+  0x00000002, 0x00000003, 0xffff0008, 0xffff0009
+};
+U16_t subl_rU16[] =
+{
+  0xfffe, 0xffff, 0xff04, 0xff05, 0x0002, 0x0003, 0xff08, 0xff09,
+  0x0006, 0x0007, 0xff0c, 0xff0d, 0x000a, 0x000b, 0xff10, 0xff11
+};
+
+#define CHECK(T,N,AS,US)                                 \
+do                                                       \
+  {                                                      \
+    for (i = 0; i < N; i++)                              \
+      if ((US##T##_t)S##T##_ta[i] != AS##_##r##US##T[i]) \
+        abort();                                         \
+  }                                                      \
+while (0)
+
+#define NCHECK(RES)                           \
+do                                            \
+  {                                           \
+    for (i = 0; i < 4; i++)                   \
+      if (S64_ta[i] != RES[i])                \
+        abort ();                             \
+  }                                           \
+while (0)
+
+#define SCHECK(T,N,AS) CHECK(T,N,AS,S)
+#define UCHECK(T,N,AS) CHECK(T,N,AS,U)
+
+int
+main ()
+{
+  int i;
+
+  test_addl_S64_S32_4 (S64_ta, S32_tb, S32_tc);
+  SCHECK (64, 4, addl);
+  test_addl_S32_S16_8 (S32_ta, S16_tb, S16_tc);
+  SCHECK (32, 8, addl);
+  test_addl_S16_S8_16 (S16_ta, S8_tb, S8_tc);
+  SCHECK (16, 16, addl);
+  test_subl_S64_S32_4 (S64_ta, S32_tb, S32_tc);
+  SCHECK (64, 4, subl);
+  test_subl_S32_S16_8 (S32_ta, S16_tb, S16_tc);
+  SCHECK (32, 8, subl);
+  test_subl_S16_S8_16 (S16_ta, S8_tb, S8_tc);
+  SCHECK (16, 16, subl);
+
+  test_addl_U64_U32_4 (S64_ta, S32_tb, S32_tc);
+  UCHECK (64, 4, addl);
+  test_addl_U32_U16_8 (S32_ta, S16_tb, S16_tc);
+  UCHECK (32, 8, addl);
+  test_addl_U16_U8_16 (S16_ta, S8_tb, S8_tc);
+  UCHECK (16, 16, addl);
+  test_subl_U64_U32_4 (S64_ta, S32_tb, S32_tc);
+  UCHECK (64, 4, subl);
+  test_subl_U32_U16_8 (S32_ta, S16_tb, S16_tc);
+  UCHECK (32, 8, subl);
+  test_subl_U16_U8_16 (S16_ta, S8_tb, S8_tc);
+  UCHECK (16, 16, subl);
+
+  test_addl_S64_S32_4_neg0 (S64_ta, S32_tb, S32_tc);
+  NCHECK (neg_r);
+  test_addl_S64_S32_4_neg1 (S64_ta, S32_tb, S32_tc);
+  NCHECK (subl_rS64);
+  test_subl_S64_S32_4_neg0 (S64_ta, S32_tb, S32_tc);
+  NCHECK (addl_rS64);
+  test_subl_S64_S32_4_neg1 (S64_ta, S32_tb, S32_tc);
+  NCHECK (neg_r);
+  test_subl_S64_S32_4_neg2 (S64_ta, S32_tb, S32_tc);
+  NCHECK (neg_r);
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
new file mode 100644
index 000000000..b70be4ccb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
@@ -0,0 +1,325 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-inline -save-temps -fno-vect-cost-model" } */
+
+typedef signed char S8_t;
+typedef signed short S16_t;
+typedef signed int S32_t;
+typedef signed long long S64_t;
+typedef signed char *__restrict__ pS8_t;
+typedef signed short *__restrict__ pS16_t;
+typedef signed int *__restrict__ pS32_t;
+typedef signed long long *__restrict__ pS64_t;
+typedef unsigned char U8_t;
+typedef unsigned short U16_t;
+typedef unsigned int U32_t;
+typedef unsigned long long U64_t;
+typedef unsigned char *__restrict__ pU8_t;
+typedef unsigned short *__restrict__ pU16_t;
+typedef unsigned int *__restrict__ pU32_t;
+typedef unsigned long long *__restrict__ pU64_t;
+
+extern void abort ();
+
+void
+test_addS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] += (S64_t) b[i] * (S64_t) c[i];
+}
+
+/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.2d" } } */
+
+void
+test_addS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    a[i] += (S32_t) b[i] * (S32_t) c[i];
+}
+
+/* { dg-final { scan-assembler "smlal\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "smlal2\tv\[0-9\]+\.4s" } } */
+
+void
+test_addS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] += (S16_t) b[i] * (S16_t) c[i];
+}
+
+void
+test_addS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] += (S16_t) -b[i] * (S16_t) -c[i];
+}
+
+void
+test_addS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] -= (S16_t) b[i] * (S16_t) -c[i];
+}
+
+void
+test_addS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] -= (S16_t) -b[i] * (S16_t) c[i];
+}
+
+/* { dg-final { scan-assembler-times "smlal\tv\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "smlal2\tv\[0-9\]+\.8h" 4 } } */
+
+void
+test_subS64_tS32_t4 (pS64_t a, pS32_t b, pS32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] -= (S64_t) b[i] * (S64_t) c[i];
+}
+
+/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.2d" } } */
+
+void
+test_subS32_tS16_t8 (pS32_t a, pS16_t b, pS16_t c)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    a[i] -= (S32_t) b[i] * (S32_t) c[i];
+}
+
+/* { dg-final { scan-assembler "smlsl\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "smlsl2\tv\[0-9\]+\.4s" } } */
+
+void
+test_subS16_tS8_t16 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] -= (S16_t) b[i] * (S16_t) c[i];
+}
+
+void
+test_subS16_tS8_t16_neg0 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] += (S16_t) -b[i] * (S16_t) c[i];
+}
+
+void
+test_subS16_tS8_t16_neg1 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] += (S16_t) b[i] * (S16_t) -c[i];
+}
+
+void
+test_subS16_tS8_t16_neg2 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] += -((S16_t) b[i] * (S16_t) c[i]);
+}
+
+void
+test_subS16_tS8_t16_neg3 (pS16_t a, pS8_t b, pS8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] -= (S16_t) -b[i] * (S16_t) -c[i];
+}
+
+/* { dg-final { scan-assembler-times "smlsl\tv\[0-9\]+\.8h" 5 } } */
+/* { dg-final { scan-assembler-times "smlsl2\tv\[0-9\]+\.8h" 5 } } */
+
+void
+test_addU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] += (U64_t) b[i] * (U64_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.2d" } } */
+
+void
+test_addU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    a[i] += (U32_t) b[i] * (U32_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.4s" } } */
+
+void
+test_addU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] += (U16_t) b[i] * (U16_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlal\tv\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "umlal2\tv\[0-9\]+\.8h" } } */
+
+void
+test_subU64_tU32_t4 (pU64_t a, pU32_t b, pU32_t c)
+{
+  int i;
+  for (i = 0; i < 4; i++)
+    a[i] -= (U64_t) b[i] * (U64_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.2d" } } */
+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.2d" } } */
+
+void
+test_subU32_tU16_t8 (pU32_t a, pU16_t b, pU16_t c)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    a[i] -= (U32_t) b[i] * (U32_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.4s" } } */
+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.4s" } } */
+
+void
+test_subU16_tU8_t16 (pU16_t a, pU8_t b, pU8_t c)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] -= (U16_t) b[i] * (U16_t) c[i];
+}
+
+/* { dg-final { scan-assembler "umlsl\tv\[0-9\]+\.8h" } } */
+/* { dg-final { scan-assembler "umlsl2\tv\[0-9\]+\.8h" } } */
+
+
+S64_t add_rS64[4] = { 6, 7, -4, -3 };
+S32_t add_rS32[8] = { 6, 7, -4, -3, 10, 11, 0, 1 };
+S16_t add_rS16[16] =
+ { 6, 7, -4, -3, 10, 11, 0, 1, 14, 15, 4, 5, 18, 19, 8, 9 };
+
+S64_t sub_rS64[4] = { 0, 1, 2, 3 };
+S32_t sub_rS32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+S16_t sub_rS16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+
+U64_t add_rU64[4] = { 0x6, 0x7, 0x2fffffffc, 0x2fffffffd };
+
+U32_t add_rU32[8] =
+{
+  0x6, 0x7, 0x2fffc, 0x2fffd,
+  0xa, 0xb, 0x30000, 0x30001
+};
+
+U16_t add_rU16[16] =
+{
+  0x6, 0x7, 0x2fc, 0x2fd, 0xa, 0xb, 0x300, 0x301,
+  0xe, 0xf, 0x304, 0x305, 0x12, 0x13, 0x308, 0x309
+};
+
+U64_t sub_rU64[4] = { 0, 1, 2, 3 };
+U32_t sub_rU32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+U16_t sub_rU16[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+
+S8_t neg_r[16] = { -6, -5, 8, 9, -2, -1, 12, 13, 2, 3, 16, 17, 6, 7, 20, 21 };
+
+S64_t S64_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+S32_t S32_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
+S32_t S32_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
+
+S32_t S32_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+S16_t S16_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
+S16_t S16_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
+
+S16_t S16_ta[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+S8_t S8_tb[16] = { 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2, 2, 2, -2, -2 };
+S8_t S8_tc[16] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
+
+
+#define CHECK(T,N,AS,US)                      \
+do                                            \
+  {                                           \
+    for (i = 0; i < N; i++)                   \
+      if (S##T##_ta[i] != AS##_r##US##T[i])   \
+        abort ();                             \
+  }                                           \
+while (0)
+
+#define SCHECK(T,N,AS) CHECK(T,N,AS,S)
+#define UCHECK(T,N,AS) CHECK(T,N,AS,U)
+
+#define NCHECK(RES)                           \
+do                                            \
+  {                                           \
+    for (i = 0; i < 16; i++)                  \
+      if (S16_ta[i] != RES[i])                \
+        abort ();                             \
+  }                                           \
+while (0)
+
+
+int
+main ()
+{
+  int i;
+
+  test_addS64_tS32_t4 (S64_ta, S32_tb, S32_tc);
+  SCHECK (64, 4, add);
+  test_addS32_tS16_t8 (S32_ta, S16_tb, S16_tc);
+  SCHECK (32, 8, add);
+  test_addS16_tS8_t16 (S16_ta, S8_tb, S8_tc);
+  SCHECK (16, 16, add);
+  test_subS64_tS32_t4 (S64_ta, S32_tb, S32_tc);
+  SCHECK (64, 4, sub);
+  test_subS32_tS16_t8 (S32_ta, S16_tb, S16_tc);
+  SCHECK (32, 8, sub);
+  test_subS16_tS8_t16 (S16_ta, S8_tb, S8_tc);
+  SCHECK (16, 16, sub);
+
+  test_addU64_tU32_t4 (S64_ta, S32_tb, S32_tc);
+  UCHECK (64, 4, add);
+  test_addU32_tU16_t8 (S32_ta, S16_tb, S16_tc);
+  UCHECK (32, 8, add);
+  test_addU16_tU8_t16 (S16_ta, S8_tb, S8_tc);
+  UCHECK (16, 16, add);
+  test_subU64_tU32_t4 (S64_ta, S32_tb, S32_tc);
+  UCHECK (64, 4, sub);
+  test_subU32_tU16_t8 (S32_ta, S16_tb, S16_tc);
+  UCHECK (32, 8, sub);
+  test_subU16_tU8_t16 (S16_ta, S8_tb, S8_tc);
+  UCHECK (16, 16, sub);
+
+  test_addS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc);
+  NCHECK (add_rS16);
+  test_subS16_tS8_t16_neg0 (S16_ta, S8_tb, S8_tc);
+  NCHECK (sub_rS16);
+  test_addS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc);
+  NCHECK (add_rS16);
+  test_subS16_tS8_t16_neg1 (S16_ta, S8_tb, S8_tc);
+  NCHECK (sub_rS16);
+  test_addS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc);
+  NCHECK (add_rS16);
+  test_subS16_tS8_t16_neg2 (S16_ta, S8_tb, S8_tc);
+  NCHECK (sub_rS16);
+  test_subS16_tS8_t16_neg3 (S16_ta, S8_tb, S8_tc);
+  NCHECK (neg_r);
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c
new file mode 100644
index 000000000..affb8a8a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c
@@ -0,0 +1,803 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include "../../../config/aarch64/arm_neon.h"
+
+
+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+float32x2_t
+test_vmax_f32 (float32x2_t __a, float32x2_t __b)
+{
+  return vmax_f32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */
+
+int8x8_t
+test_vmax_s8 (int8x8_t __a, int8x8_t __b)
+{
+  return vmax_s8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */
+
+uint8x8_t
+test_vmax_u8 (uint8x8_t __a, uint8x8_t __b)
+{
+  return vmax_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */
+
+int16x4_t
+test_vmax_s16 (int16x4_t __a, int16x4_t __b)
+{
+  return vmax_s16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */
+
+uint16x4_t
+test_vmax_u16 (uint16x4_t __a, uint16x4_t __b)
+{
+  return vmax_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+int32x2_t
+test_vmax_s32 (int32x2_t __a, int32x2_t __b)
+{
+  return vmax_s32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+uint32x2_t
+test_vmax_u32 (uint32x2_t __a, uint32x2_t __b)
+{
+  return vmax_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+float32x4_t
+test_vmaxq_f32 (float32x4_t __a, float32x4_t __b)
+{
+  return vmaxq_f32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.2d, v\[0-9\].2d, v\[0-9\].2d" 1 } } */
+
+float64x2_t
+test_vmaxq_f64 (float64x2_t __a, float64x2_t __b)
+{
+  return vmaxq_f64(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */
+
+int8x16_t
+test_vmaxq_s8 (int8x16_t __a, int8x16_t __b)
+{
+  return vmaxq_s8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */
+
+uint8x16_t
+test_vmaxq_u8 (uint8x16_t __a, uint8x16_t __b)
+{
+  return vmaxq_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */
+
+int16x8_t
+test_vmaxq_s16 (int16x8_t __a, int16x8_t __b)
+{
+  return vmaxq_s16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */
+
+uint16x8_t
+test_vmaxq_u16 (uint16x8_t __a, uint16x8_t __b)
+{
+  return vmaxq_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+int32x4_t
+test_vmaxq_s32 (int32x4_t __a, int32x4_t __b)
+{
+  return vmaxq_s32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumax\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+uint32x4_t
+test_vmaxq_u32 (uint32x4_t __a, uint32x4_t __b)
+{
+  return vmaxq_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+float32x2_t
+test_vmin_f32 (float32x2_t __a, float32x2_t __b)
+{
+  return vmin_f32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */
+
+int8x8_t
+test_vmin_s8 (int8x8_t __a, int8x8_t __b)
+{
+  return vmin_s8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 1 } } */
+
+uint8x8_t
+test_vmin_u8 (uint8x8_t __a, uint8x8_t __b)
+{
+  return vmin_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */
+
+int16x4_t
+test_vmin_s16 (int16x4_t __a, int16x4_t __b)
+{
+  return vmin_s16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 1 } } */
+
+uint16x4_t
+test_vmin_u16 (uint16x4_t __a, uint16x4_t __b)
+{
+  return vmin_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+int32x2_t
+test_vmin_s32 (int32x2_t __a, int32x2_t __b)
+{
+  return vmin_s32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */
+
+uint32x2_t
+test_vmin_u32 (uint32x2_t __a, uint32x2_t __b)
+{
+  return vmin_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+float32x4_t
+test_vminq_f32 (float32x4_t __a, float32x4_t __b)
+{
+  return vminq_f32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tfmin\\tv\[0-9\]+\.2d, v\[0-9\].2d, v\[0-9\].2d" 1 } } */
+
+float64x2_t
+test_vminq_f64 (float64x2_t __a, float64x2_t __b)
+{
+  return vminq_f64(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */
+
+int8x16_t
+test_vminq_s8 (int8x16_t __a, int8x16_t __b)
+{
+  return vminq_s8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.16b, v\[0-9\].16b, v\[0-9\].16b" 1 } } */
+
+uint8x16_t
+test_vminq_u8 (uint8x16_t __a, uint8x16_t __b)
+{
+  return vminq_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */
+
+int16x8_t
+test_vminq_s16 (int16x8_t __a, int16x8_t __b)
+{
+  return vminq_s16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.8h, v\[0-9\].8h, v\[0-9\].8h" 1 } } */
+
+uint16x8_t
+test_vminq_u16 (uint16x8_t __a, uint16x8_t __b)
+{
+  return vminq_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsmin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+int32x4_t
+test_vminq_s32 (int32x4_t __a, int32x4_t __b)
+{
+  return vminq_s32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tumin\\tv\[0-9\]+\.4s, v\[0-9\].4s, v\[0-9\].4s" 1 } } */
+
+uint32x4_t
+test_vminq_u32 (uint32x4_t __a, uint32x4_t __b)
+{
+  return vminq_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.8b, v\[0-9\].8b, v\[0-9\].8b" 2 } } */
+
+int8x8_t
+test_vpadd_s8 (int8x8_t __a, int8x8_t __b)
+{
+  return vpadd_s8(__a, __b);
+}
+
+uint8x8_t
+test_vpadd_u8 (uint8x8_t __a, uint8x8_t __b)
+{
+  return vpadd_u8(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.4h, v\[0-9\].4h, v\[0-9\].4h" 2 } } */
+
+int16x4_t
+test_vpadd_s16 (int16x4_t __a, int16x4_t __b)
+{
+  return vpadd_s16(__a, __b);
+}
+
+uint16x4_t
+test_vpadd_u16 (uint16x4_t __a, uint16x4_t __b)
+{
+  return vpadd_u16(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\taddp\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 2 } } */
+
+int32x2_t
+test_vpadd_s32 (int32x2_t __a, int32x2_t __b)
+{
+  return vpadd_s32(__a, __b);
+}
+
+uint32x2_t
+test_vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
+{
+  return vpadd_u32(__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+
+int32x4_t
+test_vqdmlal_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+  return vqdmlal_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+
+int32x4_t
+test_vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return vqdmlal_high_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+  return vqdmlal_high_lane_s16 (a, b, c, 3);
+}
+
+int32x4_t
+test_vqdmlal_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+  return vqdmlal_high_laneq_s16 (a, b, c, 6);
+}
+
+int32x4_t
+test_vqdmlal_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
+{
+  return vqdmlal_high_n_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmlal_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+{
+  return vqdmlal_lane_s16 (a, b, c, 3);
+}
+
+int32x4_t
+test_vqdmlal_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t c)
+{
+  return vqdmlal_laneq_s16 (a, b, c, 6);
+}
+
+int32x4_t
+test_vqdmlal_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+{
+  return vqdmlal_n_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+
+int64x2_t
+test_vqdmlal_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return vqdmlal_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+int64x2_t
+test_vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return vqdmlal_high_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return vqdmlal_high_lane_s32 (__a, __b, __c, 1);
+}
+
+int64x2_t
+test_vqdmlal_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return vqdmlal_high_laneq_s32 (__a, __b, __c, 3);
+}
+
+int64x2_t
+test_vqdmlal_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
+{
+  return vqdmlal_high_n_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlal\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmlal_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return vqdmlal_lane_s32 (__a, __b, __c, 1);
+}
+
+int64x2_t
+test_vqdmlal_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c)
+{
+  return vqdmlal_laneq_s32 (__a, __b, __c, 3);
+}
+
+int64x2_t
+test_vqdmlal_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+{
+  return vqdmlal_n_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+
+int32x4_t
+test_vqdmlsl_s16 (int32x4_t __a, int16x4_t __b, int16x4_t __c)
+{
+  return vqdmlsl_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+
+int32x4_t
+test_vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c)
+{
+  return vqdmlsl_high_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+  return vqdmlsl_high_lane_s16 (a, b, c, 3);
+}
+
+int32x4_t
+test_vqdmlsl_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
+{
+  return vqdmlsl_high_laneq_s16 (a, b, c, 6);
+}
+
+int32x4_t
+test_vqdmlsl_high_n_s16 (int32x4_t __a, int16x8_t __b, int16_t __c)
+{
+  return vqdmlsl_high_n_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmlsl_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
+{
+  return vqdmlsl_lane_s16 (a, b, c, 3);
+}
+
+int32x4_t
+test_vqdmlsl_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t c)
+{
+  return vqdmlsl_laneq_s16 (a, b, c, 6);
+}
+
+int32x4_t
+test_vqdmlsl_n_s16 (int32x4_t __a, int16x4_t __b, int16_t __c)
+{
+  return vqdmlsl_n_s16 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+
+int64x2_t
+test_vqdmlsl_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return vqdmlsl_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+int64x2_t
+test_vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return vqdmlsl_high_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return vqdmlsl_high_lane_s32 (__a, __b, __c, 1);
+}
+
+int64x2_t
+test_vqdmlsl_high_laneq_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c)
+{
+  return vqdmlsl_high_laneq_s32 (__a, __b, __c, 3);
+}
+
+int64x2_t
+test_vqdmlsl_high_n_s32 (int64x2_t __a, int32x4_t __b, int32_t __c)
+{
+  return vqdmlsl_high_n_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmlsl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmlsl_lane_s32 (int64x2_t __a, int32x2_t __b, int32x2_t __c)
+{
+  return vqdmlsl_lane_s32 (__a, __b, __c, 1);
+}
+
+int64x2_t
+test_vqdmlsl_laneq_s32 (int64x2_t __a, int32x2_t __b, int32x4_t __c)
+{
+  return vqdmlsl_laneq_s32 (__a, __b, __c, 3);
+}
+
+int64x2_t
+test_vqdmlsl_n_s32 (int64x2_t __a, int32x2_t __b, int32_t __c)
+{
+  return vqdmlsl_n_s32 (__a, __b, __c);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
+
+int32x4_t
+test_vqdmull_s16 (int16x4_t __a, int16x4_t __b)
+{
+  return vqdmull_s16 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+
+int32x4_t
+test_vqdmull_high_s16 (int16x8_t __a, int16x8_t __b)
+{
+  return vqdmull_high_s16 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmull_high_lane_s16 (int16x8_t a, int16x8_t b)
+{
+  return vqdmull_high_lane_s16 (a, b, 3);
+}
+
+int32x4_t
+test_vqdmull_high_laneq_s16 (int16x8_t a, int16x8_t b)
+{
+  return vqdmull_high_laneq_s16 (a, b, 6);
+}
+
+int32x4_t
+test_vqdmull_high_n_s16 (int16x8_t __a, int16_t __b)
+{
+  return vqdmull_high_n_s16 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.h" 3 } } */
+
+int32x4_t
+test_vqdmull_lane_s16 (int16x4_t a, int16x4_t b)
+{
+  return vqdmull_lane_s16 (a, b, 3);
+}
+
+int32x4_t
+test_vqdmull_laneq_s16 (int16x4_t a, int16x8_t b)
+{
+  return vqdmull_laneq_s16 (a, b, 6);
+}
+
+int32x4_t
+test_vqdmull_n_s16 (int16x4_t __a, int16_t __b)
+{
+  return vqdmull_n_s16 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
+
+int64x2_t
+test_vqdmull_s32 (int32x2_t __a, int32x2_t __b)
+{
+  return vqdmull_s32 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+
+int64x2_t
+test_vqdmull_high_s32 (int32x4_t __a, int32x4_t __b)
+{
+  return vqdmull_high_s32 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmull_high_lane_s32 (int32x4_t __a, int32x4_t __b)
+{
+  return vqdmull_high_lane_s32 (__a, __b, 1);
+}
+
+int64x2_t
+test_vqdmull_high_laneq_s32 (int32x4_t __a, int32x4_t __b)
+{
+  return vqdmull_high_laneq_s32 (__a, __b, 3);
+}
+
+int64x2_t
+test_vqdmull_high_n_s32 (int32x4_t __a, int32_t __b)
+{
+  return vqdmull_high_n_s32 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsqdmull\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.s" 3 } } */
+
+int64x2_t
+test_vqdmull_lane_s32 (int32x2_t __a, int32x2_t __b)
+{
+  return vqdmull_lane_s32 (__a, __b, 1);
+}
+
+int64x2_t
+test_vqdmull_laneq_s32 (int32x2_t __a, int32x4_t __b)
+{
+  return vqdmull_laneq_s32 (__a, __b, 1);
+}
+
+int64x2_t
+test_vqdmull_n_s32 (int32x2_t __a, int32_t __b)
+{
+  return vqdmull_n_s32 (__a, __b);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.2d" 1 } } */
+
+int64x2_t
+test_vshll_n_s32 (int32x2_t __a)
+{
+  return vshll_n_s32 (__a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.2d" 1 } } */
+
+uint64x2_t
+test_vshll_n_u32 (uint32x2_t __a)
+{
+  return vshll_n_u32 (__a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.2d" 2 } } */
+
+int64x2_t
+test_vshll_n_s32_2 (int32x2_t __a)
+{
+  return vshll_n_s32 (__a, 32);
+}
+
+uint64x2_t
+test_vshll_n_u32_2 (uint32x2_t __a)
+{
+  return vshll_n_u32 (__a, 32);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.4s" 1 } } */
+
+int32x4_t
+test_vshll_n_s16 (int16x4_t __a)
+{
+  return vshll_n_s16 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.4s" 1 } } */
+
+uint32x4_t
+test_vshll_n_u16 (uint16x4_t __a)
+{
+  return vshll_n_u16 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.4s" 2 } } */
+
+int32x4_t
+test_vshll_n_s16_2 (int16x4_t __a)
+{
+  return vshll_n_s16 (__a, 16);
+}
+
+uint32x4_t
+test_vshll_n_u16_2 (uint16x4_t __a)
+{
+  return vshll_n_u16 (__a, 16);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll\\tv\[0-9\]+\.8h" 1 } } */
+
+int16x8_t
+test_vshll_n_s8 (int8x8_t __a)
+{
+  return vshll_n_s8 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll\\tv\[0-9\]+\.8h" 1 } } */
+
+uint16x8_t
+test_vshll_n_u8 (uint8x8_t __a)
+{
+  return vshll_n_u8 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll\\tv\[0-9\]+\.8h" 2 } } */
+
+int16x8_t
+test_vshll_n_s8_2 (int8x8_t __a)
+{
+  return vshll_n_s8 (__a, 8);
+}
+
+uint16x8_t
+test_vshll_n_u8_2 (uint8x8_t __a)
+{
+  return vshll_n_u8 (__a, 8);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.2d" 1 } } */
+
+int64x2_t
+test_vshll_high_n_s32 (int32x4_t __a)
+{
+  return vshll_high_n_s32 (__a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.2d" 1 } } */
+
+uint64x2_t
+test_vshll_high_n_u32 (uint32x4_t __a)
+{
+  return vshll_high_n_u32 (__a, 9);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.2d" 2 } } */
+
+int64x2_t
+test_vshll_high_n_s32_2 (int32x4_t __a)
+{
+  return vshll_high_n_s32 (__a, 32);
+}
+
+uint64x2_t
+test_vshll_high_n_u32_2 (uint32x4_t __a)
+{
+  return vshll_high_n_u32 (__a, 32);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.4s" 1 } } */
+
+int32x4_t
+test_vshll_high_n_s16 (int16x8_t __a)
+{
+  return vshll_high_n_s16 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.4s" 1 } } */
+
+uint32x4_t
+test_vshll_high_n_u16 (uint16x8_t __a)
+{
+  return vshll_high_n_u16 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.4s" 2 } } */
+
+int32x4_t
+test_vshll_high_n_s16_2 (int16x8_t __a)
+{
+  return vshll_high_n_s16 (__a, 16);
+}
+
+uint32x4_t
+test_vshll_high_n_u16_2 (uint16x8_t __a)
+{
+  return vshll_high_n_u16 (__a, 16);
+}
+
+/* { dg-final { scan-assembler-times "\\tsshll2\\tv\[0-9\]+\.8h" 1 } } */
+
+int16x8_t
+test_vshll_high_n_s8 (int8x16_t __a)
+{
+  return vshll_high_n_s8 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tushll2\\tv\[0-9\]+\.8h" 1 } } */
+
+uint16x8_t
+test_vshll_high_n_u8 (uint8x16_t __a)
+{
+  return vshll_high_n_u8 (__a, 3);
+}
+
+/* { dg-final { scan-assembler-times "\\tshll2\\tv\[0-9\]+\.8h" 2 } } */
+
+int16x8_t
+test_vshll_high_n_s8_2 (int8x16_t __a)
+{
+  return vshll_high_n_s8 (__a, 8);
+}
+
+uint16x8_t
+test_vshll_high_n_u8_2 (uint8x16_t __a)
+{
+  return vshll_high_n_u8 (__a, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vfp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vfp-1.c
new file mode 100644
index 000000000..79c571402
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vfp-1.c
@@ -0,0 +1,109 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern float fabsf (float);
+extern float sqrtf (float);
+extern double fabs (double);
+extern double sqrt (double);
+
+volatile float f1, f2, f3;
+volatile int cond1, cond2;
+
+void test_sf() {
+  /* abssf2 */
+  /* { dg-final { scan-assembler "fabs\ts\[0-9\]*" } } */
+  f1 = fabsf (f1);
+  /* negsf2 */
+  /* { dg-final { scan-assembler "fneg\ts\[0-9\]*" } } */
+  f1 = -f1;
+  /* addsf3 */
+  /* { dg-final { scan-assembler "fadd\ts\[0-9\]*" } } */
+  f1 = f2 + f3;
+  /* subsf3 */
+  /* { dg-final { scan-assembler "fsub\ts\[0-9\]*" } } */
+  f1 = f2 - f3;
+  /* divsf3 */
+  /* { dg-final { scan-assembler "fdiv\ts\[0-9\]*" } } */
+  f1 = f2 / f3;
+  /* mulsf3 */
+  /* { dg-final { scan-assembler "fmul\ts\[0-9\]*" } } */
+  f1 = f2 * f3;
+  /* sqrtsf2 */
+  /* { dg-final { scan-assembler "fsqrt\ts\[0-9\]*" } } */
+  f1 = sqrtf (f1);
+  /* cmpsf */
+  /* { dg-final { scan-assembler "fcmp\ts\[0-9\]*" } } */
+  if (f1 < f2)
+    cond1 = 1;
+  else
+    cond2 = 1;
+}
+
+volatile double d1, d2, d3;
+
+void test_df() {
+  /* absdf2 */
+  /* { dg-final { scan-assembler "fabs\td\[0-9\]*" } } */
+  d1 = fabs (d1);
+  /* negdf2 */
+  /* { dg-final { scan-assembler "fneg\td\[0-9\]*" } } */
+  d1 = -d1;
+  /* adddf3 */
+  /* { dg-final { scan-assembler "fadd\td\[0-9\]*" } } */
+  d1 = d2 + d3;
+  /* subdf3 */
+  /* { dg-final { scan-assembler "fsub\td\[0-9\]*" } } */
+  d1 = d2 - d3;
+  /* divdf3 */
+  /* { dg-final { scan-assembler "fdiv\td\[0-9\]*" } } */
+  d1 = d2 / d3;
+  /* muldf3 */
+  /* { dg-final { scan-assembler "fmul\td\[0-9\]*" } } */
+  d1 = d2 * d3;
+  /* sqrtdf2 */
+  /* { dg-final { scan-assembler "fsqrt\td\[0-9\]*" } } */
+  d1 = sqrt (d1);
+  /* cmpdf */
+  /* { dg-final { scan-assembler "fcmp\td\[0-9\]*" } } */
+  if (d1 < d2)
+    cond1 = 1;
+  else
+    cond2 = 1;
+}
+
+volatile int i1;
+volatile unsigned int u1;
+
+void test_convert () {
+  /* extendsfdf2 */
+  /* { dg-final { scan-assembler "fcvt\td\[0-9\]*" } } */
+  d1 = f1;
+  /* truncdfsf2 */
+  /* { dg-final { scan-assembler "fcvt\ts\[0-9\]*" } } */
+  f1 = d1;
+  /* fixsfsi2 */
+  /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], s\[0-9\]*" } } */
+  i1 = f1;
+  /* fixdfsi2 */
+  /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], d\[0-9\]*" } } */
+  i1 = d1;
+  /* fixunsfsi2 */
+  /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], s\[0-9\]*" } } */
+  u1 = f1;
+  /* fixunsdfsi2 */
+  /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], d\[0-9\]*" } } */
+  u1 = d1;
+  /* floatsisf2 */
+  /* { dg-final { scan-assembler "scvtf\ts\[0-9\]*" } } */
+  f1 = i1;
+  /* floatsidf2 */
+  /* { dg-final { scan-assembler "scvtf\td\[0-9\]*" } } */
+  d1 = i1;
+  /* floatunssisf2 */
+  /* { dg-final { scan-assembler "ucvtf\ts\[0-9\]*" } } */
+  f1 = u1;
+  /* floatunssidf2 */
+  /* { dg-final { scan-assembler "ucvtf\td\[0-9\]*" } } */
+  d1 = u1;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c
new file mode 100644
index 000000000..d1834a264
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vld1-vst1_1.c
@@ -0,0 +1,52 @@
+/* Test vld1 and vst1 maintain consistent indexing.  */
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+#include <arm_neon.h>
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test_vld1_vst1 ()
+{
+  int8x8_t a;
+  int8x8_t b;
+  int i = 0;
+  int8_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+  int8_t d[8];
+  a = vld1_s8 (c);
+  asm volatile ("":::"memory");
+  vst1_s8 (d, a);
+  asm volatile ("":::"memory");
+  for (; i < 8; i++)
+    if (c[i] != d[i])
+      return 1;
+  return 0;
+}
+
+int __attribute__ ((noinline))
+test_vld1q_vst1q ()
+{
+  int16x8_t a;
+  int16x8_t b;
+  int i = 0;
+  int16_t c[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+  int16_t d[8];
+  a = vld1q_s16 (c);
+  asm volatile ("":::"memory");
+  vst1q_s16 (d, a);
+  asm volatile ("":::"memory");
+  for (; i < 8; i++)
+    if (c[i] != d[i])
+      return 1;
+  return 0;
+}
+
+int
+main ()
+{
+  if (test_vld1_vst1 ())
+    abort ();
+  if (test_vld1q_vst1q ())
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c
new file mode 100644
index 000000000..dd3fb8119
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmlsq_laneq.c
@@ -0,0 +1,158 @@
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+
+extern void abort (void);
+
+void
+test1 ()
+{
+  int16x8_t val1, val2, val3;
+  int16x8_t result;
+  uint64_t act, exp;
+
+  val1 = vcombine_s16 (vcreate_s16 (UINT64_C (0xffff9ab680000000)),
+		       vcreate_s16 (UINT64_C (0x00000000ffff0000)));
+  val2 = vcombine_s16 (vcreate_s16 (UINT64_C (0x32b77fffffff7fff)),
+		       vcreate_s16 (UINT64_C (0x0000ffff00007fff)));
+  val3 = vcombine_s16 (vcreate_s16 (UINT64_C (0x7fff00007fff0000)),
+		       vcreate_s16 (UINT64_C (0x80007fff00000000)));
+  result = vmlsq_laneq_s16 (val1, val2, val3, 6);
+
+  act = vgetq_lane_u64 (vreinterpretq_u64_s16 (result), 0);
+  exp = UINT64_C (0xb2b69ab5ffffffff);
+  if (act != exp)
+    abort ();
+
+  act = vgetq_lane_u64 (vreinterpretq_u64_s16 (result), 1);
+  exp = UINT64_C (0x00007fffffffffff);
+  if (act != exp)
+    abort ();
+}
+
+void
+test2 ()
+{
+  int32x4_t val1, val2, val3;
+  int32x4_t result;
+  uint64_t exp, act;
+
+  val1 = vcombine_s32 (vcreate_s32 (UINT64_C (0x00008000f46f7fff)),
+		       vcreate_s32 (UINT64_C (0x7fffffffffff8000)));
+  val2 = vcombine_s32 (vcreate_s32 (UINT64_C (0x7fff7fff0e700000)),
+		       vcreate_s32 (UINT64_C (0xffff000080000000)));
+  val3 = vcombine_s32 (vcreate_s32 (UINT64_C (0x00000000ffff0000)),
+		       vcreate_s32 (UINT64_C (0xd9edea1a8000fb28)));
+  result = vmlsq_laneq_s32 (val1, val2, val3, 3);
+
+  act = vgetq_lane_u64 (vreinterpretq_u64_s32 (result), 0);
+  exp = UINT64_C (0xcefb6a1a1d0f7fff);
+  if (act != exp)
+    abort ();
+
+  act = vgetq_lane_u64 (vreinterpretq_u64_s32 (result), 1);
+  exp = UINT64_C (0x6a19ffffffff8000);
+  if (act != exp)
+    abort ();
+}
+
+void
+test3 ()
+{
+  uint16x8_t val1, val2, val3;
+  uint16x8_t result;
+  uint64_t act, exp;
+
+  val1 = vcombine_u16 (vcreate_u16 (UINT64_C (0x000080008000802a)),
+		       vcreate_u16 (UINT64_C (0x7fffffff00007fff)));
+  val2 = vcombine_u16 (vcreate_u16 (UINT64_C (0x7fffcdf1ffff0000)),
+		       vcreate_u16 (UINT64_C (0xe2550000ffffffff)));
+  val3 = vcombine_u16 (vcreate_u16 (UINT64_C (0x80007fff80000000)),
+		       vcreate_u16 (UINT64_C (0xbe2100007fffffff)));
+
+  result = vmlsq_laneq_u16 (val1, val2, val3, 7);
+
+  act = vgetq_lane_u64 (vreinterpretq_u64_u16 (result), 0);
+  exp = UINT64_C (0x3e2115ef3e21802a);
+  if (act != exp)
+    abort ();
+
+  act = vgetq_lane_u64 (vreinterpretq_u64_u16 (result), 1);
+  exp = UINT64_C (0x3d0affffbe213e20);
+  if (act != exp)
+    abort ();
+}
+
+void
+test4 ()
+{
+  uint32x4_t val1, val2, val3;
+  uint32x4_t result;
+  uint64_t act, exp;
+
+  val1 = vcombine_u32 (vcreate_u32 (UINT64_C (0x3295fe3d7fff7fff)),
+		       vcreate_u32 (UINT64_C (0x7fff00007fff7fff)));
+  val2 = vcombine_u32 (vcreate_u32 (UINT64_C (0xffff7fff7fff8000)),
+		       vcreate_u32 (UINT64_C (0x7fff80008000ffff)));
+  val3 = vcombine_u32 (vcreate_u32 (UINT64_C (0x7fff7fff80008000)),
+		       vcreate_u32 (UINT64_C (0x0000800053ab7fff)));
+
+  result = vmlsq_laneq_u32 (val1, val2, val3, 2);
+
+  act = vgetq_lane_u64 (vreinterpretq_u64_u32 (result), 0);
+  exp = UINT64_C (0x4640fe3cbffeffff);
+  if (act != exp)
+    abort ();
+
+  act = vgetq_lane_u64 (vreinterpretq_u64_u32 (result), 1);
+  exp = UINT64_C (0xbffe8000d3abfffe);
+  if (act != exp)
+    abort ();
+}
+
+void
+test5 ()
+{
+  float32x4_t val1, val2, val3;
+  float32x4_t result;
+  float32_t act;
+
+  val1 = vcombine_f32 (vcreate_f32 (UINT64_C (0x3f49daf03ef3dc73)),
+		       vcreate_f32 (UINT64_C (0x3f5d467a3ef3dc73)));
+  val2 = vcombine_f32 (vcreate_f32 (UINT64_C (0x3d2064c83d10cd28)),
+		       vcreate_f32 (UINT64_C (0x3ea7d1a23d10cd28)));
+  val3 = vcombine_f32 (vcreate_f32 (UINT64_C (0x3f6131993edb1e04)),
+		       vcreate_f32 (UINT64_C (0x3f37f4bf3edb1e04)));
+
+  result = vmlsq_laneq_f32 (val1, val2, val3, 0);
+
+  act = vgetq_lane_f32 (result, 0);
+  if (act != 0.46116194128990173f)
+    abort ();
+
+  act = vgetq_lane_f32 (result, 1);
+  if (act != 0.7717385292053223f)
+    abort ();
+
+  act = vgetq_lane_f32 (result, 2);
+  if (act != 0.46116194128990173f)
+    abort ();
+
+  act = vgetq_lane_f32 (result, 3);
+  if (act != 0.7240825295448303f)
+    abort ();
+}
+
+int
+main (void)
+{
+  test1 ();
+  test2 ();
+  test3 ();
+  test4 ();
+  test5 ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmov_n_1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmov_n_1.c
new file mode 100644
index 000000000..b9d094a04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vmov_n_1.c
@@ -0,0 +1,349 @@
+/* Test vmov_n works correctly.  */
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+
+extern void abort (void);
+
+#define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
+
+#define CONCAT(a, b) a##b
+#define CONCAT1(a, b) CONCAT (a, b)
+#define REG_INFEX64 _
+#define REG_INFEX128 q_
+#define REG_INFEX(reg_len) REG_INFEX##reg_len
+#define POSTFIX_N(reg_len, data_len, data_type)	\
+  CONCAT1 (REG_INFEX (reg_len), n_##data_type##data_len)
+#define LANE_POSTFIX(reg_len, data_len, data_type) \
+  CONCAT1 (REG_INFEX (reg_len),lane_##data_type##data_len)
+
+/* Test values consist of bytes with following hex values.
+   For example:
+   TEST1 for int16_t will be 0xaaaa
+   TEST1 for int32_t will be 0xaaaaaaaa
+   etc.  */
+
+#define TEST1h aa
+#define TEST2h 55
+#define TEST3h ff
+#define TEST4h 00
+#define TEST5h cc
+#define TEST6h 33
+
+#define TESTh_8(x) TEST##x##h
+#define TESTh_16(x) CONCAT1 (TESTh_8 (x), TESTh_8 (x))
+#define TESTh_32(x) CONCAT1 (TESTh_16 (x), TESTh_16 (x))
+#define TESTh_64(x) CONCAT1 (TESTh_32 (x), TESTh_32 (x))
+
+#define TEST_8(x) CONCAT1 (0x, TESTh_8 (x))
+#define TEST_16(x) CONCAT1 (0x, TESTh_16 (x))
+#define TEST_32(x) CONCAT1 (0x, TESTh_32 (x))
+#define TEST_64(x) CONCAT1 (0x, TESTh_64 (x))
+
+#define TEST(test, data_len) \
+  CONCAT1 (TEST, _##data_len) (test)
+
+#define GET_ELEMENT(reg_len, data_len, data_type)		\
+  CONCAT1 (vget, LANE_POSTFIX (reg_len, data_len, data_type))
+
+#define VMOV_INST(reg_len, data_len, data_type)			\
+  CONCAT1 (vmov, POSTFIX_N (reg_len, data_len, data_type))
+
+#define VMOV_OBSCURE_INST(reg_len, data_len, data_type)		\
+  CONCAT1 (VMOV_INST (reg_len, data_len, data_type), _obscure)
+
+#define RUN_TEST(reg_len, data_len, data_type,				\
+		 test, n, a, b, c)					\
+{									\
+  int i;								\
+  INHIB_OPTIMIZATION;							\
+  (a) = TEST (test, data_len);						\
+  INHIB_OPTIMIZATION;							\
+  (b) = VMOV_OBSCURE_INST (reg_len, data_len, data_type) (&(a));	\
+  (c) = TEST (test, data_len);						\
+  for (i = 0; i < n; i++)						\
+    {									\
+      INHIB_OPTIMIZATION;						\
+      a = GET_ELEMENT (reg_len, data_len, data_type) (b, i);		\
+      if ((a) != (c))							\
+	return 1;							\
+    }									\
+}
+
+#define TYPE_f32 float32_t
+#define TYPE_64_f32 float32x2_t
+#define TYPE_128_f32 float32x4_t
+
+#define TYPE_f64 float64_t
+#define TYPE_64_f64 float64x1_t
+#define TYPE_128_f64 float64x2_t
+
+#define TYPE_s8 int8_t
+#define TYPE_64_s8 int8x8_t
+#define TYPE_128_s8 int8x16_t
+
+#define TYPE_s16 int16_t
+#define TYPE_64_s16 int16x4_t
+#define TYPE_128_s16 int16x8_t
+
+#define TYPE_s32 int32_t
+#define TYPE_64_s32 int32x2_t
+#define TYPE_128_s32 int32x4_t
+
+#define TYPE_s64 int64_t
+#define TYPE_64_s64 int64x1_t
+#define TYPE_128_s64 int64x2_t
+
+#define TYPE_u8 uint8_t
+#define TYPE_64_u8 uint8x8_t
+#define TYPE_128_u8 uint8x16_t
+
+#define TYPE_u16 uint16_t
+#define TYPE_64_u16 uint16x4_t
+#define TYPE_128_u16 uint16x8_t
+
+#define TYPE_u32 uint32_t
+#define TYPE_64_u32 uint32x2_t
+#define TYPE_128_u32 uint32x4_t
+
+#define TYPE_u64 uint64_t
+#define TYPE_64_u64 uint64x1_t
+#define TYPE_128_u64 uint64x2_t
+
+#define TYPE_p8 poly8_t
+#define TYPE_64_p8 poly8x8_t
+#define TYPE_128_p8 poly8x16_t
+
+#define TYPE_p16 poly16_t
+#define TYPE_64_p16 poly16x4_t
+#define TYPE_128_p16 poly16x8_t
+
+#define DIV64_8  8
+#define DIV64_16 4
+#define DIV64_32 2
+#define DIV64_64 1
+
+#define DIV128_8  16
+#define DIV128_16 8
+#define DIV128_32 4
+#define DIV128_64 2
+
+#define DIV(reg_len, data_len)			\
+CONCAT1 (CONCAT1 (DIV, reg_len),		\
+	 CONCAT1 (_, data_len))
+
+#define VECTOR_TYPE(reg_len, data_len, data_type)	\
+CONCAT1 (CONCAT1 (CONCAT1 (TYPE_,reg_len),		\
+		  CONCAT1 (_,data_type)),		\
+	 data_len)
+
+#define SIMPLE_TYPE(data_len, data_type)	\
+CONCAT1 (TYPE_,					\
+	 CONCAT1 (data_type,			\
+		  data_len))
+
+#define OBSCURE_FUNC_NAME(reg_len, data_type, data_len)		\
+CONCAT1 (CONCAT1 (vmov,						\
+		  POSTFIX_N (reg_len, data_len, data_type)),	\
+	 _obscure)
+
+#define OBSCURE_FUNC(reg_len, data_len, data_type)	\
+VECTOR_TYPE (reg_len, data_len, data_type)		\
+__attribute__ ((noinline))				\
+OBSCURE_FUNC_NAME (reg_len, data_type, data_len)	\
+ (SIMPLE_TYPE (data_len, data_type) *ap)		\
+{							\
+  SIMPLE_TYPE (data_len, data_type) register a;		\
+  INHIB_OPTIMIZATION;					\
+  a = *ap;						\
+  INHIB_OPTIMIZATION;					\
+  return VMOV_INST (reg_len, data_len, data_type) (a);	\
+}
+
+#define TESTFUNC_NAME(reg_len, data_type, data_len)	\
+CONCAT1 (test_vmov,					\
+	 POSTFIX_N (reg_len, data_len, data_type))
+
+#define TESTFUNC(reg_len, data_len, data_type)	\
+int						\
+TESTFUNC_NAME (reg_len, data_type, data_len) ()	\
+{						\
+  SIMPLE_TYPE (data_len, data_type) a;		\
+  VECTOR_TYPE (reg_len, data_len, data_type) b;	\
+  SIMPLE_TYPE (data_len, data_type) c;		\
+						\
+  RUN_TEST (reg_len, data_len, data_type, 1,	\
+	    DIV (reg_len, data_len), a, b, c);	\
+  RUN_TEST (reg_len, data_len, data_type, 2,	\
+	    DIV (reg_len, data_len), a, b, c);	\
+  RUN_TEST (reg_len, data_len, data_type, 3,	\
+	    DIV (reg_len, data_len), a, b, c);	\
+  RUN_TEST (reg_len, data_len, data_type, 4,	\
+	    DIV (reg_len, data_len), a, b, c);	\
+  RUN_TEST (reg_len, data_len, data_type, 5,	\
+	    DIV (reg_len, data_len), a, b, c);	\
+  RUN_TEST (reg_len, data_len, data_type, 6,	\
+	    DIV (reg_len, data_len), a, b, c);	\
+  return 0;					\
+}
+
+OBSCURE_FUNC (64, 32, f)
+TESTFUNC (64, 32, f)
+/* "dup  Vd.2s, Rn" is less preferable then "dup  Vd.2s, Vn.s[lane]".  */
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 1 } } */
+
+OBSCURE_FUNC (64, 64, f)
+TESTFUNC (64, 64, f)
+/* "fmov  Dd, Rn" is generated instead of "dup  Dd, Rn".
+   No assembley scan included.  */
+
+OBSCURE_FUNC (64, 8, p)
+TESTFUNC (64, 8, p)
+/* Generates "dup  Vd.8b, Rn". Scan found near s8 version.  */
+
+OBSCURE_FUNC (64, 16, p)
+TESTFUNC (64, 16, p)
+/* Generates "dup  Vd.4h, Rn". Scan found near s16 version.  */
+
+OBSCURE_FUNC (64, 8, s)
+TESTFUNC (64, 8, s)
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8b, w\[0-9\]+" 3 } } */
+
+OBSCURE_FUNC (64, 16, s)
+TESTFUNC (64, 16, s)
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4h, w\[0-9\]+" 3 } } */
+
+OBSCURE_FUNC (64, 32, s)
+TESTFUNC (64, 32, s)
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.2s, w\[0-9\]+" 2 } } */
+
+OBSCURE_FUNC (64, 64, s)
+TESTFUNC (64, 64, s)
+/* "fmov  Dd, Rn" is generated instead of "dup  Dd, Rn".
+   No assembley scan included.  */
+
+OBSCURE_FUNC (64, 8, u)
+TESTFUNC (64, 8, u)
+/* Generates "dup  Vd.8b, Rn". Scan found near s8 version.  */
+
+OBSCURE_FUNC (64, 16, u)
+TESTFUNC (64, 16, u)
+/* Generates "dup  Vd.4h, Rn". Scan found near s16 version.  */
+
+OBSCURE_FUNC (64, 32, u)
+TESTFUNC (64, 32, u)
+/* Generates "dup  Vd.2s, Rn". Scan found near s32 version.  */
+
+OBSCURE_FUNC (64, 64, u)
+TESTFUNC (64, 64, u)
+/* "fmov  Dd, Rn" is generated instead of "dup  Dd, Rn".
+   No assembley scan included.  */
+
+OBSCURE_FUNC (128, 32, f)
+TESTFUNC (128, 32, f)
+/* "dup  Vd.4s, Rn" is less preferable then "dup  Vd.4s, Vn.s[lane]".  */
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 1 } } */
+
+OBSCURE_FUNC (128, 64, f)
+TESTFUNC (128, 64, f)
+/* "dup  Vd.2d, Rn" is less preferable then "dup  Vd.2d, Vn.d[lane]".  */
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 1 } } */
+
+OBSCURE_FUNC (128, 8, p)
+TESTFUNC (128, 8, p)
+/* Generates "dup  Vd.16b, Rn". Scan found near s8 version.  */
+
+OBSCURE_FUNC (128, 16, p)
+TESTFUNC (128, 16, p)
+/* Generates "dup  Vd.8h, Rn". Scan found near s16 version.  */
+
+OBSCURE_FUNC (128, 8, s)
+TESTFUNC (128, 8, s)
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.16b, w\[0-9\]+" 3 } } */
+
+OBSCURE_FUNC (128, 16, s)
+TESTFUNC (128, 16, s)
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.8h, w\[0-9\]+" 3 } } */
+
+OBSCURE_FUNC (128, 32, s)
+TESTFUNC (128, 32, s)
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.4s, w\[0-9\]+" 2 } } */
+
+OBSCURE_FUNC (128, 64, s)
+TESTFUNC (128, 64, s)
+/* { dg-final { scan-assembler-times "dup\\tv\[0-9\]+\.2d, x\[0-9\]+" 2 } } */
+
+OBSCURE_FUNC (128, 8, u)
+TESTFUNC (128, 8, u)
+/* Generates "dup  Vd.16b, Rn". Scan found near s8 version.  */
+
+OBSCURE_FUNC (128, 16, u)
+TESTFUNC (128, 16, u)
+/* Generates "dup  Vd.8h, Rn". Scan found near s16 version.  */
+
+OBSCURE_FUNC (128, 32, u)
+TESTFUNC (128, 32, u)
+/* Generates "dup  Vd.4s, Rn". Scan found near s32 version.  */
+
+OBSCURE_FUNC (128, 64, u)
+TESTFUNC (128, 64, u)
+/* Generates "dup  Vd.2d, Rn". Scan found near s64 version.  */
+
+int
+main (int argc, char **argv)
+{
+  if (test_vmov_n_f32 ())
+    abort ();
+  if (test_vmov_n_f64 ())
+    abort ();
+  if (test_vmov_n_p8 ())
+    abort ();
+  if (test_vmov_n_p16 ())
+    abort ();
+  if (test_vmov_n_s8 ())
+    abort ();
+  if (test_vmov_n_s16 ())
+    abort ();
+  if (test_vmov_n_s32 ())
+    abort ();
+  if (test_vmov_n_s64 ())
+    abort ();
+  if (test_vmov_n_u8 ())
+    abort ();
+  if (test_vmov_n_u16 ())
+    abort ();
+  if (test_vmov_n_u32 ())
+    abort ();
+  if (test_vmov_n_u64 ())
+    abort ();
+
+  if (test_vmovq_n_f32 ())
+    abort ();
+  if (test_vmovq_n_f64 ())
+    abort ();
+  if (test_vmovq_n_p8 ())
+    abort ();
+  if (test_vmovq_n_p16 ())
+    abort ();
+  if (test_vmovq_n_s8 ())
+    abort ();
+  if (test_vmovq_n_s16 ())
+    abort ();
+  if (test_vmovq_n_s32 ())
+    abort ();
+  if (test_vmovq_n_s64 ())
+    abort ();
+  if (test_vmovq_n_u8 ())
+    abort ();
+  if (test_vmovq_n_u16 ())
+    abort ();
+  if (test_vmovq_n_u32 ())
+    abort ();
+  if (test_vmovq_n_u64 ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vneg_f.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vneg_f.c
new file mode 100644
index 000000000..015030285
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vneg_f.c
@@ -0,0 +1,270 @@
+/* Test vneg works correctly.  */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include <arm_neon.h>
+
+#define FLT_EPSILON __FLT_EPSILON__
+#define DBL_EPSILON __DBL_EPSILON__
+#define FLT_MAX __FLT_MAX__
+#define FLT_MIN __FLT_MIN__
+#define DBL_MAX __DBL_MAX__
+#define DBL_MIN __DBL_MIN__
+
+#define TEST0 0
+/* 6 digits of pi.  */
+#define TEST1 3.14159
+/* 6 digits of -e.  */
+#define TEST2 -2.71828
+/* 2^25, float has 24 significand bits
+   according to Single-precision floating-point format.  */
+#define TEST3_FLT 33554432
+/* 2^54, double has 53 significand bits
+   according to Double-precision floating-point format.  */
+#define TEST3_DBL 18014398509481984
+
+extern void abort (void);
+
+#define FLT_INFINITY (__builtin_inff ())
+#define DBL_INFINITY (__builtin_inf ())
+
+#ifndef NAN
+#define NAN (0.0 / 0.0)
+#endif
+
+#define CONCAT(a, b) a##b
+#define CONCAT1(a, b) CONCAT (a, b)
+#define REG_INFEX64 _
+#define REG_INFEX128 q_
+#define REG_INFEX(reg_len) REG_INFEX##reg_len
+#define POSTFIX(reg_len, data_len) \
+  CONCAT1 (REG_INFEX (reg_len), f##data_len)
+
+#define DATA_TYPE_32 float
+#define DATA_TYPE_64 double
+#define DATA_TYPE(data_len) DATA_TYPE_##data_len
+
+#define STORE_INST(reg_len, data_len) \
+  CONCAT1 (vst1, POSTFIX (reg_len, data_len))
+#define LOAD_INST(reg_len, data_len) \
+  CONCAT1 (vld1, POSTFIX (reg_len, data_len))
+#define NEG_INST(reg_len, data_len) \
+  CONCAT1 (vneg, POSTFIX (reg_len, data_len))
+
+#define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
+#define RUN_TEST(test_set, reg_len, data_len, n, a, b, c) \
+  {						       \
+    int i;					       \
+    (a) = LOAD_INST (reg_len, data_len) (test_set);    \
+    (b) = NEG_INST (reg_len, data_len) (a);	       \
+    STORE_INST (reg_len, data_len) (c, b);	       \
+    for (i = 0; i < n; i++)			       \
+      {						       \
+	DATA_TYPE (data_len) diff;		       \
+	INHIB_OPTIMIZATION;			       \
+	diff = test_set[i] + c[i];		       \
+	if (diff > EPSILON)			       \
+	    return 1;				       \
+      }						       \
+  }
+
+#define TEST3 TEST3_FLT
+#define EPSILON FLT_EPSILON
+#define VAR_MIN FLT_MIN
+#define VAR_MAX FLT_MAX
+#define INFINITY FLT_INFINITY
+
+int
+test_vneg_f32 ()
+{
+  float32x2_t a;
+  float32x2_t b;
+  float32_t c[2];
+
+  float32_t test_set0[2] = { TEST0, TEST1 };
+  float32_t test_set1[2] = { TEST2, TEST3 };
+  float32_t test_set2[2] = { VAR_MAX, VAR_MIN };
+  float32_t test_set3[2] = { INFINITY, NAN };
+
+  RUN_TEST (test_set0, 64, 32, 2, a, b, c);
+  RUN_TEST (test_set1, 64, 32, 2, a, b, c);
+  RUN_TEST (test_set2, 64, 32, 2, a, b, c);
+  RUN_TEST (test_set3, 64, 32, 0, a, b, c);
+
+  /* Since last test cannot be checked in a uniform way by adding
+     negation result to original value, the number of lanes to be
+     checked in RUN_TEST is 0 (last argument).  Instead, result
+     will be checked manually.  */
+
+  if (c[0] != -INFINITY)
+    return 1;
+
+  if (!__builtin_isnan (c[1]))
+    return 1;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fneg\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 4 } } */
+
+#undef TEST3
+#undef EPSILON
+#undef VAR_MIN
+#undef VAR_MAX
+#undef INFINITY
+
+#define TEST3 TEST3_DBL
+#define EPSILON DBL_EPSILON
+#define VAR_MIN DBL_MIN
+#define VAR_MAX DBL_MAX
+#define INFINITY DBL_INFINITY
+
+int
+test_vneg_f64 ()
+{
+  float64x1_t a;
+  float64x1_t b;
+  float64_t c[1];
+
+  float64_t test_set0[1] = { TEST0 };
+  float64_t test_set1[1] = { TEST1 };
+  float64_t test_set2[1] = { TEST2 };
+  float64_t test_set3[1] = { TEST3 };
+  float64_t test_set4[1] = { VAR_MAX };
+  float64_t test_set5[1] = { VAR_MIN };
+  float64_t test_set6[1] = { INFINITY };
+  float64_t test_set7[1] = { NAN };
+
+  RUN_TEST (test_set0, 64, 64, 1, a, b, c);
+  RUN_TEST (test_set1, 64, 64, 1, a, b, c);
+  RUN_TEST (test_set2, 64, 64, 1, a, b, c);
+  RUN_TEST (test_set3, 64, 64, 1, a, b, c);
+  RUN_TEST (test_set4, 64, 64, 1, a, b, c);
+  RUN_TEST (test_set5, 64, 64, 1, a, b, c);
+  RUN_TEST (test_set6, 64, 64, 0, a, b, c);
+
+  /* Since last test cannot be checked in a uniform way by adding
+     negation result to original value, the number of lanes to be
+     checked in RUN_TEST is 0 (last argument).  Instead, result
+     will be checked manually.  */
+
+  if (c[0] != -INFINITY)
+    return 1;
+
+  /* Same as above.  */
+
+  RUN_TEST (test_set7, 64, 64, 0, a, b, c);
+
+  if (!__builtin_isnan (c[0]))
+    return 1;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fneg\\td\[0-9\]+, d\[0-9\]+" 8 } } */
+
+#undef TEST3
+#undef EPSILON
+#undef VAR_MIN
+#undef VAR_MAX
+#undef INFINITY
+
+#define TEST3 TEST3_FLT
+#define EPSILON FLT_EPSILON
+#define VAR_MIN FLT_MIN
+#define VAR_MAX FLT_MAX
+#define INFINITY FLT_INFINITY
+
+int
+test_vnegq_f32 ()
+{
+  float32x4_t a;
+  float32x4_t b;
+  float32_t c[4];
+
+  float32_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+  float32_t test_set1[4] = { FLT_MAX, FLT_MIN, INFINITY, NAN };
+
+  RUN_TEST (test_set0, 128, 32, 4, a, b, c);
+  RUN_TEST (test_set1, 128, 32, 2, a, b, c);
+
+  /* Since last test cannot be fully checked in a uniform way by
+     adding negation result to original value, the number of lanes
+     to be checked in RUN_TEST is 0 (last argument).  Instead, result
+     will be checked manually.  */
+
+  if (c[2] != -INFINITY)
+    return 1;
+
+  if (!__builtin_isnan (c[3]))
+    return 1;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fneg\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+
+#undef TEST3
+#undef EPSILON
+#undef VAR_MIN
+#undef VAR_MAX
+#undef INFINITY
+
+#define TEST3 TEST3_DBL
+#define EPSILON DBL_EPSILON
+#define VAR_MIN DBL_MIN
+#define VAR_MAX DBL_MAX
+#define INFINITY DBL_INFINITY
+
+int
+test_vnegq_f64 ()
+{
+  float64x2_t a;
+  float64x2_t b;
+  float64_t c[2];
+
+  float64_t test_set0[2] = { TEST0, TEST1 };
+  float64_t test_set1[2] = { TEST2, TEST3 };
+  float64_t test_set2[2] = { FLT_MAX, FLT_MIN };
+  float64_t test_set3[2] = { INFINITY, NAN };
+
+  RUN_TEST (test_set0, 128, 64, 2, a, b, c);
+  RUN_TEST (test_set1, 128, 64, 2, a, b, c);
+  RUN_TEST (test_set2, 128, 64, 2, a, b, c);
+  RUN_TEST (test_set3, 128, 64, 0, a, b, c);
+
+  /* Since last test cannot be checked in a uniform way by adding
+     negation result to original value, the number of lanes to be
+     checked in RUN_TEST is 0 (last argument).  Instead, result
+     will be checked manually.  */
+
+  if (c[0] != -INFINITY)
+    return 1;
+
+  if (!__builtin_isnan (c[1]))
+    return 1;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fneg\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 4 } } */
+
+int
+main (int argc, char **argv)
+{
+  if (test_vneg_f32 ())
+    abort ();
+
+  if (test_vneg_f64 ())
+    abort ();
+
+  if (test_vnegq_f32 ())
+    abort ();
+
+  if (test_vnegq_f64 ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vneg_s.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vneg_s.c
new file mode 100644
index 000000000..accbf1407
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vneg_s.c
@@ -0,0 +1,309 @@
+/* Test vneg works correctly.  */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -O3 -Wno-div-by-zero --save-temps" } */
+
+#include <arm_neon.h>
+#include <limits.h>
+
+/* Used to force a variable to a SIMD register.  */
+#define force_simd(V1)   asm volatile ("mov %d0, %1.d[0]"	\
+	   : "=w"(V1)						\
+	   : "w"(V1)						\
+	   : /* No clobbers */);
+#define INHIB_OPTIMIZATION asm volatile ("" : : : "memory")
+
+#define TEST0 0
+#define TEST1 1
+#define TEST2 -1
+#define TEST3 10
+#define TEST4 -10
+#define TEST5 0
+
+#define ANSW0 0
+#define ANSW1 -1
+#define ANSW2 1
+#define ANSW3 -10
+#define ANSW4 10
+#define ANSW5 0
+
+extern void abort (void);
+
+#define CONCAT(a, b) a##b
+#define CONCAT1(a, b) CONCAT (a, b)
+#define REG_INFEX64 _
+#define REG_INFEX128 q_
+#define REG_INFEX(reg_len) REG_INFEX##reg_len
+#define POSTFIX(reg_len, data_len) \
+  CONCAT1 (REG_INFEX (reg_len), s##data_len)
+#define DATA_TYPE_32 float
+#define DATA_TYPE_64 double
+#define DATA_TYPE(data_len) DATA_TYPE_##data_len
+#define INDEX64_8 [i]
+#define INDEX64_16 [i]
+#define INDEX64_32 [i]
+#define INDEX64_64
+#define INDEX128_8 [i]
+#define INDEX128_16 [i]
+#define INDEX128_32 [i]
+#define INDEX128_64 [i]
+
+#define FORCE_SIMD_INST64_8(data)
+#define FORCE_SIMD_INST64_16(data)
+#define FORCE_SIMD_INST64_32(data)
+#define FORCE_SIMD_INST64_64(data) force_simd (data)
+#define FORCE_SIMD_INST128_8(data)
+#define FORCE_SIMD_INST128_16(data)
+#define FORCE_SIMD_INST128_32(data)
+#define FORCE_SIMD_INST128_64(data)
+
+#define INDEX(reg_len, data_len) \
+  CONCAT1 (INDEX, reg_len##_##data_len)
+#define FORCE_SIMD_INST(reg_len, data_len, data) \
+  CONCAT1 (FORCE_SIMD_INST, reg_len##_##data_len) (data)
+#define LOAD_INST(reg_len, data_len) \
+  CONCAT1 (vld1, POSTFIX (reg_len, data_len))
+#define NEG_INST(reg_len, data_len) \
+  CONCAT1 (vneg, POSTFIX (reg_len, data_len))
+
+#define RUN_TEST(test_set, answ_set, reg_len, data_len, n, a, b)	\
+  {									\
+    int i;								\
+    INHIB_OPTIMIZATION;							\
+    (a) = LOAD_INST (reg_len, data_len) (test_set);			\
+    (b) = LOAD_INST (reg_len, data_len) (answ_set);			\
+    FORCE_SIMD_INST (reg_len, data_len, a)				\
+    a = NEG_INST (reg_len, data_len) (a);				\
+    FORCE_SIMD_INST (reg_len, data_len, a)				\
+    for (i = 0; i < n; i++)						\
+      {									\
+        INHIB_OPTIMIZATION;						\
+	if (a INDEX (reg_len, data_len)					\
+	    != b INDEX (reg_len, data_len))				\
+	  return 1;							\
+      }									\
+  }
+
+int
+test_vneg_s8 ()
+{
+  int8x8_t a;
+  int8x8_t b;
+
+  int8_t test_set0[8] = {
+    TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SCHAR_MAX, SCHAR_MIN
+  };
+  int8_t answ_set0[8] = {
+    ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SCHAR_MIN + 1, SCHAR_MIN
+  };
+
+  RUN_TEST (test_set0, answ_set0, 64, 8, 8, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
+
+int
+test_vneg_s16 ()
+{
+  int16x4_t a;
+  int16x4_t b;
+
+  int16_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+  int16_t test_set1[4] = { TEST4, TEST5, SHRT_MAX, SHRT_MIN };
+
+  int16_t answ_set0[4] = { ANSW0, ANSW1, ANSW2, ANSW3 };
+  int16_t answ_set1[4] = { ANSW4, ANSW5, SHRT_MIN + 1, SHRT_MIN };
+
+  RUN_TEST (test_set0, answ_set0, 64, 16, 4, a, b);
+  RUN_TEST (test_set1, answ_set1, 64, 16, 4, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 2 } } */
+
+int
+test_vneg_s32 ()
+{
+  int32x2_t a;
+  int32x2_t b;
+
+  int32_t test_set0[2] = { TEST0, TEST1 };
+  int32_t test_set1[2] = { TEST2, TEST3 };
+  int32_t test_set2[2] = { TEST4, TEST5 };
+  int32_t test_set3[2] = { INT_MAX, INT_MIN };
+
+  int32_t answ_set0[2] = { ANSW0, ANSW1 };
+  int32_t answ_set1[2] = { ANSW2, ANSW3 };
+  int32_t answ_set2[2] = { ANSW4, ANSW5 };
+  int32_t answ_set3[2] = { INT_MIN + 1, INT_MIN };
+
+  RUN_TEST (test_set0, answ_set0, 64, 32, 2, a, b);
+  RUN_TEST (test_set1, answ_set1, 64, 32, 2, a, b);
+  RUN_TEST (test_set2, answ_set2, 64, 32, 2, a, b);
+  RUN_TEST (test_set3, answ_set3, 64, 32, 2, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 4 } } */
+
+int
+test_vneg_s64 ()
+{
+  int64x1_t a;
+  int64x1_t b;
+
+  int64_t test_set0[1] = { TEST0 };
+  int64_t test_set1[1] = { TEST1 };
+  int64_t test_set2[1] = { TEST2 };
+  int64_t test_set3[1] = { TEST3 };
+  int64_t test_set4[1] = { TEST4 };
+  int64_t test_set5[1] = { TEST5 };
+  int64_t test_set6[1] = { LLONG_MAX };
+  int64_t test_set7[1] = { LLONG_MIN };
+
+  int64_t answ_set0[1] = { ANSW0 };
+  int64_t answ_set1[1] = { ANSW1 };
+  int64_t answ_set2[1] = { ANSW2 };
+  int64_t answ_set3[1] = { ANSW3 };
+  int64_t answ_set4[1] = { ANSW4 };
+  int64_t answ_set5[1] = { ANSW5 };
+  int64_t answ_set6[1] = { LLONG_MIN + 1 };
+  int64_t answ_set7[1] = { LLONG_MIN };
+
+  RUN_TEST (test_set0, answ_set0, 64, 64, 1, a, b);
+  RUN_TEST (test_set1, answ_set1, 64, 64, 1, a, b);
+  RUN_TEST (test_set2, answ_set2, 64, 64, 1, a, b);
+  RUN_TEST (test_set3, answ_set3, 64, 64, 1, a, b);
+  RUN_TEST (test_set4, answ_set4, 64, 64, 1, a, b);
+  RUN_TEST (test_set5, answ_set5, 64, 64, 1, a, b);
+  RUN_TEST (test_set6, answ_set6, 64, 64, 1, a, b);
+  RUN_TEST (test_set7, answ_set7, 64, 64, 1, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\td\[0-9\]+, d\[0-9\]+" 8 } } */
+
+int
+test_vnegq_s8 ()
+{
+  int8x16_t a;
+  int8x16_t b;
+
+  int8_t test_set0[16] = {
+    TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SCHAR_MAX, SCHAR_MIN,
+    4, 8, 15, 16, 23, 42, -1, -2
+  };
+
+  int8_t answ_set0[16] = {
+    ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SCHAR_MIN + 1, SCHAR_MIN,
+    -4, -8, -15, -16, -23, -42, 1, 2
+  };
+
+  RUN_TEST (test_set0, answ_set0, 128, 8, 8, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+
+int
+test_vnegq_s16 ()
+{
+  int16x8_t a;
+  int16x8_t b;
+
+  int16_t test_set0[8] = {
+    TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, SHRT_MAX, SHRT_MIN
+  };
+  int16_t answ_set0[8] = {
+    ANSW0, ANSW1, ANSW2, ANSW3, ANSW4, ANSW5, SHRT_MIN + 1, SHRT_MIN
+  };
+
+  RUN_TEST (test_set0, answ_set0, 128, 16, 8, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+
+int
+test_vnegq_s32 ()
+{
+  int32x4_t a;
+  int32x4_t b;
+
+  int32_t test_set0[4] = { TEST0, TEST1, TEST2, TEST3 };
+  int32_t test_set1[4] = { TEST4, TEST5, INT_MAX, INT_MIN };
+
+  int32_t answ_set0[4] = { ANSW0, ANSW1, ANSW2, ANSW3 };
+  int32_t answ_set1[4] = { ANSW4, ANSW5, INT_MIN + 1, INT_MIN };
+
+  RUN_TEST (test_set0, answ_set0, 128, 32, 4, a, b);
+  RUN_TEST (test_set1, answ_set1, 128, 32, 4, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+
+int
+test_vnegq_s64 ()
+{
+  int64x2_t a;
+  int64x2_t b;
+
+  int64_t test_set0[2] = { TEST0, TEST1 };
+  int64_t test_set1[2] = { TEST2, TEST3 };
+  int64_t test_set2[2] = { TEST4, TEST5 };
+  int64_t test_set3[2] = { LLONG_MAX, LLONG_MIN };
+
+  int64_t answ_set0[2] = { ANSW0, ANSW1 };
+  int64_t answ_set1[2] = { ANSW2, ANSW3 };
+  int64_t answ_set2[2] = { ANSW4, ANSW5 };
+  int64_t answ_set3[2] = { LLONG_MIN + 1, LLONG_MIN };
+
+  RUN_TEST (test_set0, answ_set0, 128, 64, 2, a, b);
+  RUN_TEST (test_set1, answ_set1, 128, 64, 2, a, b);
+  RUN_TEST (test_set2, answ_set2, 128, 64, 2, a, b);
+  RUN_TEST (test_set3, answ_set3, 128, 64, 2, a, b);
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 4 } } */
+
+int
+main (int argc, char **argv)
+{
+  if (test_vneg_s8 ())
+    abort ();
+
+  if (test_vneg_s16 ())
+    abort ();
+
+  if (test_vneg_s32 ())
+    abort ();
+
+  if (test_vneg_s64 ())
+    abort ();
+
+  if (test_vnegq_s8 ())
+    abort ();
+
+  if (test_vnegq_s16 ())
+    abort ();
+
+  if (test_vnegq_s32 ())
+    abort ();
+
+  if (test_vnegq_s64 ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-1.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-1.c
new file mode 100644
index 000000000..c69d3a358
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct {
+  char a:1;
+  char b:7;
+  int c;
+} BitStruct;
+
+volatile BitStruct bits;
+
+int foo ()
+{
+  return bits.b;
+}
+
+/* { dg-final { scan-assembler "ldrb\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-2.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-2.c
new file mode 100644
index 000000000..c7a9ebaa2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct {
+  volatile unsigned long a:8;
+  volatile unsigned long b:8;
+  volatile unsigned long c:16;
+} BitStruct;
+
+BitStruct bits;
+
+unsigned long foo ()
+{
+  return bits.b;
+}
+
+/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-3.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-3.c
new file mode 100644
index 000000000..ea371dbac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/volatile-bitfields-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct {
+  volatile unsigned long a:8;
+  volatile unsigned long b:8;
+  volatile unsigned long c:16;
+} BitStruct;
+
+BitStruct bits;
+
+unsigned long foo ()
+{
+  return bits.c;
+}
+
+/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vrecps.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vrecps.c
new file mode 100644
index 000000000..c279a4493
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vrecps.c
@@ -0,0 +1,144 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+#include <math.h>
+#include <stdlib.h>
+
+int
+test_frecps_float32_t (void)
+{
+  int i;
+  float32_t value = 0.2;
+  float32_t reciprocal = 5.0;
+  float32_t step = vrecpes_f32 (value);
+  /* 3 steps should give us within ~0.001 accuracy.  */
+  for (i = 0; i < 3; i++)
+    step = step * vrecpss_f32 (step, value);
+
+  return fabs (step - reciprocal) < 0.001;
+}
+
+/* { dg-final { scan-assembler "frecpe\\ts\[0-9\]+, s\[0-9\]+" } } */
+/* { dg-final { scan-assembler "frecps\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" } } */
+
+int
+test_frecps_float32x2_t (void)
+{
+  int i;
+  int ret = 1;
+
+  const float32_t value_pool[] = {0.2, 0.4};
+  const float32_t reciprocal_pool[] = {5.0, 2.5};
+  float32x2_t value = vld1_f32 (value_pool);
+  float32x2_t reciprocal = vld1_f32 (reciprocal_pool);
+
+  float32x2_t step = vrecpe_f32 (value);
+  /* 3 steps should give us within ~0.001 accuracy.  */
+  for (i = 0; i < 3; i++)
+    step = step * vrecps_f32 (step, value);
+
+  ret &= fabs (vget_lane_f32 (step, 0)
+	       - vget_lane_f32 (reciprocal, 0)) < 0.001;
+  ret &= fabs (vget_lane_f32 (step, 1)
+	       - vget_lane_f32 (reciprocal, 1)) < 0.001;
+
+  return ret;
+}
+
+/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.2s, v\[0-9\]+.2s" } } */
+/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.2s, v\[0-9\]+.2s, v\[0-9\]+.2s" } } */
+
+int
+test_frecps_float32x4_t (void)
+{
+  int i;
+  int ret = 1;
+
+  const float32_t value_pool[] = {0.2, 0.4, 0.5, 0.8};
+  const float32_t reciprocal_pool[] = {5.0, 2.5, 2.0, 1.25};
+  float32x4_t value = vld1q_f32 (value_pool);
+  float32x4_t reciprocal = vld1q_f32 (reciprocal_pool);
+
+  float32x4_t step = vrecpeq_f32 (value);
+  /* 3 steps should give us within ~0.001 accuracy.  */
+  for (i = 0; i < 3; i++)
+    step = step * vrecpsq_f32 (step, value);
+
+  ret &= fabs (vgetq_lane_f32 (step, 0)
+	       - vgetq_lane_f32 (reciprocal, 0)) < 0.001;
+  ret &= fabs (vgetq_lane_f32 (step, 1)
+	       - vgetq_lane_f32 (reciprocal, 1)) < 0.001;
+  ret &= fabs (vgetq_lane_f32 (step, 2)
+	       - vgetq_lane_f32 (reciprocal, 2)) < 0.001;
+  ret &= fabs (vgetq_lane_f32 (step, 3)
+	       - vgetq_lane_f32 (reciprocal, 3)) < 0.001;
+
+  return ret;
+}
+
+/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.4s, v\[0-9\]+.4s" } } */
+/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.4s, v\[0-9\]+.4s, v\[0-9\]+.4s" } } */
+
+int
+test_frecps_float64_t (void)
+{
+  int i;
+  float64_t value = 0.2;
+  float64_t reciprocal = 5.0;
+  float64_t step = vrecped_f64 (value);
+  /* 3 steps should give us within ~0.001 accuracy.  */
+  for (i = 0; i < 3; i++)
+    step = step * vrecpsd_f64 (step, value);
+
+  return fabs (step - reciprocal) < 0.001;
+}
+
+/* { dg-final { scan-assembler "frecpe\\td\[0-9\]+, d\[0-9\]+" } } */
+/* { dg-final { scan-assembler "frecps\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" } } */
+
+int
+test_frecps_float64x2_t (void)
+{
+  int i;
+  int ret = 1;
+
+  const float64_t value_pool[] = {0.2, 0.4};
+  const float64_t reciprocal_pool[] = {5.0, 2.5};
+  float64x2_t value = vld1q_f64 (value_pool);
+  float64x2_t reciprocal = vld1q_f64 (reciprocal_pool);
+
+  float64x2_t step = vrecpeq_f64 (value);
+  /* 3 steps should give us within ~0.001 accuracy.  */
+  for (i = 0; i < 3; i++)
+    step = step * vrecpsq_f64 (step, value);
+
+  ret &= fabs (vgetq_lane_f64 (step, 0)
+	       - vgetq_lane_f64 (reciprocal, 0)) < 0.001;
+  ret &= fabs (vgetq_lane_f64 (step, 1)
+	       - vgetq_lane_f64 (reciprocal, 1)) < 0.001;
+
+  return ret;
+}
+
+/* { dg-final { scan-assembler "frecpe\\tv\[0-9\]+.2d, v\[0-9\]+.2d" } } */
+/* { dg-final { scan-assembler "frecps\\tv\[0-9\]+.2d, v\[0-9\]+.2d, v\[0-9\]+.2d" } } */
+
+int
+main (int argc, char **argv)
+{
+  if (!test_frecps_float32_t ())
+    abort ();
+  if (!test_frecps_float32x2_t ())
+    abort ();
+  if (!test_frecps_float32x4_t ())
+    abort ();
+  if (!test_frecps_float64_t ())
+    abort ();
+  if (!test_frecps_float64x2_t ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vrecpx.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vrecpx.c
new file mode 100644
index 000000000..63097f1d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vrecpx.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O3 --save-temps" } */
+
+#include <arm_neon.h>
+#include <math.h>
+#include <stdlib.h>
+
+float32_t in_f[] =
+{2.0, 4.0, 8.0, 16.0, 1.0, 0.5, 0.25, 0.125};
+float32_t rec_f[] =
+{1.0, 0.5, 0.25, 0.125, 2.0, 4.0, 8.0, 16.0};
+float64_t in_d[] =
+{2.0, 4.0, 8.0, 16.0, 1.0, 0.5, 0.25, 0.125};
+float32_t rec_d[] =
+{1.0, 0.5, 0.25, 0.125, 2.0, 4.0, 8.0, 16.0};
+
+int
+test_frecpx_float32_t (void)
+{
+  int i = 0;
+  int ret = 1;
+  for (i = 0; i < 8; i++)
+    ret &= fabs (vrecpxs_f32 (in_f[i]) - rec_f[i]) < 0.001;
+
+  return ret;
+}
+
+/* { dg-final { scan-assembler "frecpx\\ts\[0-9\]+, s\[0-9\]+" } } */
+
+int
+test_frecpx_float64_t (void)
+{
+  int i = 0;
+  int ret = 1;
+  for (i = 0; i < 8; i++)
+    ret &= fabs (vrecpxd_f64 (in_d[i]) - rec_d[i]) < 0.001;
+
+  return ret;
+}
+
+/* { dg-final { scan-assembler "frecpx\\td\[0-9\]+, d\[0-9\]+" } } */
+
+int
+main (int argc, char **argv)
+{
+  if (!test_frecpx_float32_t ())
+    abort ();
+  if (!test_frecpx_float64_t ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vsqrt.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vsqrt.c
new file mode 100644
index 000000000..5b777b236
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vsqrt.c
@@ -0,0 +1,72 @@
+
+
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#include "arm_neon.h"
+#include "stdio.h"
+
+extern void abort (void);
+
+void
+test_square_root_v2sf ()
+{
+  const float32_t pool[] = {4.0f, 9.0f};
+  float32x2_t val;
+  float32x2_t res;
+
+  val = vld1_f32 (pool);
+  res = vsqrt_f32 (val);
+
+  if (vget_lane_f32 (res, 0) != 2.0f)
+    abort ();
+  if (vget_lane_f32 (res, 1) != 3.0f)
+    abort ();
+}
+
+void
+test_square_root_v4sf ()
+{
+  const float32_t pool[] = {4.0f, 9.0f, 16.0f, 25.0f};
+  float32x4_t val;
+  float32x4_t res;
+
+  val = vld1q_f32 (pool);
+  res = vsqrtq_f32 (val);
+
+  if (vgetq_lane_f32 (res, 0) != 2.0f)
+    abort ();
+  if (vgetq_lane_f32 (res, 1) != 3.0f)
+    abort ();
+  if (vgetq_lane_f32 (res, 2) != 4.0f)
+    abort ();
+  if (vgetq_lane_f32 (res, 3) != 5.0f)
+    abort ();
+}
+
+void
+test_square_root_v2df ()
+{
+  const float64_t pool[] = {4.0, 9.0};
+  float64x2_t val;
+  float64x2_t res;
+
+  val = vld1q_f64 (pool);
+  res = vsqrtq_f64 (val);
+
+  if (vgetq_lane_f64 (res, 0) != 2.0)
+    abort ();
+
+  if (vgetq_lane_f64 (res, 1) != 3.0)
+    abort ();
+}
+
+int
+main (void)
+{
+  test_square_root_v2sf ();
+  test_square_root_v4sf ();
+  test_square_root_v2df ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vsub_f64.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vsub_f64.c
new file mode 100644
index 000000000..abf4fc42d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vsub_f64.c
@@ -0,0 +1,116 @@
+/* Test vsub works correctly.  */
+/* { dg-do run } */
+/* { dg-options "--save-temps" } */
+
+#include <arm_neon.h>
+
+#define FLT_EPSILON __FLT_EPSILON__
+#define DBL_EPSILON __DBL_EPSILON__
+
+#define TESTA0 1
+#define TESTA1 0.2223
+#define TESTA2 0
+#define TESTA3 -0.76544
+/* 2^54, double has 53 significand bits
+   according to Double-precision floating-point format.  */
+#define TESTA4 18014398509481984
+#define TESTA5 2.0
+
+#define TESTB0 0.66667
+#define TESTB1 2
+#define TESTB2 0
+#define TESTB3 -2
+#define TESTB4 1.0
+#define TESTB5 (1.0 / TESTA4)
+
+#define ANSW0 0.33333
+#define ANSW1 -1.7777
+#define ANSW2 0
+#define ANSW3 1.23456
+#define ANSW4 TESTA4
+#define ANSW5 2.0
+
+extern void abort (void);
+
+#define EPSILON __DBL_EPSILON__
+#define ISNAN(a) __builtin_isnan (a)
+/* FP_equals is implemented like this to execute subtraction
+   exectly once during a single test run.  */
+#define FP_equals(a, b, epsilon)		\
+(						\
+ ((a) == (b))					\
+ || (ISNAN (a) && ISNAN (b))			\
+ || (((a > b) && (a < (b + epsilon)))		\
+     || ((b > a) && (b < (a + epsilon))))	\
+)
+
+int
+test_vsub_f64 ()
+{
+  float64x1_t a;
+  float64x1_t b;
+  float64x1_t c;
+
+  a = TESTA0;
+  b = TESTB0;
+  c = ANSW0;
+
+  a = vsub_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA1;
+  b = TESTB1;
+  c = ANSW1;
+
+  a = vsub_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA2;
+  b = TESTB2;
+  c = ANSW2;
+
+  a = vsub_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA3;
+  b = TESTB3;
+  c = ANSW3;
+
+  a = vsub_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA4;
+  b = TESTB4;
+  c = ANSW4;
+
+  a = vsub_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  a = TESTA5;
+  b = TESTB5;
+  c = ANSW5;
+
+  a = vsub_f64 (a, b);
+  if (!FP_equals (a, c, EPSILON))
+    return 1;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "fsub\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 6 } } */
+
+int
+main (int argc, char **argv)
+{
+  if (test_vsub_f64 ())
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/20000715-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/20000715-1.c
new file mode 100644
index 000000000..3ff15604e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/20000715-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mieee" } */
+
+float foo(unsigned char n)
+{
+  float r = 10 * n;
+  asm volatile("" : : : "memory");
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/20011018-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/20011018-1.c
new file mode 100644
index 000000000..e01fcf5c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/20011018-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mieee" } */
+
+double foo (void);
+void bar (float, float);
+
+void test (void)
+{
+  float f, g;
+
+  f = foo();
+  g = foo();
+  asm ("");
+  bar (f, g);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/980217-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/980217-1.c
new file mode 100644
index 000000000..e4ecf69fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/980217-1.c
@@ -0,0 +1,39 @@
+/* Test float on alpha. */
+
+/* { dg-do run } */
+/* { dg-options "-mieee -O2" } */
+
+extern void abort(void);
+extern int printf(const char *, ...);
+
+typedef int int32_t __attribute__ ((__mode__ (  __SI__ ))) ;
+typedef union
+{
+  float value;
+  int32_t word;
+} ieee_float_shape_type;
+
+int isinff(float x)
+{
+  int32_t ix,t;
+  ieee_float_shape_type gf_u;
+  gf_u.value = x;
+  ix = gf_u.word;
+  printf ("%x\n", ix);
+  t = ix & 0x7fffffff;
+  t ^= 0x7f800000;
+  t |= -t;
+  return ~(t >> 31) & (1 - ((ix & 0x80000000) >> 30));
+}
+
+main ()
+{
+  float x = 1.0 / 0.0;
+  int i = isinff (x);
+
+  if (i == 0)
+    abort ();
+
+  printf ("%d\n", i);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/alpha.exp b/gcc-4.9/gcc/testsuite/gcc.target/alpha/alpha.exp
new file mode 100644
index 000000000..bd107c8df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/alpha.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an Alpha target.
+if ![istarget alpha*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/asm-1.c
new file mode 100644
index 000000000..4bb5ecbb7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/asm-1.c
@@ -0,0 +1,82 @@
+/* Asm operands that are given as hard registers must keep the same
+   hard register all the way through compilation.  Example derived
+   from glibc source.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -frename-registers -fcprop-registers" } */
+/* { dg-final { scan-assembler "callsys1 .0 .19 .0 .16 .17" } } */
+/* { dg-final { scan-assembler "callsys2 .0 .19 .0 .16 .17" } } */
+
+struct stat {
+  int dummy;
+};
+
+struct kernel_stat {
+  int dummy;
+};
+
+extern int xstat_conv (int vers, struct kernel_stat *kbuf, void *ubuf);
+extern int *__errno_location (void) __attribute__ ((__const__));
+
+int
+__fxstat (int vers, int fd, struct stat *buf)
+{
+  struct kernel_stat kbuf;
+  int result;
+
+  if (vers == 0)
+    return
+      ({
+	long _sc_ret, _sc_err;
+	{
+	  register long _sc_0 __asm__("$0");
+	  register long _sc_16 __asm__("$16");
+	  register long _sc_17 __asm__("$17");
+	  register long _sc_19 __asm__("$19");
+	  _sc_0 = 91;
+	  _sc_16 = (long) (fd);
+	  _sc_17 = (long) (((struct kernel_stat *) buf));
+	  __asm__("callsys1 %0 %1 %2 %3 %4"
+		  : "=r"(_sc_0), "=r"(_sc_19)
+		  : "0"(_sc_0), "r"(_sc_16), "r"(_sc_17)
+		  : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		    "$22", "$23", "$24", "$25", "$27", "$28", "memory");
+	  _sc_ret = _sc_0, _sc_err = _sc_19;
+	}
+	if (_sc_err)
+	  {
+	    (*__errno_location ()) = (_sc_ret);
+	    _sc_ret = -1L;
+	  }
+	_sc_ret;
+      });
+
+  result =
+      ({
+	long _sc_ret, _sc_err;
+	{
+	  register long _sc_0 __asm__("$0");
+	  register long _sc_16 __asm__("$16");
+	  register long _sc_17 __asm__("$17");
+	  register long _sc_19 __asm__("$19");
+	  _sc_0 = 91;
+	  _sc_16 = (long) (fd);
+	  _sc_17 = (long) ((&kbuf));
+	  __asm__("callsys2 %0 %1 %2 %3 %4"
+		  : "=r"(_sc_0), "=r"(_sc_19)
+		  : "0"(_sc_0), "r"(_sc_16), "r"(_sc_17)
+		  : "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		    "$22", "$23", "$24", "$25", "$27", "$28", "memory");
+	  _sc_ret = _sc_0, _sc_err = _sc_19;
+	}
+	if (_sc_err)
+	  {
+	    (*__errno_location ()) = (_sc_ret);
+	    _sc_ret = -1L;
+	  }
+	_sc_ret;
+      });
+  if (result == 0)
+    result = xstat_conv (vers, &kbuf, buf);
+
+  return result;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/base-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/base-1.c
new file mode 100644
index 000000000..bca3bf56d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/base-1.c
@@ -0,0 +1,73 @@
+/* Test that the base isa builtins compile.  */
+/* { dg-do link } */
+/* { dg-options "-mcpu=ev4" } */
+
+void test_BASE (long x, long y)
+{
+  volatile long sink;
+  long z;
+
+  sink = __builtin_alpha_implver ();
+  sink = __builtin_alpha_rpcc ();
+
+  sink = __builtin_alpha_amask (-1);
+  sink = __builtin_alpha_amask (x);
+
+  sink = __builtin_alpha_cmpbge (x, y);
+  sink = __builtin_alpha_cmpbge (-1, x);
+
+  sink = __builtin_alpha_extbl (x, y);
+  sink = __builtin_alpha_extwl (x, y);
+  sink = __builtin_alpha_extll (x, y);
+  sink = __builtin_alpha_extql (x, y);
+  sink = __builtin_alpha_extwh (x, y);
+  sink = __builtin_alpha_extlh (x, y);
+  sink = __builtin_alpha_extqh (x, y);
+
+  sink = __builtin_alpha_insbl (x, y);
+  sink = __builtin_alpha_inswl (x, y);
+  sink = __builtin_alpha_insll (x, y);
+  sink = __builtin_alpha_insql (x, y);
+  sink = __builtin_alpha_inswh (x, y);
+  sink = __builtin_alpha_inslh (x, y);
+  sink = __builtin_alpha_insqh (x, y);
+
+  sink = __builtin_alpha_mskbl (x, y);
+  sink = __builtin_alpha_mskwl (x, y);
+  sink = __builtin_alpha_mskll (x, y);
+  sink = __builtin_alpha_mskql (x, y);
+  sink = __builtin_alpha_mskwh (x, y);
+  sink = __builtin_alpha_msklh (x, y);
+  sink = __builtin_alpha_mskqh (x, y);
+
+  sink = __builtin_alpha_umulh (x, y);
+}
+
+void test_zap (long x, long y)
+{
+  volatile long sink;
+  long z;
+  sink = __builtin_alpha_zap (x, y);
+  sink = __builtin_alpha_zap (x, 0xaa);
+  z = 0xaa;
+  sink = __builtin_alpha_zap (x, z);
+  z = 0;
+  sink = __builtin_alpha_zap (z, x);
+  sink = __builtin_alpha_zap (x, z);
+}
+
+void test_zapnot (long x, long y)
+{
+  volatile long sink;
+  long z;
+
+  sink = __builtin_alpha_zapnot (x, y);
+  sink = __builtin_alpha_zapnot (x, 0xaa);
+  z = 0xaa;
+  sink = __builtin_alpha_zapnot (x, z);
+  z = 0;
+  sink = __builtin_alpha_zapnot (z, x);
+  sink = __builtin_alpha_zapnot (x, z);
+}
+
+int main() { return 0; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/base-2.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/base-2.c
new file mode 100644
index 000000000..830dbc7b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/base-2.c
@@ -0,0 +1,5 @@
+/* Test that alpha-base-1.c compiles with optimization.  */
+/* { dg-do link } */
+/* { dg-options "-mcpu=ev4 -O2" } */
+
+#include "base-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/cix-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/cix-1.c
new file mode 100644
index 000000000..53aa6efd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/cix-1.c
@@ -0,0 +1,14 @@
+/* Test that the CIX isa builtins compile.  */
+/* { dg-do link } */
+/* { dg-options "-mcpu=ev67" } */
+
+void test_CIX (long x)
+{
+  volatile long sink;
+
+  sink = __builtin_alpha_cttz (x);
+  sink = __builtin_alpha_ctlz (x);
+  sink = __builtin_alpha_ctpop (x);
+}
+
+int main() { return 0; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/cix-2.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/cix-2.c
new file mode 100644
index 000000000..c34c3c68b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/cix-2.c
@@ -0,0 +1,5 @@
+/* Test that alpha-cix-1.c compiles with optimization.  */
+/* { dg-do link } */
+/* { dg-options "-mcpu=ev67 -O2" } */
+
+#include "cix-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/max-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/max-1.c
new file mode 100644
index 000000000..3f86160f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/max-1.c
@@ -0,0 +1,27 @@
+/* Test that the MAX isa builtins compile.  */
+/* { dg-do link } */
+/* { dg-options "-mcpu=pca56" } */
+
+void test_MAX (long x, long y)
+{
+  volatile long sink;
+
+  sink = __builtin_alpha_pklb (x);
+  sink = __builtin_alpha_pkwb (x);
+  sink = __builtin_alpha_unpkbl (x);
+  sink = __builtin_alpha_unpkbw (x);
+
+  sink = __builtin_alpha_minub8 (0, x);
+  sink = __builtin_alpha_minub8 (1, x);
+  sink = __builtin_alpha_minub8 (x, y);
+  sink = __builtin_alpha_minsb8 (x, y);
+  sink = __builtin_alpha_minuw4 (x, y);
+  sink = __builtin_alpha_minsw4 (x, y);
+  sink = __builtin_alpha_maxub8 (x, y);
+  sink = __builtin_alpha_maxsb8 (x, y);
+  sink = __builtin_alpha_maxuw4 (x, y);
+  sink = __builtin_alpha_maxsw4 (x, y);
+  sink = __builtin_alpha_perr (x, y);
+}
+
+int main() { return 0; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/max-2.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/max-2.c
new file mode 100644
index 000000000..c5491eaba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/max-2.c
@@ -0,0 +1,5 @@
+/* Test that alpha-max-1.c compiles with optimization.  */
+/* { dg-do link } */
+/* { dg-options "-mcpu=pca56 -O2" } */
+
+#include "max-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr19518.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr19518.c
new file mode 100644
index 000000000..42c58b5a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr19518.c
@@ -0,0 +1,60 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ev67" } */
+
+typedef short INT16;
+typedef unsigned int CARD32;
+typedef unsigned short CARD16;
+typedef unsigned char CARD8;
+typedef struct _Picture *PicturePtr;
+typedef int FbStride;
+typedef unsigned long __m64;
+extern __m64 load8888 (__m64);
+static __inline __m64 _mm_adds_pu8(__m64 __m1, __m64 __m2)
+{
+    return __m1 + __builtin_alpha_minsb8(__m2, ~__m1);
+}
+static __inline __m64 _mm_packs_pu16(__m64 __m1, __m64 __m2)
+{
+    __m1 = __builtin_alpha_minuw4(__m1, 0x00ff00ff00ff00ff);
+    __m2 = __builtin_alpha_minuw4(__m2, 0x00ff00ff00ff00ff);
+    return __m1 | (__m2 << 32);
+}
+typedef unsigned long long ullong;
+static __inline__ __m64 pix_multiply(__m64 a)
+{
+    if (a)
+	return a;
+}
+static __inline__ __m64 over(__m64 src, __m64 srca, __m64 dest)
+{
+    return _mm_adds_pu8(src, pix_multiply(dest));
+}
+
+void fbCompositeSolid_nx8888mmx(CARD8 op, PicturePtr pSrc, PicturePtr pMask,
+				INT16 yDst, CARD16 width, CARD16 height)
+{
+    CARD32 src;
+    CARD32 *dstLine, *dst;
+    CARD16 w;
+    FbStride dstStride;
+    __m64 vsrc, vsrca;
+    vsrc = load8888(src);
+    while (height--) {
+	dst = dstLine;
+	dstLine += dstStride;
+	while (w && (unsigned long) dst & 7) {
+	    *dst = _mm_packs_pu16(_mm_adds_pu8(vsrc, load8888(*dst)),
+				  _mm_setzero_si64());
+	    dst++;
+	}
+	while (w >= 2) {
+	    __m64 dest0, dest1;
+	    *(__m64 *) dst = _mm_packs_pu16(dest0, dest1);
+	    w -= 2;
+	}
+	while (w) {
+	    *dst = _mm_packs_pu16(_mm_adds_pu8(vsrc, pix_multiply(0)), 0);
+	    w--;
+	}
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr22093.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr22093.c
new file mode 100644
index 000000000..aa00e1550
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr22093.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct shared_ptr_struct
+{
+  unsigned long phase : 48;
+  unsigned thread : 16;
+  void *addr;
+} x;
+
+void foo (void)
+{
+   x.thread = 2;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr24178.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr24178.c
new file mode 100644
index 000000000..0a31aa736
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr24178.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ev4" } */
+
+struct S {
+    long l;
+    unsigned char c;
+};
+unsigned long f(unsigned char *p10) {
+    struct S *p = (struct S *) (p10 + 10);
+    return p->c;
+}
+
+/* { dg-final { scan-assembler "ldl.*,18\\(" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr39740.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr39740.c
new file mode 100644
index 000000000..230beb7db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr39740.c
@@ -0,0 +1,162 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -std=c99 -mexplicit-relocs" } */
+
+typedef int R_len_t;
+typedef unsigned int SEXPTYPE;
+struct sxpinfo_struct
+{
+  SEXPTYPE type:5;
+};
+
+struct vecsxp_struct
+{
+  R_len_t length;
+  R_len_t truelength;
+};
+
+struct listsxp_struct
+{
+  struct SEXPREC *carval;
+  struct SEXPREC *cdrval;
+  struct SEXPREC *tagval;
+};
+
+typedef struct SEXPREC
+{
+  struct sxpinfo_struct sxpinfo;
+  union
+  {
+    struct listsxp_struct listsxp;
+  } u;
+} SEXPREC, *SEXP;
+
+typedef struct VECTOR_SEXPREC
+{
+  struct vecsxp_struct vecsxp;
+} VECTOR_SEXPREC, *VECSEXP;
+
+typedef union
+{
+  VECTOR_SEXPREC s;
+  double align;
+} SEXPREC_ALIGN;
+
+extern SEXP R_NilValue;
+extern SEXP R_MissingArg;
+
+int Rf_envlength (SEXP rho);
+SEXP Rf_protect (SEXP);
+const char *Rf_translateChar (SEXP);
+
+inline R_len_t
+Rf_length (SEXP s)
+{
+  int i;
+  switch (((s)->sxpinfo.type))
+    {
+    case 0:
+      return 0;
+    case 24:
+      return (((VECSEXP) (s))->vecsxp.length);
+    case 6:
+    case 17:
+      i = 0;
+      while (s != ((void *) 0) && s != R_NilValue)
+	{
+	  i++;
+	  s = ((s)->u.listsxp.cdrval);
+	}
+      return i;
+    case 4:
+      return Rf_envlength (s);
+    default:
+      return 1;
+    }
+}
+
+inline SEXP
+Rf_lang3 (SEXP s, SEXP t, SEXP u)
+{
+  return s;
+}
+
+typedef SEXP (*CCODE) (SEXP, SEXP, SEXP, SEXP);
+
+static SEXP PlusSymbol;
+static SEXP MinusSymbol;
+static SEXP DivideSymbol;
+
+int isZero (SEXP s);
+SEXP PP (SEXP s);
+SEXP AddParens (SEXP expr);
+SEXP Rf_install ();
+
+static int
+isUminus (SEXP s)
+{
+  if (((s)->sxpinfo.type) == 6 && ((s)->u.listsxp.carval) == MinusSymbol)
+    {
+      switch (Rf_length (s))
+	{
+	case 2:
+	  return 1;
+	case 3:
+	  if (((((((s)->u.listsxp.cdrval))->u.listsxp.cdrval))->u.listsxp.
+	       carval) == R_MissingArg)
+	    return 1;
+	  else
+	    return 0;
+	}
+    }
+  else
+    return 0;
+}
+
+static SEXP
+simplify (SEXP fun, SEXP arg1, SEXP arg2)
+{
+  SEXP ans;
+  if (fun == PlusSymbol)
+    {
+      if (isZero (arg1))
+	ans = arg2;
+      else if (isUminus (arg1))
+	ans =
+	  simplify (MinusSymbol, arg2,
+		    ((((arg1)->u.listsxp.cdrval))->u.listsxp.carval));
+      else if (isUminus (arg2))
+	ans =
+	  simplify (MinusSymbol, arg1,
+		    ((((arg2)->u.listsxp.cdrval))->u.listsxp.carval));
+    }
+  else if (fun == DivideSymbol)
+    {
+      ans = Rf_lang3 (DivideSymbol, arg1, arg2);
+    }
+
+  return ans;
+}
+
+
+static SEXP
+D (SEXP expr, SEXP var)
+{
+  return simplify (PlusSymbol,
+		   PP (D
+		       (((((expr)->u.listsxp.cdrval))->u.listsxp.carval),
+			var)),
+		   PP (D
+		       (((((((expr)->u.listsxp.cdrval))->u.listsxp.cdrval))->
+			 u.listsxp.carval), var)));
+}
+
+SEXP
+do_D (SEXP call, SEXP op, SEXP args, SEXP env)
+{
+  SEXP expr, var;
+  var = Rf_install ();
+  expr = ((args)->u.listsxp.carval);
+  Rf_protect (expr = D (expr, var));
+  expr = AddParens (expr);
+  return expr;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42113.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42113.c
new file mode 100644
index 000000000..228c14abb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42113.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int foo (int a, int b)
+{
+  int bar = a * sizeof (int);
+
+  if (b)
+    bar += sizeof (int);
+
+  return bar;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42269-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42269-1.c
new file mode 100644
index 000000000..5d4ef1c25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42269-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "addl" } } */
+
+unsigned
+parity (unsigned x)
+{
+  x ^= x >> 16;
+  x ^= x >> 8;
+  x ^= x >> 4;
+  x &= 0xf;
+  return (0x6996 >> x) & 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42448-1.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42448-1.c
new file mode 100644
index 000000000..4e2c376e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42448-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-mcpu=21064 -O0" } */
+
+extern void abort (void);
+
+struct S2180
+{
+  char t;
+  _Complex char u[2];
+};
+
+struct S2180 s2180;
+
+int
+main (void)
+{
+  volatile struct S2180 x;
+
+  s2180.u[1] = 3 + 4i;
+
+  x.u[1] = s2180.u[1];
+
+  if (x.u[1] != s2180.u[1])
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42448-2.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42448-2.c
new file mode 100644
index 000000000..aeebad280
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42448-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-mcpu=21064 -O0" } */
+
+extern void abort (void);
+
+struct S2180
+{
+  char t;
+  _Complex char u[4];
+};
+
+struct S2180 s2180;
+
+int
+main (void)
+{
+  volatile struct S2180 x;
+
+  s2180.u[3] = 3 + 4i;
+
+  x.u[3] = s2180.u[3];
+
+  if (x.u[3] != s2180.u[3])
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42774.c b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42774.c
new file mode 100644
index 000000000..65688002b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/alpha/pr42774.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ev4" } */
+
+unsigned int ntfs_getinfo(void *p)
+{
+    char bootsect[8];
+
+    __builtin_memcpy(bootsect, p, sizeof bootsect);
+    return *(unsigned short *)(bootsect + 3);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/arc.exp b/gcc-4.9/gcc/testsuite/gcc.target/arc/arc.exp
new file mode 100644
index 000000000..ec7c7381c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/arc.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2007-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an arc target.
+if ![istarget arc*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/barrel-shifter-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/barrel-shifter-1.c
new file mode 100644
index 000000000..a0eb6d70c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/barrel-shifter-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ARC601 -mbarrel-shifter" } */
+int i;
+
+int f (void)
+{
+  i >>= 2;
+}
+
+/* { dg-final { scan-assembler "asr_s" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/barrel-shifter-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/barrel-shifter-2.c
new file mode 100644
index 000000000..97998fbf1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/barrel-shifter-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+int i;
+
+int f (void)
+{
+  i >>= 2;
+}
+
+/* { dg-final { scan-assembler "asr_s" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-1.c
new file mode 100644
index 000000000..b1990c628
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-1.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+
+extern void abort (void);
+
+/* In macros like optimized memset, we want to be able to decide what
+   alignment a passed pointer has.  */
+#define f(p) __builtin_arc_aligned (p, 4)
+
+int main (void)
+{
+  int i;
+  if (f (&i) == 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-2.c
new file mode 100644
index 000000000..d48a915b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+
+extern void abort (void);
+
+typedef struct {
+  short x;
+} mytype_t;
+
+mytype_t *__attribute__  ((noinline,weak))
+some_func (void)
+{
+  static mytype_t s;
+  return &s;
+};
+
+int main (void)
+{
+  int y, y2;
+  mytype_t *shorter = some_func();
+  y = __builtin_arc_aligned (shorter, 2);
+  if (!y)
+    abort ();
+  y2 = __builtin_arc_aligned (shorter, 4);
+  if (y2)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-3.c
new file mode 100644
index 000000000..23d80edd4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/builtin_arc_aligned-3.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+
+extern void abort (void);
+
+typedef struct {
+  int b, c;
+}
+__attribute__((aligned(32))) inner_t; // data type is 32 byte aligned
+
+typedef struct {
+  inner_t *inner;
+  int a;
+} outer_t;
+
+void __attribute__  ((noinline,weak))
+somefunc (int a, int b, int c)
+{
+  if (!a || !b || c)
+    abort ();
+};
+
+__attribute__  ((noinline,weak))
+outer_t *
+some_alloc_1 ()
+{
+  static outer_t x;
+  return &x;
+}
+
+__attribute__  ((noinline,weak))
+inner_t *
+some_alloc_2 ()
+{
+  static inner_t x;
+  return &x;
+}
+
+int main (void)
+{
+  int y, y2, y3;
+  // @p_out is pointing to instance of outer_t, naturally aligned to 4+4 = 8
+  // and not gauranteed be 32 byte aligned.
+  outer_t *p_out = some_alloc_1( ); // returns 8 byte aligned ptr
+
+  // @ptr is pointing to instance of inner_t which is naturally aligned to 32.
+  // It is assigned to p_out->inner which is of type inner_t thus 32 byte
+  // aligned as well
+  // Note that gcc can deduce p_out->inner is 32b aligned, not at runtime,
+  // because it was assigned @ptr, but even at compile time, because it's data
+  // type is naturally 32 byte aligned.
+  inner_t *ptr = some_alloc_2(); // returns 32 byte aligned ptr
+  p_out->inner = ptr; // this ptr will also be 32 byte aligned
+
+  y = __builtin_arc_aligned(ptr, 32); // this shd return 1
+  y2 = __builtin_arc_aligned(p_out->inner, 32); // this also shd return 1
+  // Although p_out->inner ptr is 32 byte aligned,
+  // it's container &(p_out->inner) need not be.
+  // That is because the hoister has no relation to contents.
+  // p_out is not gauranteed to be 32 byte
+  // aligned, so it's member @inner in p_out need not be.
+  y3 = __builtin_arc_aligned(&(p_out->inner), 32);
+  // compiler not sure, so must return 0
+
+  somefunc(y, y2, y3);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/cond-set-use.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/cond-set-use.c
new file mode 100644
index 000000000..aee27251a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/cond-set-use.c
@@ -0,0 +1,128 @@
+/* { dg-do run } */
+/* { dg-options "-Os" } */
+
+/* Based on gethostbyname_r,
+ * Copyright (C) 2000-2006 Erik Andersen <andersen@uclibc.org>
+ *
+ * Licensed under the LGPL v2.1, see the file COPYING.LIB
+ *
+ * Extraction / wrapping as test by
+ * Joern Rennecke  <joern.rennecke@embecosm.com>
+ * Copyright (C) 2013 Free Software Foundation, Inc.
+ */
+
+typedef unsigned size_t;
+typedef int ssize_t;
+typedef unsigned uint32_t;
+struct resolv_answer {
+ char *dotted;
+ int atype;
+ int aclass;
+ int ttl;
+ int rdlength;
+ const unsigned char *rdata;
+ int rdoffset;
+ char* buf;
+ size_t buflen;
+ size_t add_count;
+};
+struct hostent
+{
+  char *h_name;
+  char **h_aliases;
+  int h_addrtype;
+  int h_length;
+  char **h_addr_list;
+};
+
+int *__attribute__  ((noinline,weak)) nop (void * p) { return p; };
+void __attribute__  ((noinline,weak)) seta (struct resolv_answer * p)
+{ p->atype = 1;}
+
+int ghostbyname_r(
+  struct hostent *result_buf,
+  char *buf,
+  size_t buflen,
+  struct hostent **result,
+  int *h_errnop)
+{
+ char **addr_list;
+ char **alias;
+ char *alias0;
+ int i0;
+ struct resolv_answer a;
+ int i;
+
+ *result = ((void *)0);
+
+         *h_errnop = -1;
+
+         if ((ssize_t)buflen <= 5)
+  return 34;
+
+ alias = (char **)buf;
+ addr_list = (char **)buf;
+
+  /* This got turned into branch with conditional move in delay slot.  */
+ if ((ssize_t)buflen < 256)
+  return 34;
+
+
+ {
+  if (!nop(&i0)) {
+   result_buf->h_aliases = alias;
+   result_buf->h_addrtype = 2;
+   result_buf->h_length = 4;
+   result_buf->h_addr_list = addr_list;
+   *result = result_buf;
+   *h_errnop = 0;
+   return 0;
+  }
+ }
+
+
+ seta (&a);
+
+ if (a.atype == 1) {
+
+  int need_bytes = sizeof(addr_list[0]) * (a.add_count + 1 + 1);
+
+  int ips_len = a.add_count * a.rdlength;
+
+  buflen -= (need_bytes + ips_len);
+  if ((ssize_t)buflen < 0) {
+   i = 34;
+   goto free_and_ret;
+  }
+
+  result_buf->h_addrtype = 2;
+  *result = result_buf;
+  *h_errnop = 0;
+  i = 0;
+  goto free_and_ret;
+ }
+
+ /* For cse, the 1 was is loaded into a call-saved register;
+    the load was hoisted into a delay slot before the conditional load,
+    clobbering result_buf, which (conditionally) lived in the same
+    call-saved register, because mark_referenced_resources considered the
+    destination of the COND_EXEC only clobbered, but not used.  */
+ *h_errnop = 1;
+ *nop(&i0) = 1;
+ i = 2;
+
+ free_and_ret:
+ nop (&i0);
+ return i;
+}
+
+int
+main ()
+{
+  struct hostent buf, *res;
+  int i;
+  char c;
+  ghostbyname_r (&buf,  &c, 1024, &res, &i);
+  ghostbyname_r (&buf,  0, 1024, &res, &i);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-1.c
new file mode 100644
index 000000000..70514572e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-1.c
@@ -0,0 +1,5 @@
+void __attribute__ ((interrupt("ilink1")))
+handler1 (void)
+{
+}
+/* { dg-final { scan-assembler-times "j.*\[ilink1\]" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-2.c
new file mode 100644
index 000000000..ee8593b30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-2.c
@@ -0,0 +1,5 @@
+void __attribute__ ((interrupt("ilink2")))
+handler1 (void)
+{
+}
+/* { dg-final { scan-assembler-times "j.*\[ilink2\]" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-3.c
new file mode 100644
index 000000000..fa598d67e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/interrupt-3.c
@@ -0,0 +1,14 @@
+void __attribute__ ((interrupt))
+handler0 (void)
+{ /* { dg-error "wrong number of arguments specified" } */
+}
+
+void __attribute__ ((interrupt("you load too")))
+handler1 (void)
+{ /* { dg-warning "is not \"ilink1\" or \"ilink2\"" } */
+}
+
+void __attribute__ ((interrupt(42)))
+hander2 (void)
+{ /* { dg-warning "is not a string constant" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/jump-around-jump.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/jump-around-jump.c
new file mode 100644
index 000000000..1b4532836
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/jump-around-jump.c
@@ -0,0 +1,123 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -mlock -mswape -mrtsc -fno-reorder-blocks" } */
+
+/* This caused an ICE in arc_ifcvt when the 1->3 state change was not
+   implemented for TYPE_UNCOND_BRANCH in arc_ccfsm_post_advance.  */
+
+typedef long __kernel_long_t;
+typedef __kernel_long_t __kernel_time_t;
+
+struct timespec {
+ __kernel_time_t tv_sec;
+ long tv_nsec;
+};
+
+
+struct module;
+struct device {
+ struct device *parent;
+};
+
+struct rtc_time {
+ int tm_sec;
+ int tm_min;
+ int tm_hour;
+ int tm_mday;
+ int tm_mon;
+ int tm_year;
+ int tm_wday;
+ int tm_yday;
+ int tm_isdst;
+};
+struct rtc_wkalrm {
+ unsigned char enabled;
+ unsigned char pending;
+ struct rtc_time time;
+};
+
+struct rtc_class_ops {
+ int (*open)(struct device *);
+ void (*release)(struct device *);
+ int (*ioctl)(struct device *, unsigned int, unsigned long);
+ int (*read_time)(struct device *, struct rtc_time *);
+ int (*set_time)(struct device *, struct rtc_time *);
+ int (*read_alarm)(struct device *, struct rtc_wkalrm *);
+ int (*set_alarm)(struct device *, struct rtc_wkalrm *);
+  //int (*proc)(struct device *, struct seq_file *);
+ int (*set_mmss)(struct device *, unsigned long secs);
+ int (*read_callback)(struct device *, int data);
+ int (*alarm_irq_enable)(struct device *, unsigned int enabled);
+};
+
+struct rtc_device
+{
+ struct device dev;
+ struct module *owner;
+
+ int id;
+ char name[20];
+
+ const struct rtc_class_ops *ops;
+  // struct mutex ops_lock;
+
+  // struct cdev char_dev;
+ unsigned long flags;
+
+ unsigned long irq_data;
+  //spinlock_t irq_lock;
+  //wait_queue_head_t irq_queue;
+  //struct fasync_struct *async_queue;
+
+  //struct rtc_task *irq_task;
+  //spinlock_t irq_task_lock;
+ int irq_freq;
+ int max_user_freq;
+
+  //struct timerqueue_head timerqueue;
+  //struct rtc_timer aie_timer;
+  //struct rtc_timer uie_rtctimer;
+  //struct hrtimer pie_timer;
+ int pie_enabled;
+  //struct work_struct irqwork;
+
+ int uie_unsupported;
+
+
+  //struct work_struct uie_task;
+  //struct timer_list uie_timer;
+
+ unsigned int oldsecs;
+ unsigned int uie_irq_active:1;
+ unsigned int stop_uie_polling:1;
+ unsigned int uie_task_active:1;
+ unsigned int uie_timer_active:1;
+
+};
+
+extern void rtc_time_to_tm(unsigned long time, struct rtc_time *tm);
+extern struct rtc_device *rtc_class_open(const char *name);
+extern void rtc_class_close(struct rtc_device *rtc);
+
+
+int rtc_set_ntp_time(struct timespec now)
+{
+ struct rtc_device *rtc;
+ struct rtc_time tm;
+ int err = -19;
+
+ if (now.tv_nsec < (1000000000L >> 1))
+  rtc_time_to_tm(now.tv_sec, &tm);
+ else
+  rtc_time_to_tm(now.tv_sec + 1, &tm);
+
+ rtc = rtc_class_open("rtc0");
+ if (rtc) {
+
+
+  if (rtc->ops && (rtc->ops->set_time || rtc->ops->set_mmss))
+   err = rtc_set_time(rtc, &tm);
+  rtc_class_close(rtc);
+ }
+
+ return err;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/long-calls.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/long-calls.c
new file mode 100644
index 000000000..63fafbcc6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/long-calls.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-calls" } */
+
+int g (void);
+
+int f (void)
+{
+        g();
+}
+
+/* { dg-final { scan-assembler "j @g" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mA6.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mA6.c
new file mode 100644
index 000000000..2e15a86f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mA6.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mA6" } */
+
+/* { dg-final { scan-assembler ".cpu ARC600" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mA7.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mA7.c
new file mode 100644
index 000000000..c4430f43b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mA7.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mA7" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC600.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC600.c
new file mode 100644
index 000000000..20e086aa7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC600.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mARC600" } */
+
+/* { dg-final { scan-assembler ".cpu ARC600" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC601.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC601.c
new file mode 100644
index 000000000..1d30da4ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC601.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mARC601" } */
+
+/* { dg-final { scan-assembler ".cpu ARC601" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC700.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC700.c
new file mode 100644
index 000000000..43e9baa3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mARC700.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mARC700" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc600.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc600.c
new file mode 100644
index 000000000..4c915fda0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc600.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ARC600" } */
+
+/* { dg-final { scan-assembler ".cpu ARC600" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc601.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc601.c
new file mode 100644
index 000000000..7c93c9dc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc601.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ARC601" } */
+
+/* { dg-final { scan-assembler ".cpu ARC601" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc700.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc700.c
new file mode 100644
index 000000000..c805a5af7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mcpu-arc700.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ARC700" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mcrc.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mcrc.c
new file mode 100644
index 000000000..d3780bb00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mcrc.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mcrc" } */
+/* { dg-do assemble } */
+
+int f (int i)
+{
+  __asm__("crc %1, %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mdpfp.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mdpfp.c
new file mode 100644
index 000000000..4bbc9057b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mdpfp.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdpfp" } */
+
+double i;
+
+int f (void)
+{
+        i *= 2.0;
+}
+
+/* { dg-final { scan-assembler "daddh" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mdsp-packa.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mdsp-packa.c
new file mode 100644
index 000000000..f013a6dd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mdsp-packa.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mdsp-packa" } */
+/* { dg-do assemble } */
+
+int f (int i)
+{
+  __asm__("minidl %1, %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mdvbf.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mdvbf.c
new file mode 100644
index 000000000..e2e545e8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mdvbf.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mdvbf" } */
+/* { dg-do assemble } */
+
+int f (int i)
+{
+  __asm__("vbfdw %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mlock.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mlock.c
new file mode 100644
index 000000000..3a8b050c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mlock.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mlock" } */
+/* { dg-do assemble } */
+
+int f (void *p)
+{
+  int i;
+
+  __asm__("llock %0, [%1]\n\t"
+	  "scond %0, [%1]" : "=&r"(i) : "r"(p));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mmac-24.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mmac-24.c
new file mode 100644
index 000000000..30cb6981a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mmac-24.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mmac-24" } */
+/* { dg-do assemble } */
+
+int f (int i)
+{
+  __asm__("mult %1, %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mmac-d16.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mmac-d16.c
new file mode 100644
index 000000000..0570011fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mmac-d16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mmac-d16" } */
+/* { dg-do assemble } */
+
+int f (int i)
+{
+  __asm__("muldw %1, %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-crc.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-crc.c
new file mode 100644
index 000000000..70ab9c117
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-crc.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-crc" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+int f (int i)
+{
+  __asm__("crc %1, %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-dsp-packa.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-dsp-packa.c
new file mode 100644
index 000000000..eb21522af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-dsp-packa.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-dsp-packa" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+int f (int i)
+{
+  __asm__("minidl %1, %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-dvbf.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-dvbf.c
new file mode 100644
index 000000000..ea96d987c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-dvbf.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-dvbf" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+int f (int i)
+{
+  __asm__("vbfdw %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-lock.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-lock.c
new file mode 100644
index 000000000..62ac885ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-lock.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-lock" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+int f (void *p)
+{
+  int i;
+
+  __asm__("llock %0, [%1]\n\t"
+	  "scond %0, [%1]" : "=&r"(i) : "r"(p));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-mac-24.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-mac-24.c
new file mode 100644
index 000000000..b4839579b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-mac-24.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-mac-24" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+int f (int i)
+{
+  __asm__("mult %1, %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-mac-d16.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-mac-d16.c
new file mode 100644
index 000000000..68a20f4f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-mac-d16.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-mac-d16" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+int f (int i)
+{
+  __asm__("muldw %1, %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-rtsc.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-rtsc.c
new file mode 100644
index 000000000..d74a60e93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-rtsc.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-rtsc" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+int f (int i)
+{
+  __asm__("rtsc %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-swape.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-swape.c
new file mode 100644
index 000000000..c853ab4bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-swape.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-swape" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+int f (int i)
+{
+  __asm__("swape %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-xy.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-xy.c
new file mode 100644
index 000000000..e378b3fc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mno-xy.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-xy" } */
+/* Would also like to assemble and check that we get the expected
+   "Error: bad instruction" assembler messages, but at the moment our
+   testharness can't do that.  */
+
+void f (int i)
+{
+  __asm__("add x0_u0, x0_u0, %0" : :  "r" (i));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mrtsc.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mrtsc.c
new file mode 100644
index 000000000..31852a5e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mrtsc.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtsc" } */
+/* { dg-do assemble } */
+
+int f (int i)
+{
+  __asm__("rtsc %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mspfp.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mspfp.c
new file mode 100644
index 000000000..0e41ff89d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mspfp.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mspfp" } */
+
+float i;
+
+int f (void)
+{
+        i *= 2.0;
+}
+
+/* { dg-final { scan-assembler "fadd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mswape.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mswape.c
new file mode 100644
index 000000000..692e6a2bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mswape.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mswape" } */
+/* { dg-do assemble } */
+
+int f (int i)
+{
+  __asm__("swape %1, %1" : "=r"(i) : "r"(i));
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC600.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC600.c
new file mode 100644
index 000000000..a483d1435
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC600.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=ARC600" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC601.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC601.c
new file mode 100644
index 000000000..ed57bd709
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC601.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=ARC601" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC700-xmac b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC700-xmac
new file mode 100644
index 000000000..2f1e137be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC700-xmac
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=ARC700-xmac" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC700.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC700.c
new file mode 100644
index 000000000..851ea7305
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC700.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=ARC700" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC725D.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC725D.c
new file mode 100644
index 000000000..e2aa48462
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC725D.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=ARC725D" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC750D.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC750D.c
new file mode 100644
index 000000000..20923300e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mtune-ARC750D.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=ARC750D" } */
+
+/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mul64.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mul64.c
new file mode 100644
index 000000000..3678b2799
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mul64.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ARC600 -mmul64" } */
+#include <stdint.h>
+
+int64_t i;
+int j, k;
+
+int f (void)
+{
+        i = j * k;
+}
+
+/* { dg-final { scan-assembler "mul64" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mulsi3_highpart-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mulsi3_highpart-1.c
new file mode 100644
index 000000000..398ecfe94
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mulsi3_highpart-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mARC700 --save-temps" } */
+
+#include <stdlib.h>
+
+/* Hide value propagation from the optimizers.  */
+static int
+id (int i)
+{
+  asm ("": "+Xr" (i));
+  return i;
+}
+
+static int
+mulhigh (unsigned a, unsigned b)
+{
+  return (unsigned long long) a * b >> 32;
+}
+
+int
+main (void)
+{
+  if (mulhigh (id (0x12345678), id (0x90abcdef)) != 0xa49a83e)
+    abort ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler "mpyhu\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c
new file mode 100644
index 000000000..ccc74e7b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mulsi3_highpart-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mARC700 --save-temps -mno-mpy" } */
+
+#include <stdlib.h>
+
+/* Hide value propagation from the optimizers.  */
+static int
+id (int i)
+{
+  asm ("": "+Xr" (i));
+  return i;
+}
+
+static int
+mulhigh (unsigned a, unsigned b)
+{
+  return (unsigned long long) a * b >> 32;
+}
+
+int
+main (void)
+{
+  if (mulhigh (id (0x12345678), id (0x90abcdef)) != 0xa49a83e)
+    abort ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "mpyhu\[ \t\]" } } */
+/* { dg-final { scan-assembler-not "@__muldi3" } } */
+/* { dg-final { scan-assembler "@__umulsi3_highpart" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/mxy.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/mxy.c
new file mode 100644
index 000000000..1ecc34d2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/mxy.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mxy" } */
+/* { dg-do assemble } */
+
+void f (int i)
+{
+  __asm__("add x0_u0, x0_u0, %0" : :  "r" (i));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/no-dpfp-lrsr.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/no-dpfp-lrsr.c
new file mode 100644
index 000000000..e4e23e4a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/no-dpfp-lrsr.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdpfp -mno-dpfp-lrsr" } */
+
+double i;
+
+int f (void)
+{
+        i *= 2.0;
+}
+
+/* { dg-final { scan-assembler-not "\tlr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/nv-cache.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/nv-cache.c
new file mode 100644
index 000000000..968719598
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/nv-cache.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-volatile-cache" } */
+
+volatile int i;
+void f (void)
+{
+  i = 0;
+}
+/* { dg-final { scan-assembler "st\.di" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/sdata-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/sdata-1.c
new file mode 100644
index 000000000..3d8366c15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/sdata-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msdata" } */
+
+int i;
+
+int f (void)
+{
+  return i;
+}
+/* { dg-final { scan-assembler "@sda" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/sdata-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/sdata-2.c
new file mode 100644
index 000000000..ebaa25e72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/sdata-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-sdata" } */
+
+int i;
+
+int f (void)
+{
+  return i;
+}
+/* { dg-final { scan-assembler-not "@sda" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arc/v-cache.c b/gcc-4.9/gcc/testsuite/gcc.target/arc/v-cache.c
new file mode 100644
index 000000000..7722c4335
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arc/v-cache.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mvolatile-cache" } */
+
+volatile int i;
+void f (void)
+{
+  i = 0;
+}
+/* { dg-final { scan-assembler-not "st\.di" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20030909-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20030909-1.c
new file mode 100644
index 000000000..4ed3640b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20030909-1.c
@@ -0,0 +1,5 @@
+/* Verify that ands are combined.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler-not "#255.*#255" } } */
+int f(int a, int b) { return ((a & 0xff) + (b & 0xff)) & 0xff; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20031108-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20031108-1.c
new file mode 100644
index 000000000..d9b6006f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20031108-1.c
@@ -0,0 +1,36 @@
+/* PR optimization/10467  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-options "-O2 -mthumb" } */
+
+typedef enum {Ident_1} Enumeration;
+
+typedef struct record
+{
+    struct record *Ptr_Comp;
+    Enumeration Discr;
+    union {
+	struct {
+	    Enumeration Enum_Comp;
+	    int Int_Comp;
+	    char Str_Comp [31];
+        } var_1;
+    } variant;
+} *Rec_Pointer;
+
+Rec_Pointer Ptr_Glob;
+
+Proc_1 (Ptr_Val_Par)
+    Rec_Pointer Ptr_Val_Par;
+{
+    Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;
+
+    *Ptr_Val_Par->Ptr_Comp = *Ptr_Glob;
+
+    if (Next_Record->Discr == Ident_1)
+    {
+	Proc_7 (Next_Record->variant.var_1.Int_Comp, 10,
+		&Next_Record->variant.var_1.Int_Comp);
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20051215-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20051215-1.c
new file mode 100644
index 000000000..0519dc7ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20051215-1.c
@@ -0,0 +1,36 @@
+/* ARM's load-and-call patterns used to allow automodified addresses.
+   This was wrong, because if the modified register were spilled,
+   the call would need an output reload.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+extern void abort (void);
+typedef void (*callback) (void);
+
+static void
+foo (callback *first, callback *p)
+{
+  while (p > first)
+    {
+      (*--p) ();
+#ifndef __thumb__
+      asm ("" : "=r" (p) : "0" (p)
+	   : "r4", "r5", "r6", "r7", "r8", "r9", "r10");
+#endif
+    }   
+}
+
+static void
+dummy (void)
+{
+  static int count;
+  if (count++ == 1)
+    abort ();
+}
+
+int
+main (void)
+{
+  callback list[1] = { dummy };
+  foo (&list[0], &list[1]);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20090811-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20090811-1.c
new file mode 100644
index 000000000..d82060126
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20090811-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */
+/* { dg-skip-if "do not override -mcpu" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-a8" } } */
+/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=softfp" } } */
+/* { dg-options "-O3 -mcpu=cortex-a8 -mfpu=vfp3 -mfloat-abi=softfp" } */
+
+typedef struct cb
+{
+  int cxc;
+  short int pside;
+}  *CBPTR;
+typedef struct rwb
+{
+  int stx;
+} RWB;
+extern CBPTR *car;
+extern RWB *rwAr;
+extern int nts;
+extern int nRws;
+void f()
+{
+  CBPTR pptr ;
+  int  k_lt, k_rt, k_span, rw, p, rt;
+  int sa ;
+  k_rt = 0;
+  k_lt = 10000000;
+  for (rw = 1; rw <= nRws; rw++)
+    k_lt = rwAr[rw].stx;
+  k_span = k_rt - k_lt;
+  for (; p <= nts; p++)
+    {
+      pptr = car[p];
+      if (pptr->pside == 3)
+        pptr->cxc += (int)(((double)rt / (double) k_span) *((double) sa));
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/20131120.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/20131120.c
new file mode 100644
index 000000000..c370ae60c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/20131120.c
@@ -0,0 +1,14 @@
+/* Check that CONST_INT is not forced into REG before PLUS.  */
+/* { dg-do compile { target { arm_arm_ok || arm_thumb2_ok} } } */
+/* { dg-options "-O2 -fdump-rtl-expand" } */
+
+typedef int Arr2[50][50];
+
+void
+foo (Arr2 a2, int i)
+{
+  a2[i+20][i] = 1;
+}
+
+/* { dg-final { scan-rtl-dump-not "\\\(set \\\(reg:SI \[0-9\]*\\\)\[\n\r\]+\[ \t]*\\\(const_int 4000" "expand" } } */
+/* { dg-final { cleanup-rtl-dump "expand" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp
new file mode 100644
index 000000000..746429dad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an ARM target.
+if ![istarget arm*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/abitest.h b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/abitest.h
new file mode 100644
index 000000000..06a92c3ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/abitest.h
@@ -0,0 +1,125 @@
+
+#define IN_FRAMEWORK
+
+#ifdef VFP
+#define D0	0
+#define D1	8
+#define D2	16
+#define D3	24
+#define D4	32
+#define D5	40
+#define D6	48
+#define D7	56
+
+#ifdef NEON
+#define Q0      D0
+#define Q1      D2
+#define Q2      D4
+#define Q3      D6
+#endif
+
+#define S0	64
+#define S1	68
+#define S2	72
+#define S3	76
+#define S4	80
+#define S5	84
+#define S6	88
+#define S7	92
+#define S8      86
+#define S9	100
+#define S10	104
+#define S11	108
+#define S12	112
+#define S13	116
+#define S14	120
+#define S15	124
+
+#define CORE_REG_START 128
+#else
+#define CORE_REG_START 0
+#endif
+
+#define R0	CORE_REG_START
+#define R1	(R0 + 4)
+#define R2	(R1 + 4)
+#define R3	(R2 + 4)
+#define STACK	(R3 + 4)
+
+
+
+extern void abort (void);
+
+__attribute__((naked))  void dumpregs () __asm("myfunc");
+__attribute__((naked))  void dumpregs ()
+{
+  asm(
+      "mov	ip, sp\n\t"
+      "stmfd	sp!, {r0-r3}\n\t"
+#ifdef VFP
+      "fstmdbs	sp!, {s0-s15}\n\t"
+      "fstmdbd	sp!, {d0-d7}\n\t"
+#endif
+      "mov	r0, sp\n\t"
+      "stmfd	sp!, {ip, r14}\n\t"
+      "bl	testfunc\n\t"
+      "ldmfd	sp!, {r0, r14}\n\t"
+      "mov	sp, r0\n\t"
+      "bx	lr");
+}
+
+
+#define LAST_ARG(type,val,offset) { type __x = val; if (memcmp(&__x, stack+offset, sizeof(type)) != 0) abort(); }
+#define ARG(type,val,offset) LAST_ARG(type, val, offset)
+#define ANON(type,val,offset) LAST_ARG(type, val, offset)
+#define LAST_ANON(type,val,offset) LAST_ARG(type, val, offset)
+#define DOTS
+
+void testfunc(char* stack)
+{
+#include TESTFILE
+  return;
+}
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#define LAST_ARG(type,val,offset) type
+#define ARG(type,val,offset) LAST_ARG(type, val, offset),
+#define DOTS ...
+#define ANON(type,val, offset)
+#define LAST_ANON(type,val, offset)
+
+#ifndef MYFUNCTYPE
+#define MYFUNCTYPE void
+#endif
+
+#ifndef PCSATTR
+#define PCSATTR
+#endif
+
+MYFUNCTYPE myfunc(
+#include TESTFILE
+) PCSATTR;
+
+#undef LAST_ARG
+#undef ARG
+#undef DOTS
+#undef ANON
+#undef LAST_ANON
+#define LAST_ARG(type,val,offset) val
+#define ARG(type,val,offset) LAST_ARG(type, val, offset),
+#define DOTS
+#define LAST_ANON(type,val,offset) LAST_ARG(type, val, offset)
+#define ANON(type,val,offset) LAST_ARG(type, val, offset),
+
+
+int main()
+{
+  myfunc(
+#include TESTFILE
+);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h
new file mode 100644
index 000000000..08b75f7b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-constants.h
@@ -0,0 +1,33 @@
+
+
+#include "arm_neon.h"
+
+const int32x4_t i32x4_constvec1 = { 1101, 1102, 1103, 1104};
+const int32x4_t i32x4_constvec2 = { 2101, 2102, 2103, 2104};
+
+#define ELEM(INDEX) .val[INDEX]
+
+const int32x4x2_t i32x4x2_constvec1 =   {ELEM(0) = {0xaddebccb,11,12,13}, 
+					 ELEM(1) = {14, 15, 16, 17} };
+
+const int32x4x2_t i32x4x2_constvec2 = { ELEM(0) = {0xaadebcca,11,12,13}, 
+			                ELEM(1) = {140, 15, 16, 17}};
+
+const int32x4x3_t i32x4x3_constvec1 = { ELEM(0) = {0xabbccdde,8, 9, 10},
+					ELEM(1) = {0xabcccdde, 26, 27, 28},
+			                ELEM(2) = {0xaccccddf, 29, 30, 31}};
+
+const int32x4x3_t i32x4x3_constvec2 = { ELEM(0) = {0xbccccdd0,8, 9, 10},
+					ELEM(1) = {0xbdfe1000, 26, 27, 28},
+			                ELEM(2) = {0xaccccddf, 29, 30, 31}};
+const float32x4x2_t f32x4x2_constvec1 =
+  { ELEM(0) = { 7.101f, 0.201f, 0.301f, 0.401f} ,
+    ELEM(1) = { 8.101f, 0.501f, 0.601f, 0.701f} };
+
+const float32x4x2_t f32x4x2_constvec2 = 
+  { ELEM(0) = { 11.99f , 11.21f, 1.27f, 8.74f},
+    ELEM(1) = { 13.45f , 1.23f ,1.24f, 1.26f}};
+
+const int32x2_t i32x2_constvec1 = { 1283, 1345 };
+const int32x2x2_t i32x2x2_constvec1 = { ELEM(0) = { 0xabcdefab, 32 },
+					ELEM(1) = { 0xabcdefbc, 33 }};
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c
new file mode 100644
index 000000000..47ae2f65f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect1.c
@@ -0,0 +1,27 @@
+/* Test AAPCS layout (VFP variant for Neon types) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok  } */
+/* { dg-require-effective-target arm_neon_ok  } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-add-options arm_neon } */
+
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define NEON
+#define TESTFILE "neon-vect1.c"
+#include "neon-constants.h"
+
+
+#include "abitest.h"
+#else
+
+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
+ARG(float, 3.0f, S4) /* D2, Q1 */
+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
+ARG(double, 12.0, D3) /* Backfill this particular argument.  */
+ARG(int32x4x2_t, i32x4x2_constvec2, STACK) 
+ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed.  */
+LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c
new file mode 100644
index 000000000..f7b532a3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect2.c
@@ -0,0 +1,23 @@
+/* Test AAPCS layout (VFP variant for Neon types) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-add-options arm_neon } */
+
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define NEON
+#define TESTFILE "neon-vect2.c"
+#include "neon-constants.h"
+
+
+#include "abitest.h"
+#else
+
+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1.  */
+ARG(float, 3.0f, S4) /* D2, Q1 occupied.  */
+LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c
new file mode 100644
index 000000000..e5426b0ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect3.c
@@ -0,0 +1,26 @@
+/* Test AAPCS layout (VFP variant for Neon types) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-add-options arm_neon } */
+
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define NEON
+#define TESTFILE "neon-vect3.c"
+#include "neon-constants.h"
+
+
+#include "abitest.h"
+#else
+
+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
+ARG(float, 3.0f, S4) /* D2, Q1 */
+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
+ARG(int32x4x2_t, i32x4x2_constvec2, STACK) 
+ARG(double, 11.0, STACK+sizeof(int32x4x2_t)) /* No backfill in D3.  */
+LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c
new file mode 100644
index 000000000..96bd09c45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect4.c
@@ -0,0 +1,27 @@
+/* Test AAPCS layout (VFP variant for Neon types) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok  } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-add-options arm_neon } */
+
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define NEON
+#define TESTFILE "neon-vect4.c"
+#include "neon-constants.h"
+
+
+#include "abitest.h"
+#else
+
+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
+ARG(float, 3.0f, S4) /* D2, Q1 */
+ARG(int32x4x2_t, i32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
+ARG(double, 12.0, D3) /* Backfill this particular argument.  */
+ARG(float, 5.0f, S5) /* Backfill in S5.  */
+ARG(int32x4x2_t, i32x4x2_constvec2, STACK) 
+LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c
new file mode 100644
index 000000000..59e58c96c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect5.c
@@ -0,0 +1,28 @@
+/* Test AAPCS layout (VFP variant for Neon types) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-add-options arm_neon } */
+
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define NEON
+#define TESTFILE "neon-vect5.c"
+#include "neon-constants.h"
+
+
+#include "abitest.h"
+#else
+
+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
+ARG(float, 3.0f, S4) /* D2, Q1 */
+ARG(float32x4x2_t, f32x4x2_constvec1, Q2) /* Q2, Q3 - D4-D6 , s5-s12 */
+ARG(double, 12.0, D3) /* Backfill this particular argument.  */
+ARG(int32x4x2_t, i32x4x2_constvec2, STACK) 
+ARG(float, 5.0f, STACK+sizeof(int32x4x2_t)) /* No backfill allowed.  */
+LAST_ARG(int, 3, R0)
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c
new file mode 100644
index 000000000..fcb399882
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect6.c
@@ -0,0 +1,24 @@
+/* Test AAPCS layout (VFP variant for Neon types) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-add-options arm_neon } */
+
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define NEON
+#define TESTFILE "neon-vect6.c"
+#include "neon-constants.h"
+
+
+#include "abitest.h"
+#else
+
+ARG(int32x4_t, i32x4_constvec2, Q0) /* D0, D1 */
+ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3  */
+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
+LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c
new file mode 100644
index 000000000..f8d1d0730
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect7.c
@@ -0,0 +1,27 @@
+/* Test AAPCS layout (VFP variant for Neon types) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-add-options arm_neon } */
+
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define NEON
+#define TESTFILE "neon-vect7.c"
+#include "neon-constants.h"
+
+
+#include "abitest.h"
+#else
+
+ARG(float, 24.3f, S0) /* S0 , D0, Q0 */
+ARG(int32x4x3_t, i32x4x3_constvec1, Q1) /* Q1, Q2, Q3  */
+ARG(double, 25.6, D1)
+ARG(float, 12.67f, S1)
+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
+ARG(double, 2.47, STACK+sizeof(int32x4x3_t))
+LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c
new file mode 100644
index 000000000..f2c295d84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/neon-vect8.c
@@ -0,0 +1,27 @@
+/* Test AAPCS layout (VFP variant for Neon types) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-add-options arm_neon } */
+
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define NEON
+#define TESTFILE "neon-vect8.c"
+#include "neon-constants.h"
+
+
+#include "abitest.h"
+#else
+
+ARG(float, 24.3f, S0) /* S0 , D0, Q0 */
+ARG(int32x2_t, i32x2_constvec1, D1) /* D1  */
+ARG(double, 25.6, D2)
+ARG(float, 12.67f, S1)
+ARG(int32x4x3_t, i32x4x3_constvec2, STACK)
+ARG(double, 2.47, STACK+sizeof(int32x4x3_t))
+LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c
new file mode 100644
index 000000000..9fb926dbd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c
@@ -0,0 +1,17 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp1.c"
+#include "abitest.h"
+
+#else
+  ARG(int, 4, R0)
+  ARG(double, 4.0, D0)
+  LAST_ARG(int, 3, R1)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c
new file mode 100644
index 000000000..c3a1b39a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c
@@ -0,0 +1,38 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp10.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  /* A variadic function passes using the base ABI */
+  ARG(double, 11.0, R0)
+  DOTS
+  ANON(struct z, a, R2)
+  ANON(struct z, b, STACK+24)
+  LAST_ANON(double, 0.5, STACK+56)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c
new file mode 100644
index 000000000..a496a3ed5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c
@@ -0,0 +1,39 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp11.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#define MYFUNCTYPE struct y
+
+#include "abitest.h"
+#else
+  ARG(int, 7, R1)
+  ARG(struct y, v, R2)
+  ARG(struct z, a, D0)
+  ARG(struct z, b, D4)
+  LAST_ARG(double, 0.5, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c
new file mode 100644
index 000000000..bbfa3df90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c
@@ -0,0 +1,38 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp12.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 7, R0)
+  ARG(struct y, v, R1)
+  ARG(struct z, a, D0)
+  ARG(double, 1.0, D4)
+  ARG(struct z, b, STACK+8)
+  LAST_ARG(double, 0.5, STACK+40)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c
new file mode 100644
index 000000000..a46361c09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c
@@ -0,0 +1,39 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp13.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 7, R0)
+  ARG(int, 9, R1)
+  ARG(struct z, a, D0)
+  ARG(double, 1.0, D4)
+  ARG(struct z, b, STACK)
+  ARG(int, 4, R2)
+  LAST_ARG(double, 0.5, STACK+32)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c
new file mode 100644
index 000000000..43c19f2dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c
@@ -0,0 +1,24 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp14.c"
+
+#include "abitest.h"
+#else
+  ARG(double, 1.0, D0)
+  ARG(double, 2.0, D1)
+  ARG(double, 3.0, D2)
+  ARG(double, 4.0, D3)
+  ARG(double, 5.0, D4)
+  ARG(double, 6.0, D5)
+  ARG(double, 7.0, D6)
+  ARG(double, 8.0, D7)
+  ARG(double, 9.0, STACK)
+  LAST_ARG(double, 10.0, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c
new file mode 100644
index 000000000..c98ca3810
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp15.c
@@ -0,0 +1,20 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp15.c"
+
+#define PCSATTR __attribute__((pcs("aapcs")))
+
+#include "abitest.h"
+#else
+  ARG(double, 1.0, R0)
+  ARG(double, 2.0, R2)
+  ARG(double, 3.0, STACK)
+  LAST_ARG(double, 4.0, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c
new file mode 100644
index 000000000..956bc0ab5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp16.c
@@ -0,0 +1,22 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp16.c"
+
+#define PCSATTR __attribute__((pcs("aapcs")))
+
+#include "abitest.h"
+#else
+  ARG(float, 1.0f, R0)
+  ARG(float, 2.0f, R1)
+  ARG(float, 3.0f, R2)
+  ARG(float, 4.0f, R3)
+  ARG(float, 5.0f, STACK)
+  LAST_ARG(float, 5.0f, STACK+4)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c
new file mode 100644
index 000000000..9044ec221
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp17.c
@@ -0,0 +1,20 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp17.c"
+
+#define PCSATTR __attribute__((pcs("aapcs")))
+
+#include "abitest.h"
+#else
+  ARG(float, 1.0f, R0)
+  ARG(double, 2.0, R2)
+  ARG(float, 3.0f, STACK)
+  LAST_ARG(double, 4.0, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c
new file mode 100644
index 000000000..bfe90675b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c
@@ -0,0 +1,19 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp2.c"
+#include "abitest.h"
+
+#else
+  ARG(float, 1.0f, S0)
+  ARG(double, 4.0, D1)
+  ARG(float, 2.0f, S1)
+  ARG(double, 5.0, D2)
+  LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c
new file mode 100644
index 000000000..0e645d711
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c
@@ -0,0 +1,21 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp3.c"
+
+__complex__ x = 1.0+2.0i;
+
+#include "abitest.h"
+#else
+  ARG(float, 1.0f, S0)
+  ARG(__complex__ double, x, D1)
+  ARG(float, 2.0f, S1)
+  ARG(double, 5.0, D3)
+  LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c
new file mode 100644
index 000000000..46dc4b98a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c
@@ -0,0 +1,20 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp4.c"
+
+__complex__ float x = 1.0f + 2.0fi;
+#include "abitest.h"
+#else
+  ARG(float, 1.0f, S0)
+  ARG(__complex__ float, x, S1)
+  ARG(float, 2.0f, S3)
+  ARG(double, 5.0, D2)
+  LAST_ARG(int, 3, R0)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c
new file mode 100644
index 000000000..216d98ea8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c
@@ -0,0 +1,30 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp5.c"
+
+__complex__ float x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+#include "abitest.h"
+#else
+  ARG(float, 1.0f, S0)
+  ARG(__complex__ float, x, S1)
+  ARG(float, 2.0f, S3)
+  ARG(double, 5.0, D2)
+  ARG(struct y, v, R0)
+  LAST_ARG(int, 3, STACK)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c
new file mode 100644
index 000000000..4d718da45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c
@@ -0,0 +1,30 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp6.c"
+
+__complex__ float x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+#include "abitest.h"
+#else
+  ARG(struct y, v, R0)
+  ARG(float, 1.0f, S0)
+  ARG(__complex__ float, x, S1)
+  ARG(float, 2.0f, S3)
+  ARG(double, 5.0, D2)
+  LAST_ARG(int, 3, STACK)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c
new file mode 100644
index 000000000..3e57e45c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c
@@ -0,0 +1,37 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp7.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(struct z, a, D0)
+  ARG(struct z, b, D4)
+  ARG(double, 0.5, STACK)
+  ARG(int, 7, R0)
+  LAST_ARG(struct y, v, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c
new file mode 100644
index 000000000..e55006885
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c
@@ -0,0 +1,37 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp8.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  ARG(int, 7, R0)
+  ARG(struct y, v, R1)
+  ARG(struct z, a, D0)
+  ARG(struct z, b, D4)
+  LAST_ARG(double, 0.5, STACK+8)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c
new file mode 100644
index 000000000..c2be6bf4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c
@@ -0,0 +1,38 @@
+/* Test AAPCS layout (VFP variant) */
+
+/* { dg-do run { target arm*-*-*eabi* } } */
+/* { dg-require-effective-target arm_hard_vfp_ok } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
+
+#ifndef IN_FRAMEWORK
+#define VFP
+#define TESTFILE "vfp9.c"
+
+__complex__ x = 1.0+2.0i;
+
+struct y
+{
+  int p;
+  int q;
+  int r;
+  int s;
+} v = { 1, 2, 3, 4 };
+
+struct z
+{
+  double x[4];
+};
+
+struct z a = { 5.0, 6.0, 7.0, 8.0 };
+struct z b = { 9.0, 10.0, 11.0, 12.0 };
+
+#include "abitest.h"
+#else
+  /* A variadic function passes using the base ABI */
+  ARG(int, 7, R0)
+  DOTS
+  ANON(struct z, a, R2)
+  ANON(struct z, b, STACK+24)
+  LAST_ANON(double, 0.5, STACK+56)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/acle.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/acle.exp
new file mode 100644
index 000000000..c8622697e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/acle.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 2013-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an ARM target.
+if ![istarget arm*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32b.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32b.c
new file mode 100644
index 000000000..d6f35e9fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32b.c
@@ -0,0 +1,20 @@
+/* Test the crc32b ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32b (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint8_t arg1_uint8_t;
+
+  out_uint32_t = __crc32b (arg0_uint32_t, arg1_uint8_t);
+}
+
+/* { dg-final { scan-assembler "crc32b\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cb.c
new file mode 100644
index 000000000..44aea21fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cb.c
@@ -0,0 +1,20 @@
+/* Test the crc32cb ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32cb (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint8_t arg1_uint8_t;
+
+  out_uint32_t = __crc32cb (arg0_uint32_t, arg1_uint8_t);
+}
+
+/* { dg-final { scan-assembler "crc32cb\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cd.c
new file mode 100644
index 000000000..cb7ee0df0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cd.c
@@ -0,0 +1,20 @@
+/* Test the crc32cd ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32cd (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint64_t arg1_uint64_t;
+
+  out_uint32_t = __crc32cd (arg0_uint32_t, arg1_uint64_t);
+}
+
+/* { dg-final { scan-assembler-times "crc32cw\t...?, ...?, ...?\n" 2 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32ch.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32ch.c
new file mode 100644
index 000000000..d8e733894
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32ch.c
@@ -0,0 +1,20 @@
+/* Test the crc32ch ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32ch (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint32_t = __crc32ch (arg0_uint32_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "crc32ch\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cw.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cw.c
new file mode 100644
index 000000000..84384c5d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32cw.c
@@ -0,0 +1,20 @@
+/* Test the crc32cw ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32cw (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32_t = __crc32cw (arg0_uint32_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "crc32cw\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32d.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32d.c
new file mode 100644
index 000000000..c90fad9a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32d.c
@@ -0,0 +1,20 @@
+/* Test the crc32d ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32d (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint64_t arg1_uint64_t;
+
+  out_uint32_t = __crc32d (arg0_uint32_t, arg1_uint64_t);
+}
+
+/* { dg-final { scan-assembler-times "crc32w\t...?, ...?, ...?\n" 2 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32h.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32h.c
new file mode 100644
index 000000000..c21a4ae3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32h.c
@@ -0,0 +1,20 @@
+/* Test the crc32h ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32h (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint32_t = __crc32h (arg0_uint32_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "crc32h\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32w.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32w.c
new file mode 100644
index 000000000..60cd09e4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/acle/crc32w.c
@@ -0,0 +1,20 @@
+/* Test the crc32w ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crc_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crc } */
+
+#include "arm_acle.h"
+
+void test_crc32w (void)
+{
+  uint32_t out_uint32_t;
+  uint32_t arg0_uint32_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32_t = __crc32w (arg0_uint32_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "crc32w\t...?, ...?, ...?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt.c
new file mode 100644
index 000000000..cd0d08386
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+unsigned long long
+muld (unsigned long long X, unsigned long long Y)
+{
+  unsigned long long mask = 0xffffffffull;
+  return (X & mask) * (Y & mask);
+}
+
+/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt2.c
new file mode 100644
index 000000000..efe71f42e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/anddi3-opt2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+long long muld(long long X, long long Y)
+{
+  return X & ~1;
+}
+
+/* { dg-final { scan-assembler-not "and\[\\t \]+.+,\[\\t \]*.+,\[\\t \]*.+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/arm.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/arm.exp
new file mode 100644
index 000000000..54ff2370a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/arm.exp
@@ -0,0 +1,47 @@
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an ARM target.
+if ![istarget arm*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# This variable should only apply to tests called in this exp file.
+global dg_runtest_extra_prunes
+set dg_runtest_extra_prunes ""
+lappend dg_runtest_extra_prunes "warning: switch -m(cpu|arch)=.* conflicts with -m(cpu|arch)=.* switch"
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+set dg_runtest_extra_prunes ""
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/asm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/asm.c
new file mode 100644
index 000000000..452ebf4de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/asm.c
@@ -0,0 +1,13 @@
+/* ARM and Thumb asm statements should be able to access the constant
+   pool.  */
+/* { dg-do compile } */
+extern unsigned x[];
+unsigned *trapTable()
+{
+  unsigned *i;
+
+  __asm__ volatile("ldr %0,%1" : "=r"(i) : "m"(x[0]));
+
+  return i;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
new file mode 100644
index 000000000..ea6fdd96d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-comp-swap-release-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaex" 4 } } */
+/* { dg-final { scan-assembler-times "stlex" 4 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
new file mode 100644
index 000000000..ccfa31c34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-acq_rel.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
new file mode 100644
index 000000000..52bcf99e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-char.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-char.c
new file mode 100644
index 000000000..0c30922db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-char.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-char.x"
+
+/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-consume.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-consume.c
new file mode 100644
index 000000000..0354717cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-consume.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-consume.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-int.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-int.c
new file mode 100644
index 000000000..7716994f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-int.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-int.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
new file mode 100644
index 000000000..4b72fd95b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-relaxed.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-release.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-release.c
new file mode 100644
index 000000000..8582e4f1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-release.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-release.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
new file mode 100644
index 000000000..70b5b9ebb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-seq_cst.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-short.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-short.c
new file mode 100644
index 000000000..a6f5a6df6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/atomic-op-short.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "../aarch64/atomic-op-short.x"
+
+/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c
new file mode 100644
index 000000000..43195bd82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap-1.c
@@ -0,0 +1,81 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_arch_v6_ok } */
+/* { dg-add-options arm_arch_v6 } */
+/* { dg-final { scan-assembler-not "orr\[ \t\]" } } */
+/* { dg-final { scan-assembler-times "revsh\\t" 1 { target { arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "revshne\\t" 1 { target { arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "revsh\\t" 2 { target { ! arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "rev16\\t" 1 { target { arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "rev16ne\\t" 1 { target { arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "rev16\\t" 2 { target { ! arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "rev\\t" 2 { target { arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "revne\\t" 2 { target { arm_nothumb } } } }  */
+/* { dg-final { scan-assembler-times "rev\\t" 4 { target { ! arm_nothumb } } } }  */
+
+/* revsh */
+short swaps16 (short x)
+{
+  return __builtin_bswap16 (x);
+}
+
+extern short foos16 (short);
+
+/* revshne */
+short swaps16_cond (short x, int y)
+{
+  short z = x;
+  if (y)
+    z = __builtin_bswap16 (x);
+  return foos16 (z);
+}
+
+/* rev16 */
+unsigned short swapu16 (unsigned short x)
+{
+  return __builtin_bswap16 (x);
+}
+
+extern unsigned short foou16 (unsigned short);
+
+/* rev16ne */
+unsigned short swapu16_cond (unsigned short x, int y)
+{
+  unsigned short z = x;
+  if (y)
+    z = __builtin_bswap16 (x);
+  return foou16 (z);
+}
+
+/* rev */
+int swaps32 (int x) {
+  return __builtin_bswap32 (x);
+}
+
+extern int foos32 (int);
+
+/* revne */
+int swaps32_cond (int x, int y)
+{
+  int z = x;
+  if (y)
+    z = __builtin_bswap32 (x);
+  return foos32 (z);
+}
+
+/* rev */
+unsigned int swapu32 (unsigned int x)
+{
+  return __builtin_bswap32 (x);
+}
+
+extern unsigned int foou32 (unsigned int);
+
+/* revne */
+unsigned int swapsu2 (unsigned int x, int y)
+{
+  int z = x;
+  if (y)
+    z = __builtin_bswap32 (x);
+  return foou32 (z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap16-1.c
new file mode 100644
index 000000000..6920f004e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-bswap16-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_arch_v6_ok } */
+/* { dg-add-options arm_arch_v6 } */
+/* { dg-final { scan-assembler-not "orr\[ \t\]" } } */
+
+unsigned short swapu16_1 (unsigned short x)
+{
+  return (x << 8) | (x >> 8);
+}
+
+unsigned short swapu16_2 (unsigned short x)
+{
+  return (x >> 8) | (x << 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-trap.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-trap.c
new file mode 100644
index 000000000..4ff8d253e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/builtin-trap.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm32 } */
+
+void
+trap ()
+{
+  __builtin_trap ();
+}
+
+/* { dg-final { scan-assembler "0xe7f000f0" { target { arm_nothumb } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-1.c
new file mode 100644
index 000000000..0d6b7c266
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler-not "\tbl\t" } } */
+/* { dg-final { scan-assembler-not "__aeabi" } } */
+int x, y;
+
+#define TEST_EXPR(NAME, ARGS, EXPR)			\
+  int NAME##1 ARGS { return (EXPR); }			\
+  int NAME##2 ARGS { return !(EXPR); }			\
+  int NAME##3 ARGS { return (EXPR) ? x : y; }		\
+  void NAME##4 ARGS { if (EXPR) x++; }			\
+  void NAME##5 ARGS { if (!(EXPR)) x++; }
+
+#define TEST(NAME, TYPE, OPERATOR) \
+  TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2)	\
+  TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2)	\
+  TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2)	\
+  TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \
+  TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100)		\
+  TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1)
+
+#define TEST_OP(NAME, OPERATOR) \
+  TEST (sc_##NAME, signed char, OPERATOR)		\
+  TEST (uc_##NAME, unsigned char, OPERATOR)		\
+  TEST (ss_##NAME, short, OPERATOR)			\
+  TEST (us_##NAME, unsigned short, OPERATOR)		\
+  TEST (si_##NAME, int, OPERATOR)			\
+  TEST (ui_##NAME, unsigned int, OPERATOR)		\
+  TEST (sll_##NAME, long long, OPERATOR)		\
+  TEST (ull_##NAME, unsigned long long, OPERATOR)
+
+TEST_OP (eq, ==)
+TEST_OP (ne, !=)
+TEST_OP (lt, <)
+TEST_OP (gt, >)
+TEST_OP (le, <=)
+TEST_OP (ge, >=)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-2.c
new file mode 100644
index 000000000..ed6b609ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/cmp-2.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */
+/* { dg-final { scan-assembler-not "\tbl\t" } } */
+/* { dg-final { scan-assembler-not "__aeabi" } } */
+int x, y;
+
+#define EQ(X, Y) ((X) == (Y))
+#define NE(X, Y) ((X) != (Y))
+#define LT(X, Y) ((X) < (Y))
+#define GT(X, Y) ((X) > (Y))
+#define LE(X, Y) ((X) <= (Y))
+#define GE(X, Y) ((X) >= (Y))
+
+#define TEST_EXPR(NAME, ARGS, EXPR)			\
+  int NAME##1 ARGS { return (EXPR); }			\
+  int NAME##2 ARGS { return !(EXPR); }			\
+  int NAME##3 ARGS { return (EXPR) ? x : y; }		\
+  void NAME##4 ARGS { if (EXPR) x++; }			\
+  void NAME##5 ARGS { if (!(EXPR)) x++; }
+
+#define TEST(NAME, TYPE, OPERATOR) \
+  TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2))		\
+  TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2))	\
+  TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2))	\
+  TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2))	\
+  TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100))			\
+  TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1))
+
+#define TEST_OP(NAME, OPERATOR) \
+  TEST (f_##NAME, float, OPERATOR)		\
+  TEST (d_##NAME, double, OPERATOR)		\
+  TEST (ld_##NAME, long double, OPERATOR)
+
+TEST_OP (eq, EQ)
+TEST_OP (ne, NE)
+TEST_OP (lt, LT)
+TEST_OP (gt, GT)
+TEST_OP (le, LE)
+TEST_OP (ge, GE)
+TEST_OP (blt, __builtin_isless)
+TEST_OP (bgt, __builtin_isgreater)
+TEST_OP (ble, __builtin_islessequal)
+TEST_OP (bge, __builtin_isgreaterequal)
+/* This one should be expanded into separate ordered and equality
+   comparisons.  */
+TEST_OP (blg, __builtin_islessgreater)
+TEST_OP (bun, __builtin_isunordered)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/cold-lc.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/cold-lc.c
new file mode 100644
index 000000000..295c29fe8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/cold-lc.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-calls" } */
+/* { dg-final { scan-assembler-not "bl\[^\n\]*dump_stack" } } */
+
+extern void dump_stack (void) __attribute__ ((__cold__)) __attribute__ ((noinline));
+struct thread_info {
+    struct task_struct *task;
+};
+extern struct thread_info *current_thread_info (void);
+
+void dump_stack (void)
+{
+    unsigned long stack;
+    show_stack ((current_thread_info ()->task), &stack);
+}
+
+void die (char *str, void *fp, int nr)
+{
+    dump_stack ();
+    while (1);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
new file mode 100644
index 000000000..a64f20e06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c
@@ -0,0 +1,16 @@
+/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */
+/* { dg-options "-O2 -mcpu=cortex-a8" }  */
+/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+void abort (void);
+
+SItype
+__mulvsi3 (SItype a, SItype b)
+{
+  const DItype w = (DItype) a * (DItype) b;
+  if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1))
+    abort ();
+  return w;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-movs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-movs.c
new file mode 100644
index 000000000..e9fd6cb45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/combine-movs.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { arm_thumb1 } } */
+/* { dg-options "-O" }  */
+
+void foo (unsigned long r[], unsigned int d)
+{
+  int i, n = d / 32;
+  for (i = 0; i < n; ++i)
+    r[i] = 0;
+}
+
+/* { dg-final { scan-assembler "lsrs\tr\[0-9\]" { target arm_thumb2 } } } */
+/* { dg-final { scan-assembler "movs\tr\[0-9\]" { target { ! arm_thumb2 } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/cond-asm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/cond-asm.c
new file mode 100644
index 000000000..450bd9d6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/cond-asm.c
@@ -0,0 +1,13 @@
+/* Check that %? in inline asm expands to nothing.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+int b;
+int foo(int a)
+{
+  if (a)
+    b = 42;
+  asm ("test%?me":"=r"(a):"0"(a));
+  return a;
+}
+/* { dg-final { scan-assembler "testme" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c
new file mode 100644
index 000000000..e0b25b93c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesdq_u8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b, c;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    {
+      a[i] = i;
+      b[i] = 15 - i;
+    }
+  c = vaesdq_u8 (a, b);
+  return c[0];
+}
+
+/* { dg-final { scan-assembler "aesd.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c
new file mode 100644
index 000000000..f47864662
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaeseq_u8.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b, c;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    {
+      a[i] = i;
+      b[i] = 15 - i;
+    }
+  c = vaeseq_u8 (a, b);
+  return c[0];
+}
+
+/* { dg-final { scan-assembler "aese.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c
new file mode 100644
index 000000000..fbbfda609
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesimcq_u8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    a[i] = i;
+
+  b = vaesimcq_u8 (a);
+  return b[0];
+}
+
+/* { dg-final { scan-assembler "aesimc.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c
new file mode 100644
index 000000000..cae8bd096
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vaesmcq_u8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint8x16_t a, b;
+  int i = 0;
+
+  for (i = 0; i < 16; ++i)
+    a[i] = i;
+
+  b = vaesmcq_u8 (a);
+  return b[0];
+}
+
+/* { dg-final { scan-assembler "aesmc.8\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c
new file mode 100644
index 000000000..96c0e9a75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vldrq_p128.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (poly128_t* ptr)
+{
+  return vldrq_p128 (ptr);
+}
+
+/* { dg-final { scan-assembler "vld1.64\t{d\[0-9\]+-d\[0-9\]+}.*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c
new file mode 100644
index 000000000..1290f31a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmull_high_p64.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (void)
+{
+  poly64x2_t a = { 0xdeadbeef, 0xadabcaca };
+  poly64x2_t b = { 0xdcdcdcdc, 0xbdbdbdbd };
+  return vmull_high_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmull.p64.*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c
new file mode 100644
index 000000000..b788dca52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vmullp64.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly128_t
+foo (void)
+{
+  poly64_t a = 0xdeadbeef;
+  poly64_t b = 0xadadadad;
+  return vmull_p64 (a, b);
+}
+
+/* { dg-final { scan-assembler "vmull.p64.*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
new file mode 100644
index 000000000..4dc9dee66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1cq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1cq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1c.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
new file mode 100644
index 000000000..dee277485
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1h_u32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t val = 0xdeadbeef;
+  return vsha1h_u32 (val);
+}
+
+/* { dg-final { scan-assembler "sha1h.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
new file mode 100644
index 000000000..672b93a97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1mq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1mq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1m.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
new file mode 100644
index 000000000..ff508e0dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1pq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32_t hash = 0xdeadbeef;
+  uint32x4_t a = {0, 1, 2, 3};
+  uint32x4_t b = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1pq_u32 (a, hash, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1p.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c
new file mode 100644
index 000000000..4435d1800
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su0q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha1su0q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1su0.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c
new file mode 100644
index 000000000..8610c4de2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha1su1q_u32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+
+  uint32x4_t res = vsha1su1q_u32 (a, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha1su1.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c
new file mode 100644
index 000000000..4a3e2e158
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256h2q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256h2q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256h2.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c
new file mode 100644
index 000000000..49577f2b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256hq_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256hq_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256h.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c
new file mode 100644
index 000000000..cc4305d38
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su0q_u32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+
+  uint32x4_t res = vsha256su0q_u32 (a, b);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256su0.32\tq\[0-9\]+, q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c
new file mode 100644
index 000000000..430f38adc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vsha256su1q_u32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+int
+foo (void)
+{
+  uint32x4_t a = {0xd, 0xe, 0xa, 0xd};
+  uint32x4_t b = {0, 1, 2, 3};
+  uint32x4_t c = {3, 2, 1, 0};
+
+  uint32x4_t res = vsha256su1q_u32 (a, b, c);
+  return res[0];
+}
+
+/* { dg-final { scan-assembler "sha256su1.32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c
new file mode 100644
index 000000000..acd8af34f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/crypto-vstrq_p128.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void
+foo (poly128_t* ptr, poly128_t val)
+{
+  vstrq_p128 (ptr, val);
+}
+
+/* { dg-final { scan-assembler "vst1.64\t{d\[0-9\]+-d\[0-9\]+}.*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ctz.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ctz.c
new file mode 100644
index 000000000..2455f6740
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ctz.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2" } */
+
+unsigned int functest(unsigned int x)
+{
+	return __builtin_ctz(x);
+}
+
+/* { dg-final { scan-assembler "rbit" } } */
+/* { dg-final { scan-assembler "clz" } } */
+/* { dg-final { scan-assembler-not "rsb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c
new file mode 100644
index 000000000..c2959165b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withhelpers.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v5_ok } */
+/* { dg-options "-std=gnu99" } */
+/* { dg-add-options arm_arch_v5 } */
+/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */
+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "nand_and_fetch" { target *-*-* } 0 } */
+/* { dg-message "file included" "In file included" { target *-*-* } 0 } */
+
+#include "../../gcc.dg/di-longlong64-sync-1.c"
+
+/* On an old ARM we have no ldrexd or strexd so we have to use helpers.  */
+/* { dg-final { scan-assembler-not "ldrexd" } } */
+/* { dg-final { scan-assembler-not "strexd" } } */
+/* { dg-final { scan-assembler "__sync_" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c
new file mode 100644
index 000000000..517c4a89d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/di-longlong64-sync-withldrexd.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arm_ok } */
+/* { dg-options "-marm -std=gnu99" } */
+/* { dg-require-effective-target arm_arch_v6k_ok } */
+/* { dg-add-options arm_arch_v6k } */
+/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "fetch_and_nand" { target *-*-* } 0 } */
+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "nand_and_fetch" { target *-*-* } 0 } */
+/* { dg-message "file included" "In file included" { target *-*-* } 0 } */
+
+#include "../../gcc.dg/di-longlong64-sync-1.c"
+
+/* We should be using ldrexd, strexd and no helpers or shorter ldrex.  */
+/* { dg-final { scan-assembler-times "\tldrexd" 48 } } */
+/* { dg-final { scan-assembler-times "\tstrexd" 48 } } */
+/* { dg-final { scan-assembler-not "__sync_" } } */
+/* { dg-final { scan-assembler-not "ldrex\t" } } */
+/* { dg-final { scan-assembler-not "strex\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/div64-unwinding.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/div64-unwinding.c
new file mode 100644
index 000000000..7f112eeab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/div64-unwinding.c
@@ -0,0 +1,24 @@
+/* Performing a 64-bit division should not pull in the unwinder.  */
+
+/* { dg-do run { target { ! *-*-linux* } } } */
+/* { dg-options "-O0" } */
+
+#include <stdlib.h>
+
+long long
+foo (long long c, long long d)
+{
+  return c/d;
+}
+
+long long x = 0;
+long long y = 1;
+
+extern int (*_Unwind_RaiseException) (void *) __attribute__((weak));
+
+int main(void)
+{
+  if (&_Unwind_RaiseException != NULL)
+    abort ();;
+  return foo (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/eabi1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/eabi1.c
new file mode 100644
index 000000000..c90f5ff08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/eabi1.c
@@ -0,0 +1,342 @@
+/* { dg-do run { target arm*-*-symbianelf* arm*-*-eabi* } } */
+/* { dg-options "" } */
+
+/* This file tests most of the non-C++ run-time helper functions
+   described in Section 4 of the "Run-Time ABI for the ARM
+   Architecture".  These are basic tests; they do not try to validate
+   all of the corner cases in these routines.  
+
+   The functions not tested here are:
+
+     __aeabi_cdcmpeq
+     __aeabi_cdcmple
+     __aeabi_cdrcmple
+     __aeabi_cfcmpeq
+     __aeabi_cfcmple
+     __aeabi_cfrcmple
+     __aeabi_ldivmod
+     __aeabi_uldivmod
+     __aeabi_idivmod
+     __aeabi_uidivmod
+
+   These functions have non-standard calling conventions that would
+   require the use of inline assembly to test.  It would be good to
+   add such tests, but they have not yet been implemented.  
+
+   There are also no tests for the "division by zero", "memory copying,
+   clearing, and setting" functions.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+
+/* All these functions are defined to use the base ABI, so use the
+   attribute to ensure the tests use the base ABI to call them even
+   when the VFP ABI is otherwise in effect.  */
+#define PCS __attribute__((pcs("aapcs")))
+
+#define decl_float(code, type)						\
+  extern type __aeabi_ ## code ## add (type, type) PCS;			\
+  extern type __aeabi_ ## code ## div (type, type) PCS;			\
+  extern type __aeabi_ ## code ## mul (type, type) PCS;			\
+  extern type __aeabi_ ## code ## neg (type) PCS;			\
+  extern type __aeabi_ ## code ## rsub (type, type) PCS;		\
+  extern type __aeabi_ ## code ## sub (type, type) PCS;			\
+  extern int __aeabi_ ## code ## cmpeq (type, type) PCS;		\
+  extern int __aeabi_ ## code ## cmplt (type, type) PCS;		\
+  extern int __aeabi_ ## code ## cmple (type, type) PCS;		\
+  extern int __aeabi_ ## code ## cmpge (type, type) PCS;		\
+  extern int __aeabi_ ## code ## cmpgt (type, type) PCS;		\
+  extern int __aeabi_ ## code ## cmpun (type, type) PCS;		\
+  extern int __aeabi_ ## code ## 2iz (type) PCS;			\
+  extern unsigned int __aeabi_ ## code ## 2uiz (type) PCS;		\
+  extern long long __aeabi_ ## code ## 2lz (type) PCS;			\
+  extern unsigned long long __aeabi_ ## code ## 2ulz (type) PCS;	\
+  extern type __aeabi_i2 ## code (int) PCS;				\
+  extern type __aeabi_ui2 ## code (int) PCS;				\
+  extern type __aeabi_l2 ## code (long long) PCS;			\
+  extern type __aeabi_ul2 ## code (unsigned long long) PCS;		\
+									\
+  type code ## zero = 0.0;						\
+  type code ## one = 1.0;						\
+  type code ## two = 2.0;						\
+  type code ## four = 4.0;						\
+  type code ## minus_one = -1.0;					\
+  type code ## minus_two = -2.0;					\
+  type code ## minus_four = -4.0;					\
+  type code ## epsilon = 1E-32;						\
+  type code ## NaN = 0.0 / 0.0;
+
+decl_float (d, double)
+decl_float (f, float)
+
+extern float __aeabi_d2f (double) PCS;
+extern double __aeabi_f2d (float) PCS;
+extern long long __aeabi_lmul (long long, long long);
+extern long long __aeabi_llsl (long long, int);
+extern long long __aeabi_llsr (long long, int);
+extern long long __aeabi_lasr (long long, int);
+extern int __aeabi_lcmp (long long, long long);
+extern int __aeabi_ulcmp (unsigned long long, unsigned long long);
+extern int __aeabi_idiv (int, int);
+extern unsigned int __aeabi_uidiv (unsigned int, unsigned int);
+extern int __aeabi_uread4 (void *);
+extern int __aeabi_uwrite4 (int, void *);
+extern long long __aeabi_uread8 (void *);
+extern long long __aeabi_uwrite8 (long long, void *);
+
+#define eq(a, b, type, abs, epsilon, format)			\
+  {								\
+    type a1;							\
+    type b1;							\
+								\
+    a1 = a;							\
+    b1 = b;							\
+    if (abs (a1 - b1) > epsilon)				\
+    {								\
+      fprintf (stderr, "%d: Test %s == %s\n", __LINE__, #a, #b);	\
+      fprintf (stderr, "%d: " format " != " format "\n",	\
+	       __LINE__, a1, b1);				\
+      abort ();							\
+    }								\
+  }
+
+#define ieq(a, b) eq (a, b, int, abs, 0, "%d")
+#define ueq(a, b) eq (a, b, unsigned int, abs, 0, "%u")
+#define leq(a, b) eq (a, b, long long, abs, 0, "%lld")
+#define uleq(a, b) eq (a, b, unsigned long long, abs, 0, "%llu")
+#define feq(a, b) eq (a, b, float, fabs, fepsilon, "%f")
+#define deq(a, b) eq (a, b, double, fabs, depsilon, "%g")
+
+#define NUM_CMP_VALUES 6
+
+/* Values picked to cover a range of small, large, positive and negative.  */
+static unsigned int cmp_val[NUM_CMP_VALUES] = 
+{
+  0,
+  1,
+  0x40000000,
+  0x80000000,
+  0xc0000000,
+  0xffffffff
+};
+
+/* All combinations for each of the above values. */
+#define ulcmp(l, s, m) \
+    s, l, l, l, l, l,  m, s, l, l, l, l, \
+    m, m, s, l, l, l,  m, m, m, s, l, l, \
+    m, m, m, m, s, l,  m, m, m, m, m, s
+
+#define lcmp(l, s, m) \
+    s, l, l, m, m, m,  m, s, l, m, m, m, \
+    m, m, s, m, m, m,  l, l, l, s, l, l, \
+    l, l, l, m, s, l,  l, l, l, m, m, s
+
+/* All combinations of the above for high/low words.  */
+static int lcmp_results[] =
+{
+  lcmp(ulcmp(-1, -1, -1), ulcmp(-1, 0, 1), ulcmp(1, 1, 1))
+};
+
+static int ulcmp_results[] =
+{
+  ulcmp(ulcmp(-1, -1, -1), ulcmp(-1, 0, 1), ulcmp(1, 1, 1))
+};
+
+static int signof(int i)
+{
+  if (i < 0)
+    return -1;
+
+  if (i == 0)
+    return 0;
+
+  return 1;
+}
+
+int main () {
+  unsigned char bytes[256];
+  int i, j, k, n;
+  int *result;
+
+  /* Table 2.  Double-precision floating-point arithmetic.  */
+  deq (__aeabi_dadd (dzero, done), done);
+  deq (__aeabi_dadd (done, done), dtwo);
+  deq (__aeabi_ddiv (dminus_four, dminus_two), dtwo);
+  deq (__aeabi_ddiv (dminus_two, dtwo), dminus_one);
+  deq (__aeabi_dmul (dtwo, dtwo), dfour);
+  deq (__aeabi_dmul (dminus_one, dminus_two), dtwo);
+  deq (__aeabi_dneg (dminus_one), done);
+  deq (__aeabi_dneg (dfour), dminus_four);
+  deq (__aeabi_drsub (done, dzero), dminus_one);
+  deq (__aeabi_drsub (dtwo, dminus_two), dminus_four);
+  deq (__aeabi_dsub (dzero, done), dminus_one);
+  deq (__aeabi_dsub (dminus_two, dtwo), dminus_four);
+
+  /* Table 3.  Double-precision floating-point comparisons.  */
+  ieq (__aeabi_dcmpeq (done, done), 1);
+  ieq (__aeabi_dcmpeq (done, dzero), 0);
+  ieq (__aeabi_dcmpeq (dNaN, dzero), 0);
+  ieq (__aeabi_dcmpeq (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmplt (dzero, done), 1);
+  ieq (__aeabi_dcmplt (done, dzero), 0);
+  ieq (__aeabi_dcmplt (dzero, dzero), 0);
+  ieq (__aeabi_dcmplt (dzero, dNaN), 0);
+  ieq (__aeabi_dcmplt (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmple (dzero, done), 1);
+  ieq (__aeabi_dcmple (done, dzero), 0);
+  ieq (__aeabi_dcmple (dzero, dzero), 1);
+  ieq (__aeabi_dcmple (dzero, dNaN), 0);
+  ieq (__aeabi_dcmple (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmpge (dzero, done), 0);
+  ieq (__aeabi_dcmpge (done, dzero), 1);
+  ieq (__aeabi_dcmpge (dzero, dzero), 1);
+  ieq (__aeabi_dcmpge (dzero, dNaN), 0);
+  ieq (__aeabi_dcmpge (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmpgt (dzero, done), 0);
+  ieq (__aeabi_dcmpgt (done, dzero), 1);
+  ieq (__aeabi_dcmplt (dzero, dzero), 0);
+  ieq (__aeabi_dcmpgt (dzero, dNaN), 0);
+  ieq (__aeabi_dcmpgt (dNaN, dNaN), 0);
+
+  ieq (__aeabi_dcmpun (done, done), 0);
+  ieq (__aeabi_dcmpun (done, dzero), 0);
+  ieq (__aeabi_dcmpun (dNaN, dzero), 1);
+  ieq (__aeabi_dcmpun (dNaN, dNaN), 1);
+
+  /* Table 4.  Single-precision floating-point arithmetic.  */
+  feq (__aeabi_fadd (fzero, fone), fone);
+  feq (__aeabi_fadd (fone, fone), ftwo);
+  feq (__aeabi_fdiv (fminus_four, fminus_two), ftwo);
+  feq (__aeabi_fdiv (fminus_two, ftwo), fminus_one);
+  feq (__aeabi_fmul (ftwo, ftwo), ffour);
+  feq (__aeabi_fmul (fminus_one, fminus_two), ftwo);
+  feq (__aeabi_fneg (fminus_one), fone);
+  feq (__aeabi_fneg (ffour), fminus_four);
+  feq (__aeabi_frsub (fone, fzero), fminus_one);
+  feq (__aeabi_frsub (ftwo, fminus_two), fminus_four);
+  feq (__aeabi_fsub (fzero, fone), fminus_one);
+  feq (__aeabi_fsub (fminus_two, ftwo), fminus_four);
+
+  /* Table 5.  Single-precision floating-point comparisons.  */
+  ieq (__aeabi_fcmpeq (fone, fone), 1);
+  ieq (__aeabi_fcmpeq (fone, fzero), 0);
+  ieq (__aeabi_fcmpeq (fNaN, fzero), 0);
+  ieq (__aeabi_fcmpeq (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmplt (fzero, fone), 1);
+  ieq (__aeabi_fcmplt (fone, fzero), 0);
+  ieq (__aeabi_fcmplt (fzero, fzero), 0);
+  ieq (__aeabi_fcmplt (fzero, fNaN), 0);
+  ieq (__aeabi_fcmplt (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmple (fzero, fone), 1);
+  ieq (__aeabi_fcmple (fone, fzero), 0);
+  ieq (__aeabi_fcmple (fzero, fzero), 1);
+  ieq (__aeabi_fcmple (fzero, fNaN), 0);
+  ieq (__aeabi_fcmple (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmpge (fzero, fone), 0);
+  ieq (__aeabi_fcmpge (fone, fzero), 1);
+  ieq (__aeabi_fcmpge (fzero, fzero), 1);
+  ieq (__aeabi_fcmpge (fzero, fNaN), 0);
+  ieq (__aeabi_fcmpge (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmpgt (fzero, fone), 0);
+  ieq (__aeabi_fcmpgt (fone, fzero), 1);
+  ieq (__aeabi_fcmplt (fzero, fzero), 0);
+  ieq (__aeabi_fcmpgt (fzero, fNaN), 0);
+  ieq (__aeabi_fcmpgt (fNaN, fNaN), 0);
+
+  ieq (__aeabi_fcmpun (fone, fone), 0);
+  ieq (__aeabi_fcmpun (fone, fzero), 0);
+  ieq (__aeabi_fcmpun (fNaN, fzero), 1);
+  ieq (__aeabi_fcmpun (fNaN, fNaN), 1);
+
+  /* Table 6.  Floating-point to integer conversions.  */
+  ieq (__aeabi_d2iz (dminus_one), -1);
+  ueq (__aeabi_d2uiz (done), 1);
+  leq (__aeabi_d2lz (dminus_two), -2LL);
+  uleq (__aeabi_d2ulz (dfour), 4LL);
+  ieq (__aeabi_f2iz (fminus_one), -1);
+  ueq (__aeabi_f2uiz (fone), 1);
+  leq (__aeabi_f2lz (fminus_two), -2LL);
+  uleq (__aeabi_f2ulz (ffour), 4LL);
+
+  /* Table 7.  Conversions between floating types.  */
+  feq (__aeabi_d2f (dtwo), ftwo);
+  deq (__aeabi_f2d (fminus_four), dminus_four);
+
+  /* Table 8.  Integer to floating-point conversions.  */
+  deq (__aeabi_i2d (-1), dminus_one);
+  deq (__aeabi_ui2d (2), dtwo);
+  deq (__aeabi_l2d (-1), dminus_one);
+  deq (__aeabi_ul2d (2ULL), dtwo);
+  feq (__aeabi_i2f (-1), fminus_one);
+  feq (__aeabi_ui2f (2), ftwo);
+  feq (__aeabi_l2f (-1), fminus_one);
+  feq (__aeabi_ul2f (2ULL), ftwo);
+
+  /* Table 9.  Long long functions.  */
+  leq (__aeabi_lmul (4LL, -1LL), -4LL);
+  leq (__aeabi_llsl (2LL, 1), 4LL);
+  leq (__aeabi_llsr (-1LL, 63), 1);
+  leq (__aeabi_lasr (-1LL, 63), -1);
+
+  result = lcmp_results;
+  for (i = 0; i < NUM_CMP_VALUES; i++)
+    for (j = 0; j < NUM_CMP_VALUES; j++)
+      for (k = 0; k < NUM_CMP_VALUES; k++)
+	for (n = 0; n < NUM_CMP_VALUES; n++)
+	  {
+	    ieq (signof (__aeabi_lcmp
+			  (((long long)cmp_val[i] << 32) | cmp_val[k],
+			   ((long long)cmp_val[j] << 32) | cmp_val[n])),
+			   *result);
+	    result++;
+	  }
+  result = ulcmp_results;
+  for (i = 0; i < NUM_CMP_VALUES; i++)
+    for (j = 0; j < NUM_CMP_VALUES; j++)
+      for (k = 0; k < NUM_CMP_VALUES; k++)
+	for (n = 0; n < NUM_CMP_VALUES; n++)
+	  {
+	    ieq (signof (__aeabi_ulcmp
+			  (((long long)cmp_val[i] << 32) | cmp_val[k],
+			   ((long long)cmp_val[j] << 32) | cmp_val[n])),
+			   *result);
+	    result++;
+	  }
+
+  ieq (__aeabi_idiv (-550, 11), -50);
+  ueq (__aeabi_uidiv (4000000000U, 1000000U), 4000U);
+
+  for (i = 0; i < 256; i++)
+    bytes[i] = i;
+
+#ifdef __ARMEB__
+  ieq (__aeabi_uread4 (bytes + 1), 0x01020304U);
+  leq (__aeabi_uread8 (bytes + 3), 0x030405060708090aLL);
+  ieq (__aeabi_uwrite4 (0x66778899U, bytes + 5), 0x66778899U);
+  leq (__aeabi_uwrite8 (0x2030405060708090LL, bytes + 15),
+       0x2030405060708090LL);
+#else
+  ieq (__aeabi_uread4 (bytes + 1), 0x04030201U);
+  leq (__aeabi_uread8 (bytes + 3), 0x0a09080706050403LL);
+  ieq (__aeabi_uwrite4 (0x99887766U, bytes + 5), 0x99887766U);
+  leq (__aeabi_uwrite8 (0x9080706050403020LL, bytes + 15),
+       0x9080706050403020LL);
+#endif
+
+  for (i = 0; i < 4; i++)
+    ieq (bytes[5 + i], (6 + i) * 0x11);
+
+  for (i = 0; i < 8; i++)
+    ieq (bytes[15 + i], (2 + i) * 0x10);
+
+  exit (0);		
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/eliminate.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/eliminate.c
new file mode 100644
index 000000000..f254dd811
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/eliminate.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+
+struct X
+{
+  int c;
+};
+
+extern void bar(struct X *);
+
+void foo ()
+{
+  struct X x;
+  bar (&x);
+  bar (&x);
+  bar (&x);
+}
+
+/* { dg-final { scan-assembler-times "r0,\[\\t \]*sp" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/epilog-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/epilog-1.c
new file mode 100644
index 000000000..f97f1ebea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/epilog-1.c
@@ -0,0 +1,17 @@
+/* Register liveness information from epilgoue enables peephole optimization. */
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+volatile int g_k;
+extern void bar(int, int, int, int);
+
+int foo(int a, int b, int c, int d)
+{
+  if (g_k & 4) c++;
+  bar (a, b, c, d);
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "lsls.*#29" 1 } } */
+/* { dg-final { scan-assembler-not "tst" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed-point-exec.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed-point-exec.c
new file mode 100644
index 000000000..6bc3b07d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed-point-exec.c
@@ -0,0 +1,301 @@
+/* { dg-do run { target { fixed_point } } } */
+/* { dg-options "-std=gnu99" } */
+
+/* Check basic arithmetic ops for ARM fixed-point/saturating operation support.
+   Not target-independent since we make various assumptions about precision and
+   magnitudes of various types.  */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <math.h>
+#include <stdfix.h>
+
+#define TEST(TYPE, OP, NAME, SUFFIX)				\
+  TYPE NAME##SUFFIX (TYPE A, TYPE B)				\
+    {								\
+      return A OP B;						\
+    }
+
+#define VARIANTS(TYPE, OP, NAME)				\
+  TEST (short TYPE, OP, NAME, _short);				\
+  TEST (TYPE, OP, NAME, _regular);				\
+  TEST (long TYPE, OP, NAME, _long);				\
+  TEST (_Sat short TYPE, OP, NAME, _sat_short);			\
+  TEST (_Sat TYPE, OP, NAME, _sat_regular);			\
+  TEST (_Sat long TYPE, OP, NAME, _sat_long);			\
+  TEST (unsigned short TYPE, OP, NAME, _uns_short);		\
+  TEST (unsigned TYPE, OP, NAME, _uns_regular);			\
+  TEST (unsigned long TYPE, OP, NAME, _uns_long);		\
+  TEST (unsigned _Sat short TYPE, OP, NAME, _uns_sat_short);	\
+  TEST (unsigned _Sat TYPE, OP, NAME, _uns_sat_regular);	\
+  TEST (unsigned _Sat long TYPE, OP, NAME, _uns_sat_long)
+
+VARIANTS (_Fract, +, plus_fract);
+VARIANTS (_Accum, +, plus_accum);
+VARIANTS (_Fract, -, minus_fract);
+VARIANTS (_Accum, -, minus_accum);
+VARIANTS (_Fract, *, mult_fract);
+VARIANTS (_Accum, *, mult_accum);
+VARIANTS (_Accum, /, div_accum);
+
+/* Inputs for signed add, multiply fractional tests.  */
+short _Fract sf_a = 0.9hr;
+short _Fract sf_b = -0.8hr;
+_Fract f_a = 0.9r;
+_Fract f_b = -0.8r;
+long _Fract lf_a = 0.9lr;
+long _Fract lf_b = -0.8lr;
+
+/* Inputs for signed subtract fractional tests.  */
+short _Fract sf_c = 0.7hr;
+short _Fract sf_d = 0.9hr;
+_Fract f_c = 0.7r;
+_Fract f_d = 0.9r;
+long _Fract lf_c = 0.7lr;
+long _Fract lf_d = 0.9lr;
+
+/* Inputs for unsigned add, subtract, multiply fractional tests.  */
+unsigned short _Fract usf_a = 0.4uhr;
+unsigned short _Fract usf_b = 0.3uhr;
+unsigned _Fract uf_a = 0.4ur;
+unsigned _Fract uf_b = 0.3ur;
+unsigned long _Fract ulf_a = 0.4ulr;
+unsigned long _Fract ulf_b = 0.3ulr;
+
+/* Inputs for saturating signed add tests.  */
+short _Sat _Fract sf_e = 0.8hr;
+short _Sat _Fract sf_f = 0.8hr;
+_Sat _Fract f_e = 0.8r;
+_Sat _Fract f_f = 0.8r;
+long _Sat _Fract lf_e = 0.8r;
+long _Sat _Fract lf_f = 0.8r;
+
+short _Sat _Fract sf_g = -0.8hr;
+short _Sat _Fract sf_h = -0.8hr;
+_Sat _Fract f_g = -0.8r;
+_Sat _Fract f_h = -0.8r;
+long _Sat _Fract lf_g = -0.8r;
+long _Sat _Fract lf_h = -0.8r;
+
+/* Inputs for saturating unsigned subtract tests.  */
+unsigned short _Sat _Fract usf_c = 0.3uhr;
+unsigned short _Sat _Fract usf_d = 0.4uhr;
+unsigned _Sat _Fract uf_c = 0.3ur;
+unsigned _Sat _Fract uf_d = 0.4ur;
+unsigned long _Sat _Fract ulf_c = 0.3ulr;
+unsigned long _Sat _Fract ulf_d = 0.4ulr;
+
+/* Inputs for signed accumulator tests.  */
+
+short _Accum sa_a = 1.25hk;
+short _Accum sa_b = -1.5hk;
+_Accum a_a = 100.25k;
+_Accum a_b = -100.5k;
+long _Accum la_a = 1000.25lk;
+long _Accum la_b = -1000.5lk;
+
+/* Inputs for unsigned accumulator tests.  */
+
+unsigned short _Accum usa_a = 2.5uhk;
+unsigned short _Accum usa_b = 1.75uhk;
+unsigned _Accum ua_a = 255.5uk;
+unsigned _Accum ua_b = 170.25uk;
+unsigned long _Accum ula_a = 1550.5ulk;
+unsigned long _Accum ula_b = 999.5ulk;
+
+/* Inputs for signed saturating accumulator tests.  */
+
+short _Sat _Accum sa_c = 240.0hk;
+short _Sat _Accum sa_d = 250.0hk;
+short _Sat _Accum sa_e = -240.0hk;
+short _Sat _Accum sa_f = -250.0hk;
+short _Sat _Accum sa_g = 0.5hk;
+
+_Sat _Accum a_c = 65000.0k;
+_Sat _Accum a_d = 20000.0k;
+_Sat _Accum a_e = -65000.0k;
+_Sat _Accum a_f = -20000.0k;
+_Sat _Accum a_g = 0.5k;
+
+long _Sat _Accum la_c = 3472883712.0lk;
+long _Sat _Accum la_d = 3456106496.0lk;
+long _Sat _Accum la_e = -3472883712.0lk;
+long _Sat _Accum la_f = -3456106496.0lk;
+long _Sat _Accum la_g = 0.5lk;
+
+/* Inputs for unsigned saturating accumulator tests.  */
+
+unsigned short _Sat _Accum usa_c = 250.0uhk;
+unsigned short _Sat _Accum usa_d = 240.0uhk;
+unsigned short _Sat _Accum usa_e = 0.5uhk;
+
+unsigned _Sat _Accum ua_c = 65000.0uk;
+unsigned _Sat _Accum ua_d = 20000.0uk;
+unsigned _Sat _Accum ua_e = 0.5uk;
+
+unsigned long _Sat _Accum ula_c = 3472883712.0ulk;
+unsigned long _Sat _Accum ula_d = 3456106496.0ulk;
+unsigned long _Sat _Accum ula_e = 0.5ulk;
+
+#define CHECK(FN, EXP) do {						     \
+  if (fabs ((float) (FN) - (EXP)) > 0.05)				     \
+    {									     \
+      fprintf (stderr, "result for " #FN " (as float): %f\n", (double) (FN));\
+      abort ();								     \
+    }									     \
+  } while (0)
+
+#define CHECK_EXACT(FN, EXP) do {					     \
+  if ((FN) != (EXP))							     \
+    {									     \
+      fprintf (stderr, "result for " #FN " (as float): %f, should be %f\n",  \
+	       (double) (FN), (double) (EXP));				     \
+      abort ();								     \
+    }									     \
+  } while (0)
+
+int
+main (int argc, char *argv[])
+{
+  /* Fract/fract operations, non-saturating.  */
+
+  CHECK (plus_fract_short (sf_a, sf_b), 0.1);
+  CHECK (plus_fract_regular (f_a, f_b), 0.1);
+  CHECK (plus_fract_long (lf_a, lf_b), 0.1);
+
+  CHECK (plus_fract_uns_short (usf_a, usf_b), 0.7);
+  CHECK (plus_fract_uns_regular (uf_a, uf_b), 0.7);
+  CHECK (plus_fract_uns_long (ulf_a, ulf_b), 0.7);
+
+  CHECK (minus_fract_short (sf_c, sf_d), -0.2);
+  CHECK (minus_fract_regular (f_c, f_d), -0.2);
+  CHECK (minus_fract_long (lf_c, lf_d), -0.2);
+
+  CHECK (minus_fract_uns_short (usf_a, usf_b), 0.1);
+  CHECK (minus_fract_uns_regular (uf_a, uf_b), 0.1);
+  CHECK (minus_fract_uns_long (ulf_a, ulf_b), 0.1);
+
+  CHECK (mult_fract_short (sf_a, sf_b), -0.72);
+  CHECK (mult_fract_regular (f_a, f_b), -0.72);
+  CHECK (mult_fract_long (lf_a, lf_b), -0.72);
+
+  CHECK (mult_fract_uns_short (usf_a, usf_b), 0.12);
+  CHECK (mult_fract_uns_regular (uf_a, uf_b), 0.12);
+  CHECK (mult_fract_uns_long (ulf_a, ulf_b), 0.12);
+
+  /* Fract/fract operations, saturating.  */
+
+  CHECK (plus_fract_sat_short (sf_e, sf_f), 1.0);
+  CHECK (plus_fract_sat_regular (f_e, f_f), 1.0);
+  CHECK (plus_fract_sat_long (lf_e, lf_f), 1.0);
+
+  CHECK (plus_fract_sat_short (sf_g, sf_h), -1.0);
+  CHECK (plus_fract_sat_regular (f_g, f_h), -1.0);
+  CHECK (plus_fract_sat_long (lf_g, lf_h), -1.0);
+  
+  CHECK (plus_fract_uns_sat_short (sf_e, sf_f), 1.0);
+  CHECK (plus_fract_uns_sat_regular (f_e, f_f), 1.0);
+  CHECK (plus_fract_uns_sat_long (lf_e, lf_f), 1.0);
+
+  CHECK (plus_fract_sat_short (sf_a, sf_b), 0.1);
+  CHECK (plus_fract_sat_regular (f_a, f_b), 0.1);
+  CHECK (plus_fract_sat_long (lf_a, lf_b), 0.1);
+  
+  CHECK (plus_fract_uns_sat_short (usf_a, usf_b), 0.7);
+  CHECK (plus_fract_uns_sat_regular (uf_a, uf_b), 0.7);
+  CHECK (plus_fract_uns_sat_long (ulf_a, ulf_b), 0.7);
+
+  CHECK (minus_fract_uns_sat_short (usf_c, usf_d), 0.0);
+  CHECK (minus_fract_uns_sat_regular (uf_c, uf_d), 0.0);
+  CHECK (minus_fract_uns_sat_short (ulf_c, ulf_d), 0.0);
+  
+  CHECK (minus_fract_sat_short (sf_c, sf_d), -0.2);
+  CHECK (minus_fract_sat_regular (f_c, f_d), -0.2);
+  CHECK (minus_fract_sat_long (lf_c, lf_d), -0.2);
+
+  /* Accum/accum operations, non-saturating.  */
+
+  CHECK (plus_accum_short (sa_a, sa_b), -0.25);
+  CHECK (plus_accum_regular (a_a, a_b), -0.25);
+  CHECK (plus_accum_long (la_a, la_b), -0.25);
+
+  CHECK (minus_accum_short (sa_a, sa_b), 2.75);
+  CHECK (minus_accum_regular (a_a, a_b), 200.75);
+  CHECK (minus_accum_long (la_a, la_b), 2000.75);
+  
+  CHECK (mult_accum_short (sa_a, sa_b), -1.875);
+  CHECK (mult_accum_regular (a_a, a_b), -10075.125);
+  CHECK (mult_accum_long (la_a, la_b), -1000750.125);
+
+  CHECK (div_accum_short (sa_a, sa_b), -1.25/1.5);
+  CHECK (div_accum_regular (a_a, a_b), -100.25/100.5);
+  CHECK (div_accum_long (la_a, la_b), -1000.25/1000.5);
+
+  /* Unsigned accum/accum operations, non-saturating.  */
+  
+  CHECK (plus_accum_uns_short (usa_a, usa_b), 4.25);
+  CHECK (plus_accum_uns_regular (ua_a, ua_b), 425.75);
+  CHECK (plus_accum_uns_long (ula_a, ula_b), 2550.0);
+
+  CHECK (minus_accum_uns_short (usa_a, usa_b), 0.75);
+  CHECK (minus_accum_uns_regular (ua_a, ua_b), 85.25);
+  CHECK (minus_accum_uns_long (ula_a, ula_b), 551.0);
+  
+  CHECK (mult_accum_uns_short (usa_a, usa_b), 4.375);
+  CHECK (mult_accum_uns_regular (ua_a, ua_b), 43498.875);
+  CHECK (mult_accum_uns_long (ula_a, ula_b), 1549724.75);
+
+  CHECK (div_accum_uns_short (usa_a, usa_b), 2.5/1.75);
+  CHECK (div_accum_uns_regular (ua_a, ua_b), 255.5/170.25);
+  CHECK (div_accum_uns_long (ula_a, ula_b), 1550.5/999.5);
+
+  /* Signed accum/accum operations, saturating.  */
+  
+  CHECK_EXACT (plus_accum_sat_short (sa_c, sa_d), SACCUM_MAX);
+  CHECK_EXACT (plus_accum_sat_short (sa_e, sa_f), SACCUM_MIN);
+  CHECK_EXACT (plus_accum_sat_regular (a_c, a_d), ACCUM_MAX);
+  CHECK_EXACT (plus_accum_sat_regular (a_e, a_f), ACCUM_MIN);
+  CHECK_EXACT (plus_accum_sat_long (la_c, la_d), LACCUM_MAX);
+  CHECK_EXACT (plus_accum_sat_long (la_e, la_f), LACCUM_MIN);
+
+  CHECK_EXACT (minus_accum_sat_short (sa_e, sa_d), SACCUM_MIN);
+  CHECK_EXACT (minus_accum_sat_short (sa_c, sa_f), SACCUM_MAX);
+  CHECK_EXACT (minus_accum_sat_regular (a_e, a_d), ACCUM_MIN);
+  CHECK_EXACT (minus_accum_sat_regular (a_c, a_f), ACCUM_MAX);
+  CHECK_EXACT (minus_accum_sat_long (la_e, la_d), LACCUM_MIN);
+  CHECK_EXACT (minus_accum_sat_long (la_c, la_f), LACCUM_MAX);
+
+  CHECK_EXACT (mult_accum_sat_short (sa_c, sa_d), SACCUM_MAX);
+  CHECK_EXACT (mult_accum_sat_short (sa_c, sa_e), SACCUM_MIN);
+  CHECK_EXACT (mult_accum_sat_regular (a_c, a_d), ACCUM_MAX);
+  CHECK_EXACT (mult_accum_sat_regular (a_c, a_e), ACCUM_MIN);
+  CHECK_EXACT (mult_accum_sat_long (la_c, la_d), LACCUM_MAX);
+  CHECK_EXACT (mult_accum_sat_long (la_c, la_e), LACCUM_MIN);
+  
+  CHECK_EXACT (div_accum_sat_short (sa_d, sa_g), SACCUM_MAX);
+  CHECK_EXACT (div_accum_sat_short (sa_e, sa_g), SACCUM_MIN);
+  CHECK_EXACT (div_accum_sat_regular (a_c, a_g), ACCUM_MAX);
+  CHECK_EXACT (div_accum_sat_regular (a_e, a_g), ACCUM_MIN);
+  CHECK_EXACT (div_accum_sat_long (la_d, la_g), LACCUM_MAX);
+  CHECK_EXACT (div_accum_sat_long (la_e, la_g), LACCUM_MIN);
+
+  /* Unsigned accum/accum operations, saturating.  */
+
+  CHECK_EXACT (plus_accum_uns_sat_short (usa_c, usa_d), USACCUM_MAX);
+  CHECK_EXACT (plus_accum_uns_sat_regular (ua_c, ua_d), UACCUM_MAX);
+  CHECK_EXACT (plus_accum_uns_sat_long (ula_c, ula_d), ULACCUM_MAX);
+  
+  CHECK_EXACT (minus_accum_uns_sat_short (usa_d, usa_c), 0uhk);
+  CHECK_EXACT (minus_accum_uns_sat_regular (ua_d, ua_c), 0uk);
+  CHECK_EXACT (minus_accum_uns_sat_long (ula_d, ula_c), 0ulk);
+
+  CHECK_EXACT (mult_accum_uns_sat_short (usa_c, usa_d), USACCUM_MAX);
+  CHECK_EXACT (mult_accum_uns_sat_regular (ua_c, ua_d), UACCUM_MAX);
+  CHECK_EXACT (mult_accum_uns_sat_long (ula_c, ula_d), ULACCUM_MAX);
+
+  CHECK_EXACT (div_accum_uns_sat_short (usa_c, usa_e), USACCUM_MAX);
+  CHECK_EXACT (div_accum_uns_sat_regular (ua_c, ua_e), UACCUM_MAX);
+  CHECK_EXACT (div_accum_uns_sat_long (ula_c, ula_e), ULACCUM_MAX);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c
new file mode 100644
index 000000000..078b10374
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fixed_float_conversion.c
@@ -0,0 +1,20 @@
+/* Check that vcvt is used for fixed and float data conversions.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp3_ok } */
+/* { dg-options "-O1" } */
+/* { dg-add-options arm_vfp3 } */
+
+float
+fixed_to_float (int i)
+{
+  return ((float) i / (1 << 16));
+}
+
+int
+float_to_fixed (float f)
+{
+  return ((int) (f * (1 << 16)));
+}
+
+/* { dg-final { scan-assembler "vcvt.f32.s32" } } */
+/* { dg-final { scan-assembler "vcvt.s32.f32" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fma-sp.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma-sp.c
new file mode 100644
index 000000000..e1884545f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma-sp.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicts with multilib options" { ! arm_thumb2_ok } { "-march=*" } { "" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-m4" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfpu=*" } { "-mfpu=fpv4-sp-d16" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-options "-O2 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mthumb -mfloat-abi=hard" } */
+
+#include "fma.h"
+
+/* { dg-final { scan-assembler-not "vfma\.f64\td\[0-9\]" } } */
+/* { dg-final { scan-assembler-times "vfma\.f32\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vfms\.f64\td\[0-9\]" } } */
+/* { dg-final { scan-assembler-times "vfms\.f32\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vfnma\.f64\td\[0-9\]" } } */
+/* { dg-final { scan-assembler-times "vfnma\.f32\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vfnms\.f64\td\[0-9\]" } } */
+/* { dg-final { scan-assembler-times "vfnms\.f32\ts\[0-9\]" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.c
new file mode 100644
index 000000000..704559a57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicts with multilib options" { ! arm_thumb2_ok } { "-mthumb" } { "" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mcpu=*" } { "-mcpu=cortex-a15" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfpu=*" } { "-mfpu=vfpv4" } } */
+/* { dg-skip-if "avoid conflicts with multilib options" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-options "-O2 -mcpu=cortex-a15 -mfpu=vfpv4 -mfloat-abi=hard" } */
+
+#include "fma.h"
+
+/* { dg-final { scan-assembler-times "vfma\.f64\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfma\.f32\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfms\.f64\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfms\.f32\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnma\.f64\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnma\.f32\ts\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnms\.f64\td\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnms\.f32\ts\[0-9\]" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.h b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.h
new file mode 100644
index 000000000..0812c2d73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fma.h
@@ -0,0 +1,50 @@
+extern double fma (double, double, double);
+extern float fmaf (float, float, float);
+
+float
+vfma32 (float x, float y, float z)
+{
+  return fmaf (x, y, z);
+}
+
+float
+vfms32 (float x, float y, float z)
+{
+  return fmaf (-x, y, z);
+}
+
+float
+vfnms32 (float x, float y, float z)
+{
+  return fmaf (x, y, -z);
+}
+
+float
+vfnma32 (float x, float y, float z)
+{
+  return fmaf (-x, y, -z);
+}
+
+double
+vfma64 (double x, double y, double z)
+{
+  return fma (x, y, z);
+}
+
+double
+vfms64 (double x, double y, double z)
+{
+  return fma (-x, y, z);
+}
+
+double
+vfnms64 (double x, double y, double z)
+{
+  return fma (x, y, -z);
+}
+
+double
+vfnma64 (double x, double y, double z)
+{
+  return fma (-x, y, -z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-builtins-1.c
new file mode 100644
index 000000000..868768028
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-builtins-1.c
@@ -0,0 +1,92 @@
+/* Test type-generic builtins with __fp16 arguments.
+   Except as otherwise noted, they should behave exactly
+   the same as those with float arguments.  */
+
+/* { dg-do run } */
+/* { dg-options "-mfp16-format=ieee -std=gnu99" } */
+
+#include <stdlib.h>
+#include <math.h>
+
+volatile __fp16 h1, h2;
+volatile float f1, f2;
+
+void
+set1 (double x)
+{
+  h1 = x;
+  f1 = h1;
+}
+
+void
+set2 (double x, double y)
+{
+  h1 = x;
+  f1 = h1;
+  h2 = y;
+  f2 = h2;
+}
+
+#define test1(p,x)				\
+  set1 (x);					\
+  hp = (p (h1) ? 1 : 0);			\
+  fp = (p (f1) ? 1 : 0);			\
+  if (hp ^ fp) abort ()
+
+#define test2(p,x,y)				\
+  set2 (x,y);					\
+  hp = (p (h1, h2) ? 1 : 0);			\
+  fp = (p (f1, f2) ? 1 : 0);			\
+  if (hp ^ fp) abort ()
+
+int
+main (void)
+{
+  int hp, fp;
+
+  test1 (__builtin_isfinite, 17.0);
+  test1 (__builtin_isfinite, INFINITY);
+  test1 (__builtin_isinf, -0.5);
+  test1 (__builtin_isinf, INFINITY);
+  test1 (__builtin_isnan, 493.0);
+  test1 (__builtin_isnan, NAN);
+  test1 (__builtin_isnormal, 3.14159);
+
+  test2 (__builtin_isgreater, 5.0, 3.0);
+  test2 (__builtin_isgreater, 3.0, 5.0);
+  test2 (__builtin_isgreater, 73.5, 73.5);
+  test2 (__builtin_isgreater, 1.0, NAN);
+
+  test2 (__builtin_isgreaterequal, 5.0, 3.0);
+  test2 (__builtin_isgreaterequal, 3.0, 5.0);
+  test2 (__builtin_isgreaterequal, 73.5, 73.5);
+  test2 (__builtin_isgreaterequal, 1.0, NAN);
+
+  test2 (__builtin_isless, 5.0, 3.0);
+  test2 (__builtin_isless, 3.0, 5.0);
+  test2 (__builtin_isless, 73.5, 73.5);
+  test2 (__builtin_isless, 1.0, NAN);
+
+  test2 (__builtin_islessequal, 5.0, 3.0);
+  test2 (__builtin_islessequal, 3.0, 5.0);
+  test2 (__builtin_islessequal, 73.5, 73.5);
+  test2 (__builtin_islessequal, 1.0, NAN);
+
+  test2 (__builtin_islessgreater, 5.0, 3.0);
+  test2 (__builtin_islessgreater, 3.0, 5.0);
+  test2 (__builtin_islessgreater, 73.5, 73.5);
+  test2 (__builtin_islessgreater, 1.0, NAN);
+
+  test2 (__builtin_isunordered, 5.0, 3.0);
+  test2 (__builtin_isunordered, 3.0, 5.0);
+  test2 (__builtin_isunordered, 73.5, 73.5);
+  test2 (__builtin_isunordered, 1.0, NAN);
+
+  /* Test that __builtin_isnormal recognizes a denormalized __fp16 value,
+     even if it's representable as a normalized float.  */
+  h1 = 5.96046E-8;
+  if (__builtin_isnormal (h1))
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
new file mode 100644
index 000000000..3abcd947a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+__fp16 xx = 0.0;
+
+/* { dg-final { scan-assembler "\t.eabi_attribute 38, 2" } } */
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.space\t2" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
new file mode 100644
index 000000000..2e3d31fdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */
+
+#include <math.h>
+
+/* NaNs are not representable in the alternative format; we should get a
+   diagnostic.  */
+__fp16 xx = NAN; /* { dg-warning "overflow" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c
new file mode 100644
index 000000000..62a7a3df5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */
+
+#include <math.h>
+
+/* Infinities are not representable in the alternative format;
+   we should get a diagnostic, and the value set to the largest
+   representable value.  */
+/* 0x7fff = 32767 */
+__fp16 xx = INFINITY; /* { dg-warning "overflow" } */
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t32767" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c
new file mode 100644
index 000000000..09586e9b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+float xx __attribute__((mode(HF))) = 0.0;
+
+/* { dg-final { scan-assembler "\t.eabi_attribute 38, 2" } } */
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.space\t2" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c
new file mode 100644
index 000000000..b7fe99d53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* 0x3c00 = 15360 */
+__fp16 xx = 1.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t15360" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c
new file mode 100644
index 000000000..f325a84fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* 0xc000 = 49152 */
+__fp16 xx = -2.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t49152" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c
new file mode 100644
index 000000000..4b9b33117
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* 0x7bff = 31743 */
+__fp16 xx = 65504.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t31743" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c
new file mode 100644
index 000000000..458f5073b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* 0x3555 = 13653 */
+__fp16 xx = (1.0/3.0);
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t13653" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c
new file mode 100644
index 000000000..dbb4a9999
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+/* This number is the maximum value representable in the alternative
+   encoding.  */
+/* 0x7fff = 32767 */
+__fp16 xx = 131008.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t32767" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c
new file mode 100644
index 000000000..40940a634
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative -pedantic" } */
+
+/* This number overflows the range of the alternative encoding.  Since this
+   encoding doesn't have infinities, we should get a pedantic warning,
+   and the value should be set to the largest representable value.  */
+/* 0x7fff = 32767 */
+__fp16 xx = 123456789.0;  /* { dg-warning "overflow" } */
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t32767" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c
new file mode 100644
index 000000000..cbc0a3947
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* This is the minimum normalized value.  */
+/* 0x0400 = 1024 */
+__fp16 xx = 6.10352E-5;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t1024" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c
new file mode 100644
index 000000000..6487c8d67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* This is the minimum denormalized value.  */
+/* 0x0001 = 1 */
+__fp16 xx = 5.96046E-8;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-exprtype.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-exprtype.c
new file mode 100644
index 000000000..1d8953b48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-exprtype.c
@@ -0,0 +1,29 @@
+/* Test that expressions involving __fp16 values have the right types.  */
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* This produces a diagnostic if EXPR doesn't have type TYPE.  */
+#define CHECK(expr,type)			\
+  do {						\
+    type v;					\
+    __typeof (expr) *p = &v;			\
+  } while (0);
+
+volatile __fp16 f1;
+volatile __fp16 f2;
+
+int
+main (void)
+{
+  CHECK (f1, __fp16);
+  CHECK (+f1, float);
+  CHECK (-f1, float);
+  CHECK (f1+f2, float);
+  CHECK ((__fp16)(f1+f2), __fp16);
+  CHECK ((__fp16)99.99, __fp16);
+  CHECK ((f1+f2, f1), __fp16);
+}
+
+
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-1.c
new file mode 100644
index 000000000..d5d0ba2e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+__fp16 xx = 0.0;
+
+/* { dg-final { scan-assembler "\t.eabi_attribute 38, 1" } } */
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.space\t2" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-10.c
new file mode 100644
index 000000000..51604374e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-10.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee -std=gnu99" } */
+
+#include <math.h>
+
+/* 0x7e00 = 32256 */
+__fp16 xx = NAN;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t32256" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-11.c
new file mode 100644
index 000000000..afab518b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-11.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee -std=gnu99" } */
+
+#include <math.h>
+
+/* 0x7c00 = 31744 */
+__fp16 xx = INFINITY;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t31744" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-12.c
new file mode 100644
index 000000000..244c96ffd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-12.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+float xx __attribute__((mode(HF))) = 0.0;
+
+/* { dg-final { scan-assembler "\t.eabi_attribute 38, 1" } } */
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.space\t2" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-2.c
new file mode 100644
index 000000000..35f2031c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* 0x3c00 = 15360 */
+__fp16 xx = 1.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t15360" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-3.c
new file mode 100644
index 000000000..90edd0119
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* 0xc000 = 49152 */
+__fp16 xx = -2.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t49152" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-4.c
new file mode 100644
index 000000000..20676d89d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-4.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* 0x7bff = 31743 */
+__fp16 xx = 65504.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t31743" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-5.c
new file mode 100644
index 000000000..aff9e1356
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-5.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* 0x3555 = 13653 */
+__fp16 xx = (1.0/3.0);
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t13653" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-6.c
new file mode 100644
index 000000000..c736e63a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-6.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* This number is too big and is represented as infinity.  */
+/* 0x7c00 = 31744 */
+__fp16 xx = 131008.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t31744" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-7.c
new file mode 100644
index 000000000..93163772b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-7.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee -pedantic" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* This number is too big and is represented as infinity.  */
+/* We should *not* get an overflow warning here.  */
+/* 0x7c00 = 31744 */
+__fp16 xx = 123456789.0;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t31744" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-8.c
new file mode 100644
index 000000000..a9646739f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-8.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* This is the minimum normalized value.  */
+/* 0x0400 = 1024 */
+__fp16 xx = 6.10352E-5;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t1024" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-9.c
new file mode 100644
index 000000000..11b31ce40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-9.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Encoding taken from:  http://en.wikipedia.org/wiki/Half_precision */
+/* This is the minimum denormalized value.  */
+/* 0x0001 = 1 */
+__fp16 xx = 5.96046E-8;
+
+/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
+/* { dg-final { scan-assembler "\t.short\t1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c
new file mode 100644
index 000000000..e91250581
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=none" } */
+
+/* __fp16 type name is not recognized unless you explicitly enable it
+   by selecting -mfp16-format=ieee or -mfp16-format=alternative.  */
+__fp16 xx = 0.0;  /* { dg-error "unknown type name" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c
new file mode 100644
index 000000000..eb7eef5ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=none" } */
+
+/* mode(HF) attributes are not recognized unless you explicitly enable
+   half-precision floating point by selecting -mfp16-format=ieee or
+   -mfp16-format=alternative.  */
+float xx __attribute__((mode(HF))) = 0.0;  /* { dg-error "HF" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c
new file mode 100644
index 000000000..e40e1a3f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_fp16_ok } */
+/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-add-options arm_fp16 } */
+
+/* Test generation of VFP __fp16 instructions.  */
+
+__fp16 h1 = 0.0;
+__fp16 h2 = 1234.0;
+float f1 = 2.0;
+float f2 = -999.9;
+
+void f (void)
+{
+  h1 = f1;
+  f2 = h2;
+}
+
+/* { dg-final { scan-assembler "\tvcvtb.f32.f16" } } */
+/* { dg-final { scan-assembler "\tvcvtb.f16.f32" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-param-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-param-1.c
new file mode 100644
index 000000000..af4845f9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-param-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Functions cannot have parameters of type __fp16.  */
+extern void f (__fp16);		/* { dg-error "parameters cannot have __fp16 type" } */
+extern void (*pf) (__fp16);	/* { dg-error "parameters cannot have __fp16 type" } */
+
+/* These should be OK.  */
+extern void g (__fp16 *);
+extern void (*pg) (__fp16 *);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-return-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-return-1.c
new file mode 100644
index 000000000..f76394126
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-return-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+/* Functions cannot return type __fp16.  */
+extern __fp16 f (void);		/* { dg-error "cannot return __fp16" } */
+extern __fp16 (*pf) (void);	/* { dg-error "cannot return __fp16" } */
+
+/* These should be OK.  */
+extern __fp16 *g (void);
+extern __fp16 *(*pg) (void);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c
new file mode 100644
index 000000000..f50b4475f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c
@@ -0,0 +1,47 @@
+/* Test intermediate rounding of double to float and then to __fp16, using
+   an example of a number that would round differently if it went directly
+   from double to __fp16.  */
+
+/* { dg-do run } */
+/* { dg-options "-mfp16-format=alternative" } */
+
+#include <stdlib.h>
+
+/* The original double value.  */
+#define ORIG 0x1.0020008p0
+
+/* The expected (double)((__fp16)((float)ORIG)) value.  */
+#define ROUNDED 0x1.0000000p0
+
+typedef union u {
+  __fp16 f;
+  unsigned short h;
+} ufh;
+
+ufh s = { ORIG };
+ufh r = { ROUNDED };
+
+double d = ORIG;
+
+int
+main (void)
+{
+  ufh x;
+
+  /* Test that the rounding is correct for static initializers.  */
+  if (s.h != r.h)
+    abort ();
+
+  /* Test that the rounding is correct for a casted constant expression
+     not in a static initializer.  */
+  x.f = (__fp16)ORIG;
+  if (x.h != r.h)
+    abort ();
+
+  /* Test that the rounding is correct for a runtime conversion.  */
+  x.f = (__fp16)d;
+  if (x.h != r.h)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-ieee-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-ieee-1.c
new file mode 100644
index 000000000..866d4d824
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-rounding-ieee-1.c
@@ -0,0 +1,47 @@
+/* Test intermediate rounding of double to float and then to __fp16, using
+   an example of a number that would round differently if it went directly
+   from double to __fp16.  */
+
+/* { dg-do run } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+#include <stdlib.h>
+
+/* The original double value.  */
+#define ORIG 0x1.0020008p0
+
+/* The expected (double)((__fp16)((float)ORIG)) value.  */
+#define ROUNDED 0x1.0000000p0
+
+typedef union u {
+  __fp16 f;
+  unsigned short h;
+} ufh;
+
+ufh s = { ORIG };
+ufh r = { ROUNDED };
+
+double d = ORIG;
+
+int
+main (void)
+{
+  ufh x;
+
+  /* Test that the rounding is correct for static initializers.  */
+  if (s.h != r.h)
+    abort ();
+
+  /* Test that the rounding is correct for a casted constant expression
+     not in a static initializer.  */
+  x.f = (__fp16)ORIG;
+  if (x.h != r.h)
+    abort ();
+
+  /* Test that the rounding is correct for a runtime conversion.  */
+  x.f = (__fp16)d;
+  if (x.h != r.h)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c
new file mode 100644
index 000000000..70c295648
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c
@@ -0,0 +1,21 @@
+/* Test promotion of __fp16 to double as arguments to unprototyped
+   function in another compilation unit.  */
+
+/* { dg-do run } */
+/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-additional-sources "fp16-unprototyped-2.c" } */
+
+#include <stdlib.h>
+
+extern int f ();
+
+static __fp16 x = 42.0;
+static __fp16 y = -42.0;
+
+int
+main (void)
+{
+  if (!f (x, y))
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c
new file mode 100644
index 000000000..0c0f9cda6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+extern int f ();
+
+int
+f (double xx, double yy)
+{
+  if (xx == 42.0 && yy == -42.0)
+    return 1;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-variadic-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-variadic-1.c
new file mode 100644
index 000000000..52b438638
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/fp16-variadic-1.c
@@ -0,0 +1,37 @@
+/* Test promotion of __fp16 to double as arguments to variadic function.  */
+
+/* { dg-do run } */
+/* { dg-options "-mfp16-format=ieee" } */
+
+#include <stdlib.h>
+#include <stdarg.h>
+
+extern int f (int n, ...);
+
+int 
+f (int n, ...)
+{
+  if (n == 2)
+    {
+      double xx, yy;
+      va_list ap;
+      va_start (ap, n);
+      xx = va_arg (ap, double);
+      yy = va_arg (ap, double);
+      va_end (ap);
+      if (xx == 42.0 && yy == -42.0)
+	return 1;
+    }
+  return 0;
+}
+
+static __fp16 x = 42.0;
+static __fp16 y = -42.0;
+
+int
+main (void)
+{
+  if (!f (2, x, y))
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c
new file mode 100644
index 000000000..bb1888e38
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/frame-pointer-1.c
@@ -0,0 +1,42 @@
+/* Check local register variables using a register conventionally 
+   used as the frame pointer aren't clobbered under high register pressure.  */
+/* { dg-do run } */
+/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */
+
+#include <stdlib.h>
+
+int global=5;
+
+void __attribute__((noinline)) foo(int p1, int p2, int p3, int p4)
+{
+  if (global != 5 || p1 != 1 || p2 != 2 || p3 != 3 || p4 != 4)
+    abort();
+}
+
+int __attribute__((noinline)) test(int a, int b, int c, int d)
+{
+  register unsigned long r __asm__("r7") = 0xdeadbeef;
+  int e;
+
+  /* ABCD are live after the call which should be enough
+     to cause r7 to be used if it weren't for the register variable.  */
+  foo(a,b,c,d);
+
+  e = 0;
+  __asm__ __volatile__ ("mov %0, %2"
+			: "=r" (e)
+			: "0" (e), "r" (r));
+
+  global = a+b+c+d;
+
+  return e;
+}
+
+int main()
+{
+  if (test(1, 2, 3, 4) != 0xdeadbeef)
+    abort();
+  if (global != 10)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c
new file mode 100644
index 000000000..4b48ef803
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4-arm.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v4 } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 4
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#include "ftest-support.h"
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c
new file mode 100644
index 000000000..016506f46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-arm.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4t" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v4t } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 4
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c
new file mode 100644
index 000000000..9ef944e5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv4t-thumb.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv4t" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v4t } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 4
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c
new file mode 100644
index 000000000..a9403e97c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-arm.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5t" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v5t } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 5
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c
new file mode 100644
index 000000000..f3ad07ec0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5t-thumb.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5t" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v5t } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 5
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c
new file mode 100644
index 000000000..f98c01a0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-arm.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5te" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v5te } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 5
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c
new file mode 100644
index 000000000..5d71787e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv5te-thumb.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv5te" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v5te } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 5
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c
new file mode 100644
index 000000000..88a508954
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-arm.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v6 } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 4
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c
new file mode 100644
index 000000000..0f42a0ca8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6-thumb.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v6 } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c
new file mode 100644
index 000000000..8de021a0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-arm.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v6k } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c
new file mode 100644
index 000000000..8e4a18804
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6k-thumb.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6k" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v6k } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c
new file mode 100644
index 000000000..ee075e290
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6m-thumb.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6-m" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v6m } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'M'
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c
new file mode 100644
index 000000000..83b4bc4c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-arm.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6t2" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v6t2 } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 4
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c
new file mode 100644
index 000000000..1a1cbc5ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6t2-thumb.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6t2" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v6t2 } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c
new file mode 100644
index 000000000..e2df0d482
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-arm.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6z" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v6z } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 4
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c
new file mode 100644
index 000000000..9761f0a96
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv6z-thumb.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv6z" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v6z } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 6
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 1
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c
new file mode 100644
index 000000000..c71a7cdb7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-arm.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-a" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v7a } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 7
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'A'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c
new file mode 100644
index 000000000..f1f789e8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7a-thumb.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-a" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v7a } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 7
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'A'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c
new file mode 100644
index 000000000..688d766e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7em-thumb.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7e-m" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v7em } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 7
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'M'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 7
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7m-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7m-thumb.c
new file mode 100644
index 000000000..363b48b75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7m-thumb.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=arm7-m" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v7m } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 7
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'M'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 7
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c
new file mode 100644
index 000000000..08c017fc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-arm.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-r" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v7r } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 7
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'R'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c
new file mode 100644
index 000000000..1b69dc0f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7r-thumb.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7-r" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v7r } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 7
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'R'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c
new file mode 100644
index 000000000..3cf987ccc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-arm.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7ve" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v7ve } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 7
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'A'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c
new file mode 100644
index 000000000..0d6b43221
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv7ve-thumb.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv7ve" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v7ve } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 7
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'A'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c
new file mode 100644
index 000000000..7812c5cd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-a" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 8
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'A'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c
new file mode 100644
index 000000000..605b1735e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-march=*" } { "-march=armv8-a" } } */
+/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" } { "" } } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#define NEED_ARM_ARCH
+#define VALUE_ARM_ARCH 8
+
+#define NEED_ARM_ARCH_ISA_ARM
+#define VALUE_ARM_ARCH_ISA_ARM 1
+
+#define NEED_ARM_ARCH_ISA_THUMB
+#define VALUE_ARM_ARCH_ISA_THUMB 2
+
+#define NEED_ARM_ARCH_PROFILE
+#define VALUE_ARM_ARCH_PROFILE 'A'
+
+#define NEED_ARM_FEATURE_UNALIGNED
+#define VALUE_ARM_FEATURE_UNALIGNED 1
+
+#define NEED_ARM_FEATURE_LDREX
+#define VALUE_ARM_FEATURE_LDREX 15
+
+#define NEED_ARM_FEATURE_CLZ
+#define VALUE_ARM_FEATURE_CLZ 1
+
+#define NEED_ARM_FEATURE_DSP
+#define VALUE_ARM_FEATURE_DSP 1
+
+#define NEED_ARM_FEATURE_SIMD32
+#define VALUE_ARM_FEATURE_SIMD32 1
+
+#define NEED_ARM_FEATURE_QBIT
+#define VALUE_ARM_FEATURE_QBIT 1
+
+#define NEED_ARM_FEATURE_SAT
+#define VALUE_ARM_FEATURE_SAT 1
+
+#include "ftest-support.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-support.h b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-support.h
new file mode 100644
index 000000000..c56d2d588
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ftest-support.h
@@ -0,0 +1,156 @@
+/* For each of several ARM architecture features, check that relevant
+   macros are defined or not, and that they have the expected values.  */
+
+#ifdef NEED_ARM_ARCH
+# ifdef __ARM_ARCH
+#  if __ARM_ARCH != VALUE_ARM_ARCH
+#   error __ARM_ARCH has unexpected value
+#  endif
+# else
+#  error __ARM_ARCH is not defined but should be
+# endif
+#else
+# ifdef __ARM_ARCH
+#  error __ARM_ARCH is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_ARCH_ISA_ARM
+# ifdef __ARM_ARCH_ISA_ARM
+#  if __ARM_ARCH_ISA_ARM != VALUE_ARM_ARCH_ISA_ARM
+#   error __ARM_ARCH_ISA_ARM has unexpected value
+#  endif
+# else
+#  error __ARM_ARCH_ISA_ARM is not defined but should be
+# endif
+#else
+# ifdef __ARM_ARCH_ISA_ARM
+#  error __ARM_ARCH_ISA_ARM is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_ARCH_ISA_THUMB
+# ifdef __ARM_ARCH_ISA_THUMB
+#  if __ARM_ARCH_ISA_THUMB != VALUE_ARM_ARCH_ISA_THUMB
+#   error __ARM_ARCH_ISA_THUMB has unexpected value
+#  endif
+# else
+#  error __ARM_ARCH_ISA_THUMB is not defined but should be
+# endif
+#else
+# ifdef __ARM_ARCH_ISA_THUMB
+#  error __ARM_ARCH_ISA_THUMB is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_ARCH_PROFILE
+# ifdef __ARM_ARCH_PROFILE
+#  if __ARM_ARCH_PROFILE != VALUE_ARM_ARCH_PROFILE
+#   error __ARM_ARCH_PROFILE has unexpected value
+#  endif
+# else
+#  error __ARM_ARCH_PROFILE is not defined but should be
+# endif
+#else
+# ifdef __ARM_ARCH_PROFILE
+#  error __ARM_ARCH_PROFILE is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_FEATURE_UNALIGNED
+# ifdef __ARM_FEATURE_UNALIGNED
+#  if __ARM_FEATURE_UNALIGNED != VALUE_ARM_FEATURE_UNALIGNED
+#   error __ARM_FEATURE_UNALIGNED has unexpected value
+#  endif
+# else
+#  error __ARM_FEATURE_UNALIGNED is not defined but should be
+# endif
+#else
+# ifdef __ARM_FEATURE_UNALIGNED
+#  error __ARM_FEATURE_UNALIGNED is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_FEATURE_LDREX
+# ifdef __ARM_FEATURE_LDREX
+#  if __ARM_FEATURE_LDREX != VALUE_ARM_FEATURE_LDREX
+#   error __ARM_FEATURE_LDREX has unexpected value
+#  endif
+# else
+#  error __ARM_FEATURE_LDREX is not defined but should be
+# endif
+#else
+# ifdef __ARM_FEATURE_LDREX
+#  error __ARM_FEATURE_LDREX is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_FEATURE_CLZ
+# ifdef __ARM_FEATURE_CLZ
+#  if __ARM_FEATURE_CLZ != VALUE_ARM_FEATURE_CLZ
+#   error __ARM_FEATURE_CLZ has unexpected value
+#  endif
+# else
+#  error __ARM_FEATURE_CLZ is not defined but should be
+# endif
+#else
+# ifdef __ARM_FEATURE_CLZ
+#  error __ARM_FEATURE_CLZ is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_FEATURE_DSP
+# ifdef __ARM_FEATURE_DSP
+#  if __ARM_FEATURE_DSP != VALUE_ARM_FEATURE_DSP
+#   error __ARM_FEATURE_DSP has unexpected value
+#  endif
+# else
+#  error __ARM_FEATURE_DSP is not defined but should be
+# endif
+#else
+# ifdef __ARM_FEATURE_DSP
+#  error __ARM_FEATURE_DSP is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_FEATURE_SIMD32
+# ifdef __ARM_FEATURE_SIMD32
+#  if __ARM_FEATURE_SIMD32 != VALUE_ARM_FEATURE_SIMD32
+#   error __ARM_FEATURE_SIMD32 has unexpected value
+#  endif
+# else
+#  error __ARM_FEATURE_SIMD32 is not defined but should be
+# endif
+#else
+# ifdef __ARM_FEATURE_SIMD32
+#  error __ARM_FEATURE_SIMD32 is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_FEATURE_QBIT
+# ifdef __ARM_FEATURE_QBIT
+#  if __ARM_FEATURE_QBIT != VALUE_ARM_FEATURE_QBIT
+#   error __ARM_FEATURE_QBIT has unexpected value
+#  endif
+# else
+#  error __ARM_FEATURE_QBIT is not defined but should be
+# endif
+#else
+# ifdef __ARM_FEATURE_QBIT
+#  error __ARM_FEATURE_QBIT is defined but should not be
+# endif
+#endif
+
+#ifdef NEED_ARM_FEATURE_SAT
+# ifdef __ARM_FEATURE_SAT
+#  if __ARM_FEATURE_SAT != VALUE_ARM_FEATURE_SAT
+#   error __ARM_FEATURE_SAT has unexpected value
+#  endif
+# else
+#  error __ARM_FEATURE_SAT is not defined but should be
+# endif
+#else
+# ifdef __ARM_FEATURE_SAT
+#  error __ARM_FEATURE_SAT is defined but should not be
+# endif
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/g2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/g2.c
new file mode 100644
index 000000000..85ba1906a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/g2.c
@@ -0,0 +1,22 @@
+/* Verify that hardware multiply is preferred on XScale. */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=xscale -O2" } */
+/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */
+/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */
+/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
+/* { dg-require-effective-target arm32 } */
+
+/* Brett Gaines' test case. */
+unsigned BCPL(unsigned) __attribute__ ((naked));
+unsigned BCPL(unsigned seed)
+{
+    /* Best code would be:
+       ldr r1, =2147001325
+       ldr r2, =715136305
+       mla r0, r1, r0, r2
+       mov pc, lr */
+
+    return seed * 2147001325U + 715136305U;
+}
+
+/* { dg-final { scan-assembler "mla\[ 	].*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/handler-align.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/handler-align.c
new file mode 100644
index 000000000..6c5187b20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/handler-align.c
@@ -0,0 +1,42 @@
+/* Test epilogue of a realigned interrupt handler. */
+/* { dg-do run } */
+/* { dg-options "-mthumb -Os" } */
+/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-require-effective-target arm_cortex_m } */
+/* { dg-require-effective-target arm_eabi } */
+
+extern __attribute__((noreturn)) void abort(void);
+extern int snprintf(char *, int, const char *, ...);
+
+#define BUFF_LEN 256
+char buff[BUFF_LEN];
+
+char *get_buffer(void)
+{
+	return buff;
+}
+
+void __attribute__((interrupt)) foo(void)
+{
+        char *msg = get_buffer();
+        snprintf(msg, BUFF_LEN, "%d %p", 1, buff+BUFF_LEN);
+}
+
+volatile void * save_sp;
+int main()
+{
+	register volatile void * sp asm("sp");
+	/* Check stack pointer before/after calling the interrupt
+         * handler. Not equal means that handler doesn't restore
+         * stack correctly.  */
+	save_sp = sp;
+	foo();
+	/* Abort here instead of return non-zero. Due to wrong sp, lr value,
+	 * returning from main may not work.  */
+	if (save_sp != sp)
+	{
+		sp = save_sp;
+		abort();
+	}
+	return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-1.c
new file mode 100644
index 000000000..218c6a21e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile }  */
+/* { dg-options "-O2" }  */
+/* { dg-final { scan-assembler-times "#120" 1 } } */
+
+extern void foo1 (int);
+extern void foo2 (int);
+
+void t (int x, int y)
+{
+  if (y < 5)
+    foo1 (120);
+  else
+    foo2 (120);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-2.c
new file mode 100644
index 000000000..17d8e9365
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/headmerge-2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile }  */
+/* { dg-options "-O2" }  */
+/* { dg-final { scan-assembler-times "120\n" 1 } } */
+
+extern void foo1 (int);
+extern void foo2 (int);
+extern void foo3 (int);
+extern void foo4 (int);
+extern void foo5 (int);
+extern void foo6 (int);
+
+void t (int x, int y)
+{
+  switch (y)
+    {
+    case 1:
+      foo1 (120);
+      break;
+    case 5:
+      foo2 (120);
+      break;
+    case 7:
+      foo3 (120);
+      break;
+    case 10:
+      foo4 (120);
+      break;
+    case 13:
+      foo5 (120);
+      break;
+    default:
+      foo6 (120);
+      break;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-1.c
new file mode 100644
index 000000000..a38424228
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-1.c
@@ -0,0 +1,17 @@
+/* Verify that prologue and epilogue are correct for functions with
+   __attribute__ ((interrupt)).  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_nothumb } */
+/* { dg-options "-O0 -marm" } */
+
+/* This test is not valid when -mthumb.  */
+extern void bar (int);
+extern void foo (void) __attribute__ ((interrupt("IRQ")));
+
+void foo ()
+{
+  bar (0);
+}
+
+/* { dg-final { scan-assembler "stmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, lr}" } } */
+/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, fp, ip, pc}\\^" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-2.c
new file mode 100644
index 000000000..61d313053
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/interrupt-2.c
@@ -0,0 +1,19 @@
+/* Verify that prologue and epilogue are correct for functions with
+   __attribute__ ((interrupt)).  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_nothumb } */
+/* { dg-options "-O1 -marm" } */
+
+/* This test is not valid when -mthumb.  */
+extern void bar (int);
+extern void test (void) __attribute__((__interrupt__));
+
+int foo;
+void test()
+{
+  bar (foo);
+  foo = 0;
+}
+
+/* { dg-final { scan-assembler "stmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, lr}" } } */
+/* { dg-final { scan-assembler "ldmfd\tsp!, {r0, r1, r2, r3, r4, r5, ip, pc}\\^" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/iordi3-opt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/iordi3-opt.c
new file mode 100644
index 000000000..b3f465b74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/iordi3-opt.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+unsigned long long or64 (unsigned long long input)
+{
+    return input | 0x200000004ULL;
+}
+
+/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/its.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/its.c
new file mode 100644
index 000000000..5425f1e92
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/its.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+int test (int a, int b)
+{
+  int r;
+  if (a > 10)
+    {
+      r = a - b;
+      r += 10;
+    }
+  else
+    {
+      r = b - a;
+      r -= 7;
+    }
+  if (r > 0)
+    r -= 3;
+  return r;
+}
+/* { dg-final { scan-assembler-times "\tit" 2 { target arm_thumb2 } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-2.c
new file mode 100644
index 000000000..2cf637230
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-2.c
@@ -0,0 +1,19 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
+
+extern void foo2 (short*);
+
+void
+tr4 (short array[], int n)
+{
+  int x;
+  if (n > 0)
+    for (x = 0; x < n; x++)
+      foo2 (&array[x]);
+}
+
+/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */
+/* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */
+/* { dg-final { object-size text <= 26 { target arm_thumb2 } } } */
+/* { dg-final { cleanup-tree-dump "ivopts" } } */
+/* { dg-final { cleanup-saved-temps "ivopts" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-3.c
new file mode 100644
index 000000000..11d9aac80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-3.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
+
+extern unsigned int foo2 (short*) __attribute__((pure));
+
+unsigned int
+tr3 (short array[], unsigned int n)
+{
+  int sum = 0;
+  unsigned int x;
+  for (x = 0; x < n; ++x)
+    sum += foo2 (&array[x]);
+  return sum;
+}
+
+/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */
+/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */
+/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */
+/* { dg-final { object-size text <= 30 { target arm_thumb2 } } } */
+/* { dg-final { cleanup-tree-dump "ivopts" } } */
+/* { dg-final { cleanup-saved-temps "ivopts" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-4.c
new file mode 100644
index 000000000..0c476b874
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-4.c
@@ -0,0 +1,22 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
+
+extern unsigned int foo (int*) __attribute__((pure));
+
+unsigned int
+tr2 (int array[], int n)
+{
+  unsigned int sum = 0;
+  int x;
+  if (n > 0)
+    for (x = 0; x < n; x++)
+      sum += foo (&array[x]);
+  return sum;
+}
+
+/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */
+/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */
+/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */
+/* { dg-final { object-size text <= 36 { target arm_thumb2 } } } */
+/* { dg-final { cleanup-tree-dump "ivopts" } } */
+/* { dg-final { cleanup-saved-temps "ivopts" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-5.c
new file mode 100644
index 000000000..0f9023808
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-5.c
@@ -0,0 +1,21 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
+
+extern unsigned int foo (int*) __attribute__((pure));
+
+unsigned int
+tr1 (int array[], unsigned int n)
+{
+  int sum = 0;
+  unsigned int x;
+  for (x = 0; x < n; ++x)
+    sum += foo (&array[x]);
+  return sum;
+}
+
+/* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */
+/* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */
+/* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */
+/* { dg-final { object-size text <= 30 { target arm_thumb2 } } } */
+/* { dg-final { cleanup-tree-dump "ivopts" } } */
+/* { dg-final { cleanup-saved-temps "ivopts" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c
new file mode 100644
index 000000000..f466ff35f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts-orig_biv-inc.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
+/* { dg-skip-if "" { arm_thumb1 } } */
+
+extern char *__ctype_ptr__;
+
+unsigned char * foo(unsigned char *ReadPtr)
+{
+
+ unsigned char c;
+
+ while (!(((__ctype_ptr__+sizeof(""[*ReadPtr]))[(int)(*ReadPtr)])&04) == (!(0)))
+  ReadPtr++;
+
+ return ReadPtr;
+}
+
+/* { dg-final { scan-tree-dump-times "original biv" 2 "ivopts"} } */
+/* { dg-final { cleanup-tree-dump "ivopts" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts.c
new file mode 100644
index 000000000..8183d1d5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ivopts.c
@@ -0,0 +1,18 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
+
+void
+tr5 (short array[], int n)
+{
+  int x;
+  if (n > 0)
+    for (x = 0; x < n; x++)
+      array[x] = 0;
+}
+
+/* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */
+/* { dg-final { object-size text <= 20 { target arm_thumb2 } } } */
+/* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */
+/* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok }  } } } */
+/* { dg-final { cleanup-tree-dump "ivopts" } } */
+/* { dg-final { cleanup-saved-temps "ivopts" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/ldrd-strd-offset.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/ldrd-strd-offset.c
new file mode 100644
index 000000000..a128a0a0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/ldrd-strd-offset.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct
+{
+  int x;
+  int i, j;
+} off_struct;
+
+int foo (char *str, int *a, int b, int c)
+{
+  off_struct *p = (off_struct *)(str + 3);
+  b = p->i;
+  c = p->j;
+  *a = b + c;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-1.c
new file mode 100644
index 000000000..f10f10606
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-1.c
@@ -0,0 +1,134 @@
+/* Check that long calls to different sections are not optimized to "bl".  */
+/* { dg-do compile { target { arm32 && nonpic } } } */
+/* { dg-options "-O2" } */
+/* This test expects that short calls are the default.  */
+/* { dg-skip-if "-mlong-calls in use" { "*-*-*" } { "-mlong-calls" } { "" } } */
+
+#define section(S) __attribute__((section(S)))
+#define weak __attribute__((weak))
+#define noinline __attribute__((noinline))
+#define long_call __attribute__((long_call))
+#define short_call __attribute__((short_call))
+
+#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS ID (void);					\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }
+
+#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS noinline ID (void) { return #ID; }		\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  static const char *TARGET_ATTRS noinline ID (void) { return #ID; }	\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS)			\
+  TEST (ID##1, TARGET_ATTRS, )						\
+  TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b"))	\
+  TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c"))
+
+#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS)			\
+  DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS)				\
+  DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call)		\
+  DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call)
+
+DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,)
+DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,)
+DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak)
+DO_TESTS_CALL_ATTR (static_, STATIC_CALL,)
+
+
+/* Calls to remote_* should honor the call type attribute,
+   with "short" being the default.
+
+   In the regular expressions below:
+   
+   * We allow both "b" and "bl" in some cases to allow for the
+     possibility of sibling calls.  As of this writing, GCC does not
+     use sibling calls in Thumb-2 mode.  */
+
+/* { dg-final { scan-assembler "\tbl\tremote_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_n3\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tremote_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s3\n" } } */
+
+
+/* Calls to strong_*2 calls should honor the call type attribute,
+   with "short" being the default.  Calls to other strong_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_l1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_l3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s3\n" } } */
+
+
+/* Calls to weak_* should honor the call type attribute,
+   with "short" being the default.  */
+
+/* { dg-final { scan-assembler "\tbl\tweak_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n3\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tweak_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s3\n" } } */
+
+
+/* Calls to static_*2 calls should honor the call type attribute,
+   with "short" being the default.  Calls to other static_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_l1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_l3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s3\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-2.c
new file mode 100644
index 000000000..8ce2404c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-2.c
@@ -0,0 +1,127 @@
+/* Check that long calls to different sections are not optimized to "bl".  */
+/* { dg-do compile { target { arm32 && nonpic } } } */
+/* { dg-options "-O2 -mlong-calls" } */
+
+#define section(S) __attribute__((section(S)))
+#define weak __attribute__((weak))
+#define noinline __attribute__((noinline))
+#define long_call __attribute__((long_call))
+#define short_call __attribute__((short_call))
+
+#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS ID (void);					\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }
+
+#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS noinline ID (void) { return #ID; }		\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  static const char *TARGET_ATTRS noinline ID (void) { return #ID; }	\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS)			\
+  TEST (ID##1, TARGET_ATTRS, )						\
+  TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b"))	\
+  TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c"))
+
+#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS)			\
+  DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS)				\
+  DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call)		\
+  DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call)
+
+DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,)
+DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,)
+DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak)
+DO_TESTS_CALL_ATTR (static_, STATIC_CALL,)
+
+
+/* Calls to remote_* should honor the call type attribute,
+   with "long" being the default.
+
+   In the regular expressions below:
+   
+   * We allow both "b" and "bl" in some cases to allow for the
+     possibility of sibling calls.  As of this writing, GCC does not
+     use sibling calls in Thumb-2 mode.  */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_n1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_n2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_n3\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tremote_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s3\n" } } */
+
+
+/* Calls to strong_*2 calls should honor the call type attribute,
+   with "long" being the default.  Calls to other strong_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tstrong_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_l1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_l3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s3\n" } } */
+
+
+/* Calls to weak_* should honor the call type attribute,
+   with "long" being the default.  */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n3\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l2\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tweak_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s3\n" } } */
+
+
+/* Calls to static_*2 calls should honor the call type attribute,
+   with "long" being the default.  Calls to other static_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_n1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_n2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_l1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l1\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_l3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l3\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s1\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s2\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s3\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s3\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-3.c
new file mode 100644
index 000000000..bd1891c00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-3.c
@@ -0,0 +1,126 @@
+/* Check that long calls to different sections are not optimized to "bl".  */
+/* { dg-do compile { target { arm32 && fpic } } } */
+/* { dg-options "-O2 -fpic" } */
+
+#define section(S) __attribute__((section(S)))
+#define weak __attribute__((weak))
+#define noinline __attribute__((noinline))
+#define long_call __attribute__((long_call))
+#define short_call __attribute__((short_call))
+
+#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS ID (void);					\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }
+
+#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS noinline ID (void) { return #ID; }		\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  static const char *TARGET_ATTRS noinline ID (void) { return #ID; }	\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS)			\
+  TEST (ID##1, TARGET_ATTRS, )						\
+  TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b"))	\
+  TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c"))
+
+#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS)			\
+  DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS)				\
+  DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call)		\
+  DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call)
+
+DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,)
+DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,)
+DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak)
+DO_TESTS_CALL_ATTR (static_, STATIC_CALL,)
+
+
+/* Calls to remote_*, strong_* and weak_* should honor the call type
+   attribute, with "short" being the default.  
+
+   In the regular expressions below:
+   
+   * The PLT marker is optional, even though we are using -fpic,
+     because it is not used (or required) on some targets.
+
+   * We allow both "b" and "bl" in some cases to allow for the
+     possibility of sibling calls.  As of this writing, GCC does not
+     use sibling calls in Thumb-2 mode.  */
+
+/* { dg-final { scan-assembler "\tbl\tremote_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tremote_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s3(\\(PLT\\))?\n" } } */
+
+
+/* { dg-final { scan-assembler "\tbl\tstrong_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_n3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tstrong_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tstrong_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s3(\\(PLT\\))?\n" } } */
+
+
+/* { dg-final { scan-assembler "\tbl\tweak_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_n3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tweak_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s3(\\(PLT\\))?\n" } } */
+
+
+/* Calls to static_*2 calls should honor the call type attribute,
+   with "short" being the default.  Calls to other static_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_n1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n3((\\(PLT\\))?)\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_l1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_l3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l3((\\(PLT\\))?)\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_s1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s3((\\(PLT\\))?)\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-4.c
new file mode 100644
index 000000000..dc184b8f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/long-calls-4.c
@@ -0,0 +1,119 @@
+/* Check that long calls to different sections are not optimized to "bl".  */
+/* { dg-do compile { target { arm32 && fpic } } } */
+/* { dg-options "-O2 -fpic -mlong-calls" } */
+
+#define section(S) __attribute__((section(S)))
+#define weak __attribute__((weak))
+#define noinline __attribute__((noinline))
+#define long_call __attribute__((long_call))
+#define short_call __attribute__((short_call))
+
+#define REMOTE_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS ID (void);					\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }
+
+#define EXTERN_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  const char *TARGET_ATTRS noinline ID (void) { return #ID; }		\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define STATIC_CALL(ID, TARGET_ATTRS, CALL_ATTRS)			\
+  static const char *TARGET_ATTRS noinline ID (void) { return #ID; }	\
+  const char *CALL_ATTRS call_##ID (void) { return ID () + 1; }		\
+  const char *CALL_ATTRS sibcall_##ID (void) { return ID (); }
+
+#define DO_TESTS_SECTION(ID, TEST, TARGET_ATTRS)			\
+  TEST (ID##1, TARGET_ATTRS, )						\
+  TEST (ID##2, TARGET_ATTRS section (".test.a"), section (".test.b"))	\
+  TEST (ID##3, TARGET_ATTRS section (".test.c"), section (".test.c"))
+
+#define DO_TESTS_CALL_ATTR(ID, TEST, TARGET_ATTRS)			\
+  DO_TESTS_SECTION (ID##n, TEST, TARGET_ATTRS)				\
+  DO_TESTS_SECTION (ID##l, TEST, TARGET_ATTRS long_call)		\
+  DO_TESTS_SECTION (ID##s, TEST, TARGET_ATTRS short_call)
+
+DO_TESTS_CALL_ATTR (remote_, REMOTE_CALL,)
+DO_TESTS_CALL_ATTR (strong_, EXTERN_CALL,)
+DO_TESTS_CALL_ATTR (weak_, EXTERN_CALL, weak)
+DO_TESTS_CALL_ATTR (static_, STATIC_CALL,)
+
+
+/* Calls to remote_*, strong_* and weak_* should honor the call type
+   attribute, with "long" being the default.  
+
+   In the regular expressions below:
+   
+   * The PLT marker is optional, even though we are using -fpic,
+     because it is not used (or required) on some targets.
+
+   * We allow both "b" and "bl" in some cases to allow for the
+     possibility of sibling calls.  As of this writing, GCC does not
+     use sibling calls in Thumb-2 mode.  */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl\tremote_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl\tremote_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tremote_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tremote_s3(\\(PLT\\))?\n" } } */
+
+
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstrong_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstrong_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstrong_s3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstrong_s3(\\(PLT\\))?\n" } } */
+
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_n3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tweak_l3(\\(PLT\\))?\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tweak_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s1(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s2(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl\tweak_s3(\\(PLT\\))?\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tweak_s3(\\(PLT\\))?\n" } } */
+
+
+/* Calls to static_*2 calls should honor the call type attribute,
+   with "long" being the default.  Calls to other static_* functions
+   should be short.  */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_n1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_n2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_n3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_n3((\\(PLT\\))?)\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_l1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler-not "\tbl?\tstatic_l2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_l3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_l3((\\(PLT\\))?)\n" } } */
+
+/* { dg-final { scan-assembler "\tbl\tstatic_s1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s1((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s2((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl\tstatic_s3((\\(PLT\\))?)\n" } } */
+/* { dg-final { scan-assembler "\tbl?\tstatic_s3((\\(PLT\\))?)\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1189445.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1189445.c
new file mode 100644
index 000000000..766748e55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1189445.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon } */
+/* { dg-add-options arm_neon } */
+/* { dg-options "-O3" } */
+
+int id;
+int
+test (const long int *data)
+{
+  int i, retval;
+  retval = id;
+  for (i = 0; i < id; i++)
+    {
+      retval &= (data[i] <= 0);
+    }
+
+  return (retval);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1243022.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1243022.c
new file mode 100644
index 000000000..cb405908e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/lp1243022.c
@@ -0,0 +1,201 @@
+/* { dg-do compile { target arm_thumb2 } } */
+/* { dg-options "-O2 -fdump-rtl-subreg2" } */
+
+/* { dg-final { scan-rtl-dump "REG_INC" "subreg2" { target { ! arm_neon } } } } */
+/* { dg-final { cleanup-rtl-dump "subreg2" } } */
+struct device;
+typedef unsigned int __u32;
+typedef unsigned long long u64;
+typedef __u32 __le32;
+typedef u64 dma_addr_t;
+typedef unsigned gfp_t;
+int dev_warn (const struct device *dev, const char *fmt, ...);
+struct usb_bus
+{
+    struct device *controller;
+};
+struct usb_hcd
+{
+    struct usb_bus self;
+};
+struct xhci_generic_trb
+{
+    __le32 field[4];
+};
+union xhci_trb
+{
+    struct xhci_generic_trb generic;
+};
+struct xhci_segment
+{
+    union xhci_trb *trbs;
+    dma_addr_t dma;
+};
+struct xhci_ring
+{
+    struct xhci_segment *first_seg;
+};
+struct xhci_hcd
+{
+    struct xhci_ring *cmd_ring;
+    struct xhci_ring *event_ring;
+};
+struct usb_hcd *xhci_to_hcd (struct xhci_hcd *xhci)
+{
+}
+dma_addr_t xhci_trb_virt_to_dma (struct xhci_segment * seg,
+				 union xhci_trb * trb);
+struct xhci_segment *trb_in_td (struct xhci_segment *start_seg,
+				dma_addr_t suspect_dma);
+xhci_test_trb_in_td (struct xhci_hcd *xhci, struct xhci_segment *input_seg,
+		     union xhci_trb *start_trb, union xhci_trb *end_trb,
+		     dma_addr_t input_dma, struct xhci_segment *result_seg,
+		     char *test_name, int test_number)
+{
+    unsigned long long start_dma;
+    unsigned long long end_dma;
+    struct xhci_segment *seg;
+    start_dma = xhci_trb_virt_to_dma (input_seg, start_trb);
+    end_dma = xhci_trb_virt_to_dma (input_seg, end_trb);
+    {
+        dev_warn (xhci_to_hcd (xhci)->self.controller,
+                  "%d\n", test_number);
+        dev_warn (xhci_to_hcd (xhci)->self.controller,
+                  "Expected seg %p, got seg %p\n", result_seg, seg);
+    }
+}
+xhci_check_trb_in_td_math (struct xhci_hcd *xhci, gfp_t mem_flags)
+{
+    struct
+    {
+        dma_addr_t input_dma;
+        struct xhci_segment *result_seg;
+    }
+    simple_test_vector[] =
+        {
+            {
+                0, ((void *) 0)
+            }
+            ,
+            {
+                xhci->event_ring->first_seg->dma - 16, ((void *) 0)}
+            ,
+            {
+                xhci->event_ring->first_seg->dma - 1, ((void *) 0)}
+            ,
+            {
+                xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg}
+            ,
+            {
+                xhci->event_ring->first_seg->dma + (64 - 1) * 16,
+                xhci->event_ring->first_seg
+            }
+            ,
+            {
+                xhci->event_ring->first_seg->dma + (64 - 1) * 16 + 1, ((void *) 0)}
+            ,
+            {
+                xhci->event_ring->first_seg->dma + (64) * 16, ((void *) 0)}
+            ,
+            {
+                (dma_addr_t) (~0), ((void *) 0)
+            }
+        };
+    struct
+    {
+        struct xhci_segment *input_seg;
+        union xhci_trb *start_trb;
+        union xhci_trb *end_trb;
+        dma_addr_t input_dma;
+        struct xhci_segment *result_seg;
+    }
+    complex_test_vector[] =
+        {
+            {
+                .input_seg = xhci->event_ring->first_seg,.start_trb =
+                xhci->event_ring->first_seg->trbs,.end_trb =
+                &xhci->event_ring->first_seg->trbs[64 - 1],.input_dma =
+                xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0),
+            }
+            ,
+            {
+                .input_seg = xhci->event_ring->first_seg,.start_trb =
+                xhci->event_ring->first_seg->trbs,.end_trb =
+                &xhci->cmd_ring->first_seg->trbs[64 - 1],.input_dma =
+                xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0),
+            }
+            ,
+            {
+                .input_seg = xhci->event_ring->first_seg,.start_trb =
+                xhci->cmd_ring->first_seg->trbs,.end_trb =
+                &xhci->cmd_ring->first_seg->trbs[64 - 1],.input_dma =
+                xhci->cmd_ring->first_seg->dma,.result_seg = ((void *) 0),
+            }
+            ,
+            {
+                .input_seg = xhci->event_ring->first_seg,.start_trb =
+                &xhci->event_ring->first_seg->trbs[0],.end_trb =
+                &xhci->event_ring->first_seg->trbs[3],.input_dma =
+                xhci->event_ring->first_seg->dma + 4 * 16,.result_seg = ((void *) 0),
+            }
+            ,
+            {
+                .input_seg = xhci->event_ring->first_seg,.start_trb =
+                &xhci->event_ring->first_seg->trbs[3],.end_trb =
+                &xhci->event_ring->first_seg->trbs[6],.input_dma =
+                xhci->event_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0),
+            }
+            ,
+            {
+                .input_seg = xhci->event_ring->first_seg,.start_trb =
+                &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb =
+                &xhci->event_ring->first_seg->trbs[1],.input_dma =
+                xhci->event_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0),
+            }
+            ,
+            {
+                .input_seg = xhci->event_ring->first_seg,.start_trb =
+                &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb =
+                &xhci->event_ring->first_seg->trbs[1],.input_dma =
+                xhci->event_ring->first_seg->dma + (64 - 4) * 16,.result_seg =
+                ((void *) 0),
+            }
+            ,
+            {
+                .input_seg = xhci->event_ring->first_seg,.start_trb =
+                &xhci->event_ring->first_seg->trbs[64 - 3],.end_trb =
+                &xhci->event_ring->first_seg->trbs[1],.input_dma =
+                xhci->cmd_ring->first_seg->dma + 2 * 16,.result_seg = ((void *) 0),
+            }
+        };
+    unsigned int num_tests;
+    int i, ret;
+    num_tests =
+        (sizeof (simple_test_vector) / sizeof ((simple_test_vector)[0]) +
+         (sizeof (struct
+             {
+         }
+             )));
+    for (i = 0; i < num_tests; i++)
+    {
+        ret =
+            xhci_test_trb_in_td (xhci, xhci->event_ring->first_seg,
+                                 xhci->event_ring->first_seg->trbs,
+                                 &xhci->event_ring->first_seg->trbs[64 - 1],
+                                 simple_test_vector[i].input_dma,
+                                 simple_test_vector[i].result_seg, "Simple", i);
+        if (ret < 0)
+            return ret;
+    }
+    for (i = 0; i < num_tests; i++)
+    {
+        ret =
+            xhci_test_trb_in_td (xhci, complex_test_vector[i].input_seg,
+                                 complex_test_vector[i].start_trb,
+                                 complex_test_vector[i].end_trb,
+                                 complex_test_vector[i].input_dma,
+                                 complex_test_vector[i].result_seg, "Complex", i);
+        if (ret < 0)
+            return ret;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/minmax_minus.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/minmax_minus.c
new file mode 100644
index 000000000..906342a87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/minmax_minus.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_cond_exec } */
+/* { dg-options "-O2" } */
+
+#define MAX(a, b) (a > b ? a : b)
+int
+foo (int a, int b, int c)
+{
+  return c - MAX (a, b);
+}
+
+/* { dg-final { scan-assembler-not "mov" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-1.c
new file mode 100644
index 000000000..42101ef37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { arm_thumb1 } { "*" } { "" } } */
+/* { dg-options "-O2" } */
+
+
+int
+foo (int *p, int *q)
+{
+  int i;
+  int accum = 0;
+
+  for (i = 0 ; i < 1024; i++)
+    {
+      accum += ((*p--) * (*q++));
+      accum += 4096;
+      accum >>= 13 ;
+    }
+
+  return accum;
+}
+
+/* { dg-final { scan-assembler "mla\\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-2.c
new file mode 100644
index 000000000..1e3ca200b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/mla-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O2" } */
+
+long long foolong (long long x, short *a, short *b)
+{
+    return x + *a * *b;
+}
+
+/* { dg-final { scan-assembler "smlalbb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-1.c
new file mode 100644
index 000000000..d13c98284
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-1.c
@@ -0,0 +1,25 @@
+/* Verify that if IP is saved to ensure stack alignment, we don't load
+   it into sp.  */
+/* { dg-do compile } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
+/* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-require-effective-target arm_iwmmxt_ok } */
+/* { dg-final { scan-assembler "ldmfd\[ 	]sp!.*ip,\[ ]*pc" } } */
+
+/* This function uses all the call-saved registers, namely r4, r5, r6,
+   r7, r8, r9, sl, fp.  Since we also save lr, that leaves an odd
+   number of registers, and the compiler will push ip to align the
+   stack.  Make sure that we restore ip into ip, not into sp as is
+   done when using a frame pointer.  The -mno-apcs-frame option
+   permits the frame pointer to be used as an ordinary register.  */
+
+void
+foo(void)
+{
+  __asm volatile ("" : : :
+		  "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "lr");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-2.c
new file mode 100644
index 000000000..0540f659d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/mmx-2.c
@@ -0,0 +1,166 @@
+/* { dg-do compile } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mcpu=*" } { "-mcpu=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-mabi=*" } { "-mabi=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to the iWMMXt" { arm*-*-* } { "-march=*" } { "-march=iwmmxt" } } */
+/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-require-effective-target arm_iwmmxt_ok } */
+/* { dg-options "-mcpu=iwmmxt -flax-vector-conversions -std=gnu99" } */
+
+/* Internal data types for implementing the intrinsics.  */
+typedef int __v2si __attribute__ ((vector_size (8)));
+typedef short __v4hi __attribute__ ((vector_size (8)));
+typedef signed char __v8qi __attribute__ ((vector_size (8)));
+
+void
+foo(void)
+{
+  volatile int isink;
+  volatile long long llsink;
+  volatile __v8qi v8sink;
+  volatile __v4hi v4sink;
+  volatile __v2si v2sink;
+
+  isink = __builtin_arm_getwcgr0 ();
+  __builtin_arm_setwcgr0 (isink);
+  isink = __builtin_arm_getwcgr1 ();
+  __builtin_arm_setwcgr1 (isink);
+  isink = __builtin_arm_getwcgr2 ();
+  __builtin_arm_setwcgr2 (isink);
+  isink = __builtin_arm_getwcgr3 ();
+  __builtin_arm_setwcgr3 (isink);
+
+  isink = __builtin_arm_textrmsb (v8sink, 0);
+  isink = __builtin_arm_textrmsh (v4sink, 0);
+  isink = __builtin_arm_textrmsw (v2sink, 0);
+  isink = __builtin_arm_textrmub (v8sink, 0);
+  isink = __builtin_arm_textrmuh (v4sink, 0);
+  isink = __builtin_arm_textrmuw (v2sink, 0);
+  v8sink = __builtin_arm_tinsrb (v8sink, isink, 0);
+  v4sink = __builtin_arm_tinsrh (v4sink, isink, 0);
+  v2sink = __builtin_arm_tinsrw (v2sink, isink, 0);
+  llsink = __builtin_arm_tmia (llsink, isink, isink);
+  llsink = __builtin_arm_tmiabb (llsink, isink, isink);
+  llsink = __builtin_arm_tmiabt (llsink, isink, isink);
+  llsink = __builtin_arm_tmiaph (llsink, isink, isink);
+  llsink = __builtin_arm_tmiatb (llsink, isink, isink);
+  llsink = __builtin_arm_tmiatt (llsink, isink, isink);
+  isink = __builtin_arm_tmovmskb (v8sink);
+  isink = __builtin_arm_tmovmskh (v4sink);
+  isink = __builtin_arm_tmovmskw (v2sink);
+  llsink = __builtin_arm_waccb (v8sink);
+  llsink = __builtin_arm_wacch (v4sink);
+  llsink = __builtin_arm_waccw (v2sink);
+  v8sink = __builtin_arm_waddb (v8sink, v8sink);
+  v8sink = __builtin_arm_waddbss (v8sink, v8sink);
+  v8sink = __builtin_arm_waddbus (v8sink, v8sink);
+  v4sink = __builtin_arm_waddh (v4sink, v4sink);
+  v4sink = __builtin_arm_waddhss (v4sink, v4sink);
+  v4sink = __builtin_arm_waddhus (v4sink, v4sink);
+  v2sink = __builtin_arm_waddw (v2sink, v2sink);
+  v2sink = __builtin_arm_waddwss (v2sink, v2sink);
+  v2sink = __builtin_arm_waddwus (v2sink, v2sink);
+  v8sink = __builtin_arm_walign (v8sink, v8sink, 0);  /* waligni: 3-bit immediate.  */
+  v8sink = __builtin_arm_walign (v8sink, v8sink, isink); /* walignr: GP register.  */
+  llsink = __builtin_arm_wand(llsink, llsink);
+  llsink = __builtin_arm_wandn (llsink, llsink);
+  v8sink = __builtin_arm_wavg2b (v8sink, v8sink);
+  v8sink = __builtin_arm_wavg2br (v8sink, v8sink);
+  v4sink = __builtin_arm_wavg2h (v4sink, v4sink);
+  v4sink = __builtin_arm_wavg2hr (v4sink, v4sink);
+  v8sink = __builtin_arm_wcmpeqb (v8sink, v8sink);
+  v4sink = __builtin_arm_wcmpeqh (v4sink, v4sink);
+  v2sink = __builtin_arm_wcmpeqw (v2sink, v2sink);
+  v8sink = __builtin_arm_wcmpgtsb (v8sink, v8sink);
+  v4sink = __builtin_arm_wcmpgtsh (v4sink, v4sink);
+  v2sink = __builtin_arm_wcmpgtsw (v2sink, v2sink);
+  v8sink = __builtin_arm_wcmpgtub (v8sink, v8sink);
+  v4sink = __builtin_arm_wcmpgtuh (v4sink, v4sink);
+  v2sink = __builtin_arm_wcmpgtuw (v2sink, v2sink);
+  llsink = __builtin_arm_wmacs (llsink, v4sink, v4sink);
+  llsink = __builtin_arm_wmacsz (v4sink, v4sink);
+  llsink = __builtin_arm_wmacu (llsink, v4sink, v4sink);
+  llsink = __builtin_arm_wmacuz (v4sink, v4sink);
+  v4sink = __builtin_arm_wmadds (v4sink, v4sink);
+  v4sink = __builtin_arm_wmaddu (v4sink, v4sink);
+  v8sink = __builtin_arm_wmaxsb (v8sink, v8sink);
+  v4sink = __builtin_arm_wmaxsh (v4sink, v4sink);
+  v2sink = __builtin_arm_wmaxsw (v2sink, v2sink);
+  v8sink = __builtin_arm_wmaxub (v8sink, v8sink);
+  v4sink = __builtin_arm_wmaxuh (v4sink, v4sink);
+  v2sink = __builtin_arm_wmaxuw (v2sink, v2sink);
+  v8sink = __builtin_arm_wminsb (v8sink, v8sink);
+  v4sink = __builtin_arm_wminsh (v4sink, v4sink);
+  v2sink = __builtin_arm_wminsw (v2sink, v2sink);
+  v8sink = __builtin_arm_wminub (v8sink, v8sink);
+  v4sink = __builtin_arm_wminuh (v4sink, v4sink);
+  v2sink = __builtin_arm_wminuw (v2sink, v2sink);
+  v4sink = __builtin_arm_wmulsm (v4sink, v4sink);
+  v4sink = __builtin_arm_wmulul (v4sink, v4sink);
+  v4sink = __builtin_arm_wmulum (v4sink, v4sink);
+  llsink = __builtin_arm_wor (llsink, llsink);
+  v2sink = __builtin_arm_wpackdss (llsink, llsink);
+  v2sink = __builtin_arm_wpackdus (llsink, llsink);
+  v8sink = __builtin_arm_wpackhss (v4sink, v4sink);
+  v8sink = __builtin_arm_wpackhus (v4sink, v4sink);
+  v4sink = __builtin_arm_wpackwss (v2sink, v2sink);
+  v4sink = __builtin_arm_wpackwus (v2sink, v2sink);
+  llsink = __builtin_arm_wrord (llsink, llsink);
+  llsink = __builtin_arm_wrordi (llsink, isink);
+  v4sink = __builtin_arm_wrorh (v4sink, llsink);
+  v4sink = __builtin_arm_wrorhi (v4sink, isink);
+  v2sink = __builtin_arm_wrorw (v2sink, llsink);
+  v2sink = __builtin_arm_wrorwi (v2sink, isink);
+  v2sink = __builtin_arm_wsadb (v2sink, v8sink, v8sink);
+  v2sink = __builtin_arm_wsadbz (v8sink, v8sink);
+  v2sink = __builtin_arm_wsadh (v2sink, v4sink, v4sink);
+  v2sink = __builtin_arm_wsadhz (v4sink, v4sink);
+  v4sink = __builtin_arm_wshufh (v4sink, 0);
+  llsink = __builtin_arm_wslld (llsink, llsink);
+  llsink = __builtin_arm_wslldi (llsink, 0);
+  v4sink = __builtin_arm_wsllh (v4sink, llsink);
+  v4sink = __builtin_arm_wsllhi (v4sink, isink);
+  v2sink = __builtin_arm_wsllw (v2sink, llsink);
+  v2sink = __builtin_arm_wsllwi (v2sink, isink);
+  llsink = __builtin_arm_wsrad (llsink, llsink);
+  llsink = __builtin_arm_wsradi (llsink, isink);
+  v4sink = __builtin_arm_wsrah (v4sink, llsink);
+  v4sink = __builtin_arm_wsrahi (v4sink, isink);
+  v2sink = __builtin_arm_wsraw (v2sink, llsink);
+  v2sink = __builtin_arm_wsrawi (v2sink, isink);
+  llsink = __builtin_arm_wsrld (llsink, llsink);
+  llsink = __builtin_arm_wsrldi (llsink, isink);
+  v4sink = __builtin_arm_wsrlh (v4sink, llsink);
+  v4sink = __builtin_arm_wsrlhi (v4sink, isink);
+  v2sink = __builtin_arm_wsrlw (v2sink, llsink);
+  v2sink = __builtin_arm_wsrlwi (v2sink, isink);
+  v8sink = __builtin_arm_wsubb (v8sink, v8sink);
+  v8sink = __builtin_arm_wsubbss (v8sink, v8sink);
+  v8sink = __builtin_arm_wsubbus (v8sink, v8sink);
+  v4sink = __builtin_arm_wsubh (v4sink, v4sink);
+  v4sink = __builtin_arm_wsubhss (v4sink, v4sink);
+  v4sink = __builtin_arm_wsubhus (v4sink, v4sink);
+  v2sink = __builtin_arm_wsubw (v2sink, v2sink);
+  v2sink = __builtin_arm_wsubwss (v2sink, v2sink);
+  v2sink = __builtin_arm_wsubwus (v2sink, v2sink);
+  v4sink = __builtin_arm_wunpckehsb (v8sink);
+  v2sink = __builtin_arm_wunpckehsh (v4sink);
+  llsink = __builtin_arm_wunpckehsw (v2sink);
+  v4sink = __builtin_arm_wunpckehub (v8sink);
+  v2sink = __builtin_arm_wunpckehuh (v4sink);
+  llsink = __builtin_arm_wunpckehuw (v2sink);
+  v4sink = __builtin_arm_wunpckelsb (v8sink);
+  v2sink = __builtin_arm_wunpckelsh (v4sink);
+  llsink = __builtin_arm_wunpckelsw (v2sink);
+  v4sink = __builtin_arm_wunpckelub (v8sink);
+  v2sink = __builtin_arm_wunpckeluh (v4sink);
+  llsink = __builtin_arm_wunpckeluw (v2sink);
+  v8sink = __builtin_arm_wunpckihb (v8sink, v8sink);
+  v4sink = __builtin_arm_wunpckihh (v4sink, v4sink);
+  v2sink = __builtin_arm_wunpckihw (v2sink, v2sink);
+  v8sink = __builtin_arm_wunpckilb (v8sink, v8sink);
+  v4sink = __builtin_arm_wunpckilh (v4sink, v4sink);
+  v2sink = __builtin_arm_wunpckilw (v2sink, v2sink);
+  llsink = __builtin_arm_wxor (llsink, llsink);
+  llsink = __builtin_arm_wzero ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-1.c
new file mode 100644
index 000000000..fefffae81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+/* Check that function arguments aren't assigned and copied to stack slots
+   in naked functions.  This usually happens at -O0 (presumably for
+   better debugging), but is highly undesirable if we haven't created
+   a stack frame.  */
+void __attribute__((naked))
+foo(int n)
+{
+  __asm__ volatile ("frob r0\n");
+}
+/* { dg-final { scan-assembler "\tfrob r0" } } */
+/* { dg-final { scan-assembler-not "\tstr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-2.c
new file mode 100644
index 000000000..92e7db444
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/naked-2.c
@@ -0,0 +1,12 @@
+/* Verify that __attribute__((naked)) produces a naked function 
+   that does not use bx to return. Naked functions could be used
+   to implement interrupt routines and must not return using bx.  */
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+/* Use more arguments than we have argument registers.  */
+int __attribute__((naked)) foo(int a, int b, int c, int d, int e, int f)
+{
+  __asm__ volatile ("@ naked");
+}
+/* { dg-final { scan-assembler "\t@ naked" } } */
+/* { dg-final { scan-assembler-not "\tbx\tlr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-1.c
new file mode 100644
index 000000000..c9bef049c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O2" } */
+
+signed long long extendsidi_negsi (signed int x)
+{
+  return -x;
+}
+
+/*
+Expected output:
+	rsb	r0, r0, #0
+	mov	r1, r0, asr #31
+*/
+/* { dg-final { scan-assembler-times "rsb" 1 { target { arm_nothumb } } } } */
+/* { dg-final { scan-assembler-times "negs\\t" 1 { target { ! { arm_nothumb } } } } } */
+/* { dg-final { scan-assembler-times "asr" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-2.c
new file mode 100644
index 000000000..4444c20ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O2" } */
+
+signed long long zero_extendsidi_negsi (unsigned int x)
+{
+  return -x;
+}
+/*
+Expected output:
+	rsb	r0, r0, #0
+	mov	r1, #0
+*/
+/* { dg-final { scan-assembler-times "rsb\\t...?, ...?, #0" 1 { target { arm_nothumb } } } } */
+/* { dg-final { scan-assembler-times "negs\\t...?, ...?" 1 { target { ! arm_nothumb } } } } */
+/* { dg-final { scan-assembler-times "mov" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-3.c
new file mode 100644
index 000000000..76ddf49fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/negdi-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm32 } */
+/* { dg-options "-O2" } */
+
+signed long long negdi_zero_extendsidi (unsigned int x)
+{
+  return -((signed long long) x);
+}
+/*
+Expected output:
+        rsbs    r0, r0, #0
+        sbc     r1, r1, r1
+*/
+/* { dg-final { scan-assembler-times "rsb" 1 } } */
+/* { dg-final { scan-assembler-times "sbc" 1 } } */
+/* { dg-final { scan-assembler-times "mov" 0 } } */
+/* { dg-final { scan-assembler-times "rsc" 0 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c
new file mode 100644
index 000000000..fe3d78b30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-combine-sub-abs-into-vabd.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -funsafe-math-optimizations" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+float32x2_t f_sub_abs_to_vabd_32(float32x2_t val1, float32x2_t val2)
+{
+  float32x2_t sres = vsub_f32(val1, val2);
+  float32x2_t res = vabs_f32 (sres);
+
+  return res;
+}
+/* { dg-final { scan-assembler "vabd\.f32" } }*/
+
+#include <arm_neon.h>
+int8x8_t sub_abs_to_vabd_8(int8x8_t val1, int8x8_t val2)
+{
+  int8x8_t sres = vsub_s8(val1, val2);
+  int8x8_t res = vabs_s8 (sres);
+
+  return res;
+}
+/* { dg-final { scan-assembler "vabd\.s8" } }*/
+
+int16x4_t sub_abs_to_vabd_16(int16x4_t val1, int16x4_t val2)
+{
+  int16x4_t sres = vsub_s16(val1, val2);
+  int16x4_t res = vabs_s16 (sres);
+
+  return res;
+}
+/* { dg-final { scan-assembler "vabd\.s16" } }*/
+
+int32x2_t sub_abs_to_vabd_32(int32x2_t val1, int32x2_t val2)
+{
+  int32x2_t sres = vsub_s32(val1, val2);
+  int32x2_t res = vabs_s32 (sres);
+
+   return res;
+}
+/* { dg-final { scan-assembler "vabd\.s32" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-cond-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-cond-1.c
new file mode 100644
index 000000000..a67625014
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-cond-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+/* Check that the arm_final_prescan_insn ccfsm code does not try to
+ * conditionally execute NEON instructions.  */
+#include <arm_neon.h>
+#include <stdlib.h>
+
+int __attribute__((noinline))
+foo(uint32x2_t a, uint32_t *p, uint32_t *q)
+{
+  if (p != q)
+    /* This vst1 instruction could be conditional, except that NEON
+       instructions are never conditional in ARM mode.  */
+    vst1_u32(p, a);
+  return 0;
+}
+
+int
+main()
+{
+    uint32x2_t v;
+    uint32_t a[2] = {1, 42};
+    v = vld1_u32(a);
+    v = vadd_u32(v, v);
+    foo(v, a, a);
+    if (a[0] != 1 || a[1] != 42)
+      abort();
+    exit(0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-1.c
new file mode 100644
index 000000000..cfe83ce1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-1.c
@@ -0,0 +1,13 @@
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+void
+f (unsigned int a)
+{
+  unsigned long long b = a;
+  asm volatile ("@ extended to %0" : : "w" (b));
+}
+
+/* { dg-final { scan-assembler "vdup.32" } } */
+/* { dg-final { scan-assembler "vshr.u64" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-2.c
new file mode 100644
index 000000000..1c5a17e42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-extend-2.c
@@ -0,0 +1,13 @@
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+void
+f (int a)
+{
+  long long b = a;
+  asm volatile ("@ extended to %0" : : "w" (b));
+}
+
+/* { dg-final { scan-assembler "vdup.32" } } */
+/* { dg-final { scan-assembler "vshr.s64" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c
new file mode 100644
index 000000000..a2a4103b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-for-64bits-1.c
@@ -0,0 +1,54 @@
+/* Check that Neon is *not* used by default to handle 64-bits scalar
+   operations.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+typedef long long i64;
+typedef unsigned long long u64;
+typedef unsigned int u32;
+typedef int i32;
+
+/* Unary operators */
+#define UNARY_OP(name, op) \
+  void unary_##name(u64 *a, u64 *b) { *a = op (*b + 0x1234567812345678ULL) ; }
+
+/* Binary operators */
+#define BINARY_OP(name, op) \
+  void binary_##name(u64 *a, u64 *b, u64 *c) { *a = *b op *c ; }
+
+/* Unsigned shift */
+#define SHIFT_U(name, op, amount) \
+  void ushift_##name(u64 *a, u64 *b, int c) { *a = *b op amount; }
+
+/* Signed shift */
+#define SHIFT_S(name, op, amount) \
+  void sshift_##name(i64 *a, i64 *b, int c) { *a = *b op amount; }
+
+UNARY_OP(not, ~)
+
+BINARY_OP(add, +)
+BINARY_OP(sub, -)
+BINARY_OP(and, &)
+BINARY_OP(or, |)
+BINARY_OP(xor, ^)
+
+SHIFT_U(right1, >>, 1)
+SHIFT_U(right2, >>, 2)
+SHIFT_U(right5, >>, 5)
+SHIFT_U(rightn, >>, c)
+
+SHIFT_S(right1, >>, 1)
+SHIFT_S(right2, >>, 2)
+SHIFT_S(right5, >>, 5)
+SHIFT_S(rightn, >>, c)
+
+/* { dg-final {scan-assembler-times "vmvn" 0} }  */
+/* { dg-final {scan-assembler-times "vadd" 0} }  */
+/* { dg-final {scan-assembler-times "vsub" 0} }  */
+/* { dg-final {scan-assembler-times "vand" 0} }  */
+/* { dg-final {scan-assembler-times "vorr" 0} }  */
+/* { dg-final {scan-assembler-times "veor" 0} }  */
+/* { dg-final {scan-assembler-times "vshr" 0} }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-1.c
new file mode 100644
index 000000000..6ee13af01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+void neon_internal_error(int *dst, int *src)
+{
+  uint16x8x4_t sval;
+
+  sval = vld4q_u16((void *)src);
+  vst4q_u16((void *)dst,sval);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-2.c
new file mode 100644
index 000000000..40f1bba36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+#define SETUP(A) x##A = vld3_u32 (ptr + A * 0x20)
+#define MODIFY(A) x##A = vld3_lane_u32 (ptr + A * 0x20 + 0x10, x##A, 1)
+#define STORE(A) vst3_u32 (ptr + A * 0x20, x##A)
+
+#define MANY(A) A (0), A (1), A (2), A (3), A (4), A (5)
+
+void
+bar (uint32_t *ptr, int y)
+{
+  uint32x2x3_t MANY (SETUP);
+  int *x = __builtin_alloca (y);
+  int z[0x1000];
+  foo (x, z);
+  MANY (MODIFY);
+  foo (x, z);
+  MANY (STORE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-3.c
new file mode 100644
index 000000000..f3e4f335e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-modes-3.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O -g" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+void f1 (volatile float32x4_t *dest, volatile float32x4x4_t *src, int n)
+{
+  float32x4x4_t a5, a6, a7, a8, a9;
+  int i;
+
+  a5 = *src;
+  a6 = *src;
+  a7 = *src;
+  a8 = *src;
+  a9 = *src;
+  while (n--)
+    {
+      for (i = 0; i < 8; i++)
+	{
+	  float32x4x4_t a0, a1, a2, a3, a4;
+
+	  a0 = *src;
+	  a1 = *src;
+	  a2 = *src;
+	  a3 = *src;
+	  a4 = *src;
+	  *src = a0;
+	  *dest = a0.val[0];
+	  *dest = a0.val[3];
+	  *src = a1;
+	  *dest = a1.val[0];
+	  *dest = a1.val[3];
+	  *src = a2;
+	  *dest = a2.val[0];
+	  *dest = a2.val[3];
+	  *src = a3;
+	  *dest = a3.val[0];
+	  *dest = a3.val[3];
+	  *src = a4;
+	  *dest = a4.val[0];
+	  *dest = a4.val[3];
+	}
+      *src = a5;
+      *dest = a5.val[0];
+      *dest = a5.val[3];
+      *src = a6;
+      *dest = a6.val[0];
+      *dest = a6.val[3];
+      *src = a7;
+      *dest = a7.val[0];
+      *dest = a7.val[3];
+      *src = a8;
+      *dest = a8.val[0];
+      *dest = a8.val[3];
+      *src = a9;
+      *dest = a9.val[0];
+      *dest = a9.val[3];
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-nested-apcs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-nested-apcs.c
new file mode 100644
index 000000000..cd92d7d33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-nested-apcs.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-fno-omit-frame-pointer -mapcs-frame -O" }
+/* { dg-add-options arm_neon } */
+
+extern void abort (void);
+
+float data;
+
+void __attribute__((noinline, noclone)) bar (float f)
+{
+  data = f;
+}
+
+float __attribute__((noinline, noclone)) foo (float f)
+{
+  int error_reported = 0;
+
+  void __attribute__((noinline, noclone)) 
+  nested (int a, int b, int c, int d, float f0, float f1, float f2, float f3)
+  {
+    float e;
+
+    if (f3 > f2)
+      e = f3;
+    else
+      e = f2;
+
+    if (f0 - f1 > e)
+      {
+	error_reported = a + b + c + d;
+	bar (f0);
+	bar (e);
+      }
+  }
+
+  nested (1, 2, 3, 4, 1.0, 1.0, 3.5, 4.2);
+  return f + (float)error_reported;
+}
+
+#define PI 3.1415927f
+
+int main (void)
+{
+  if (foo (PI) != PI)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-offset-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-offset-1.c
new file mode 100644
index 000000000..91dde6a20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-offset-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+void neon_internal_error(int32x4_t *dst, char *src)
+{
+  *dst = *(int32x4_t *)(src+1008);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-reload-class.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-reload-class.c
new file mode 100644
index 000000000..c63aa0496
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-reload-class.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -ftree-vectorize" }  */
+/* { dg-add-options arm_neon } */
+
+
+void
+_op_blend_p_caa_dp(unsigned *s, unsigned* e, unsigned *d, unsigned c) {
+  while (d < e) {
+    *d = ( (((((*s) >> 8) & 0x00ff00ff) * (c)) & 0xff00ff00) + (((((*s) & 0x00ff00ff) * (c)) >> 8) & 0x00ff00ff) );
+    d++;
+    s++;
+  }
+}
+
+/* These constants should be emitted as immediates rather than loaded from memory.  */
+
+/* { dg-final { scan-assembler-not "(\\.d?word|mov(w|t))" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
new file mode 100644
index 000000000..9cf86dd05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-thumb2-move.c
@@ -0,0 +1,101 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2 -mthumb -march=armv7-a" } */
+/* { dg-add-options arm_neon } */
+/* { dg-prune-output "switch .* conflicts with" } */
+
+#include <arm_neon.h>
+#include <stddef.h>
+
+void *
+memset (DST, C, LENGTH)
+     void *DST;
+     int C;
+     size_t LENGTH;
+{
+  void* DST0 = DST;
+  unsigned char C_BYTE = C;
+
+
+  if (__builtin_expect(LENGTH < 4, 1)) {
+    size_t i = 0;
+    while (i < LENGTH) {
+      ((char*)DST)[i] = C_BYTE;
+      i++;
+    }
+    return DST;
+  }
+
+  const char* DST_end = (char*)DST + LENGTH;
+
+
+  while ((uintptr_t)DST % 4 != 0) {
+    *(char*) (DST++) = C_BYTE;
+  }
+
+
+  uint32_t C_SHORTWORD = (uint32_t)(unsigned char)(C_BYTE) * 0x01010101;
+
+
+  if (__builtin_expect(DST_end - (char*)DST >= 16, 0)) {
+    while ((uintptr_t)DST % 16 != 0) {
+      *((uint32_t*)((char*)(DST) + (0))) = C_SHORTWORD;
+      DST += 4;
+    }
+
+
+    uint8x16_t C_WORD = vdupq_n_u8(C_BYTE);
+
+
+
+
+
+    size_t i = 0;
+    LENGTH = DST_end - (char*)DST;
+    while (i + 16 * 16 <= LENGTH) {
+      *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 1))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 2))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 3))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 4))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 5))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 6))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 7))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 8))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 9))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 10))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 11))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 12))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 13))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 14))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 15))) = C_WORD;
+      i += 16 * 16;
+    }
+    while (i + 16 * 4 <= LENGTH) {
+      *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 1))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 2))) = C_WORD;
+      *((uint8x16_t*)((char*)(DST) + (i + 16 * 3))) = C_WORD;
+      i += 16 * 4;
+    }
+    while (i + 16 <= LENGTH) {
+      *((uint8x16_t*)((char*)(DST) + (i))) = C_WORD;
+      i += 16;
+    }
+    DST += i;
+  }
+
+  while (4 <= DST_end - (char*)DST) {
+    *((uint32_t*)((char*)(DST) + (0))) = C_SHORTWORD;
+    DST += 4;
+  }
+
+
+  while ((char*)DST < DST_end) {
+    *((char*)DST) = C_BYTE;
+    DST++;
+  }
+
+  return DST0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vadds64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vadds64.c
new file mode 100644
index 000000000..284a1d8ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vadds64.c
@@ -0,0 +1,21 @@
+/* Test the `vadd_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
+  int64x1_t arg1_int64x1_t = (int64x1_t)0x00000000deadbeefLL;
+
+  out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+  if (out_int64x1_t != (int64x1_t)0xdeadbeefdeadbeefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vaddu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vaddu64.c
new file mode 100644
index 000000000..05bda8b04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vaddu64.c
@@ -0,0 +1,21 @@
+/* Test the `vadd_u64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
+  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x00000000deadbeefLL;
+
+  out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+  if (out_uint64x1_t != (uint64x1_t)0xdeadbeefdeadbeefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vands64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vands64.c
new file mode 100644
index 000000000..8b6975db6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vands64.c
@@ -0,0 +1,21 @@
+/* Test the `vand_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
+  int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
+
+  out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
+  if (out_int64x1_t != (int64x1_t)0xdead000000000000LL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vandu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vandu64.c
new file mode 100644
index 000000000..a8ec3a28b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vandu64.c
@@ -0,0 +1,21 @@
+/* Test the `vand_u64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
+  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
+
+  out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+  if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbics64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbics64.c
new file mode 100644
index 000000000..ec3438bae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbics64.c
@@ -0,0 +1,21 @@
+/* Test the `vbic_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
+  int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL);
+
+  out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
+  if (out_int64x1_t != (int64x1_t)0xdead000000000000LL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbicu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbicu64.c
new file mode 100644
index 000000000..a0c1b85b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vbicu64.c
@@ -0,0 +1,21 @@
+/* Test the `vbic_u64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
+  uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL);
+
+  out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+  if (out_uint64x1_t != (uint64x1_t)0xdead000000000000LL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c
new file mode 100644
index 000000000..21a6a78a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vceq_p64.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+extern void abort (void);
+
+int
+main (void)
+{
+  uint64_t args[] = { 0x0, 0xdeadbeef, ~0xdeadbeef, 0xffff,
+                      ~0xffff, 0xffffffff, ~0xffffffff, ~0x0 };
+  int i, j;
+
+  for (i = 0; i < sizeof (args) / sizeof (args[0]); ++i)
+    {
+       for (j = 0; j < sizeof (args) / sizeof (args[0]); ++j)
+         {
+           uint64_t a1 = args[i];
+           uint64_t a2 = args[j];
+           uint64_t res = vceq_p64 (vreinterpret_p64_u64 (a1),
+                                    vreinterpret_p64_u64 (a2));
+           uint64_t exp = (a1 == a2) ? ~0x0 : 0x0;
+
+           if (res != exp)
+             {
+               fprintf (stderr, "vceq_p64 (a1= %lx, a2= %lx)"
+                                " returned %lx, expected %lx\n",
+                                 a1, a2, res, exp);
+               abort ();
+             }
+         }
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c
new file mode 100644
index 000000000..8e9f37851
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-gt.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" }  */
+/* { dg-add-options arm_neon } */
+
+#define MAX(a, b) (a > b ? a : b)
+void foo (int ilast,float* w, float* w2)
+{
+  int i;
+  for (i = 0; i < ilast; ++i)
+  {
+    w[i] = MAX (0.0f, w2[i]);
+  }
+}
+
+/* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c
new file mode 100644
index 000000000..c8306e364
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-ltgt.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" }  */
+/* { dg-add-options arm_neon } */
+
+#define LTGT(a, b) (__builtin_islessgreater (a, b) ? a : b)
+void foo (int ilast,float* w, float* w2)
+{
+  int i;
+  for (i = 0; i < ilast; ++i)
+  {
+    w[i] = LTGT (0.0f, w2[i]);
+  }
+}
+
+/* { dg-final { scan-assembler-times "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c
new file mode 100644
index 000000000..3bb67d3af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vcond-unordered.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1 -funsafe-math-optimizations -ftree-vectorize" }  */
+/* { dg-add-options arm_neon } */
+
+#define UNORD(a, b) (__builtin_isunordered (a, b) ? a : b)
+void foo (int ilast,float* w, float* w2)
+{
+  int i;
+  for (i = 0; i < ilast; ++i)
+  {
+    w[i] = UNORD (0.0f, w2[i]);
+  }
+}
+
+/* { dg-final { scan-assembler "vcgt\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcge\\.f32\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vorr\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vbsl|vbit|vbif\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+,\[\\t \]*q\[0-9\]+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-1.c
new file mode 100644
index 000000000..41799a25c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-1.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+float32x4_t out_float32x4_t;
+void test_vdupq_nf32 (void)
+{
+  out_float32x4_t = vdupq_n_f32 (0.0);
+}
+
+/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[qQ\]\[0-9\]+, #0\.0\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-10.c
new file mode 100644
index 000000000..a06b0647a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-10.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (~0x12000000);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #3992977407\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-11.c
new file mode 100644
index 000000000..07d08896a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-11.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t out_uint16x8_t;
+void test_vdupq_nu16 (void)
+{
+  out_uint16x8_t = vdupq_n_u16 (0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i16\[ 	\]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-12.c
new file mode 100644
index 000000000..27b418682
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-12.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t out_uint16x8_t;
+void test_vdupq_nu16 (void)
+{
+  out_uint16x8_t = vdupq_n_u16 (0x1200);
+}
+
+/* { dg-final { scan-assembler "vmov\.i16\[ 	\]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-13.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-13.c
new file mode 100644
index 000000000..4d38bc088
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-13.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t out_uint16x8_t;
+void test_vdupq_nu16 (void)
+{
+  out_uint16x8_t = vdupq_n_u16 (~0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i16\[ 	\]+\[qQ\]\[0-9\]+, #65517\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-14.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-14.c
new file mode 100644
index 000000000..a16659fda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-14.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t out_uint16x8_t;
+void test_vdupq_nu16 (void)
+{
+  out_uint16x8_t = vdupq_n_u16 (~0x1200);
+}
+
+/* { dg-final { scan-assembler "vmov\.i16\[ 	\]+\[qQ\]\[0-9\]+, #60927\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-15.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-15.c
new file mode 100644
index 000000000..84a6fe04f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-15.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u8' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint8x16_t out_uint8x16_t;
+void test_vdupq_nu8 (void)
+{
+  out_uint8x16_t = vdupq_n_u8 (0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i8\[ 	\]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-16.c
new file mode 100644
index 000000000..70bec0336
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-16.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (0x12ff);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4863\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-17.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-17.c
new file mode 100644
index 000000000..e0283f1fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-17.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (0x12ffff);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #1245183\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-18.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-18.c
new file mode 100644
index 000000000..7dcf85d39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-18.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (~0x12ff);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4294962432\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-19.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-19.c
new file mode 100644
index 000000000..09804373f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-19.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (~0x12ffff);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4293722112\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-2.c
new file mode 100644
index 000000000..f9e6a72ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-2.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+float32x4_t out_float32x4_t;
+void test_vdupq_nf32 (void)
+{
+  out_float32x4_t = vdupq_n_f32 (0.125);
+}
+
+/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[qQ\]\[0-9\]+, #1\.25e-1\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-3.c
new file mode 100644
index 000000000..d40731643
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-3.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-4.c
new file mode 100644
index 000000000..bc1be079f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-4.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (0x1200);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-5.c
new file mode 100644
index 000000000..9b04f16d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-5.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (0x120000);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #1179648\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-6.c
new file mode 100644
index 000000000..0889b80af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-6.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (0x12000000);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #301989888\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-7.c
new file mode 100644
index 000000000..f7b1dc861
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-7.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (~0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4294967277\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-8.c
new file mode 100644
index 000000000..9d494c355
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-8.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (~0x1200);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4294962687\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-9.c
new file mode 100644
index 000000000..799e95ed9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup-9.c
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+  out_uint32x4_t = vdupq_n_u32 (~0x120000);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ 	\]+\[qQ\]\[0-9\]+, #4293787647\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c
new file mode 100644
index 000000000..da24eaca6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c
@@ -0,0 +1,22 @@
+/* Test the `vdupq_lanes64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x2_t out_int64x2_t = {0, 0};
+  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
+
+  out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0);
+  if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
+    abort();
+  if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c
new file mode 100644
index 000000000..cc19ea512
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c
@@ -0,0 +1,22 @@
+/* Test the `vdupq_laneu64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x2_t out_uint64x2_t = {0, 0};
+  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
+
+  out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0);
+  if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
+    abort();
+  if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c
new file mode 100644
index 000000000..79b4d4eb6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c
@@ -0,0 +1,22 @@
+/* Test the `vdupq_ns64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x2_t out_int64x2_t = {0, 0};
+  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
+
+  out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
+  if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
+    abort();
+  if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c
new file mode 100644
index 000000000..ef6f47fd3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c
@@ -0,0 +1,22 @@
+/* Test the `vdupq_nu64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x2_t out_uint64x2_t = {0, 0};
+  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
+
+  out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
+  if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
+    abort();
+  if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c
new file mode 100644
index 000000000..589ea2293
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_ns64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
+
+  out_int64x1_t = vdup_n_s64 (arg0_int64_t);
+  if ((int64_t)out_int64x1_t != arg0_int64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c
new file mode 100644
index 000000000..8bed5a0c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_nu64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
+
+  out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
+  if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veors64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veors64.c
new file mode 100644
index 000000000..59d5baa35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veors64.c
@@ -0,0 +1,21 @@
+/* Test the `veor_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
+  int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
+
+  out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
+  if (out_int64x1_t != (int64x1_t)0x0000beef0000beefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veoru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veoru64.c
new file mode 100644
index 000000000..b7ff77af0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-veoru64.c
@@ -0,0 +1,21 @@
+/* Test the `veor_u64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
+  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
+
+  out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+  if (out_uint64x1_t != (uint64x1_t)0x0000beef0000beefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c
new file mode 100644
index 000000000..3d6c28cca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext-execute.c
@@ -0,0 +1,340 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm_little_endian } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+uint8x8_t
+tst_vext_u8 (uint8x8_t __a, uint8x8_t __b)
+{
+  uint8x8_t __mask1 = {2, 3, 4, 5, 6, 7, 8, 9};
+
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint8x8_t
+tst_vext_u8_rotate (uint8x8_t __a)
+{
+  uint8x8_t __mask1 = {2, 3, 4, 5, 6, 7, 0, 1};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint16x4_t
+tst_vext_u16 (uint16x4_t __a, uint16x4_t __b)
+{
+  uint16x4_t __mask1 = {2, 3, 4, 5};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint16x4_t
+tst_vext_u16_rotate (uint16x4_t __a)
+{
+  uint16x4_t __mask1 = {2, 3, 0, 1};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint32x2_t
+tst_vext_u32 (uint32x2_t __a, uint32x2_t __b)
+{
+  uint32x2_t __mask1 = {1, 2};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+/* This one is mapped into vrev64.32.  */
+uint32x2_t
+tst_vext_u32_rotate (uint32x2_t __a)
+{
+  uint32x2_t __mask1 = {1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint8x16_t
+tst_vextq_u8 (uint8x16_t __a, uint8x16_t __b)
+{
+  uint8x16_t __mask1 = {4, 5, 6, 7, 8, 9, 10, 11,
+			12, 13, 14, 15, 16, 17, 18, 19};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint8x16_t
+tst_vextq_u8_rotate (uint8x16_t __a)
+{
+  uint8x16_t __mask1 = {4, 5, 6, 7, 8, 9, 10, 11,
+			12, 13, 14, 15, 0, 1, 2, 3};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint16x8_t
+tst_vextq_u16 (uint16x8_t __a, uint16x8_t __b)
+{
+  uint16x8_t __mask1 = {2, 3, 4, 5, 6, 7, 8, 9};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint16x8_t
+tst_vextq_u16_rotate (uint16x8_t __a)
+{
+  uint16x8_t __mask1 = {2, 3, 4, 5, 6, 7, 0, 1};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint32x4_t
+tst_vextq_u32 (uint32x4_t __a, uint32x4_t __b)
+{
+  uint32x4_t __mask1 = {1, 2, 3, 4};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint32x4_t
+tst_vextq_u32_rotate (uint32x4_t __a)
+{
+  uint32x4_t __mask1 = {1, 2, 3, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint64x2_t
+tst_vextq_u64 (uint64x2_t __a, uint64x2_t __b)
+{
+  uint64x2_t __mask1 = {1, 2};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint64x2_t
+tst_vextq_u64_rotate (uint64x2_t __a)
+{
+  uint64x2_t __mask1 = {1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+int main (void)
+{
+  uint8_t arr_u8x8[] = {0, 1, 2, 3, 4, 5, 6, 7};
+  uint8_t arr2_u8x8[] = {8, 9, 10, 11, 12, 13, 14, 15};
+  uint16_t arr_u16x4[] = {0, 1, 2, 3};
+  uint16_t arr2_u16x4[] = {4, 5, 6, 7};
+  uint32_t arr_u32x2[] = {0, 1};
+  uint32_t arr2_u32x2[] = {2, 3};
+  uint8_t arr_u8x16[] = {0, 1, 2, 3, 4, 5, 6, 7,
+			 8, 9, 10, 11, 12, 13, 14, 15};
+  uint8_t arr2_u8x16[] = {16, 17, 18, 19, 20, 21, 22, 23,
+			  24, 25, 26, 27, 28, 29, 30, 31};
+  uint16_t arr_u16x8[] = {0, 1, 2, 3, 4, 5, 6, 7};
+  uint16_t arr2_u16x8[] = {8, 9, 10, 11, 12, 13, 14, 15};
+  uint32_t arr_u32x4[] = {0, 1, 2, 3};
+  uint32_t arr2_u32x4[] = {4, 5, 6, 7};
+  uint64_t arr_u64x2[] = {0, 1};
+  uint64_t arr2_u64x2[] = {2, 3};
+
+  uint8_t expected_u8x8[] = {2, 3, 4, 5, 6, 7, 8, 9};
+  uint8_t expected_rot_u8x8[] = {2, 3, 4, 5, 6, 7, 0, 1};
+  uint16_t expected_u16x4[] = {2, 3, 4, 5};
+  uint16_t expected_rot_u16x4[] = {2, 3, 0, 1};
+  uint32_t expected_u32x2[] = {1, 2};
+  uint32_t expected_rot_u32x2[] = {1, 0};
+  uint8_t expected_u8x16[] = {4, 5, 6, 7, 8, 9, 10, 11,
+			      12, 13, 14, 15, 16, 17, 18, 19};
+  uint8_t expected_rot_u8x16[] = {4, 5, 6, 7, 8, 9, 10, 11,
+				  12, 13, 14, 15, 0, 1, 2, 3,};
+  uint16_t expected_u16x8[] = {2, 3, 4, 5, 6, 7, 8, 9};
+  uint16_t expected_rot_u16x8[] = {2, 3, 4, 5, 6, 7, 0, 1};
+  uint32_t expected_u32x4[] = {1, 2, 3, 4};
+  uint32_t expected_rot_u32x4[] = {1, 2, 3, 0};
+  uint64_t expected_u64x2[] = {1, 2};
+  uint64_t expected_rot_u64x2[] = {1, 0};
+
+  uint8x8_t vec_u8x8 = vld1_u8 (arr_u8x8);
+  uint8x8_t vec2_u8x8 = vld1_u8 (arr2_u8x8);
+  uint16x4_t vec_u16x4 = vld1_u16 (arr_u16x4);
+  uint16x4_t vec2_u16x4 = vld1_u16 (arr2_u16x4);
+  uint32x2_t vec_u32x2 = vld1_u32 (arr_u32x2);
+  uint32x2_t vec2_u32x2 = vld1_u32 (arr2_u32x2);
+  uint8x16_t vec_u8x16 = vld1q_u8 (arr_u8x16);
+  uint8x16_t vec2_u8x16 = vld1q_u8 (arr2_u8x16);
+  uint16x8_t vec_u16x8 = vld1q_u16 (arr_u16x8);
+  uint16x8_t vec2_u16x8 = vld1q_u16 (arr2_u16x8);
+  uint32x4_t vec_u32x4 = vld1q_u32 (arr_u32x4);
+  uint32x4_t vec2_u32x4 = vld1q_u32 (arr2_u32x4);
+  uint64x2_t vec_u64x2 = vld1q_u64 (arr_u64x2);
+  uint64x2_t vec2_u64x2 = vld1q_u64 (arr2_u64x2);
+
+  uint8x8_t result_u8x8;
+  uint16x4_t result_u16x4;
+  uint32x2_t result_u32x2;
+  uint8x16_t result_u8x16;
+  uint16x8_t result_u16x8;
+  uint32x4_t result_u32x4;
+  uint64x2_t result_u64x2;
+
+  union {uint8x8_t v; uint8_t buf[8];} mem_u8x8;
+  union {uint16x4_t v; uint16_t buf[4];} mem_u16x4;
+  union {uint32x2_t v; uint32_t buf[2];} mem_u32x2;
+  union {uint8x16_t v; uint8_t buf[16];} mem_u8x16;
+  union {uint16x8_t v; uint16_t buf[8];} mem_u16x8;
+  union {uint32x4_t v; uint32_t buf[4];} mem_u32x4;
+  union {uint64x2_t v; uint64_t buf[2];} mem_u64x2;
+
+  int i;
+
+  result_u8x8 = tst_vext_u8 (vec_u8x8, vec2_u8x8);
+  vst1_u8 (mem_u8x8.buf, result_u8x8);
+
+  for (i=0; i<8; i++)
+      if (mem_u8x8.buf[i] != expected_u8x8[i])
+	{
+	  printf ("tst_vext_u8[%d]=%d expected %d\n",
+		  i, mem_u8x8.buf[i], expected_u8x8[i]);
+	  abort ();
+	}
+
+  result_u8x8 = tst_vext_u8_rotate (vec_u8x8);
+  vst1_u8 (mem_u8x8.buf, result_u8x8);
+
+  for (i=0; i<8; i++)
+      if (mem_u8x8.buf[i] != expected_rot_u8x8[i])
+	{
+	  printf ("tst_vext_u8_rotate[%d]=%d expected %d\n",
+		  i, mem_u8x8.buf[i], expected_rot_u8x8[i]);
+	  abort ();
+	}
+
+
+  result_u16x4 = tst_vext_u16 (vec_u16x4, vec2_u16x4);
+  vst1_u16 (mem_u16x4.buf, result_u16x4);
+
+  for (i=0; i<4; i++)
+      if (mem_u16x4.buf[i] != expected_u16x4[i])
+	{
+	  printf ("tst_vext_u16[%d]=%d expected %d\n",
+		  i, mem_u16x4.buf[i], expected_u16x4[i]);
+	  abort ();
+	}
+
+  result_u16x4 = tst_vext_u16_rotate (vec_u16x4);
+  vst1_u16 (mem_u16x4.buf, result_u16x4);
+
+  for (i=0; i<4; i++)
+      if (mem_u16x4.buf[i] != expected_rot_u16x4[i])
+	{
+	  printf ("tst_vext_u16_rotate[%d]=%d expected %d\n",
+		  i, mem_u16x4.buf[i], expected_rot_u16x4[i]);
+	  abort ();
+	}
+
+
+  result_u32x2 = tst_vext_u32 (vec_u32x2, vec2_u32x2);
+  vst1_u32 (mem_u32x2.buf, result_u32x2);
+
+  for (i=0; i<2; i++)
+      if (mem_u32x2.buf[i] != expected_u32x2[i])
+	{
+	  printf ("tst_vext_u32[%d]=%d expected %d\n",
+		  i, mem_u32x2.buf[i], expected_u32x2[i]);
+	  abort ();
+	}
+
+  result_u32x2 = tst_vext_u32_rotate (vec_u32x2);
+  vst1_u32 (mem_u32x2.buf, result_u32x2);
+
+  for (i=0; i<2; i++)
+      if (mem_u32x2.buf[i] != expected_rot_u32x2[i])
+	{
+	  printf ("tst_vext_u32_rotate[%d]=%d expected %d\n",
+		  i, mem_u32x2.buf[i], expected_rot_u32x2[i]);
+	  abort ();
+	}
+
+
+  result_u8x16 = tst_vextq_u8 (vec_u8x16, vec2_u8x16);
+  vst1q_u8 (mem_u8x16.buf, result_u8x16);
+
+  for (i=0; i<16; i++)
+      if (mem_u8x16.buf[i] != expected_u8x16[i])
+	{
+	  printf ("tst_vextq_u8[%d]=%d expected %d\n",
+		  i, mem_u8x16.buf[i], expected_u8x16[i]);
+	  abort ();
+	}
+
+  result_u8x16 = tst_vextq_u8_rotate (vec_u8x16);
+  vst1q_u8 (mem_u8x16.buf, result_u8x16);
+
+  for (i=0; i<16; i++)
+      if (mem_u8x16.buf[i] != expected_rot_u8x16[i])
+	{
+	  printf ("tst_vextq_u8_rotate[%d]=%d expected %d\n",
+		  i, mem_u8x16.buf[i], expected_rot_u8x16[i]);
+	  abort ();
+	}
+
+  result_u16x8 = tst_vextq_u16 (vec_u16x8, vec2_u16x8);
+  vst1q_u16 (mem_u16x8.buf, result_u16x8);
+
+  for (i=0; i<8; i++)
+      if (mem_u16x8.buf[i] != expected_u16x8[i])
+	{
+	  printf ("tst_vextq_u16[%d]=%d expected %d\n",
+		  i, mem_u16x8.buf[i], expected_u16x8[i]);
+	  abort ();
+	}
+
+  result_u16x8 = tst_vextq_u16_rotate (vec_u16x8);
+  vst1q_u16 (mem_u16x8.buf, result_u16x8);
+
+  for (i=0; i<8; i++)
+      if (mem_u16x8.buf[i] != expected_rot_u16x8[i])
+	{
+	  printf ("tst_vextq_u16_rotate[%d]=%d expected %d\n",
+		  i, mem_u16x8.buf[i], expected_rot_u16x8[i]);
+	  abort ();
+	}
+
+  result_u32x4 = tst_vextq_u32 (vec_u32x4, vec2_u32x4);
+  vst1q_u32 (mem_u32x4.buf, result_u32x4);
+
+  for (i=0; i<4; i++)
+      if (mem_u32x4.buf[i] != expected_u32x4[i])
+	{
+	  printf ("tst_vextq_u32[%d]=%d expected %d\n",
+		  i, mem_u32x4.buf[i], expected_u32x4[i]);
+	  abort ();
+	}
+
+  result_u32x4 = tst_vextq_u32_rotate (vec_u32x4);
+  vst1q_u32 (mem_u32x4.buf, result_u32x4);
+
+  for (i=0; i<4; i++)
+      if (mem_u32x4.buf[i] != expected_rot_u32x4[i])
+	{
+	  printf ("tst_vextq_u32_rotate[%d]=%d expected %d\n",
+		  i, mem_u32x4.buf[i], expected_rot_u32x4[i]);
+	  abort ();
+	}
+
+  result_u64x2 = tst_vextq_u64 (vec_u64x2, vec2_u64x2);
+  vst1q_u64 (mem_u64x2.buf, result_u64x2);
+
+  for (i=0; i<2; i++)
+      if (mem_u64x2.buf[i] != expected_u64x2[i])
+	{
+	  printf ("tst_vextq_u64[%d]=%lld expected %lld\n",
+		  i, mem_u64x2.buf[i], expected_u64x2[i]);
+	  abort ();
+	}
+
+  result_u64x2 = tst_vextq_u64_rotate (vec_u64x2);
+  vst1q_u64 (mem_u64x2.buf, result_u64x2);
+
+  for (i=0; i<2; i++)
+      if (mem_u64x2.buf[i] != expected_rot_u64x2[i])
+	{
+	  printf ("tst_vextq_u64_rotate[%d]=%lld expected %lld\n",
+		  i, mem_u64x2.buf[i], expected_rot_u64x2[i]);
+	  abort ();
+	}
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext.c
new file mode 100644
index 000000000..4a012a996
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vext.c
@@ -0,0 +1,115 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-require-effective-target arm_little_endian } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint8x8_t
+tst_vext_u8 (uint8x8_t __a, uint8x8_t __b)
+{
+  uint8x8_t __mask1 = {2, 3, 4, 5, 6, 7, 8, 9};
+
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint8x8_t
+tst_vext_u8_rotate (uint8x8_t __a)
+{
+  uint8x8_t __mask1 = {2, 3, 4, 5, 6, 7, 0, 1};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint16x4_t
+tst_vext_u16 (uint16x4_t __a, uint16x4_t __b)
+{
+  uint16x4_t __mask1 = {2, 3, 4, 5};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint16x4_t
+tst_vext_u16_rotate (uint16x4_t __a)
+{
+  uint16x4_t __mask1 = {2, 3, 0, 1};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint32x2_t
+tst_vext_u32 (uint32x2_t __a, uint32x2_t __b)
+{
+  uint32x2_t __mask1 = {1, 2};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+/* This one is mapped into vrev64.32.  */
+uint32x2_t
+tst_vext_u32_rotate (uint32x2_t __a)
+{
+  uint32x2_t __mask1 = {1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint8x16_t
+tst_vextq_u8 (uint8x16_t __a, uint8x16_t __b)
+{
+  uint8x16_t __mask1 = {4, 5, 6, 7, 8, 9, 10, 11,
+			12, 13, 14, 15, 16, 17, 18, 19};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint8x16_t
+tst_vextq_u8_rotate (uint8x16_t __a)
+{
+  uint8x16_t __mask1 = {4, 5, 6, 7, 8, 9, 10, 11,
+			12, 13, 14, 15, 0, 1, 2, 3};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint16x8_t
+tst_vextq_u16 (uint16x8_t __a, uint16x8_t __b)
+{
+  uint16x8_t __mask1 = {2, 3, 4, 5, 6, 7, 8, 9};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint16x8_t
+tst_vextq_u16_rotate (uint16x8_t __a)
+{
+  uint16x8_t __mask1 = {2, 3, 4, 5, 6, 7, 0, 1};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint32x4_t
+tst_vextq_u32 (uint32x4_t __a, uint32x4_t __b)
+{
+  uint32x4_t __mask1 = {1, 2, 3, 4};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint32x4_t
+tst_vextq_u32_rotate (uint32x4_t __a)
+{
+  uint32x4_t __mask1 = {1, 2, 3, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint64x2_t
+tst_vextq_u64 (uint64x2_t __a, uint64x2_t __b)
+{
+  uint64x2_t __mask1 = {1, 2};
+  return __builtin_shuffle ( __a, __b, __mask1) ;
+}
+
+uint64x2_t
+tst_vextq_u64_rotate (uint64x2_t __a)
+{
+  uint64x2_t __mask1 = {1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+/* { dg-final {scan-assembler-times "vext\.8\\t" 4} }  */
+/* { dg-final {scan-assembler-times "vext\.16\\t" 4} }  */
+/* { dg-final {scan-assembler-times "vext\.32\\t" 3} }  */
+/* { dg-final {scan-assembler-times "vrev64\.32\\t" 1} }  */
+/* { dg-final {scan-assembler-times "vext\.64\\t" 2} }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfma-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfma-1.c
new file mode 100644
index 000000000..a003a8274
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfma-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-add-options arm_neonv2 } */
+/* { dg-final { scan-assembler "vfma\\.f32\[	\]+\[dDqQ]" } } */
+
+/* Verify that VFMA is used.  */
+void f1(int n, float a, float x[], float y[]) {
+  int i;
+  for (i = 0; i < n; ++i)
+    y[i] = a * x[i] + y[i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfms-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfms-1.c
new file mode 100644
index 000000000..8cefd8a85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vfms-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-add-options arm_neonv2 } */
+/* { dg-final { scan-assembler "vfms\\.f32\[	\]+\[dDqQ]" } } */
+
+/* Verify that VFMS is used.  */
+void f1(int n, float a, float x[], float y[]) {
+  int i;
+  for (i = 0; i < n; ++i)
+    y[i] = a * -x[i] + y[i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c
new file mode 100644
index 000000000..5891e6619
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lane_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64_t out_int64_t = 0;
+  int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL;
+
+  out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
+  if (out_int64_t != (int64_t)arg0_int64x1_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c
new file mode 100644
index 000000000..b0ce070d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lane_u64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64_t out_uint64_t = 0;
+  uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL;
+
+  out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
+  if (out_uint64_t != (uint64_t)arg0_uint64x1_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld-1.c
new file mode 100644
index 000000000..f6bf6911d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O1" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint8x16_t
+foo (uint8_t *a, uint8x16_t b)
+{
+  vst1q_lane_u8 (a, b, 14);
+  return vld1q_lane_u8 (a + 0x100, b, 15);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld1_dupQ.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld1_dupQ.c
new file mode 100644
index 000000000..cf8396643
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld1_dupQ.c
@@ -0,0 +1,24 @@
+/* Test the `vld1q_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t input[2] = {(int64x1_t)0x0123456776543210LL,
+			(int64x1_t)0x89abcdeffedcba90LL};
+  int64x1_t output[2] = {0, 0};
+  int64x2_t var = vld1q_dup_s64((int64_t *)input);
+
+  vst1q_s64((int64_t *)output, var);
+  if (output[0] != (int64x1_t)0x0123456776543210LL)
+    abort();
+  if (output[1] != (int64x1_t)0x0123456776543210LL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld3-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld3-1.c
new file mode 100644
index 000000000..0cc5c8826
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vld3-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint32_t buffer[12];
+
+void __attribute__((noinline))
+foo (uint32_t *a)
+{
+  uint32x4x3_t x;
+
+  x = vld3q_u32 (a);
+  x.val[0] = vaddq_u32 (x.val[0], x.val[1]);
+  vst3q_u32 (a, x);
+}
+
+int
+main (void)
+{
+  buffer[0] = 1;
+  buffer[1] = 2;
+  foo (buffer);
+  return buffer[0] != 3;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c
new file mode 100644
index 000000000..e66637168
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vlshr-imm-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-final { scan-assembler "vshr\.u32.*#3" } } */
+
+/* Verify that VSHR immediate is used.  */
+void f1(int n, unsigned int x[], unsigned int y[]) {
+  int i;
+  for (i = 0; i < n; ++i)
+    y[i] = x[i] >> 3;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmla-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmla-1.c
new file mode 100644
index 000000000..c60c014e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmla-1.c
@@ -0,0 +1,11 @@
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-add-options arm_neon } */
+/* { dg-final { scan-assembler "vmla\\.i32" } } */
+
+/* Verify that VMLA is used.  */
+void f1(int n, int a, int x[], int y[]) {
+  int i;
+  for (i = 0; i < n; ++i)
+    y[i] = a * x[i] + y[i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmls-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmls-1.c
new file mode 100644
index 000000000..89ee82b0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmls-1.c
@@ -0,0 +1,11 @@
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2 -ftree-vectorize -ffast-math" } */
+/* { dg-add-options arm_neon } */
+/* { dg-final { scan-assembler "vmls\\.i32" } } */
+
+/* Verify that VMLS is used.  */
+void f1(int n, int a, int x[], int y[]) {
+  int i;
+  for (i = 0; i < n; ++i)
+    y[i] = y[i] - a * x[i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c
new file mode 100644
index 000000000..5a8abdce0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c
@@ -0,0 +1,22 @@
+/* Test the `vmovq_ns64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x2_t out_int64x2_t = {0, 0};
+  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
+
+  out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+  if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
+    abort();
+  if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c
new file mode 100644
index 000000000..8012fc175
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c
@@ -0,0 +1,23 @@
+/* Test the `vmovq_nu64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x2_t out_uint64x2_t = {0, 0};
+  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
+
+  out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+  if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
+    abort();
+  if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
+    abort();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c
new file mode 100644
index 000000000..c125f4a24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_ns64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
+
+  out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+  if ((int64_t)out_int64x1_t != arg0_int64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c
new file mode 100644
index 000000000..71ecaed13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_nu64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
+
+  out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+  if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c
new file mode 100644
index 000000000..6f2d20b6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorn-vbic.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-add-options arm_neon } */
+
+void bor (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b)
+{
+  int i;
+  for (i = 0; i < 9; i++)
+    c[i] = b[i] | (~a[i]);
+}
+void bic (int *__restrict__ c, int *__restrict__ a, int *__restrict__ b)
+{
+  int i;
+  for (i = 0; i < 9; i++)
+    c[i] = b[i] & (~a[i]);
+}
+
+/* { dg-final { scan-assembler "vorn\\t" } } */
+/* { dg-final { scan-assembler "vbic\\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorns64.c
new file mode 100644
index 000000000..364dbd190
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorns64.c
@@ -0,0 +1,21 @@
+/* Test the `vorn_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
+  int64x1_t arg1_int64x1_t = (int64x1_t)(~0xdead00000000beefLL);
+
+  out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+  if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vornu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vornu64.c
new file mode 100644
index 000000000..b35286846
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vornu64.c
@@ -0,0 +1,21 @@
+/* Test the `vorn_u64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
+  uint64x1_t arg1_uint64x1_t = (uint64x1_t)(~0xdead00000000beefLL);
+
+  out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+  if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorrs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorrs64.c
new file mode 100644
index 000000000..90ced9e9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorrs64.c
@@ -0,0 +1,21 @@
+/* Test the `vorr_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeef00000000LL;
+  int64x1_t arg1_int64x1_t = (int64x1_t)0xdead00000000beefLL;
+
+  out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+  if (out_int64x1_t != (int64x1_t)0xdeadbeef0000beefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorru64.c
new file mode 100644
index 000000000..5b44afb07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vorru64.c
@@ -0,0 +1,21 @@
+/* Test the `vorr_u64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeef00000000LL;
+  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0xdead00000000beefLL;
+
+  out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+  if (out_uint64x1_t != (uint64x1_t)0xdeadbeef0000beefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vrev.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vrev.c
new file mode 100644
index 000000000..10f41bc32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vrev.c
@@ -0,0 +1,105 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x4_t
+tst_vrev642_u16 (uint16x4_t __a)
+{
+  uint16x4_t __rv;
+  uint16x4_t __mask1 = { 3, 2, 1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint16x8_t
+tst_vrev64q2_u16 (uint16x8_t __a)
+{
+  uint16x8_t __rv;
+  uint16x8_t __mask1 = {3, 2, 1, 0, 7, 6, 5, 4 };
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint8x8_t
+tst_vrev642_u8 (uint8x8_t __a)
+{
+  uint8x8_t __rv;
+  uint8x8_t __mask1 = { 7, 6, 5, 4, 3, 2, 1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint8x16_t
+tst_vrev64q2_u8 (uint8x16_t __a)
+{
+  uint8x16_t __rv;
+  uint8x16_t __mask1 = {7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8};
+  return __builtin_shuffle ( __a, __mask1) ;
+
+}
+
+uint32x2_t
+tst_vrev642_u32 (uint32x2_t __a)
+{
+  uint32x2_t __rv;
+  uint32x2_t __mask1 = {1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+
+}
+
+uint32x4_t
+tst_vrev64q2_u32 (uint32x4_t __a)
+{
+  uint32x4_t __rv;
+  uint32x4_t __mask1 = {1, 0, 3, 2};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint16x4_t
+tst_vrev322_u16 (uint16x4_t __a)
+{
+  uint16x4_t __mask1 = { 1, 0, 3, 2 };
+  return __builtin_shuffle (__a, __mask1);
+}
+
+uint16x8_t
+tst_vrev32q2_u16 (uint16x8_t __a)
+{
+  uint16x8_t __mask1 = { 1, 0, 3, 2, 5, 4, 7, 6 }; 
+  return __builtin_shuffle (__a, __mask1);
+}
+
+uint8x8_t
+tst_vrev322_u8 (uint8x8_t __a)
+{
+  uint8x8_t __mask1 = { 3, 2, 1, 0, 7, 6, 5, 4};
+  return __builtin_shuffle (__a, __mask1);
+}
+
+uint8x16_t
+tst_vrev32q2_u8 (uint8x16_t __a)
+{
+  uint8x16_t __mask1 = { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12};
+  return __builtin_shuffle (__a, __mask1);
+}
+
+uint8x8_t
+tst_vrev162_u8 (uint8x8_t __a)
+{
+  uint8x8_t __mask = { 1, 0, 3, 2, 5, 4, 7, 6};
+  return __builtin_shuffle (__a, __mask);
+}
+
+uint8x16_t
+tst_vrev16q2_u8 (uint8x16_t __a)
+{
+  uint8x16_t __mask = { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14};
+  return __builtin_shuffle (__a, __mask);
+}
+
+/* { dg-final {scan-assembler-times "vrev32\.16\\t" 2} }  */
+/* { dg-final {scan-assembler-times "vrev32\.8\\t" 2} }  */ 
+/* { dg-final {scan-assembler-times "vrev16\.8\\t" 2} }  */
+/* { dg-final {scan-assembler-times "vrev64\.8\\t" 2} }  */
+/* { dg-final {scan-assembler-times "vrev64\.32\\t" 2} }  */
+/* { dg-final {scan-assembler-times "vrev64\.16\\t" 2} }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c
new file mode 100644
index 000000000..101139327
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c
@@ -0,0 +1,21 @@
+/* Test the `vset_lane_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64_t arg0_int64_t = 0xf00f00f00LL;
+  int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL;
+
+  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+  if ((int64_t)out_int64x1_t != arg0_int64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c
new file mode 100644
index 000000000..51d38fd1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_lanes8.c
@@ -0,0 +1,24 @@
+/* Test the `vset_lane_s8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+#include <string.h>
+
+int8_t x_init[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+int8_t y_init[8] = { 1, 2, 3, 16, 5, 6, 7, 8 };
+
+int main (void)
+{
+  int8x8_t x = vld1_s8 (x_init);
+  int8x8_t y = vld1_s8 (y_init);
+
+  x = vset_lane_s8 (16, x, 3);
+  if (memcmp (&x, &y, sizeof (x)) != 0)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c
new file mode 100644
index 000000000..cafc26076
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c
@@ -0,0 +1,21 @@
+/* Test the `vset_lane_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64_t arg0_uint64_t = 0xf00f00f00LL;
+  uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL;
+
+  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+  if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c
new file mode 100644
index 000000000..913d5959b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshl-imm-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-final { scan-assembler "vshl\.i32.*#3" } } */
+
+/* Verify that VSHR immediate is used.  */
+void f1(int n, int x[], int y[]) {
+  int i;
+  for (i = 0; i < n; ++i)
+    y[i] = x[i] << 3;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c
new file mode 100644
index 000000000..82a3c5cfb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vshr-imm-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-final { scan-assembler "vshr\.s32.*#3" } } */
+
+/* Verify that VSHR immediate is used.  */
+void f1(int n, int x[], int y[]) {
+  int i;
+  for (i = 0; i < n; ++i)
+    y[i] = x[i] >> 3;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vst3-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vst3-1.c
new file mode 100644
index 000000000..a3bee6cb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vst3-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint32_t buffer[64];
+
+void __attribute__((noinline))
+foo (uint32_t *a)
+{
+  uint32x4x3_t x;
+
+  x = vld3q_u32 (a);
+  a[35] = 1;
+  vst3q_lane_u32 (a + 32, x, 1);
+}
+
+int
+main (void)
+{
+  foo (buffer);
+  return buffer[35] != 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubs64.c
new file mode 100644
index 000000000..239470041
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubs64.c
@@ -0,0 +1,21 @@
+/* Test the `vsub_s64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  int64x1_t out_int64x1_t = 0;
+  int64x1_t arg0_int64x1_t = (int64x1_t)0xdeadbeefdeadbeefLL;
+  int64x1_t arg1_int64x1_t = (int64x1_t)0x0000beefdead0000LL;
+
+  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+  if (out_int64x1_t != (int64x1_t)0xdead00000000beefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubu64.c
new file mode 100644
index 000000000..0162e206e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vsubu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsub_u64' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main (void)
+{
+  uint64x1_t out_uint64x1_t = 0;
+  uint64x1_t arg0_uint64x1_t = (uint64x1_t)0xdeadbeefdeadbeefLL;
+  uint64x1_t arg1_uint64x1_t = (uint64x1_t)0x0000beefdead0000LL;
+
+  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+  if (out_uint64x1_t != (uint64x1_t)0xdead00000000beefLL)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c
new file mode 100644
index 000000000..3a0b117c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon-vtst_p64.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+#include <stdio.h>
+
+extern void abort (void);
+
+int
+main (void)
+{
+  uint64_t args[] = { 0x0, 0xdeadbeef, ~0xdeadbeef, 0xffff,
+                      ~0xffff, 0xffffffff, ~0xffffffff, ~0x0 };
+  int i, j;
+
+  for (i = 0; i < sizeof (args) / sizeof (args[0]); ++i)
+    {
+       for (j = 0; j < sizeof (args) / sizeof (args[0]); ++j)
+         {
+           uint64_t a1 = args[i];
+           uint64_t a2 = args[j];
+           uint64_t res = vtst_p64 (vreinterpret_p64_u64 (a1),
+                                    vreinterpret_p64_u64 (a2));
+           uint64_t exp = (a1 & a2) ? ~0x0 : 0x0;
+
+           if (res != exp)
+             {
+               fprintf (stderr, "vtst_p64 (a1= %lx, a2= %lx)"
+                                " returned %lx, expected %lx\n",
+                                 a1, a2, res, exp);
+               abort ();
+             }
+         }
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp
new file mode 100644
index 000000000..746429dad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/neon.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an ARM target.
+if ![istarget arm*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c
new file mode 100644
index 000000000..f91f800a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/polytypes.c
@@ -0,0 +1,48 @@
+/* Check that NEON polynomial vector types are suitably incompatible with
+   integer vector types of the same layout.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+void s64_8 (int8x8_t a) {}
+void u64_8 (uint8x8_t a) {}
+void p64_8 (poly8x8_t a) {}
+void s64_16 (int16x4_t a) {}
+void u64_16 (uint16x4_t a) {}
+void p64_16 (poly16x4_t a) {}
+
+void s128_8 (int8x16_t a) {}
+void u128_8 (uint8x16_t a) {}
+void p128_8 (poly8x16_t a) {}
+void s128_16 (int16x8_t a) {}
+void u128_16 (uint16x8_t a) {}
+void p128_16 (poly16x8_t a) {}
+
+void foo ()
+{
+  poly8x8_t v64_8;
+  poly16x4_t v64_16;
+  poly8x16_t v128_8;
+  poly16x8_t v128_16;
+
+  s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */
+  /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */
+  u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
+  p64_8 (v64_8);
+
+  s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
+  u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
+  p64_16 (v64_16);
+
+  s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
+  u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
+  p128_8 (v128_8);
+
+  s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
+  u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
+  p128_16 (v128_16);
+}
+/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c
new file mode 100644
index 000000000..71cbb055f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/pr51534.c
@@ -0,0 +1,84 @@
+/* Test the vector comparison intrinsics when comparing to immediate zero.
+   */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+#define GEN_TEST(T, D, C, R) \
+  R test_##C##_##T (T a) { return C (a, D (0)); }
+
+#define GEN_DOUBLE_TESTS(S, T, C) \
+  GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
+  GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T) 
+
+#define GEN_QUAD_TESTS(S, T, C) \
+  GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
+  GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T) 
+
+#define GEN_COND_TESTS(C) \
+  GEN_DOUBLE_TESTS (8, int8x8_t, C) \
+  GEN_DOUBLE_TESTS (16, int16x4_t, C) \
+  GEN_DOUBLE_TESTS (32, int32x2_t, C) \
+  GEN_QUAD_TESTS (8, int8x16_t, C) \
+  GEN_QUAD_TESTS (16, int16x8_t, C) \
+  GEN_QUAD_TESTS (32, int32x4_t, C)
+
+GEN_COND_TESTS(vcgt)
+GEN_COND_TESTS(vcge)
+GEN_COND_TESTS(vclt)
+GEN_COND_TESTS(vcle)
+GEN_COND_TESTS(vceq)
+
+/* Scan for expected outputs.  */
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+/* { dg-final { scan-assembler-times "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" } } */
+/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+/* { dg-final { scan-assembler-times "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+/* { dg-final { scan-assembler-times "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+/* { dg-final { scan-assembler-times "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+
+/* And ensure we don't have unexpected output too.  */
+/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ 	\]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
+
+/* Tidy up.  */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
new file mode 100644
index 000000000..8a8032d01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
@@ -0,0 +1,21 @@
+/* Test the `vRaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vraddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
new file mode 100644
index 000000000..45b577631
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns32.c
@@ -0,0 +1,21 @@
+/* Test the `vRaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vraddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
new file mode 100644
index 000000000..4e564ee10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhns64.c
@@ -0,0 +1,21 @@
+/* Test the `vRaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vraddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
new file mode 100644
index 000000000..f036e0438
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu16.c
@@ -0,0 +1,21 @@
+/* Test the `vRaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vraddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
new file mode 100644
index 000000000..f9fbb869d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu32.c
@@ -0,0 +1,21 @@
+/* Test the `vRaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vraddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
new file mode 100644
index 000000000..853ab7fcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRaddhnu64.c
@@ -0,0 +1,21 @@
+/* Test the `vRaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vraddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vraddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
new file mode 100644
index 000000000..1be084ede
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
new file mode 100644
index 000000000..acc6c0176
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
new file mode 100644
index 000000000..bfac186e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
new file mode 100644
index 000000000..10dcdfe12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
new file mode 100644
index 000000000..9c6178135
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
new file mode 100644
index 000000000..ac8488498
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
new file mode 100644
index 000000000..a1207e2d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds16.c
@@ -0,0 +1,21 @@
+/* Test the `vRhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
new file mode 100644
index 000000000..758572982
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds32.c
@@ -0,0 +1,21 @@
+/* Test the `vRhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
new file mode 100644
index 000000000..c6048c2e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhadds8.c
@@ -0,0 +1,21 @@
+/* Test the `vRhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
new file mode 100644
index 000000000..41e03fe6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu16.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
new file mode 100644
index 000000000..f0cdae6d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu32.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
new file mode 100644
index 000000000..278496f28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRhaddu8.c
@@ -0,0 +1,21 @@
+/* Test the `vRhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
new file mode 100644
index 000000000..622cd3843
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
new file mode 100644
index 000000000..9d6c8b849
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
new file mode 100644
index 000000000..d9f1accae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
new file mode 100644
index 000000000..695e9e17f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
new file mode 100644
index 000000000..1abf88844
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
new file mode 100644
index 000000000..ee517d83b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
new file mode 100644
index 000000000..ec46e7632
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
new file mode 100644
index 000000000..3abdefcd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
new file mode 100644
index 000000000..5d13fac3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls16.c
@@ -0,0 +1,21 @@
+/* Test the `vRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
new file mode 100644
index 000000000..71ed3401f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls32.c
@@ -0,0 +1,21 @@
+/* Test the `vRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
new file mode 100644
index 000000000..c6e20c0dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls64.c
@@ -0,0 +1,21 @@
+/* Test the `vRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
new file mode 100644
index 000000000..b4cc42739
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshls8.c
@@ -0,0 +1,21 @@
+/* Test the `vRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
new file mode 100644
index 000000000..42c77250c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu16.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
new file mode 100644
index 000000000..dfc5da7f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu32.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
new file mode 100644
index 000000000..030b5eed3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu64.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
new file mode 100644
index 000000000..2e091b39b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshlu8.c
@@ -0,0 +1,21 @@
+/* Test the `vRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
new file mode 100644
index 000000000..f844a5bfd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
new file mode 100644
index 000000000..a651bf484
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
new file mode 100644
index 000000000..2e78282d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vrshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
new file mode 100644
index 000000000..376fcf1d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
new file mode 100644
index 000000000..ae1555dcf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
new file mode 100644
index 000000000..18ec347c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
new file mode 100644
index 000000000..370ae502f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vrshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
new file mode 100644
index 000000000..5c5149ed0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
new file mode 100644
index 000000000..3045dddee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
new file mode 100644
index 000000000..2c3c12665
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
new file mode 100644
index 000000000..182c56b86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vrshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
new file mode 100644
index 000000000..1e41c26be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
new file mode 100644
index 000000000..c34b54e22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
new file mode 100644
index 000000000..c07863ec1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
new file mode 100644
index 000000000..910d7de54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vrshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
new file mode 100644
index 000000000..25b5a6b5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshr_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vRshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
new file mode 100644
index 000000000..966e6c78e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
new file mode 100644
index 000000000..6227223e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
new file mode 100644
index 000000000..d219e9482
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
new file mode 100644
index 000000000..9f59e8c3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
new file mode 100644
index 000000000..d7904ea56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
new file mode 100644
index 000000000..33d390157
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRshrn_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
new file mode 100644
index 000000000..cb7c469a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vRsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vrsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
new file mode 100644
index 000000000..3ac2e316e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vRsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vrsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
new file mode 100644
index 000000000..d0b6a9272
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns64.c
@@ -0,0 +1,21 @@
+/* Test the `vRsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vrsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
new file mode 100644
index 000000000..af402f4f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_ns8.c
@@ -0,0 +1,21 @@
+/* Test the `vRsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vrsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
new file mode 100644
index 000000000..b8c0fbf1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vRsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vrsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
new file mode 100644
index 000000000..7bec98340
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vRsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vrsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
new file mode 100644
index 000000000..167a27c4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu64.c
@@ -0,0 +1,21 @@
+/* Test the `vRsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vrsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
new file mode 100644
index 000000000..14a6251fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsraQ_nu8.c
@@ -0,0 +1,21 @@
+/* Test the `vRsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vrsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
new file mode 100644
index 000000000..31d6f0ca3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vRsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vrsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
new file mode 100644
index 000000000..43fa61aac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vRsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vrsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
new file mode 100644
index 000000000..1b28f926a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns64.c
@@ -0,0 +1,21 @@
+/* Test the `vRsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vrsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
new file mode 100644
index 000000000..fc810c2cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_ns8.c
@@ -0,0 +1,21 @@
+/* Test the `vRsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vrsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
new file mode 100644
index 000000000..d951b266b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vRsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vrsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
new file mode 100644
index 000000000..f7f74c3c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vRsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vrsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
new file mode 100644
index 000000000..713c7bb1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu64.c
@@ -0,0 +1,21 @@
+/* Test the `vRsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vrsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
new file mode 100644
index 000000000..4b19bd846
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsra_nu8.c
@@ -0,0 +1,21 @@
+/* Test the `vRsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vrsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vrsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
new file mode 100644
index 000000000..8ba5a2075
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns16.c
@@ -0,0 +1,21 @@
+/* Test the `vRsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vrsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
new file mode 100644
index 000000000..26fa452c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns32.c
@@ -0,0 +1,21 @@
+/* Test the `vRsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vrsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
new file mode 100644
index 000000000..ed990790f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhns64.c
@@ -0,0 +1,21 @@
+/* Test the `vRsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vrsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
new file mode 100644
index 000000000..b5e7b28ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu16.c
@@ -0,0 +1,21 @@
+/* Test the `vRsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vrsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
new file mode 100644
index 000000000..5275c97b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu32.c
@@ -0,0 +1,21 @@
+/* Test the `vRsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vrsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
new file mode 100644
index 000000000..3951ff0c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vRsubhnu64.c
@@ -0,0 +1,21 @@
+/* Test the `vRsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vRsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vrsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
new file mode 100644
index 000000000..4fe8aa303
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs16.c
@@ -0,0 +1,22 @@
+/* Test the `vabaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vabaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
new file mode 100644
index 000000000..0e2b06fdd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs32.c
@@ -0,0 +1,22 @@
+/* Test the `vabaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vabaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
new file mode 100644
index 000000000..679805ad6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQs8.c
@@ -0,0 +1,22 @@
+/* Test the `vabaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vabaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
new file mode 100644
index 000000000..87e5f2232
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu16.c
@@ -0,0 +1,22 @@
+/* Test the `vabaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vabaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
new file mode 100644
index 000000000..91ee45dfa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu32.c
@@ -0,0 +1,22 @@
+/* Test the `vabaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vabaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
new file mode 100644
index 000000000..f4adb3272
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabaQu8.c
@@ -0,0 +1,22 @@
+/* Test the `vabaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vabaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c
new file mode 100644
index 000000000..14f8aa0d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals16.c
@@ -0,0 +1,22 @@
+/* Test the `vabals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vabal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c
new file mode 100644
index 000000000..980b27e6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals32.c
@@ -0,0 +1,22 @@
+/* Test the `vabals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vabal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c
new file mode 100644
index 000000000..85dcb40b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabals8.c
@@ -0,0 +1,22 @@
+/* Test the `vabals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vabal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
new file mode 100644
index 000000000..9cf105ee3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu16.c
@@ -0,0 +1,22 @@
+/* Test the `vabalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vabal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
new file mode 100644
index 000000000..dc9925f58
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu32.c
@@ -0,0 +1,22 @@
+/* Test the `vabalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vabal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
new file mode 100644
index 000000000..464e2cdad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabalu8.c
@@ -0,0 +1,22 @@
+/* Test the `vabalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vabal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c
new file mode 100644
index 000000000..21f5adbdd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas16.c
@@ -0,0 +1,22 @@
+/* Test the `vabas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vaba_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c
new file mode 100644
index 000000000..f9a41481e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas32.c
@@ -0,0 +1,22 @@
+/* Test the `vabas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vaba_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c
new file mode 100644
index 000000000..609680a05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabas8.c
@@ -0,0 +1,22 @@
+/* Test the `vabas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vaba_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c
new file mode 100644
index 000000000..0896900fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau16.c
@@ -0,0 +1,22 @@
+/* Test the `vabau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vaba_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c
new file mode 100644
index 000000000..4f4f25abd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau32.c
@@ -0,0 +1,22 @@
+/* Test the `vabau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vaba_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c
new file mode 100644
index 000000000..91dfc1a83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabau8.c
@@ -0,0 +1,22 @@
+/* Test the `vabau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vaba_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaba\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
new file mode 100644
index 000000000..50c1acc63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vabdQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vabdq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
new file mode 100644
index 000000000..7ef3f2edd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vabdQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vabdq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
new file mode 100644
index 000000000..673b01f2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vabdQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vabdq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
new file mode 100644
index 000000000..5d24d228f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vabdQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vabdq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
new file mode 100644
index 000000000..222384e1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabdQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vabdq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
new file mode 100644
index 000000000..ef5716b69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabdQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vabdq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
new file mode 100644
index 000000000..065a5f3be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabdQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vabdq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
new file mode 100644
index 000000000..8fc0be271
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdf32.c
@@ -0,0 +1,21 @@
+/* Test the `vabdf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vabd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
new file mode 100644
index 000000000..e9df745b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls16.c
@@ -0,0 +1,21 @@
+/* Test the `vabdls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vabdl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
new file mode 100644
index 000000000..b4ad32735
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls32.c
@@ -0,0 +1,21 @@
+/* Test the `vabdls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vabdl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
new file mode 100644
index 000000000..75ca12502
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdls8.c
@@ -0,0 +1,21 @@
+/* Test the `vabdls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vabdl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
new file mode 100644
index 000000000..692962ede
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabdlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vabdl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
new file mode 100644
index 000000000..f5a7ef691
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabdlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vabdl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
new file mode 100644
index 000000000..221729ae6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdlu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabdlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vabdl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabdl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c
new file mode 100644
index 000000000..2d76a286d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds16.c
@@ -0,0 +1,21 @@
+/* Test the `vabds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vabd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c
new file mode 100644
index 000000000..9ca6e5d8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds32.c
@@ -0,0 +1,21 @@
+/* Test the `vabds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vabd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c
new file mode 100644
index 000000000..561687047
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabds8.c
@@ -0,0 +1,21 @@
+/* Test the `vabds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vabd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
new file mode 100644
index 000000000..e23873494
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu16.c
@@ -0,0 +1,21 @@
+/* Test the `vabdu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vabd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
new file mode 100644
index 000000000..61871dda4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu32.c
@@ -0,0 +1,21 @@
+/* Test the `vabdu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vabd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
new file mode 100644
index 000000000..bff9f9cf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabdu8.c
@@ -0,0 +1,21 @@
+/* Test the `vabdu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabdu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vabd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
new file mode 100644
index 000000000..36e145d08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vabsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vabsq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
new file mode 100644
index 000000000..befade576
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vabsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
new file mode 100644
index 000000000..8d1270012
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vabsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
new file mode 100644
index 000000000..a69d7a89e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vabsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
new file mode 100644
index 000000000..e60dd896d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabsf32.c
@@ -0,0 +1,20 @@
+/* Test the `vabsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vabs_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c
new file mode 100644
index 000000000..9cc1ab561
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss16.c
@@ -0,0 +1,20 @@
+/* Test the `vabss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c
new file mode 100644
index 000000000..5f3c6353e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss32.c
@@ -0,0 +1,20 @@
+/* Test the `vabss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c
new file mode 100644
index 000000000..05ae5241a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vabss8.c
@@ -0,0 +1,20 @@
+/* Test the `vabss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vabss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
new file mode 100644
index 000000000..fb856385d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vaddq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
new file mode 100644
index 000000000..839af2433
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
new file mode 100644
index 000000000..f93a83221
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
new file mode 100644
index 000000000..fdc99171a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
new file mode 100644
index 000000000..49fe47812
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
new file mode 100644
index 000000000..2f6ac31a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
new file mode 100644
index 000000000..3c279b4ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
new file mode 100644
index 000000000..c525a85d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
new file mode 100644
index 000000000..975dfa37c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
new file mode 100644
index 000000000..15364b77c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddf32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
new file mode 100644
index 000000000..d39d14a27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vaddhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
new file mode 100644
index 000000000..52d622164
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vaddhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
new file mode 100644
index 000000000..cb593a2ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhns64.c
@@ -0,0 +1,21 @@
+/* Test the `vaddhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vaddhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
new file mode 100644
index 000000000..59d311fa0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vaddhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
new file mode 100644
index 000000000..570b8855b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vaddhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
new file mode 100644
index 000000000..2156254e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddhnu64.c
@@ -0,0 +1,21 @@
+/* Test the `vaddhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vaddhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
new file mode 100644
index 000000000..0ee3e4908
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vaddl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
new file mode 100644
index 000000000..3cd0978cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vaddl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
new file mode 100644
index 000000000..50e5197ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddls8.c
@@ -0,0 +1,21 @@
+/* Test the `vaddls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vaddl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
new file mode 100644
index 000000000..671fc9250
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vaddl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
new file mode 100644
index 000000000..5a69ba320
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vaddl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
new file mode 100644
index 000000000..723b45e80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddlu8.c
@@ -0,0 +1,21 @@
+/* Test the `vaddlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vaddl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c
new file mode 100644
index 000000000..4f2250e8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds16.c
@@ -0,0 +1,21 @@
+/* Test the `vadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c
new file mode 100644
index 000000000..bc030289d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds32.c
@@ -0,0 +1,21 @@
+/* Test the `vadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c
new file mode 100644
index 000000000..fb17e0ea3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds64.c
@@ -0,0 +1,20 @@
+/* Test the `vadds64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vadds64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c
new file mode 100644
index 000000000..e928b1250
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vadds8.c
@@ -0,0 +1,21 @@
+/* Test the `vadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
new file mode 100644
index 000000000..9564df38e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
new file mode 100644
index 000000000..2bc009e3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
new file mode 100644
index 000000000..18fc500b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu64.c
@@ -0,0 +1,20 @@
+/* Test the `vaddu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
new file mode 100644
index 000000000..625931b3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddu8.c
@@ -0,0 +1,21 @@
+/* Test the `vaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
new file mode 100644
index 000000000..b99025334
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vaddw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
new file mode 100644
index 000000000..447b8919b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vaddw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
new file mode 100644
index 000000000..f604c1ebf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddws8.c
@@ -0,0 +1,21 @@
+/* Test the `vaddws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vaddw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
new file mode 100644
index 000000000..f374bef96
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu16.c
@@ -0,0 +1,21 @@
+/* Test the `vaddwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vaddw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
new file mode 100644
index 000000000..211f79897
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu32.c
@@ -0,0 +1,21 @@
+/* Test the `vaddwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vaddw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
new file mode 100644
index 000000000..ae9601608
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vaddwu8.c
@@ -0,0 +1,21 @@
+/* Test the `vaddwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vaddwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vaddw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vaddw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
new file mode 100644
index 000000000..87c030442
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vandQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vandq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
new file mode 100644
index 000000000..3ae1a5218
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vandQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vandq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
new file mode 100644
index 000000000..cca486875
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vandQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vandq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
new file mode 100644
index 000000000..4d0ce17cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vandQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vandq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
new file mode 100644
index 000000000..ff7d646a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vandQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vandq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
new file mode 100644
index 000000000..a99a525b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vandQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vandq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
new file mode 100644
index 000000000..2484dd04c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vandQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vandq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
new file mode 100644
index 000000000..c20979fcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vandQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vandq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c
new file mode 100644
index 000000000..dbb2c622f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands16.c
@@ -0,0 +1,21 @@
+/* Test the `vands16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vands16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vand_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c
new file mode 100644
index 000000000..61c0c4113
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands32.c
@@ -0,0 +1,21 @@
+/* Test the `vands32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vands32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vand_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c
new file mode 100644
index 000000000..13e18fb0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands64.c
@@ -0,0 +1,20 @@
+/* Test the `vands64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vands64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vand_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c
new file mode 100644
index 000000000..526a50072
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vands8.c
@@ -0,0 +1,21 @@
+/* Test the `vands8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vands8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vand_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c
new file mode 100644
index 000000000..5c998856f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu16.c
@@ -0,0 +1,21 @@
+/* Test the `vandu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vand_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c
new file mode 100644
index 000000000..8a936e673
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu32.c
@@ -0,0 +1,21 @@
+/* Test the `vandu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vand_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c
new file mode 100644
index 000000000..d9ddf847a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu64.c
@@ -0,0 +1,20 @@
+/* Test the `vandu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vand_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c
new file mode 100644
index 000000000..728c5a6d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vandu8.c
@@ -0,0 +1,21 @@
+/* Test the `vandu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vandu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vand_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vand\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
new file mode 100644
index 000000000..e15a260ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vbicQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vbicq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
new file mode 100644
index 000000000..f376bf077
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vbicQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vbicq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
new file mode 100644
index 000000000..87049f129
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vbicQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vbicq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
new file mode 100644
index 000000000..4f64e8817
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vbicQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vbicq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
new file mode 100644
index 000000000..f92f9b384
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vbicQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vbicq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
new file mode 100644
index 000000000..06d10da23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vbicQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vbicq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
new file mode 100644
index 000000000..7cd63c035
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vbicQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vbicq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
new file mode 100644
index 000000000..3f44418d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vbicQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vbicq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c
new file mode 100644
index 000000000..943e30534
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics16.c
@@ -0,0 +1,21 @@
+/* Test the `vbics16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbics16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vbic_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c
new file mode 100644
index 000000000..30df639e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics32.c
@@ -0,0 +1,21 @@
+/* Test the `vbics32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbics32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vbic_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c
new file mode 100644
index 000000000..379db45f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics64.c
@@ -0,0 +1,20 @@
+/* Test the `vbics64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbics64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vbic_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c
new file mode 100644
index 000000000..3b4bc8a8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbics8.c
@@ -0,0 +1,21 @@
+/* Test the `vbics8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbics8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vbic_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
new file mode 100644
index 000000000..e9952bc52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu16.c
@@ -0,0 +1,21 @@
+/* Test the `vbicu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vbic_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
new file mode 100644
index 000000000..9334f403f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu32.c
@@ -0,0 +1,21 @@
+/* Test the `vbicu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vbic_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
new file mode 100644
index 000000000..c276d65eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu64.c
@@ -0,0 +1,20 @@
+/* Test the `vbicu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vbic_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
new file mode 100644
index 000000000..5e42c5237
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbicu8.c
@@ -0,0 +1,21 @@
+/* Test the `vbicu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbicu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vbic_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vbic\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
new file mode 100644
index 000000000..33bc0257e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
new file mode 100644
index 000000000..06db6555d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+  poly16x8_t arg2_poly16x8_t;
+
+  out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
new file mode 100644
index 000000000..519ee370d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vbslQp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+  poly64x2_t arg2_poly64x2_t;
+
+  out_poly64x2_t = vbslq_p64 (arg0_uint64x2_t, arg1_poly64x2_t, arg2_poly64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
new file mode 100644
index 000000000..52d498b8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+  poly8x16_t arg2_poly8x16_t;
+
+  out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
new file mode 100644
index 000000000..f8f090f52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
new file mode 100644
index 000000000..194ecdb35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
new file mode 100644
index 000000000..cba963da0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+  int64x2_t arg2_int64x2_t;
+
+  out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
new file mode 100644
index 000000000..fe8a64c5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
new file mode 100644
index 000000000..121ce1edc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu16.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vbslq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
new file mode 100644
index 000000000..dc213f1a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu32.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vbslq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
new file mode 100644
index 000000000..6635e652f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+  uint64x2_t arg2_uint64x2_t;
+
+  out_uint64x2_t = vbslq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, arg2_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
new file mode 100644
index 000000000..0fc6eb820
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslQu8.c
@@ -0,0 +1,22 @@
+/* Test the `vbslQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vbslq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
new file mode 100644
index 000000000..ea8750da5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
@@ -0,0 +1,22 @@
+/* Test the `vbslf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
new file mode 100644
index 000000000..632fea22f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
@@ -0,0 +1,22 @@
+/* Test the `vbslp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+  poly16x4_t arg2_poly16x4_t;
+
+  out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
new file mode 100644
index 000000000..51929274d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vbslp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+  poly64x1_t arg2_poly64x1_t;
+
+  out_poly64x1_t = vbsl_p64 (arg0_uint64x1_t, arg1_poly64x1_t, arg2_poly64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
new file mode 100644
index 000000000..a867a3b12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
@@ -0,0 +1,22 @@
+/* Test the `vbslp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  poly8x8_t arg2_poly8x8_t;
+
+  out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
new file mode 100644
index 000000000..849b8ff85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
@@ -0,0 +1,22 @@
+/* Test the `vbsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbsls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
new file mode 100644
index 000000000..734560180
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
@@ -0,0 +1,22 @@
+/* Test the `vbsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbsls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
new file mode 100644
index 000000000..79516cd89
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
@@ -0,0 +1,22 @@
+/* Test the `vbsls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbsls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+  int64x1_t arg2_int64x1_t;
+
+  out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
new file mode 100644
index 000000000..7cfd379b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
@@ -0,0 +1,22 @@
+/* Test the `vbsls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbsls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
new file mode 100644
index 000000000..aef15fa6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu16.c
@@ -0,0 +1,22 @@
+/* Test the `vbslu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vbsl_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
new file mode 100644
index 000000000..e04e349ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu32.c
@@ -0,0 +1,22 @@
+/* Test the `vbslu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vbsl_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
new file mode 100644
index 000000000..a4a53af2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu64.c
@@ -0,0 +1,22 @@
+/* Test the `vbslu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+  uint64x1_t arg2_uint64x1_t;
+
+  out_uint64x1_t = vbsl_u64 (arg0_uint64x1_t, arg1_uint64x1_t, arg2_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
new file mode 100644
index 000000000..154ea961d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vbslu8.c
@@ -0,0 +1,22 @@
+/* Test the `vbslu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vbslu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vbsl_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
new file mode 100644
index 000000000..8b5995525
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcageQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcageQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcageQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcageq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
new file mode 100644
index 000000000..0d45e320e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagef32.c
@@ -0,0 +1,21 @@
+/* Test the `vcagef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcagef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcage_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
new file mode 100644
index 000000000..cef77b38c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcagtQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcagtQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcagtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
new file mode 100644
index 000000000..89b875927
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcagtf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcagtf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcagtf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcagt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
new file mode 100644
index 000000000..8cfef154d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaleQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcaleQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcaleQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcaleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
new file mode 100644
index 000000000..1101fde68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcalef32.c
@@ -0,0 +1,21 @@
+/* Test the `vcalef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcalef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcale_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
new file mode 100644
index 000000000..1d2cf7445
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcaltQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcaltQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcaltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
new file mode 100644
index 000000000..6a8a8171e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcaltf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcaltf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcaltf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcalt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vacgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
new file mode 100644
index 000000000..14ad3e7dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vceqQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vceqq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
new file mode 100644
index 000000000..80a8f6233
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vceqQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vceqq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
new file mode 100644
index 000000000..843bfe0ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vceqQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vceqq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
new file mode 100644
index 000000000..f25faa5ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vceqQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vceqq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
new file mode 100644
index 000000000..77bda24d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vceqQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vceqq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
new file mode 100644
index 000000000..c6293f285
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vceqQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vceqq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
new file mode 100644
index 000000000..7090033be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vceqQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vceqq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
new file mode 100644
index 000000000..3ff24d546
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vceqQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vceqq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
new file mode 100644
index 000000000..b150b32c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqf32.c
@@ -0,0 +1,21 @@
+/* Test the `vceqf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vceq_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
new file mode 100644
index 000000000..2e4e608d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqp8.c
@@ -0,0 +1,21 @@
+/* Test the `vceqp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vceq_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
new file mode 100644
index 000000000..3cf450228
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs16.c
@@ -0,0 +1,21 @@
+/* Test the `vceqs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqs16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vceq_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
new file mode 100644
index 000000000..989484130
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs32.c
@@ -0,0 +1,21 @@
+/* Test the `vceqs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqs32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vceq_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
new file mode 100644
index 000000000..825214ae4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vceqs8.c
@@ -0,0 +1,21 @@
+/* Test the `vceqs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vceqs8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vceq_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
new file mode 100644
index 000000000..b7dd5450d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ16.c
@@ -0,0 +1,21 @@
+/* Test the `vcequ16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcequ16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vceq_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
new file mode 100644
index 000000000..7864cfdf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ32.c
@@ -0,0 +1,21 @@
+/* Test the `vcequ32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcequ32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vceq_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
new file mode 100644
index 000000000..8b8b26fba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcequ8.c
@@ -0,0 +1,21 @@
+/* Test the `vcequ8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcequ8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vceq_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vceq\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
new file mode 100644
index 000000000..b0eb53cfc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcgeq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
new file mode 100644
index 000000000..2ef989ac1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcgeq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
new file mode 100644
index 000000000..2bef01abb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcgeq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
new file mode 100644
index 000000000..15083d35e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcgeq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
new file mode 100644
index 000000000..59c609b65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcgeq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
new file mode 100644
index 000000000..fa4d67cf1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcgeq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
new file mode 100644
index 000000000..39dee295c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcgeq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
new file mode 100644
index 000000000..797f43f6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgef32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcge_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c
new file mode 100644
index 000000000..52984c796
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges16.c
@@ -0,0 +1,21 @@
+/* Test the `vcges16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcges16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcge_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c
new file mode 100644
index 000000000..935bde799
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges32.c
@@ -0,0 +1,21 @@
+/* Test the `vcges32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcges32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcge_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c
new file mode 100644
index 000000000..15abad3fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcges8.c
@@ -0,0 +1,21 @@
+/* Test the `vcges8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcges8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcge_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
new file mode 100644
index 000000000..ec96ebc74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu16.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcge_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
new file mode 100644
index 000000000..12c67bf7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcge_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
new file mode 100644
index 000000000..5457b91a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgeu8.c
@@ -0,0 +1,21 @@
+/* Test the `vcgeu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgeu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcge_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
new file mode 100644
index 000000000..9f6e6dc2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcgtq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
new file mode 100644
index 000000000..b733e6ffa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcgtq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
new file mode 100644
index 000000000..eae07ad12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcgtq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
new file mode 100644
index 000000000..2f82a9539
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcgtq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
new file mode 100644
index 000000000..080a7af7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcgtq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
new file mode 100644
index 000000000..0dfb361b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcgtq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
new file mode 100644
index 000000000..0643e22e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcgtq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
new file mode 100644
index 000000000..833bf1f55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcgt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
new file mode 100644
index 000000000..141df1061
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts16.c
@@ -0,0 +1,21 @@
+/* Test the `vcgts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcgt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
new file mode 100644
index 000000000..6350041d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcgt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
new file mode 100644
index 000000000..1ad43968a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgts8.c
@@ -0,0 +1,21 @@
+/* Test the `vcgts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcgt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
new file mode 100644
index 000000000..e3b2c80c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu16.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcgt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
new file mode 100644
index 000000000..60e6a9f1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu32.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcgt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
new file mode 100644
index 000000000..858647548
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcgtu8.c
@@ -0,0 +1,21 @@
+/* Test the `vcgtu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcgtu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcgt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
new file mode 100644
index 000000000..770da7b04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcleQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcleq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
new file mode 100644
index 000000000..f4f69e2b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vcleQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcleq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
new file mode 100644
index 000000000..49d6cc0f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vcleQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcleq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
new file mode 100644
index 000000000..32447e67a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vcleQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcleq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
new file mode 100644
index 000000000..3c8ae5217
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vcleQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcleq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
new file mode 100644
index 000000000..e2556e38e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vcleQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcleq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
new file mode 100644
index 000000000..48e3ee239
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vcleQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcleq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c
new file mode 100644
index 000000000..88fa76483
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclef32.c
@@ -0,0 +1,21 @@
+/* Test the `vclef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclef32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vcle_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c
new file mode 100644
index 000000000..885c5d510
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles16.c
@@ -0,0 +1,21 @@
+/* Test the `vcles16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcles16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vcle_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c
new file mode 100644
index 000000000..5bbd0d2d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles32.c
@@ -0,0 +1,21 @@
+/* Test the `vcles32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcles32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vcle_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c
new file mode 100644
index 000000000..e247608db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcles8.c
@@ -0,0 +1,21 @@
+/* Test the `vcles8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcles8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vcle_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
new file mode 100644
index 000000000..6fcacbadd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu16.c
@@ -0,0 +1,21 @@
+/* Test the `vcleu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vcle_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
new file mode 100644
index 000000000..568f56f99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu32.c
@@ -0,0 +1,21 @@
+/* Test the `vcleu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vcle_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
new file mode 100644
index 000000000..81884bf72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcleu8.c
@@ -0,0 +1,21 @@
+/* Test the `vcleu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcleu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vcle_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcge\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
new file mode 100644
index 000000000..22009dce0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vclsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vclsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
new file mode 100644
index 000000000..a4e2d70c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vclsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vclsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
new file mode 100644
index 000000000..91394e198
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclsQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vclsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vclsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c
new file mode 100644
index 000000000..c98508412
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss16.c
@@ -0,0 +1,20 @@
+/* Test the `vclss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vcls_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c
new file mode 100644
index 000000000..4f3e16f88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss32.c
@@ -0,0 +1,20 @@
+/* Test the `vclss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vcls_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c
new file mode 100644
index 000000000..3c363745f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclss8.c
@@ -0,0 +1,20 @@
+/* Test the `vclss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vcls_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcls\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
new file mode 100644
index 000000000..1616849a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcltQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQf32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_uint32x4_t = vcltq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
new file mode 100644
index 000000000..794d2c4b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vcltQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vcltq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
new file mode 100644
index 000000000..871519b14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vcltQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vcltq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
new file mode 100644
index 000000000..41d32111f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vcltQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vcltq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
new file mode 100644
index 000000000..209bc3d0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vcltQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vcltq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
new file mode 100644
index 000000000..797c62a81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vcltQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vcltq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
new file mode 100644
index 000000000..5a067fedf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vcltQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vcltq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
new file mode 100644
index 000000000..82ef84fb6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltf32.c
@@ -0,0 +1,21 @@
+/* Test the `vcltf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltf32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_uint32x2_t = vclt_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c
new file mode 100644
index 000000000..b6aaeabb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts16.c
@@ -0,0 +1,21 @@
+/* Test the `vclts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c
new file mode 100644
index 000000000..cb66ca98e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts32.c
@@ -0,0 +1,21 @@
+/* Test the `vclts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vclt_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c
new file mode 100644
index 000000000..60bbf636c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclts8.c
@@ -0,0 +1,21 @@
+/* Test the `vclts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vclt_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
new file mode 100644
index 000000000..e5d2918cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu16.c
@@ -0,0 +1,21 @@
+/* Test the `vcltu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vclt_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
new file mode 100644
index 000000000..936e6b867
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu32.c
@@ -0,0 +1,21 @@
+/* Test the `vcltu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vclt_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
new file mode 100644
index 000000000..ab73e1f18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcltu8.c
@@ -0,0 +1,21 @@
+/* Test the `vcltu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcltu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vclt_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcgt\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
new file mode 100644
index 000000000..24df7b676
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vclzQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vclzq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
new file mode 100644
index 000000000..1e01ee9e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vclzQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vclzq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
new file mode 100644
index 000000000..80e40fd86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vclzQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vclzq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
new file mode 100644
index 000000000..2b023fa24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vclzQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vclzq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
new file mode 100644
index 000000000..529cbcf58
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vclzQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vclzq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
new file mode 100644
index 000000000..2be4915ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vclzQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vclzq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
new file mode 100644
index 000000000..b024559f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs16.c
@@ -0,0 +1,20 @@
+/* Test the `vclzs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vclz_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
new file mode 100644
index 000000000..b01e429c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs32.c
@@ -0,0 +1,20 @@
+/* Test the `vclzs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vclz_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
new file mode 100644
index 000000000..b23be0c1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzs8.c
@@ -0,0 +1,20 @@
+/* Test the `vclzs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vclz_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
new file mode 100644
index 000000000..4f2516326
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu16.c
@@ -0,0 +1,20 @@
+/* Test the `vclzu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vclz_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
new file mode 100644
index 000000000..4dd898345
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu32.c
@@ -0,0 +1,20 @@
+/* Test the `vclzu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vclz_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
new file mode 100644
index 000000000..4bfe49878
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vclzu8.c
@@ -0,0 +1,20 @@
+/* Test the `vclzu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vclzu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vclz_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vclz\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
new file mode 100644
index 000000000..15a4f7154
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vcntQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vcntq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
new file mode 100644
index 000000000..fb6511903
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vcntQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vcntq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
new file mode 100644
index 000000000..dea80786b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcntQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vcntq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
new file mode 100644
index 000000000..39e0d1100
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntp8.c
@@ -0,0 +1,20 @@
+/* Test the `vcntp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vcnt_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
new file mode 100644
index 000000000..89ae7b7b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcnts8.c
@@ -0,0 +1,20 @@
+/* Test the `vcnts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcnts8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vcnt_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
new file mode 100644
index 000000000..9a5f2f045
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcntu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcntu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcntu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vcnt_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vcnt\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
new file mode 100644
index 000000000..a177288dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinef32.c
@@ -0,0 +1,20 @@
+/* Test the `vcombinef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombinef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x4_t = vcombine_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
new file mode 100644
index 000000000..79b4440b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep16.c
@@ -0,0 +1,20 @@
+/* Test the `vcombinep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombinep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x8_t = vcombine_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
new file mode 100644
index 000000000..d5e156bdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep64.c
@@ -0,0 +1,20 @@
+/* Test the `vcombinep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vcombinep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x2_t = vcombine_p64 (arg0_poly64x1_t, arg1_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
new file mode 100644
index 000000000..0fa1af6df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombinep8.c
@@ -0,0 +1,20 @@
+/* Test the `vcombinep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombinep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x16_t = vcombine_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
new file mode 100644
index 000000000..9799f99b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines16.c
@@ -0,0 +1,20 @@
+/* Test the `vcombines16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombines16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vcombine_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
new file mode 100644
index 000000000..d68676c3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines32.c
@@ -0,0 +1,20 @@
+/* Test the `vcombines32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombines32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vcombine_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
new file mode 100644
index 000000000..389941540
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines64.c
@@ -0,0 +1,20 @@
+/* Test the `vcombines64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombines64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x2_t = vcombine_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
new file mode 100644
index 000000000..b3c8d3a7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombines8.c
@@ -0,0 +1,20 @@
+/* Test the `vcombines8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombines8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x16_t = vcombine_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
new file mode 100644
index 000000000..f35528b6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu16.c
@@ -0,0 +1,20 @@
+/* Test the `vcombineu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombineu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x8_t = vcombine_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
new file mode 100644
index 000000000..9c10e8597
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu32.c
@@ -0,0 +1,20 @@
+/* Test the `vcombineu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombineu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x4_t = vcombine_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
new file mode 100644
index 000000000..fac517b48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu64.c
@@ -0,0 +1,20 @@
+/* Test the `vcombineu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombineu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x2_t = vcombine_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
new file mode 100644
index 000000000..808a9f299
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcombineu8.c
@@ -0,0 +1,20 @@
+/* Test the `vcombineu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcombineu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x16_t = vcombine_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
new file mode 100644
index 000000000..68fe67e50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatef32.c
@@ -0,0 +1,19 @@
+/* Test the `vcreatef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreatef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_float32x2_t = vcreate_f32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
new file mode 100644
index 000000000..b02247259
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep16.c
@@ -0,0 +1,19 @@
+/* Test the `vcreatep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreatep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly16x4_t = vcreate_p16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
new file mode 100644
index 000000000..7aedb73fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep64.c
@@ -0,0 +1,19 @@
+/* Test the `vcreatep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vcreatep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly64x1_t = vcreate_p64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
new file mode 100644
index 000000000..7a3f607dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreatep8.c
@@ -0,0 +1,19 @@
+/* Test the `vcreatep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreatep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_poly8x8_t = vcreate_p8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
new file mode 100644
index 000000000..2adfeb31e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates16.c
@@ -0,0 +1,19 @@
+/* Test the `vcreates16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreates16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_int16x4_t = vcreate_s16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
new file mode 100644
index 000000000..4212dcba5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates32.c
@@ -0,0 +1,19 @@
+/* Test the `vcreates32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreates32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_int32x2_t = vcreate_s32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
new file mode 100644
index 000000000..77e4a51b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates64.c
@@ -0,0 +1,19 @@
+/* Test the `vcreates64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreates64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_int64x1_t = vcreate_s64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
new file mode 100644
index 000000000..0c0d546aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreates8.c
@@ -0,0 +1,19 @@
+/* Test the `vcreates8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreates8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_int8x8_t = vcreate_s8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
new file mode 100644
index 000000000..d8004802b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu16.c
@@ -0,0 +1,19 @@
+/* Test the `vcreateu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreateu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint16x4_t = vcreate_u16 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
new file mode 100644
index 000000000..42d72adc3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu32.c
@@ -0,0 +1,19 @@
+/* Test the `vcreateu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreateu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint32x2_t = vcreate_u32 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
new file mode 100644
index 000000000..5b0b37865
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu64.c
@@ -0,0 +1,19 @@
+/* Test the `vcreateu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreateu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vcreate_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
new file mode 100644
index 000000000..ea4114617
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcreateu8.c
@@ -0,0 +1,19 @@
+/* Test the `vcreateu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcreateu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint8x8_t = vcreate_u8 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
new file mode 100644
index 000000000..85916e770
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_s32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtQ_nf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vcvtq_n_f32_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
new file mode 100644
index 000000000..ab20ff0ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nf32_u32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtQ_nf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vcvtq_n_f32_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
new file mode 100644
index 000000000..76ce86a0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_ns32_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtQ_ns32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_ns32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vcvtq_n_s32_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
new file mode 100644
index 000000000..16de37fe1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQ_nu32_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtQ_nu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQ_nu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vcvtq_n_u32_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
new file mode 100644
index 000000000..1160edeab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_s32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtQf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vcvtq_f32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
new file mode 100644
index 000000000..285e1dd89
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQf32_u32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtQf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vcvtq_f32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
new file mode 100644
index 000000000..562137430
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQs32_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtQs32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQs32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vcvtq_s32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
new file mode 100644
index 000000000..f2ea8f541
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtQu32_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtQu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtQu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vcvtq_u32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
new file mode 100644
index 000000000..403fe621c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_s32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvt_nf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vcvt_n_f32_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
new file mode 100644
index 000000000..dc344a3ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nf32_u32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvt_nf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vcvt_n_f32_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
new file mode 100644
index 000000000..b50b20e01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_ns32_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvt_ns32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvt_ns32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vcvt_n_s32_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
new file mode 100644
index 000000000..b003f0097
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvt_nu32_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvt_nu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvt_nu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vcvt_n_u32_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c
new file mode 100644
index 000000000..6675596d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf16_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtf16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+void test_vcvtf16_f32 (void)
+{
+  float16x4_t out_float16x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float16x4_t = vcvt_f16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f16.f32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c
new file mode 100644
index 000000000..dd0ce1702
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_f16.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtf32_f16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_f16 (void)
+{
+  float32x4_t out_float32x4_t;
+  float16x4_t arg0_float16x4_t;
+
+  out_float32x4_t = vcvt_f32_f16 (arg0_float16x4_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.f16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
new file mode 100644
index 000000000..e0ca9b062
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_s32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vcvt_f32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
new file mode 100644
index 000000000..b3b44bedf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtf32_u32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vcvt_f32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.f32.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
new file mode 100644
index 000000000..b626fbf74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvts32_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvts32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvts32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vcvt_s32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.s32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
new file mode 100644
index 000000000..8c86d47af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vcvtu32_f32.c
@@ -0,0 +1,20 @@
+/* Test the `vcvtu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vcvtu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vcvt_u32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vcvt\.u32.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
new file mode 100644
index 000000000..8593d871a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
new file mode 100644
index 000000000..b48966b76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
new file mode 100644
index 000000000..6211413c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly64x2_t = vdupq_lane_p64 (arg0_poly64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
new file mode 100644
index 000000000..ebe7a0da5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
new file mode 100644
index 000000000..dae7cb568
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
new file mode 100644
index 000000000..4ef5cb789
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
new file mode 100644
index 000000000..9c41050e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x2_t = vdupq_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
new file mode 100644
index 000000000..428dfc404
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
new file mode 100644
index 000000000..840e6e2b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
new file mode 100644
index 000000000..76f3c756f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
new file mode 100644
index 000000000..8a6487135
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x2_t = vdupq_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
new file mode 100644
index 000000000..c4886e62d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
new file mode 100644
index 000000000..5f7305aca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+
+  out_float32x4_t = vdupq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
new file mode 100644
index 000000000..bd73329cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
new file mode 100644
index 000000000..68a1d746b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64_t arg0_poly64_t;
+
+  out_poly64x2_t = vdupq_n_p64 (arg0_poly64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
new file mode 100644
index 000000000..7c90d560d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
new file mode 100644
index 000000000..de837d919
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+
+  out_int16x8_t = vdupq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
new file mode 100644
index 000000000..00f175cec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+
+  out_int32x4_t = vdupq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
new file mode 100644
index 000000000..ab749a7bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+
+  out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
new file mode 100644
index 000000000..3794d6eb1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+
+  out_int8x16_t = vdupq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
new file mode 100644
index 000000000..fed6ea227
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
new file mode 100644
index 000000000..5b96fbcdd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
new file mode 100644
index 000000000..0ddb72dec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vdupQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
new file mode 100644
index 000000000..a490472fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdupQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vdupQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdupQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
new file mode 100644
index 000000000..495f189bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
new file mode 100644
index 000000000..f951fac35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
new file mode 100644
index 000000000..ab263f170
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly64x1_t = vdup_lane_p64 (arg0_poly64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
new file mode 100644
index 000000000..dad99e4fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
new file mode 100644
index 000000000..046d440ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
new file mode 100644
index 000000000..f249a626a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
new file mode 100644
index 000000000..628140fd3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vdup_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
new file mode 100644
index 000000000..9ca250152
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
new file mode 100644
index 000000000..1b3dd02a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
new file mode 100644
index 000000000..520757873
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
new file mode 100644
index 000000000..a9de614c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vdup_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
new file mode 100644
index 000000000..5687c0b47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
new file mode 100644
index 000000000..ba99fdce5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+
+  out_float32x2_t = vdup_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
new file mode 100644
index 000000000..55bca29b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x4_t = vdup_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
new file mode 100644
index 000000000..3b6b7ec31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vdup_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64_t arg0_poly64_t;
+
+  out_poly64x1_t = vdup_n_p64 (arg0_poly64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
new file mode 100644
index 000000000..80d29e860
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x8_t = vdup_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
new file mode 100644
index 000000000..4d1ea6a6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+
+  out_int16x4_t = vdup_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
new file mode 100644
index 000000000..9fb1fc289
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+
+  out_int32x2_t = vdup_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
new file mode 100644
index 000000000..033f1b474
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+
+  out_int64x1_t = vdup_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
new file mode 100644
index 000000000..eba462c79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+
+  out_int8x8_t = vdup_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
new file mode 100644
index 000000000..24015e592
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x4_t = vdup_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
new file mode 100644
index 000000000..78374d42a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x2_t = vdup_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
new file mode 100644
index 000000000..6888125c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vdup_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
new file mode 100644
index 000000000..ee35ff37b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vdup_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vdup_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vdup_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x8_t = vdup_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c
new file mode 100644
index 000000000..f31d9bfab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */
+/* { dg-add-options arm_neon } */
+
+#define N 32
+
+int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+float fa[N];
+int ia[N];
+
+int convert()
+{
+  int i;
+
+  /* int -> float */
+  for (i = 0; i < N; i++)
+    fa[i] = (float) ib[i];
+
+  /* float -> int */
+  for (i = 0; i < N; i++)
+    ia[i] = (int) fa[i];
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c
new file mode 100644
index 000000000..f3f01c65e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
+/* { dg-add-options arm_neon } */
+
+#define N 32
+
+int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+float fa[N];
+int ia[N];
+
+int convert()
+{
+  int i;
+
+  /* int -> float */
+  for (i = 0; i < N; i++)
+    fa[i] = (float) ib[i];
+
+  /* float -> int */
+  for (i = 0; i < N; i++)
+    ia[i] = (int) fa[i];
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
new file mode 100644
index 000000000..a0428bee7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
@@ -0,0 +1,21 @@
+/* Test the `veorQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = veorq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
new file mode 100644
index 000000000..7b24ea477
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs32.c
@@ -0,0 +1,21 @@
+/* Test the `veorQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = veorq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
new file mode 100644
index 000000000..fd023171a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs64.c
@@ -0,0 +1,21 @@
+/* Test the `veorQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = veorq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
new file mode 100644
index 000000000..17da85c6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQs8.c
@@ -0,0 +1,21 @@
+/* Test the `veorQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = veorq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
new file mode 100644
index 000000000..d2865e9fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu16.c
@@ -0,0 +1,21 @@
+/* Test the `veorQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = veorq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
new file mode 100644
index 000000000..76370677d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu32.c
@@ -0,0 +1,21 @@
+/* Test the `veorQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = veorq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
new file mode 100644
index 000000000..156b07b34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu64.c
@@ -0,0 +1,21 @@
+/* Test the `veorQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = veorq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
new file mode 100644
index 000000000..b3ff98343
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veorQu8.c
@@ -0,0 +1,21 @@
+/* Test the `veorQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veorQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = veorq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c
new file mode 100644
index 000000000..8af437edf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors16.c
@@ -0,0 +1,21 @@
+/* Test the `veors16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veors16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = veor_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c
new file mode 100644
index 000000000..105780393
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors32.c
@@ -0,0 +1,21 @@
+/* Test the `veors32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veors32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = veor_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c
new file mode 100644
index 000000000..2781be1b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors64.c
@@ -0,0 +1,20 @@
+/* Test the `veors64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veors64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = veor_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c
new file mode 100644
index 000000000..cda05c7e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veors8.c
@@ -0,0 +1,21 @@
+/* Test the `veors8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veors8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = veor_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c
new file mode 100644
index 000000000..d89d87302
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru16.c
@@ -0,0 +1,21 @@
+/* Test the `veoru16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veoru16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = veor_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c
new file mode 100644
index 000000000..7804a8c16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru32.c
@@ -0,0 +1,21 @@
+/* Test the `veoru32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veoru32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = veor_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c
new file mode 100644
index 000000000..19d081489
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru64.c
@@ -0,0 +1,20 @@
+/* Test the `veoru64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veoru64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = veor_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c
new file mode 100644
index 000000000..aad32de44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/veoru8.c
@@ -0,0 +1,21 @@
+/* Test the `veoru8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_veoru8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = veor_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "veor\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
new file mode 100644
index 000000000..92597f9bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vextQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vextq_f32 (arg0_float32x4_t, arg1_float32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
new file mode 100644
index 000000000..546da6990
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp16.c
@@ -0,0 +1,21 @@
+/* Test the `vextQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vextq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
new file mode 100644
index 000000000..bc5e08aa7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp64.c
@@ -0,0 +1,21 @@
+/* Test the `vextQp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vextQp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vextq_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
new file mode 100644
index 000000000..f9273c2d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vextQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vextq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
new file mode 100644
index 000000000..d95ff2976
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vextQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vextq_s16 (arg0_int16x8_t, arg1_int16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
new file mode 100644
index 000000000..b6824ff6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vextQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vextq_s32 (arg0_int32x4_t, arg1_int32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
new file mode 100644
index 000000000..226aa207f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vextQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vextq_s64 (arg0_int64x2_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
new file mode 100644
index 000000000..274279a2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vextQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vextq_s8 (arg0_int8x16_t, arg1_int8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
new file mode 100644
index 000000000..36fcb5273
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vextQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vextq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
new file mode 100644
index 000000000..082592a0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vextQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vextq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
new file mode 100644
index 000000000..ac496db0d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vextQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vextq_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
new file mode 100644
index 000000000..e77b9a2e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vextQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vextq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c
new file mode 100644
index 000000000..5f7ef947c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextf32.c
@@ -0,0 +1,21 @@
+/* Test the `vextf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vext_f32 (arg0_float32x2_t, arg1_float32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c
new file mode 100644
index 000000000..f1e176efb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp16.c
@@ -0,0 +1,21 @@
+/* Test the `vextp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vext_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c
new file mode 100644
index 000000000..aa1e91f59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp64.c
@@ -0,0 +1,21 @@
+/* Test the `vextp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vextp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vext_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c
new file mode 100644
index 000000000..feb2fdd07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextp8.c
@@ -0,0 +1,21 @@
+/* Test the `vextp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vext_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c
new file mode 100644
index 000000000..1d3eb7980
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts16.c
@@ -0,0 +1,21 @@
+/* Test the `vexts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vexts16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vext_s16 (arg0_int16x4_t, arg1_int16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c
new file mode 100644
index 000000000..e83a0de6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts32.c
@@ -0,0 +1,21 @@
+/* Test the `vexts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vexts32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vext_s32 (arg0_int32x2_t, arg1_int32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c
new file mode 100644
index 000000000..e594beca5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts64.c
@@ -0,0 +1,21 @@
+/* Test the `vexts64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vexts64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vext_s64 (arg0_int64x1_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c
new file mode 100644
index 000000000..0575bd349
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vexts8.c
@@ -0,0 +1,21 @@
+/* Test the `vexts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vexts8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vext_s8 (arg0_int8x8_t, arg1_int8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c
new file mode 100644
index 000000000..b94afdf61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu16.c
@@ -0,0 +1,21 @@
+/* Test the `vextu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vext_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c
new file mode 100644
index 000000000..39bdf31ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu32.c
@@ -0,0 +1,21 @@
+/* Test the `vextu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vext_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c
new file mode 100644
index 000000000..17afbd751
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu64.c
@@ -0,0 +1,21 @@
+/* Test the `vextu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vext_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c
new file mode 100644
index 000000000..5176a7201
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vextu8.c
@@ -0,0 +1,21 @@
+/* Test the `vextu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vextu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vext_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 0);
+}
+
+/* { dg-final { scan-assembler "vext\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c
new file mode 100644
index 000000000..d400163a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c
@@ -0,0 +1,22 @@
+/* Test the `vfmaQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmaQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vfmaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vfma\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c
new file mode 100644
index 000000000..988328dd0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c
@@ -0,0 +1,22 @@
+/* Test the `vfmaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmaf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vfma_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vfma\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c
new file mode 100644
index 000000000..247a8edfd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c
@@ -0,0 +1,22 @@
+/* Test the `vfmsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vfmsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vfms\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c
new file mode 100644
index 000000000..7f9e8570d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c
@@ -0,0 +1,22 @@
+/* Test the `vfmsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vfms_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vfms\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
new file mode 100644
index 000000000..5c772c04c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
@@ -0,0 +1,28 @@
+/* Check that NEON vector shifts support immediate values == size.  /*
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t test_vshll_n_u8 (uint8x8_t a)
+{
+    return vshll_n_u8(a, 8);
+}
+
+uint32x4_t test_vshll_n_u16 (uint16x4_t a)
+{   
+    return vshll_n_u16(a, 16);
+}
+
+uint64x2_t test_vshll_n_u32 (uint32x2_t a)
+{
+    return vshll_n_u32(a, 32);
+}
+
+/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
new file mode 100644
index 000000000..54e04c50a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanef32 (void)
+{
+  float32_t out_float32_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
new file mode 100644
index 000000000..cfb5447bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanep16 (void)
+{
+  poly16_t out_poly16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
new file mode 100644
index 000000000..7325dd744
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanep8 (void)
+{
+  poly8_t out_poly8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
new file mode 100644
index 000000000..f992d17a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes16 (void)
+{
+  int16_t out_int16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
new file mode 100644
index 000000000..36cb88ff4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes32 (void)
+{
+  int32_t out_int32_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
new file mode 100644
index 000000000..e3d3c178e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes64 (void)
+{
+  register int64_t out_int64_t asm ("r0");
+  int64x2_t arg0_int64x2_t;
+
+  out_int64_t = vgetq_lane_s64 (arg0_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
new file mode 100644
index 000000000..7ce2cc651
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_lanes8 (void)
+{
+  int8_t out_int8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
new file mode 100644
index 000000000..d44f05f2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu16 (void)
+{
+  uint16_t out_uint16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
new file mode 100644
index 000000000..3004f503c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu32 (void)
+{
+  uint32_t out_uint32_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
new file mode 100644
index 000000000..3426e4694
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu64 (void)
+{
+  register uint64_t out_uint64_t asm ("r0");
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64_t = vgetq_lane_u64 (arg0_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "((vmov)|(fmrrd))\[ 	\]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
new file mode 100644
index 000000000..57528f2f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vgetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vgetQ_laneu8 (void)
+{
+  uint8_t out_uint8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
new file mode 100644
index 000000000..60f935e97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highf32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x2_t = vget_high_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
new file mode 100644
index 000000000..660b83e34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x4_t = vget_high_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
new file mode 100644
index 000000000..f2b1b7a9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vget_highp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly64x1_t = vget_high_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
new file mode 100644
index 000000000..e9519606e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highp8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x8_t = vget_high_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
new file mode 100644
index 000000000..ca4e7706e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x4_t = vget_high_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
new file mode 100644
index 000000000..77ead1ac8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x2_t = vget_high_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
new file mode 100644
index 000000000..cb6a48480
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x1_t = vget_high_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
new file mode 100644
index 000000000..ec249f823
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highs8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x8_t = vget_high_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
new file mode 100644
index 000000000..263a920aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu16.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x4_t = vget_high_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
new file mode 100644
index 000000000..4797a132e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu32.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x2_t = vget_high_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
new file mode 100644
index 000000000..899309f1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x1_t = vget_high_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
new file mode 100644
index 000000000..a0c689736
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_highu8.c
@@ -0,0 +1,19 @@
+/* Test the `vget_highu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_highu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x8_t = vget_high_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
new file mode 100644
index 000000000..908adeb70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanef32 (void)
+{
+  float32_t out_float32_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
new file mode 100644
index 000000000..0dcf90b57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanep16 (void)
+{
+  poly16_t out_poly16_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
new file mode 100644
index 000000000..22b06bdf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanep8 (void)
+{
+  poly8_t out_poly8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
new file mode 100644
index 000000000..4a86bf465
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes16 (void)
+{
+  int16_t out_int16_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
new file mode 100644
index 000000000..8559da7ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes32 (void)
+{
+  int32_t out_int32_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
new file mode 100644
index 000000000..5dc99424f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes64 (void)
+{
+  int64_t out_int64_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
new file mode 100644
index 000000000..be6110408
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lanes8 (void)
+{
+  int8_t out_int8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
new file mode 100644
index 000000000..66f645e32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vget_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu16 (void)
+{
+  uint16_t out_uint16_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
new file mode 100644
index 000000000..b19de8d28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vget_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu32 (void)
+{
+  uint32_t out_uint32_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
new file mode 100644
index 000000000..496a057fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu64 (void)
+{
+  uint64_t out_uint64_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
new file mode 100644
index 000000000..1affae83a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vget_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_laneu8 (void)
+{
+  uint8_t out_uint8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
new file mode 100644
index 000000000..81982d438
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowf32.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lowf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowf32 (void)
+{
+  register float32x2_t out_float32x2_t asm ("d18");
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x2_t = vget_low_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
new file mode 100644
index 000000000..395461196
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp16.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lowp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp16 (void)
+{
+  register poly16x4_t out_poly16x4_t asm ("d18");
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x4_t = vget_low_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
new file mode 100644
index 000000000..94cd3a8ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly64x1_t = vget_low_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
new file mode 100644
index 000000000..e4bf2f1d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowp8.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lowp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowp8 (void)
+{
+  register poly8x8_t out_poly8x8_t asm ("d18");
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x8_t = vget_low_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
new file mode 100644
index 000000000..d2a07c63e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows16.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lows16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lows16 (void)
+{
+  register int16x4_t out_int16x4_t asm ("d18");
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x4_t = vget_low_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
new file mode 100644
index 000000000..4278e2bcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows32.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lows32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lows32 (void)
+{
+  register int32x2_t out_int32x2_t asm ("d18");
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x2_t = vget_low_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
new file mode 100644
index 000000000..53d26e7e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lows64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lows64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x1_t = vget_low_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
new file mode 100644
index 000000000..a4ad63371
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lows8.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lows8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lows8 (void)
+{
+  register int8x8_t out_int8x8_t asm ("d18");
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x8_t = vget_low_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
new file mode 100644
index 000000000..c9e0a51a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu16.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lowu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu16 (void)
+{
+  register uint16x4_t out_uint16x4_t asm ("d18");
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x4_t = vget_low_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
new file mode 100644
index 000000000..841a619cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu32.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lowu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu32 (void)
+{
+  register uint32x2_t out_uint32x2_t asm ("d18");
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x2_t = vget_low_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
new file mode 100644
index 000000000..ab2b42c2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu64.c
@@ -0,0 +1,19 @@
+/* Test the `vget_lowu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x1_t = vget_low_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
new file mode 100644
index 000000000..fd2537bbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vget_lowu8.c
@@ -0,0 +1,20 @@
+/* Test the `vget_lowu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vget_lowu8 (void)
+{
+  register uint8x8_t out_uint8x8_t asm ("d18");
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x8_t = vget_low_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
new file mode 100644
index 000000000..2bd30cd1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vhaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
new file mode 100644
index 000000000..04bbf03bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vhaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
new file mode 100644
index 000000000..86c3db518
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vhaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
new file mode 100644
index 000000000..75aae10e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vhaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
new file mode 100644
index 000000000..c7ec45a2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vhaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
new file mode 100644
index 000000000..8668d141b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vhaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
new file mode 100644
index 000000000..61344cff5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds16.c
@@ -0,0 +1,21 @@
+/* Test the `vhadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vhadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
new file mode 100644
index 000000000..03d090292
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds32.c
@@ -0,0 +1,21 @@
+/* Test the `vhadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vhadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
new file mode 100644
index 000000000..90e79daa7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhadds8.c
@@ -0,0 +1,21 @@
+/* Test the `vhadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vhadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
new file mode 100644
index 000000000..971778b78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu16.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vhadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
new file mode 100644
index 000000000..70865fad0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu32.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vhadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
new file mode 100644
index 000000000..b541b87d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhaddu8.c
@@ -0,0 +1,21 @@
+/* Test the `vhaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vhadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
new file mode 100644
index 000000000..5647c6297
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vhsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
new file mode 100644
index 000000000..44e780e01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vhsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
new file mode 100644
index 000000000..8162a1014
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vhsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
new file mode 100644
index 000000000..1a84876ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vhsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
new file mode 100644
index 000000000..ae52afd29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vhsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
new file mode 100644
index 000000000..ef43a4f3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vhsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
new file mode 100644
index 000000000..786c8d389
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs16.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vhsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
new file mode 100644
index 000000000..4c7e9c8b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs32.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vhsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
new file mode 100644
index 000000000..c8c1ada08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubs8.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vhsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
new file mode 100644
index 000000000..bf83c7ce0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu16.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vhsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
new file mode 100644
index 000000000..f224eaf07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu32.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vhsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
new file mode 100644
index 000000000..fe145a9b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vhsubu8.c
@@ -0,0 +1,21 @@
+/* Test the `vhsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vhsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vhsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vhsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
new file mode 100644
index 000000000..fa9cf20f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupf32 (void)
+{
+  float32x4_t out_float32x4_t;
+
+  out_float32x4_t = vld1q_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
new file mode 100644
index 000000000..4e8303825
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+
+  out_poly16x8_t = vld1q_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
new file mode 100644
index 000000000..2d504c163
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+
+  out_poly64x2_t = vld1q_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
new file mode 100644
index 000000000..70fb89885
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+
+  out_poly8x16_t = vld1q_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
new file mode 100644
index 000000000..1fedcf94d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups16 (void)
+{
+  int16x8_t out_int16x8_t;
+
+  out_int16x8_t = vld1q_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
new file mode 100644
index 000000000..2abd4e447
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups32 (void)
+{
+  int32x4_t out_int32x4_t;
+
+  out_int32x4_t = vld1q_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
new file mode 100644
index 000000000..4fceee82e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups64 (void)
+{
+  int64x2_t out_int64x2_t;
+
+  out_int64x2_t = vld1q_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
new file mode 100644
index 000000000..e431a5cf1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dups8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dups8 (void)
+{
+  int8x16_t out_int8x16_t;
+
+  out_int8x16_t = vld1q_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
new file mode 100644
index 000000000..6da756774
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+
+  out_uint16x8_t = vld1q_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
new file mode 100644
index 000000000..8e400bd25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+
+  out_uint32x4_t = vld1q_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
new file mode 100644
index 000000000..ef0a3828c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+
+  out_uint64x2_t = vld1q_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
new file mode 100644
index 000000000..b1e540d70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_dupu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Q_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_dupu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+
+  out_uint8x16_t = vld1q_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
new file mode 100644
index 000000000..8c7689edb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
new file mode 100644
index 000000000..163c2a7a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
new file mode 100644
index 000000000..d19267a4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vld1q_lane_p64 (0, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
new file mode 100644
index 000000000..7f7a22eba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
new file mode 100644
index 000000000..0d56492c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
new file mode 100644
index 000000000..3c5869fcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
new file mode 100644
index 000000000..154583b67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vld1q_lane_s64 (0, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
new file mode 100644
index 000000000..a6aa3f804
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
new file mode 100644
index 000000000..1653dd31c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
new file mode 100644
index 000000000..034e24d52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
new file mode 100644
index 000000000..ff92e91fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vld1q_lane_u64 (0, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
new file mode 100644
index 000000000..be338f187
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vld1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Q_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
new file mode 100644
index 000000000..d792148d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+
+  out_float32x4_t = vld1q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
new file mode 100644
index 000000000..84bceb557
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+
+  out_poly16x8_t = vld1q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
new file mode 100644
index 000000000..99ef87673
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+
+  out_poly64x2_t = vld1q_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
new file mode 100644
index 000000000..e756b1bc7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+
+  out_poly8x16_t = vld1q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
new file mode 100644
index 000000000..aaa29e982
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+
+  out_int16x8_t = vld1q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
new file mode 100644
index 000000000..14bc4221e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+
+  out_int32x4_t = vld1q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
new file mode 100644
index 000000000..093aee61a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs64 (void)
+{
+  int64x2_t out_int64x2_t;
+
+  out_int64x2_t = vld1q_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
new file mode 100644
index 000000000..d4fffd0a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qs8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+
+  out_int8x16_t = vld1q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
new file mode 100644
index 000000000..267f7d15b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+
+  out_uint16x8_t = vld1q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
new file mode 100644
index 000000000..53ccab0c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+
+  out_uint32x4_t = vld1q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
new file mode 100644
index 000000000..56b0dbd3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+
+  out_uint64x2_t = vld1q_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
new file mode 100644
index 000000000..d68fc89ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1Qu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+
+  out_uint8x16_t = vld1q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
new file mode 100644
index 000000000..6f8435b36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupf32 (void)
+{
+  float32x2_t out_float32x2_t;
+
+  out_float32x2_t = vld1_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
new file mode 100644
index 000000000..1287b471b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+
+  out_poly16x4_t = vld1_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
new file mode 100644
index 000000000..f2b05c5d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+
+  out_poly64x1_t = vld1_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
new file mode 100644
index 000000000..8fde64553
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+
+  out_poly8x8_t = vld1_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
new file mode 100644
index 000000000..084f89e06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups16 (void)
+{
+  int16x4_t out_int16x4_t;
+
+  out_int16x4_t = vld1_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
new file mode 100644
index 000000000..ba6697a4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups32 (void)
+{
+  int32x2_t out_int32x2_t;
+
+  out_int32x2_t = vld1_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
new file mode 100644
index 000000000..410ee6fcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups64 (void)
+{
+  int64x1_t out_int64x1_t;
+
+  out_int64x1_t = vld1_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
new file mode 100644
index 000000000..18b21b527
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dups8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dups8 (void)
+{
+  int8x8_t out_int8x8_t;
+
+  out_int8x8_t = vld1_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
new file mode 100644
index 000000000..1d893cd3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+
+  out_uint16x4_t = vld1_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
new file mode 100644
index 000000000..f64084640
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+
+  out_uint32x2_t = vld1_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
new file mode 100644
index 000000000..17be90a0b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+
+  out_uint64x1_t = vld1_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
new file mode 100644
index 000000000..5811f25fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_dupu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_dupu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+
+  out_uint8x8_t = vld1_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\\\]\\\})|(\[dD\]\[0-9\]+\\\[\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
new file mode 100644
index 000000000..6165897ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
new file mode 100644
index 000000000..feecf1baa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
new file mode 100644
index 000000000..cf09f6cd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vld1_lane_p64 (0, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
new file mode 100644
index 000000000..0d1729936
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
new file mode 100644
index 000000000..26272410e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
new file mode 100644
index 000000000..39575d456
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
new file mode 100644
index 000000000..1216405bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vld1_lane_s64 (0, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
new file mode 100644
index 000000000..7c763fd90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
new file mode 100644
index 000000000..9d2c45ed9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
new file mode 100644
index 000000000..3a7f3eec9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
new file mode 100644
index 000000000..b9e5d2042
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vld1_lane_u64 (0, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
new file mode 100644
index 000000000..7e4835afe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vld1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
new file mode 100644
index 000000000..2d90ac559
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1f32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1f32 (void)
+{
+  float32x2_t out_float32x2_t;
+
+  out_float32x2_t = vld1_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
new file mode 100644
index 000000000..62aa89e8a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+
+  out_poly16x4_t = vld1_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
new file mode 100644
index 000000000..9f182d441
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld1p64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+
+  out_poly64x1_t = vld1_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
new file mode 100644
index 000000000..60e47c2d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1p8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+
+  out_poly8x8_t = vld1_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
new file mode 100644
index 000000000..1d4cf525f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1s16 (void)
+{
+  int16x4_t out_int16x4_t;
+
+  out_int16x4_t = vld1_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
new file mode 100644
index 000000000..7af67c383
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1s32 (void)
+{
+  int32x2_t out_int32x2_t;
+
+  out_int32x2_t = vld1_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
new file mode 100644
index 000000000..dadb9de22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1s64 (void)
+{
+  int64x1_t out_int64x1_t;
+
+  out_int64x1_t = vld1_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
new file mode 100644
index 000000000..c27ebcd06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1s8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+
+  out_int8x8_t = vld1_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
new file mode 100644
index 000000000..f973d6ec5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u16.c
@@ -0,0 +1,19 @@
+/* Test the `vld1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+
+  out_uint16x4_t = vld1_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
new file mode 100644
index 000000000..4b455b292
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u32.c
@@ -0,0 +1,19 @@
+/* Test the `vld1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+
+  out_uint32x2_t = vld1_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
new file mode 100644
index 000000000..1504215d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u64.c
@@ -0,0 +1,19 @@
+/* Test the `vld1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1u64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+
+  out_uint64x1_t = vld1_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
new file mode 100644
index 000000000..600d03518
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld1u8.c
@@ -0,0 +1,19 @@
+/* Test the `vld1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+
+  out_uint8x8_t = vld1_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
new file mode 100644
index 000000000..9afbbecf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanef32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
new file mode 100644
index 000000000..e1b85aad9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanep16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
new file mode 100644
index 000000000..467c02b64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
new file mode 100644
index 000000000..5f9c4a8b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_lanes32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
new file mode 100644
index 000000000..851572917
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
new file mode 100644
index 000000000..65ec23a6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Q_laneu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
new file mode 100644
index 000000000..afde42c20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+
+  out_float32x4x2_t = vld2q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
new file mode 100644
index 000000000..f74004628
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+
+  out_poly16x8x2_t = vld2q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
new file mode 100644
index 000000000..9e4ff25f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+
+  out_poly8x16x2_t = vld2q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
new file mode 100644
index 000000000..97c8a2c5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+
+  out_int16x8x2_t = vld2q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
new file mode 100644
index 000000000..cd03e17d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+
+  out_int32x4x2_t = vld2q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
new file mode 100644
index 000000000..b33a5a8f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+
+  out_int8x16x2_t = vld2q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
new file mode 100644
index 000000000..76169af56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+
+  out_uint16x8x2_t = vld2q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
new file mode 100644
index 000000000..347e164bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+
+  out_uint32x4x2_t = vld2q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
new file mode 100644
index 000000000..3b738a7ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vld2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2Qu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+
+  out_uint8x16x2_t = vld2q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
new file mode 100644
index 000000000..54fbd3da9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
new file mode 100644
index 000000000..b5ec4e227
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
new file mode 100644
index 000000000..0531a732d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp64 (void)
+{
+  poly64x1x2_t out_poly64x1x2_t;
+
+  out_poly64x1x2_t = vld2_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
new file mode 100644
index 000000000..2ad81b53a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
new file mode 100644
index 000000000..43b245d3d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
new file mode 100644
index 000000000..51e4fc8e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
new file mode 100644
index 000000000..644db84ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups64 (void)
+{
+  int64x1x2_t out_int64x1x2_t;
+
+  out_int64x1x2_t = vld2_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
new file mode 100644
index 000000000..015923392
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dups8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dups8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
new file mode 100644
index 000000000..85bbc4681
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
new file mode 100644
index 000000000..3549fde1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
new file mode 100644
index 000000000..a830f8310
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu64 (void)
+{
+  uint64x1x2_t out_uint64x1x2_t;
+
+  out_uint64x1x2_t = vld2_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
new file mode 100644
index 000000000..c3763c8f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_dupu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_dupu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
new file mode 100644
index 000000000..f60279efd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanef32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
new file mode 100644
index 000000000..0d7f415b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
new file mode 100644
index 000000000..8174e7bee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanep8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
new file mode 100644
index 000000000..5a1eb54bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
new file mode 100644
index 000000000..a663c52ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
new file mode 100644
index 000000000..073ba5417
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_lanes8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
new file mode 100644
index 000000000..7250b562e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
new file mode 100644
index 000000000..9a46c65d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
new file mode 100644
index 000000000..ba2007109
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vld2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2_laneu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
new file mode 100644
index 000000000..c790de941
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2f32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2f32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+
+  out_float32x2x2_t = vld2_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
new file mode 100644
index 000000000..4c4338cfc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2p16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+
+  out_poly16x4x2_t = vld2_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
new file mode 100644
index 000000000..0a39b37f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld2p64 (void)
+{
+  poly64x1x2_t out_poly64x1x2_t;
+
+  out_poly64x1x2_t = vld2_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
new file mode 100644
index 000000000..d319c22e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2p8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2p8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+
+  out_poly8x8x2_t = vld2_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
new file mode 100644
index 000000000..f725d79de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2s16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+
+  out_int16x4x2_t = vld2_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
new file mode 100644
index 000000000..3f417eeee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2s32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+
+  out_int32x2x2_t = vld2_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
new file mode 100644
index 000000000..b9900893f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2s64 (void)
+{
+  int64x1x2_t out_int64x1x2_t;
+
+  out_int64x1x2_t = vld2_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
new file mode 100644
index 000000000..1df9eee6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2s8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2s8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+
+  out_int8x8x2_t = vld2_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
new file mode 100644
index 000000000..7440e0c08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u16.c
@@ -0,0 +1,19 @@
+/* Test the `vld2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2u16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+
+  out_uint16x4x2_t = vld2_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
new file mode 100644
index 000000000..940fd7497
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u32.c
@@ -0,0 +1,19 @@
+/* Test the `vld2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2u32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+
+  out_uint32x2x2_t = vld2_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
new file mode 100644
index 000000000..35c046a0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u64.c
@@ -0,0 +1,19 @@
+/* Test the `vld2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2u64 (void)
+{
+  uint64x1x2_t out_uint64x1x2_t;
+
+  out_uint64x1x2_t = vld2_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
new file mode 100644
index 000000000..2231e26c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld2u8.c
@@ -0,0 +1,19 @@
+/* Test the `vld2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld2u8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+
+  out_uint8x8x2_t = vld2_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
new file mode 100644
index 000000000..6bdc1e14a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanef32 (void)
+{
+  float32x4x3_t out_float32x4x3_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
new file mode 100644
index 000000000..12b3be0ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanep16 (void)
+{
+  poly16x8x3_t out_poly16x8x3_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
new file mode 100644
index 000000000..8ed21e3d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes16 (void)
+{
+  int16x8x3_t out_int16x8x3_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
new file mode 100644
index 000000000..af0118da0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_lanes32 (void)
+{
+  int32x4x3_t out_int32x4x3_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
new file mode 100644
index 000000000..7880b98e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu16 (void)
+{
+  uint16x8x3_t out_uint16x8x3_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
new file mode 100644
index 000000000..0b1bce5c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Q_laneu32 (void)
+{
+  uint32x4x3_t out_uint32x4x3_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
new file mode 100644
index 000000000..6f16d9d87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qf32 (void)
+{
+  float32x4x3_t out_float32x4x3_t;
+
+  out_float32x4x3_t = vld3q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
new file mode 100644
index 000000000..ff4ef8653
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp16 (void)
+{
+  poly16x8x3_t out_poly16x8x3_t;
+
+  out_poly16x8x3_t = vld3q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
new file mode 100644
index 000000000..a23749378
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qp8 (void)
+{
+  poly8x16x3_t out_poly8x16x3_t;
+
+  out_poly8x16x3_t = vld3q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
new file mode 100644
index 000000000..cfa01367f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs16 (void)
+{
+  int16x8x3_t out_int16x8x3_t;
+
+  out_int16x8x3_t = vld3q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
new file mode 100644
index 000000000..e1721ef3d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs32 (void)
+{
+  int32x4x3_t out_int32x4x3_t;
+
+  out_int32x4x3_t = vld3q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
new file mode 100644
index 000000000..9f762ca6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qs8 (void)
+{
+  int8x16x3_t out_int8x16x3_t;
+
+  out_int8x16x3_t = vld3q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
new file mode 100644
index 000000000..a2308729f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu16 (void)
+{
+  uint16x8x3_t out_uint16x8x3_t;
+
+  out_uint16x8x3_t = vld3q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
new file mode 100644
index 000000000..21f20f880
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu32 (void)
+{
+  uint32x4x3_t out_uint32x4x3_t;
+
+  out_uint32x4x3_t = vld3q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
new file mode 100644
index 000000000..7cbcc4690
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vld3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3Qu8 (void)
+{
+  uint8x16x3_t out_uint8x16x3_t;
+
+  out_uint8x16x3_t = vld3q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
new file mode 100644
index 000000000..542336971
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupf32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
new file mode 100644
index 000000000..6c08c8343
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
new file mode 100644
index 000000000..23bf88aa6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp64 (void)
+{
+  poly64x1x3_t out_poly64x1x3_t;
+
+  out_poly64x1x3_t = vld3_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
new file mode 100644
index 000000000..fd4a6603f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupp8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
new file mode 100644
index 000000000..4c11e7ef8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
new file mode 100644
index 000000000..b500c24a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
new file mode 100644
index 000000000..cf11f5c1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups64 (void)
+{
+  int64x1x3_t out_int64x1x3_t;
+
+  out_int64x1x3_t = vld3_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
new file mode 100644
index 000000000..4f0c8300d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dups8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dups8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
new file mode 100644
index 000000000..57e3597bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
new file mode 100644
index 000000000..e4abde4f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
new file mode 100644
index 000000000..a91712623
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu64 (void)
+{
+  uint64x1x3_t out_uint64x1x3_t;
+
+  out_uint64x1x3_t = vld3_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
new file mode 100644
index 000000000..842618785
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_dupu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_dupu8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
new file mode 100644
index 000000000..ccbe45f00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanef32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
new file mode 100644
index 000000000..94b4ce421
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
new file mode 100644
index 000000000..12b0786bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanep8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
new file mode 100644
index 000000000..5ab744fc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
new file mode 100644
index 000000000..168f3f363
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
new file mode 100644
index 000000000..9d0d1a4b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_lanes8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
new file mode 100644
index 000000000..baf97a98a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
new file mode 100644
index 000000000..05d7107f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
new file mode 100644
index 000000000..af7556350
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vld3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3_laneu8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
new file mode 100644
index 000000000..120f834d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3f32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3f32 (void)
+{
+  float32x2x3_t out_float32x2x3_t;
+
+  out_float32x2x3_t = vld3_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
new file mode 100644
index 000000000..2c47f5e8e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3p16 (void)
+{
+  poly16x4x3_t out_poly16x4x3_t;
+
+  out_poly16x4x3_t = vld3_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
new file mode 100644
index 000000000..cc7992892
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld3p64 (void)
+{
+  poly64x1x3_t out_poly64x1x3_t;
+
+  out_poly64x1x3_t = vld3_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
new file mode 100644
index 000000000..77c2462e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3p8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3p8 (void)
+{
+  poly8x8x3_t out_poly8x8x3_t;
+
+  out_poly8x8x3_t = vld3_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
new file mode 100644
index 000000000..355ede8c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3s16 (void)
+{
+  int16x4x3_t out_int16x4x3_t;
+
+  out_int16x4x3_t = vld3_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
new file mode 100644
index 000000000..8d18a8843
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3s32 (void)
+{
+  int32x2x3_t out_int32x2x3_t;
+
+  out_int32x2x3_t = vld3_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
new file mode 100644
index 000000000..67bb3568f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3s64 (void)
+{
+  int64x1x3_t out_int64x1x3_t;
+
+  out_int64x1x3_t = vld3_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
new file mode 100644
index 000000000..1be5d11bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3s8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3s8 (void)
+{
+  int8x8x3_t out_int8x8x3_t;
+
+  out_int8x8x3_t = vld3_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
new file mode 100644
index 000000000..4db18f049
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u16.c
@@ -0,0 +1,19 @@
+/* Test the `vld3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3u16 (void)
+{
+  uint16x4x3_t out_uint16x4x3_t;
+
+  out_uint16x4x3_t = vld3_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
new file mode 100644
index 000000000..82c10ff16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u32.c
@@ -0,0 +1,19 @@
+/* Test the `vld3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3u32 (void)
+{
+  uint32x2x3_t out_uint32x2x3_t;
+
+  out_uint32x2x3_t = vld3_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
new file mode 100644
index 000000000..bca1df48f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u64.c
@@ -0,0 +1,19 @@
+/* Test the `vld3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3u64 (void)
+{
+  uint64x1x3_t out_uint64x1x3_t;
+
+  out_uint64x1x3_t = vld3_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
new file mode 100644
index 000000000..c8ac20af1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld3u8.c
@@ -0,0 +1,19 @@
+/* Test the `vld3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld3u8 (void)
+{
+  uint8x8x3_t out_uint8x8x3_t;
+
+  out_uint8x8x3_t = vld3_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
new file mode 100644
index 000000000..5c2499cdc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanef32 (void)
+{
+  float32x4x4_t out_float32x4x4_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
new file mode 100644
index 000000000..1d2d84e63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanep16 (void)
+{
+  poly16x8x4_t out_poly16x8x4_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
new file mode 100644
index 000000000..df23d281c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes16 (void)
+{
+  int16x8x4_t out_int16x8x4_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
new file mode 100644
index 000000000..db1daff7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_lanes32 (void)
+{
+  int32x4x4_t out_int32x4x4_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
new file mode 100644
index 000000000..e2da0ea27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu16 (void)
+{
+  uint16x8x4_t out_uint16x8x4_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
new file mode 100644
index 000000000..d2960ecfc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Q_laneu32 (void)
+{
+  uint32x4x4_t out_uint32x4x4_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
new file mode 100644
index 000000000..0a6e7e6be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qf32 (void)
+{
+  float32x4x4_t out_float32x4x4_t;
+
+  out_float32x4x4_t = vld4q_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
new file mode 100644
index 000000000..5d902f531
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp16 (void)
+{
+  poly16x8x4_t out_poly16x8x4_t;
+
+  out_poly16x8x4_t = vld4q_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
new file mode 100644
index 000000000..e6d66b048
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qp8 (void)
+{
+  poly8x16x4_t out_poly8x16x4_t;
+
+  out_poly8x16x4_t = vld4q_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
new file mode 100644
index 000000000..04394215d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs16 (void)
+{
+  int16x8x4_t out_int16x8x4_t;
+
+  out_int16x8x4_t = vld4q_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
new file mode 100644
index 000000000..4101fa1bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs32 (void)
+{
+  int32x4x4_t out_int32x4x4_t;
+
+  out_int32x4x4_t = vld4q_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
new file mode 100644
index 000000000..9e74f1e4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qs8 (void)
+{
+  int8x16x4_t out_int8x16x4_t;
+
+  out_int8x16x4_t = vld4q_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
new file mode 100644
index 000000000..6b84331f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu16 (void)
+{
+  uint16x8x4_t out_uint16x8x4_t;
+
+  out_uint16x8x4_t = vld4q_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
new file mode 100644
index 000000000..55f7e93e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu32 (void)
+{
+  uint32x4x4_t out_uint32x4x4_t;
+
+  out_uint32x4x4_t = vld4q_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
new file mode 100644
index 000000000..9c766c127
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vld4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4Qu8 (void)
+{
+  uint8x16x4_t out_uint8x16x4_t;
+
+  out_uint8x16x4_t = vld4q_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
new file mode 100644
index 000000000..5315db2d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupf32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupf32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_dup_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
new file mode 100644
index 000000000..7ed8224cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_dup_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
new file mode 100644
index 000000000..bb15964af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp64 (void)
+{
+  poly64x1x4_t out_poly64x1x4_t;
+
+  out_poly64x1x4_t = vld4_dup_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
new file mode 100644
index 000000000..ca1f8fa98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupp8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupp8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_dup_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
new file mode 100644
index 000000000..43dab8f2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dups16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_dup_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
new file mode 100644
index 000000000..183e3e9ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dups32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_dup_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
new file mode 100644
index 000000000..f4c50493a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dups64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups64 (void)
+{
+  int64x1x4_t out_int64x1x4_t;
+
+  out_int64x1x4_t = vld4_dup_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
new file mode 100644
index 000000000..3a4684a09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dups8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dups8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dups8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_dup_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
new file mode 100644
index 000000000..a436cf092
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_dup_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
new file mode 100644
index 000000000..6836abd69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_dup_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
new file mode 100644
index 000000000..244eb6188
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu64 (void)
+{
+  uint64x1x4_t out_uint64x1x4_t;
+
+  out_uint64x1x4_t = vld4_dup_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
new file mode 100644
index 000000000..33c787517
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_dupu8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4_dupu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_dupu8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_dup_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\\\]-\[dD\]\[0-9\]+\\\[\\\])|(\[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\], \[dD\]\[0-9\]+\\\[\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
new file mode 100644
index 000000000..0fc0ab5fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanef32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
new file mode 100644
index 000000000..b7407ade1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
new file mode 100644
index 000000000..7e084106d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanep8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
new file mode 100644
index 000000000..0dc653c5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
new file mode 100644
index 000000000..a3bdaf234
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
new file mode 100644
index 000000000..8555220fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_lanes8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
new file mode 100644
index 000000000..4a417f744
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
new file mode 100644
index 000000000..c1e013a9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
new file mode 100644
index 000000000..31dcf8ae6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vld4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4_laneu8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
new file mode 100644
index 000000000..aa755c0f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4f32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4f32 (void)
+{
+  float32x2x4_t out_float32x2x4_t;
+
+  out_float32x2x4_t = vld4_f32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
new file mode 100644
index 000000000..e0300e8b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4p16 (void)
+{
+  poly16x4x4_t out_poly16x4x4_t;
+
+  out_poly16x4x4_t = vld4_p16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
new file mode 100644
index 000000000..b11fb9384
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vld4p64 (void)
+{
+  poly64x1x4_t out_poly64x1x4_t;
+
+  out_poly64x1x4_t = vld4_p64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
new file mode 100644
index 000000000..7fbb29cf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4p8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4p8 (void)
+{
+  poly8x8x4_t out_poly8x8x4_t;
+
+  out_poly8x8x4_t = vld4_p8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
new file mode 100644
index 000000000..a5ef07b20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4s16 (void)
+{
+  int16x4x4_t out_int16x4x4_t;
+
+  out_int16x4x4_t = vld4_s16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
new file mode 100644
index 000000000..08b929475
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4s32 (void)
+{
+  int32x2x4_t out_int32x2x4_t;
+
+  out_int32x2x4_t = vld4_s32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
new file mode 100644
index 000000000..99ea54803
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4s64 (void)
+{
+  int64x1x4_t out_int64x1x4_t;
+
+  out_int64x1x4_t = vld4_s64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
new file mode 100644
index 000000000..c9574671e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4s8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4s8 (void)
+{
+  int8x8x4_t out_int8x8x4_t;
+
+  out_int8x8x4_t = vld4_s8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
new file mode 100644
index 000000000..4dea8af02
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u16.c
@@ -0,0 +1,19 @@
+/* Test the `vld4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4u16 (void)
+{
+  uint16x4x4_t out_uint16x4x4_t;
+
+  out_uint16x4x4_t = vld4_u16 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
new file mode 100644
index 000000000..aee222589
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u32.c
@@ -0,0 +1,19 @@
+/* Test the `vld4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4u32 (void)
+{
+  uint32x2x4_t out_uint32x2x4_t;
+
+  out_uint32x2x4_t = vld4_u32 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
new file mode 100644
index 000000000..2e8575406
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u64.c
@@ -0,0 +1,19 @@
+/* Test the `vld4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4u64 (void)
+{
+  uint64x1x4_t out_uint64x1x4_t;
+
+  out_uint64x1x4_t = vld4_u64 (0);
+}
+
+/* { dg-final { scan-assembler "vld1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
new file mode 100644
index 000000000..ec1d9f9c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vld4u8.c
@@ -0,0 +1,19 @@
+/* Test the `vld4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vld4u8 (void)
+{
+  uint8x8x4_t out_uint8x8x4_t;
+
+  out_uint8x8x4_t = vld4_u8 (0);
+}
+
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
new file mode 100644
index 000000000..83a2f44d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vmaxq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
new file mode 100644
index 000000000..c8edb7bd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vmaxq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
new file mode 100644
index 000000000..d40f05ee2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vmaxq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
new file mode 100644
index 000000000..55fdce62b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vmaxq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
new file mode 100644
index 000000000..587a7f1c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vmaxq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
new file mode 100644
index 000000000..dbbe70cc8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vmaxq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
new file mode 100644
index 000000000..f785ac8d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vmaxq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
new file mode 100644
index 000000000..ab8cacc3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
new file mode 100644
index 000000000..047d77b49
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
new file mode 100644
index 000000000..43ff8874b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
new file mode 100644
index 000000000..54cec995f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
new file mode 100644
index 000000000..8970ba591
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
new file mode 100644
index 000000000..e7094cdff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
new file mode 100644
index 000000000..4e68c3426
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmaxu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmaxu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmaxu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
new file mode 100644
index 000000000..c1a93c6f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vminQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vminq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
new file mode 100644
index 000000000..889bd4175
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vminQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vminq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
new file mode 100644
index 000000000..dd92bcc49
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vminQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vminq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
new file mode 100644
index 000000000..dc62e26d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vminQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vminq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
new file mode 100644
index 000000000..8b32ee617
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vminQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vminq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
new file mode 100644
index 000000000..bc2bb6a32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vminQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vminq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
new file mode 100644
index 000000000..4f7c5c63d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vminQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vminq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c
new file mode 100644
index 000000000..4b69eb92f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminf32.c
@@ -0,0 +1,21 @@
+/* Test the `vminf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c
new file mode 100644
index 000000000..33d080c73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins16.c
@@ -0,0 +1,21 @@
+/* Test the `vmins16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmins16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c
new file mode 100644
index 000000000..ba9920272
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins32.c
@@ -0,0 +1,21 @@
+/* Test the `vmins32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmins32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c
new file mode 100644
index 000000000..956729db5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmins8.c
@@ -0,0 +1,21 @@
+/* Test the `vmins8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmins8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c
new file mode 100644
index 000000000..eba01626f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu16.c
@@ -0,0 +1,21 @@
+/* Test the `vminu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c
new file mode 100644
index 000000000..079c4ca71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu32.c
@@ -0,0 +1,21 @@
+/* Test the `vminu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c
new file mode 100644
index 000000000..0a2241821
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vminu8.c
@@ -0,0 +1,21 @@
+/* Test the `vminu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vminu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
new file mode 100644
index 000000000..594c1ebdc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
new file mode 100644
index 000000000..151943896
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
new file mode 100644
index 000000000..7ba19cb74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
new file mode 100644
index 000000000..d8885876a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
new file mode 100644
index 000000000..e96e9a7ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
new file mode 100644
index 000000000..3e4057913
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32_t arg2_float32_t;
+
+  out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
new file mode 100644
index 000000000..28e0d462d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16_t arg2_int16_t;
+
+  out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
new file mode 100644
index 000000000..9b5ecf73b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32_t arg2_int32_t;
+
+  out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
new file mode 100644
index 000000000..94481f947
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
new file mode 100644
index 000000000..3b1926ab9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
new file mode 100644
index 000000000..336d56967
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQf32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vmlaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
new file mode 100644
index 000000000..339db8763
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vmlaq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
new file mode 100644
index 000000000..579b2921d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vmlaq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
new file mode 100644
index 000000000..f0e5b60e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQs8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vmlaq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
new file mode 100644
index 000000000..246df1d8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vmlaq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
new file mode 100644
index 000000000..3108c90b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vmlaq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
new file mode 100644
index 000000000..b87b44872
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaQu8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vmlaq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
new file mode 100644
index 000000000..8d68f1c79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
new file mode 100644
index 000000000..a426e1138
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
new file mode 100644
index 000000000..998c06bdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
new file mode 100644
index 000000000..9274af803
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
new file mode 100644
index 000000000..17e96cb82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
new file mode 100644
index 000000000..3a707c7d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32_t arg2_float32_t;
+
+  out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
new file mode 100644
index 000000000..04f2493f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
new file mode 100644
index 000000000..464c09450
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
new file mode 100644
index 000000000..b2eb2ed11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
new file mode 100644
index 000000000..6f11e99a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmla_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmla_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
new file mode 100644
index 000000000..8b1ac6a97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlaf32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlaf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmla_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
new file mode 100644
index 000000000..61f3c7ba9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlal_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
new file mode 100644
index 000000000..d7348de60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlal_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
new file mode 100644
index 000000000..93fc8bf55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlal_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
new file mode 100644
index 000000000..12103d125
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlal_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
new file mode 100644
index 000000000..968aef746
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlal_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
new file mode 100644
index 000000000..d4b3e46be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlal_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
new file mode 100644
index 000000000..9bec57879
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlal_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
new file mode 100644
index 000000000..4fadfe94f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlal_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlal_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
new file mode 100644
index 000000000..a62162000
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
new file mode 100644
index 000000000..e64db5959
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
new file mode 100644
index 000000000..22f4bdbed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlals8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlals8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vmlal_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
new file mode 100644
index 000000000..874fd87b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlalu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlal_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
new file mode 100644
index 000000000..593c06b45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlalu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlal_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
new file mode 100644
index 000000000..efb4312cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlalu8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlalu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vmlal_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
new file mode 100644
index 000000000..b37272b89
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlas16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlas16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmla_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
new file mode 100644
index 000000000..65c2e9af2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlas32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlas32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmla_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
new file mode 100644
index 000000000..fcb1fd38d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlas8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlas8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlas8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vmla_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
new file mode 100644
index 000000000..c1dceab97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlau16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlau16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmla_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
new file mode 100644
index 000000000..6acbea572
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlau32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlau32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmla_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
new file mode 100644
index 000000000..9fc36666b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlau8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlau8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlau8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vmla_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmla\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
new file mode 100644
index 000000000..64ef449a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
new file mode 100644
index 000000000..3788e7f82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
new file mode 100644
index 000000000..952638079
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
new file mode 100644
index 000000000..a176265ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
new file mode 100644
index 000000000..094b9fd17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
new file mode 100644
index 000000000..292a32874
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32_t arg2_float32_t;
+
+  out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
new file mode 100644
index 000000000..02da0712a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16_t arg2_int16_t;
+
+  out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
new file mode 100644
index 000000000..b09aaec97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32_t arg2_int32_t;
+
+  out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
new file mode 100644
index 000000000..a42471171
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
new file mode 100644
index 000000000..b84ff6f6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
new file mode 100644
index 000000000..af2ca68fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQf32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+  float32x4_t arg2_float32x4_t;
+
+  out_float32x4_t = vmlsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
new file mode 100644
index 000000000..4c83d9f31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+  int16x8_t arg2_int16x8_t;
+
+  out_int16x8_t = vmlsq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
new file mode 100644
index 000000000..575ae0c39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+  int32x4_t arg2_int32x4_t;
+
+  out_int32x4_t = vmlsq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
new file mode 100644
index 000000000..227ad9b21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQs8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+  int8x16_t arg2_int8x16_t;
+
+  out_int8x16_t = vmlsq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
new file mode 100644
index 000000000..9d785da73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+  uint16x8_t arg2_uint16x8_t;
+
+  out_uint16x8_t = vmlsq_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
new file mode 100644
index 000000000..55a56a0de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+  uint32x4_t arg2_uint32x4_t;
+
+  out_uint32x4_t = vmlsq_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
new file mode 100644
index 000000000..fc589718e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsQu8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+  uint8x16_t arg2_uint8x16_t;
+
+  out_uint8x16_t = vmlsq_u8 (arg0_uint8x16_t, arg1_uint8x16_t, arg2_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
new file mode 100644
index 000000000..f4b9c306c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
new file mode 100644
index 000000000..827178e4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
new file mode 100644
index 000000000..5e226c1db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
new file mode 100644
index 000000000..dbc1e8bba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
new file mode 100644
index 000000000..7e6406ec0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
new file mode 100644
index 000000000..fca965b90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32_t arg2_float32_t;
+
+  out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
new file mode 100644
index 000000000..712cfbb8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
new file mode 100644
index 000000000..6d977ec22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
new file mode 100644
index 000000000..772d3f97c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
new file mode 100644
index 000000000..4f1368d78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmls_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmls_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
new file mode 100644
index 000000000..2f44ee0ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsf32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+  float32x2_t arg2_float32x2_t;
+
+  out_float32x2_t = vmls_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
new file mode 100644
index 000000000..b36355acf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsl_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
new file mode 100644
index 000000000..dfab11895
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsl_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
new file mode 100644
index 000000000..aff34beac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsl_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
new file mode 100644
index 000000000..c9738747d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsl_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
new file mode 100644
index 000000000..22a045515
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
new file mode 100644
index 000000000..83370fdc0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
new file mode 100644
index 000000000..232f7fe74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16_t arg2_uint16_t;
+
+  out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
new file mode 100644
index 000000000..b64226659
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsl_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32_t arg2_uint32_t;
+
+  out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
new file mode 100644
index 000000000..6ec259efe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
new file mode 100644
index 000000000..b7dd71427
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
new file mode 100644
index 000000000..ca6960bc0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsls8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int16x8_t = vmlsl_s8 (arg0_int16x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
new file mode 100644
index 000000000..47cbfb32a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlslu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlslu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint32x4_t = vmlsl_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
new file mode 100644
index 000000000..9765e5139
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlslu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlslu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint64x2_t = vmlsl_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
new file mode 100644
index 000000000..dcb55162b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlslu8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlslu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlslu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint16x8_t = vmlsl_u8 (arg0_uint16x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmlsl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
new file mode 100644
index 000000000..5655a1584
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int16x4_t = vmls_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
new file mode 100644
index 000000000..1a467dcd3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int32x2_t = vmls_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
new file mode 100644
index 000000000..db95bdc47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlss8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vmls_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
new file mode 100644
index 000000000..dfb918b6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu16.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+  uint16x4_t arg2_uint16x4_t;
+
+  out_uint16x4_t = vmls_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
new file mode 100644
index 000000000..0afbc089f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu32.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+  uint32x2_t arg2_uint32x2_t;
+
+  out_uint32x2_t = vmls_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
new file mode 100644
index 000000000..4da7a41d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmlsu8.c
@@ -0,0 +1,22 @@
+/* Test the `vmlsu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmlsu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vmls_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmls\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
new file mode 100644
index 000000000..751910996
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+
+  out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
new file mode 100644
index 000000000..48361e99e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
new file mode 100644
index 000000000..a3de68fde
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
new file mode 100644
index 000000000..1cec77735
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+
+  out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
new file mode 100644
index 000000000..59178b799
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+
+  out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
new file mode 100644
index 000000000..35936cbd4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+
+  out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
new file mode 100644
index 000000000..e6883aed5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+
+  out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
new file mode 100644
index 000000000..66b459a74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
new file mode 100644
index 000000000..958bb97f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
new file mode 100644
index 000000000..e373a1218
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vmovQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
new file mode 100644
index 000000000..53120a8dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmovQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
new file mode 100644
index 000000000..589911947
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nf32.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+
+  out_float32x2_t = vmov_n_f32 (arg0_float32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
new file mode 100644
index 000000000..02c906c10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np16.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+
+  out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
new file mode 100644
index 000000000..afd6b46f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_np8.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+
+  out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
new file mode 100644
index 000000000..7691e1f4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+
+  out_int16x4_t = vmov_n_s16 (arg0_int16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
new file mode 100644
index 000000000..b1454ca29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+
+  out_int32x2_t = vmov_n_s32 (arg0_int32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
new file mode 100644
index 000000000..7b0112828
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+
+  out_int64x1_t = vmov_n_s64 (arg0_int64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
new file mode 100644
index 000000000..46a5dc8f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+
+  out_int8x8_t = vmov_n_s8 (arg0_int8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
new file mode 100644
index 000000000..00ad860b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+
+  out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
new file mode 100644
index 000000000..c8424c204
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+
+  out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
new file mode 100644
index 000000000..b9613e06f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
@@ -0,0 +1,19 @@
+/* Test the `vmov_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+
+  out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
new file mode 100644
index 000000000..38d80bcd0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmov_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmov_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmov_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+
+  out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
+}
+
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
new file mode 100644
index 000000000..31d5ef14a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls16.c
@@ -0,0 +1,20 @@
+/* Test the `vmovls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vmovl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
new file mode 100644
index 000000000..0d95e2eb9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls32.c
@@ -0,0 +1,20 @@
+/* Test the `vmovls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vmovl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
new file mode 100644
index 000000000..b27db8300
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovls8.c
@@ -0,0 +1,20 @@
+/* Test the `vmovls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vmovl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
new file mode 100644
index 000000000..acca55af2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmovlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovlu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vmovl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
new file mode 100644
index 000000000..f1eee8ee0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmovlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovlu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vmovl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
new file mode 100644
index 000000000..2bf08e1e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmovlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovlu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vmovl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
new file mode 100644
index 000000000..abd648bda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmovns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
new file mode 100644
index 000000000..82c1c3714
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmovns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
new file mode 100644
index 000000000..091bddc2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovns64.c
@@ -0,0 +1,20 @@
+/* Test the `vmovns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
new file mode 100644
index 000000000..85fca5f57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmovnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
new file mode 100644
index 000000000..6bdf0d453
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmovnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
new file mode 100644
index 000000000..41019fb7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmovnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vmovnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmovnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vmovn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
new file mode 100644
index 000000000..cc4651be0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
new file mode 100644
index 000000000..e4620490d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
new file mode 100644
index 000000000..0e0e52734
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
new file mode 100644
index 000000000..d8897a599
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
new file mode 100644
index 000000000..f336710cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
new file mode 100644
index 000000000..e37e9ae40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32_t arg1_float32_t;
+
+  out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
new file mode 100644
index 000000000..ff81b43ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
new file mode 100644
index 000000000..714bef43a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
new file mode 100644
index 000000000..ef05b9378
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
new file mode 100644
index 000000000..2af6d757a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
new file mode 100644
index 000000000..3e9ceb056
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vmulq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
new file mode 100644
index 000000000..fe19f13da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vmulq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
new file mode 100644
index 000000000..5d4ac7b1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vmulq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
new file mode 100644
index 000000000..3f8027270
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vmulq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
new file mode 100644
index 000000000..8e49dbcf2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vmulq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
new file mode 100644
index 000000000..e73bc6dd0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vmulq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
new file mode 100644
index 000000000..d041a0d8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vmulq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
new file mode 100644
index 000000000..75b3c67d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmulQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vmulq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
new file mode 100644
index 000000000..967117975
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
new file mode 100644
index 000000000..b1a089274
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
new file mode 100644
index 000000000..dce5e9a94
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
new file mode 100644
index 000000000..d73a2514d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
new file mode 100644
index 000000000..c77268bca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
new file mode 100644
index 000000000..8f7522402
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_nf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_nf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32_t arg1_float32_t;
+
+  out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
new file mode 100644
index 000000000..cf24912d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
new file mode 100644
index 000000000..9c0a35e53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
new file mode 100644
index 000000000..5d2c60b48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
new file mode 100644
index 000000000..9957837e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmul_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmul_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
new file mode 100644
index 000000000..7081b2f07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulf32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vmul_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
new file mode 100644
index 000000000..4467bca7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vmull_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
new file mode 100644
index 000000000..db1655faa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vmull_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
new file mode 100644
index 000000000..c723df2ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmull_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
new file mode 100644
index 000000000..adea5cc3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmull_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_laneu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
new file mode 100644
index 000000000..9de27deb9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vmull_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
new file mode 100644
index 000000000..0fe16d16f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vmull_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
new file mode 100644
index 000000000..b3e9c1932
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmull_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16_t arg1_uint16_t;
+
+  out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
new file mode 100644
index 000000000..6cf18d24a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmull_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmull_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32_t arg1_uint32_t;
+
+  out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
new file mode 100644
index 000000000..72c288392
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullp8.c
@@ -0,0 +1,21 @@
+/* Test the `vmullp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmullp8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly16x8_t = vmull_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.p8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
new file mode 100644
index 000000000..cb7327886
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls16.c
@@ -0,0 +1,21 @@
+/* Test the `vmulls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
new file mode 100644
index 000000000..816f3abc0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
new file mode 100644
index 000000000..4c0d2b4aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulls8.c
@@ -0,0 +1,21 @@
+/* Test the `vmulls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vmull_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
new file mode 100644
index 000000000..8dad8be65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmullu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmullu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vmull_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
new file mode 100644
index 000000000..6010fa92c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmullu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmullu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vmull_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
new file mode 100644
index 000000000..05eb05ac3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmullu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmullu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmullu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vmull_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmull\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
new file mode 100644
index 000000000..3a9857271
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulp8.c
@@ -0,0 +1,21 @@
+/* Test the `vmulp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vmul_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.p8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
new file mode 100644
index 000000000..b2ac4c8c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls16.c
@@ -0,0 +1,21 @@
+/* Test the `vmuls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmuls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vmul_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
new file mode 100644
index 000000000..7cac98d82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls32.c
@@ -0,0 +1,21 @@
+/* Test the `vmuls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmuls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vmul_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
new file mode 100644
index 000000000..08fd311ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmuls8.c
@@ -0,0 +1,21 @@
+/* Test the `vmuls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmuls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vmul_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
new file mode 100644
index 000000000..141d72fbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu16.c
@@ -0,0 +1,21 @@
+/* Test the `vmulu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vmul_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
new file mode 100644
index 000000000..5c36ffb9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu32.c
@@ -0,0 +1,21 @@
+/* Test the `vmulu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vmul_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
new file mode 100644
index 000000000..51d4a1708
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmulu8.c
@@ -0,0 +1,21 @@
+/* Test the `vmulu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmulu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vmul_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmul\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
new file mode 100644
index 000000000..47d50b64f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vmvnq_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
new file mode 100644
index 000000000..e60488447
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vmvnq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
new file mode 100644
index 000000000..ccad86944
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vmvnq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
new file mode 100644
index 000000000..164907c7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vmvnq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
new file mode 100644
index 000000000..ce18a4907
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vmvnq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
new file mode 100644
index 000000000..34795c776
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vmvnq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
new file mode 100644
index 000000000..d93aa36b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vmvnq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
new file mode 100644
index 000000000..46e3cf910
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnp8.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnp8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vmvn_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
new file mode 100644
index 000000000..8464b2b95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns16.c
@@ -0,0 +1,20 @@
+/* Test the `vmvns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vmvn_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
new file mode 100644
index 000000000..7a4dd9a79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns32.c
@@ -0,0 +1,20 @@
+/* Test the `vmvns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vmvn_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
new file mode 100644
index 000000000..c09872092
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvns8.c
@@ -0,0 +1,20 @@
+/* Test the `vmvns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vmvn_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
new file mode 100644
index 000000000..ab600a0a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vmvn_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
new file mode 100644
index 000000000..df2bd4b5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vmvn_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
new file mode 100644
index 000000000..729ab71c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vmvnu8.c
@@ -0,0 +1,20 @@
+/* Test the `vmvnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vmvnu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vmvn_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vmvn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
new file mode 100644
index 000000000..c1e116913
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vnegQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vnegq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
new file mode 100644
index 000000000..c8b149789
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vnegQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
new file mode 100644
index 000000000..e8b3e925c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vnegQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
new file mode 100644
index 000000000..4e8e80d31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vnegQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
new file mode 100644
index 000000000..82e95399f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegf32.c
@@ -0,0 +1,20 @@
+/* Test the `vnegf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vneg_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
new file mode 100644
index 000000000..ff2315180
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs16.c
@@ -0,0 +1,20 @@
+/* Test the `vnegs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
new file mode 100644
index 000000000..82108678e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs32.c
@@ -0,0 +1,20 @@
+/* Test the `vnegs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
new file mode 100644
index 000000000..952e34010
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vnegs8.c
@@ -0,0 +1,20 @@
+/* Test the `vnegs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vnegs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
new file mode 100644
index 000000000..519da3ccc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vornQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vornq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
new file mode 100644
index 000000000..cec659911
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vornQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vornq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
new file mode 100644
index 000000000..05166ba4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vornQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vornq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
new file mode 100644
index 000000000..99982aefd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vornQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vornq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
new file mode 100644
index 000000000..761e72d7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vornQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vornq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
new file mode 100644
index 000000000..18a968539
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vornQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vornq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
new file mode 100644
index 000000000..84c9f895d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vornQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vornq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
new file mode 100644
index 000000000..ffe6766d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vornQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vornq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c
new file mode 100644
index 000000000..b860142dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns16.c
@@ -0,0 +1,21 @@
+/* Test the `vorns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vorn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c
new file mode 100644
index 000000000..826e0d288
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns32.c
@@ -0,0 +1,21 @@
+/* Test the `vorns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vorn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c
new file mode 100644
index 000000000..d7b8e60d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns64.c
@@ -0,0 +1,20 @@
+/* Test the `vorns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vorn_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c
new file mode 100644
index 000000000..c71a6bb0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorns8.c
@@ -0,0 +1,21 @@
+/* Test the `vorns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vorn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c
new file mode 100644
index 000000000..d4983eebf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu16.c
@@ -0,0 +1,21 @@
+/* Test the `vornu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vorn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c
new file mode 100644
index 000000000..aba68841a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu32.c
@@ -0,0 +1,21 @@
+/* Test the `vornu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vorn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c
new file mode 100644
index 000000000..6fb3a9502
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu64.c
@@ -0,0 +1,20 @@
+/* Test the `vornu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vorn_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c
new file mode 100644
index 000000000..6fdb7331c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vornu8.c
@@ -0,0 +1,21 @@
+/* Test the `vornu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vornu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vorn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorn\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
new file mode 100644
index 000000000..20ae7342e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vorrQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vorrq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
new file mode 100644
index 000000000..ba42dccd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vorrQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vorrq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
new file mode 100644
index 000000000..f46e7c16e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vorrQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vorrq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
new file mode 100644
index 000000000..d58607c84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vorrQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vorrq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
new file mode 100644
index 000000000..ce29c4ad7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vorrQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vorrq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
new file mode 100644
index 000000000..8b1a64845
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vorrQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vorrq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
new file mode 100644
index 000000000..55cf57ae5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vorrQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vorrq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
new file mode 100644
index 000000000..7be85fc43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vorrQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vorrq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
new file mode 100644
index 000000000..8e942cc1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs16.c
@@ -0,0 +1,21 @@
+/* Test the `vorrs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vorr_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
new file mode 100644
index 000000000..f940a6530
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs32.c
@@ -0,0 +1,21 @@
+/* Test the `vorrs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vorr_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
new file mode 100644
index 000000000..a1c7e5ee2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs64.c
@@ -0,0 +1,20 @@
+/* Test the `vorrs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vorr_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
new file mode 100644
index 000000000..2d6b70cbe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorrs8.c
@@ -0,0 +1,21 @@
+/* Test the `vorrs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorrs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vorr_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c
new file mode 100644
index 000000000..5d50d7aad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru16.c
@@ -0,0 +1,21 @@
+/* Test the `vorru16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorru16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vorr_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c
new file mode 100644
index 000000000..60c847649
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru32.c
@@ -0,0 +1,21 @@
+/* Test the `vorru32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorru32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vorr_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c
new file mode 100644
index 000000000..1991b0215
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru64.c
@@ -0,0 +1,20 @@
+/* Test the `vorru64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorru64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vorr_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c
new file mode 100644
index 000000000..e47d465e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vorru8.c
@@ -0,0 +1,21 @@
+/* Test the `vorru8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vorru8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vorr_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vorr\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
new file mode 100644
index 000000000..35dcdbbad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int32x4_t = vpadalq_s16 (arg0_int32x4_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
new file mode 100644
index 000000000..a82551a28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int64x2_t = vpadalq_s32 (arg0_int64x2_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
new file mode 100644
index 000000000..182ea46c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQs8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int16x8_t = vpadalq_s8 (arg0_int16x8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
new file mode 100644
index 000000000..c9f7833d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint32x4_t = vpadalq_u16 (arg0_uint32x4_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
new file mode 100644
index 000000000..80cf323ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint64x2_t = vpadalq_u32 (arg0_uint64x2_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
new file mode 100644
index 000000000..8e1dac223
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalQu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint16x8_t = vpadalq_u8 (arg0_uint16x8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
new file mode 100644
index 000000000..88c3cb179
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals16.c
@@ -0,0 +1,21 @@
+/* Test the `vpadals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadals16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x2_t = vpadal_s16 (arg0_int32x2_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
new file mode 100644
index 000000000..95897f5cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals32.c
@@ -0,0 +1,21 @@
+/* Test the `vpadals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadals32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x1_t = vpadal_s32 (arg0_int64x1_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
new file mode 100644
index 000000000..3cc18459d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadals8.c
@@ -0,0 +1,21 @@
+/* Test the `vpadals8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadals8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x4_t = vpadal_s8 (arg0_int16x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
new file mode 100644
index 000000000..280e4d611
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu16.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalu16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x2_t = vpadal_u16 (arg0_uint32x2_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
new file mode 100644
index 000000000..1792b43d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu32.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalu32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x1_t = vpadal_u32 (arg0_uint64x1_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
new file mode 100644
index 000000000..f3fb6b031
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadalu8.c
@@ -0,0 +1,21 @@
+/* Test the `vpadalu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadalu8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x4_t = vpadal_u8 (arg0_uint16x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadal\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
new file mode 100644
index 000000000..f08c8506a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddf32.c
@@ -0,0 +1,21 @@
+/* Test the `vpaddf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpadd_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
new file mode 100644
index 000000000..b3fc9aa13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int32x4_t = vpaddlq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
new file mode 100644
index 000000000..00399e804
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int64x2_t = vpaddlq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
new file mode 100644
index 000000000..09191ab3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQs8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int16x8_t = vpaddlq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
new file mode 100644
index 000000000..d65754b0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint32x4_t = vpaddlq_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
new file mode 100644
index 000000000..b93bfd3f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint64x2_t = vpaddlq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
new file mode 100644
index 000000000..15f8a18a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlQu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlQu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint16x8_t = vpaddlq_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
new file mode 100644
index 000000000..57d93b50d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls16.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddls16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x2_t = vpaddl_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
new file mode 100644
index 000000000..5abb48994
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddls32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x1_t = vpaddl_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
new file mode 100644
index 000000000..0107bfa1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddls8.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddls8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x4_t = vpaddl_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
new file mode 100644
index 000000000..01c1fac9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu16.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vpaddl_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
new file mode 100644
index 000000000..6c47b0582
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu32.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vpaddl_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
new file mode 100644
index 000000000..47fbc738a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddlu8.c
@@ -0,0 +1,20 @@
+/* Test the `vpaddlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddlu8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vpaddl_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpaddl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
new file mode 100644
index 000000000..6d9ad1afd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds16.c
@@ -0,0 +1,21 @@
+/* Test the `vpadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
new file mode 100644
index 000000000..36d8aad1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds32.c
@@ -0,0 +1,21 @@
+/* Test the `vpadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
new file mode 100644
index 000000000..ea6bcae85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpadds8.c
@@ -0,0 +1,21 @@
+/* Test the `vpadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
new file mode 100644
index 000000000..1a19916e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu16.c
@@ -0,0 +1,21 @@
+/* Test the `vpaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
new file mode 100644
index 000000000..3bf215c71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu32.c
@@ -0,0 +1,21 @@
+/* Test the `vpaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
new file mode 100644
index 000000000..e1b6c5987
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpaddu8.c
@@ -0,0 +1,21 @@
+/* Test the `vpaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpadd\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
new file mode 100644
index 000000000..267fc3862
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxf32.c
@@ -0,0 +1,21 @@
+/* Test the `vpmaxf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpmax_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
new file mode 100644
index 000000000..7476f2462
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs16.c
@@ -0,0 +1,21 @@
+/* Test the `vpmaxs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpmax_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
new file mode 100644
index 000000000..d2c3e81f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs32.c
@@ -0,0 +1,21 @@
+/* Test the `vpmaxs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpmax_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
new file mode 100644
index 000000000..c15c0b0a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxs8.c
@@ -0,0 +1,21 @@
+/* Test the `vpmaxs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpmax_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
new file mode 100644
index 000000000..8fbad8694
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu16.c
@@ -0,0 +1,21 @@
+/* Test the `vpmaxu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpmax_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
new file mode 100644
index 000000000..2869fd339
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu32.c
@@ -0,0 +1,21 @@
+/* Test the `vpmaxu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpmax_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
new file mode 100644
index 000000000..75a29f27b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmaxu8.c
@@ -0,0 +1,21 @@
+/* Test the `vpmaxu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmaxu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpmax_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmax\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
new file mode 100644
index 000000000..59836f78f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminf32.c
@@ -0,0 +1,21 @@
+/* Test the `vpminf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpminf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vpmin_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
new file mode 100644
index 000000000..14af72840
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins16.c
@@ -0,0 +1,21 @@
+/* Test the `vpmins16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmins16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vpmin_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
new file mode 100644
index 000000000..c34afbdff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins32.c
@@ -0,0 +1,21 @@
+/* Test the `vpmins32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmins32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vpmin_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
new file mode 100644
index 000000000..b0212ff90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpmins8.c
@@ -0,0 +1,21 @@
+/* Test the `vpmins8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpmins8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vpmin_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
new file mode 100644
index 000000000..a9fa87c7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu16.c
@@ -0,0 +1,21 @@
+/* Test the `vpminu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpminu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vpmin_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
new file mode 100644
index 000000000..2c2cb75ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu32.c
@@ -0,0 +1,21 @@
+/* Test the `vpminu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpminu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vpmin_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
new file mode 100644
index 000000000..726fa72fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vpminu8.c
@@ -0,0 +1,21 @@
+/* Test the `vpminu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vpminu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vpmin_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vpmin\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
new file mode 100644
index 000000000..75cbc0a2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulhQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
new file mode 100644
index 000000000..12978d383
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulhQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
new file mode 100644
index 000000000..55f9037f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulhQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
new file mode 100644
index 000000000..7323fe22a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulhQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
new file mode 100644
index 000000000..f6c3d1fdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulhQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqrdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
new file mode 100644
index 000000000..2801f4ffc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulhQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqrdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
new file mode 100644
index 000000000..3567a8ced
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulh_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
new file mode 100644
index 000000000..04d8fe750
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulh_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
new file mode 100644
index 000000000..1ab2c5ab6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulh_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
new file mode 100644
index 000000000..16a0de031
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulh_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulh_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
new file mode 100644
index 000000000..d27b4bce3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulhs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
new file mode 100644
index 000000000..e4dc0b90d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRdmulhs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRdmulhs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRdmulhs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
new file mode 100644
index 000000000..ed3dc442a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqrshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
new file mode 100644
index 000000000..54bd77781
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqrshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
new file mode 100644
index 000000000..47dc81e8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqrshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
new file mode 100644
index 000000000..4bd258949
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqrshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
new file mode 100644
index 000000000..b150120eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vqrshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
new file mode 100644
index 000000000..f38f38396
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vqrshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
new file mode 100644
index 000000000..0c2da6d42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vqrshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
new file mode 100644
index 000000000..e2e515577
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vqrshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
new file mode 100644
index 000000000..c0c456c34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqrshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
new file mode 100644
index 000000000..275150c86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqrshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
new file mode 100644
index 000000000..6e67b57d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls64.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqrshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
new file mode 100644
index 000000000..a81c9eaf2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshls8.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqrshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
new file mode 100644
index 000000000..2c2a7bfcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu16.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vqrshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
new file mode 100644
index 000000000..65dd695fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu32.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vqrshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
new file mode 100644
index 000000000..3757279e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu64.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vqrshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
new file mode 100644
index 000000000..01565bba5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshlu8.c
@@ -0,0 +1,21 @@
+/* Test the `vqRshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vqrshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqrshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
new file mode 100644
index 000000000..ff5902f6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqrshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
new file mode 100644
index 000000000..7a01d6b7a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqrshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
new file mode 100644
index 000000000..ddb866280
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqrshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
new file mode 100644
index 000000000..5147ac90f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqrshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
new file mode 100644
index 000000000..8d682946b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqrshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
new file mode 100644
index 000000000..7f7eacba8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrn_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqrshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
new file mode 100644
index 000000000..547ffd1b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrun_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqrshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
new file mode 100644
index 000000000..a8f7904a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrun_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqrshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
new file mode 100644
index 000000000..fde62bcbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrun_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
new file mode 100644
index 000000000..a31b5cb51
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqabsQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqabsq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
new file mode 100644
index 000000000..3ef17b938
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqabsQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqabsq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
new file mode 100644
index 000000000..e4ddbb666
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabsQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqabsQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabsQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqabsq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
new file mode 100644
index 000000000..9bcab766b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss16.c
@@ -0,0 +1,20 @@
+/* Test the `vqabss16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabss16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqabs_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
new file mode 100644
index 000000000..20ecb7eea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss32.c
@@ -0,0 +1,20 @@
+/* Test the `vqabss32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabss32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqabs_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
new file mode 100644
index 000000000..e4ee27ce6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqabss8.c
@@ -0,0 +1,20 @@
+/* Test the `vqabss8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqabss8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqabs_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqabs\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
new file mode 100644
index 000000000..d5e1fc289
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqaddq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
new file mode 100644
index 000000000..f408a3e04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqaddq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
new file mode 100644
index 000000000..8f1a1a8b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqaddq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
new file mode 100644
index 000000000..e94dc13d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqaddq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
new file mode 100644
index 000000000..84f567748
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vqaddq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
new file mode 100644
index 000000000..5055627d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vqaddq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
new file mode 100644
index 000000000..cc3da0faa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vqaddq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
new file mode 100644
index 000000000..d64daf408
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vqaddq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
new file mode 100644
index 000000000..4a4df0be8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds16.c
@@ -0,0 +1,21 @@
+/* Test the `vqadds16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqadds16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqadd_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
new file mode 100644
index 000000000..b1a022fd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds32.c
@@ -0,0 +1,21 @@
+/* Test the `vqadds32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqadds32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqadd_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
new file mode 100644
index 000000000..48b4a6ebc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds64.c
@@ -0,0 +1,21 @@
+/* Test the `vqadds64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqadds64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqadd_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
new file mode 100644
index 000000000..3b408bc8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqadds8.c
@@ -0,0 +1,21 @@
+/* Test the `vqadds8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqadds8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqadd_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
new file mode 100644
index 000000000..b3d720483
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu16.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vqadd_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
new file mode 100644
index 000000000..dbe9038a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu32.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vqadd_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
new file mode 100644
index 000000000..08230f833
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu64.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vqadd_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
new file mode 100644
index 000000000..c465022f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqaddu8.c
@@ -0,0 +1,21 @@
+/* Test the `vqaddu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqaddu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vqadd_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqadd\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
new file mode 100644
index 000000000..d2567c092
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlal_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
new file mode 100644
index 000000000..7a9cfe8bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlal_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
new file mode 100644
index 000000000..43a096265
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlal_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
new file mode 100644
index 000000000..2031a60db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlal_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlal_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
new file mode 100644
index 000000000..6391a7988
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals16.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlals16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlal_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
new file mode 100644
index 000000000..e7ff0d849
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlals32.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlals32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlals32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlal_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
new file mode 100644
index 000000000..aa32c490b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlsl_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
new file mode 100644
index 000000000..c88b81a5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlsl_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
new file mode 100644
index 000000000..3981f508b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlsl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16_t arg2_int16_t;
+
+  out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
new file mode 100644
index 000000000..36c200be8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlsl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsl_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32_t arg2_int32_t;
+
+  out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
new file mode 100644
index 000000000..06aeb8e14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls16.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlsls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+  int16x4_t arg2_int16x4_t;
+
+  out_int32x4_t = vqdmlsl_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
new file mode 100644
index 000000000..fac2fb654
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmlsls32.c
@@ -0,0 +1,22 @@
+/* Test the `vqdmlsls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmlsls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+  int32x2_t arg2_int32x2_t;
+
+  out_int64x2_t = vqdmlsl_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
new file mode 100644
index 000000000..70ee8a3f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulhQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
new file mode 100644
index 000000000..ea74a9172
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulhQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
new file mode 100644
index 000000000..10009f0d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulhQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16_t arg1_int16_t;
+
+  out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
new file mode 100644
index 000000000..1884c9528
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulhQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32_t arg1_int32_t;
+
+  out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
new file mode 100644
index 000000000..c9cacfc1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulhQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqdmulhq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
new file mode 100644
index 000000000..ff6eb74e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulhQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqdmulhq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
new file mode 100644
index 000000000..5b8e4c54e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulh_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
new file mode 100644
index 000000000..507bde891
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulh_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
new file mode 100644
index 000000000..e16030c2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulh_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
new file mode 100644
index 000000000..be38f92ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulh_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulh_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
new file mode 100644
index 000000000..ef591cba6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulhs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqdmulh_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
new file mode 100644
index 000000000..cb51f4be9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulhs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulhs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulhs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqdmulh_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
new file mode 100644
index 000000000..f9476a2f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmull_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
new file mode 100644
index 000000000..2d5ee0064
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmull_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_lanes32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
new file mode 100644
index 000000000..1e980f1ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmull_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16_t arg1_int16_t;
+
+  out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
new file mode 100644
index 000000000..947aa9635
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmull_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmull_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32_t arg1_int32_t;
+
+  out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
new file mode 100644
index 000000000..72ba7c2ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls16.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vqdmull_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
new file mode 100644
index 000000000..6a6b2e2d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqdmulls32.c
@@ -0,0 +1,21 @@
+/* Test the `vqdmulls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqdmulls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vqdmull_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
new file mode 100644
index 000000000..8807b5909
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqmovn_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
new file mode 100644
index 000000000..a921575e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqmovn_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
new file mode 100644
index 000000000..3c5285b11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqmovn_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
new file mode 100644
index 000000000..ce74646fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqmovn_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
new file mode 100644
index 000000000..74e1b8a08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqmovn_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
new file mode 100644
index 000000000..2e312505b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovnu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqmovn_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
new file mode 100644
index 000000000..845af1fa9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovuns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqmovun_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
new file mode 100644
index 000000000..6fa8d97a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovuns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqmovun_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
new file mode 100644
index 000000000..cb9b462b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqmovuns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqmovuns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqmovuns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqmovun_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqmovun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
new file mode 100644
index 000000000..c5f523858
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqnegQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
new file mode 100644
index 000000000..cc32b2138
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqnegQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
new file mode 100644
index 000000000..755847d0b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqnegQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
new file mode 100644
index 000000000..a05a1fc8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs16.c
@@ -0,0 +1,20 @@
+/* Test the `vqnegs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqneg_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
new file mode 100644
index 000000000..30c43ef5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs32.c
@@ -0,0 +1,20 @@
+/* Test the `vqnegs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqneg_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
new file mode 100644
index 000000000..d9f23ad83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqnegs8.c
@@ -0,0 +1,20 @@
+/* Test the `vqnegs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqnegs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqneg_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
new file mode 100644
index 000000000..1383779fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vqshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
new file mode 100644
index 000000000..acafc1c28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vqshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
new file mode 100644
index 000000000..ec90a8866
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vqshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
new file mode 100644
index 000000000..e2a25e93d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vqshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
new file mode 100644
index 000000000..b01497d40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vqshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
new file mode 100644
index 000000000..613d3dc66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vqshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
new file mode 100644
index 000000000..1d9bea8b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vqshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
new file mode 100644
index 000000000..1f0e739b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vqshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
new file mode 100644
index 000000000..80f3644a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
new file mode 100644
index 000000000..6c5bd1606
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
new file mode 100644
index 000000000..6819d8286
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
new file mode 100644
index 000000000..27c5c1d26
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
new file mode 100644
index 000000000..163e02def
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vqshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
new file mode 100644
index 000000000..b6f46d096
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vqshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
new file mode 100644
index 000000000..15ecce049
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vqshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
new file mode 100644
index 000000000..058095b36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vqshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
new file mode 100644
index 000000000..de81ba00e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vqshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
new file mode 100644
index 000000000..fac6fdb49
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vqshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
new file mode 100644
index 000000000..0860a4463
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vqshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
new file mode 100644
index 000000000..4e49ad352
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vqshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
new file mode 100644
index 000000000..483aa8179
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vqshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
new file mode 100644
index 000000000..ad09efda2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vqshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
new file mode 100644
index 000000000..9abc96025
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vqshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
new file mode 100644
index 000000000..d02d6f7c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshl_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vqshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
new file mode 100644
index 000000000..cf288a078
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls16.c
@@ -0,0 +1,21 @@
+/* Test the `vqshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
new file mode 100644
index 000000000..39e38bfc8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls32.c
@@ -0,0 +1,21 @@
+/* Test the `vqshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
new file mode 100644
index 000000000..6057b3589
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls64.c
@@ -0,0 +1,21 @@
+/* Test the `vqshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
new file mode 100644
index 000000000..4d3332fd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshls8.c
@@ -0,0 +1,21 @@
+/* Test the `vqshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
new file mode 100644
index 000000000..cbae9aaec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu16.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vqshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
new file mode 100644
index 000000000..89ba48a23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu32.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vqshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
new file mode 100644
index 000000000..df91fa9b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu64.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vqshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
new file mode 100644
index 000000000..f7ea9231b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu8.c
@@ -0,0 +1,21 @@
+/* Test the `vqshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vqshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
new file mode 100644
index 000000000..26feb6474
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshluQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint16x8_t = vqshluq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
new file mode 100644
index 000000000..70a156d6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshluQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint32x4_t = vqshluq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
new file mode 100644
index 000000000..bed332d60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshluQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint64x2_t = vqshluq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
new file mode 100644
index 000000000..96e434752
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshluQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshluQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshluQ_ns8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint8x16_t = vqshluq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
new file mode 100644
index 000000000..2ec926ee2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vqshlu_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
new file mode 100644
index 000000000..b9c156ad0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vqshlu_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
new file mode 100644
index 000000000..5003573d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vqshlu_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
new file mode 100644
index 000000000..649588e97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshlu_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vqshlu_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshlu_ns8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vqshlu_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshlu\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
new file mode 100644
index 000000000..4a0d5095b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vqshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
new file mode 100644
index 000000000..e9a10f6d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vqshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
new file mode 100644
index 000000000..32e9aef2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vqshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
new file mode 100644
index 000000000..6582d8fea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vqshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
new file mode 100644
index 000000000..39eef07f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vqshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
new file mode 100644
index 000000000..b479526ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrn_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vqshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrn\.u64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
new file mode 100644
index 000000000..94d6b60e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrun_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x8_t = vqshrun_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
new file mode 100644
index 000000000..9d04d51a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrun_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x4_t = vqshrun_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
new file mode 100644
index 000000000..37085e97c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqshrun_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqshrun_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqshrun_ns64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x2_t = vqshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqshrun\.s64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
new file mode 100644
index 000000000..72943b2e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vqsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
new file mode 100644
index 000000000..be37e9115
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vqsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
new file mode 100644
index 000000000..019b0a696
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vqsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
new file mode 100644
index 000000000..a08c1404d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vqsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
new file mode 100644
index 000000000..979f7c173
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vqsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
new file mode 100644
index 000000000..b0de08699
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vqsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
new file mode 100644
index 000000000..e03c2b236
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vqsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
new file mode 100644
index 000000000..a447931a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vqsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
new file mode 100644
index 000000000..89a87e5b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs16.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vqsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
new file mode 100644
index 000000000..fdc563c19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs32.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vqsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
new file mode 100644
index 000000000..f8ba1ed00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs64.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vqsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
new file mode 100644
index 000000000..c16cb1a9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubs8.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vqsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
new file mode 100644
index 000000000..51b58df63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu16.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vqsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
new file mode 100644
index 000000000..799a3e38d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu32.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vqsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
new file mode 100644
index 000000000..673c8174b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu64.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vqsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
new file mode 100644
index 000000000..5a1eb44cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqsubu8.c
@@ -0,0 +1,21 @@
+/* Test the `vqsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vqsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vqsub\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
new file mode 100644
index 000000000..d35cbd6e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpeQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrecpeq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
new file mode 100644
index 000000000..9f0949e0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpeQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpeQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrecpeq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
new file mode 100644
index 000000000..edd17ee47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpef32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrecpe_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
new file mode 100644
index 000000000..d59e810ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpeu32.c
@@ -0,0 +1,20 @@
+/* Test the `vrecpeu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpeu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrecpe_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecpe\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
new file mode 100644
index 000000000..d3452e96e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vrecpsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrecpsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
new file mode 100644
index 000000000..c8d885b07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrecpsf32.c
@@ -0,0 +1,21 @@
+/* Test the `vrecpsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrecpsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrecps_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrecps\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
new file mode 100644
index 000000000..91cac4df5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p128 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_float32x4_t = vreinterpretq_f32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
new file mode 100644
index 000000000..58049ac5b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p16 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
new file mode 100644
index 000000000..96909f677
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p64 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
new file mode 100644
index 000000000..fc5676001
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_p8 (void)
+{
+  float32x4_t out_float32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
new file mode 100644
index 000000000..dc2227fe2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s16 (void)
+{
+  float32x4_t out_float32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
new file mode 100644
index 000000000..d0781f467
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s32 (void)
+{
+  float32x4_t out_float32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_float32x4_t = vreinterpretq_f32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
new file mode 100644
index 000000000..1528c711e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s64 (void)
+{
+  float32x4_t out_float32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
new file mode 100644
index 000000000..eb3a46bd4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_s8 (void)
+{
+  float32x4_t out_float32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
new file mode 100644
index 000000000..5562dfff4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u16 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_float32x4_t = vreinterpretq_f32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
new file mode 100644
index 000000000..8b43c6693
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u32 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_float32x4_t = vreinterpretq_f32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
new file mode 100644
index 000000000..71e6a5f9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u64 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_float32x4_t = vreinterpretq_f32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
new file mode 100644
index 000000000..569316344
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQf32_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQf32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQf32_u8 (void)
+{
+  float32x4_t out_float32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_float32x4_t = vreinterpretq_f32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
new file mode 100644
index 000000000..aa7d2e7e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_f32 (void)
+{
+  poly128_t out_poly128_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
new file mode 100644
index 000000000..94f2e9b4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p16 (void)
+{
+  poly128_t out_poly128_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
new file mode 100644
index 000000000..d32007547
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p64 (void)
+{
+  poly128_t out_poly128_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
new file mode 100644
index 000000000..112b0c6e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_p8 (void)
+{
+  poly128_t out_poly128_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
new file mode 100644
index 000000000..4fa06b238
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s16 (void)
+{
+  poly128_t out_poly128_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
new file mode 100644
index 000000000..5f17cb813
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s32 (void)
+{
+  poly128_t out_poly128_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
new file mode 100644
index 000000000..9b83912b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s64 (void)
+{
+  poly128_t out_poly128_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
new file mode 100644
index 000000000..49e8b74b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_s8 (void)
+{
+  poly128_t out_poly128_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
new file mode 100644
index 000000000..d47429aeb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u16 (void)
+{
+  poly128_t out_poly128_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly128_t = vreinterpretq_p128_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
new file mode 100644
index 000000000..57abf79a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u32 (void)
+{
+  poly128_t out_poly128_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly128_t = vreinterpretq_p128_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
new file mode 100644
index 000000000..4d04daaaa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u64 (void)
+{
+  poly128_t out_poly128_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly128_t = vreinterpretq_p128_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
new file mode 100644
index 000000000..ba07bbc8a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp128_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp128_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp128_u8 (void)
+{
+  poly128_t out_poly128_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly128_t = vreinterpretq_p128_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
new file mode 100644
index 000000000..b94f8f6ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_f32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
new file mode 100644
index 000000000..27d0d0afb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p128 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
new file mode 100644
index 000000000..a0a3aaff4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
new file mode 100644
index 000000000..d284b595c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_p8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
new file mode 100644
index 000000000..fedcfa8de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
new file mode 100644
index 000000000..8c56fee74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
new file mode 100644
index 000000000..03c391a73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
new file mode 100644
index 000000000..11b6c915d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_s8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
new file mode 100644
index 000000000..80ba65f7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
new file mode 100644
index 000000000..f1c9aeb75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u32 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
new file mode 100644
index 000000000..c2365d1bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u64 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
new file mode 100644
index 000000000..8333c2f16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp16_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp16_u8 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly16x8_t = vreinterpretq_p16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
new file mode 100644
index 000000000..9f9b1a4ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_f32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
new file mode 100644
index 000000000..3f7129513
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p128 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
new file mode 100644
index 000000000..897b7cd9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
new file mode 100644
index 000000000..772b268bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_p8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
new file mode 100644
index 000000000..29f3f6c1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
new file mode 100644
index 000000000..fae22f65e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
new file mode 100644
index 000000000..8769bc8e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
new file mode 100644
index 000000000..1163cc2b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_s8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
new file mode 100644
index 000000000..f2b53260e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u16 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
new file mode 100644
index 000000000..6b6179ba4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u32 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
new file mode 100644
index 000000000..655ffd4fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
new file mode 100644
index 000000000..40b40dd11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp64_u8 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly64x2_t = vreinterpretq_p64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
new file mode 100644
index 000000000..e27080efd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_f32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
new file mode 100644
index 000000000..b517a6fdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p128 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
new file mode 100644
index 000000000..86dd6a4a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
new file mode 100644
index 000000000..9e70b8a07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_p64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
new file mode 100644
index 000000000..608e27293
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
new file mode 100644
index 000000000..7900676d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
new file mode 100644
index 000000000..27483dcf4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
new file mode 100644
index 000000000..d4be56f6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_s8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_poly8x16_t = vreinterpretq_p8_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
new file mode 100644
index 000000000..c00a55fe0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u16 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
new file mode 100644
index 000000000..e5b580b44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u32 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
new file mode 100644
index 000000000..5e80ed7d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u64 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
new file mode 100644
index 000000000..321e8f8dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQp8_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQp8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQp8_u8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_poly8x16_t = vreinterpretq_p8_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
new file mode 100644
index 000000000..08d6b6afc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_f32 (void)
+{
+  int16x8_t out_int16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
new file mode 100644
index 000000000..77bfe3882
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p128 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_int16x8_t = vreinterpretq_s16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
new file mode 100644
index 000000000..1505b725e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p16 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int16x8_t = vreinterpretq_s16_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
new file mode 100644
index 000000000..41890f32a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p64 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
new file mode 100644
index 000000000..48c54f212
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_p8 (void)
+{
+  int16x8_t out_int16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
new file mode 100644
index 000000000..15f54fa94
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s32 (void)
+{
+  int16x8_t out_int16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
new file mode 100644
index 000000000..eb8e53516
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s64 (void)
+{
+  int16x8_t out_int16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
new file mode 100644
index 000000000..f353c9268
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_s8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
new file mode 100644
index 000000000..8ea96b7b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u16 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int16x8_t = vreinterpretq_s16_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
new file mode 100644
index 000000000..ac571b126
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u32 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int16x8_t = vreinterpretq_s16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
new file mode 100644
index 000000000..73959abd9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u64 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int16x8_t = vreinterpretq_s16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
new file mode 100644
index 000000000..45e85b131
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs16_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs16_u8 (void)
+{
+  int16x8_t out_int16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int16x8_t = vreinterpretq_s16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
new file mode 100644
index 000000000..795db0753
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_f32 (void)
+{
+  int32x4_t out_int32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int32x4_t = vreinterpretq_s32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
new file mode 100644
index 000000000..9a179ae3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p128 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_int32x4_t = vreinterpretq_s32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
new file mode 100644
index 000000000..473c12350
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p16 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
new file mode 100644
index 000000000..cc7ad95ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p64 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
new file mode 100644
index 000000000..819e1d122
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_p8 (void)
+{
+  int32x4_t out_int32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
new file mode 100644
index 000000000..7d2b5a0b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
new file mode 100644
index 000000000..8116033e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s64 (void)
+{
+  int32x4_t out_int32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
new file mode 100644
index 000000000..6786ddbfd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_s8 (void)
+{
+  int32x4_t out_int32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
new file mode 100644
index 000000000..104e22d68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u16 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int32x4_t = vreinterpretq_s32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
new file mode 100644
index 000000000..8385fd8a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u32 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int32x4_t = vreinterpretq_s32_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
new file mode 100644
index 000000000..90b91a74a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u64 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int32x4_t = vreinterpretq_s32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
new file mode 100644
index 000000000..60ad32a44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs32_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs32_u8 (void)
+{
+  int32x4_t out_int32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int32x4_t = vreinterpretq_s32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
new file mode 100644
index 000000000..212005fab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_f32 (void)
+{
+  int64x2_t out_int64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
new file mode 100644
index 000000000..adc1b9bbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p128 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_int64x2_t = vreinterpretq_s64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
new file mode 100644
index 000000000..0003a1f72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p16 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
new file mode 100644
index 000000000..89ab9ccb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p64 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int64x2_t = vreinterpretq_s64_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
new file mode 100644
index 000000000..02d7174b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_p8 (void)
+{
+  int64x2_t out_int64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
new file mode 100644
index 000000000..26350eeb8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s16 (void)
+{
+  int64x2_t out_int64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
new file mode 100644
index 000000000..471db5cc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
new file mode 100644
index 000000000..903be8ff6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_s8 (void)
+{
+  int64x2_t out_int64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
new file mode 100644
index 000000000..cbb49098f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u16 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int64x2_t = vreinterpretq_s64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
new file mode 100644
index 000000000..882cf77bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u32 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int64x2_t = vreinterpretq_s64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
new file mode 100644
index 000000000..f9bc43ae4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u64 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int64x2_t = vreinterpretq_s64_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
new file mode 100644
index 000000000..3af2f0138
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs64_u8 (void)
+{
+  int64x2_t out_int64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int64x2_t = vreinterpretq_s64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
new file mode 100644
index 000000000..6a31442cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_f32 (void)
+{
+  int8x16_t out_int8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
new file mode 100644
index 000000000..d94090068
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p128 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_int8x16_t = vreinterpretq_s8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
new file mode 100644
index 000000000..6491c795a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p16 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
new file mode 100644
index 000000000..a9adec387
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p64 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
new file mode 100644
index 000000000..914321d55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_p8 (void)
+{
+  int8x16_t out_int8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_int8x16_t = vreinterpretq_s8_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
new file mode 100644
index 000000000..fee5e2723
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s16 (void)
+{
+  int8x16_t out_int8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
new file mode 100644
index 000000000..2bf941aa5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s32 (void)
+{
+  int8x16_t out_int8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
new file mode 100644
index 000000000..1e6557174
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_s64 (void)
+{
+  int8x16_t out_int8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
new file mode 100644
index 000000000..84b86eaae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u16 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_int8x16_t = vreinterpretq_s8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
new file mode 100644
index 000000000..e5f85ccd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u32 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_int8x16_t = vreinterpretq_s8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
new file mode 100644
index 000000000..9f299b366
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u64 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_int8x16_t = vreinterpretq_s8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
new file mode 100644
index 000000000..f04a53733
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQs8_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQs8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQs8_u8 (void)
+{
+  int8x16_t out_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_int8x16_t = vreinterpretq_s8_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
new file mode 100644
index 000000000..cb4a2e502
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_f32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
new file mode 100644
index 000000000..792609246
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p128 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
new file mode 100644
index 000000000..5667d60c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
new file mode 100644
index 000000000..7a9b538f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
new file mode 100644
index 000000000..d45442d9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_p8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
new file mode 100644
index 000000000..9b6615909
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
new file mode 100644
index 000000000..9a6d0f44a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
new file mode 100644
index 000000000..c5a5378e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
new file mode 100644
index 000000000..4ca22dceb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_s8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
new file mode 100644
index 000000000..516c94957
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u32 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
new file mode 100644
index 000000000..816da82c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u64 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
new file mode 100644
index 000000000..ac5e98fa8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu16_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu16_u8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint16x8_t = vreinterpretq_u16_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
new file mode 100644
index 000000000..7453f24b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_f32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint32x4_t = vreinterpretq_u32_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
new file mode 100644
index 000000000..ce716b0ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p128 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
new file mode 100644
index 000000000..27989c53c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
new file mode 100644
index 000000000..a8b709e02
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
new file mode 100644
index 000000000..2b3e01843
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_p8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
new file mode 100644
index 000000000..3a6f20f0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
new file mode 100644
index 000000000..3079729aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
new file mode 100644
index 000000000..927cd3a60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
new file mode 100644
index 000000000..5b546ccac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_s8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
new file mode 100644
index 000000000..055739e8e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
new file mode 100644
index 000000000..ddf51f8ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u64 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
new file mode 100644
index 000000000..2f860c193
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu32_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu32_u8 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint32x4_t = vreinterpretq_u32_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
new file mode 100644
index 000000000..5224dcf87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_f32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
new file mode 100644
index 000000000..789973e0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p128 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
new file mode 100644
index 000000000..fc592b78d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
new file mode 100644
index 000000000..38071503e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
new file mode 100644
index 000000000..503c44393
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_p8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
new file mode 100644
index 000000000..430694abc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
new file mode 100644
index 000000000..acfc69e74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
new file mode 100644
index 000000000..033c6516e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
new file mode 100644
index 000000000..b6c312fbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_s8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
new file mode 100644
index 000000000..dbe9d5160
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u16 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
new file mode 100644
index 000000000..58b3c67e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
new file mode 100644
index 000000000..c20fef185
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu64_u8 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint64x2_t = vreinterpretq_u64_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
new file mode 100644
index 000000000..f7b470415
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_f32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
new file mode 100644
index 000000000..54a832cf4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p128.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_p128' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p128 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly128_t arg0_poly128_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p128 (arg0_poly128_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
new file mode 100644
index 000000000..758f10bea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
new file mode 100644
index 000000000..3336e6c24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly64x2_t arg0_poly64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p64 (arg0_poly64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
new file mode 100644
index 000000000..29f2aa19e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_p8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_uint8x16_t = vreinterpretq_u8_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
new file mode 100644
index 000000000..1d79abb9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
new file mode 100644
index 000000000..9f7c4f2f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
new file mode 100644
index 000000000..a01fb1d1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s64 (arg0_int64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
new file mode 100644
index 000000000..0d65f31d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_s8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_uint8x16_t = vreinterpretq_u8_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
new file mode 100644
index 000000000..dd9306192
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u16 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
new file mode 100644
index 000000000..30f4b4559
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u32 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
new file mode 100644
index 000000000..3f04c7192
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretQu8_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretQu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretQu8_u64 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint8x16_t = vreinterpretq_u8_u64 (arg0_uint64x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
new file mode 100644
index 000000000..92ede4949
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p16 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
new file mode 100644
index 000000000..e9714658f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p64 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
new file mode 100644
index 000000000..ee2e6a92e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_p8 (void)
+{
+  float32x2_t out_float32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
new file mode 100644
index 000000000..39ec36947
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s16 (void)
+{
+  float32x2_t out_float32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
new file mode 100644
index 000000000..008598f14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s32 (void)
+{
+  float32x2_t out_float32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_float32x2_t = vreinterpret_f32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
new file mode 100644
index 000000000..6a5ede493
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s64 (void)
+{
+  float32x2_t out_float32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
new file mode 100644
index 000000000..cc645e5d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_s8 (void)
+{
+  float32x2_t out_float32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
new file mode 100644
index 000000000..fbb96790f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u16 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_float32x2_t = vreinterpret_f32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
new file mode 100644
index 000000000..f87c885c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u32 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_float32x2_t = vreinterpret_f32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
new file mode 100644
index 000000000..610f77ad4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u64 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_float32x2_t = vreinterpret_f32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
new file mode 100644
index 000000000..bfd81b171
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretf32_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretf32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretf32_u8 (void)
+{
+  float32x2_t out_float32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_float32x2_t = vreinterpret_f32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
new file mode 100644
index 000000000..91508a6d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_f32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
new file mode 100644
index 000000000..4cd6818db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
new file mode 100644
index 000000000..a2f7207ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_p8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
new file mode 100644
index 000000000..3f22296cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly16x4_t = vreinterpret_p16_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
new file mode 100644
index 000000000..393246cca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
new file mode 100644
index 000000000..f5c99711a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
new file mode 100644
index 000000000..6cf01b280
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_s8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
new file mode 100644
index 000000000..4cdeeac44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly16x4_t = vreinterpret_p16_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
new file mode 100644
index 000000000..5b1094097
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u32 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly16x4_t = vreinterpret_p16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
new file mode 100644
index 000000000..b036ff475
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u64 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly16x4_t = vreinterpret_p16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
new file mode 100644
index 000000000..d165cafb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp16_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp16_u8 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly16x4_t = vreinterpret_p16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
new file mode 100644
index 000000000..d9ecd6f88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_f32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
new file mode 100644
index 000000000..db437279b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_p16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
new file mode 100644
index 000000000..1fb0131d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_p8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
new file mode 100644
index 000000000..528db2d57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
new file mode 100644
index 000000000..c6887d7e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
new file mode 100644
index 000000000..f2b041649
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly64x1_t = vreinterpret_p64_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
new file mode 100644
index 000000000..1866d19fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_s8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
new file mode 100644
index 000000000..7903ec26f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u16 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly64x1_t = vreinterpret_p64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
new file mode 100644
index 000000000..3d8e9e40f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u32 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly64x1_t = vreinterpret_p64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
new file mode 100644
index 000000000..caa0464aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly64x1_t = vreinterpret_p64_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
new file mode 100644
index 000000000..47e1dfa5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp64_u8 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly64x1_t = vreinterpret_p64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
new file mode 100644
index 000000000..b73599085
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_f32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
new file mode 100644
index 000000000..28a04a3e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
new file mode 100644
index 000000000..f5eff21ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_p64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
new file mode 100644
index 000000000..2a559c8d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
new file mode 100644
index 000000000..a3c627085
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
new file mode 100644
index 000000000..1a5cbbbcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
new file mode 100644
index 000000000..0f8af3e5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_s8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_poly8x8_t = vreinterpret_p8_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
new file mode 100644
index 000000000..f3cdaab48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u16 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_poly8x8_t = vreinterpret_p8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
new file mode 100644
index 000000000..210e063c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u32 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_poly8x8_t = vreinterpret_p8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
new file mode 100644
index 000000000..bf83e5df9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u64 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_poly8x8_t = vreinterpret_p8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
new file mode 100644
index 000000000..17d8d8c87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretp8_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretp8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretp8_u8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_poly8x8_t = vreinterpret_p8_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
new file mode 100644
index 000000000..380947bcc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_f32 (void)
+{
+  int16x4_t out_int16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
new file mode 100644
index 000000000..3742001b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p16 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int16x4_t = vreinterpret_s16_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
new file mode 100644
index 000000000..127865d16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p64 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
new file mode 100644
index 000000000..5970dc86c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_p8 (void)
+{
+  int16x4_t out_int16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
new file mode 100644
index 000000000..bee17e4c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
new file mode 100644
index 000000000..4a8feda9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s64 (void)
+{
+  int16x4_t out_int16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
new file mode 100644
index 000000000..e079c6158
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_s8 (void)
+{
+  int16x4_t out_int16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
new file mode 100644
index 000000000..cf86bd4a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u16 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int16x4_t = vreinterpret_s16_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
new file mode 100644
index 000000000..853e7ab2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u32 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int16x4_t = vreinterpret_s16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
new file mode 100644
index 000000000..a72786ded
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u64 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int16x4_t = vreinterpret_s16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
new file mode 100644
index 000000000..9c8459e46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets16_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets16_u8 (void)
+{
+  int16x4_t out_int16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int16x4_t = vreinterpret_s16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
new file mode 100644
index 000000000..73fe251e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_f32 (void)
+{
+  int32x2_t out_int32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int32x2_t = vreinterpret_s32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
new file mode 100644
index 000000000..36df97c5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p16 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
new file mode 100644
index 000000000..f8be30b92
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p64 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
new file mode 100644
index 000000000..54e9dee78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_p8 (void)
+{
+  int32x2_t out_int32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
new file mode 100644
index 000000000..f5e3fb6fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s16 (void)
+{
+  int32x2_t out_int32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
new file mode 100644
index 000000000..f1430843f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
new file mode 100644
index 000000000..a336577d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_s8 (void)
+{
+  int32x2_t out_int32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
new file mode 100644
index 000000000..2f078613e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u16 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int32x2_t = vreinterpret_s32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
new file mode 100644
index 000000000..4087e9c78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u32 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int32x2_t = vreinterpret_s32_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
new file mode 100644
index 000000000..826bb8efb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u64 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int32x2_t = vreinterpret_s32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
new file mode 100644
index 000000000..31589a8a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets32_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets32_u8 (void)
+{
+  int32x2_t out_int32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int32x2_t = vreinterpret_s32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
new file mode 100644
index 000000000..0096e368a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_f32 (void)
+{
+  int64x1_t out_int64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
new file mode 100644
index 000000000..bdbe4302f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p16 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
new file mode 100644
index 000000000..5f7c17bd3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p64 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int64x1_t = vreinterpret_s64_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
new file mode 100644
index 000000000..76da59f39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_p8 (void)
+{
+  int64x1_t out_int64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
new file mode 100644
index 000000000..0f978f390
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s16 (void)
+{
+  int64x1_t out_int64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
new file mode 100644
index 000000000..aefa689a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s32 (void)
+{
+  int64x1_t out_int64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
new file mode 100644
index 000000000..a7e0adad9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_s8 (void)
+{
+  int64x1_t out_int64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
new file mode 100644
index 000000000..110818567
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u16 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int64x1_t = vreinterpret_s64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
new file mode 100644
index 000000000..978a6e480
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u32 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int64x1_t = vreinterpret_s64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
new file mode 100644
index 000000000..0546f26dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u64 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int64x1_t = vreinterpret_s64_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
new file mode 100644
index 000000000..601b5988d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets64_u8 (void)
+{
+  int64x1_t out_int64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int64x1_t = vreinterpret_s64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
new file mode 100644
index 000000000..05d921d7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_f32 (void)
+{
+  int8x8_t out_int8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
new file mode 100644
index 000000000..38e812a16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p16 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
new file mode 100644
index 000000000..8345963ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p64 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
new file mode 100644
index 000000000..402484411
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_p8 (void)
+{
+  int8x8_t out_int8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
new file mode 100644
index 000000000..df368e370
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
new file mode 100644
index 000000000..caefc38dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s32 (void)
+{
+  int8x8_t out_int8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
new file mode 100644
index 000000000..a8c7c333e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_s64 (void)
+{
+  int8x8_t out_int8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
new file mode 100644
index 000000000..dbd1eec43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u16 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_int8x8_t = vreinterpret_s8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
new file mode 100644
index 000000000..40e1475ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u32 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_int8x8_t = vreinterpret_s8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
new file mode 100644
index 000000000..6d53d41e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u64 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_int8x8_t = vreinterpret_s8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
new file mode 100644
index 000000000..8f31a4c76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterprets8_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterprets8_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterprets8_u8 (void)
+{
+  int8x8_t out_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_int8x8_t = vreinterpret_s8_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
new file mode 100644
index 000000000..f960624d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_f32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
new file mode 100644
index 000000000..e787a969e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
new file mode 100644
index 000000000..34f920bbd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
new file mode 100644
index 000000000..c332e9450
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_p8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
new file mode 100644
index 000000000..d72ec3452
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint16x4_t = vreinterpret_u16_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
new file mode 100644
index 000000000..b6d86c011
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
new file mode 100644
index 000000000..87f494bec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
new file mode 100644
index 000000000..11695c169
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_s8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
new file mode 100644
index 000000000..9f0171a05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint16x4_t = vreinterpret_u16_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
new file mode 100644
index 000000000..0db76c692
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u64 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint16x4_t = vreinterpret_u16_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
new file mode 100644
index 000000000..71b555ac5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu16_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu16_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu16_u8 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x4_t = vreinterpret_u16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
new file mode 100644
index 000000000..813b8b961
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_f32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
new file mode 100644
index 000000000..3662cc3cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
new file mode 100644
index 000000000..b5f24fbc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
new file mode 100644
index 000000000..73ddff115
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_p8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
new file mode 100644
index 000000000..02ec84c91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
new file mode 100644
index 000000000..2a964c830
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint32x2_t = vreinterpret_u32_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
new file mode 100644
index 000000000..ad9493856
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
new file mode 100644
index 000000000..8ff896e70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_s8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
new file mode 100644
index 000000000..5c4883422
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u16 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x2_t = vreinterpret_u32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
new file mode 100644
index 000000000..8fd55f24b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint32x2_t = vreinterpret_u32_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
new file mode 100644
index 000000000..ab192091d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu32_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu32_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu32_u8 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint32x2_t = vreinterpret_u32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
new file mode 100644
index 000000000..7ded8687a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_f32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
new file mode 100644
index 000000000..c48213439
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
new file mode 100644
index 000000000..741912a4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
new file mode 100644
index 000000000..858af4624
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_p8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
new file mode 100644
index 000000000..e07c4e83e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
new file mode 100644
index 000000000..0fa51a1a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
new file mode 100644
index 000000000..1f1f62e43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint64x1_t = vreinterpret_u64_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
new file mode 100644
index 000000000..299b45ce5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_s8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
new file mode 100644
index 000000000..dd2c1550d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u16 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint64x1_t = vreinterpret_u64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
new file mode 100644
index 000000000..8dbe9e200
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u32 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x1_t = vreinterpret_u64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
new file mode 100644
index 000000000..fe0724a8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu64_u8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu64_u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu64_u8 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint64x1_t = vreinterpret_u64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
new file mode 100644
index 000000000..e82cba753
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_f32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_f32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
new file mode 100644
index 000000000..08516125c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
new file mode 100644
index 000000000..907b67c15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly64x1_t arg0_poly64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_p64 (arg0_poly64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
new file mode 100644
index 000000000..91d3d0eaa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_p8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_p8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
new file mode 100644
index 000000000..50a2cd187
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
new file mode 100644
index 000000000..a5db01b62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
new file mode 100644
index 000000000..f906e018b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_s64 (arg0_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
new file mode 100644
index 000000000..bd2ba481f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_s8.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_s8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_uint8x8_t = vreinterpret_u8_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
new file mode 100644
index 000000000..eb38ca82f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u16.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint8x8_t = vreinterpret_u8_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
new file mode 100644
index 000000000..6fb11b26f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u32.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u32 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint8x8_t = vreinterpret_u8_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
new file mode 100644
index 000000000..cf7ff27ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vreinterpretu8_u64.c
@@ -0,0 +1,19 @@
+/* Test the `vreinterpretu8_u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vreinterpretu8_u64 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint8x8_t = vreinterpret_u8_u64 (arg0_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
new file mode 100644
index 000000000..b815c199f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev16Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev16q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
new file mode 100644
index 000000000..7167fec30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev16Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev16q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
new file mode 100644
index 000000000..d43613079
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev16Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev16q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
new file mode 100644
index 000000000..15086d584
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16p8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev16p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev16_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
new file mode 100644
index 000000000..b2c7ca88e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16s8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev16s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev16_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
new file mode 100644
index 000000000..10ba66f7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev16u8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev16u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev16u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev16_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev16\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
new file mode 100644
index 000000000..af213d91e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev32q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
new file mode 100644
index 000000000..926068f10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev32q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
new file mode 100644
index 000000000..bfd8ec2e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev32q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
new file mode 100644
index 000000000..74fc2470d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev32q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
new file mode 100644
index 000000000..cf0220a86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev32q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
new file mode 100644
index 000000000..ad5dba31c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev32q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
new file mode 100644
index 000000000..93f19405e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev32_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
new file mode 100644
index 000000000..b19ce01c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32p8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev32_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
new file mode 100644
index 000000000..08bf6f258
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev32_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
new file mode 100644
index 000000000..47b8a591d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32s8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev32_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
new file mode 100644
index 000000000..928c1d45c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev32_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
new file mode 100644
index 000000000..ac5c63690
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev32u8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev32u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev32u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev32_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev32\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
new file mode 100644
index 000000000..c9ab7008d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrev64q_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
new file mode 100644
index 000000000..2d5d2f86b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+
+  out_poly16x8_t = vrev64q_p16 (arg0_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
new file mode 100644
index 000000000..019b6d419
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qp8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+
+  out_poly8x16_t = vrev64q_p8 (arg0_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
new file mode 100644
index 000000000..5923b2d2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vrev64q_s16 (arg0_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
new file mode 100644
index 000000000..93ffd5818
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vrev64q_s32 (arg0_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
new file mode 100644
index 000000000..9353e7057
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vrev64q_s8 (arg0_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
new file mode 100644
index 000000000..590d833fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vrev64q_u16 (arg0_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
new file mode 100644
index 000000000..014da6812
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrev64q_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
new file mode 100644
index 000000000..4b7d8e495
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64Qu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vrev64q_u8 (arg0_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
new file mode 100644
index 000000000..3ea280e90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64f32.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64f32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrev64_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
new file mode 100644
index 000000000..1b30d60e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64p16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+
+  out_poly16x4_t = vrev64_p16 (arg0_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
new file mode 100644
index 000000000..370f49854
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64p8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+
+  out_poly8x8_t = vrev64_p8 (arg0_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
new file mode 100644
index 000000000..ee4206ba7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64s16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vrev64_s16 (arg0_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
new file mode 100644
index 000000000..f7057ce49
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s32.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64s32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vrev64_s32 (arg0_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
new file mode 100644
index 000000000..c073b0b68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64s8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vrev64_s8 (arg0_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
new file mode 100644
index 000000000..4fdd2697c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u16.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64u16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vrev64_u16 (arg0_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
new file mode 100644
index 000000000..61d21b69d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u32.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64u32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrev64_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
new file mode 100644
index 000000000..71a6af177
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrev64u8.c
@@ -0,0 +1,20 @@
+/* Test the `vrev64u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrev64u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vrev64_u8 (arg0_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vrev64\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c
new file mode 100644
index 000000000..02ca46509
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndaf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndaf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrnda_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrinta\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c
new file mode 100644
index 000000000..b94165735
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrnd_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrintz\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c
new file mode 100644
index 000000000..7f4e90bf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndmf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndmf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndmf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrndm_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrintm\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c
new file mode 100644
index 000000000..df8e3e934
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndnf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndnf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndnf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrndn_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrintn\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c
new file mode 100644
index 000000000..d3900cd78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndpf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndpf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndpf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrndp_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrintp\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c
new file mode 100644
index 000000000..b7b5d73c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndqaf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndqaf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndqa_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrinta\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c
new file mode 100644
index 000000000..08b4b45f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndqf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndqf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrintz\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c
new file mode 100644
index 000000000..6d16bfc93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndqmf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndqmf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndqm_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrintm\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c
new file mode 100644
index 000000000..b31ca95db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndqnf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndqnf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndqn_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrintn\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c
new file mode 100644
index 000000000..5c4a86690
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrndqpf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_v8_neon } */
+
+#include "arm_neon.h"
+
+void test_vrndqpf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrndqp_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrintp\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
new file mode 100644
index 000000000..05b92b0aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQf32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrteQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+
+  out_float32x4_t = vrsqrteq_f32 (arg0_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
new file mode 100644
index 000000000..5d51dec60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteQu32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrteQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vrsqrteq_u32 (arg0_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
new file mode 100644
index 000000000..6e1bf7532
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtef32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrtef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+
+  out_float32x2_t = vrsqrte_f32 (arg0_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
new file mode 100644
index 000000000..1e4908e46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrteu32.c
@@ -0,0 +1,20 @@
+/* Test the `vrsqrteu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrteu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vrsqrte_u32 (arg0_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrte\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
new file mode 100644
index 000000000..ee38e04fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vrsqrtsQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vrsqrtsq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
new file mode 100644
index 000000000..36cb69def
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vrsqrtsf32.c
@@ -0,0 +1,21 @@
+/* Test the `vrsqrtsf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vrsqrtsf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vrsqrts_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vrsqrts\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
new file mode 100644
index 000000000..c6b18495e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanef32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32_t arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
new file mode 100644
index 000000000..dda571aaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16_t arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
new file mode 100644
index 000000000..873c8cfe4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanep8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8_t arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
new file mode 100644
index 000000000..f6ade301c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16_t arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
new file mode 100644
index 000000000..c825da15e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32_t arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
new file mode 100644
index 000000000..af8f2853c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes64.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64_t arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsetq_lane_s64 (arg0_int64_t, arg1_int64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
new file mode 100644
index 000000000..55dca359b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_lanes8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8_t arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
new file mode 100644
index 000000000..f671e1e4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16_t arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
new file mode 100644
index 000000000..27a0f7225
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32_t arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
new file mode 100644
index 000000000..b30b26748
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64_t arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsetq_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 0);
+}
+
+/* { dg-final { scan-assembler "vmov\[ 	\]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
new file mode 100644
index 000000000..d6e5817d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsetQ_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsetQ_laneu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8_t arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
new file mode 100644
index 000000000..340614cd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
@@ -0,0 +1,21 @@
+/* Test the `vset_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanef32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32_t arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
new file mode 100644
index 000000000..d02118a25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
@@ -0,0 +1,21 @@
+/* Test the `vset_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16_t arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
new file mode 100644
index 000000000..e63a197df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
@@ -0,0 +1,21 @@
+/* Test the `vset_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanep8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8_t arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
new file mode 100644
index 000000000..6f4f4d379
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
@@ -0,0 +1,21 @@
+/* Test the `vset_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16_t arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
new file mode 100644
index 000000000..77c22056b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
@@ -0,0 +1,21 @@
+/* Test the `vset_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32_t arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
new file mode 100644
index 000000000..5c5454f98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vset_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64_t arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
new file mode 100644
index 000000000..fd09e21d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
@@ -0,0 +1,21 @@
+/* Test the `vset_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_lanes8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8_t arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
new file mode 100644
index 000000000..783cc82c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
@@ -0,0 +1,21 @@
+/* Test the `vset_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16_t arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
new file mode 100644
index 000000000..0d5a89ec1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
@@ -0,0 +1,21 @@
+/* Test the `vset_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32_t arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
new file mode 100644
index 000000000..3bff5d232
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vset_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64_t arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
new file mode 100644
index 000000000..0e4853190
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
@@ -0,0 +1,21 @@
+/* Test the `vset_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vset_laneu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8_t arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
new file mode 100644
index 000000000..31344a6e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshlq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
new file mode 100644
index 000000000..dd11cd54b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshlq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
new file mode 100644
index 000000000..2fdbc0d01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshlq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
new file mode 100644
index 000000000..078ffd41b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshlq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
new file mode 100644
index 000000000..a330ae3d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshlq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
new file mode 100644
index 000000000..cdf26269a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshlq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
new file mode 100644
index 000000000..70fe6ccf1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshlq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
new file mode 100644
index 000000000..06e6b52d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshlQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshlq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
new file mode 100644
index 000000000..ed3d4a4a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vshlQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vshlq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
new file mode 100644
index 000000000..6413ef8d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vshlQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vshlq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
new file mode 100644
index 000000000..8dc0bd470
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vshlQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vshlq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
new file mode 100644
index 000000000..58a6dbb97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vshlQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vshlq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
new file mode 100644
index 000000000..584ef1270
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vshlQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vshlq_u16 (arg0_uint16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
new file mode 100644
index 000000000..77e6e0160
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vshlQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vshlq_u32 (arg0_uint32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
new file mode 100644
index 000000000..6138ad3dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vshlQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_uint64x2_t = vshlq_u64 (arg0_uint64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
new file mode 100644
index 000000000..65bfdb1d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vshlQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vshlq_u8 (arg0_uint8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
new file mode 100644
index 000000000..59a91bdec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vshl_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshl_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
new file mode 100644
index 000000000..66f4c3119
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vshl_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshl_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
new file mode 100644
index 000000000..f7a49f4bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vshl_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshl_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
new file mode 100644
index 000000000..634e66739
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vshl_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshl_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
new file mode 100644
index 000000000..7d71f84f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshl_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshl_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
new file mode 100644
index 000000000..ae1f85ae9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshl_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshl_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
new file mode 100644
index 000000000..c4e11a18b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshl_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshl_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
new file mode 100644
index 000000000..12378ebfe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshl_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshl_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshl_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshl_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshl\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
new file mode 100644
index 000000000..cc2c7d5f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vshll_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int32x4_t = vshll_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
new file mode 100644
index 000000000..6591e42c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vshll_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int64x2_t = vshll_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
new file mode 100644
index 000000000..94d904506
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vshll_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_ns8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int16x8_t = vshll_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
new file mode 100644
index 000000000..eabc7928c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshll_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint32x4_t = vshll_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
new file mode 100644
index 000000000..f205caf00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshll_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint64x2_t = vshll_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
new file mode 100644
index 000000000..bf8240fde
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshll_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshll_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshll_nu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint16x8_t = vshll_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshll\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c
new file mode 100644
index 000000000..2c8941f9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls16.c
@@ -0,0 +1,21 @@
+/* Test the `vshls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshls16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vshl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c
new file mode 100644
index 000000000..fb6be6ea0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls32.c
@@ -0,0 +1,21 @@
+/* Test the `vshls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshls32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vshl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c
new file mode 100644
index 000000000..b5a61033f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls64.c
@@ -0,0 +1,21 @@
+/* Test the `vshls64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshls64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vshl_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c
new file mode 100644
index 000000000..a807191ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshls8.c
@@ -0,0 +1,21 @@
+/* Test the `vshls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshls8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vshl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
new file mode 100644
index 000000000..14f2428d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu16.c
@@ -0,0 +1,21 @@
+/* Test the `vshlu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vshl_u16 (arg0_uint16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
new file mode 100644
index 000000000..596327584
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu32.c
@@ -0,0 +1,21 @@
+/* Test the `vshlu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vshl_u32 (arg0_uint32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
new file mode 100644
index 000000000..f29dedc14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu64.c
@@ -0,0 +1,21 @@
+/* Test the `vshlu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_uint64x1_t = vshl_u64 (arg0_uint64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
new file mode 100644
index 000000000..1b900396b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshlu8.c
@@ -0,0 +1,21 @@
+/* Test the `vshlu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshlu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vshl_u8 (arg0_uint8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vshl\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
new file mode 100644
index 000000000..286edb14b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vshrQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int16x8_t = vshrq_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
new file mode 100644
index 000000000..d47d574e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vshrQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int32x4_t = vshrq_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
new file mode 100644
index 000000000..66b693e73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vshrQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int64x2_t = vshrq_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
new file mode 100644
index 000000000..f92da931d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vshrQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+
+  out_int8x16_t = vshrq_n_s8 (arg0_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
new file mode 100644
index 000000000..8f81e7896
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshrQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint16x8_t = vshrq_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
new file mode 100644
index 000000000..e5fbf44f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshrQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint32x4_t = vshrq_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
new file mode 100644
index 000000000..a8ff5f7d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshrQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint64x2_t = vshrq_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
new file mode 100644
index 000000000..673d90e4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrQ_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshrQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+
+  out_uint8x16_t = vshrq_n_u8 (arg0_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
new file mode 100644
index 000000000..0a14a00df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vshr_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+
+  out_int16x4_t = vshr_n_s16 (arg0_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
new file mode 100644
index 000000000..545478909
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vshr_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+
+  out_int32x2_t = vshr_n_s32 (arg0_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
new file mode 100644
index 000000000..3fd27fc98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vshr_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+
+  out_int64x1_t = vshr_n_s64 (arg0_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
new file mode 100644
index 000000000..069978d47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_ns8.c
@@ -0,0 +1,20 @@
+/* Test the `vshr_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+
+  out_int8x8_t = vshr_n_s8 (arg0_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
new file mode 100644
index 000000000..43c610b62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshr_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+
+  out_uint16x4_t = vshr_n_u16 (arg0_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
new file mode 100644
index 000000000..1b7bb5d33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshr_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+
+  out_uint32x2_t = vshr_n_u32 (arg0_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
new file mode 100644
index 000000000..a78b9fcf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshr_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+
+  out_uint64x1_t = vshr_n_u64 (arg0_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
new file mode 100644
index 000000000..cdb968693
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshr_nu8.c
@@ -0,0 +1,20 @@
+/* Test the `vshr_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshr_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+
+  out_uint8x8_t = vshr_n_u8 (arg0_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshr\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
new file mode 100644
index 000000000..832dc831a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns16.c
@@ -0,0 +1,20 @@
+/* Test the `vshrn_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+
+  out_int8x8_t = vshrn_n_s16 (arg0_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
new file mode 100644
index 000000000..314ba2516
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns32.c
@@ -0,0 +1,20 @@
+/* Test the `vshrn_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+
+  out_int16x4_t = vshrn_n_s32 (arg0_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
new file mode 100644
index 000000000..465592a65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vshrn_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_ns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+
+  out_int32x2_t = vshrn_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
new file mode 100644
index 000000000..614451a68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu16.c
@@ -0,0 +1,20 @@
+/* Test the `vshrn_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+
+  out_uint8x8_t = vshrn_n_u16 (arg0_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
new file mode 100644
index 000000000..6fe4066ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu32.c
@@ -0,0 +1,20 @@
+/* Test the `vshrn_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+
+  out_uint16x4_t = vshrn_n_u32 (arg0_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
new file mode 100644
index 000000000..901b17c31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vshrn_nu64.c
@@ -0,0 +1,20 @@
+/* Test the `vshrn_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vshrn_nu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+
+  out_uint32x2_t = vshrn_n_u64 (arg0_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vshrn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
new file mode 100644
index 000000000..601ee13c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np16.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsliq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
new file mode 100644
index 000000000..cbb47285e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vsliq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
new file mode 100644
index 000000000..8e5a256e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_np8.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsliq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
new file mode 100644
index 000000000..d3c67ac77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsliq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
new file mode 100644
index 000000000..12b69848f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsliq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
new file mode 100644
index 000000000..441996f8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns64.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsliq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
new file mode 100644
index 000000000..8f393b4c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_ns8.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsliq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
new file mode 100644
index 000000000..0936eb759
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsliq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
new file mode 100644
index 000000000..23b1dddcf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsliq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
new file mode 100644
index 000000000..b14a16592
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsliq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
new file mode 100644
index 000000000..d6a86a6e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsliQ_nu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsliQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsliQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsliq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
new file mode 100644
index 000000000..30d206e79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np16.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsli_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
new file mode 100644
index 000000000..801add49b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsli_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vsli_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
new file mode 100644
index 000000000..ffcacb25b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_np8.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsli_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
new file mode 100644
index 000000000..1d58cc7ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsli_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
new file mode 100644
index 000000000..1920c9115
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsli_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
new file mode 100644
index 000000000..4bef7bc91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns64.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsli_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
new file mode 100644
index 000000000..7b0260f4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_ns8.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsli_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
new file mode 100644
index 000000000..addda9c20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsli_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
new file mode 100644
index 000000000..0bdaef3a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsli_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
new file mode 100644
index 000000000..3733d7055
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsli_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
new file mode 100644
index 000000000..020e5959b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsli_nu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsli_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsli_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsli_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsli\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
new file mode 100644
index 000000000..d1f6100e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vsraQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsraq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
new file mode 100644
index 000000000..9d44cca6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vsraQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsraq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
new file mode 100644
index 000000000..bcda76849
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns64.c
@@ -0,0 +1,21 @@
+/* Test the `vsraQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsraq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
new file mode 100644
index 000000000..0dbf181c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_ns8.c
@@ -0,0 +1,21 @@
+/* Test the `vsraQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsraq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
new file mode 100644
index 000000000..4b6553314
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsraQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsraq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
new file mode 100644
index 000000000..721459583
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsraQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsraq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
new file mode 100644
index 000000000..8a982d205
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsraQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsraq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
new file mode 100644
index 000000000..523e5a09b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsraQ_nu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsraQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsraQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsraq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
new file mode 100644
index 000000000..37c97c562
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vsra_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsra_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
new file mode 100644
index 000000000..e79430804
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vsra_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsra_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
new file mode 100644
index 000000000..6381a13e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns64.c
@@ -0,0 +1,21 @@
+/* Test the `vsra_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsra_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
new file mode 100644
index 000000000..6f46eef22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_ns8.c
@@ -0,0 +1,21 @@
+/* Test the `vsra_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsra_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
new file mode 100644
index 000000000..42ad77321
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsra_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsra_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
new file mode 100644
index 000000000..baaab7e48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsra_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsra_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
new file mode 100644
index 000000000..dc63a5ad9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsra_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsra_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
new file mode 100644
index 000000000..5555f75d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsra_nu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsra_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsra_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsra_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsra\.u8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
new file mode 100644
index 000000000..39a96c080
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np16.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np16 (void)
+{
+  poly16x8_t out_poly16x8_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8_t = vsriq_n_p16 (arg0_poly16x8_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
new file mode 100644
index 000000000..d2e48165a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np64 (void)
+{
+  poly64x2_t out_poly64x2_t;
+  poly64x2_t arg0_poly64x2_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  out_poly64x2_t = vsriq_n_p64 (arg0_poly64x2_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
new file mode 100644
index 000000000..d17d7e724
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_np8.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_np8 (void)
+{
+  poly8x16_t out_poly8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16_t = vsriq_n_p8 (arg0_poly8x16_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
new file mode 100644
index 000000000..c7375409c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsriq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
new file mode 100644
index 000000000..1b17696aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsriq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
new file mode 100644
index 000000000..d959c341b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns64.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsriq_n_s64 (arg0_int64x2_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
new file mode 100644
index 000000000..b04c800cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_ns8.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_ns8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsriq_n_s8 (arg0_int8x16_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
new file mode 100644
index 000000000..2d3f1d6b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsriq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
new file mode 100644
index 000000000..19c87fec7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsriq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
new file mode 100644
index 000000000..b747b2237
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsriq_n_u64 (arg0_uint64x2_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
new file mode 100644
index 000000000..1e949e5e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsriQ_nu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsriQ_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsriQ_nu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsriq_n_u8 (arg0_uint8x16_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
new file mode 100644
index 000000000..a1aac08f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np16.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_np16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_np16 (void)
+{
+  poly16x4_t out_poly16x4_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4_t = vsri_n_p16 (arg0_poly16x4_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
new file mode 100644
index 000000000..0abffc2e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np64.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_np64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vsri_np64 (void)
+{
+  poly64x1_t out_poly64x1_t;
+  poly64x1_t arg0_poly64x1_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  out_poly64x1_t = vsri_n_p64 (arg0_poly64x1_t, arg1_poly64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
new file mode 100644
index 000000000..bd102bf98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_np8.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_np8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_np8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8_t = vsri_n_p8 (arg0_poly8x8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
new file mode 100644
index 000000000..bb0687220
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns16.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_ns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsri_n_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
new file mode 100644
index 000000000..8712857ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns32.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_ns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsri_n_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
new file mode 100644
index 000000000..f54fca4dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns64.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_ns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsri_n_s64 (arg0_int64x1_t, arg1_int64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
new file mode 100644
index 000000000..405e03522
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_ns8.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_ns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_ns8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsri_n_s8 (arg0_int8x8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
new file mode 100644
index 000000000..4c751e792
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_nu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsri_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
new file mode 100644
index 000000000..b82f63b59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_nu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsri_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
new file mode 100644
index 000000000..20381bfd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_nu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsri_n_u64 (arg0_uint64x1_t, arg1_uint64x1_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.64\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
new file mode 100644
index 000000000..87293317c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsri_nu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsri_nu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsri_nu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsri_n_u8 (arg0_uint8x8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vsri\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
new file mode 100644
index 000000000..1f95128e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
new file mode 100644
index 000000000..90e7ccc1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
new file mode 100644
index 000000000..74a198baf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  vst1q_lane_p64 (arg0_poly64_t, arg1_poly64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
new file mode 100644
index 000000000..6abb646c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
new file mode 100644
index 000000000..ec283e228
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
new file mode 100644
index 000000000..6e73d6e11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
new file mode 100644
index 000000000..46d369c99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_lane_s64 (arg0_int64_t, arg1_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
new file mode 100644
index 000000000..d7b3a1c12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
new file mode 100644
index 000000000..27958f6d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
new file mode 100644
index 000000000..b4aa760e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c
new file mode 100644
index 000000000..5f4c927b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c
@@ -0,0 +1,25 @@
+/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+
+/* Detect ICE in the case of unaligned memory address.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+unsigned char dummy_store[1000];
+
+void
+foo (char* addr)
+{
+  uint8x16_t vdata = vld1q_u8 (addr);
+  vst1q_lane_u64 ((uint64_t*) &dummy_store, vreinterpretq_u64_u8 (vdata), 0);
+}
+
+uint64_t
+bar (uint64x2_t vdata)
+{
+  vdata = vld1q_lane_u64 ((uint64_t*) &dummy_store, vdata, 0);
+  return vgetq_lane_u64 (vdata, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
new file mode 100644
index 000000000..54faaa3fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_lane_u64 (arg0_uint64_t, arg1_uint64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
new file mode 100644
index 000000000..9b09e72c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Q_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Q_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
new file mode 100644
index 000000000..a4b3d8a1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qf32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4_t arg1_float32x4_t;
+
+  vst1q_f32 (arg0_float32_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
new file mode 100644
index 000000000..9b4873371
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  vst1q_p16 (arg0_poly16_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
new file mode 100644
index 000000000..7d1e020f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qp64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x2_t arg1_poly64x2_t;
+
+  vst1q_p64 (arg0_poly64_t, arg1_poly64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
new file mode 100644
index 000000000..f3843399e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qp8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  vst1q_p8 (arg0_poly8_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
new file mode 100644
index 000000000..e6c39cf35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8_t arg1_int16x8_t;
+
+  vst1q_s16 (arg0_int16_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
new file mode 100644
index 000000000..587dcf0ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4_t arg1_int32x4_t;
+
+  vst1q_s32 (arg0_int32_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
new file mode 100644
index 000000000..50511d1ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x2_t arg1_int64x2_t;
+
+  vst1q_s64 (arg0_int64_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
new file mode 100644
index 000000000..2de9814b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qs8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16_t arg1_int8x16_t;
+
+  vst1q_s8 (arg0_int8_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
new file mode 100644
index 000000000..81d8cc5ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  vst1q_u16 (arg0_uint16_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
new file mode 100644
index 000000000..408c6b29e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  vst1q_u32 (arg0_uint32_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
new file mode 100644
index 000000000..1c17e5b0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  vst1q_u64 (arg0_uint64_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
new file mode 100644
index 000000000..1605e2756
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1Qu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  vst1q_u8 (arg0_uint8_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
new file mode 100644
index 000000000..781703140
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
new file mode 100644
index 000000000..c6a19daf2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
new file mode 100644
index 000000000..f8c70c359
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanep64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  vst1_lane_p64 (arg0_poly64_t, arg1_poly64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
new file mode 100644
index 000000000..1b5dd4f77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
new file mode 100644
index 000000000..4efdc5024
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
new file mode 100644
index 000000000..9c3c1354c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
new file mode 100644
index 000000000..64fed4a10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanes64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
new file mode 100644
index 000000000..59646f8a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
new file mode 100644
index 000000000..6ae716647
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
new file mode 100644
index 000000000..369abf7fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
new file mode 100644
index 000000000..7296fee8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_laneu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
new file mode 100644
index 000000000..ba6076e1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
new file mode 100644
index 000000000..f3460f5e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1f32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2_t arg1_float32x2_t;
+
+  vst1_f32 (arg0_float32_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
new file mode 100644
index 000000000..7504c5cf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  vst1_p16 (arg0_poly16_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
new file mode 100644
index 000000000..7329fba9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst1p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1_t arg1_poly64x1_t;
+
+  vst1_p64 (arg0_poly64_t, arg1_poly64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
new file mode 100644
index 000000000..3059aac60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1p8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  vst1_p8 (arg0_poly8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
new file mode 100644
index 000000000..fbddb2fd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4_t arg1_int16x4_t;
+
+  vst1_s16 (arg0_int16_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
new file mode 100644
index 000000000..f264db036
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2_t arg1_int32x2_t;
+
+  vst1_s32 (arg0_int32_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
new file mode 100644
index 000000000..64de48bb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1_t arg1_int64x1_t;
+
+  vst1_s64 (arg0_int64_t, arg1_int64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
new file mode 100644
index 000000000..7916448d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1s8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8_t arg1_int8x8_t;
+
+  vst1_s8 (arg0_int8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
new file mode 100644
index 000000000..797aef16f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u16.c
@@ -0,0 +1,20 @@
+/* Test the `vst1u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  vst1_u16 (arg0_uint16_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
new file mode 100644
index 000000000..563ea9dc3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u32.c
@@ -0,0 +1,20 @@
+/* Test the `vst1u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  vst1_u32 (arg0_uint32_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
new file mode 100644
index 000000000..b95f5d587
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u64.c
@@ -0,0 +1,20 @@
+/* Test the `vst1u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  vst1_u64 (arg0_uint64_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
new file mode 100644
index 000000000..75358e769
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst1u8.c
@@ -0,0 +1,20 @@
+/* Test the `vst1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst1u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  vst1_u8 (arg0_uint8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
new file mode 100644
index 000000000..485735632
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
new file mode 100644
index 000000000..bed15034c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
new file mode 100644
index 000000000..57867352f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
new file mode 100644
index 000000000..cf0dc15dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
new file mode 100644
index 000000000..b751e6b97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
new file mode 100644
index 000000000..b5fbe0e28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
new file mode 100644
index 000000000..56f9adcda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qf32.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x2_t arg1_float32x4x2_t;
+
+  vst2q_f32 (arg0_float32_t, arg1_float32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
new file mode 100644
index 000000000..184199033
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp16.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x2_t arg1_poly16x8x2_t;
+
+  vst2q_p16 (arg0_poly16_t, arg1_poly16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
new file mode 100644
index 000000000..2d98ec910
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qp8.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x2_t arg1_poly8x16x2_t;
+
+  vst2q_p8 (arg0_poly8_t, arg1_poly8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
new file mode 100644
index 000000000..39395f6d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs16.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x2_t arg1_int16x8x2_t;
+
+  vst2q_s16 (arg0_int16_t, arg1_int16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
new file mode 100644
index 000000000..1768d4786
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs32.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x2_t arg1_int32x4x2_t;
+
+  vst2q_s32 (arg0_int32_t, arg1_int32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
new file mode 100644
index 000000000..423cb8c8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qs8.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x2_t arg1_int8x16x2_t;
+
+  vst2q_s8 (arg0_int8_t, arg1_int8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
new file mode 100644
index 000000000..a25958a72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu16.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x2_t arg1_uint16x8x2_t;
+
+  vst2q_u16 (arg0_uint16_t, arg1_uint16x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
new file mode 100644
index 000000000..47722b352
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu32.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x2_t arg1_uint32x4x2_t;
+
+  vst2q_u32 (arg0_uint32_t, arg1_uint32x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
new file mode 100644
index 000000000..b79478026
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2Qu8.c
@@ -0,0 +1,21 @@
+/* Test the `vst2Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x2_t arg1_uint8x16x2_t;
+
+  vst2q_u8 (arg0_uint8_t, arg1_uint8x16x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
new file mode 100644
index 000000000..e7752920e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
new file mode 100644
index 000000000..be9913b39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
new file mode 100644
index 000000000..0a95e268d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
new file mode 100644
index 000000000..728593ccb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
new file mode 100644
index 000000000..32d49b58c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
new file mode 100644
index 000000000..9e67eb323
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
new file mode 100644
index 000000000..d56f20961
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
new file mode 100644
index 000000000..053704cea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
new file mode 100644
index 000000000..a35360088
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
new file mode 100644
index 000000000..b43c4135b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2f32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x2_t arg1_float32x2x2_t;
+
+  vst2_f32 (arg0_float32_t, arg1_float32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
new file mode 100644
index 000000000..1d112ff65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x2_t arg1_poly16x4x2_t;
+
+  vst2_p16 (arg0_poly16_t, arg1_poly16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
new file mode 100644
index 000000000..3ccaa5464
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst2p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst2p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x2_t arg1_poly64x1x2_t;
+
+  vst2_p64 (arg0_poly64_t, arg1_poly64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
new file mode 100644
index 000000000..59c4d62e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2p8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+
+  vst2_p8 (arg0_poly8_t, arg1_poly8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
new file mode 100644
index 000000000..eb6cb59a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x2_t arg1_int16x4x2_t;
+
+  vst2_s16 (arg0_int16_t, arg1_int16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
new file mode 100644
index 000000000..a17b58dc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x2_t arg1_int32x2x2_t;
+
+  vst2_s32 (arg0_int32_t, arg1_int32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
new file mode 100644
index 000000000..668ae50a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s64.c
@@ -0,0 +1,20 @@
+/* Test the `vst2s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x2_t arg1_int64x1x2_t;
+
+  vst2_s64 (arg0_int64_t, arg1_int64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
new file mode 100644
index 000000000..343414e34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2s8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+
+  vst2_s8 (arg0_int8_t, arg1_int8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
new file mode 100644
index 000000000..903279d0d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u16.c
@@ -0,0 +1,20 @@
+/* Test the `vst2u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x2_t arg1_uint16x4x2_t;
+
+  vst2_u16 (arg0_uint16_t, arg1_uint16x4x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
new file mode 100644
index 000000000..1396ed119
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u32.c
@@ -0,0 +1,20 @@
+/* Test the `vst2u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x2_t arg1_uint32x2x2_t;
+
+  vst2_u32 (arg0_uint32_t, arg1_uint32x2x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
new file mode 100644
index 000000000..006e31f25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u64.c
@@ -0,0 +1,20 @@
+/* Test the `vst2u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x2_t arg1_uint64x1x2_t;
+
+  vst2_u64 (arg0_uint64_t, arg1_uint64x1x2_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
new file mode 100644
index 000000000..55cd34779
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst2u8.c
@@ -0,0 +1,20 @@
+/* Test the `vst2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst2u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+
+  vst2_u8 (arg0_uint8_t, arg1_uint8x8x2_t);
+}
+
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
new file mode 100644
index 000000000..8e4f0dca9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
new file mode 100644
index 000000000..f8fcb977f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
new file mode 100644
index 000000000..3fde1a3af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
new file mode 100644
index 000000000..1eb428922
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
new file mode 100644
index 000000000..ca98dded6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
new file mode 100644
index 000000000..a2a59d7a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
new file mode 100644
index 000000000..b4b480fb7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qf32.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x3_t arg1_float32x4x3_t;
+
+  vst3q_f32 (arg0_float32_t, arg1_float32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
new file mode 100644
index 000000000..aa34886f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp16.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x3_t arg1_poly16x8x3_t;
+
+  vst3q_p16 (arg0_poly16_t, arg1_poly16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
new file mode 100644
index 000000000..b13fcd7e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qp8.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x3_t arg1_poly8x16x3_t;
+
+  vst3q_p8 (arg0_poly8_t, arg1_poly8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
new file mode 100644
index 000000000..6cac405f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs16.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x3_t arg1_int16x8x3_t;
+
+  vst3q_s16 (arg0_int16_t, arg1_int16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
new file mode 100644
index 000000000..3c8437094
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs32.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x3_t arg1_int32x4x3_t;
+
+  vst3q_s32 (arg0_int32_t, arg1_int32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
new file mode 100644
index 000000000..fee56af42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qs8.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x3_t arg1_int8x16x3_t;
+
+  vst3q_s8 (arg0_int8_t, arg1_int8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
new file mode 100644
index 000000000..af3910b7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu16.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x3_t arg1_uint16x8x3_t;
+
+  vst3q_u16 (arg0_uint16_t, arg1_uint16x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
new file mode 100644
index 000000000..8828885af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu32.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x3_t arg1_uint32x4x3_t;
+
+  vst3q_u32 (arg0_uint32_t, arg1_uint32x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
new file mode 100644
index 000000000..c273fe6dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3Qu8.c
@@ -0,0 +1,21 @@
+/* Test the `vst3Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x3_t arg1_uint8x16x3_t;
+
+  vst3q_u8 (arg0_uint8_t, arg1_uint8x16x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
new file mode 100644
index 000000000..de654e907
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
new file mode 100644
index 000000000..de733ff67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
new file mode 100644
index 000000000..a9a26447f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
new file mode 100644
index 000000000..a98b40714
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
new file mode 100644
index 000000000..5b2450c67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
new file mode 100644
index 000000000..8cd04f716
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
new file mode 100644
index 000000000..692058d91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
new file mode 100644
index 000000000..32a5193a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
new file mode 100644
index 000000000..952ffcbec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
new file mode 100644
index 000000000..e80b8e916
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3f32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x3_t arg1_float32x2x3_t;
+
+  vst3_f32 (arg0_float32_t, arg1_float32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
new file mode 100644
index 000000000..1d7831264
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x3_t arg1_poly16x4x3_t;
+
+  vst3_p16 (arg0_poly16_t, arg1_poly16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
new file mode 100644
index 000000000..73ced9544
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst3p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst3p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x3_t arg1_poly64x1x3_t;
+
+  vst3_p64 (arg0_poly64_t, arg1_poly64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
new file mode 100644
index 000000000..ca8c5ec43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3p8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+
+  vst3_p8 (arg0_poly8_t, arg1_poly8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
new file mode 100644
index 000000000..5c1bcf9de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x3_t arg1_int16x4x3_t;
+
+  vst3_s16 (arg0_int16_t, arg1_int16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
new file mode 100644
index 000000000..3f5a3aad1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x3_t arg1_int32x2x3_t;
+
+  vst3_s32 (arg0_int32_t, arg1_int32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
new file mode 100644
index 000000000..8c6a851db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s64.c
@@ -0,0 +1,20 @@
+/* Test the `vst3s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x3_t arg1_int64x1x3_t;
+
+  vst3_s64 (arg0_int64_t, arg1_int64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
new file mode 100644
index 000000000..8853fbaf5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3s8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+
+  vst3_s8 (arg0_int8_t, arg1_int8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
new file mode 100644
index 000000000..e17c6c8d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u16.c
@@ -0,0 +1,20 @@
+/* Test the `vst3u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x3_t arg1_uint16x4x3_t;
+
+  vst3_u16 (arg0_uint16_t, arg1_uint16x4x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
new file mode 100644
index 000000000..3b7d8ce20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u32.c
@@ -0,0 +1,20 @@
+/* Test the `vst3u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x3_t arg1_uint32x2x3_t;
+
+  vst3_u32 (arg0_uint32_t, arg1_uint32x2x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
new file mode 100644
index 000000000..08d9c7a08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u64.c
@@ -0,0 +1,20 @@
+/* Test the `vst3u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x3_t arg1_uint64x1x3_t;
+
+  vst3_u64 (arg0_uint64_t, arg1_uint64x1x3_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
new file mode 100644
index 000000000..78944cba0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst3u8.c
@@ -0,0 +1,20 @@
+/* Test the `vst3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst3u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+
+  vst3_u8 (arg0_uint8_t, arg1_uint8x8x3_t);
+}
+
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
new file mode 100644
index 000000000..adbb4d569
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Q_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
new file mode 100644
index 000000000..587477c87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Q_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
new file mode 100644
index 000000000..3febdf7d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Q_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
new file mode 100644
index 000000000..71406af83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Q_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
new file mode 100644
index 000000000..1229c86a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Q_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
new file mode 100644
index 000000000..5e0683f30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4Q_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Q_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
new file mode 100644
index 000000000..2ecb6b173
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qf32.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qf32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x4x4_t arg1_float32x4x4_t;
+
+  vst4q_f32 (arg0_float32_t, arg1_float32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
new file mode 100644
index 000000000..a9b9b7ca9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp16.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x8x4_t arg1_poly16x8x4_t;
+
+  vst4q_p16 (arg0_poly16_t, arg1_poly16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
new file mode 100644
index 000000000..17142c1a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qp8.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qp8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x16x4_t arg1_poly8x16x4_t;
+
+  vst4q_p8 (arg0_poly8_t, arg1_poly8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
new file mode 100644
index 000000000..8511619fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs16.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x8x4_t arg1_int16x8x4_t;
+
+  vst4q_s16 (arg0_int16_t, arg1_int16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
new file mode 100644
index 000000000..f65894eab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs32.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x4x4_t arg1_int32x4x4_t;
+
+  vst4q_s32 (arg0_int32_t, arg1_int32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
new file mode 100644
index 000000000..a74d58b5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qs8.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qs8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x16x4_t arg1_int8x16x4_t;
+
+  vst4q_s8 (arg0_int8_t, arg1_int8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
new file mode 100644
index 000000000..b124c7cc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu16.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x8x4_t arg1_uint16x8x4_t;
+
+  vst4q_u16 (arg0_uint16_t, arg1_uint16x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
new file mode 100644
index 000000000..fa7d2130d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu32.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x4x4_t arg1_uint32x4x4_t;
+
+  vst4q_u32 (arg0_uint32_t, arg1_uint32x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
new file mode 100644
index 000000000..d853b12bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4Qu8.c
@@ -0,0 +1,21 @@
+/* Test the `vst4Qu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4Qu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x16x4_t arg1_uint8x16x4_t;
+
+  vst4q_u8 (arg0_uint8_t, arg1_uint8x16x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
new file mode 100644
index 000000000..acef9f0a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_lanef32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanef32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
new file mode 100644
index 000000000..64e4713ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_lanep16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
new file mode 100644
index 000000000..1ac58df28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_lanep8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanep8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
new file mode 100644
index 000000000..e7e1e2aea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_lanes16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
new file mode 100644
index 000000000..2c99611a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_lanes32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
new file mode 100644
index 000000000..7eebc1644
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_lanes8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_lanes8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
new file mode 100644
index 000000000..decc7caf2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_laneu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
new file mode 100644
index 000000000..4cfeddbbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_laneu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
new file mode 100644
index 000000000..217ced27a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4_laneu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4_laneu8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
new file mode 100644
index 000000000..931b8ed15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4f32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4f32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4f32 (void)
+{
+  float32_t *arg0_float32_t;
+  float32x2x4_t arg1_float32x2x4_t;
+
+  vst4_f32 (arg0_float32_t, arg1_float32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
new file mode 100644
index 000000000..ea58c44fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4p16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4p16 (void)
+{
+  poly16_t *arg0_poly16_t;
+  poly16x4x4_t arg1_poly16x4x4_t;
+
+  vst4_p16 (arg0_poly16_t, arg1_poly16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
new file mode 100644
index 000000000..b9f7b168d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p64.c
@@ -0,0 +1,20 @@
+/* Test the `vst4p64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+void test_vst4p64 (void)
+{
+  poly64_t *arg0_poly64_t;
+  poly64x1x4_t arg1_poly64x1x4_t;
+
+  vst4_p64 (arg0_poly64_t, arg1_poly64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
new file mode 100644
index 000000000..95e5ccdf1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4p8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4p8 (void)
+{
+  poly8_t *arg0_poly8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+
+  vst4_p8 (arg0_poly8_t, arg1_poly8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
new file mode 100644
index 000000000..7811d74c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4s16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4s16 (void)
+{
+  int16_t *arg0_int16_t;
+  int16x4x4_t arg1_int16x4x4_t;
+
+  vst4_s16 (arg0_int16_t, arg1_int16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
new file mode 100644
index 000000000..f93ea4097
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4s32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4s32 (void)
+{
+  int32_t *arg0_int32_t;
+  int32x2x4_t arg1_int32x2x4_t;
+
+  vst4_s32 (arg0_int32_t, arg1_int32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
new file mode 100644
index 000000000..796762a3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s64.c
@@ -0,0 +1,20 @@
+/* Test the `vst4s64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4s64 (void)
+{
+  int64_t *arg0_int64_t;
+  int64x1x4_t arg1_int64x1x4_t;
+
+  vst4_s64 (arg0_int64_t, arg1_int64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
new file mode 100644
index 000000000..877e2c407
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4s8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4s8 (void)
+{
+  int8_t *arg0_int8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+
+  vst4_s8 (arg0_int8_t, arg1_int8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
new file mode 100644
index 000000000..5de43f591
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u16.c
@@ -0,0 +1,20 @@
+/* Test the `vst4u16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4u16 (void)
+{
+  uint16_t *arg0_uint16_t;
+  uint16x4x4_t arg1_uint16x4x4_t;
+
+  vst4_u16 (arg0_uint16_t, arg1_uint16x4x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
new file mode 100644
index 000000000..1ae9e5e60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u32.c
@@ -0,0 +1,20 @@
+/* Test the `vst4u32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4u32 (void)
+{
+  uint32_t *arg0_uint32_t;
+  uint32x2x4_t arg1_uint32x2x4_t;
+
+  vst4_u32 (arg0_uint32_t, arg1_uint32x2x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
new file mode 100644
index 000000000..2453d6bd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u64.c
@@ -0,0 +1,20 @@
+/* Test the `vst4u64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4u64 (void)
+{
+  uint64_t *arg0_uint64_t;
+  uint64x1x4_t arg1_uint64x1x4_t;
+
+  vst4_u64 (arg0_uint64_t, arg1_uint64x1x4_t);
+}
+
+/* { dg-final { scan-assembler "vst1\.64\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
new file mode 100644
index 000000000..380acc647
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vst4u8.c
@@ -0,0 +1,20 @@
+/* Test the `vst4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vst4u8 (void)
+{
+  uint8_t *arg0_uint8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+
+  vst4_u8 (arg0_uint8_t, arg1_uint8x8x4_t);
+}
+
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \\\[\[rR\]\[0-9\]+\(:\[0-9\]+\)?\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
new file mode 100644
index 000000000..88caa2898
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQf32 (void)
+{
+  float32x4_t out_float32x4_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4_t = vsubq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
new file mode 100644
index 000000000..d33790b9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQs16 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8_t = vsubq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
new file mode 100644
index 000000000..77b2a743f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQs32 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4_t = vsubq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
new file mode 100644
index 000000000..1b0c5a198
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs64.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQs64 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int64x2_t = vsubq_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
new file mode 100644
index 000000000..11b2f6a8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQs8 (void)
+{
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16_t = vsubq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
new file mode 100644
index 000000000..e3f750406
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vsubq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
new file mode 100644
index 000000000..5fe1d0b4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vsubq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
new file mode 100644
index 000000000..19536b992
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQu64 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint64x2_t = vsubq_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i64\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
new file mode 100644
index 000000000..c9f5d95b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsubQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vsubq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
new file mode 100644
index 000000000..442828abd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubf32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubf32 (void)
+{
+  float32x2_t out_float32x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2_t = vsub_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
new file mode 100644
index 000000000..06e6189be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubhns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhns16 (void)
+{
+  int8x8_t out_int8x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int8x8_t = vsubhn_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
new file mode 100644
index 000000000..42e8b5740
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubhns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhns32 (void)
+{
+  int16x4_t out_int16x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int16x4_t = vsubhn_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
new file mode 100644
index 000000000..f314a40d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhns64.c
@@ -0,0 +1,21 @@
+/* Test the `vsubhns64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhns64 (void)
+{
+  int32x2_t out_int32x2_t;
+  int64x2_t arg0_int64x2_t;
+  int64x2_t arg1_int64x2_t;
+
+  out_int32x2_t = vsubhn_s64 (arg0_int64x2_t, arg1_int64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
new file mode 100644
index 000000000..5c3f82624
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubhnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu16 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint8x8_t = vsubhn_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i16\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
new file mode 100644
index 000000000..1bd62fc15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubhnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu32 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint16x4_t = vsubhn_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i32\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
new file mode 100644
index 000000000..35fa65afa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubhnu64.c
@@ -0,0 +1,21 @@
+/* Test the `vsubhnu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubhnu64 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint64x2_t arg1_uint64x2_t;
+
+  out_uint32x2_t = vsubhn_u64 (arg0_uint64x2_t, arg1_uint64x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubhn\.i64\[ 	\]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
new file mode 100644
index 000000000..1db042d94
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubls16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubls16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubl_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
new file mode 100644
index 000000000..e8acf9240
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubls32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubls32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubl_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
new file mode 100644
index 000000000..7b457cadb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubls8.c
@@ -0,0 +1,21 @@
+/* Test the `vsubls8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubls8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubl_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
new file mode 100644
index 000000000..b9cc873ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsublu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsublu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubl_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
new file mode 100644
index 000000000..afb456e65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsublu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsublu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubl_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
new file mode 100644
index 000000000..890925437
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsublu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsublu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsublu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubl_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubl\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
new file mode 100644
index 000000000..0638a7dfe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubs16 (void)
+{
+  int16x4_t out_int16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4_t = vsub_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
new file mode 100644
index 000000000..0c9b6a360
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubs32 (void)
+{
+  int32x2_t out_int32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2_t = vsub_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
new file mode 100644
index 000000000..57bcd33d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubs64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubs64 (void)
+{
+  int64x1_t out_int64x1_t;
+  int64x1_t arg0_int64x1_t;
+  int64x1_t arg1_int64x1_t;
+
+  out_int64x1_t = vsub_s64 (arg0_int64x1_t, arg1_int64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
new file mode 100644
index 000000000..cb927d615
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubs8.c
@@ -0,0 +1,21 @@
+/* Test the `vsubs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubs8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vsub_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
new file mode 100644
index 000000000..80985e247
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vsub_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
new file mode 100644
index 000000000..47d595ba1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vsub_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
new file mode 100644
index 000000000..3a8ae462e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu64.c
@@ -0,0 +1,20 @@
+/* Test the `vsubu64' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubu64 (void)
+{
+  uint64x1_t out_uint64x1_t;
+  uint64x1_t arg0_uint64x1_t;
+  uint64x1_t arg1_uint64x1_t;
+
+  out_uint64x1_t = vsub_u64 (arg0_uint64x1_t, arg1_uint64x1_t);
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
new file mode 100644
index 000000000..b359e1655
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsubu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vsub_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsub\.i8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
new file mode 100644
index 000000000..90cbe20a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubws16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubws16 (void)
+{
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int32x4_t = vsubw_s16 (arg0_int32x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
new file mode 100644
index 000000000..963e5933c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubws32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubws32 (void)
+{
+  int64x2_t out_int64x2_t;
+  int64x2_t arg0_int64x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int64x2_t = vsubw_s32 (arg0_int64x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
new file mode 100644
index 000000000..103b8fcb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubws8.c
@@ -0,0 +1,21 @@
+/* Test the `vsubws8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubws8 (void)
+{
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int16x8_t = vsubw_s8 (arg0_int16x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
new file mode 100644
index 000000000..98e5cdac3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu16.c
@@ -0,0 +1,21 @@
+/* Test the `vsubwu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubwu16 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint32x4_t = vsubw_u16 (arg0_uint32x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
new file mode 100644
index 000000000..ccd2a7b09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu32.c
@@ -0,0 +1,21 @@
+/* Test the `vsubwu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubwu32 (void)
+{
+  uint64x2_t out_uint64x2_t;
+  uint64x2_t arg0_uint64x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint64x2_t = vsubw_u32 (arg0_uint64x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
new file mode 100644
index 000000000..c89e73331
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vsubwu8.c
@@ -0,0 +1,21 @@
+/* Test the `vsubwu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vsubwu8 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint16x8_t = vsubw_u8 (arg0_uint16x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vsubw\.u8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
new file mode 100644
index 000000000..225159c3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl1_p8 (arg0_poly8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
new file mode 100644
index 000000000..a8ecd46e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl1_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
new file mode 100644
index 000000000..1d2ea7d0d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl1u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl1_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
new file mode 100644
index 000000000..bb748f95b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x2_t arg0_poly8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl2_p8 (arg0_poly8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
new file mode 100644
index 000000000..29dc16190
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x2_t arg0_int8x8x2_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl2_s8 (arg0_int8x8x2_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
new file mode 100644
index 000000000..493538461
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl2u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x2_t arg0_uint8x8x2_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl2_u8 (arg0_uint8x8x2_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
new file mode 100644
index 000000000..4bc77fa1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x3_t arg0_poly8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl3_p8 (arg0_poly8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
new file mode 100644
index 000000000..f088f3777
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x3_t arg0_int8x8x3_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl3_s8 (arg0_int8x8x3_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
new file mode 100644
index 000000000..3f84d0062
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl3u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x3_t arg0_uint8x8x3_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl3_u8 (arg0_uint8x8x3_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
new file mode 100644
index 000000000..2cdc37d04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4p8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8x4_t arg0_poly8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_poly8x8_t = vtbl4_p8 (arg0_poly8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
new file mode 100644
index 000000000..870c9bd4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4s8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8x4_t arg0_int8x8x4_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8_t = vtbl4_s8 (arg0_int8x8x4_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
new file mode 100644
index 000000000..461fc9569
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbl4u8.c
@@ -0,0 +1,21 @@
+/* Test the `vtbl4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbl4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8x4_t arg0_uint8x8x4_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtbl4_u8 (arg0_uint8x8x4_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbl\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
new file mode 100644
index 000000000..a081f169e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1p8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx1p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx1p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx1_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
new file mode 100644
index 000000000..400ef33ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1s8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx1s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx1s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx1_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
new file mode 100644
index 000000000..da4a65d43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx1u8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx1u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx1u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx1_u8 (arg0_uint8x8_t, arg1_uint8x8_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, ((\\\{\[dD\]\[0-9\]+\\\})|(\[dD\]\[0-9\]+)), \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
new file mode 100644
index 000000000..ffc07b470
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2p8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx2p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx2p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x2_t arg1_poly8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx2_p8 (arg0_poly8x8_t, arg1_poly8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
new file mode 100644
index 000000000..96c9104a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2s8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx2s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx2s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x2_t arg1_int8x8x2_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx2_s8 (arg0_int8x8_t, arg1_int8x8x2_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
new file mode 100644
index 000000000..4b5606448
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx2u8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx2u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx2u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x2_t arg1_uint8x8x2_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx2_u8 (arg0_uint8x8_t, arg1_uint8x8x2_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
new file mode 100644
index 000000000..8f06ef92e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3p8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx3p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx3p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x3_t arg1_poly8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx3_p8 (arg0_poly8x8_t, arg1_poly8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
new file mode 100644
index 000000000..996277476
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3s8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx3s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx3s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x3_t arg1_int8x8x3_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx3_s8 (arg0_int8x8_t, arg1_int8x8x3_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
new file mode 100644
index 000000000..b6785512a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx3u8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx3u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx3u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x3_t arg1_uint8x8x3_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx3_u8 (arg0_uint8x8_t, arg1_uint8x8x3_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
new file mode 100644
index 000000000..c021cf823
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4p8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx4p8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx4p8 (void)
+{
+  poly8x8_t out_poly8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8x4_t arg1_poly8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_poly8x8_t = vtbx4_p8 (arg0_poly8x8_t, arg1_poly8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
new file mode 100644
index 000000000..c06b1aaf9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4s8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx4s8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx4s8 (void)
+{
+  int8x8_t out_int8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8x4_t arg1_int8x8x4_t;
+  int8x8_t arg2_int8x8_t;
+
+  out_int8x8_t = vtbx4_s8 (arg0_int8x8_t, arg1_int8x8x4_t, arg2_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
new file mode 100644
index 000000000..e43ca46f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtbx4u8.c
@@ -0,0 +1,22 @@
+/* Test the `vtbx4u8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtbx4u8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8x4_t arg1_uint8x8x4_t;
+  uint8x8_t arg2_uint8x8_t;
+
+  out_uint8x8_t = vtbx4_u8 (arg0_uint8x8_t, arg1_uint8x8x4_t, arg2_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtbx\.8\[ 	\]+\[dD\]\[0-9\]+, \\\{((\[dD\]\[0-9\]+-\[dD\]\[0-9\]+)|(\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+))\\\}, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
new file mode 100644
index 000000000..690fa19d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vtrnq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
new file mode 100644
index 000000000..58f156eab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp16.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vtrnq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
new file mode 100644
index 000000000..0819bfbf2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vtrnq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
new file mode 100644
index 000000000..dc4f76e8e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vtrnq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
new file mode 100644
index 000000000..fe71416de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vtrnq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
new file mode 100644
index 000000000..5ddd827d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vtrnq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
new file mode 100644
index 000000000..1d66dae84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vtrnq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
new file mode 100644
index 000000000..2712dd513
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vtrnq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
new file mode 100644
index 000000000..58f6f64e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vtrnq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
new file mode 100644
index 000000000..c5a301b99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnf32.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vtrn_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
new file mode 100644
index 000000000..b970a6a26
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp16.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vtrn_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
new file mode 100644
index 000000000..615bd5750
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnp8.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vtrn_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
new file mode 100644
index 000000000..068720c86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns16.c
@@ -0,0 +1,21 @@
+/* Test the `vtrns16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrns16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vtrn_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
new file mode 100644
index 000000000..f01047497
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns32.c
@@ -0,0 +1,21 @@
+/* Test the `vtrns32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrns32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vtrn_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
new file mode 100644
index 000000000..bf900a107
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrns8.c
@@ -0,0 +1,21 @@
+/* Test the `vtrns8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrns8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vtrn_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
new file mode 100644
index 000000000..aa98b4026
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu16.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vtrn_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
new file mode 100644
index 000000000..74f5cace6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu32.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vtrn_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
new file mode 100644
index 000000000..f4766be76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtrnu8.c
@@ -0,0 +1,21 @@
+/* Test the `vtrnu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtrnu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vtrn_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtrn\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
new file mode 100644
index 000000000..69e876328
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vtstQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQp8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_uint8x16_t = vtstq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
new file mode 100644
index 000000000..a41fd7df9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vtstQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQs16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_uint16x8_t = vtstq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
new file mode 100644
index 000000000..b5e46b442
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vtstQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQs32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_uint32x4_t = vtstq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
new file mode 100644
index 000000000..f3bf7004a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vtstQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQs8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_uint8x16_t = vtstq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
new file mode 100644
index 000000000..7024ebe1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vtstQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQu16 (void)
+{
+  uint16x8_t out_uint16x8_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8_t = vtstq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
new file mode 100644
index 000000000..717ffd1ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vtstQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQu32 (void)
+{
+  uint32x4_t out_uint32x4_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4_t = vtstq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
new file mode 100644
index 000000000..bc3729961
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vtstQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstQu8 (void)
+{
+  uint8x16_t out_uint8x16_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16_t = vtstq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
new file mode 100644
index 000000000..6bd7cae15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstp8.c
@@ -0,0 +1,21 @@
+/* Test the `vtstp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstp8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_uint8x8_t = vtst_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
new file mode 100644
index 000000000..1637af486
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts16.c
@@ -0,0 +1,21 @@
+/* Test the `vtsts16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtsts16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_uint16x4_t = vtst_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
new file mode 100644
index 000000000..e8037b977
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts32.c
@@ -0,0 +1,21 @@
+/* Test the `vtsts32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtsts32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_uint32x2_t = vtst_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
new file mode 100644
index 000000000..ec3379adb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtsts8.c
@@ -0,0 +1,21 @@
+/* Test the `vtsts8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtsts8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_uint8x8_t = vtst_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
new file mode 100644
index 000000000..629855f61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu16.c
@@ -0,0 +1,21 @@
+/* Test the `vtstu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstu16 (void)
+{
+  uint16x4_t out_uint16x4_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4_t = vtst_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
new file mode 100644
index 000000000..a8b774b7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu32.c
@@ -0,0 +1,21 @@
+/* Test the `vtstu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstu32 (void)
+{
+  uint32x2_t out_uint32x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2_t = vtst_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
new file mode 100644
index 000000000..51480d8ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vtstu8.c
@@ -0,0 +1,21 @@
+/* Test the `vtstu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vtstu8 (void)
+{
+  uint8x8_t out_uint8x8_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8_t = vtst_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vtst\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
new file mode 100644
index 000000000..2f429394e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vuzpq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
new file mode 100644
index 000000000..31760090a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp16.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vuzpq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
new file mode 100644
index 000000000..e5d7a2de5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vuzpq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
new file mode 100644
index 000000000..b0a427e4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vuzpq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
new file mode 100644
index 000000000..b883174b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vuzpq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
new file mode 100644
index 000000000..84d2a8afb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vuzpq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
new file mode 100644
index 000000000..f583a5082
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vuzpq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
new file mode 100644
index 000000000..3c96ef362
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vuzpq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
new file mode 100644
index 000000000..f385a56ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vuzpq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
new file mode 100644
index 000000000..ca92c7e9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpf32.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vuzp_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
new file mode 100644
index 000000000..cf2b796ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp16.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vuzp_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
new file mode 100644
index 000000000..da46ec058
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpp8.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vuzp_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
new file mode 100644
index 000000000..4d0a90670
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps16.c
@@ -0,0 +1,21 @@
+/* Test the `vuzps16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzps16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vuzp_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
new file mode 100644
index 000000000..b337fad20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps32.c
@@ -0,0 +1,21 @@
+/* Test the `vuzps32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzps32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vuzp_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
new file mode 100644
index 000000000..73da12852
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzps8.c
@@ -0,0 +1,21 @@
+/* Test the `vuzps8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzps8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vuzp_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
new file mode 100644
index 000000000..259a141e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu16.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vuzp_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
new file mode 100644
index 000000000..1d5fae6a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu32.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vuzp_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
new file mode 100644
index 000000000..e5e368039
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vuzpu8.c
@@ -0,0 +1,21 @@
+/* Test the `vuzpu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vuzpu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vuzp_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
new file mode 100644
index 000000000..fee46b793
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQf32.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQf32 (void)
+{
+  float32x4x2_t out_float32x4x2_t;
+  float32x4_t arg0_float32x4_t;
+  float32x4_t arg1_float32x4_t;
+
+  out_float32x4x2_t = vzipq_f32 (arg0_float32x4_t, arg1_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
new file mode 100644
index 000000000..1a0b0803e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp16.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQp16 (void)
+{
+  poly16x8x2_t out_poly16x8x2_t;
+  poly16x8_t arg0_poly16x8_t;
+  poly16x8_t arg1_poly16x8_t;
+
+  out_poly16x8x2_t = vzipq_p16 (arg0_poly16x8_t, arg1_poly16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
new file mode 100644
index 000000000..c0cca6074
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQp8.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQp8 (void)
+{
+  poly8x16x2_t out_poly8x16x2_t;
+  poly8x16_t arg0_poly8x16_t;
+  poly8x16_t arg1_poly8x16_t;
+
+  out_poly8x16x2_t = vzipq_p8 (arg0_poly8x16_t, arg1_poly8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
new file mode 100644
index 000000000..2979d1a0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs16.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQs16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQs16 (void)
+{
+  int16x8x2_t out_int16x8x2_t;
+  int16x8_t arg0_int16x8_t;
+  int16x8_t arg1_int16x8_t;
+
+  out_int16x8x2_t = vzipq_s16 (arg0_int16x8_t, arg1_int16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
new file mode 100644
index 000000000..4a96c4aa3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs32.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQs32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQs32 (void)
+{
+  int32x4x2_t out_int32x4x2_t;
+  int32x4_t arg0_int32x4_t;
+  int32x4_t arg1_int32x4_t;
+
+  out_int32x4x2_t = vzipq_s32 (arg0_int32x4_t, arg1_int32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
new file mode 100644
index 000000000..718756774
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQs8.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQs8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQs8 (void)
+{
+  int8x16x2_t out_int8x16x2_t;
+  int8x16_t arg0_int8x16_t;
+  int8x16_t arg1_int8x16_t;
+
+  out_int8x16x2_t = vzipq_s8 (arg0_int8x16_t, arg1_int8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
new file mode 100644
index 000000000..b4641de3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu16.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQu16 (void)
+{
+  uint16x8x2_t out_uint16x8x2_t;
+  uint16x8_t arg0_uint16x8_t;
+  uint16x8_t arg1_uint16x8_t;
+
+  out_uint16x8x2_t = vzipq_u16 (arg0_uint16x8_t, arg1_uint16x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
new file mode 100644
index 000000000..c8fee60c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu32.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQu32 (void)
+{
+  uint32x4x2_t out_uint32x4x2_t;
+  uint32x4_t arg0_uint32x4_t;
+  uint32x4_t arg1_uint32x4_t;
+
+  out_uint32x4x2_t = vzipq_u32 (arg0_uint32x4_t, arg1_uint32x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
new file mode 100644
index 000000000..eee6bc54f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipQu8.c
@@ -0,0 +1,21 @@
+/* Test the `vzipQu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipQu8 (void)
+{
+  uint8x16x2_t out_uint8x16x2_t;
+  uint8x16_t arg0_uint8x16_t;
+  uint8x16_t arg1_uint8x16_t;
+
+  out_uint8x16x2_t = vzipq_u8 (arg0_uint8x16_t, arg1_uint8x16_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
new file mode 100644
index 000000000..6c13a07ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipf32.c
@@ -0,0 +1,21 @@
+/* Test the `vzipf32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipf32 (void)
+{
+  float32x2x2_t out_float32x2x2_t;
+  float32x2_t arg0_float32x2_t;
+  float32x2_t arg1_float32x2_t;
+
+  out_float32x2x2_t = vzip_f32 (arg0_float32x2_t, arg1_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
new file mode 100644
index 000000000..726500ed3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp16.c
@@ -0,0 +1,21 @@
+/* Test the `vzipp16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipp16 (void)
+{
+  poly16x4x2_t out_poly16x4x2_t;
+  poly16x4_t arg0_poly16x4_t;
+  poly16x4_t arg1_poly16x4_t;
+
+  out_poly16x4x2_t = vzip_p16 (arg0_poly16x4_t, arg1_poly16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
new file mode 100644
index 000000000..4a5dd76b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipp8.c
@@ -0,0 +1,21 @@
+/* Test the `vzipp8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipp8 (void)
+{
+  poly8x8x2_t out_poly8x8x2_t;
+  poly8x8_t arg0_poly8x8_t;
+  poly8x8_t arg1_poly8x8_t;
+
+  out_poly8x8x2_t = vzip_p8 (arg0_poly8x8_t, arg1_poly8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c
new file mode 100644
index 000000000..795bab6d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips16.c
@@ -0,0 +1,21 @@
+/* Test the `vzips16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzips16 (void)
+{
+  int16x4x2_t out_int16x4x2_t;
+  int16x4_t arg0_int16x4_t;
+  int16x4_t arg1_int16x4_t;
+
+  out_int16x4x2_t = vzip_s16 (arg0_int16x4_t, arg1_int16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c
new file mode 100644
index 000000000..663985ebe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips32.c
@@ -0,0 +1,21 @@
+/* Test the `vzips32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzips32 (void)
+{
+  int32x2x2_t out_int32x2x2_t;
+  int32x2_t arg0_int32x2_t;
+  int32x2_t arg1_int32x2_t;
+
+  out_int32x2x2_t = vzip_s32 (arg0_int32x2_t, arg1_int32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c
new file mode 100644
index 000000000..cca6933aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzips8.c
@@ -0,0 +1,21 @@
+/* Test the `vzips8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzips8 (void)
+{
+  int8x8x2_t out_int8x8x2_t;
+  int8x8_t arg0_int8x8_t;
+  int8x8_t arg1_int8x8_t;
+
+  out_int8x8x2_t = vzip_s8 (arg0_int8x8_t, arg1_int8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
new file mode 100644
index 000000000..53822f93a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu16.c
@@ -0,0 +1,21 @@
+/* Test the `vzipu16' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipu16 (void)
+{
+  uint16x4x2_t out_uint16x4x2_t;
+  uint16x4_t arg0_uint16x4_t;
+  uint16x4_t arg1_uint16x4_t;
+
+  out_uint16x4x2_t = vzip_u16 (arg0_uint16x4_t, arg1_uint16x4_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
new file mode 100644
index 000000000..d9a280bf4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu32.c
@@ -0,0 +1,21 @@
+/* Test the `vzipu32' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipu32 (void)
+{
+  uint32x2x2_t out_uint32x2x2_t;
+  uint32x2_t arg0_uint32x2_t;
+  uint32x2_t arg1_uint32x2_t;
+
+  out_uint32x2x2_t = vzip_u32 (arg0_uint32x2_t, arg1_uint32x2_t);
+}
+
+/* { dg-final { scan-assembler "vuzp\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
new file mode 100644
index 000000000..056898939
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vzipu8.c
@@ -0,0 +1,21 @@
+/* Test the `vzipu8' ARM Neon intrinsic.  */
+/* This file was autogenerated by neon-testgen.  */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vzipu8 (void)
+{
+  uint8x8x2_t out_uint8x8x2_t;
+  uint8x8_t arg0_uint8x8_t;
+  uint8x8_t arg1_uint8x8_t;
+
+  out_uint8x8x2_t = vzip_u8 (arg0_uint8x8_t, arg1_uint8x8_t);
+}
+
+/* { dg-final { scan-assembler "vzip\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/nested-apcs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/nested-apcs.c
new file mode 100644
index 000000000..9dac3043e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/nested-apcs.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-fno-omit-frame-pointer -mapcs-frame -O" } */
+
+extern void abort (void);
+
+struct x
+{
+  int y;
+  int z;
+};
+
+int __attribute__((noinline)) f (int c, int d, int e, int h, int i)
+{
+  int a;
+  struct x b;
+
+  int __attribute__((noinline)) g (int p, int q, int r, struct x s)
+  {
+    return a + p + q + r + s.y + s.z;
+  }
+
+  a = 5;
+  b.y = h;
+  b.z = i;
+
+  return g(c, d, e, b);
+}
+
+int main(void)
+{
+  if (f (1, 2, 3, 4, 5) != 20)
+    abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/no-wmla-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/no-wmla-1.c
new file mode 100644
index 000000000..1be162e05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/no-wmla-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+int
+foo (int a, short b, short c)
+{
+     int bc = b * c;
+        return a + (short)bc;
+}
+
+/* { dg-final { scan-assembler "\tmul\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c
new file mode 100644
index 000000000..eb2b86ee7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-ldrd-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_prefer_ldrd_strd } */
+/* { dg-options "-O2" }  */
+int foo(int a, int b, int* p, int *q)
+{
+  a = p[2] + p[3];
+  *q = a;
+  *p = a;
+  return a;
+}
+/* { dg-final { scan-assembler "ldrd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-strd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-strd-1.c
new file mode 100644
index 000000000..bd3307695
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/peep-strd-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_prefer_ldrd_strd } */
+/* { dg-options "-O2" }  */
+void foo(int a, int b, int* p)
+{
+  p[2] = a;
+  p[3] = b;
+}
+/* { dg-final { scan-assembler "strd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr19599.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr19599.c
new file mode 100644
index 000000000..c3ee22017
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr19599.c
@@ -0,0 +1,10 @@
+/* { dg-skip-if "need at least armv5te" { *-*-* } { "-march=armv[234]*" "-mthumb" } { "" } } */
+/* { dg-options "-O2 -march=armv5te -marm" }  */
+/* { dg-final { scan-assembler "bx" } } */
+
+int (*indirect_func)();
+
+int indirect_call()
+{
+  return indirect_func();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr39839.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr39839.c
new file mode 100644
index 000000000..3d353244c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr39839.c
@@ -0,0 +1,24 @@
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-Os -fpic" }  */
+/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */
+
+struct S
+{
+  int count;
+  char *addr;
+};
+
+void func(const char*, const char*, int, const char*);
+
+/* This function should not need to spill to the stack. */
+void test(struct S *p)
+{
+  int off = p->count;
+  while (p->count >= 0)
+    {
+      const char *s = "xyz";
+      if (*p->addr) s = "pqr";
+      func("abcde", p->addr + off, off, s);
+      p->count--;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-1.c
new file mode 100644
index 000000000..44122bb2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-1.c
@@ -0,0 +1,10 @@
+/* { dg-options "-Os" }  */
+/* { dg-do compile } */
+
+int bar(int* p)
+{
+  int x = p[0] + p[1];
+  return x;
+}
+
+/* { dg-final { scan-assembler "ldrd|ldm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-2.c
new file mode 100644
index 000000000..31624d351
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-2.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O2" }  */
+/* { dg-do compile } */
+
+void foo(int* p)
+{
+  p[0] = 1;
+  p[1] = 0;
+}
+
+/* { dg-final { scan-assembler "strd|stm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-3.c
new file mode 100644
index 000000000..81f6a424c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40457-3.c
@@ -0,0 +1,10 @@
+/* { dg-options "-Os" }  */
+/* { dg-do compile } */
+
+void foo(int* p)
+{
+  p[0] = 1;
+  p[1] = 0;
+}
+
+/* { dg-final { scan-assembler "strd|stm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40482.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40482.c
new file mode 100644
index 000000000..6926e6fc8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40482.c
@@ -0,0 +1,8 @@
+/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-final { scan-assembler-not "ldr" } } */
+
+unsigned int foo (unsigned int i )
+{
+  return i | 0xff000000;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-1.c
new file mode 100644
index 000000000..a6ac6c78a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-1.c
@@ -0,0 +1,13 @@
+/* { dg-options "-Os -march=armv5te -mthumb" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler "pop.*r1.*pc" } } */
+/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */
+/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */
+
+extern void bar(int*);
+int foo()
+{
+  int x;
+  bar(&x);
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-2.c
new file mode 100644
index 000000000..afd469a76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40657-2.c
@@ -0,0 +1,20 @@
+/* { dg-options "-Os -mthumb" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp" } } */
+/* { dg-final { scan-assembler-not "add\[\\t \]*sp,\[\\t \]*sp" } } */
+
+/* Here, we test that if there's a pop of r[4567] in the epilogue,
+   add sp,sp,#12 is removed and replaced by three additional pops
+   of lower-numbered regs.  */
+
+extern void bar(int*);
+
+int t1, t2, t3, t4, t5;
+int foo()
+{
+  int i,j,k,x = 0;
+  for (i = 0; i < t1; i++)
+    for (j = 0; j < t2; j++)
+	  bar(&x);
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40670.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40670.c
new file mode 100644
index 000000000..24786385d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40670.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mthumb -O2" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "ldr" } } */
+
+float foo (void)
+{
+  return 2.0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40835.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40835.c
new file mode 100644
index 000000000..76ad509eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40835.c
@@ -0,0 +1,56 @@
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+
+int bar();
+void goo(int, int);
+
+void eq()
+{
+  int v = bar();
+  if (v == 0)
+    return;
+  goo(1, v);
+}
+
+void ge()
+{
+  int v = bar();
+  if (v >= 0)
+    return;
+  goo(1, v);
+}
+
+void gt()
+{
+  int v = bar();
+  if (v > 0)
+    return;
+  goo(1, v);
+}
+
+void lt()
+{
+  int v = bar();
+  if (v < 0)
+    return;
+  goo(1, v);
+}
+
+void le()
+{
+  int v = bar();
+  if (v <= 0)
+    return;
+  goo(1, v);
+}
+
+unsigned int foo();
+
+void leu()
+{
+  unsigned int v = foo();
+  if (v <= 0)
+    return;
+  goo(1, v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40887.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40887.c
new file mode 100644
index 000000000..5cabe3ab7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40887.c
@@ -0,0 +1,10 @@
+/* { dg-skip-if "need at least armv5" { *-*-* } { "-march=armv[234]*" } { "" } } */
+/* { dg-options "-O2 -march=armv5te" }  */
+/* { dg-final { scan-assembler "blx" } } */
+
+int (*indirect_func)(int x);
+
+int indirect_call()
+{
+  return indirect_func(20) + indirect_func (40);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40900.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40900.c
new file mode 100644
index 000000000..278bc3702
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40900.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-optimize-sibling-calls" }  */
+
+extern short shortv2();
+short shortv1()
+{
+  return shortv2();
+}
+
+/* { dg-final { scan-assembler-not "lsl" } } */
+/* { dg-final { scan-assembler-not "asr" } } */
+/* { dg-final { scan-assembler-not "sxth" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40956.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40956.c
new file mode 100644
index 000000000..167cdc6ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr40956.c
@@ -0,0 +1,13 @@
+/* { dg-options "-Os -fpic" }  */
+/* { dg-require-effective-target fpic } */
+/* Make sure the constant "0" is loaded into register only once.  */
+/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */
+
+int foo(int p, int* q)
+{
+  if (p!=9)
+    *q = 0;
+  else
+    *(q+1) = 0;
+  return 3;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42093.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42093.c
new file mode 100644
index 000000000..7ba2f933e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42093.c
@@ -0,0 +1,51 @@
+/* { dg-options "-mthumb -O2 -fno-reorder-blocks" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler-not "tbb" } } */
+/* { dg-final { scan-assembler-not "tbh" } } */
+
+#include <stdlib.h>
+
+int gbl;
+int foo (int *buf, int n)
+{
+  int ctr = 0;
+  int c;
+  while (1)
+    {
+      c = buf[ctr++];
+      switch (c)
+        {
+        case '\n':
+          gbl++;
+          break;
+
+        case ' ': case '\t' : case '\f' : case '\r':
+          break;
+
+        case ';':
+          do
+            c = buf [ctr++];
+          while (c != '\n' && c != -1);
+          gbl++;
+          break;
+
+        case '/':
+          {
+            int prevc;
+            c = buf [ctr++];
+            if (c != '*')
+              abort ();
+
+            prevc = 0;
+            while ((c = buf[ctr++]) && c != -1)
+              {
+                if (c == '\n')
+                  gbl++;
+              }
+            break;
+          }
+        default:
+          return c;
+        }
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42172-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42172-1.c
new file mode 100644
index 000000000..207f6001f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42172-1.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O2" }  */
+
+struct A {
+  unsigned int f1 : 3;
+  unsigned int f2 : 3;
+  unsigned int f3 : 1;
+  unsigned int f4 : 1;
+
+};
+
+void init_A (struct A *this)
+{
+  this->f1 = 0;
+  this->f2 = 1;
+  this->f3 = 0;
+  this->f4 = 0;
+}
+
+/* { dg-final { scan-assembler-times "ldr" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42235.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42235.c
new file mode 100644
index 000000000..582c8a2d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42235.c
@@ -0,0 +1,11 @@
+/* { dg-options "-mthumb -O2" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*r.,\[\\t \]*\#1" } } */
+/* { dg-final { scan-assembler-not "add\[\\t \]*r.,\[\\t \]*\#1" } } */
+
+#include <string.h>
+
+int foo (char *x)
+{
+  memset (x, 0, 6);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42495.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42495.c
new file mode 100644
index 000000000..7e08cf298
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42495.c
@@ -0,0 +1,31 @@
+/* { dg-options "-mthumb -Os -fpic -fdump-rtl-hoist" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-require-effective-target fpic } */
+/* Make sure all calculations of gObj's address get hoisted to one location.  */
+/* { dg-final { scan-rtl-dump "PRE/HOIST: end of bb .* copying expression" "hoist" } } */
+
+struct st_a {
+   int data;
+};
+
+struct st_b {
+   struct st_a *p_a;
+    struct st_b *next;
+};
+
+extern struct st_b gObj;
+extern void foo(int, struct st_b*);
+
+int goo(struct st_b * obj) {
+   struct st_a *pa;
+   if (gObj.p_a->data != 0) {
+     foo(gObj.p_a->data, obj);
+   }
+   pa = obj->p_a;
+   if (pa == 0) {
+     return 0;
+   } else if (pa == gObj.p_a) {
+     return 0;
+   }
+   return pa->data;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42496.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42496.c
new file mode 100644
index 000000000..c6d8a1f39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42496.c
@@ -0,0 +1,16 @@
+/* { dg-options "-O2" }  */
+
+void foo(int i)
+{
+    extern int j;
+
+    if (i) {
+         j = 10;
+    }
+    else {
+          j = 20;
+    }
+}
+
+/* { dg-final { scan-assembler-not "strne" } } */
+/* { dg-final { scan-assembler-not "streq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42505.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42505.c
new file mode 100644
index 000000000..5ddfea1da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42505.c
@@ -0,0 +1,22 @@
+/* { dg-options "-Os" }  */
+/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */
+
+struct A {
+ int f1;
+ int f2;
+};
+
+int func(int c);
+
+/* This function should not need to spill anything to the stack.  */
+int test(struct A* src, struct A* dst, int count)
+{
+  while (count--) {
+    if (!func(src->f2)) {
+        return 0;
+      }
+      *dst++ = *src++;
+  }
+
+  return 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42574.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42574.c
new file mode 100644
index 000000000..0ccd05f99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42574.c
@@ -0,0 +1,24 @@
+/* { dg-options "-mthumb -Os -fpic" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-require-effective-target fpic } */
+/* Make sure the address of glob.c is calculated only once and using
+   a logical shift for the offset (200<<1).  */
+/* { dg-final { scan-assembler-times "lsl" 1 } } */
+
+struct A {
+ char a[400];
+ float* c;
+};
+struct A glob;
+void func();
+void func1(float*);
+int func2(float*, int*);
+void func3(float*);
+
+void test(int *p) {
+ func1(glob.c);
+ if (func2(glob.c, p)) {
+   func();
+ }
+ func3(glob.c);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42575.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42575.c
new file mode 100644
index 000000000..1998e323d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42575.c
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" }  */
+/* Make sure RA does good job allocating registers and avoids
+   unnecessary moves.  */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+long long longfunc(long long x, long long y)
+{
+      return x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42835.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42835.c
new file mode 100644
index 000000000..867dd0287
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42835.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os -fno-tree-tail-merge" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+int foo(int *p, int i)
+{
+  return( (i < 0 && *p == 1)
+	  || (i > 0 && *p == 2) );
+}
+
+/* { dg-final { scan-assembler-times "movne\[\\t \]*r.,\[\\t \]*#" 1 } } */
+/* { dg-final { scan-assembler-times "moveq\[\\t \]*r.,\[\\t \]*#" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42879.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42879.c
new file mode 100644
index 000000000..9fcdad694
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr42879.c
@@ -0,0 +1,19 @@
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-final { scan-assembler "lsls" } } */
+
+struct A
+{
+#ifdef __ARMEB__
+  int dummy:31;
+#endif
+  int v:1;
+};
+
+int bar();
+int foo(struct A* p)
+{
+  if (p->v)
+    return 1;
+  return bar();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43137.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43137.c
new file mode 100644
index 000000000..3fb381227
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43137.c
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" }  */
+/* { dg-final { scan-assembler-not "mov\tr1, r\[1-9\]" } } */
+
+int foo();
+long long bar22()
+{
+  int result = foo();
+  return result;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43597.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43597.c
new file mode 100644
index 000000000..af382ba72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43597.c
@@ -0,0 +1,28 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os -save-temps -mthumb" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+extern int bar ();
+extern void bar2 (int);
+
+int
+foo4 ()
+{
+  int result = 0;
+  int f = -1;
+  f = bar ();
+  if (f < 0)
+    {
+      result = 1;
+      goto bail;
+    }
+  bar ();
+ bail:
+  bar2 (f);
+  return result;
+}
+
+/* { dg-final { scan-assembler-times "sub" 1 } } */
+/* { dg-final { scan-assembler-times "cmp" 0 } } */
+/* { dg-final { object-size text <= 30 } } */
+/* { dg-final { cleanup-saved-temps "pr43597" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43698.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43698.c
new file mode 100644
index 000000000..1fc497c22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43698.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-Os" } */
+#include <stdint.h>
+#include <stdlib.h>
+
+
+char do_reverse_endian = 0;
+
+#  define bswap_32(x) \
+  ((((x) & 0xff000000) >> 24) | \
+   (((x) & 0x00ff0000) >>  8) | \
+   (((x) & 0x0000ff00) <<  8) | \
+   (((x) & 0x000000ff) << 24))
+
+#define EGET(X) \
+  (__extension__ ({ \
+      uint64_t __res; \
+      if (!do_reverse_endian) {    __res = (X); \
+      } else if (sizeof(X) == 4) { __res = bswap_32((X)); \
+      } \
+      __res; \
+    }))
+
+void __attribute__((noinline)) X(char **phdr, char **data, int *phoff)
+{
+  *phdr = *data + EGET(*phoff);
+}
+
+int main()
+{
+  char *phdr;
+  char *data = (char *)0x40164000;
+  int phoff = 0x34;
+  X(&phdr, &data, &phoff);
+  if (phdr != (char *)0x40164034)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-1.c
new file mode 100644
index 000000000..d673f1e88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+int
+f (int start, int end, int *start_)
+{
+  if (start == -1 || end == -1)
+    return -1;
+
+  if (end - start)
+    return -1;
+
+  *start_ = start;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "\torr" 0 } } */
+/* { dg-final { scan-assembler-times "\tit\t" 0 } } */
+/* { dg-final { scan-assembler "\tbeq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-2.c
new file mode 100644
index 000000000..f647165bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr43920-2.c
@@ -0,0 +1,30 @@
+/* { dg-do assemble } */
+/* { dg-options "-mthumb -Os -save-temps" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+#include <stdio.h>
+
+int getFileStartAndLength (int fd, int *start_, size_t *length_)
+{
+      int start, end;
+      size_t length;
+
+      start = lseek (fd, 0L, SEEK_CUR);
+      end = lseek (fd, 0L, SEEK_END);
+
+      if (start == -1 || end == -1)
+         return -1;
+
+      length = end - start;
+      if (length == 0)
+         return -1;
+
+      *start_ = start;
+      *length_ = length;
+
+      return 0;
+}
+
+/* { dg-final { scan-assembler-times "pop" 2 } } */
+/* { dg-final { scan-assembler-times "beq" 3 } } */
+/* { dg-final { object-size text <= 54 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44788.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44788.c
new file mode 100644
index 000000000..eb4bc11af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44788.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-Os -fno-strict-aliasing -fPIC -mthumb -march=armv7-a -mfpu=vfp3 -mfloat-abi=softfp" } */
+
+void joint_decode(float* mlt_buffer1, int t) {
+    int i;
+    float decode_buffer[1060];
+    foo(decode_buffer);
+    for (i=0; i<10 ; i++) {
+        mlt_buffer1[i] = i * decode_buffer[t];
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44999.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44999.c
new file mode 100644
index 000000000..d07dca1a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr44999.c
@@ -0,0 +1,9 @@
+/* Use UXTB to extract the lowest byte.  */
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "uxtb" } } */
+
+int tp(int x, int y)
+{
+  return (x & 0xff) - (y & 0xffff);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45094.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45094.c
new file mode 100644
index 000000000..f35e7bb2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45094.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2 -mcpu=cortex-a8" } */
+/* { dg-add-options arm_neon } */
+
+#include <stdlib.h>
+
+long long buffer[32];
+
+void __attribute__((noinline)) f(long long *p, int n)
+{
+  while (--n >= 0)
+    {
+      *p = 1;
+      p += 32;
+    }
+}
+
+int main(void)
+{
+  f(buffer, 1);
+  
+  if (!buffer[0])
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45447.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45447.c
new file mode 100644
index 000000000..cb4a44275
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45447.c
@@ -0,0 +1,3 @@
+/* { dg-do compile } */
+/* { dg-options "-g -femit-struct-debug-baseonly" } */
+typedef __builtin_va_list x;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-1.c
new file mode 100644
index 000000000..2c690d5bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-final { scan-assembler "push\t\{r3" } } */
+/* { dg-final { scan-assembler-not "r8" } } */
+
+extern int hist_verify;
+extern char *pre_process_line (char*);
+extern char* str_cpy (char*, char*);
+extern int str_len (char*);
+extern char* x_malloc (int);
+#define savestring(x) (char *)str_cpy (x_malloc (1 + str_len (x)), (x))
+
+char *
+history_expand_line_internal (char* line)
+{
+  char *new_line;
+  int old_verify;
+
+  old_verify = hist_verify;
+  hist_verify = 0;
+  new_line = pre_process_line (line);
+  hist_verify = old_verify;
+  return (new_line == line) ? savestring (line) : new_line;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-2.c
new file mode 100644
index 000000000..ee1ee7df0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-final { scan-assembler "push\t\{r3" } } */
+/* { dg-final { scan-assembler-not "r8" } } */
+
+extern int hist_verify;
+extern char *pre_process_line (char*);
+extern char* savestring1 (char*, char*);
+extern char* str_cpy (char*, char*);
+extern int str_len (char*);
+extern char* x_malloc (int);
+#define savestring(x) (char *)str_cpy (x_malloc (1 + str_len (x)), (x))
+
+char *
+history_expand_line_internal (char* line)
+{
+  char *new_line;
+  int old_verify;
+
+  old_verify = hist_verify;
+  hist_verify = 0;
+  new_line = pre_process_line (line);
+  hist_verify = old_verify;
+  /* Two tail calls here, but r3 is not used to pass values.  */
+  return (new_line == line) ? savestring (line) : savestring1 (new_line, line);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-3.c
new file mode 100644
index 000000000..452c398f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr45701-3.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-final { scan-assembler "push\t.*r8" } } */
+/* { dg-final { scan-assembler-not "push\t*r3" } } */
+
+extern int hist_verify;
+extern char *pre_process_line (char*);
+extern char* savestring1 (char*, char*, int, int);
+extern char* str_cpy (char*, char*);
+extern int str_len (char*);
+extern char* x_malloc (int);
+#define savestring(x) (char *)str_cpy (x_malloc (1 + str_len (x)), (x))
+
+char *
+history_expand_line_internal (char* line)
+{
+  char *new_line;
+  int old_verify;
+
+  old_verify = hist_verify;
+  hist_verify = 0;
+  new_line = pre_process_line (line);
+  hist_verify = old_verify;
+  /* Two tail calls here, but r3 is used to pass values.  */
+  return (new_line == line) ? savestring (line) : 
+    savestring1 (new_line, line, 0, old_verify+1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46329.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46329.c
new file mode 100644
index 000000000..9dd939c7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46329.c
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+int __attribute__ ((vector_size (32))) x;
+void
+foo (void)
+{
+  x <<= x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46631.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46631.c
new file mode 100644
index 000000000..6f6dc4e85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46631.c
@@ -0,0 +1,16 @@
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "ands" } } */
+
+struct S {
+      int bi_buf;
+      int bi_valid;
+};
+
+int tz (struct S* p, int bits, int value)
+{
+     if (p == 0) return 1;
+      p->bi_valid = bits;
+      p->bi_buf = value & ((1 << bits) - 1);
+      return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46788.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46788.c
new file mode 100644
index 000000000..223676946
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46788.c
@@ -0,0 +1,26 @@
+/* { dg-options "-mthumb -O2" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler-not "-32768" } } */
+
+typedef union
+{
+  unsigned long int u_32_value;
+  struct 
+  {
+    unsigned short int u_16_value_0;
+    unsigned short int u_16_value_1;
+  } u_16_values;
+} my_union;
+
+
+unsigned long int Test(const unsigned short int wXe)
+{
+  my_union dwCalcVal;
+  
+  dwCalcVal.u_16_values.u_16_value_0=wXe;
+  dwCalcVal.u_16_values.u_16_value_1=0x8000u;
+
+  dwCalcVal.u_32_value /=3;
+  
+  return (dwCalcVal.u_32_value);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975-2.c
new file mode 100644
index 000000000..f4017e3f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975-2.c
@@ -0,0 +1,10 @@
+/* { dg-options "-mthumb -O2" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "sub" } } */
+/* { dg-final { scan-assembler "clz" } } */
+/* { dg-final { scan-assembler "lsr.*#5" } } */
+
+int foo (int s)
+{
+      return s == 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975.c
new file mode 100644
index 000000000..60d773b1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr46975.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "subs" } } */
+/* { dg-final { scan-assembler "adcs" } } */
+
+int foo (int s)
+{
+      return s == 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48183.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48183.c
new file mode 100644
index 000000000..f021825b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48183.c
@@ -0,0 +1,25 @@
+/* testsuite/gcc.target/arm/pr48183.c */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O -g" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+void move_16bit_to_32bit (int32_t *dst, const short *src, unsigned n)
+{
+    unsigned i;
+    int16x4x2_t input;
+    int32x4x2_t mid;
+    int32x4x2_t output;
+
+    for (i = 0; i < n/2; i += 8) {
+        input = vld2_s16(src + i);
+        mid.val[0] = vmovl_s16(input.val[0]);
+        mid.val[1] = vmovl_s16(input.val[1]);
+        output.val[0] = vshlq_n_s32(mid.val[0], 8);
+        output.val[1] = vshlq_n_s32(mid.val[1], 8);
+        vst2q_s32((int32_t *)dst + i, output);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c
new file mode 100644
index 000000000..17f729bb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr48252.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include <stdlib.h>
+
+int main(void)
+{
+    uint8_t v1_init[8] = {1, 1, 1, 1, 1, 1, 1, 1};
+    uint8_t v2_init[8] = {2, 2, 2, 2, 2, 2, 2, 2};
+    uint8x8_t v1 = vld1_u8 (v1_init);
+    uint8x8_t v2 = vld1_u8 (v2_init);
+    uint8x8x2_t vd1, vd2;
+    union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4;
+    int i;
+    uint8_t odd, even;
+
+    vd1 = vzip_u8(v1, vdup_n_u8(0));
+    vd2 = vzip_u8(v2, vdup_n_u8(0));
+
+    vst1_u8(d1.buf, vd1.val[0]);
+    vst1_u8(d2.buf, vd1.val[1]);
+    vst1_u8(d3.buf, vd2.val[0]);
+    vst1_u8(d4.buf, vd2.val[1]);
+
+#ifdef __ARMEL__
+    odd = 1;
+    even = 0;
+#else
+    odd = 0;
+    even = 1;
+#endif
+
+    for (i = 0; i < 8; i++)
+      if ((i % 2 == even && d4.buf[i] != 2)
+          || (i % 2 == odd && d4.buf[i] != 0))
+         abort ();
+
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr49641.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr49641.c
new file mode 100644
index 000000000..7f9b3769c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr49641.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -O2" } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "stmia\[\\t \]*r3!\[^\\n]*r3" } } */
+typedef struct {
+  void *t1, *t2, *t3;
+} z;
+extern volatile int y;
+static inline void foo(z *x) {
+  x->t1 = &x->t2;
+  x->t2 = ((void *)0);
+  x->t3 = &x->t1;
+}
+extern z v;
+void bar (void) {
+   y = 0;
+   foo(&v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50099.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50099.c
new file mode 100644
index 000000000..c0d143dd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50099.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long long foo (signed char * arg)
+{
+  long long temp_1;
+
+  temp_1 = arg[256]; 
+  return temp_1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50305.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50305.c
new file mode 100644
index 000000000..2f6ad5cfe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50305.c
@@ -0,0 +1,60 @@
+/* { dg-do compile } */
+/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "-march=armv7-a" } } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -marm -march=armv7-a -mfpu=vfp3" } */
+
+struct event {
+ unsigned long long id;
+ unsigned int flag;
+};
+
+void dummy(void)
+{
+  /* This is here to ensure that the offset of perf_event_id below
+     relative to the LANCHOR symbol exceeds the allowed displacement.  */
+  static int __warned[300];
+ __warned[0] = 1;
+}
+
+extern void *kmem_cache_alloc_trace (void *cachep);
+extern void *cs_cachep;
+extern int nr_cpu_ids;
+
+struct event *
+event_alloc (int cpu)
+{
+ static unsigned long long __attribute__((aligned(8))) perf_event_id;
+ struct event *event;
+ unsigned long long result;
+ unsigned long tmp;
+
+ if (cpu >= nr_cpu_ids)
+  return 0;
+
+ event = kmem_cache_alloc_trace (cs_cachep);
+
+ __asm__ __volatile__ ("dmb" : : : "memory");
+
+ __asm__ __volatile__("@ atomic64_add_return\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	adds	%0, %0, %4\n"
+"	adc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
+"	teq	%1, #0\n"
+"	bne	1b"
+ : "=&r" (result), "=&r" (tmp), "+Qo" (perf_event_id)
+ : "r" (&perf_event_id), "r" (1LL)
+ : "cc");
+
+ __asm__ __volatile__ ("dmb" : : : "memory");
+
+ event->id = result;
+
+ if (cpu)
+  event->flag = 1;
+
+ for (cpu = 0; cpu < nr_cpu_ids; cpu++)
+   kmem_cache_alloc_trace (cs_cachep);
+
+ return event;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50318-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50318-1.c
new file mode 100644
index 000000000..be270eefa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr50318-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+long long test (unsigned int sec, unsigned long long nsecs)
+{
+   return (long long)(long)sec * 1000000000L + (long long)(unsigned
+   long)nsecs;
+}
+
+/* { dg-final { scan-assembler "smlal" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51835.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51835.c
new file mode 100644
index 000000000..6d462d915
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51835.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */
+/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "avoid conflicting -mfpu" { *-*-* } { "-mfpu=*" } { "-mfpu=fpv4-sp-d16" "-mfpu=vfpv3xd" "-mfpu=vfpv3xd-fp16" } } */
+/* { dg-options "-O2 -march=armv7-a -mfloat-abi=hard -mfpu=fpv4-sp-d16" }  */
+
+int func1 (double d)
+{
+  return (int)d;
+}
+unsigned int func2 (double d)
+{
+  return (unsigned int)d;
+}
+
+/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r0,\[\\t \]*r1,\[\\t \]*d0" 2 { target { arm_little_endian } } } } */
+/* { dg-final { scan-assembler-times "fmrrd\[\\t \]+r1,\[\\t \]*r0,\[\\t \]*d0" 2 { target { ! arm_little_endian } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51915.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51915.c
new file mode 100644
index 000000000..144d522f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51915.c
@@ -0,0 +1,15 @@
+/* PR target/51915 */
+/* { dg-do compile } */
+/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */
+/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2" } */
+
+struct S { int s1; void *s2; };
+struct T { struct S t1; unsigned long long t2; };
+struct S *foo (unsigned long long);
+
+struct S *
+bar (struct S *x)
+{
+  return foo (((struct T *) x)->t2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51968.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51968.c
new file mode 100644
index 000000000..f0506c267
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr51968.c
@@ -0,0 +1,32 @@
+/* PR target/51968 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv7-a -mfloat-abi=softfp -mfpu=neon" } */
+/* { dg-require-effective-target arm_neon_ok } */
+
+typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8)));
+typedef __builtin_neon_uqi uint8x8_t __attribute__ ((__vector_size__ (8)));
+typedef __builtin_neon_qi int8x16_t __attribute__ ((__vector_size__ (16)));
+typedef __builtin_neon_hi int16x8_t __attribute__ ((__vector_size__ (16)));
+typedef __builtin_neon_si int32x4_t __attribute__ ((__vector_size__ (16)));
+struct T { int8x8_t val[2]; };
+int y;
+
+void
+foo (int8x8_t z, int8x8_t x, int16x8_t b, int8x8_t n)
+{
+  if (y)
+    {
+      struct T m;
+      __builtin_neon_vuzpv8qi (&m.val[0], z, x);
+    }
+  for (;;)
+    {
+      int8x16_t g;
+      int8x8_t h, j, k;
+      struct T m;
+      j = __builtin_neon_vqmovunv8hi (b, 1);
+      g = __builtin_neon_vcombinev8qi (j, h);
+      k = __builtin_neon_vget_lowv16qi (g);
+      __builtin_neon_vuzpv8qi (&m.val[0], k, n);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52006.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52006.c
new file mode 100644
index 000000000..c274449ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52006.c
@@ -0,0 +1,21 @@
+/* PR target/52006 */
+/* { dg-do compile } */
+/* { dg-skip-if "avoid conflicts with multilib flags" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */
+/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2 -fPIC" } */
+
+unsigned long a;
+static int b;
+
+void
+foo (void)
+{
+  asm volatile ("" : "=r" (b));
+}
+
+void
+bar (float f)
+{
+  if (f < b / 100.0)
+    a = 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52375.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52375.c
new file mode 100644
index 000000000..0405c6685
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52375.c
@@ -0,0 +1,15 @@
+/* PR target/52375 */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -O -ftree-vectorize" } */
+
+struct C { int c, d; };
+
+unsigned
+foo (struct C *p)
+{
+  unsigned int b = 0, i;
+  for (i = 0; i < 64; i++)
+    b |= 0x80000000U >> p[i].c;
+  return b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52633.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52633.c
new file mode 100644
index 000000000..b904d59d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52633.c
@@ -0,0 +1,13 @@
+/* PR tree-optimization/52633 */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-march=armv7-a -mfloat-abi=softfp -mfpu=neon -O -ftree-vectorize" } */
+
+void
+test (unsigned short *x, signed char *y)
+{
+  int i;
+  for (i = 0; i < 32; i++)
+    x[i] = (short) (y[i] << 5);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52686.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52686.c
new file mode 100644
index 000000000..66cbc575e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr52686.c
@@ -0,0 +1,19 @@
+/* PR target/52375 */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-march=armv7-a -mfloat-abi=softfp -mfpu=neon -O -ftree-vectorize" } */
+
+unsigned int output[4];
+
+void test (unsigned short *p)
+{
+  unsigned int x = *p;
+  if (x)
+    {
+      output[0] = x << 1;
+      output[1] = x << 1;
+      output[2] = x << 1;
+      output[3] = x << 1;
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53187.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53187.c
new file mode 100644
index 000000000..b40dbbb31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53187.c
@@ -0,0 +1,15 @@
+/* PR target/53187 */
+/* { dg-do compile } */
+/* { dg-skip-if "no support for hard-float VFP ABI" { arm_thumb1 } { "-march=*" } { "" } } */
+/* { dg-skip-if "do not override -mfloat-abi" { *-*-* } { "-mfloat-abi=*" } { "-mfloat-abi=hard" } } */
+/* { dg-options "-march=armv7-a -mfloat-abi=hard -O2" } */
+
+void bar (int);
+
+void
+foo (int x, double y, double z)
+{
+  _Bool t = z >= y;
+  if (!t || x)
+    bar (t ? 1 : 16);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-1.c
new file mode 100644
index 000000000..dc094180c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-1.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+void t0p(long long * p)
+{
+  *p += 0x100000001;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-2.c
new file mode 100644
index 000000000..9a2b0315c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-2.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+void t0p(long long * p)
+{
+  *p -= 0x100000008;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-3.c
new file mode 100644
index 000000000..8e48f119b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-3.c
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+
+void t0p(long long * p)
+{
+  *p +=0x1fffffff8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-4.c
new file mode 100644
index 000000000..22acb9727
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53447-4.c
@@ -0,0 +1,9 @@
+/* { dg-options "-O2" }  */
+/* { dg-require-effective-target arm32 } */
+/* { dg-final { scan-assembler-not "mov" } } */
+
+
+void t0p(long long * p)
+{
+  *p -=0x1fffffff8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53636.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53636.c
new file mode 100644
index 000000000..dbad7957e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53636.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O -ftree-vectorize" } */
+/* { dg-add-options arm_neon } */
+
+void fill (short *buf) __attribute__ ((noinline));
+void fill (short *buf)
+{
+  int i;
+
+  for (i = 0; i < 11 * 8; i++)
+    buf[i] = i;
+}
+
+void test (unsigned char *dst) __attribute__ ((noinline));
+void test (unsigned char *dst)
+{
+  short tmp[11 * 8], *tptr;
+  int i;
+
+  fill (tmp);
+
+  tptr = tmp;
+  for (i = 0; i < 8; i++)
+    {
+      dst[0] = (-tptr[0] + 9 * tptr[0 + 1] + 9 * tptr[0 + 2] - tptr[0 + 3]) >> 7;
+      dst[1] = (-tptr[1] + 9 * tptr[1 + 1] + 9 * tptr[1 + 2] - tptr[1 + 3]) >> 7;
+      dst[2] = (-tptr[2] + 9 * tptr[2 + 1] + 9 * tptr[2 + 2] - tptr[2 + 3]) >> 7;
+      dst[3] = (-tptr[3] + 9 * tptr[3 + 1] + 9 * tptr[3 + 2] - tptr[3 + 3]) >> 7;
+      dst[4] = (-tptr[4] + 9 * tptr[4 + 1] + 9 * tptr[4 + 2] - tptr[4 + 3]) >> 7;
+      dst[5] = (-tptr[5] + 9 * tptr[5 + 1] + 9 * tptr[5 + 2] - tptr[5 + 3]) >> 7;
+      dst[6] = (-tptr[6] + 9 * tptr[6 + 1] + 9 * tptr[6 + 2] - tptr[6 + 3]) >> 7;
+      dst[7] = (-tptr[7] + 9 * tptr[7 + 1] + 9 * tptr[7 + 2] - tptr[7 + 3]) >> 7;
+
+      dst += 8;
+      tptr += 11;
+    }
+}
+
+int main (void)
+{
+  char buf [8 * 8];
+
+  test (buf);
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53859.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53859.c
new file mode 100644
index 000000000..003489e0b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr53859.c
@@ -0,0 +1,11 @@
+/* PR target/53859 */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-mcpu=cortex-m4 -mthumb -O2" } */
+
+void bar (int,int,char* ,int);
+
+void foo (char c)
+{
+    bar (1,2,&c,3);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54051.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54051.c
new file mode 100644
index 000000000..1d2e93c89
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54051.c
@@ -0,0 +1,20 @@
+/* { dg-do assemble }  */
+/* { dg-require-effective-target arm_neon }  */
+/* { dg-options "-O2" }  */
+/* { dg-add-options arm_neon }  */
+
+#include <arm_neon.h>
+
+int32_t a __attribute__ ((aligned (64)));
+
+int32x2x3_t test (void)
+{
+  return vld3_dup_s32 (&a);
+}
+
+int32x2x3_t test1 (void)
+{
+  int32x2x3_t res ;
+  return vld3_lane_s32 (&a, res, 1);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54300.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54300.C
new file mode 100644
index 000000000..eb1a74e36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54300.C
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+#include <stdlib.h>
+
+struct __attribute__ ((aligned(8))) _v16u8_ {
+  uint8x16_t val;
+  _v16u8_( const int16x8_t &src) { val = vreinterpretq_u8_s16(src); }
+  operator int16x8_t () const { return vreinterpretq_s16_u8(val); }
+};
+typedef struct _v16u8_ v16u8;
+
+struct __attribute__ ((aligned(4))) _v8u8_ {
+  uint8x8_t val;
+  _v8u8_( const uint8x8_t &src) { val = src; }
+  operator int16x4_t () const { return vreinterpret_s16_u8(val); }
+};
+typedef struct _v8u8_ v8u8;
+
+typedef v16u8                v8i16;
+typedef int32x4_t            v4i32;
+typedef const short         cv1i16;
+typedef const unsigned char cv1u8;
+typedef const v8i16         cv8i16;
+
+static inline __attribute__((always_inline)) v8u8 zero_64(){ return vdup_n_u8( 0 ); }
+
+static inline __attribute__((always_inline)) v8i16 loadlo_8i16( cv8i16* p ){
+  return vcombine_s16( vld1_s16( (cv1i16 *)p ), zero_64() );
+}
+static inline __attribute__((always_inline)) v8i16 _loadlo_8i16( cv8i16* p, int offset ){
+  return loadlo_8i16( (cv8i16*)(&((cv1u8*)p)[offset]) );
+}
+
+void __attribute__((noinline))
+test(unsigned short *_Inp, int32_t *_Out,
+     unsigned int s1v, unsigned int dv0,
+     unsigned int smask_v)
+{
+  int32x4_t c = vdupq_n_s32(0);
+
+  for(unsigned int sv=0 ; sv!=dv0 ; sv=(sv+s1v)&smask_v )
+    {
+      int32x4_t s;
+      s = vmovl_s16( vget_low_s16( _loadlo_8i16( (cv8i16*) _Inp, sv ) ) );
+      c = vaddq_s32( c, s );
+    }
+  vst1q_s32( _Out, c );
+}
+
+main()
+{
+  unsigned short a[4] = {1, 2, 3, 4};
+  int32_t b[4] = {0, 0, 0, 0};
+  test(a, b, 1, 1, ~0);
+  if (b[0] != 1 || b[1] != 2 || b[2] != 3 || b[3] != 4)
+    abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54892.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54892.c
new file mode 100644
index 000000000..a7fe1bc66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr54892.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+
+int set_role(unsigned char role_id, short m_role)
+{
+  return __sync_bool_compare_and_swap(&m_role, -1, role_id);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55073.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55073.C
new file mode 100644
index 000000000..5575cf779
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55073.C
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+#include <stdlib.h>
+
+struct __attribute__((aligned(16))) _v16u8_ {
+	uint8x16_t val;
+	_v16u8_() { }
+
+	_v16u8_( const  uint8x16_t &src) { val = src; }
+	_v16u8_( const   int16x8_t &src) { val = vreinterpretq_u8_s16(src); }
+	_v16u8_( const  uint32x4_t &src) { val = vreinterpretq_u8_u32(src); }
+
+	operator  uint8x16_t () const { return val; }
+	operator   int8x16_t () const { return vreinterpretq_s8_u8 (val); }
+	operator   int16x8_t () const { return vreinterpretq_s16_u8(val); }
+	operator  uint32x4_t () const { return vreinterpretq_u32_u8(val); }
+	operator   int32x4_t () const { return vreinterpretq_s32_u8(val); }
+};
+typedef struct _v16u8_ v16u8;
+typedef const v16u8 cv16u8;
+
+typedef v16u8 v16i8;
+typedef v16u8 v8i16;
+typedef v16u8 v4u32;
+
+inline v16u8 __attribute__((always_inline)) mergelo( const v16u8 & s, const v16u8 & t )
+{
+	uint8x8x2_t r = vzip_u8( vget_low_u8(s), vget_low_u8(t) );
+	return vcombine_u8( r.val[0], r.val[1] );
+}
+
+inline v8i16 __attribute__((always_inline)) unpacklo(const v16i8 & s)
+{
+	return vmovl_s8( vget_low_s8( s ) );
+}
+
+const uint32_t __attribute__((aligned(16))) _InA [4] = { 0xFF020001, 0xFF020001, 0xFF000101, 0xFF000101 } ;
+const uint32_t __attribute__((aligned(16))) _InB [4] = { 0xFF050002, 0xFF050002, 0xFF000303, 0xFF000203 } ;
+
+__attribute__((noinline)) v16i8 test_func(void)
+{
+	v16u8 A = vld1q_u8( (uint8_t*) _InA );
+	v16u8 B = vld1q_u8( (uint8_t*) _InB );
+	v8i16 r   = vdupq_n_s16(2);
+
+	v16u8 _0 = mergelo( A, B );
+	v16u8 _1 = mergelo( B, A );
+
+	v16u8 _2 = mergelo( _0, _1 );
+	v16u8 _3 = mergelo( _1, _0 );
+
+	v8i16 _4 = vsubq_s16( unpacklo( _2 ), r );
+	v8i16 _5 = vsubq_s16( unpacklo( _3 ), r );
+
+	v8i16 ret = vaddq_s16( _4, _5 );
+
+	return ( ret );
+}
+
+int main (int argc, char **argv)
+{
+	v16u8 val = test_func();
+
+	if (vgetq_lane_u32( val, 0 ) != 0xffffffff
+	    || vgetq_lane_u32( val, 1 ) != 0xffffffff
+	    || vgetq_lane_u32( val, 2 ) != 0xfffcfffc
+	    || vgetq_lane_u32( val, 3 ) != 0xfffcfffc)
+	  abort ();
+	exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55642.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55642.c
new file mode 100644
index 000000000..10f2daa25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr55642.c
@@ -0,0 +1,15 @@
+/* { dg-options "-mthumb -O2" }  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+int
+foo (int v)
+{
+  register int i asm ("r0");
+  register int j asm ("r1");
+  if (v > 1)
+    i = abs (j);
+
+  return i;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C
new file mode 100644
index 000000000..d44c1b432
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56184.C
@@ -0,0 +1,257 @@
+/* { dg-do compile } */
+/* { dg-options "-fno-short-enums -O2 -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=softfp -mtune=cortex-a9 -fno-section-anchors" } */
+
+typedef unsigned int size_t;
+__extension__ typedef int __intptr_t;
+typedef __intptr_t intptr_t;
+typedef union tree_node *tree;
+typedef const union tree_node *const_tree;
+extern void *ggc_internal_cleared_alloc_stat (size_t )
+  __attribute__ ((__malloc__));
+enum tree_code {
+TREE_LIST=2,
+FUNCTION_DECL,
+MAX_TREE_CODES=254
+};
+extern unsigned char tree_contains_struct[MAX_TREE_CODES][64];
+struct tree_base {
+  enum tree_code code : 16;
+};
+struct tree_common {
+  tree chain;
+};
+enum tree_node_structure_enum {
+TS_COMMON,
+TS_DECL_COMMON,
+};
+extern void tree_contains_struct_check_failed (const_tree,
+            const enum tree_node_structure_enum,
+            const char *, int, const char *)
+  __attribute__ ((__noreturn__));
+extern void tree_check_failed (const_tree, const char *, int, const char *,
+          ...) __attribute__ ((__noreturn__));
+struct tree_list {
+  tree value;
+};
+struct tree_decl_common {
+  tree initial;
+};
+struct tree_function_decl {
+  struct function *f;
+};
+union
+                                                         tree_node {
+  struct tree_base base;
+  struct tree_common common;
+  struct tree_decl_common decl_common;
+  struct tree_function_decl function_decl;
+  struct tree_list list;
+};
+inline tree
+tree_check (tree __t, const char *__f, int __l, const char *__g, enum tree_code __c)
+{
+  if (((enum tree_code) (__t)->base.code) != __c)
+    tree_check_failed (__t, __f, __l, __g, __c, 0);
+}
+inline tree
+contains_struct_check (tree __t, const enum tree_node_structure_enum __s,
+                       const char *__f, int __l, const char *__g)
+{
+  if (tree_contains_struct[((enum tree_code) (__t)->base.code)][__s] != 1)
+      tree_contains_struct_check_failed (__t, __s, __f, __l, __g);
+}
+struct function {
+  tree static_chain_decl;
+};
+enum gimple_code {
+    LAST_AND_UNUSED_GIMPLE_CODE
+};
+struct eh_catch_d
+{
+  struct eh_catch_d *next_catch;
+  struct eh_catch_d *prev_catch;
+  tree type_list;
+  tree filter_list;
+  tree label;
+};
+struct eh_region_d
+{
+  struct eh_region_d *outer;
+  struct eh_region_d *inner;
+  int index;
+  union eh_region_u {
+    struct eh_region_u_try {
+      struct eh_catch_d *first_catch;
+    } eh_try;
+  } u;
+};
+typedef struct eh_catch_d *eh_catch;
+typedef struct eh_region_d *eh_region;
+extern void add_type_for_runtime (tree);
+enum LTO_tags
+{
+  LTO_null = 0,
+  LTO_bb0 = 1 + MAX_TREE_CODES + LAST_AND_UNUSED_GIMPLE_CODE,
+  LTO_ert_cleanup,
+  LTO_NUM_TAGS
+};
+enum lto_section_type
+{
+  LTO_section_function_body,
+};
+struct lto_input_block
+{
+  const char *data;
+  unsigned int p;
+  unsigned int len;
+};
+extern void lto_section_overrun (struct lto_input_block *) __attribute__ ((__noreturn__));
+extern void lto_value_range_error (const char *,
+       long long, long long,
+       long long) __attribute__ ((__noreturn__));
+long long streamer_read_hwi (struct lto_input_block *);
+static inline unsigned char
+streamer_read_uchar (struct lto_input_block *ib)
+{
+  if (ib->p >= ib->len)
+    lto_section_overrun (ib);
+  return (ib->data[ib->p++]);
+}
+static inline long long
+streamer_read_hwi_in_range (struct lto_input_block *ib,
+     const char *purpose,
+     long long min,
+     long long max)
+{
+  long long range = max - min;
+  long long val = streamer_read_uchar (ib);
+  if (range >= 0xff)
+    val |= ((long long)streamer_read_uchar (ib)) << 8;
+  if (val < min || val > max)
+    lto_value_range_error (purpose, val, min, max);
+  return val;
+}
+static inline enum LTO_tags
+streamer_read_record_start (struct lto_input_block *ib)
+{
+  return (enum LTO_tags)streamer_read_hwi_in_range ((ib), "LTO_tags", 0, (int)(LTO_NUM_TAGS) - 1);
+}
+struct streamer_hooks {
+  tree (*read_tree) (struct lto_input_block *, struct data_in *);
+};
+extern struct streamer_hooks streamer_hooks;
+static struct eh_catch_d *
+lto_input_eh_catch_list (struct lto_input_block *ib, struct data_in *data_in,
+    eh_catch *last_p)
+{
+  eh_catch first;
+  enum LTO_tags tag;
+  *last_p = first = __null;
+  tag = streamer_read_record_start (ib);
+  while (tag)
+    {
+      tree list;
+      eh_catch n;
+      n = ((struct eh_catch_d *)(ggc_internal_cleared_alloc_stat (sizeof (struct eh_catch_d) )));
+      n->type_list = streamer_hooks.read_tree(ib, data_in);
+      n->filter_list = streamer_hooks.read_tree(ib, data_in);
+      n->label = streamer_hooks.read_tree(ib, data_in);
+      for (list = n->filter_list; list; list = ((contains_struct_check ((list), (TS_COMMON), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 275, __FUNCTION__))->common.chain))
+ add_type_for_runtime (((tree_check ((list), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 276, __FUNCTION__, (TREE_LIST)))->list.value));
+      if (*last_p)
+ (*last_p)->next_catch = n;
+      n->prev_catch = *last_p;
+      *last_p = n;
+      if (first == __null)
+ first = n;
+      tag = streamer_read_record_start (ib);
+    }
+  return first;
+}
+static eh_region
+input_eh_region (struct lto_input_block *ib, struct data_in *data_in, int ix)
+{
+  enum LTO_tags tag;
+  eh_region r;
+  tag = streamer_read_record_start (ib);
+  if (tag == LTO_null)
+    return __null;
+  r = ((struct eh_region_d *)(ggc_internal_cleared_alloc_stat (sizeof (struct eh_region_d) )));
+  r->index = streamer_read_hwi (ib);
+  r->outer = (eh_region) (intptr_t) streamer_read_hwi (ib);
+  r->inner = (eh_region) (intptr_t) streamer_read_hwi (ib);
+  switch (tag)
+    {
+      case LTO_ert_cleanup:
+ {
+   struct eh_catch_d *last_catch;
+   r->u.eh_try.first_catch = lto_input_eh_catch_list (ib, data_in,
+            &last_catch);
+ }
+ {
+   tree l;
+     add_type_for_runtime (((tree_check ((l), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 346, __FUNCTION__, (TREE_LIST)))->list.value));
+ }
+    }
+}
+static void
+input_eh_regions (struct lto_input_block *ib, struct data_in *data_in,
+    struct function *fn)
+{
+  long long i, root_region, len;
+  enum LTO_tags tag;
+  tag = streamer_read_record_start (ib);
+  if (tag == LTO_null)
+    return;
+  len = streamer_read_hwi (ib);
+  if (len > 0)
+    {
+      for (i = 0; i < len; i++)
+ {
+   eh_region r = input_eh_region (ib, data_in, i);
+ }
+    }
+}
+static void
+input_ssa_names (struct lto_input_block *ib, struct data_in *data_in,
+   struct function *fn)
+{
+  unsigned int i, size;
+  while (i)
+    {
+    }
+}
+static void
+input_struct_function_base (struct function *fn, struct data_in *data_in,
+                            struct lto_input_block *ib)
+{
+  fn->static_chain_decl = streamer_hooks.read_tree(ib, data_in);
+}
+static void
+input_function (tree fn_decl, struct data_in *data_in,
+  struct lto_input_block *ib)
+{
+  struct function *fn;
+  enum LTO_tags tag;
+  fn = ((tree_check ((fn_decl), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 807, __FUNCTION__, (FUNCTION_DECL)))->function_decl.f);
+  tag = streamer_read_record_start (ib);
+  input_struct_function_base (fn, data_in, ib);
+  input_ssa_names (ib, data_in, fn);
+  input_eh_regions (ib, data_in, fn);
+  ((contains_struct_check ((fn_decl), (TS_DECL_COMMON), "../../../gcc-4.8~svn195526/gcc/lto-streamer-in.c", 823, __FUNCTION__))->decl_common.initial) = streamer_hooks.read_tree(ib, data_in);
+}
+static void
+lto_read_body (struct lto_file_decl_data *file_data, tree fn_decl,
+        const char *data, enum lto_section_type section_type)
+{
+  struct data_in *data_in;
+  struct lto_input_block ib_main;
+  input_function (fn_decl, data_in, &ib_main);
+}
+void
+lto_input_function_body (struct lto_file_decl_data *file_data,
+    tree fn_decl, const char *data)
+{
+  lto_read_body (file_data, fn_decl, data, LTO_section_function_body);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56732-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56732-1.c
new file mode 100644
index 000000000..ac8b8cf67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr56732-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target naked_functions } */
+/* { dg-options "-O2 -Wall" } */
+extern void bar();
+
+void __attribute__((__naked__))
+foo(void)
+{
+  bar ();
+}
+
+int __attribute__((naked))
+zoo (int a, int b, int c, int d, int e, int f)
+{
+  bar ();
+  return e;
+}
+/* Verify that __attribute__((naked)) produces a naked function that
+   does not use bx to return. */
+/* { dg-final { scan-assembler-not "\tbx\tlr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr57637.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr57637.c
new file mode 100644
index 000000000..2b9bfdded
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr57637.c
@@ -0,0 +1,206 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline" } */
+
+typedef struct _GtkCssStyleProperty GtkCssStyleProperty;
+
+struct _GtkCssStyleProperty
+{
+  int *initial_value;
+  unsigned int id;
+  unsigned int inherit :1;
+  unsigned int animated :1;
+  unsigned int affects_size :1;
+  unsigned int affects_font :1;
+
+  int * parse_value;
+  int * query_value;
+  int * assign_value;
+};
+
+void
+g_assertion_message_expr (const char *domain,
+			  const char *file,
+			  int line,
+			  const char *func,
+			  const char *expr) __attribute__((__noreturn__));
+
+void
+g_assertion_message_expr (const char *domain,
+			  const char *file,
+			  int line,
+			  const char *func,
+			  const char *expr)
+{
+  __builtin_abort ();
+}
+int
+get_id (GtkCssStyleProperty *property)
+{
+  return 1;
+}
+int
+_gtk_css_style_property_get_type ()
+{
+  return 1;
+}
+
+GtkCssStyleProperty *
+g_object_new (int object_type,
+            const char *first_property_name,
+            ...)
+{
+  return (GtkCssStyleProperty *) __builtin_malloc (sizeof (GtkCssStyleProperty));
+}
+
+typedef enum {
+  INHERIT = (1 << 0),
+  ANIMATED = (1 << 1),
+  RESIZE = (1 << 2),
+  FONT = (1 << 3)
+} GtkStylePropertyFlags;
+
+int t = 0;
+void
+gtk_css_style_property_register (const char * name,
+				 int expected_id,
+				 int value_type,
+				 int flags,
+				 int *parse_value,
+				 int *query_value,
+				 int *assign_value,
+				 int *initial_value)
+{
+  GtkCssStyleProperty *node;
+
+  do
+    {
+      if (__builtin_expect (__extension__ (
+					   {
+					     int _g_boolean_var_;
+					     if (initial_value != ((void *)0))
+					       _g_boolean_var_ = 1;
+					     else
+					       _g_boolean_var_ = 0;
+					     _g_boolean_var_;
+					   }),
+			    1))
+	;
+      else
+        g_assertion_message_expr ("Gtk",
+				  "gtkcssstylepropertyimpl.c",
+				  85,
+				  ((const char*) (__PRETTY_FUNCTION__)),
+				  "initial_value != NULL");
+    } while (0);
+
+  do
+    {
+      if (__builtin_expect (__extension__ (
+					   {
+					     int _g_boolean_var_;
+					     if (parse_value != ((void *)0))
+					       _g_boolean_var_ = 1;
+					     else
+					       _g_boolean_var_ = 0;
+					     _g_boolean_var_;
+					   }),
+			    1))
+	;
+      else
+	g_assertion_message_expr ("Gtk",
+				  "gtkcssstylepropertyimpl.c",
+				  86,
+				  ((const char*) (__PRETTY_FUNCTION__)),
+				  "parse_value != NULL");
+    } while (0);
+
+  do
+    {
+      if (__builtin_expect (__extension__ (
+					   {
+					     int _g_boolean_var_;
+					     if (value_type == ((int) ((1) << (2)))
+						 || query_value != ((void *)0))
+					       _g_boolean_var_ = 1;
+					     else
+					       _g_boolean_var_ = 0;
+					     _g_boolean_var_;
+					   }),
+			    1))
+	;
+      else
+	g_assertion_message_expr ("Gtk",
+				  "gtkcssstylepropertyimpl.c",
+				  87, ((const char*) (__PRETTY_FUNCTION__)),
+				  "value_type == NONE || query_value != NULL");
+    } while (0);
+
+  /* FLAGS is changed in a cond_exec instruction with pr57637.  */
+  if (flags  == 15)
+    t = 15;
+
+  do
+    {
+      if (__builtin_expect (__extension__ (
+					   {
+					     int _g_boolean_var_;
+					     if (value_type == ((1) << (2))
+						 || assign_value != ((void *)0))
+					       _g_boolean_var_ = 1;
+					     else
+					       _g_boolean_var_ = 0;
+					     _g_boolean_var_;
+					   }),
+			    1))
+	;
+      else
+	g_assertion_message_expr ("Gtk",
+				  "gtkcssstylepropertyimpl.c",
+				  88, ((const char*) (__PRETTY_FUNCTION__)),
+				  "value_type == NONE || assign_value != NULL");
+    } while (0);
+
+  node = g_object_new ((_gtk_css_style_property_get_type ()),
+			"value-type", value_type,
+			"affects-size", (flags & RESIZE) ? (0) : (!(0)),
+			"affects-font", (flags & FONT) ? (!(0)) : (0),
+			"animated", (flags & ANIMATED) ? (!(0)) : (0),
+			"inherit", (flags & INHERIT) ? (!(0)) : (0),
+			"initial-value", initial_value,
+			"name", name,
+			((void *)0));
+
+  node->parse_value = parse_value;
+  node->query_value = query_value;
+  node->assign_value = assign_value;
+
+  do
+    {
+      if (__builtin_expect (__extension__ (
+					   {
+					     int _g_boolean_var_;
+					     if (get_id (node) == expected_id)
+					       _g_boolean_var_ = 1;
+					     else
+					       _g_boolean_var_ = 0;
+					     _g_boolean_var_;
+					   }),
+			    1))
+	;
+      else
+	g_assertion_message_expr ("Gtk",
+				  "gtkcssstylepropertyimpl.c",
+				  106,
+				  ((const char*) (__PRETTY_FUNCTION__)),
+				  "get_id (node) == expected_id");
+    } while (0);
+}
+
+int main ()
+{
+  gtk_css_style_property_register ("test", 1, 4, 15, &t, &t, &t, &t);
+
+  if (t != 15)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58041.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58041.c
new file mode 100644
index 000000000..481a72b81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58041.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -mno-unaligned-access" } */
+/* { dg-final { scan-assembler "ldrb" } } */
+/* { dg-final { scan-assembler "strb" } } */
+
+struct s
+{
+  char u;
+  long long v[2];
+} __attribute__((packed,aligned(1)));
+
+__attribute__((noinline, noclone))
+long long foo(struct s *x, int y, long long z)
+{
+  long long a = x->v[y];
+  x->v[y] = z;
+  return a;
+}
+
+struct s a = {0,{0,0}};
+int main()
+{
+  if (foo(&a,0,1) != 0)
+    __builtin_abort();
+  if (foo(&a,0,2) != 1)
+    __builtin_abort();
+  if (foo(&a,1,1) != 0)
+    __builtin_abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58578.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58578.c
new file mode 100644
index 000000000..2b474f544
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58578.c
@@ -0,0 +1,54 @@
+
+/* PR target/58578 */
+/* { dg-do run } */
+/* { dg-options "-O1" } */
+
+#include <stdlib.h>
+
+typedef struct {
+    long _prec;
+    int _flag;
+    long _exp;
+} __my_st_t;
+
+typedef __my_st_t *__my_st_ptr;
+
+int
+_test_fn (__my_st_ptr y, const __my_st_ptr xt)
+{
+  int inexact;
+  if (xt->_exp != -2147483647L)
+    {
+      (y->_flag = xt->_flag);
+    }
+
+  do {
+      __my_st_ptr _y = y;
+      long _err1 = -2 * xt->_exp;
+      long _err2 = 2;
+      if (0 < _err1)
+	{
+	  unsigned long _err = (unsigned long) _err1 + _err2;
+	  if (__builtin_expect(!!(_err > _y->_prec + 1), 0))
+	    return 2;
+	  return 3;
+	}
+  } while (0);
+
+  return 0;
+}
+
+int main ()
+{
+  __my_st_t x, y;
+  long pz;
+  int inex;
+
+  x._prec = 914;
+  y._exp = 18;
+  if (_test_fn (&x, &y))
+    {
+      abort();
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c
new file mode 100644
index 000000000..e3ef950b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr58784.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv7-a -mfloat-abi=hard -mfpu=neon -marm -O2" } */
+
+typedef struct __attribute__ ((__packed__))
+{
+    char valueField[2];
+} ptp_tlv_t;
+typedef struct __attribute__ ((__packed__))
+{
+    char stepsRemoved;
+    ptp_tlv_t tlv[1];
+} ptp_message_announce_t;
+int ptplib_send_announce(int sequenceId, int i)
+{
+    ptp_message_announce_t tx_packet;
+    ((long long *)tx_packet.tlv[0].valueField)[sequenceId] = i;
+    f(&tx_packet);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59575.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59575.c
new file mode 100644
index 000000000..13494f463
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59575.c
@@ -0,0 +1,15 @@
+/* PR target/59575 */
+/* { dg-do compile } */
+/* { dg-options "-Os -g -march=armv7-a" } */
+
+void foo (int *);
+int *bar (int, long long, int);
+
+void
+test (int *p)
+{
+  if (p)
+    foo (p);
+  else if (p = bar (0, 1, 2))
+    foo (p);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59858.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59858.c
new file mode 100644
index 000000000..a944b9afa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59858.c
@@ -0,0 +1,163 @@
+/* { dg-do compile } */
+/* { dg-options "-march=armv5te -fno-builtin -mfloat-abi=soft -mthumb -fno-stack-protector -Os -fno-tree-loop-optimize -fno-tree-dominator-opts -fPIC -w" } */
+/* { dg-skip-if "Incompatible command line options: -mfloat-abi=soft -mfloat-abi=hard" { *-*-* } { "-mfloat-abi=hard" } { "" } } */
+
+typedef enum {
+ REG_ENOSYS = -1,
+} reg_errcode_t;
+typedef unsigned long int bitset_word_t;
+typedef bitset_word_t bitset_t[(256 / (sizeof (bitset_word_t) * 8))];
+typedef bitset_word_t *re_bitset_ptr_t;
+typedef const bitset_word_t *re_const_bitset_ptr_t;
+typedef struct {
+ int nelem;
+ int *elems;
+} re_node_set;
+typedef enum {
+ CHARACTER = 1,
+} re_token_type_t;
+typedef struct {
+ re_token_type_t type:8;
+ unsigned int word_char:1;
+} re_token_t;
+struct re_string_t {
+ const unsigned char *raw_mbs;
+ int raw_mbs_idx;
+ int cur_idx;
+ unsigned int tip_context;
+ re_const_bitset_ptr_t word_char;
+};
+typedef struct re_string_t re_string_t;
+typedef struct re_dfa_t re_dfa_t;
+struct re_dfastate_t {
+ re_node_set nodes;
+};
+typedef struct re_dfastate_t re_dfastate_t;
+typedef struct {
+ re_dfastate_t **array;
+} state_array_t;
+typedef struct {
+ state_array_t path;
+} re_sub_match_last_t;
+typedef struct {
+ int nlasts;
+ re_sub_match_last_t **lasts;
+} re_sub_match_top_t;
+typedef struct {
+ re_string_t input;
+ const re_dfa_t *dfa;
+ int nsub_tops;
+ re_sub_match_top_t **sub_tops;
+} re_match_context_t;
+struct re_dfa_t {
+ re_token_t *nodes;
+ re_bitset_ptr_t sb_char;
+ int mb_cur_max;
+ bitset_t word_char;
+} bracket_elem_t;
+static reg_errcode_t
+re_string_reconstruct (
+ re_string_t * pstr,
+ int idx,
+ int eflags
+)
+{
+ int offset = idx - pstr->raw_mbs_idx;
+ int c = pstr->raw_mbs[pstr->raw_mbs_idx + offset - 1];
+ pstr->tip_context = ((pstr->word_char[c] & ((bitset_word_t) 1)) ? : (c));
+}
+
+static void match_ctx_clean (
+ re_match_context_t *
+);
+static int check_matching (
+);
+static re_dfastate_t *transit_state (
+);
+static int build_trtable (
+);
+re_search_internal (int eflags
+)
+{
+ reg_errcode_t err;
+ int incr;
+ int
+  match_first,
+  match_last = -1;
+ re_match_context_t mctx;
+ err = re_string_allocate (&mctx.input);
+ for (;; match_first += incr)
+  {
+   err = re_string_reconstruct (&mctx.input, match_first, eflags);
+   err = re_string_reconstruct (&mctx.input, match_first, eflags);
+   match_last = check_matching (&mctx, &match_first);
+   match_ctx_clean (&mctx);
+  }
+}
+
+check_matching (re_match_context_t * mctx, int *p_match_first
+)
+{
+ int cur_str_idx = ((&mctx->input)->cur_idx);
+ re_dfastate_t *cur_state;
+ int next_start_idx = cur_str_idx;
+ cur_state = transit_state (mctx, cur_state);
+ *p_match_first += next_start_idx;
+}
+
+static re_dfastate_t *
+transit_state (
+ re_match_context_t * mctx,
+ re_dfastate_t * state
+)
+{
+ if (!build_trtable (mctx->dfa, state))
+  {
+  }
+}
+
+build_trtable (const re_dfa_t * dfa,
+	             re_dfastate_t * state
+)
+{
+ int i,
+  j;
+ bitset_t accepts;
+ const re_node_set *cur_nodes = &state->nodes;
+ for (i = 0; i < cur_nodes->nelem; ++i)
+  {
+   re_token_t *node = &dfa->nodes[cur_nodes->elems[i]];
+   re_token_type_t type = node->type;
+   {
+    if (dfa->mb_cur_max > 1)
+     bitset_merge (accepts, dfa->sb_char);
+    {
+     bitset_word_t any_set = 0;
+     if (type == CHARACTER && !node->word_char)
+      any_set |= (accepts[j] &= (dfa->word_char[j] | ~dfa->sb_char[j]));
+     else
+      for (j = 0; j < (256 / (sizeof (bitset_word_t) * 8)); ++j)
+       any_set |= (accepts[j] &= dfa->word_char[j]);
+    }
+   }
+  }
+}
+
+static void
+match_ctx_clean (
+ re_match_context_t * mctx
+)
+{
+ int st_idx;
+ for (st_idx = 0; st_idx < mctx->nsub_tops; ++st_idx)
+  {
+   int sl_idx;
+   re_sub_match_top_t *top = mctx->sub_tops[st_idx];
+   for (sl_idx = 0; sl_idx < top->nlasts; ++sl_idx)
+    {
+     re_sub_match_last_t *last = top->lasts[sl_idx];
+     free (last->path.array);
+    }
+  }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c
new file mode 100644
index 000000000..5896e7379
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59896.c
@@ -0,0 +1,1374 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -O2" } */
+
+typedef unsigned int size_t;
+typedef unsigned int wchar_t;
+typedef int ptrdiff_t;
+typedef signed char __int8_t ;
+typedef unsigned char __uint8_t ;
+typedef signed short __int16_t;
+typedef unsigned short __uint16_t;
+typedef __int16_t __int_least16_t;
+typedef __uint16_t __uint_least16_t;
+typedef signed int __int32_t;
+typedef unsigned int __uint32_t;
+typedef __int32_t __int_least32_t;
+typedef __uint32_t __uint_least32_t;
+typedef signed long long __int64_t;
+typedef unsigned long long __uint64_t;
+typedef int _LOCK_T;
+typedef int _LOCK_RECURSIVE_T;
+typedef long _off_t;
+typedef short __dev_t;
+typedef unsigned short __uid_t;
+typedef unsigned short __gid_t;
+__extension__ typedef long long _off64_t;
+typedef long _fpos_t;
+typedef signed int _ssize_t;
+typedef unsigned int wint_t;
+typedef struct
+{
+  int __count;
+  union
+  {
+    wint_t __wch;
+    unsigned char __wchb[4];
+  } __value;
+} _mbstate_t;
+typedef _LOCK_RECURSIVE_T _flock_t;
+typedef void *_iconv_t;
+typedef unsigned long __ULong;
+struct _reent;
+struct _Bigint
+{
+  struct _Bigint *_next;
+  int _k, _maxwds, _sign, _wds;
+  __ULong _x[1];
+};
+struct __tm
+{
+  int __tm_sec;
+  int __tm_min;
+  int __tm_hour;
+  int __tm_mday;
+  int __tm_mon;
+  int __tm_year;
+  int __tm_wday;
+  int __tm_yday;
+  int __tm_isdst;
+};
+struct _on_exit_args {
+ void * _fnargs[32];
+ void * _dso_handle[32];
+ __ULong _fntypes;
+ __ULong _is_cxa;
+};
+struct _atexit {
+ struct _atexit *_next;
+ int _ind;
+ void (*_fns[32])(void);
+        struct _on_exit_args _on_exit_args;
+};
+struct __sbuf {
+ unsigned char *_base;
+ int _size;
+};
+struct __sFILE {
+  unsigned char *_p;
+  int _r;
+  int _w;
+  short _flags;
+  short _file;
+  struct __sbuf _bf;
+  int _lbfsize;
+  void * _cookie;
+  int (* _read) (struct _reent *, void *, char *, int)
+                                          ;
+  int (* _write) (struct _reent *, void *, const char *, int)
+                                   ;
+  _fpos_t (* _seek) (struct _reent *, void *, _fpos_t, int);
+  int (* _close) (struct _reent *, void *);
+  struct __sbuf _ub;
+  unsigned char *_up;
+  int _ur;
+  unsigned char _ubuf[3];
+  unsigned char _nbuf[1];
+  struct __sbuf _lb;
+  int _blksize;
+  _off_t _offset;
+  struct _reent *_data;
+  _flock_t _lock;
+  _mbstate_t _mbstate;
+  int _flags2;
+};
+typedef struct __sFILE __FILE;
+struct _glue
+{
+  struct _glue *_next;
+  int _niobs;
+  __FILE *_iobs;
+};
+struct _rand48 {
+  unsigned short _seed[3];
+  unsigned short _mult[3];
+  unsigned short _add;
+};
+struct _reent
+{
+  int _errno;
+  __FILE *_stdin, *_stdout, *_stderr;
+  int _inc;
+  char _emergency[25];
+  int _current_category;
+  const char *_current_locale;
+  int __sdidinit;
+  void (* __cleanup) (struct _reent *);
+  struct _Bigint *_result;
+  int _result_k;
+  struct _Bigint *_p5s;
+  struct _Bigint **_freelist;
+  int _cvtlen;
+  char *_cvtbuf;
+  union
+    {
+      struct
+        {
+          unsigned int _unused_rand;
+          char * _strtok_last;
+          char _asctime_buf[26];
+          struct __tm _localtime_buf;
+          int _gamma_signgam;
+          __extension__ unsigned long long _rand_next;
+          struct _rand48 _r48;
+          _mbstate_t _mblen_state;
+          _mbstate_t _mbtowc_state;
+          _mbstate_t _wctomb_state;
+          char _l64a_buf[8];
+          char _signal_buf[24];
+          int _getdate_err;
+          _mbstate_t _mbrlen_state;
+          _mbstate_t _mbrtowc_state;
+          _mbstate_t _mbsrtowcs_state;
+          _mbstate_t _wcrtomb_state;
+          _mbstate_t _wcsrtombs_state;
+   int _h_errno;
+        } _reent;
+      struct
+        {
+          unsigned char * _nextf[30];
+          unsigned int _nmalloc[30];
+        } _unused;
+    } _new;
+  struct _atexit *_atexit;
+  struct _atexit _atexit0;
+  void (**(_sig_func))(int);
+  struct _glue __sglue;
+  __FILE __sf[3];
+};
+extern struct _reent *_impure_ptr ;
+extern struct _reent *const _global_impure_ptr ;
+void _reclaim_reent (struct _reent *);
+typedef struct
+{
+  int quot;
+  int rem;
+} div_t;
+typedef struct
+{
+  long quot;
+  long rem;
+} ldiv_t;
+typedef struct
+{
+  long long int quot;
+  long long int rem;
+} lldiv_t;
+typedef int (*__compar_fn_t) (const void *, const void *);
+int __locale_mb_cur_max (void);
+void abort (void) __attribute__ ((noreturn));
+int abs (int);
+int atexit (void (*__func)(void));
+double atof (const char *__nptr);
+float atoff (const char *__nptr);
+int atoi (const char *__nptr);
+int _atoi_r (struct _reent *, const char *__nptr);
+long atol (const char *__nptr);
+long _atol_r (struct _reent *, const char *__nptr);
+void * bsearch (const void * __key, const void * __base, size_t __nmemb, size_t __size, __compar_fn_t _compar)
+                                ;
+void * calloc (size_t __nmemb, size_t __size) ;
+div_t div (int __numer, int __denom);
+void exit (int __status) __attribute__ ((noreturn));
+void free (void *) ;
+char * getenv (const char *__string);
+char * _getenv_r (struct _reent *, const char *__string);
+char * _findenv (const char *, int *);
+char * _findenv_r (struct _reent *, const char *, int *);
+extern char *suboptarg;
+int getsubopt (char **, char * const *, char **);
+long labs (long);
+ldiv_t ldiv (long __numer, long __denom);
+void * malloc (size_t __size) ;
+int mblen (const char *, size_t);
+int _mblen_r (struct _reent *, const char *, size_t, _mbstate_t *);
+int mbtowc (wchar_t *, const char *, size_t);
+int _mbtowc_r (struct _reent *, wchar_t *, const char *, size_t, _mbstate_t *);
+int wctomb (char *, wchar_t);
+int _wctomb_r (struct _reent *, char *, wchar_t, _mbstate_t *);
+size_t mbstowcs (wchar_t *, const char *, size_t);
+size_t _mbstowcs_r (struct _reent *, wchar_t *, const char *, size_t, _mbstate_t *);
+size_t wcstombs (char *, const wchar_t *, size_t);
+size_t _wcstombs_r (struct _reent *, char *, const wchar_t *, size_t, _mbstate_t *);
+char * mkdtemp (char *);
+int mkostemp (char *, int);
+int mkostemps (char *, int, int);
+int mkstemp (char *);
+int mkstemps (char *, int);
+char * mktemp (char *) __attribute__ ((__warning__ ("the use of `mktemp' is dangerous; use `mkstemp' instead")));
+char * _mkdtemp_r (struct _reent *, char *);
+int _mkostemp_r (struct _reent *, char *, int);
+int _mkostemps_r (struct _reent *, char *, int, int);
+int _mkstemp_r (struct _reent *, char *);
+int _mkstemps_r (struct _reent *, char *, int);
+char * _mktemp_r (struct _reent *, char *) __attribute__ ((__warning__ ("the use of `mktemp' is dangerous; use `mkstemp' instead")));
+void qsort (void * __base, size_t __nmemb, size_t __size, __compar_fn_t _compar);
+int rand (void);
+void * realloc (void * __r, size_t __size) ;
+void * reallocf (void * __r, size_t __size);
+void srand (unsigned __seed);
+double strtod (const char *__n, char **__end_PTR);
+double _strtod_r (struct _reent *,const char *__n, char **__end_PTR);
+float strtof (const char *__n, char **__end_PTR);
+long strtol (const char *__n, char **__end_PTR, int __base);
+long _strtol_r (struct _reent *,const char *__n, char **__end_PTR, int __base);
+unsigned long strtoul (const char *__n, char **__end_PTR, int __base);
+unsigned long _strtoul_r (struct _reent *,const char *__n, char **__end_PTR, int __base);
+int system (const char *__string);
+long a64l (const char *__input);
+char * l64a (long __input);
+char * _l64a_r (struct _reent *,long __input);
+int on_exit (void (*__func)(int, void *),void * __arg);
+void _Exit (int __status) __attribute__ ((noreturn));
+int putenv (char *__string);
+int _putenv_r (struct _reent *, char *__string);
+void * _reallocf_r (struct _reent *, void *, size_t);
+int setenv (const char *__string, const char *__value, int __overwrite);
+int _setenv_r (struct _reent *, const char *__string, const char *__value, int __overwrite);
+char * gcvt (double,int,char *);
+char * gcvtf (float,int,char *);
+char * fcvt (double,int,int *,int *);
+char * fcvtf (float,int,int *,int *);
+char * ecvt (double,int,int *,int *);
+char * ecvtbuf (double, int, int*, int*, char *);
+char * fcvtbuf (double, int, int*, int*, char *);
+char * ecvtf (float,int,int *,int *);
+char * dtoa (double, int, int, int *, int*, char**);
+int rand_r (unsigned *__seed);
+double drand48 (void);
+double _drand48_r (struct _reent *);
+double erand48 (unsigned short [3]);
+double _erand48_r (struct _reent *, unsigned short [3]);
+long jrand48 (unsigned short [3]);
+long _jrand48_r (struct _reent *, unsigned short [3]);
+void lcong48 (unsigned short [7]);
+void _lcong48_r (struct _reent *, unsigned short [7]);
+long lrand48 (void);
+long _lrand48_r (struct _reent *);
+long mrand48 (void);
+long _mrand48_r (struct _reent *);
+long nrand48 (unsigned short [3]);
+long _nrand48_r (struct _reent *, unsigned short [3]);
+unsigned short *
+       seed48 (unsigned short [3]);
+unsigned short *
+       _seed48_r (struct _reent *, unsigned short [3]);
+void srand48 (long);
+void _srand48_r (struct _reent *, long);
+long long atoll (const char *__nptr);
+long long _atoll_r (struct _reent *, const char *__nptr);
+long long llabs (long long);
+lldiv_t lldiv (long long __numer, long long __denom);
+long long strtoll (const char *__n, char **__end_PTR, int __base);
+long long _strtoll_r (struct _reent *, const char *__n, char **__end_PTR, int __base);
+unsigned long long strtoull (const char *__n, char **__end_PTR, int __base);
+unsigned long long _strtoull_r (struct _reent *, const char *__n, char **__end_PTR, int __base);
+void cfree (void *);
+int unsetenv (const char *__string);
+int _unsetenv_r (struct _reent *, const char *__string);
+char * _dtoa_r (struct _reent *, double, int, int, int *, int*, char**);
+void * _malloc_r (struct _reent *, size_t) ;
+void * _calloc_r (struct _reent *, size_t, size_t) ;
+void _free_r (struct _reent *, void *) ;
+void * _realloc_r (struct _reent *, void *, size_t) ;
+void _mstats_r (struct _reent *, char *);
+int _system_r (struct _reent *, const char *);
+void __eprintf (const char *, const char *, unsigned int, const char *);
+extern long double strtold (const char *, char **);
+extern long double wcstold (const wchar_t *, wchar_t **);
+typedef long int __off_t;
+typedef int __pid_t;
+__extension__ typedef long long int __loff_t;
+struct stat;
+struct tms;
+struct timeval;
+struct timezone;
+extern int _close_r (struct _reent *, int);
+extern int _execve_r (struct _reent *, const char *, char *const *, char *const *);
+extern int _fcntl_r (struct _reent *, int, int, int);
+extern int _fork_r (struct _reent *);
+extern int _fstat_r (struct _reent *, int, struct stat *);
+extern int _getpid_r (struct _reent *);
+extern int _isatty_r (struct _reent *, int);
+extern int _kill_r (struct _reent *, int, int);
+extern int _link_r (struct _reent *, const char *, const char *);
+extern _off_t _lseek_r (struct _reent *, int, _off_t, int);
+extern int _mkdir_r (struct _reent *, const char *, int);
+extern int _open_r (struct _reent *, const char *, int, int);
+extern _ssize_t _read_r (struct _reent *, int, void *, size_t);
+extern int _rename_r (struct _reent *, const char *, const char *);
+extern void *_sbrk_r (struct _reent *, ptrdiff_t);
+extern int _stat_r (struct _reent *, const char *, struct stat *);
+extern unsigned long _times_r (struct _reent *, struct tms *);
+extern int _unlink_r (struct _reent *, const char *);
+extern int _wait_r (struct _reent *, int *);
+extern _ssize_t _write_r (struct _reent *, int, const void *, size_t);
+extern int _gettimeofday_r (struct _reent *, struct timeval *__tp, void *__tzp);
+typedef signed char int8_t ;
+typedef unsigned char uint8_t ;
+typedef signed char int_least8_t;
+typedef unsigned char uint_least8_t;
+typedef signed short int16_t;
+typedef unsigned short uint16_t;
+typedef int16_t int_least16_t;
+typedef uint16_t uint_least16_t;
+typedef signed long int32_t;
+typedef unsigned long uint32_t;
+typedef int32_t int_least32_t;
+typedef uint32_t uint_least32_t;
+typedef signed long long int64_t;
+typedef unsigned long long uint64_t;
+typedef int64_t int_least64_t;
+typedef uint64_t uint_least64_t;
+  typedef signed int int_fast8_t;
+  typedef unsigned int uint_fast8_t;
+  typedef signed int int_fast16_t;
+  typedef unsigned int uint_fast16_t;
+  typedef signed int int_fast32_t;
+  typedef unsigned int uint_fast32_t;
+  typedef int_least64_t int_fast64_t;
+  typedef uint_least64_t uint_fast64_t;
+  typedef long long int intmax_t;
+  typedef long long unsigned int uintmax_t;
+typedef signed int intptr_t;
+typedef unsigned int uintptr_t;
+void * memchr (const void *, int, size_t);
+int memcmp (const void *, const void *, size_t);
+void * memcpy (void * , const void * , size_t);
+void * memmove (void *, const void *, size_t);
+void * memset (void *, int, size_t);
+char *strcat (char *, const char *);
+char *strchr (const char *, int);
+int strcmp (const char *, const char *);
+int strcoll (const char *, const char *);
+char *strcpy (char *, const char *);
+size_t strcspn (const char *, const char *);
+char *strerror (int);
+size_t strlen (const char *);
+char *strncat (char *, const char *, size_t);
+int strncmp (const char *, const char *, size_t);
+char *strncpy (char *, const char *, size_t);
+char *strpbrk (const char *, const char *);
+char *strrchr (const char *, int);
+size_t strspn (const char *, const char *);
+char *strstr (const char *, const char *);
+char *strtok (char *, const char *);
+size_t strxfrm (char *, const char *, size_t);
+char *strtok_r (char *, const char *, char **);
+int bcmp (const void *, const void *, size_t);
+void bcopy (const void *, void *, size_t);
+void bzero (void *, size_t);
+int ffs (int);
+char *index (const char *, int);
+void * memccpy (void * , const void * , int, size_t);
+void * mempcpy (void *, const void *, size_t);
+void * memmem (const void *, size_t, const void *, size_t);
+void * memrchr (const void *, int, size_t);
+void * rawmemchr (const void *, int);
+char *rindex (const char *, int);
+char *stpcpy (char *, const char *);
+char *stpncpy (char *, const char *, size_t);
+int strcasecmp (const char *, const char *);
+char *strcasestr (const char *, const char *);
+char *strchrnul (const char *, int);
+char *strdup (const char *);
+char *_strdup_r (struct _reent *, const char *);
+char *strndup (const char *, size_t);
+char *_strndup_r (struct _reent *, const char *, size_t);
+int strerror_r (int, char *, size_t) __asm__ ("" "__xpg_strerror_r");
+size_t strlcat (char *, const char *, size_t);
+size_t strlcpy (char *, const char *, size_t);
+int strncasecmp (const char *, const char *, size_t);
+size_t strnlen (const char *, size_t);
+char *strsep (char **, const char *);
+char *strlwr (char *);
+char *strupr (char *);
+char *strsignal (int __signo);
+char * _strerror_r (struct _reent *, int, int, int *);
+typedef union
+{
+  double value;
+  struct
+  {
+    unsigned int fraction1:32;
+    unsigned int fraction0:20;
+    unsigned int exponent :11;
+    unsigned int sign : 1;
+  } number;
+  struct
+  {
+    unsigned int function1:32;
+    unsigned int function0:19;
+    unsigned int quiet:1;
+    unsigned int exponent: 11;
+    unsigned int sign : 1;
+  } nan;
+  struct
+  {
+    unsigned long lsw;
+    unsigned long msw;
+  } parts;
+  long aslong[2];
+} __ieee_double_shape_type;
+typedef union
+{
+  float value;
+  struct
+  {
+    unsigned int fraction0: 7;
+    unsigned int fraction1: 16;
+    unsigned int exponent: 8;
+    unsigned int sign : 1;
+  } number;
+  struct
+  {
+    unsigned int function1:16;
+    unsigned int function0:6;
+    unsigned int quiet:1;
+    unsigned int exponent:8;
+    unsigned int sign:1;
+  } nan;
+  long p1;
+} __ieee_float_shape_type;
+typedef int fp_rnd;
+fp_rnd fpgetround (void);
+fp_rnd fpsetround (fp_rnd);
+typedef int fp_except;
+fp_except fpgetmask (void);
+fp_except fpsetmask (fp_except);
+fp_except fpgetsticky (void);
+fp_except fpsetsticky (fp_except);
+typedef int fp_rdi;
+fp_rdi fpgetroundtoi (void);
+fp_rdi fpsetroundtoi (fp_rdi);
+int isnan (double);
+int isinf (double);
+int finite (double);
+int isnanf (float);
+int isinff (float);
+int finitef (float);
+union __dmath
+{
+  double d;
+  __ULong i[2];
+};
+union __fmath
+{
+  float f;
+  __ULong i[1];
+};
+union __ldmath
+{
+  long double ld;
+  __ULong i[4];
+};
+extern double atan (double);
+extern double cos (double);
+extern double sin (double);
+extern double tan (double);
+extern double tanh (double);
+extern double frexp (double, int *);
+extern double modf (double, double *);
+extern double ceil (double);
+extern double fabs (double);
+extern double floor (double);
+extern double acos (double);
+extern double asin (double);
+extern double atan2 (double, double);
+extern double cosh (double);
+extern double sinh (double);
+extern double exp (double);
+extern double ldexp (double, int);
+extern double log (double);
+extern double log10 (double);
+extern double pow (double, double);
+extern double sqrt (double);
+extern double fmod (double, double);
+    typedef float float_t;
+    typedef double double_t;
+extern int __isinff (float x);
+extern int __isinfd (double x);
+extern int __isnanf (float x);
+extern int __isnand (double x);
+extern int __fpclassifyf (float x);
+extern int __fpclassifyd (double x);
+extern int __signbitf (float x);
+extern int __signbitd (double x);
+extern double infinity (void);
+extern double nan (const char *);
+extern int finite (double);
+extern double copysign (double, double);
+extern double logb (double);
+extern int ilogb (double);
+extern double asinh (double);
+extern double cbrt (double);
+extern double nextafter (double, double);
+extern double rint (double);
+extern double scalbn (double, int);
+extern double exp2 (double);
+extern double scalbln (double, long int);
+extern double tgamma (double);
+extern double nearbyint (double);
+extern long int lrint (double);
+extern long long int llrint (double);
+extern double round (double);
+extern long int lround (double);
+extern long long int llround (double);
+extern double trunc (double);
+extern double remquo (double, double, int *);
+extern double fdim (double, double);
+extern double fmax (double, double);
+extern double fmin (double, double);
+extern double fma (double, double, double);
+extern double log1p (double);
+extern double expm1 (double);
+extern double acosh (double);
+extern double atanh (double);
+extern double remainder (double, double);
+extern double gamma (double);
+extern double lgamma (double);
+extern double erf (double);
+extern double erfc (double);
+extern double log2 (double);
+extern double hypot (double, double);
+extern float atanf (float);
+extern float cosf (float);
+extern float sinf (float);
+extern float tanf (float);
+extern float tanhf (float);
+extern float frexpf (float, int *);
+extern float modff (float, float *);
+extern float ceilf (float);
+extern float fabsf (float);
+extern float floorf (float);
+extern float acosf (float);
+extern float asinf (float);
+extern float atan2f (float, float);
+extern float coshf (float);
+extern float sinhf (float);
+extern float expf (float);
+extern float ldexpf (float, int);
+extern float logf (float);
+extern float log10f (float);
+extern float powf (float, float);
+extern float sqrtf (float);
+extern float fmodf (float, float);
+extern float exp2f (float);
+extern float scalblnf (float, long int);
+extern float tgammaf (float);
+extern float nearbyintf (float);
+extern long int lrintf (float);
+extern long long llrintf (float);
+extern float roundf (float);
+extern long int lroundf (float);
+extern long long int llroundf (float);
+extern float truncf (float);
+extern float remquof (float, float, int *);
+extern float fdimf (float, float);
+extern float fmaxf (float, float);
+extern float fminf (float, float);
+extern float fmaf (float, float, float);
+extern float infinityf (void);
+extern float nanf (const char *);
+extern int finitef (float);
+extern float copysignf (float, float);
+extern float logbf (float);
+extern int ilogbf (float);
+extern float asinhf (float);
+extern float cbrtf (float);
+extern float nextafterf (float, float);
+extern float rintf (float);
+extern float scalbnf (float, int);
+extern float log1pf (float);
+extern float expm1f (float);
+extern float acoshf (float);
+extern float atanhf (float);
+extern float remainderf (float, float);
+extern float gammaf (float);
+extern float lgammaf (float);
+extern float erff (float);
+extern float erfcf (float);
+extern float log2f (float);
+extern float hypotf (float, float);
+extern long double atanl (long double);
+extern long double cosl (long double);
+extern long double sinl (long double);
+extern long double tanl (long double);
+extern long double tanhl (long double);
+extern long double frexpl (long double value, int *);
+extern long double modfl (long double, long double *);
+extern long double ceill (long double);
+extern long double fabsl (long double);
+extern long double floorl (long double);
+extern long double log1pl (long double);
+extern long double expm1l (long double);
+extern long double acosl (long double);
+extern long double asinl (long double);
+extern long double atan2l (long double, long double);
+extern long double coshl (long double);
+extern long double sinhl (long double);
+extern long double expl (long double);
+extern long double ldexpl (long double, int);
+extern long double logl (long double);
+extern long double log10l (long double);
+extern long double powl (long double, long double);
+extern long double sqrtl (long double);
+extern long double fmodl (long double, long double);
+extern long double hypotl (long double, long double);
+extern long double copysignl (long double, long double);
+extern long double nanl (const char *);
+extern int ilogbl (long double);
+extern long double asinhl (long double);
+extern long double cbrtl (long double);
+extern long double nextafterl (long double, long double);
+extern long double rintl (long double);
+extern long double scalbnl (long double, int);
+extern long double exp2l (long double);
+extern long double scalblnl (long double, long);
+extern long double tgammal (long double);
+extern long double nearbyintl (long double);
+extern long int lrintl (long double);
+extern long long int llrintl (long double);
+extern long double roundl (long double);
+extern long lroundl (long double);
+extern long long int llroundl (long double);
+extern long double truncl (long double);
+extern long double remquol (long double, long double, int *);
+extern long double fdiml (long double, long double);
+extern long double fmaxl (long double, long double);
+extern long double fminl (long double, long double);
+extern long double fmal (long double, long double, long double);
+extern long double acoshl (long double);
+extern long double atanhl (long double);
+extern long double remainderl (long double, long double);
+extern long double lgammal (long double);
+extern long double erfl (long double);
+extern long double erfcl (long double);
+extern double drem (double, double);
+extern void sincos (double, double *, double *);
+extern double gamma_r (double, int *);
+extern double lgamma_r (double, int *);
+extern double y0 (double);
+extern double y1 (double);
+extern double yn (int, double);
+extern double j0 (double);
+extern double j1 (double);
+extern double jn (int, double);
+extern float dremf (float, float);
+extern void sincosf (float, float *, float *);
+extern float gammaf_r (float, int *);
+extern float lgammaf_r (float, int *);
+extern float y0f (float);
+extern float y1f (float);
+extern float ynf (int, float);
+extern float j0f (float);
+extern float j1f (float);
+extern float jnf (int, float);
+extern double exp10 (double);
+extern double pow10 (double);
+extern float exp10f (float);
+extern float pow10f (float);
+extern int *__signgam (void);
+struct exception
+{
+  int type;
+  char *name;
+  double arg1;
+  double arg2;
+  double retval;
+  int err;
+};
+extern int matherr (struct exception *e);
+enum __fdlibm_version
+{
+  __fdlibm_ieee = -1,
+  __fdlibm_svid,
+  __fdlibm_xopen,
+  __fdlibm_posix
+};
+extern enum __fdlibm_version __fdlib_version;
+typedef int error_t;
+extern int *__errno (void);
+extern const char * const _sys_errlist[];
+extern int _sys_nerr;
+typedef unsigned char u_char;
+typedef unsigned short u_short;
+typedef unsigned int u_int;
+typedef unsigned long u_long;
+typedef unsigned short ushort;
+typedef unsigned int uint;
+typedef unsigned long ulong;
+typedef unsigned long clock_t;
+typedef long time_t;
+struct timespec {
+  time_t tv_sec;
+  long tv_nsec;
+};
+struct itimerspec {
+  struct timespec it_interval;
+  struct timespec it_value;
+};
+typedef long daddr_t;
+typedef char * caddr_t;
+typedef unsigned short ino_t;
+typedef _off_t off_t;
+typedef __dev_t dev_t;
+typedef __uid_t uid_t;
+typedef __gid_t gid_t;
+typedef int pid_t;
+typedef long key_t;
+typedef _ssize_t ssize_t;
+typedef unsigned int mode_t __attribute__ ((__mode__ (__SI__)));
+typedef unsigned short nlink_t;
+typedef long fd_mask;
+typedef struct _types_fd_set {
+ fd_mask fds_bits[(((64)+(((sizeof (fd_mask) * 8))-1))/((sizeof (fd_mask) * 8)))];
+} _types_fd_set;
+typedef unsigned long clockid_t;
+typedef unsigned long timer_t;
+typedef unsigned long useconds_t;
+typedef long suseconds_t;
+union double_union
+{
+  double d;
+  __uint32_t i[2];
+};
+typedef __int32_t Long;
+typedef union { double d; __ULong i[2]; } U;
+typedef struct _Bigint _Bigint;
+struct _reent ;
+struct FPI;
+double __ulp (double x);
+double __b2d (_Bigint *a , int *e);
+_Bigint * _Balloc (struct _reent *p, int k);
+void _Bfree (struct _reent *p, _Bigint *v);
+_Bigint * __multadd (struct _reent *p, _Bigint *, int, int);
+_Bigint * __s2b (struct _reent *, const char*, int, int, __ULong);
+_Bigint * __i2b (struct _reent *,int);
+_Bigint * __multiply (struct _reent *, _Bigint *, _Bigint *);
+_Bigint * __pow5mult (struct _reent *, _Bigint *, int k);
+int __hi0bits (__ULong);
+int __lo0bits (__ULong *);
+_Bigint * __d2b (struct _reent *p, double d, int *e, int *bits);
+_Bigint * __lshift (struct _reent *p, _Bigint *b, int k);
+_Bigint * __mdiff (struct _reent *p, _Bigint *a, _Bigint *b);
+int __mcmp (_Bigint *a, _Bigint *b);
+int __gethex (struct _reent *p, const char **sp, const struct FPI *fpi, Long *exp, _Bigint **bp, int sign);
+double __ratio (_Bigint *a, _Bigint *b);
+__ULong __any_on (_Bigint *b, int k);
+void __copybits (__ULong *c, int n, _Bigint *b);
+int __hexnan (const char **sp, const struct FPI *fpi, __ULong *x0);
+extern const double __mprec_tinytens[];
+extern const double __mprec_bigtens[];
+extern const double __mprec_tens[];
+extern const unsigned char __hexdig[];
+double _mprec_log10 (int);
+static int
+quorem(_Bigint * b , _Bigint * S)
+{
+  int n;
+  long borrow, y;
+  __ULong carry, q, ys;
+  __ULong *bx, *bxe, *sx, *sxe;
+  long z;
+  __ULong si, zs;
+  n = S->_wds;
+  if (b->_wds < n)
+    return 0;
+  sx = S->_x;
+  sxe = sx + --n;
+  bx = b->_x;
+  bxe = bx + n;
+  q = *bxe / (*sxe + 1);
+  if (q)
+    {
+      borrow = 0;
+      carry = 0;
+      do
+ {
+   si = *sx++;
+   ys = (si & 0xffff) * q + carry;
+   zs = (si >> 16) * q + (ys >> 16);
+   carry = zs >> 16;
+   y = (*bx & 0xffff) - (ys & 0xffff) + borrow;
+   borrow = y >> 16;
+   ;
+   z = (*bx >> 16) - (zs & 0xffff) + borrow;
+   borrow = z >> 16;
+   ;
+   (*(bx)++ = ((z) << 16) | ((y) & 0xffff));
+ }
+      while (sx <= sxe);
+      if (!*bxe)
+ {
+   bx = b->_x;
+   while (--bxe > bx && !*bxe)
+     --n;
+   b->_wds = n;
+ }
+    }
+  if (__mcmp (b, S) >= 0)
+    {
+      q++;
+      borrow = 0;
+      carry = 0;
+      bx = b->_x;
+      sx = S->_x;
+      do
+ {
+   si = *sx++;
+   ys = (si & 0xffff) + carry;
+   zs = (si >> 16) + (ys >> 16);
+   carry = zs >> 16;
+   y = (*bx & 0xffff) - (ys & 0xffff) + borrow;
+   borrow = y >> 16;
+   ;
+   z = (*bx >> 16) - (zs & 0xffff) + borrow;
+   borrow = z >> 16;
+   ;
+   (*(bx)++ = ((z) << 16) | ((y) & 0xffff));
+ }
+      while (sx <= sxe);
+      bx = b->_x;
+      bxe = bx + n;
+      if (!*bxe)
+ {
+   while (--bxe > bx && !*bxe)
+     --n;
+   b->_wds = n;
+ }
+    }
+  return q;
+}
+char *
+_dtoa_r(struct _reent *ptr , double _d , int mode , int ndigits , int *decpt , int *sign , char **rve)
+{
+  int bbits, b2, b5, be, dig, i, ieps, ilim, ilim0, ilim1, j, j1, k, k0,
+    k_check, leftright, m2, m5, s2, s5, spec_case, try_quick;
+  union double_union d, d2, eps;
+  long L;
+  int denorm;
+  __ULong x;
+  _Bigint *b, *b1, *delta, *mlo = ((void *)0), *mhi, *S;
+  double ds;
+  char *s, *s0;
+  d.d = _d;
+  ;
+  if (((ptr)->_result))
+    {
+      ((ptr)->_result)->_k = ((ptr)->_result_k);
+      ((ptr)->_result)->_maxwds = 1 << ((ptr)->_result_k);
+      _Bfree (ptr, ((ptr)->_result));
+      ((ptr)->_result) = 0;
+    }
+  if ((d.i[1]) & ((__uint32_t)0x80000000L))
+    {
+      *sign = 1;
+      (d.i[1]) &= ~((__uint32_t)0x80000000L);
+    }
+  else
+    *sign = 0;
+  if (((d.i[1]) & ((__uint32_t)0x7ff00000L)) == ((__uint32_t)0x7ff00000L))
+    {
+      *decpt = 9999;
+      s =
+ !(d.i[0]) && !((d.i[1]) & 0xfffff) ? "Infinity" :
+ "NaN";
+      if (rve)
+ *rve =
+   s[3] ? s + 8 :
+   s + 3;
+      return s;
+    }
+  if (!d.d)
+    {
+      *decpt = 1;
+      s = "0";
+      if (rve)
+ *rve = s + 1;
+      return s;
+    }
+  b = __d2b (ptr, d.d, &be, &bbits);
+  if ((i = (int) ((d.i[1]) >> 20 & (((__uint32_t)0x7ff00000L) >> 20))) != 0)
+    {
+      d2.d = d.d;
+      (d2.i[1]) &= ((__uint32_t)0xfffffL);
+      (d2.i[1]) |= ((__uint32_t)0x3ff00000L);
+      i -= 1023;
+      denorm = 0;
+    }
+  else
+    {
+      i = bbits + be + (1023 + (53 - 1) - 1);
+      x = (i > 32) ? ((d.i[1]) << (64 - i)) | ((d.i[0]) >> (i - 32))
+       : ((d.i[0]) << (32 - i));
+      d2.d = x;
+      (d2.i[1]) -= 31 * ((__uint32_t)0x100000L);
+      i -= (1023 + (53 - 1) - 1) + 1;
+      denorm = 1;
+    }
+  ds = (d2.d - 1.5) * 0.289529654602168 + 0.1760912590558 + i * 0.301029995663981;
+  k = (int) ds;
+  if (ds < 0. && ds != k)
+    k--;
+  k_check = 1;
+  if (k >= 0 && k <= 22)
+    {
+      if (d.d < __mprec_tens[k])
+ k--;
+      k_check = 0;
+    }
+  j = bbits - i - 1;
+  if (j >= 0)
+    {
+      b2 = 0;
+      s2 = j;
+    }
+  else
+    {
+      b2 = -j;
+      s2 = 0;
+    }
+  if (k >= 0)
+    {
+      b5 = 0;
+      s5 = k;
+      s2 += k;
+    }
+  else
+    {
+      b2 -= k;
+      b5 = -k;
+      s5 = 0;
+    }
+  if (mode < 0 || mode > 9)
+    mode = 0;
+  try_quick = 1;
+  if (mode > 5)
+    {
+      mode -= 4;
+      try_quick = 0;
+    }
+  leftright = 1;
+  ilim = ilim1 = -1;
+  switch (mode)
+    {
+    case 0:
+    case 1:
+      i = 18;
+      ndigits = 0;
+      break;
+    case 2:
+      leftright = 0;
+    case 4:
+      if (ndigits <= 0)
+ ndigits = 1;
+      ilim = ilim1 = i = ndigits;
+      break;
+    case 3:
+      leftright = 0;
+    case 5:
+      i = ndigits + k + 1;
+      ilim = i;
+      ilim1 = i - 1;
+      if (i <= 0)
+ i = 1;
+    }
+  j = sizeof (__ULong);
+  for (((ptr)->_result_k) = 0; sizeof (_Bigint) - sizeof (__ULong) + j <= i;
+       j <<= 1)
+    ((ptr)->_result_k)++;
+  ((ptr)->_result) = _Balloc (ptr, ((ptr)->_result_k));
+  s = s0 = (char *) ((ptr)->_result);
+  if (ilim >= 0 && ilim <= 14 && try_quick)
+    {
+      i = 0;
+      d2.d = d.d;
+      k0 = k;
+      ilim0 = ilim;
+      ieps = 2;
+      if (k > 0)
+ {
+   ds = __mprec_tens[k & 0xf];
+   j = k >> 4;
+   if (j & 0x10)
+     {
+       j &= 0x10 - 1;
+       d.d /= __mprec_bigtens[5 - 1];
+       ieps++;
+     }
+   for (; j; j >>= 1, i++)
+     if (j & 1)
+       {
+  ieps++;
+  ds *= __mprec_bigtens[i];
+       }
+   d.d /= ds;
+ }
+      else if ((j1 = -k) != 0)
+ {
+   d.d *= __mprec_tens[j1 & 0xf];
+   for (j = j1 >> 4; j; j >>= 1, i++)
+     if (j & 1)
+       {
+  ieps++;
+  d.d *= __mprec_bigtens[i];
+       }
+ }
+      if (k_check && d.d < 1. && ilim > 0)
+ {
+   if (ilim1 <= 0)
+     goto fast_failed;
+   ilim = ilim1;
+   k--;
+   d.d *= 10.;
+   ieps++;
+ }
+      eps.d = ieps * d.d + 7.;
+      (eps.i[1]) -= (53 - 1) * ((__uint32_t)0x100000L);
+      if (ilim == 0)
+ {
+   S = mhi = 0;
+   d.d -= 5.;
+   if (d.d > eps.d)
+     goto one_digit;
+   if (d.d < -eps.d)
+     goto no_digits;
+   goto fast_failed;
+ }
+      if (leftright)
+ {
+   eps.d = 0.5 / __mprec_tens[ilim - 1] - eps.d;
+   for (i = 0;;)
+     {
+       L = d.d;
+       d.d -= L;
+       *s++ = '0' + (int) L;
+       if (d.d < eps.d)
+  goto ret1;
+       if (1. - d.d < eps.d)
+  goto bump_up;
+       if (++i >= ilim)
+  break;
+       eps.d *= 10.;
+       d.d *= 10.;
+     }
+ }
+      else
+ {
+   eps.d *= __mprec_tens[ilim - 1];
+   for (i = 1;; i++, d.d *= 10.)
+     {
+       L = d.d;
+       d.d -= L;
+       *s++ = '0' + (int) L;
+       if (i == ilim)
+  {
+    if (d.d > 0.5 + eps.d)
+      goto bump_up;
+    else if (d.d < 0.5 - eps.d)
+      {
+        while (*--s == '0');
+        s++;
+        goto ret1;
+      }
+    break;
+  }
+     }
+ }
+    fast_failed:
+      s = s0;
+      d.d = d2.d;
+      k = k0;
+      ilim = ilim0;
+    }
+  if (be >= 0 && k <= 14)
+    {
+      ds = __mprec_tens[k];
+      if (ndigits < 0 && ilim <= 0)
+ {
+   S = mhi = 0;
+   if (ilim < 0 || d.d <= 5 * ds)
+     goto no_digits;
+   goto one_digit;
+ }
+      for (i = 1;; i++)
+ {
+   L = d.d / ds;
+   d.d -= L * ds;
+   *s++ = '0' + (int) L;
+   if (i == ilim)
+     {
+       d.d += d.d;
+             if ((d.d > ds) || ((d.d == ds) && (L & 1)))
+  {
+  bump_up:
+    while (*--s == '9')
+      if (s == s0)
+        {
+   k++;
+   *s = '0';
+   break;
+        }
+    ++*s++;
+  }
+       break;
+     }
+   if (!(d.d *= 10.))
+     break;
+ }
+      goto ret1;
+    }
+  m2 = b2;
+  m5 = b5;
+  mhi = mlo = 0;
+  if (leftright)
+    {
+      if (mode < 2)
+ {
+   i =
+     denorm ? be + (1023 + (53 - 1) - 1 + 1) :
+     1 + 53 - bbits;
+ }
+      else
+ {
+   j = ilim - 1;
+   if (m5 >= j)
+     m5 -= j;
+   else
+     {
+       s5 += j -= m5;
+       b5 += j;
+       m5 = 0;
+     }
+   if ((i = ilim) < 0)
+     {
+       m2 -= i;
+       i = 0;
+     }
+ }
+      b2 += i;
+      s2 += i;
+      mhi = __i2b (ptr, 1);
+    }
+  if (m2 > 0 && s2 > 0)
+    {
+      i = m2 < s2 ? m2 : s2;
+      b2 -= i;
+      m2 -= i;
+      s2 -= i;
+    }
+  if (b5 > 0)
+    {
+      if (leftright)
+ {
+   if (m5 > 0)
+     {
+       mhi = __pow5mult (ptr, mhi, m5);
+       b1 = __multiply (ptr, mhi, b);
+       _Bfree (ptr, b);
+       b = b1;
+     }
+         if ((j = b5 - m5) != 0)
+     b = __pow5mult (ptr, b, j);
+ }
+      else
+ b = __pow5mult (ptr, b, b5);
+    }
+  S = __i2b (ptr, 1);
+  if (s5 > 0)
+    S = __pow5mult (ptr, S, s5);
+  spec_case = 0;
+  if (mode < 2)
+    {
+      if (!(d.i[0]) && !((d.i[1]) & ((__uint32_t)0xfffffL))
+   && (d.i[1]) & ((__uint32_t)0x7ff00000L)
+ )
+ {
+   b2 += 1;
+   s2 += 1;
+   spec_case = 1;
+ }
+    }
+  if ((i = ((s5 ? 32 - __hi0bits (S->_x[S->_wds - 1]) : 1) + s2) & 0x1f) != 0)
+    i = 32 - i;
+  if (i > 4)
+    {
+      i -= 4;
+      b2 += i;
+      m2 += i;
+      s2 += i;
+    }
+  else if (i < 4)
+    {
+      i += 28;
+      b2 += i;
+      m2 += i;
+      s2 += i;
+    }
+  if (b2 > 0)
+    b = __lshift (ptr, b, b2);
+  if (s2 > 0)
+    S = __lshift (ptr, S, s2);
+  if (k_check)
+    {
+      if (__mcmp (b, S) < 0)
+ {
+   k--;
+   b = __multadd (ptr, b, 10, 0);
+   if (leftright)
+     mhi = __multadd (ptr, mhi, 10, 0);
+   ilim = ilim1;
+ }
+    }
+  if (ilim <= 0 && mode > 2)
+    {
+      if (ilim < 0 || __mcmp (b, S = __multadd (ptr, S, 5, 0)) <= 0)
+ {
+ no_digits:
+   k = -1 - ndigits;
+   goto ret;
+ }
+    one_digit:
+      *s++ = '1';
+      k++;
+      goto ret;
+    }
+  if (leftright)
+    {
+      if (m2 > 0)
+ mhi = __lshift (ptr, mhi, m2);
+      mlo = mhi;
+      if (spec_case)
+ {
+   mhi = _Balloc (ptr, mhi->_k);
+   memcpy((char *)&mhi->_sign, (char *)&mlo->_sign, mlo->_wds*sizeof(long) + 2*sizeof(int));
+   mhi = __lshift (ptr, mhi, 1);
+ }
+      for (i = 1;; i++)
+ {
+   dig = quorem (b, S) + '0';
+   j = __mcmp (b, mlo);
+   delta = __mdiff (ptr, S, mhi);
+   j1 = delta->_sign ? 1 : __mcmp (b, delta);
+   _Bfree (ptr, delta);
+   if (j1 == 0 && !mode && !((d.i[0]) & 1))
+     {
+       if (dig == '9')
+  goto round_9_up;
+       if (j > 0)
+  dig++;
+       *s++ = dig;
+       goto ret;
+     }
+         if ((j < 0) || ((j == 0) && !mode
+       && !((d.i[0]) & 1)
+           ))
+     {
+       if (j1 > 0)
+  {
+    b = __lshift (ptr, b, 1);
+    j1 = __mcmp (b, S);
+                 if (((j1 > 0) || ((j1 == 0) && (dig & 1)))
+        && dig++ == '9')
+      goto round_9_up;
+  }
+       *s++ = dig;
+       goto ret;
+     }
+   if (j1 > 0)
+     {
+       if (dig == '9')
+  {
+  round_9_up:
+    *s++ = '9';
+    goto roundoff;
+  }
+       *s++ = dig + 1;
+       goto ret;
+     }
+   *s++ = dig;
+   if (i == ilim)
+     break;
+   b = __multadd (ptr, b, 10, 0);
+   if (mlo == mhi)
+     mlo = mhi = __multadd (ptr, mhi, 10, 0);
+   else
+     {
+       mlo = __multadd (ptr, mlo, 10, 0);
+       mhi = __multadd (ptr, mhi, 10, 0);
+     }
+ }
+    }
+  else
+    for (i = 1;; i++)
+      {
+ *s++ = dig = quorem (b, S) + '0';
+ if (i >= ilim)
+   break;
+ b = __multadd (ptr, b, 10, 0);
+      }
+  b = __lshift (ptr, b, 1);
+  j = __mcmp (b, S);
+  if ((j > 0) || ((j == 0) && (dig & 1)))
+    {
+    roundoff:
+      while (*--s == '9')
+ if (s == s0)
+   {
+     k++;
+     *s++ = '1';
+     goto ret;
+   }
+      ++*s++;
+    }
+  else
+    {
+      while (*--s == '0');
+      s++;
+    }
+ret:
+  _Bfree (ptr, S);
+  if (mhi)
+    {
+      if (mlo && mlo != mhi)
+ _Bfree (ptr, mlo);
+      _Bfree (ptr, mhi);
+    }
+ret1:
+  _Bfree (ptr, b);
+  *s = 0;
+  *decpt = k + 1;
+  if (rve)
+    *rve = s;
+  return s0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59923.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59923.c
new file mode 100644
index 000000000..86a4e7d83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59923.c
@@ -0,0 +1,24 @@
+/* PR target/59923 */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2 -mcpu=cortex-a15 -fno-strict-aliasing -mthumb -g" } */
+
+struct S
+{
+  void *s;
+  struct T { unsigned short a; unsigned char b[4], c[4]; } *t;
+} s;
+void bar (void *);
+
+void
+foo (struct S *x, int *y)
+{
+  if (*y > 0)
+    return;
+  else if (x->t->b[0] == 0x43 && x->t->b[1] == 0x6d && x->t->c[0] == 1)
+    x->s = &s;
+  else
+    *y = 16384;
+  if (*y > 0)
+    bar (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C
new file mode 100644
index 000000000..cc688a965
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr59985.C
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-g -fcompare-debug -O2 -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=hard" } */
+
+extern void *f1 (unsigned long, unsigned long);
+extern const struct line_map *f2 (void *, int, unsigned int, const char *, unsigned int);
+extern unsigned int f3 (void *, unsigned int);
+extern void *v1;
+struct B { const char *s; int t; };
+struct C { unsigned u; unsigned long long v; void *w; };
+unsigned long long f4 (struct C *);
+const char *f5 (void *, unsigned int, unsigned int *);
+unsigned long long f6 (void *);
+
+static inline unsigned long long
+f7 (struct C *x, unsigned y)
+{
+  unsigned long long a, b;
+  int u = x->u;
+  a = y == 64 ? -1ULL : (1ULL << y) - 1;
+  if (u + y > 64)
+    {
+      f6 (x->w);
+      x->u = y;
+      return b & a;
+    }
+  b = x->v;
+  b >>= u;
+  x->u = u + y;
+  return b & a;
+}
+
+static const char *
+f8 (const char *x)
+{
+  B **a;
+  unsigned long t = __builtin_strlen (x);
+  char *b;
+  struct B *c;
+  b = (char *) f1 (t + 1, 1);
+  c = (struct B *) f1 (1, sizeof (struct B));
+  __builtin_memcpy (b, x, t + 1);
+  c->t = t;
+  struct B *d = *a;
+  return d->s;
+}
+
+unsigned int
+f9 (struct C *x, void *y)
+{
+  static const char *a;
+  static int b;
+  static int c;
+  bool d, e, f;
+  unsigned t;
+  bool prev_file = a != __null;
+  if (f7 (x, 1))
+    return ((unsigned int) 0);
+  d = f7 (x, 1);
+  e = f7 (x, 1);
+  f = f7 (x, 1);
+  a = f8 (f5 (y, f4 (x), &t));
+  if (e) b = f4 (x);
+  if (f)
+    if (d)
+      if (prev_file)
+        f2 (v1, 1, false, __null, 0);
+  return f3 (v1, c);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60264.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60264.c
new file mode 100644
index 000000000..4fe6aedb2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/pr60264.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mapcs -g" } */
+
+double bar(void);
+
+int foo(void)
+{
+  int i = bar() + bar();
+
+  return i;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/register-variables.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/register-variables.c
new file mode 100644
index 000000000..8c874b22e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/register-variables.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O" } */
+
+#include <stdlib.h>
+
+void __attribute__((noinline)) 
+bar(int a, int b)
+{
+  if (a != 43 || b != 42)
+    abort();
+}
+
+int main(void)
+{
+    register int r0 asm("r0") = 42;
+    register int r1 asm("r1") = 43;
+    asm volatile("": "+r" (r0), "+r" (r1));
+    bar(r1, r0);
+    return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c
new file mode 100644
index 000000000..bd85e8640
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-g -fPIC" } */
+
+void *v;
+void a (void *x) { }
+void b (void) { }
+                       /* line 7.  */
+int                    /* line 8.  */
+main (int argc)        /* line 9.  */
+{                      /* line 10.  */
+  if (argc == 12345)   /* line 11.  */
+    {
+      a (v);
+      return 1;
+    }
+  b ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "\.loc 1 7 0" } } */
+/* { dg-final { scan-assembler-not "\.loc 1 8 0" } } */
+/* { dg-final { scan-assembler-not "\.loc 1 9 0" } } */
+
+/* The loc at the start of the prologue.  */
+/* { dg-final { scan-assembler-times "\.loc 1 10 0" 1 } } */
+
+/* The loc at the end of the prologue, with the first user line.  */
+/* { dg-final { scan-assembler-times "\.loc 1 11 0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/sat-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/sat-1.c
new file mode 100644
index 000000000..ebde56a45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/sat-1.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arm_ok } */
+/* { dg-require-effective-target arm_arch_v6_ok } */
+/* { dg-options "-O2 -marm" } */
+/* { dg-add-options arm_arch_v6 } */
+
+
+static inline int sat1 (int a, int amin, int amax)
+{
+  if      (a < amin) return amin;
+  else if (a > amax) return amax;
+  else               return a;
+}
+
+static inline int sat2 (int a, int amin, int amax)
+{
+  if      (a > amax) return amax;
+  else if (a < amin) return amin;
+  else               return a;
+}
+
+int u1 (int x)
+{
+  return sat1 (x, 0, 63);
+}
+
+int us1 (int x)
+{
+  return sat1 (x >> 5, 0, 63);
+}
+
+int s1 (int x)
+{
+  return sat1 (x, -64, 63);
+}
+
+int ss1 (int x)
+{
+  return sat1 (x >> 5, -64, 63);
+}
+
+int u2 (int x)
+{
+  return sat2 (x, 0, 63);
+}
+
+int us2 (int x)
+{
+  return sat2 (x >> 5, 0, 63);
+}
+
+int s2 (int x)
+{
+  return sat2 (x, -64, 63);
+}
+
+int ss2 (int x)
+{
+  return sat2 (x >> 5, -64, 63);
+}
+
+/* { dg-final { scan-assembler-times "usat" 4 } } */
+/* { dg-final { scan-assembler-times "ssat" 4 } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-1.c
new file mode 100644
index 000000000..2cd1eeb8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-1.c
@@ -0,0 +1,16 @@
+/* Verify that mov is preferred on XScale for loading a 1 byte constant. */
+/* { dg-do compile } */
+/* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "" } } */
+/* { dg-options "-mcpu=xscale -O" } */
+
+unsigned load1(void) __attribute__ ((naked));
+unsigned load1(void)
+{
+    /* Best code would be:
+       mov r0, =17
+       mov pc, lr */
+
+    return 17;
+}
+
+/* { dg-final { scan-assembler "mov\[ 	].*17" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-2.c
new file mode 100644
index 000000000..e07740234
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-2.c
@@ -0,0 +1,20 @@
+/* Verify that mov is preferred on XScale for loading a 2 byte constant. */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=xscale -O" } */
+/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */
+/* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */
+/* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" } { "" } } */
+/* { dg-require-effective-target arm32 } */
+
+unsigned load2(void) __attribute__ ((naked));
+unsigned load2(void)
+{
+    /* Best code would be:
+       mov r0, =272
+       add r0, r0, =1
+       mov pc, lr */
+
+    return 273;
+}
+
+/* { dg-final { scan-assembler "mov\[ 	].*272" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-3.c
new file mode 100644
index 000000000..eb90e43c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/scd42-3.c
@@ -0,0 +1,17 @@
+/* Verify that ldr is preferred on XScale for loading a 3 or 4 byte constant. */
+/* { dg-do compile } */
+/* { dg-skip-if "Test is specific to Xscale" { arm*-*-* } { "-march=*" } { "-march=xscale" } } */
+/* { dg-skip-if "Test is specific to Xscale" { arm*-*-* } { "-mcpu=*" } { "-mcpu=xscale" } } */
+/* { dg-options "-mcpu=xscale -O" } */
+
+unsigned load4(void) __attribute__ ((naked));
+unsigned load4(void)
+{
+    /* Best code would be:
+       ldr r0, =65809
+       mov pc, lr */
+
+    return 65809;
+}
+
+/* { dg-final { scan-assembler "ldr\[ 	].*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c
new file mode 100644
index 000000000..f3080620a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/shiftable.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm32 } */
+
+/* ARM has shift-and-alu insns.  Depending on the ALU op GCC represents some
+   of these as a left shift, others as a multiply.  Check that we match the
+    right one.  */
+
+int
+plus (int a, int b)
+{
+  return (a * 64) + b;
+}
+
+/* { dg-final { scan-assembler "add.*\[al]sl #6" } } */
+
+int
+minus (int a, int b)
+{
+  return a - (b * 64);
+}
+
+/* { dg-final { scan-assembler "sub.*\[al]sl #6" } } */
+
+int
+ior (int a, int b)
+{
+  return (a * 64) | b;
+}
+
+/* { dg-final { scan-assembler "orr.*\[al]sl #6" } } */
+
+int
+xor (int a, int b)
+{
+  return (a * 64) ^ b;
+}
+
+/* { dg-final { scan-assembler "eor.*\[al]sl #6" } } */
+
+int
+and (int a, int b)
+{
+  return (a * 64) & b;
+}
+
+/* { dg-final { scan-assembler "and.*\[al]sl #6" } } */
+
+int
+rsb (int a, int b)
+{
+  return (a * 64) - b;
+}
+
+/* { dg-final { scan-assembler "rsb.*\[al]sl #6" } } */
+
+int
+mvn (int a, int b)
+{
+  return ~(a * 64);
+}
+
+/* { dg-final { scan-assembler "mvn.*\[al]sl #6" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-1.c
new file mode 100644
index 000000000..cf352c12c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target { arm32 } } } */
+/* { dg-options "-O2" } */
+
+#define noinline __attribute__((noinline))
+
+typedef struct {
+  int data[4];
+} arr16_t;
+
+int result = 0;
+
+void noinline func2 (int i, int j, arr16_t arr)
+{
+  result = (arr.data[0] != 1
+	    || arr.data[1] != 2
+	    || arr.data[2] != 3
+	    || arr.data[3] != 4);
+}
+
+void func1 (int i, int j, int k, int l, int m, int n, arr16_t a)
+{
+  func2(i, j, a);
+}
+
+int main(int argc, const char *argv[])
+{
+  arr16_t arr = {{1, 2, 3, 4}};
+    
+  func1(0, 0, 0, 0, 0, 0, arr);
+  return result;
+}
+
+/* The PLT marker may appear if the test is run with -fpic/-fPIC.  */
+/* { dg-final { scan-assembler "\tb\tfunc2(\\(PLT\\))?\n" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-2.c
new file mode 100644
index 000000000..921c0f302
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/sibcall-2.c
@@ -0,0 +1,12 @@
+/* { dg-require-effective-target arm_eabi } */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=aapcs" } */
+
+
+extern void __attribute__((weak)) wfunc(void);
+void main(void)
+{
+  wfunc();  /* Must not tail-call.  */
+}
+
+/* { dg-final { scan-assembler-not "b\[\\t \]+wfunc" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltb-1.c
new file mode 100644
index 000000000..a27009d25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltb-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O2" } */
+
+long long int
+foo (long long x, int in)
+{
+  short a = in & 0xffff;
+  short b = (in & 0xffff0000) >> 16;
+
+  return x + b * a;
+}
+
+/* { dg-final { scan-assembler "smlaltb\\t" { xfail *-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltt-1.c
new file mode 100644
index 000000000..380e3d01b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlaltt-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O2" } */
+
+long long int
+foo (long long x, int in1, int in2)
+{
+  short a = (in1 & 0xffff0000) >> 16;
+  short b = (in2 & 0xffff0000) >> 16;
+
+  return x + b * a;
+}
+
+/* { dg-final { scan-assembler "smlaltt\\t" { xfail *-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatb-1.c
new file mode 100644
index 000000000..d73aa18ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatb-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O2" } */
+
+int
+foo (int x, int in)
+{
+  short a = in & 0xffff;
+  short b = (in & 0xffff0000) >> 16;
+
+  return x + b * a;
+}
+
+/* { dg-final { scan-assembler "smlatb\\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatt-1.c
new file mode 100644
index 000000000..d7fb03400
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/smlatt-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O2" } */
+
+int
+foo (int x, int in1, int in2)
+{
+  short a = (in1 & 0xffff0000) >> 16;
+  short b = (in2 & 0xffff0000) >> 16;
+
+  return x + b * a;
+}
+
+/* { dg-final { scan-assembler "smlatt\\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-corruption.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-corruption.c
new file mode 100644
index 000000000..cc44c6280
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-corruption.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-options "-O -mthumb -fno-omit-frame-pointer" } */
+
+int main() {
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "\tadd\tr7, sp, #8\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c
new file mode 100644
index 000000000..b9f0f9937
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/stack-red-zone.c
@@ -0,0 +1,12 @@
+/* No stack red zone.  PR38644.  */
+/* { dg-options "-mthumb -O2" } */
+/* { dg-final { scan-assembler "ldrb\[^\n\]*\\n\[\t \]*add\[\t \]*sp" } } */
+
+extern int doStreamReadBlock (int *, char *, int size, int);
+
+char readStream (int *s)
+{
+       char c = 0;
+       doStreamReadBlock (s, &c, 1, *s);
+       return c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian1.c
new file mode 100644
index 000000000..25e812816
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* Symbian OS requires that all defined symbols with external linkage
+   have the ELF STV_HIDDEN attribute set by default.  */
+/* { dg-final { scan-assembler ".hidden.*i" } } */
+/* { dg-final { scan-assembler ".hidden.*j" } } */
+/* { dg-final { scan-assembler ".hidden.*f" } } */
+
+int i;
+int j = 3;
+void f() {}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian2.c
new file mode 100644
index 000000000..987016368
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* { dg-options "-O2" } */
+
+/* Symbian OS requires that builtins not be expanded by default.  Make
+   sure that a reference to "strlen" is emitted.  */
+/* { dg-final { scan-assembler "strlen" } } */
+
+int f() {
+  return strlen("abc");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian3.c
new file mode 100644
index 000000000..2f11d355b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* Check that enumeration types are 4-byte types.  */
+
+enum e { e_1 };
+
+extern int i[sizeof (enum e)];
+int i[4];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian4.c
new file mode 100644
index 000000000..aede7f5c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian4.c
@@ -0,0 +1,5 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* Check that wchar_t is a 2-byte type.  */
+
+extern int i[sizeof (L'a')];
+int i[2];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian5.c
new file mode 100644
index 000000000..0bde6b0cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/symbian5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target arm*-*-symbianelf* } } */
+/* { dg-options "-fno-short-wchar" } */
+/* Check that wchar_t is a 4-byte type when -fno-short-wchar is
+   used.  */
+
+extern int i[sizeof (L'a')];
+int i[4];
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/sync-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/sync-1.c
new file mode 100644
index 000000000..d1b648105
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/sync-1.c
@@ -0,0 +1,26 @@
+
+/* { dg-do run { target sync_int_long } } */
+/* { dg-options "-O2" } */
+
+volatile int mem;
+
+int
+bar (int x, int y)
+{
+  if (x)
+    __sync_fetch_and_add(&mem, y);
+  return 0;
+}
+
+extern void abort (void);
+
+int
+main (int argc, char *argv[])
+{
+  mem = 0;
+  bar (0, 1);
+  bar (1, 1);
+  if (mem != 1)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/synchronize.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/synchronize.c
new file mode 100644
index 000000000..7ef10e2d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/synchronize.c
@@ -0,0 +1,6 @@
+/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-* } } } */
+
+void *foo (void)
+{
+  __sync_synchronize();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c
new file mode 100644
index 000000000..90407eb68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-16bit-ops.c
@@ -0,0 +1,203 @@
+/* Check that the compiler properly uses 16-bit encodings where available.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-Os -fno-builtin -mthumb" } */
+
+int
+f (int a, int b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "add	r0, r0, r1" } } */
+
+int
+f2 (int a, int b, int c)
+{
+  return b + c;
+}
+
+/* { dg-final { scan-assembler "adds	r0, r1, r2" } } */
+int
+g1 (int a)
+{
+  return a + 255;
+}
+
+/* { dg-final { scan-assembler "adds	r0, r0, #255" } } */
+
+int
+g2 (int a)
+{
+  return a + 256;
+}
+
+/* { dg-final { scan-assembler "add	r0, r0, #256" } } */
+
+int
+g3 (int a)
+{
+  return a - 255;
+}
+
+/* { dg-final { scan-assembler "subs	r0, r0, #255" } } */
+
+int
+g4 (int a)
+{
+  return a - 256;
+}
+
+/* { dg-final { scan-assembler "sub	r0, r0, #256" } } */
+
+int
+h1 (int a, int b)
+{
+  return b + 7;
+}
+
+/* { dg-final { scan-assembler "adds	r0, r1, #7" } } */
+
+int
+h2 (int a, int b)
+{
+  return b + 8;
+}
+
+/* { dg-final { scan-assembler "add	r0, r1, #8" } } */
+
+int
+h3 (int a, int b)
+{
+  return b - 7;
+}
+
+/* { dg-final { scan-assembler "subs	r0, r1, #7" } } */
+
+int
+h4 (int a, int b)
+{
+  return b - 8;
+}
+
+/* { dg-final { scan-assembler "sub	r0, r1, #8" } } */
+
+int
+i (int a, int b)
+{
+  return b;
+}
+
+/* { dg-final { scan-assembler "mov	r0, r1" } } */
+
+int
+j1 ()
+{
+  return 255;
+}
+
+/* { dg-final { scan-assembler "movs	r0, #255" } } */
+
+int
+j2 ()
+{
+  return 256;
+}
+
+/* { dg-final { scan-assembler "mov	r0, #256" } } */
+
+int
+k (int a, int b)
+{
+  return b << 15;
+}
+
+/* { dg-final { scan-assembler "lsls	r0, r1, #15" } } */
+
+int
+l1 (int a, int b)
+{
+  return a << b;
+}
+
+/* { dg-final { scan-assembler "lsls	r0, r0, r1" } } */
+
+int
+l2 (int a, int b, int c)
+{
+  return b << c;
+}
+
+/* { dg-final { scan-assembler "lsl	r0, r1, r2" } } */
+
+int
+m (int a, int b)
+{
+  return b >> 15;
+}
+
+/* { dg-final { scan-assembler "asrs	r0, r1, #15" } } */
+
+int
+n1 (int a, int b)
+{
+  return a >> b;
+}
+
+/* { dg-final { scan-assembler "asrs	r0, r0, r1" } } */
+
+int
+n2 (int a, int b, int c)
+{
+  return b >> c;
+}
+
+/* { dg-final { scan-assembler "asr	r0, r1, r2" } } */
+
+unsigned int
+o (unsigned int a, unsigned int b)
+{
+  return b >> 15;
+}
+
+/* { dg-final { scan-assembler "lsrs	r0, r1, #15" } } */
+
+unsigned int
+p1 (unsigned int a, unsigned int b)
+{
+  return a >> b;
+}
+
+/* { dg-final { scan-assembler "lsrs	r0, r0, r1" } } */
+
+unsigned int
+p2 (unsigned int a, unsigned int b, unsigned int c)
+{
+  return b >> c;
+}
+
+/* { dg-final { scan-assembler "lsr	r0, r1, r2" } } */
+
+int
+q (int a, int b)
+{
+  return b * a;
+}
+
+/* { dg-final { scan-assembler "muls	r0, r1, r0" } } */
+
+int
+r (int a, int b)
+{
+  return ~b;
+}
+
+/* { dg-final { scan-assembler "mvns	r0, r1" } } */
+
+int
+s (int a, int b)
+{
+  return -b;
+}
+
+/* { dg-final { scan-assembler "negs	r0, r1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-andsi.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-andsi.c
new file mode 100644
index 000000000..992d437c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-andsi.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+unsigned get_least_bits(unsigned value)
+{
+  return value << 9 >> 9;
+}
+
+/* { dg-final { scan-assembler "lsl" } } */
+/* { dg-final { scan-assembler "lsr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c
new file mode 100644
index 000000000..ee39887d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-bitfld1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-options "-O1 -mthumb" }  */
+
+struct foo
+{
+  unsigned b31 : 1;
+  unsigned b30 : 1;
+  unsigned b29 : 1;
+  unsigned b28 : 1;
+  unsigned rest : 28;
+};
+foo(a)
+     struct foo a;
+{
+  return a.b30;
+}
+
+/* { dg-final { scan-assembler-times "lsl" 1 } } */
+/* { dg-final { scan-assembler-times "lsr" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-branch1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-branch1.c
new file mode 100644
index 000000000..73f6cf78a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-branch1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { arm_thumb1_ok || arm_thumb2_ok } } } */
+/* { dg-options "-Os -mthumb" } */
+
+int returnbool(int a, int b)
+{
+    if (a < b)
+        return 1;
+    return 0;
+}
+
+/* { dg-final { scan-assembler-not "eor" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-builtin-trap.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-builtin-trap.c
new file mode 100644
index 000000000..22e90e7d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-builtin-trap.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb" } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+void
+trap ()
+{
+  __builtin_trap ();
+}
+
+/* { dg-final { scan-assembler "0xdeff" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c
new file mode 100644
index 000000000..5894df964
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-cbranchqi.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+int ldrb(unsigned char* p)
+{
+  if (p[8] <= 0x7F)
+    return 2;
+  else
+    return 5;
+}
+
+
+/* { dg-final { scan-assembler "127" } } */
+/* { dg-final { scan-assembler "bhi|bls" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-comparisons.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-comparisons.c
new file mode 100644
index 000000000..45be2cf74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-comparisons.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+int foo(char ch)
+{
+  switch (ch) {
+    case '-':
+    case '?':
+    case '/':
+    case 99:
+        return 1;
+    default:
+        return 0;
+  }
+}
+
+/* { dg-final { scan-assembler-times "cmp\[\\t \]*r.,\[\\t \]*#63" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c
new file mode 100644
index 000000000..f2c0225a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-find-work-register.c
@@ -0,0 +1,40 @@
+/* Wrong method to get number of arg reg will cause argument corruption.  */
+/* { dg-do run } */
+/* { dg-require-effective-target arm_eabi } */
+/* { dg-options "-mthumb -O1" } */
+
+extern void abort (void);
+
+int foo (int, int, int, int) __attribute__((noinline));
+
+int
+foo (int a, int b, int c, int d)
+{
+  register int m asm ("r8");
+
+  m = a;
+  m += b;
+  m += c;
+  m += d;
+
+  asm ("" : "=r" (m) : "0" (m));
+
+  return m;
+}
+
+int
+main ()
+{
+  volatile int a = 10;
+  volatile int b = 20;
+  volatile int c = 30;
+  volatile int d = 40;
+  volatile int sum = 0;
+
+  sum = foo (a, b, c, d);
+
+  if (sum != 100)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt-2.c
new file mode 100644
index 000000000..3da9ef080
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt-2.c
@@ -0,0 +1,18 @@
+/* Check that Thumb 16-bit shifts by immediate can be if-converted.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2 -mthumb" } */
+
+int
+foo (int a, int b)
+{
+  if (a != b)
+      a = a << 1;
+  else
+      a = a >> 1;
+
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "lslne" } } */
+/* { dg-final { scan-assembler "asreq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c
new file mode 100644
index 000000000..d51827aa7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c
@@ -0,0 +1,19 @@
+/* Check that Thumb 16-bit shifts can be if-converted.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2 -mthumb" } */
+
+int
+foo (int a, int b)
+{
+  if (a != b)
+    {
+      a = a << b;
+      a = a >> 1;
+    }
+
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "lslne" } } */
+/* { dg-final { scan-assembler "asrne" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ltu.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ltu.c
new file mode 100644
index 000000000..d057ea34d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-ltu.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-options "-mcpu=arm1136jf-s -mthumb -O2" } */
+
+void f(unsigned a, unsigned b, unsigned c, unsigned d)
+{
+  if (a <= b || c > d)
+    foo();
+  else
+    bar();
+}
+
+/* { dg-final { scan-assembler-not "uxtb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-stackframe.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-stackframe.c
new file mode 100644
index 000000000..f6c78804e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb-stackframe.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+extern void bar(int*);
+int foo()
+{
+  int x;
+  bar(&x);
+  return x;
+}
+
+/* { dg-final { scan-assembler-not "sub\[\\t \]*sp,\[\\t \]*sp," } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c
new file mode 100644
index 000000000..31b8bd692
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c
@@ -0,0 +1,12 @@
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { ! { arm_thumb1 } } } */
+
+int
+mymul3 (int x)
+{
+  return x * 0x555;
+}
+
+/* { dg-final { scan-assembler "mul\[\\t \]*r.,\[\\t \]*r." } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c
new file mode 100644
index 000000000..eb16d2fc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c
@@ -0,0 +1,34 @@
+/* Check for thumb1 far jump. Shouldn't save lr for small leaf functions
+ * even with a branch in it.  */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { ! { arm_thumb1 } } } */
+
+void f()
+{
+  for (;;);
+}
+
+volatile int g;
+void f2(int i)
+{
+  if (i) g=0;
+}
+
+void f3(int i)
+{
+  if (i) {
+    g=0;
+    g=1;
+    g=2;
+    g=3;
+    g=4;
+    g=5;
+    g=6;
+    g=7;
+    g=8;
+    g=9;
+  }
+}
+
+/* { dg-final { scan-assembler-not "push.*lr" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c
new file mode 100644
index 000000000..c6878f8ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c
@@ -0,0 +1,57 @@
+/* Check for thumb1 far jump. This is the extreme case that far jump
+ * will be used with minimum number of instructions. By passing this case
+ * it means the heuristic of saving lr for far jump meets the most extreme
+ * requirement.  */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { ! { arm_thumb1 } } } */
+
+volatile register r4 asm("r4");
+void f3(int i)
+{
+#define GO(n) \
+  extern volatile int g_##n; \
+  r4=(int)&g_##n;
+
+#define GO8(n) \
+  GO(n##_0) \
+  GO(n##_1) \
+  GO(n##_2) \
+  GO(n##_3) \
+  GO(n##_4) \
+  GO(n##_5) \
+  GO(n##_6) \
+  GO(n##_7)
+
+#define GO64(n) \
+  GO8(n##_0) \
+  GO8(n##_1) \
+  GO8(n##_2) \
+  GO8(n##_3) \
+  GO8(n##_4) \
+  GO8(n##_5) \
+  GO8(n##_6) \
+  GO8(n##_7) \
+
+#define GO498(n) \
+  GO64(n##_0) \
+  GO64(n##_1) \
+  GO64(n##_2) \
+  GO64(n##_3) \
+  GO64(n##_4) \
+  GO64(n##_5) \
+  GO64(n##_6) \
+  GO8(n##_0) \
+  GO8(n##_1) \
+  GO8(n##_2) \
+  GO8(n##_3) \
+  GO8(n##_4) \
+  GO8(n##_5) \
+  GO(n##_0) \
+  GO(n##_1) \
+
+  if (i) {
+    GO498(0);
+  }
+}
+
+/* { dg-final { scan-assembler "push.*lr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c
new file mode 100644
index 000000000..90559bacb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c
@@ -0,0 +1,108 @@
+/* Catch reload ICE on target thumb1 with far jump optimization.
+ * It is also a valid case for non-thumb1 target.  */
+
+/* Add -mno-lra option as it is only reproducable with reload.  It will
+   be removed after reload is completely removed.  */
+/* { dg-options "-mno-lra -fomit-frame-pointer" } */
+/* { dg-do compile } */
+
+#define C      2
+#define A      4
+#define RGB  (C | A)
+#define GRAY (A)
+
+typedef unsigned long uint_32;
+typedef unsigned char byte;
+typedef byte        * bytep;
+
+typedef struct ss
+{
+   uint_32 w;
+   uint_32 r;
+   byte c;
+   byte b;
+   byte p;
+} info;
+
+typedef info * infop;
+
+void
+foo(infop info, bytep row)
+{
+   uint_32 iw = info->w;
+   if (info->c == RGB)
+   {
+      if (info->b == 8)
+      {
+         bytep sp = row + info->r;
+         bytep dp = sp;
+         byte save;
+         uint_32 i;
+
+         for (i = 0; i < iw; i++)
+         {
+            save = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = save;
+         }
+      }
+
+      else
+      {
+         bytep sp = row + info->r;
+         bytep dp = sp;
+         byte save[2];
+         uint_32 i;
+
+         for (i = 0; i < iw; i++)
+         {
+            save[0] = *(--sp);
+            save[1] = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = save[0];
+            *(--dp) = save[1];
+         }
+      }
+   }
+   else if (info->c == GRAY)
+   {
+      if (info->b == 8)
+      {
+         bytep sp = row + info->r;
+         bytep dp = sp;
+         byte save;
+         uint_32 i;
+
+         for (i = 0; i < iw; i++)
+         {
+            save = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = save;
+         }
+      }
+      else
+      {
+         bytep sp = row + info->r;
+         bytep dp = sp;
+         byte save[2];
+         uint_32 i;
+
+         for (i = 0; i < iw; i++)
+         {
+            save[0] = *(--sp);
+            save[1] = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = *(--sp);
+            *(--dp) = save[0];
+            *(--dp) = save[1];
+         }
+      }
+   }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-imm.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-imm.c
new file mode 100644
index 000000000..6d950aa18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-imm.c
@@ -0,0 +1,12 @@
+/* Check for thumb1 imm [255-510] moves.  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { ! { arm_thumb1 } } } */
+
+int f()
+{
+  return 257;
+}
+
+/* { dg-final { scan-assembler-not "ldr" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-mul-moves.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-mul-moves.c
new file mode 100644
index 000000000..6235774fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-mul-moves.c
@@ -0,0 +1,11 @@
+/* Check for unnecessary register moves.  */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+int f(int x)
+{
+  return x*42;
+}
+
+/* { dg-final { scan-assembler-not "mov\[\\t \]*r0," } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c
new file mode 100644
index 000000000..df269fc84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-options "-mthumb -fpic -mpic-register=9" } */
+
+int g_test;
+
+int
+foo (int par)
+{
+    g_test = par;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c
new file mode 100644
index 000000000..6e9b2570a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-options "-mthumb -fpic -msingle-pic-base" } */
+
+int g_test;
+
+int
+foo (int par)
+{
+    g_test = par;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c
new file mode 100644
index 000000000..d75f13aa0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-1.c
@@ -0,0 +1,12 @@
+/* Use ADDS clobbering source operand, rather than CMN */
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "adds" } } */
+/* { dg-final { scan-assembler-not "cmn" } } */
+
+void foo1(void);
+void bar5(int x)
+{
+  if (x == -15)
+    foo1();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c
new file mode 100644
index 000000000..358bc6e14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cmpneg2add-2.c
@@ -0,0 +1,12 @@
+/* Use ADDS with a scratch, rather than CMN */
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "adds" } } */
+/* { dg-final { scan-assembler-not "cmn" } } */
+
+void foo1(int);
+void bar5(int x)
+{
+  if (x == -1)
+    foo1(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c
new file mode 100644
index 000000000..45ab605e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-1.c
@@ -0,0 +1,13 @@
+/* Use conditional compare */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { arm_thumb1_ok } } */
+/* { dg-final { scan-assembler "cmpne" } } */
+
+int f(int i, int j) 
+{
+  if ( (i == '+') || (j == '-') ) {
+    return 1;
+  } else {
+    return 0;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c
new file mode 100644
index 000000000..17d9a8f76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-2.c
@@ -0,0 +1,13 @@
+/* Use conditional compare */                                                                                         
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { arm_thumb1_ok } } */
+/* { dg-final { scan-assembler "cmpeq" } } */
+
+int f(int i, int j) 
+{
+  if ( (i == '+') && (j == '-') ) {
+    return 1;
+  } else {
+    return 0;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c
new file mode 100644
index 000000000..6b2a79b1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-3.c
@@ -0,0 +1,12 @@
+/* Use conditional compare */                                                                                         
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { arm_thumb1_ok } } */
+/* { dg-final { scan-assembler "cmpgt" } } */
+
+int f(int i, int j)
+{
+  if ( (i >= '+') ? (j > '-') : 0)
+    return 1;
+  else
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c
new file mode 100644
index 000000000..80e1076fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-cond-cmp-4.c
@@ -0,0 +1,12 @@
+/* Use conditional compare */                                                                                         
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { arm_thumb1_ok } } */
+/* { dg-final { scan-assembler "cmpgt" } } */
+
+int f(int i, int j)
+{
+  if ( (i >= '+') ? (j <= '-') : 1)
+    return 1;
+  else
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-2.c
new file mode 100644
index 000000000..b53df2fa1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-2.c
@@ -0,0 +1,15 @@
+/* In Thumb-2 mode, when optimizing for size, generate a "muls"
+   instruction and use the resulting condition flags rather than a
+   separate compare instruction.  */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "muls" } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+
+int x;
+
+void f(int i, int j)
+{
+  if (i * j < 0)
+    x = 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-3.c
new file mode 100644
index 000000000..143a6deee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space-3.c
@@ -0,0 +1,17 @@
+/* In Thumb-2 mode, when optimizing for size, generate a "muls"
+   instruction and use the resulting condition flags rather than a
+   separate compare instruction.  */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "muls" } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+
+int x;
+
+int f(int i, int j)
+{
+  i = i * j;
+  if (i < 0)
+    x = 1;
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space.c
new file mode 100644
index 000000000..8cf0cb40f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-space.c
@@ -0,0 +1,10 @@
+/* Use 16-bit multiply instruction in Thumb-2 mode when optimizing for
+   size.  */
+/* { dg-options "-mthumb -Os" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "muls" } } */
+
+int f(int i, int j) 
+{
+  return i * j;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-speed.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-speed.c
new file mode 100644
index 000000000..03cccdb65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-mul-speed.c
@@ -0,0 +1,27 @@
+/* Do not use 16-bit multiply instructions in Thumb-2 mode when
+   optimizing for speed.  */
+/* { dg-options "-mthumb -O2" }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler-not "muls" } } */
+
+int f(int i, int j) 
+{
+  return i * j;
+}
+
+int x;
+
+void g(int i, int j)
+{
+  if (i * j < 0)
+    x = 1;
+}
+
+int h(int i, int j)
+{
+  i = i * j;
+  if (i < 0)
+    x = 1;
+  return i;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c
new file mode 100644
index 000000000..e10ea0375
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant1.c
@@ -0,0 +1,27 @@
+/* Ensure simple replicated constant immediates work.  */
+/* { dg-options "-mthumb -O2" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+int
+foo1 (int a)
+{
+  return a + 0xfefefefe;
+}
+
+/* { dg-final { scan-assembler "add.*#-16843010" } } */
+
+int
+foo2 (int a)
+{
+  return a - 0xab00ab00;
+}
+
+/* { dg-final { scan-assembler "sub.*#-1426019584" } } */
+
+int
+foo3 (int a)
+{
+  return a & 0x00cd00cd;
+}
+
+/* { dg-final { scan-assembler "and.*#13435085" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c
new file mode 100644
index 000000000..3739adba5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant2.c
@@ -0,0 +1,75 @@
+/* Ensure split constants can use replicated patterns.  */
+/* { dg-options "-mthumb -O2" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+int
+foo1 (int a)
+{
+  return a + 0xfe00fe01;
+}
+
+/* { dg-final { scan-assembler "add.*#-33489408" } } */
+/* { dg-final { scan-assembler "add.*#1" } } */
+
+int
+foo2 (int a)
+{
+  return a + 0xdd01dd00;
+}
+
+/* { dg-final { scan-assembler "add.*#-587145984" } } */
+/* { dg-final { scan-assembler "add.*#65536" } } */
+
+int
+foo3 (int a)
+{
+  return a + 0x00443344;
+}
+
+/* { dg-final { scan-assembler "add.*#4456516" } } */
+/* { dg-final { scan-assembler "add.*#13056" } } */
+
+int
+foo4 (int a)
+{
+  return a + 0x77330033;
+}
+
+/* { dg-final { scan-assembler "add.*#1996488704" } } */
+/* { dg-final { scan-assembler "add.*#3342387" } } */
+
+int
+foo5 (int a)
+{
+  return a + 0x11221122;
+}
+
+/* { dg-final { scan-assembler "add.*#285217024" } } */
+/* { dg-final { scan-assembler "add.*#2228258" } } */
+
+int
+foo6 (int a)
+{
+  return a + 0x66666677;
+}
+
+/* { dg-final { scan-assembler "add.*#1717986918" } } */
+/* { dg-final { scan-assembler "add.*#17" } } */
+
+int
+foo7 (int a)
+{
+  return a + 0x99888888;
+}
+
+/* { dg-final { scan-assembler "add.*#-2004318072" } } */
+/* { dg-final { scan-assembler "add.*#285212672" } } */
+
+int
+foo8 (int a)
+{
+  return a + 0xdddddfff;
+}
+
+/* { dg-final { scan-assembler "add.*#-572662307" } } */
+/* { dg-final { scan-assembler "addw.*#546" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c
new file mode 100644
index 000000000..eb6ad443c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant3.c
@@ -0,0 +1,28 @@
+/* Ensure negated/inverted replicated constant immediates work.  */
+/* { dg-options "-mthumb -O2" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+int
+foo1 (int a)
+{
+  return a | 0xffffff00;
+}
+
+/* { dg-final { scan-assembler "orn.*#255" } } */
+
+int
+foo2 (int a)
+{
+  return a & 0xffeeffee;
+}
+
+/* { dg-final { scan-assembler "bic.*#1114129" } } */
+
+int
+foo3 (int a)
+{
+  return a & 0xaaaaaa00;
+}
+
+/* { dg-final { scan-assembler "and.*#-1431655766" } } */
+/* { dg-final { scan-assembler "bic.*#170" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c
new file mode 100644
index 000000000..24efdcf34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-replicated-constant4.c
@@ -0,0 +1,22 @@
+/* Ensure replicated constants don't make things worse.  */
+/* { dg-options "-mthumb -O2" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+int
+foo1 (int a)
+{
+  /* It might be tempting to use 0x01000100, but it wouldn't help. */
+  return a + 0x01f001e0;
+}
+
+/* { dg-final { scan-assembler "add.*#32505856" } } */
+/* { dg-final { scan-assembler "add.*#480" } } */
+
+int
+foo2 (int a)
+{
+  return a + 0x0f100e10;
+}
+
+/* { dg-final { scan-assembler "add.*#252706816" } } */
+/* { dg-final { scan-assembler "add.*#3600" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c
new file mode 100644
index 000000000..9852ea5d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c
@@ -0,0 +1,74 @@
+/* The option -mslow-flash-data is just for performance tuning, it
+   doesn't totally disable the use of literal pools.  But for below
+   simple cases, the use of literal pool should be replaced by
+   movw/movt or read-only constant pool.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_cortex_m } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O2 -mthumb -mslow-flash-data" } */
+
+float sf;
+double df;
+long long l;
+static char *p = "Hello World";
+
+float
+testsf (float *p)
+{
+  if (*p > 1.1234f)
+    return 2.1234f;
+  else
+    return 3.1234f;
+}
+
+double
+testdf (double *p)
+{
+  if (*p > 4.1234)
+    return 2.1234;
+  else
+    return 3.1234;
+}
+
+long long
+testll (long long *p)
+{
+  if (*p > 0x123456789ABCDEFll)
+    return 0x111111111ll;
+  else
+    return 0x222222222ll;
+}
+
+char *
+testchar ()
+{
+  return p + 4;
+}
+
+int
+foo (int a, int b)
+{
+  int i;
+  volatile *labelref = &&label1;
+
+  if (a > b)
+    {
+      while (i < b)
+	{
+	  a += *labelref;
+	  i += 1;
+	}
+      goto *labelref;
+    }
+  else
+    b = b + 3;
+
+  a = a * b;
+
+label1:
+  return a + b;
+}
+
+/* { dg-final { scan-assembler-times "movt" 13 } } */
+/* { dg-final { scan-assembler-times "movt.*LC0\\+4" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/tlscall.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/tlscall.c
new file mode 100644
index 000000000..366c1ae71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/tlscall.c
@@ -0,0 +1,31 @@
+/* Test non-duplication of tlscall insn */
+
+/* { dg-do assemble } */
+/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */
+
+typedef struct _IO_FILE FILE;
+
+extern int foo(void);
+extern int bar(void);
+
+void uuid__generate_time()
+{
+ static int has_init = 0;
+ static __thread int state_fd = -2;
+ static __thread FILE *state_f;
+
+ if (!has_init) {
+   foo();
+   has_init = 1;
+ }
+
+ if (state_fd == -2) {
+  if (!state_f) {
+   state_fd = -1;
+  }
+ }
+ if (state_fd >= 0) {
+  while (bar() < 0) {}
+ }
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c
new file mode 100644
index 000000000..c4f564042
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_unaligned } */
+/* { dg-options "-O2" } */
+
+#include <string.h>
+
+void unknown_alignment (char *dest, char *src)
+{
+  memcpy (dest, src, 15);
+}
+
+/* We should see three unaligned word loads and store pairs, one unaligned
+   ldrh/strh pair, and an ldrb/strb pair.  Sanity check that.  */
+
+/* { dg-final { scan-assembler-times "@ unaligned" 8 } } */
+/* { dg-final { scan-assembler-times "ldrh" 1 } } */
+/* { dg-final { scan-assembler-times "strh" 1 } } */
+/* { dg-final { scan-assembler-times "ldrb" 1 } } */
+/* { dg-final { scan-assembler-times "strb" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c
new file mode 100644
index 000000000..1ad730d64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_unaligned } */
+/* { dg-options "-O2" } */
+
+#include <string.h>
+
+char dest[16] = { 0 };
+
+void aligned_dest (char *src)
+{
+  memcpy (dest, src, 15);
+}
+
+/* Expect a multi-word store for the main part of the copy, but subword
+   loads/stores for the remainder.  */
+
+/* { dg-final { scan-assembler-times "ldmia" 0 } } */
+/* { dg-final { scan-assembler-times "ldrd" 0 } } */
+/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
+/* { dg-final { scan-assembler-times "strd" 1 { target { arm_prefer_ldrd_strd } } } } */
+/* { dg-final { scan-assembler-times "ldrh" 1 } } */
+/* { dg-final { scan-assembler-times "strh" 1 } } */
+/* { dg-final { scan-assembler-times "ldrb" 1 } } */
+/* { dg-final { scan-assembler-times "strb" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c
new file mode 100644
index 000000000..d0b09bd48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-3.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_unaligned } */
+/* { dg-options "-O2" } */
+
+#include <string.h>
+
+char src[16] = {0};
+
+void aligned_src (char *dest)
+{
+  memcpy (dest, src, 15);
+}
+
+/* Expect a multi-word load for the main part of the copy, but subword
+   loads/stores for the remainder.  */
+
+/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
+/* { dg-final { scan-assembler-times "ldrd" 1 { target { arm_prefer_ldrd_strd } } } } */
+/* { dg-final { scan-assembler-times "strd" 0 } } */
+/* { dg-final { scan-assembler-times "stm" 0 } } */
+/* { dg-final { scan-assembler-times "ldrh" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
+/* { dg-final { scan-assembler-times "strh" 1 } } */
+/* { dg-final { scan-assembler-times "ldrb" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
+/* { dg-final { scan-assembler-times "strb" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c
new file mode 100644
index 000000000..830e22e09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unaligned-memcpy-4.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_unaligned } */
+/* { dg-options "-O2" } */
+
+#include <string.h>
+
+char src[16] = { 0 };
+char dest[16] = { 0 };
+
+void aligned_both (void)
+{
+  memcpy (dest, src, 15);
+}
+
+/* We know both src and dest to be aligned: expect multiword loads/stores.  */
+
+/* { dg-final { scan-assembler-times "ldmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
+/* { dg-final { scan-assembler-times "stmia" 1 { target { ! { arm_prefer_ldrd_strd } } } } } */
+/* { dg-final { scan-assembler "ldrd" { target { arm_prefer_ldrd_strd } } } } */
+/* { dg-final { scan-assembler-times "ldm" 0 { target { arm_prefer_ldrd_strd } } } } */
+/* { dg-final { scan-assembler "strd" { target { arm_prefer_ldrd_strd } } } } */
+/* { dg-final { scan-assembler-times "stm" 0 { target { arm_prefer_ldrd_strd } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
new file mode 100644
index 000000000..3b4ab048f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned char foo (unsigned char c)
+{
+  return (c >= '0') && (c <= '9');
+}
+
+/* { dg-final { scan-assembler-not "uxtb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
new file mode 100644
index 000000000..b610b7361
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-options "-O" } */
+
+unsigned short foo (unsigned short x)
+{
+  unsigned char i = 0;
+  for (i = 0; i < 8; i++)
+    {
+      x >>= 1;
+      x &= 0x7fff;
+    }
+  return x;
+}
+
+/* { dg-final { scan-assembler "ands" } } */
+/* { dg-final { scan-assembler-not "uxtb" } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/va_list.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/va_list.c
new file mode 100644
index 000000000..b988a0d33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/va_list.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_eabi } */
+
+#include <stdarg.h>
+#include <stddef.h>
+
+/* AAPCS \S 7.1.4 requires that va_list match the structure shown
+   here */
+typedef struct my_va_list 
+{
+  void *ap;
+} my_va_list;
+
+int 
+main () {
+  if (sizeof (va_list) != sizeof (my_va_list))
+    return 1;
+  /* This check confirms both that "va_list" has a member named "__ap"
+     and that it is located at the correct position.  */
+  if (offsetof (va_list, __ap) 
+      != offsetof (my_va_list, ap))
+    return 2;
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-noalign.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-noalign.c
new file mode 100644
index 000000000..a934233a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-noalign.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-mfpu=neon -ffast-math -ftree-vectorize -fno-common -O2 -mno-unaligned-access" } */
+
+
+/* Test for-mno-unaligned-access and -ftree-vectorize  and results bus error. */
+#define N 128
+
+char ia[N];
+char ib[N+1];
+
+int main() {
+  int i;
+  for(i = 0; i < N; ++i) {
+    ia[i] = ib[i + 1];
+  }
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c
new file mode 100644
index 000000000..ff033d437
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-btruncf.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */
+/* { dg-add-options arm_v8_neon } */
+
+#define N 32
+
+void
+foo (float *output, float *input)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = __builtin_truncf (input[i]);
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_btruncf } } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c
new file mode 100644
index 000000000..b54f358f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-ceilf.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */
+/* { dg-add-options arm_v8_neon } */
+
+#define N 32
+
+void
+foo (float *output, float *input)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = __builtin_ceilf (input[i]);
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_ceilf } } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c
new file mode 100644
index 000000000..02e188d96
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-floorf.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */
+/* { dg-add-options arm_v8_neon } */
+
+#define N 32
+
+void
+foo (float *output, float *input)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = __builtin_floorf (input[i]);
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_floorf } } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c
new file mode 100644
index 000000000..85e205806
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vect-rounding-roundf.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize" } */
+/* { dg-add-options arm_v8_neon } */
+
+#define N 32
+
+void
+foo (float *output, float *input)
+{
+  int i = 0;
+  /* Vectorizable.  */
+  for (i = 0; i < N; i++)
+    output[i] = __builtin_roundf (input[i]);
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_call_roundf } } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-1.c
new file mode 100644
index 000000000..d6d9c4642
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-1.c
@@ -0,0 +1,139 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_vfp_ok } */
+
+extern float fabsf (float);
+extern float sqrtf (float);
+extern double fabs (double);
+extern double sqrt (double);
+
+volatile float f1, f2, f3;
+
+void test_sf() {
+  /* abssf2_vfp */
+  /* { dg-final { scan-assembler "fabss" } } */
+  f1 = fabsf (f1);
+  /* negsf2_vfp */
+  /* { dg-final { scan-assembler "fnegs" } } */
+  f1 = -f1;
+  /* addsf3_vfp */
+  /* { dg-final { scan-assembler "fadds" } } */
+  f1 = f2 + f3;
+  /* subsf3_vfp */
+  /* { dg-final { scan-assembler "fsubs" } } */
+  f1 = f2 - f3;
+  /* divsf3_vfp */
+  /* { dg-final { scan-assembler "fdivs" } } */
+  f1 = f2 / f3;
+  /* mulsf3_vfp */
+  /* { dg-final { scan-assembler "fmuls" } } */
+  f1 = f2 * f3;
+  /* mulsf3negsf_vfp */
+  /* { dg-final { scan-assembler "fnmuls" } } */
+  f1 = -f2 * f3;
+  /* mulsf3addsf_vfp */
+  /* { dg-final { scan-assembler "fmacs" } } */
+  f1 = f2 * f3 + f1;
+  /* mulsf3subsf_vfp */
+  /* { dg-final { scan-assembler "fmscs" } } */
+  f1 = f2 * f3 - f1;
+  /* mulsf3negsfaddsf_vfp */
+  /* { dg-final { scan-assembler "fnmacs" } } */
+  f1 = f2 - f3 * f1;
+  /* mulsf3negsfsubsf_vfp */
+  /* { dg-final { scan-assembler "fnmscs" } } */
+  f1 = -f2 * f3 - f1;
+  /* sqrtsf2_vfp */
+  /* { dg-final { scan-assembler "fsqrts" } } */
+  f1 = sqrtf (f1);
+}
+
+volatile double d1, d2, d3;
+
+void test_df() {
+  /* absdf2_vfp */
+  /* { dg-final { scan-assembler "fabsd" } } */
+  d1 = fabs (d1);
+  /* negdf2_vfp */
+  /* { dg-final { scan-assembler "fnegd" } } */
+  d1 = -d1;
+  /* adddf3_vfp */
+  /* { dg-final { scan-assembler "faddd" } } */
+  d1 = d2 + d3;
+  /* subdf3_vfp */
+  /* { dg-final { scan-assembler "fsubd" } } */
+  d1 = d2 - d3;
+  /* divdf3_vfp */
+  /* { dg-final { scan-assembler "fdivd" } } */
+  d1 = d2 / d3;
+  /* muldf3_vfp */
+  /* { dg-final { scan-assembler "fmuld" } } */
+  d1 = d2 * d3;
+  /* muldf3negdf_vfp */
+  /* { dg-final { scan-assembler "fnmuld" } } */
+  d1 = -d2 * d3;
+  /* muldf3adddf_vfp */
+  /* { dg-final { scan-assembler "fmacd" } } */
+  d1 = d2 * d3 + d1;
+  /* muldf3subdf_vfp */
+  /* { dg-final { scan-assembler "fmscd" } } */
+  d1 = d2 * d3 - d1;
+  /* muldf3negdfadddf_vfp */
+  /* { dg-final { scan-assembler "fnmacd" } } */
+  d1 = d2 - d3 * d1;
+  /* muldf3negdfsubdf_vfp */
+  /* { dg-final { scan-assembler "fnmscd" } } */
+  d1 = -d2 * d3 - d1;
+  /* sqrtdf2_vfp */
+  /* { dg-final { scan-assembler "fsqrtd" } } */
+  d1 = sqrt (d1);
+}
+
+volatile int i1;
+volatile unsigned int u1;
+
+void test_convert () {
+  /* extendsfdf2_vfp */
+  /* { dg-final { scan-assembler "fcvtds" } } */
+  d1 = f1;
+  /* truncdfsf2_vfp */
+  /* { dg-final { scan-assembler "fcvtsd" } } */
+  f1 = d1;
+  /* truncsisf2_vfp */
+  /* { dg-final { scan-assembler "ftosizs" } } */
+  i1 = f1;
+  /* truncsidf2_vfp */
+  /* { dg-final { scan-assembler "ftosizd" } } */
+  i1 = d1;
+  /* fixuns_truncsfsi2 */
+  /* { dg-final { scan-assembler "ftouizs" } } */
+  u1 = f1;
+  /* fixuns_truncdfsi2 */
+  /* { dg-final { scan-assembler "ftouizd" } } */
+  u1 = d1;
+  /* floatsisf2_vfp */
+  /* { dg-final { scan-assembler "fsitos" } } */
+  f1 = i1;
+  /* floatsidf2_vfp */
+  /* { dg-final { scan-assembler "fsitod" } } */
+  d1 = i1;
+  /* floatunssisf2 */
+  /* { dg-final { scan-assembler "fuitos" } } */
+  f1 = u1;
+  /* floatunssidf2 */
+  /* { dg-final { scan-assembler "fuitod" } } */
+  d1 = u1;
+}
+
+void test_ldst (float f[], double d[]) {
+  /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */
+  /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
+  /* { dg-final { scan-assembler "add.+ r0, #1024" } } */
+  /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\]\\\]\n" } } */
+  f[256] = f[255] + f[-255];
+
+  /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */
+  /* { dg-final { scan-assembler "fldd.+ \\\[r\[1-9\], #-1016\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */
+  /* { dg-final { scan-assembler "fstd.+ \\\[r1, #256\\\]" } } */
+  d[32] = d[127] + d[-127];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
new file mode 100644
index 000000000..280471496
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void bar (double);
+
+void
+foo (double *p, double a, int n)
+{
+  do
+    bar (*--p + a);
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmdbd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
new file mode 100644
index 000000000..f5940ef97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void baz (float);
+
+void
+foo (float *p, float a, int n)
+{
+  do
+    bar (*--p + a);
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmdbs" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
new file mode 100644
index 000000000..6f0526712
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void bar (double);
+
+void
+foo (double *p, double a, int n)
+{
+  do
+    bar (*p++ + a);
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmiad" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmias.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
new file mode 100644
index 000000000..79ad7bf17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void baz (float);
+
+void
+foo (float *p, float a, int n)
+{
+  do
+    bar (*p++ + a);
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmias" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
new file mode 100644
index 000000000..d8093d9d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (double *p, double a, double b, int n)
+{
+  double c = a + b;
+  do
+    *--p = c;
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmdbd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
new file mode 100644
index 000000000..bb19d902b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (float *p, float a, float b, int n)
+{
+  float c = a + b;
+  do
+    *--p = c;
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmdbs" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmiad.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
new file mode 100644
index 000000000..1b6d22bd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (double *p, double a, double b, int n)
+{
+  double c = a + b;
+  do
+    *p++ = c;
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmiad" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmias.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmias.c
new file mode 100644
index 000000000..3da632745
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vfp-stmias.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (float *p, float a, float b, int n)
+{
+  float c = a + b;
+  do
+    *p++ = c;
+  while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmias" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmdf.c
new file mode 100644
index 000000000..1a172b8c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmdf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  return __builtin_fmax (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmsf.c
new file mode 100644
index 000000000..bc2326187
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vmaxnmsf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  return __builtin_fmaxf (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmdf.c
new file mode 100644
index 000000000..c2a6915b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmdf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  return __builtin_fmin (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmsf.c
new file mode 100644
index 000000000..eee43bce1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vminnmsf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-ffast-math" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  return __builtin_fminf (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c
new file mode 100644
index 000000000..c519419cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-1.c
@@ -0,0 +1,18 @@
+/* { dg-require-effective-target arm_eabi } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct {
+  char a:1;
+  char b:7;
+  int c;
+} BitStruct;
+
+volatile BitStruct bits;
+
+int foo ()
+{
+  return bits.b;
+}
+
+/* { dg-final { scan-assembler "ldrb\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c
new file mode 100644
index 000000000..eb0aaf7f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-2.c
@@ -0,0 +1,18 @@
+/* { dg-require-effective-target arm_eabi } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct {
+  volatile unsigned long a:8;
+  volatile unsigned long b:8;
+  volatile unsigned long c:16;
+} BitStruct;
+
+BitStruct bits;
+
+unsigned long foo ()
+{
+  return bits.b;
+}
+
+/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c
new file mode 100644
index 000000000..0f5dde08b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-3.c
@@ -0,0 +1,18 @@
+/* { dg-require-effective-target arm_eabi } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct {
+  volatile unsigned long a:8;
+  volatile unsigned long b:8;
+  volatile unsigned long c:16;
+} BitStruct;
+
+BitStruct bits;
+
+unsigned long foo ()
+{
+  return bits.c;
+}
+
+/* { dg-final { scan-assembler "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c
new file mode 100644
index 000000000..805dab164
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/volatile-bitfields-4.c
@@ -0,0 +1,30 @@
+/* { dg-require-effective-target arm_eabi } */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "ldr\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "str\[\\t \]+\[^\n\]*,\[\\t \]*\\\[\[^\n\]*\\\]" 2 } } */
+/* { dg-final { scan-assembler-not "strb" } } */
+
+struct thing {
+  unsigned a: 8;
+  unsigned b: 8;
+  unsigned c: 8;
+  unsigned d: 8;
+};
+
+struct thing2 {
+  volatile unsigned a: 8;
+  volatile unsigned b: 8;
+  volatile unsigned c: 8;
+  volatile unsigned d: 8;
+};
+
+void test1(volatile struct thing *t)
+{
+  t->a = 5;
+}
+
+void test2(struct thing2 *t)
+{
+  t->a = 5;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrinta-ce.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrinta-ce.c
new file mode 100644
index 000000000..71c5b3b0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrinta-ce.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2 -marm -march=armv8-a" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double foo (double a)
+{
+  if (a > 3.0)
+    return  __builtin_round (a);
+
+  return 0.0;
+}
+
+/* { dg-final { scan-assembler-times "vrinta.f64\td\[0-9\]+" 1 } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf32.c
new file mode 100644
index 000000000..bea4aca55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x)
+{
+  return __builtin_roundf (x);
+}
+
+/* { dg-final { scan-assembler-times "vrinta.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf64.c
new file mode 100644
index 000000000..0c393474f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintaf64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x)
+{
+  return __builtin_round (x);
+}
+
+/* { dg-final { scan-assembler-times "vrinta.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf32.c
new file mode 100644
index 000000000..33c22885f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x)
+{
+  return __builtin_floorf (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintm.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf64.c
new file mode 100644
index 000000000..d1b3db964
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintmf64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x)
+{
+  return __builtin_floor (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintm.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf32.c
new file mode 100644
index 000000000..ecea15db6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x)
+{
+  return __builtin_ceilf (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintp.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf64.c
new file mode 100644
index 000000000..a4ce30d64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintpf64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x)
+{
+  return __builtin_ceil (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintp.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf32.c
new file mode 100644
index 000000000..f1b03be5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x)
+{
+  return __builtin_nearbyintf (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintr.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf64.c
new file mode 100644
index 000000000..3f8171898
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintrf64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x)
+{
+  return __builtin_nearbyint (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintr.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf32.c
new file mode 100644
index 000000000..ca00b0f51
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x)
+{
+  return __builtin_rintf (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintx.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf64.c
new file mode 100644
index 000000000..9b8604887
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintxf64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x)
+{
+  return __builtin_rint (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintx.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf32.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf32.c
new file mode 100644
index 000000000..c76bf6e99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x)
+{
+  return __builtin_truncf (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintz.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf64.c
new file mode 100644
index 000000000..602e876f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vrintzf64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x)
+{
+  return __builtin_trunc (x);
+}
+
+/* { dg-final { scan-assembler-times "vrintz.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqdf.c
new file mode 100644
index 000000000..86e147b1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqdf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  volatile int i = 0;
+  return i == 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vseleq.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqsf.c
new file mode 100644
index 000000000..120f44bf0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vseleqsf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  volatile int i = 0;
+  return i == 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgedf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgedf.c
new file mode 100644
index 000000000..cea08d12e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgedf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  volatile int i = 0;
+  return i >= 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgesf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgesf.c
new file mode 100644
index 000000000..86f2a0490
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgesf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  volatile int i = 0;
+  return i >= 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselge.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtdf.c
new file mode 100644
index 000000000..2c4a6ba90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtdf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  volatile int i = 0;
+  return i > 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselgt.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtsf.c
new file mode 100644
index 000000000..388e74c11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselgtsf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  volatile int i = 0;
+  return i > 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselledf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselledf.c
new file mode 100644
index 000000000..088dc04b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselledf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  volatile int i = 0;
+  return i <= 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselgt.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vsellesf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vsellesf.c
new file mode 100644
index 000000000..d0afdbcec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vsellesf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  volatile int i = 0;
+  return i <= 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselgt.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltdf.c
new file mode 100644
index 000000000..fbcb9ea2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltdf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  volatile int i = 0;
+  return i < 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselge.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltsf.c
new file mode 100644
index 000000000..959dab7fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselltsf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  volatile int i = 0;
+  return i < 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselge.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnedf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnedf.c
new file mode 100644
index 000000000..cf67f29f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnedf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  volatile int i = 0;
+  return i != 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vseleq.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnesf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnesf.c
new file mode 100644
index 000000000..2e16423b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselnesf.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  volatile int i = 0;
+  return i != 0 ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vseleq.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcdf.c
new file mode 100644
index 000000000..7f30270c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcdf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  return !__builtin_isunordered (x, y) ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcsf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcsf.c
new file mode 100644
index 000000000..1bb736925
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvcsf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  return !__builtin_isunordered (x, y) ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselvs.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvsdf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvsdf.c
new file mode 100644
index 000000000..83ad5bf69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvsdf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+double
+foo (double x, double y)
+{
+  return __builtin_isunordered (x, y) ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselvs.f64\td\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvssf.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvssf.c
new file mode 100644
index 000000000..7d762899c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/vselvssf.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_vfp_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_v8_vfp } */
+
+float
+foo (float x, float y)
+{
+  return __builtin_isunordered (x, y) ? x : y;
+}
+
+/* { dg-final { scan-assembler-times "vselvs.f32\ts\[0-9\]+" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-1.c
new file mode 100644
index 000000000..ddddd509f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O1 -fexpensive-optimizations" } */
+
+int mac(const short *a, const short *b, int sqr, int *sum)
+{
+  int i;
+  int dotp = *sum;
+
+  for (i = 0; i < 150; i++) {
+    dotp += b[i] * a[i];
+    sqr += b[i] * b[i];
+  }
+
+  *sum = dotp;
+  return sqr;
+}
+
+/* { dg-final { scan-assembler-times "smlabb" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-10.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-10.c
new file mode 100644
index 000000000..5ffd169ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-10.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+
+unsigned long long
+foo (unsigned short a, unsigned short *b, unsigned short *c)
+{
+  return (unsigned)a + (unsigned long long)*b * (unsigned long long)*c;
+}
+
+/* { dg-final { scan-assembler "umlal" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-11.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-11.c
new file mode 100644
index 000000000..904f0153a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-11.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+long long
+foo (int *b)
+{
+  return 10 * (long long)*b;
+}
+
+/* { dg-final { scan-assembler "smull" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-12.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-12.c
new file mode 100644
index 000000000..5c6b5b988
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-12.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+long long
+foo (int *b, int *c)
+{
+  long long tmp = (long long)*b * *c;
+  return 10 + tmp;
+}
+
+/* { dg-final { scan-assembler "smlal" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-13.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-13.c
new file mode 100644
index 000000000..a73d80f63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-13.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+long long
+foo (int *a, int *b)
+{
+  return *a + (long long)*b * 10;
+}
+
+/* { dg-final { scan-assembler "smlal" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-2.c
new file mode 100644
index 000000000..2ea55f9fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O1 -fexpensive-optimizations" } */
+
+void vec_mpy(int y[], const short x[], short scaler)
+{
+ int i;
+
+ for (i = 0; i < 150; i++)
+   y[i] += ((scaler * x[i]) >> 31);
+}
+
+/* { dg-final { scan-assembler-times "smulbb" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-3.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-3.c
new file mode 100644
index 000000000..144b55308
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O1 -fexpensive-optimizations" } */
+
+int mac(const short *a, const short *b, int sqr, int *sum)
+{
+  int i;
+  int dotp = *sum;
+
+  for (i = 0; i < 150; i++) {
+    dotp -= b[i] * a[i];
+    sqr -= b[i] * b[i];
+  }
+
+  *sum = dotp;
+  return sqr;
+}
+
+/* { dg-final { scan-assembler-times "smulbb" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-4.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-4.c
new file mode 100644
index 000000000..68f986674
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_dsp } */
+/* { dg-options "-O1 -fexpensive-optimizations" } */
+
+int mac(const int *a, const int *b, long long sqr, long long *sum)
+{
+  int i;
+  long long dotp = *sum;
+
+  for (i = 0; i < 150; i++) {
+    dotp += (long long) b[i] * a[i];
+    sqr += (long long) b[i] * b[i];
+  }
+
+  *sum = dotp;
+  return sqr;
+}
+
+/* { dg-final { scan-assembler-times "smlal" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-5.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-5.c
new file mode 100644
index 000000000..9f29a81c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-5.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+long long
+foo (long long a, char *b, char *c)
+{
+  return a + *b * *c;
+}
+
+/* { dg-final { scan-assembler "umlal" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-6.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-6.c
new file mode 100644
index 000000000..babdaab1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-6.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+long long
+foo (long long a, unsigned char *b, signed char *c)
+{
+  return a + (long long)*b * (long long)*c;
+}
+
+/* { dg-final { scan-assembler "smlalbb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-7.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-7.c
new file mode 100644
index 000000000..2db4ad4e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-7.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+unsigned long long
+foo (unsigned long long a, unsigned char *b, unsigned short *c)
+{
+  return a + *b * *c;
+}
+
+/* { dg-final { scan-assembler "umlal" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-8.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-8.c
new file mode 100644
index 000000000..5ae110d3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-8.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+long long
+foo (long long a, int *b, int *c)
+{
+  return a + (long long)*b * *c;
+}
+
+/* { dg-final { scan-assembler "smlal" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-9.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-9.c
new file mode 100644
index 000000000..40ed0219a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-9.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+long long
+foo (long long a, short *b, char *c)
+{
+  return a + *b * *c;
+}
+
+/* { dg-final { scan-assembler "smlalbb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c
new file mode 100644
index 000000000..2e9da5923
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+struct bf
+{
+  int a : 3;
+  int b : 15;
+  int c : 3;
+};
+
+long long
+foo (long long a, struct bf b, struct bf c)
+{
+  return a + b.b * c.b;
+}
+
+/* { dg-final { scan-assembler "smlalbb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c
new file mode 100644
index 000000000..07ba9a84d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/wmul-bitfield-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_dsp } */
+
+struct bf
+{
+  int a : 3;
+  unsigned int b : 15;
+  int c : 3;
+};
+
+long long
+foo (long long a, struct bf b, struct bf c)
+{
+  return a + b.b * c.c;
+}
+
+/* { dg-final { scan-assembler "smlalbb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/xor-and.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/xor-and.c
new file mode 100644
index 000000000..53dff85f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/xor-and.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=armv6" } */
+/* { dg-prune-output "switch .* conflicts with" } */
+
+unsigned short foo (unsigned short x)
+{
+  x ^= 0x4002;
+  x >>= 1;
+  x |= 0x8000;
+  return x;
+}
+
+/* { dg-final { scan-assembler "orr" } } */
+/* { dg-final { scan-assembler-not "mvn" } } */
+/* { dg-final { scan-assembler-not "uxth" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/xordi3-opt.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/xordi3-opt.c
new file mode 100644
index 000000000..7e031c3af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/xordi3-opt.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+unsigned long long xor64 (unsigned long long input)
+{
+    return input ^ 0x200000004ULL;
+}
+
+/* { dg-final { scan-assembler-not "mov\[\\t \]+.+,\[\\t \]*.+" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/avr.exp b/gcc-4.9/gcc/testsuite/gcc.target/avr/avr.exp
new file mode 100644
index 000000000..86a541a09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/avr.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2008-2014 Free Software Foundation, Inc.
+

+# This program is free software; you can redistribute it and/or modify

+# it under the terms of the GNU General Public License as published by

+# the Free Software Foundation; either version 3 of the License, or

+# (at your option) any later version.

+# 

+# This program is distributed in the hope that it will be useful,

+# but WITHOUT ANY WARRANTY; without even the implied warranty of

+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+# GNU General Public License for more details.

+# 

+# You should have received a copy of the GNU General Public License

+# along with GCC; see the file COPYING3.  If not see

+# <http://www.gnu.org/licenses/>.

+

+# GCC testsuite that uses the `dg.exp' driver.

+

+# Exit immediately if this isn't an AVR target.

+if ![istarget avr-*-*] then {

+  return

+}

+

+# Load support procs.

+load_lib gcc-dg.exp

+

+# If a testcase doesn't have special options, use these.

+global DEFAULT_CFLAGS

+if ![info exists DEFAULT_CFLAGS] then {

+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"

+}

+

+# Initialize `dg'.

+dg-init

+

+# Main loop.

+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{\[cCS\],cpp}]] \

+	"" $DEFAULT_CFLAGS

+

+# All done.

+dg-finish

diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/exit-abort.h b/gcc-4.9/gcc/testsuite/gcc.target/avr/exit-abort.h
new file mode 100644
index 000000000..cf7df203a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/exit-abort.h
@@ -0,0 +1,8 @@
+#ifdef __cplusplus
+extern "C" {
+#endif
+  extern void exit (int);
+  extern void abort (void);
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/pr46779-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/pr46779-1.c
new file mode 100644
index 000000000..24522f175
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/pr46779-1.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-options "-Os -fsplit-wide-types" } */
+
+/* This testcase should uncover bugs like
+   PR46779
+   PR45291
+   PR41894
+
+   The inline asm just serves to direct y into the Y register.
+   Otherwise, it is hard to write a "stable" test case that
+   also fails with slight variations in source code, middle- resp.
+   backend.
+
+   The problem is that Y is also the frame-pointer, and
+   avr.c:avr_hard_regno_mode_ok disallows QI to get in Y-reg.
+   However, the y.a = 0 generates a
+       (set (subreg:QI (reg:HI pseudo)) ...)
+   where pseudo gets allocated to Y.
+
+   Reload fails to generate the right spill.
+*/
+
+#include <stdlib.h>
+
+struct S
+{
+    unsigned char a, b;
+} ab = {12, 34};
+
+void yoo (struct S y)
+{
+    __asm volatile ("ldi %B0, 56" : "+y" (y));
+    y.a = 0;
+    __asm volatile ("; y = %0" : "+y" (y));
+    ab = y;
+}
+
+int main ()
+{
+    yoo (ab);
+
+    if (ab.a != 0)
+        abort();
+
+    if (ab.b != 56)
+        abort();
+
+    exit (0);
+    
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/pr46779-2.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/pr46779-2.c
new file mode 100644
index 000000000..682070b5e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/pr46779-2.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-options "-Os -fno-split-wide-types" } */
+
+/* This testcase should uncover bugs like
+   PR46779
+   PR45291
+   PR41894
+
+   The inline asm just serves to direct y into the Y register.
+   Otherwise, it is hard to write a "stable" test case that
+   also fails with slight variations in source code, middle- resp.
+   backend.
+
+   The problem is that Y is also the frame-pointer, and
+   avr.c:avr_hard_regno_mode_ok disallows QI to get in Y-reg.
+   However, the y.a = 0 generates a
+       (set (subreg:QI (reg:HI pseudo)) ...)
+   where pseudo gets allocated to Y.
+
+   Reload fails to generate the right spill.
+*/
+
+#include <stdlib.h>
+
+struct S
+{
+    unsigned char a, b;
+} ab = {12, 34};
+
+void yoo (struct S y)
+{
+    __asm volatile ("ldi %B0, 56" : "+y" (y));
+    y.a = 0;
+    __asm volatile ("; y = %0" : "+y" (y));
+    ab = y;
+}
+
+int main ()
+{
+    yoo (ab);
+
+    if (ab.a != 0)
+        abort();
+
+    if (ab.b != 56)
+        abort();
+
+    exit (0);
+    
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/pr58545.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/pr58545.c
new file mode 100644
index 000000000..d1b8461f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/pr58545.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -mmcu=atmega8" } */
+
+typedef unsigned char uint8_t;
+typedef unsigned int uint16_t;
+
+extern uint8_t f1 (const uint8_t*);
+extern void f2 (uint8_t*, uint8_t);
+
+void func (uint16_t parameter, uint8_t *addr, uint8_t data)
+{
+   uint8_t status;
+
+   status = f1 (addr + 8);
+
+   addr++;
+
+   if (*addr == parameter + 8)
+      *addr = parameter;
+
+   f2 (addr, data);
+   f2 (addr + 8, status + 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-error-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-error-1.c
new file mode 100644
index 000000000..cf53cc8e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-error-1.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+
+#include "progmem.h"
+
+char str[] PROGMEM = "Hallo"; /* { dg-error "must be const" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp b/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp
new file mode 100644
index 000000000..934b93c15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+
+#include "progmem.h"
+
+char str[] PROGMEM = "Hallo"; /* { dg-error "must be const" "" { target avr-*-* } 1 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-warning-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-warning-1.c
new file mode 100644
index 000000000..67af05fe5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem-warning-1.c
@@ -0,0 +1,7 @@
+/* PR target/34734 */
+/* { dg-do compile } */
+/* { dg-options "-Wuninitialized" } */
+
+#include "progmem.h"
+
+const char c PROGMEM; /* { dg-warning "uninitialized variable 'c' put into program memory area" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem.h b/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem.h
new file mode 100644
index 000000000..17bb77153
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/progmem.h
@@ -0,0 +1,25 @@
+#define PROGMEM __attribute__((progmem))
+
+#define PSTR(s)                                             \
+    (__extension__({                                        \
+            static const char __c[] PROGMEM = (s);          \
+            &__c[0];}))
+
+#ifdef __AVR_HAVE_LPMX__
+#define pgm_read_char(addr)                                 \
+    (__extension__({                                        \
+            unsigned int __addr16 = (unsigned int)(addr);   \
+            char __result;                                  \
+            __asm__ ("lpm %0, %a1"                          \
+                     : "=r" (__result) : "z" (__addr16));   \
+            __result; }))
+#else
+#define pgm_read_char(addr)                                 \
+    (__extension__({                                        \
+            unsigned int __addr16 = (unsigned int)(addr);   \
+            char __result;                                  \
+            __asm__ ("lpm" "\n\t"                           \
+                     "mov %0, r0"                           \
+                     : "=r" (__result) : "z" (__addr16));   \
+            __result; }))
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-0.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-0.c
new file mode 100644
index 000000000..880654201
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-0.c
@@ -0,0 +1,6 @@
+/* { dg-options "-std=gnu99" } */
+/* { dg-do run } */
+
+#define __as __flash
+
+#include "addr-space-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-1.c
new file mode 100644
index 000000000..137526527
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-1.c
@@ -0,0 +1,6 @@
+/* { dg-options "-std=gnu99 -Tavr51-flash1.x" } */
+/* { dg-do run } */
+
+#define __as __flash1
+
+#include "addr-space-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-g.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-g.c
new file mode 100644
index 000000000..60feca145
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-g.c
@@ -0,0 +1,6 @@
+/* { dg-options "-std=gnu99" } */
+/* { dg-do run } */
+
+#define __as
+
+#include "addr-space-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-x.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-x.c
new file mode 100644
index 000000000..0b3c43a4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1-x.c
@@ -0,0 +1,6 @@
+/* { dg-options "-std=gnu99" } */
+/* { dg-do run } */
+
+#define __as __memx
+
+#include "addr-space-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1.h b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1.h
new file mode 100644
index 000000000..322a5b8b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-1.h
@@ -0,0 +1,83 @@
+#include <stdlib.h>
+#include <string.h>
+
+typedef struct
+{
+  char i1;
+  short i2;
+  long i4;
+  long long i8;
+  char str[2][10];
+} a_t;
+
+const __as a_t A =
+  {
+    12, 345, 678910, 1234567891011ll,
+    {
+      "xxx..xxx",
+      "yyy..yyy"
+    }
+  };
+
+const __as volatile a_t V =
+  {
+    12+1, 345+1, 678910+1, 1234567891011ll+1,
+    {
+      "XXX..XXX",
+      "YYY..YYY"
+    }
+  };
+
+a_t A2;
+volatile a_t V2;
+
+int main (void)
+{
+  if (A.i1 != 12
+      || A.i1 != V.i1 -1)
+    abort();
+
+  if (A.i2 != 345
+      || A.i2 != V.i2 -1)
+    abort();
+
+  if (A.i4 != 678910
+      || A.i4 != V.i4 -1)
+    abort();
+
+  if (A.i8 != 1234567891011ll
+      || A.i8 != V.i8 -1)
+    abort();
+
+  A2 = A;
+  V2 = V;
+
+  if (A2.i1 != 12
+      || A2.i1 != V2.i1 -1)
+    abort();
+
+  if (A2.i2 != 345
+      || A2.i2 != V2.i2 -1)
+    abort();
+
+  if (A2.i4 != 678910
+      || A2.i4 != V2.i4 -1)
+    abort();
+
+  if (A2.i8 != 1234567891011ll
+      || A2.i8 != V2.i8 -1)
+    abort();
+
+  if (strcmp (A2.str[0], "xxx..xxx"))
+    abort();
+  if (strcmp (A2.str[1], "yyy..yyy"))
+    abort();
+
+  if (strcmp ((const char*) V2.str[0], "XXX..XXX"))
+    abort();
+  if (strcmp ((const char*) V2.str[1], "YYY..YYY"))
+   abort();
+  
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-0.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-0.c
new file mode 100644
index 000000000..d5d4f92a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-0.c
@@ -0,0 +1,6 @@
+/* { dg-options "-std=gnu99" } */
+/* { dg-do run } */
+
+#define __as __flash
+
+#include "addr-space-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-1.c
new file mode 100644
index 000000000..c8041f7d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-1.c
@@ -0,0 +1,6 @@
+/* { dg-options "-std=gnu99 -Tavr51-flash1.x" } */
+/* { dg-do run } */
+
+#define __as __flash1
+
+#include "addr-space-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-g.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-g.c
new file mode 100644
index 000000000..ad0b2b841
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-g.c
@@ -0,0 +1,6 @@
+/* { dg-options "-std=gnu99" } */
+/* { dg-do run } */
+
+#define __as
+
+#include "addr-space-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-x.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-x.c
new file mode 100644
index 000000000..846cca47d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2-x.c
@@ -0,0 +1,9 @@
+/* { dg-options "-std=gnu99 -Wa,--no-warn" } */
+/* { dg-do run } */
+
+/* --no-warn because: "assembling 24-bit address needs binutils extension"
+   see binutils PR13503.  */
+
+#define __as __memx
+
+#include "addr-space-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2.h b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2.h
new file mode 100644
index 000000000..c95a1631a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/addr-space-2.h
@@ -0,0 +1,106 @@
+extern void exit (int);
+extern void abort (void);
+
+typedef struct T
+{
+  char val;
+  const __as struct T *l, *r;
+} tree;
+
+/*
+                    abcd   
+                   /    \
+                 ab      cd
+                /  \    /  \
+               a    b  c    d
+*/
+
+const __as tree a = { 'a', 0, 0 };
+const __as tree b = { 'b', 0, 0 };
+const __as tree c = { 'c', 0, 0 };
+const __as tree d = { 'd', 0, 0 };
+
+const __as tree ab = { 'A', &a, &b };
+const __as tree cd = { 'C', &c, &d };
+
+const __as tree abcd = { '*', &ab, &cd };
+
+static void
+test1 (void)
+{
+  if (abcd.val != '*')
+    abort();
+
+  if (abcd.l->val != 'A')
+    abort();
+  if (abcd.r->val != 'C')
+    abort();
+
+  if (abcd.l->l->val != 'a')
+    abort();
+  if (abcd.l->r->val != 'b')
+    abort();
+  if (abcd.r->l->val != 'c')
+    abort();
+  if (abcd.r->r->val != 'd')
+    abort();
+}
+
+static void
+test2 (const __as tree *t)
+{
+  if (t->val != '*')
+    abort();
+
+  if (t->l->val != 'A')
+    abort();
+  if (t->r->val != 'C')
+    abort();
+
+  if (t->l->l->val != 'a')
+    abort();
+  if (t->l->r->val != 'b')
+    abort();
+  if (t->r->l->val != 'c')
+    abort();
+  if (t->r->r->val != 'd')
+    abort();
+}
+
+static void
+test3 (const __as tree *pt)
+{
+  tree t = *pt;
+  
+  if (t.val != '*')
+    abort();
+
+  if (t.l->val != 'A')
+    abort();
+  if (t.r->val != 'C')
+    abort();
+
+  if (t.l->l->val != 'a')
+    abort();
+  if (t.l->r->val != 'b')
+    abort();
+  if (t.r->l->val != 'c')
+    abort();
+  if (t.r->r->val != 'd')
+    abort();
+}
+
+int main (void)
+{
+  const __as tree *t = &abcd;
+  test1();
+  test2 (&abcd);
+  test3 (&abcd);
+
+  __asm ("" : "+r" (t));
+  test2 (t);
+  test3 (t);
+  
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp
new file mode 100644
index 000000000..3e5fdfbd4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/avr-torture.exp
@@ -0,0 +1,64 @@
+#   Copyright (C) 2008-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `gcc-dg.exp' driver, looping over
+# optimization options.
+
+# Exit immediately if this isn't a AVR target.
+if { ![istarget avr-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+    set AVR_TORTURE_OPTIONS [list \
+	{ -O0 } \
+	{ -O1 } \
+	{ -O2 } \
+	{ -Os -flto } \
+	{ -O2 -mcall-prologues } \
+	{ -O2 -fdata-sections } \
+	{ -O2 -fmerge-all-constants } \
+	{ -Os -fomit-frame-pointer } \
+	{ -Os -fomit-frame-pointer -finline-functions } \
+	{ -O3 -g } \
+	{ -Os -mcall-prologues} ]
+
+
+#Initialize use of torture lists. 
+torture-init
+
+set-torture-options $AVR_TORTURE_OPTIONS
+
+
+# Main loop.
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.{\[cS\],cpp}]] $DEFAULT_CFLAGS
+
+# Finalize use of torture lists.
+torture-finish
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-1.c
new file mode 100644
index 000000000..fe20c9163
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-1.c
@@ -0,0 +1,97 @@
+/* { dg-do run } */
+
+#include <stdlib.h>
+
+#define MASK_F(M)                                       \
+  (0                                                    \
+   | ((0xf == (0xf & ((M) >> (4*0)))) ? (1 << 0) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*1)))) ? (1 << 1) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*2)))) ? (1 << 2) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*3)))) ? (1 << 3) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*4)))) ? (1 << 4) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*5)))) ? (1 << 5) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*6)))) ? (1 << 6) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*7)))) ? (1 << 7) : 0)   \
+   | 0)
+
+#define MASK_0_7(M)                                     \
+  (0                                                    \
+   | ((8 > (0xf & ((M) >> (4*0)))) ? (1 << 0) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*1)))) ? (1 << 1) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*2)))) ? (1 << 2) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*3)))) ? (1 << 3) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*4)))) ? (1 << 4) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*5)))) ? (1 << 5) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*6)))) ? (1 << 6) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*7)))) ? (1 << 7) : 0)      \
+   | 0)
+
+#define INSERT_BITS(M,B,V)                                              \
+  (__extension__({                                                      \
+      unsigned char _n, _r = 0;                                         \
+      _n = 0xf & (M >> (4*0)); if (_n<8) _r |= (!!(B & (1 << _n))) << 0; \
+      _n = 0xf & (M >> (4*1)); if (_n<8) _r |= (!!(B & (1 << _n))) << 1; \
+      _n = 0xf & (M >> (4*2)); if (_n<8) _r |= (!!(B & (1 << _n))) << 2; \
+      _n = 0xf & (M >> (4*3)); if (_n<8) _r |= (!!(B & (1 << _n))) << 3; \
+      _n = 0xf & (M >> (4*4)); if (_n<8) _r |= (!!(B & (1 << _n))) << 4; \
+      _n = 0xf & (M >> (4*5)); if (_n<8) _r |= (!!(B & (1 << _n))) << 5; \
+      _n = 0xf & (M >> (4*6)); if (_n<8) _r |= (!!(B & (1 << _n))) << 6; \
+      _n = 0xf & (M >> (4*7)); if (_n<8) _r |= (!!(B & (1 << _n))) << 7; \
+      (unsigned char) ((V) & MASK_F(M)) | _r;                           \
+    }))
+
+#define MASK_USED(M) (MASK_F(M) | MASK_0_7(M))
+
+#define TEST2(M,B,V)                                    \
+  do {                                                  \
+    __asm volatile (";" #M);                            \
+    r1 = MASK_USED (M)                                  \
+      & __builtin_avr_insert_bits (M,B,V);              \
+    r2 = INSERT_BITS (M,B,V);                           \
+    if (r1 != r2)                                       \
+      abort ();                                         \
+  } while(0)
+
+#define TEST1(M,X)                                      \
+  do {                                                  \
+    TEST2 (M,X,0x00); TEST2 (M,0x00,X);                 \
+    TEST2 (M,X,0xff); TEST2 (M,0xff,X);                 \
+    TEST2 (M,X,0xaa); TEST2 (M,0xaa,X);                 \
+    TEST2 (M,X,0xcc); TEST2 (M,0xcc,X);                 \
+    TEST2 (M,X,0x96); TEST2 (M,0x96,X);                 \
+  } while(0)
+
+
+
+void test8 (void)
+{
+  unsigned char r1, r2;
+  unsigned char ib;
+
+  static const unsigned char V[] =
+    {
+      0, 0xaa, 0xcc, 0xf0, 0xff, 0x5b, 0x4d
+    };
+
+  for (ib = 0; ib < sizeof (V) / sizeof (*V); ib++)
+    {
+      unsigned char b = V[ib];
+      
+      TEST1 (0x76543210, b);
+      TEST1 (0x3210ffff, b);
+      TEST1 (0x67452301, b);
+      TEST1 (0xf0f1f2f3, b);
+      TEST1 (0xff10ff54, b);
+      TEST1 (0x01234567, b);
+      TEST1 (0xff765f32, b);
+    }
+}
+
+/****************************************************************/
+
+int main()
+{
+  test8();
+  
+  exit(0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-2.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-2.c
new file mode 100644
index 000000000..06cafd6af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtin_insert_bits-2.c
@@ -0,0 +1,94 @@
+/* { dg-do run } */
+
+#include <stdlib.h>
+
+#define MASK_F(M)                                       \
+  (0                                                    \
+   | ((0xf == (0xf & ((M) >> (4*0)))) ? (1 << 0) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*1)))) ? (1 << 1) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*2)))) ? (1 << 2) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*3)))) ? (1 << 3) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*4)))) ? (1 << 4) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*5)))) ? (1 << 5) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*6)))) ? (1 << 6) : 0)   \
+   | ((0xf == (0xf & ((M) >> (4*7)))) ? (1 << 7) : 0)   \
+   | 0)
+
+#define MASK_0_7(M)                                     \
+  (0                                                    \
+   | ((8 > (0xf & ((M) >> (4*0)))) ? (1 << 0) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*1)))) ? (1 << 1) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*2)))) ? (1 << 2) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*3)))) ? (1 << 3) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*4)))) ? (1 << 4) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*5)))) ? (1 << 5) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*6)))) ? (1 << 6) : 0)      \
+   | ((8 > (0xf & ((M) >> (4*7)))) ? (1 << 7) : 0)      \
+   | 0)
+
+#define INSERT_BITS(M,B,V)                                              \
+  (__extension__({                                                      \
+      unsigned char _n, _r = 0;                                         \
+      _n = 0xf & (M >> (4*0)); if (_n<8) _r |= (!!(B & (1 << _n))) << 0; \
+      _n = 0xf & (M >> (4*1)); if (_n<8) _r |= (!!(B & (1 << _n))) << 1; \
+      _n = 0xf & (M >> (4*2)); if (_n<8) _r |= (!!(B & (1 << _n))) << 2; \
+      _n = 0xf & (M >> (4*3)); if (_n<8) _r |= (!!(B & (1 << _n))) << 3; \
+      _n = 0xf & (M >> (4*4)); if (_n<8) _r |= (!!(B & (1 << _n))) << 4; \
+      _n = 0xf & (M >> (4*5)); if (_n<8) _r |= (!!(B & (1 << _n))) << 5; \
+      _n = 0xf & (M >> (4*6)); if (_n<8) _r |= (!!(B & (1 << _n))) << 6; \
+      _n = 0xf & (M >> (4*7)); if (_n<8) _r |= (!!(B & (1 << _n))) << 7; \
+      (unsigned char) ((V) & MASK_F(M)) | _r;                           \
+    }))
+
+#define MASK_USED(M) (MASK_F(M) | MASK_0_7(M))
+
+#define TEST2(M,B,V)                                    \
+  do {                                                  \
+    __asm volatile (";" #M);                            \
+    r1 = MASK_USED (M)                                  \
+      & __builtin_avr_insert_bits (M,B,V);              \
+    r2 = INSERT_BITS (M,B,V);                           \
+    if (r1 != r2)                                       \
+      abort ();                                         \
+  } while(0)
+
+void test8 (void)
+{
+  unsigned char r1, r2;
+  unsigned char ib, iv;
+
+  static const unsigned char V[] =
+    {
+      0, 0xaa, 0xcc, 0xf0, 0xff, 0x5b, 0x4d
+    };
+
+  for (ib = 0; ib < sizeof (V) / sizeof (*V); ib++)
+    {
+      unsigned char b = V[ib];
+      
+      for (iv = 0; iv < sizeof (V) / sizeof (*V); iv++)
+        {
+          unsigned char v = V[iv];
+          
+          TEST2 (0x76543210, b, v);
+          TEST2 (0xffffffff, b, v);
+          TEST2 (0x3210ffff, b, v);
+          TEST2 (0x67452301, b, v);
+          TEST2 (0xf0f1f2f3, b, v);
+          TEST2 (0xff10ff54, b, v);
+          TEST2 (0x0765f321, b, v);
+          TEST2 (0x11223344, b, v);
+          TEST2 (0x01234567, b, v);
+          TEST2 (0xff7765f3, b, v);
+        }
+    }
+}
+
+/****************************************************************/
+
+int main()
+{
+  test8();
+  
+  exit(0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-1.c
new file mode 100644
index 000000000..1fa3aaaae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-1.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+
+void nop (void)    { __builtin_avr_nop (); }
+void sei (void)    { __builtin_avr_sei (); }
+void cli (void)    { __builtin_avr_cli (); }
+void wdr (void)    { __builtin_avr_wdr (); }
+void sleep (void)  { __builtin_avr_sleep (); }
+
+char fmul (char a, char b)   { return __builtin_avr_fmul (a, b); }
+char fmuls (char a, char b)  { return __builtin_avr_fmuls (a, b); }
+char fmulsu (char a, char b) { return __builtin_avr_fmulsu (a, b); }
+
+char swap1 (char a)
+{
+    return __builtin_avr_swap (a+1);
+}
+
+char swap2 (char a)
+{
+    return __builtin_avr_swap (__builtin_avr_swap (a+1));
+}
+
+char swap15 (void)
+{
+    return __builtin_avr_swap (15);
+}
+
+void delay0 (void)  { __builtin_avr_delay_cycles (0); }
+void delay1 (void)  { __builtin_avr_delay_cycles (1); }
+void delay2 (void)  { __builtin_avr_delay_cycles (2); }
+void delay3 (void)  { __builtin_avr_delay_cycles (3); }
+
+void delay_1 (void)  { __builtin_avr_delay_cycles (44); }
+void delay_2 (void)  { __builtin_avr_delay_cycles (0x1234); }
+void delay_3 (void)  { __builtin_avr_delay_cycles (0x123456); }
+void delay_4 (void)  { __builtin_avr_delay_cycles (-1ul); }
+
+/* { dg-final { scan-assembler-not "__builtin_avr_" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-2.c
new file mode 100644
index 000000000..ae207d9a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-2.c
@@ -0,0 +1,46 @@
+/* { dg-options "-std=gnu99 -Tavr51-flash1.x" } */
+/* { dg-do run } */
+
+#include <stdlib.h>
+#include "../progmem.h"
+
+int volatile a;
+
+void f1 (void) 
+{
+  __builtin_avr_sei (); 
+  __builtin_avr_cli (); 
+  __builtin_avr_wdr (); 
+  __builtin_avr_sleep (); 
+  __builtin_avr_nop ();
+  a = __builtin_avr_swap (a);
+  a = __builtin_avr_fmul (1,a);
+  a = __builtin_avr_fmuls (1,a);
+  a = __builtin_avr_fmulsu (1,a);
+  a = __builtin_avr_insert_bits (0x1f2f5364, a, a);
+}
+
+const __flash char c0 = 1;
+const __flash1 char c1 = 1;
+
+int main (void) 
+{
+  const __memx void *p;
+
+  f1();
+  __builtin_avr_delay_cycles (1000);
+
+  p = &c0;
+  if (__builtin_avr_flash_segment (p) != 0)
+    abort();
+
+  p = &c1;
+  if (__builtin_avr_flash_segment (p) != 1)
+    abort();
+
+  if (__builtin_avr_flash_segment ("p") != -1)
+    abort();
+
+  exit (0);
+  return 0; 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-3-absfx.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-3-absfx.c
new file mode 100644
index 000000000..a8bde2952
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-3-absfx.c
@@ -0,0 +1,171 @@
+/* { dg-options "-std=gnu99" } */
+/* { dg-do run } */
+
+#include <stdfix.h>
+
+extern void abort (void);
+
+short fract test1_hr (short fract x)
+{
+  return abshr (x);
+}
+
+fract test1_r (fract x)
+{
+  return absr (x);
+}
+
+long fract test1_lr (long fract x)
+{
+  return abslr (x);
+}
+
+long long fract test1_llr (long long fract x)
+{
+  return absllr (x);
+}
+
+short accum test1_hk (short accum x)
+{
+  return abshk (x);
+}
+
+accum test1_k (accum x)
+{
+  return absk (x);
+}
+
+long accum test1_lk (long accum x)
+{
+  return abslk (x);
+}
+
+long long accum test1_llk (long long accum x)
+{
+  return absllk (x);
+}
+
+
+short fract test2_hr (void)
+{
+  return abshr (-0.12hr);
+}
+
+fract test2_r (void)
+{
+  return absr (-0.12r);
+}
+
+long fract test2_lr (void)
+{
+  return abslr (-0.12lr);
+}
+
+long long fract test2_llr (void)
+{
+  return absllr (-0.123456llr);
+}
+
+short accum test2_hk (void)
+{
+  return abshk (-221.12hk);
+}
+
+accum test2_k (void)
+{
+  return absk (-4321.12k);
+}
+
+long accum test2_lk (void)
+{
+  return abslk (-4321.12lk);
+}
+
+long long accum test2_llk (void)
+{
+  return absllk (-4321.12llk);
+}
+
+#define TEST1(VAL,FX)                                          \
+  if (abs ## FX (-VAL ## FX -v) != VAL ## FX + v)              \
+    abort();                                                   \
+  if (abs ## FX (-VAL ## FX -v) != abs ## FX (VAL ## FX + v))  \
+    abort();
+
+#define TEST2(VAL,FX)                                   \
+  if (abs ## FX (-VAL ## FX) != VAL ## FX)              \
+    abort();                                            \
+  if (abs ## FX (-VAL ## FX) != abs ## FX (VAL ## FX))  \
+    abort();
+
+const __flash short fract volatile v = 0.33hr;
+const __flash short fract volatile z = 0hr;
+
+void test1 (void)
+{
+  TEST1 (0.123, hr);
+  TEST1 (0.123, r);
+  TEST1 (0.1234567, lr);
+  TEST1 (0.1234567, llr);
+  
+  TEST1 (223.123, hk);
+  TEST1 (12345.123, k);
+  TEST1 (12342345.123, lk);
+  TEST1 (12345.123, llk);
+}
+
+
+void test2 (void)
+{
+  TEST2 (0.123, hr);
+  TEST2 (0.123, r);
+  TEST2 (0.1234567, lr);
+  TEST2 (0.1234567, llr);
+  
+  TEST2 (223.123, hk);
+  TEST2 (12345.123, k);
+  TEST2 (12342345.123, lk);
+  TEST2 (12345.123, llk);
+}
+
+#define MINMAX(T,FX)                                                    \
+  {                                                                     \
+    int_ ## FX ## _t imin                                               \
+      = (int_ ## FX ## _t) 1 << (8 * sizeof (int_ ## FX ## _t) -1);     \
+    int_ ## FX ## _t imax = ~imin;                                      \
+    T fmin =  FX ## bits (imin);                                        \
+    T fmax =  FX ## bits (imax);                                        \
+                                                                        \
+    if (abs ## FX (fmin) != fmax)                                       \
+      abort();                                                          \
+    if (abs ## FX (fmin) != abs ## FX (fmax))                           \
+      abort();                                                          \
+    if (abs ## FX (fmin + z) != fmax + z)                               \
+      abort();                                                          \
+    if (abs ## FX (fmin - z) != abs ## FX (fmax + z))                   \
+      abort();                                                          \
+  }
+
+void test3 (void)
+{
+  MINMAX (short fract, hr);
+  MINMAX (fract, r);
+  MINMAX (long fract, lr);
+  MINMAX (long long fract, llr);
+
+  MINMAX (short accum, hk);
+  MINMAX (accum, k);
+  MINMAX (long accum, lk);
+  MINMAX (long long accum, llk);
+}
+
+
+int main (void)
+{
+  test1();
+  test2();
+  test3();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-4-roundfx.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-4-roundfx.c
new file mode 100644
index 000000000..46e915a6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-4-roundfx.c
@@ -0,0 +1,164 @@
+/* { dg-options "-std=gnu99" } */
+/* { dg-do run } */
+
+#include <stdfix.h>
+
+extern void abort (void);
+
+typedef short _Fract fx_hr_t;
+typedef _Fract fx_r_t;
+typedef long _Fract fx_lr_t;
+typedef long long _Fract fx_llr_t;
+
+typedef unsigned short _Fract fx_uhr_t;
+typedef unsigned _Fract fx_ur_t;
+typedef unsigned long _Fract fx_ulr_t;
+typedef unsigned long long _Fract fx_ullr_t;
+
+typedef short _Accum fx_hk_t;
+typedef _Accum fx_k_t;
+typedef long _Accum fx_lk_t;
+typedef long long _Accum fx_llk_t;
+
+typedef unsigned short _Accum fx_uhk_t;
+typedef unsigned _Accum fx_uk_t;
+typedef unsigned long _Accum fx_ulk_t;
+typedef unsigned long long _Accum fx_ullk_t;
+
+
+typedef unsigned char int_uhr_t;
+typedef unsigned int int_ur_t;
+typedef unsigned long int_ulr_t;
+typedef unsigned long long int_ullr_t;
+
+typedef unsigned int int_uhk_t;
+typedef unsigned long int_uk_t;
+typedef unsigned long long int_ulk_t;
+typedef unsigned long long int_ullk_t;
+
+
+#define DEFTEST1(T,FX)                              \
+  T test1_##FX (T x, int rp)                        \
+  {                                                 \
+    return round##FX (x, rp);                       \
+  }                                                 \
+                                                    \
+  unsigned T test1_u##FX (unsigned T x, int rp)     \
+  {                                                 \
+    return roundu##FX (x, rp);                      \
+  }
+
+DEFTEST1 (short fract, hr)
+DEFTEST1 (fract, r)
+DEFTEST1 (long fract, lr)
+DEFTEST1 (long long fract, llr)
+
+DEFTEST1 (short accum, hk)
+DEFTEST1 (accum, k)
+
+DEFTEST1 (long accum, lk)
+DEFTEST1 (long long accum, llk)
+
+
+#define TEST2(FX, RP, VAL, ROUND)                                    \
+  {                                                                  \
+    if (round##FX (FX##bits (VAL), RP) != FX##bits (ROUND))          \
+      abort();                                                       \
+    fx_##FX##_t (*f)(fx_##FX##_t,int) = round##FX;                   \
+    asm ("" : "+r" (f));                                             \
+    if (f (FX##bits (VAL), RP) != FX##bits (ROUND))                  \
+      abort();                                                       \
+  }
+
+static void test2hr (void)
+{
+  TEST2 (hr, 1, 0x7f, 0x7f);
+  TEST2 (hr, 2, 0x70, 0x7f);
+  TEST2 (hr, 3, 0x78, 0x7f);
+  TEST2 (hr, 4, 0x7f, 0x7f);
+ 
+  TEST2 (uhr, 1, 0x7f, 0x80);
+  TEST2 (uhr, 2, 0x7f, 0x80);
+  TEST2 (uhr, 3, 0x7f, 0x80);
+  TEST2 (uhr, 4, 0x7f, 0x80);
+}
+
+void test2k (void)
+{
+  TEST2 (k, 1, 0x7fffff00, 0x7fffffff);
+  TEST2 (k, 2, 0x7ffffff0, 0x7fffffff);
+  TEST2 (k, 2, 0x7ffff000, 0x7fffffff);
+  TEST2 (k, 3, 0x7ffff000, 0x7ffff000);
+  TEST2 (k, 3, 0x7ffff800, 0x7fffffff);
+  TEST2 (k, 3, 0x7ffff7ff, 0x7ffff000);
+  TEST2 (k, 4, 0x7ffff7ff, 0x7ffff800);
+
+  TEST2 (uk, 1, 0x7fffffff, 1ul << 31);
+  TEST2 (uk, 2, 0x7fffffff, 1ul << 31);
+  TEST2 (uk, 3, 0x7fffffff, 1ul << 31);
+  TEST2 (uk, 4, 0x7fffffff, 1ul << 31);
+}
+
+#define DEFTEST3(FX, FBIT)                            \
+  void test3##FX (void)                               \
+  {                                                   \
+    TEST2 (FX, FBIT-1, 0b01100, 0b01100);             \
+    TEST2 (FX, FBIT-2, 0b01100, 0b01100);             \
+    TEST2 (FX, FBIT-3, 0b01100, 0b10000);             \
+    TEST2 (FX, FBIT-4, 0b01100, 0b10000);             \
+    TEST2 (FX, FBIT-5, 0b01100, 0);                   \
+                                                      \
+    if (FX##bits ((int_##FX##_t) -1) > 0)             \
+      return;                                         \
+                                                      \
+    TEST2 (FX, FBIT-1, -0b01100, -0b01100);           \
+    TEST2 (FX, FBIT-2, -0b01100, -0b01100);           \
+    TEST2 (FX, FBIT-3, -0b01100, -0b01000);           \
+    TEST2 (FX, FBIT-4, -0b01100, -0b10000);           \
+    TEST2 (FX, FBIT-5, -0b01100, -0b00000);           \
+    }
+
+DEFTEST3 (hr, SFRACT_FBIT)
+DEFTEST3 (r, FRACT_FBIT)
+DEFTEST3 (lr, LFRACT_FBIT)
+
+DEFTEST3 (uhr, USFRACT_FBIT)
+DEFTEST3 (ur, UFRACT_FBIT)
+DEFTEST3 (ulr, ULFRACT_FBIT)
+
+DEFTEST3 (hk, SACCUM_FBIT)
+DEFTEST3 (k, ACCUM_FBIT)
+DEFTEST3 (lk, LACCUM_FBIT)
+DEFTEST3 (llk, LLACCUM_FBIT)
+
+DEFTEST3 (uhk, USACCUM_FBIT)
+DEFTEST3 (uk, UACCUM_FBIT)
+DEFTEST3 (ulk, ULACCUM_FBIT)
+DEFTEST3 (ullk, ULLACCUM_FBIT)
+
+int main (void)
+{
+  test2hr();
+  test2k();
+
+  test3hr();
+  test3r();
+  test3lr();
+
+  test3uhr();
+  test3ur();
+  test3ulr();
+
+  test3hk();
+  test3k();
+  test3lk();
+  test3llk();
+
+  test3uhk();
+  test3uk();
+  test3ulk();
+  test3ullk();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-5-countlsfx.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-5-countlsfx.c
new file mode 100644
index 000000000..b0ff5e3d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-5-countlsfx.c
@@ -0,0 +1,82 @@
+/* { dg-options "-std=gnu99" } */
+/* { dg-do run } */
+
+#include <stdfix.h>
+
+extern void abort (void);
+
+#define DEFTEST1(T,FX)                              \
+  int test1_##FX (T x)                              \
+  {                                                 \
+    return countls##FX (x);                         \
+  }                                                 \
+                                                    \
+  int test1_u##FX (unsigned T x)                    \
+  {                                                 \
+    return countlsu##FX (x);                        \
+  }
+
+DEFTEST1 (short fract, hr)
+DEFTEST1 (fract, r)
+DEFTEST1 (long fract, lr)
+DEFTEST1 (long long fract, llr)
+
+DEFTEST1 (short accum, hk)
+DEFTEST1 (accum, k)
+DEFTEST1 (long accum, lk)
+DEFTEST1 (long long accum, llk)
+
+
+#define TEST2P(FX, VAL, DD)                                             \
+  {                                                                     \
+    if (countls##FX (FX##bits (VAL)) != 8 * sizeof (0##FX) - DD)        \
+      abort();                                                          \
+                                                                        \
+    if (countlsu##FX (u##FX##bits (VAL)) != 8 * sizeof (0u##FX) + 1 - DD) \
+      abort();                                                          \
+  }
+
+
+#define TEST2M(FX, VAL, DD)                                             \
+  {                                                                     \
+    if (countls##FX (FX##bits (VAL)) != 8 * sizeof (0##FX) - (DD))      \
+      abort();                                                          \
+                                                                        \
+    if (countlsu##FX (u##FX##bits (VAL)) != 0)                          \
+      abort();                                                          \
+  }
+
+
+#define TEST2PX(VAL, DD)                        \
+  TEST2P (hr, VAL, DD);                         \
+  TEST2P (r,  VAL, DD);                         \
+  TEST2P (lr, VAL, DD);                         \
+                                                \
+  TEST2P (hk, VAL, DD);                         \
+  TEST2P (k,  VAL, DD);                         \
+  TEST2P (lk, VAL, DD);                         \
+  TEST2P (llk, VAL, DD)
+
+#define TEST2MX(VAL, DD)                        \
+  TEST2M (hr, VAL,  DD);                        \
+  TEST2M (r,  VAL,  DD);                        \
+  TEST2M (lr, VAL,  DD);                        \
+                                                \
+  TEST2M (hk,  VAL, DD);                        \
+  TEST2M (k,   VAL, DD);                        \
+  TEST2M (lk,  VAL, DD);                        \
+  TEST2M (llk, VAL, DD)
+
+
+int main (void)
+{
+  TEST2PX (1, 2);
+  TEST2PX (2, 3);
+  TEST2PX (3, 3);
+  
+  TEST2MX (-1, 1);
+  TEST2MX (-2, 2);
+  TEST2MX (-3, 3);
+  
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-error.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-error.c
new file mode 100644
index 000000000..692b8afd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/builtins-error.c
@@ -0,0 +1,11 @@
+/* { dg-do assemble } */
+
+char insert (long a)
+{
+    return __builtin_avr_insert_bits (15.3f+a, 0, 0); /* { dg-error "expects a compile time" } */
+}
+
+void delay (long a)
+{
+    __builtin_avr_delay_cycles (a); /* { dg-error "expects a compile time" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/fix-types.h b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/fix-types.h
new file mode 100644
index 000000000..f6a2aeb6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/fix-types.h
@@ -0,0 +1,134 @@
+typedef __INT8_TYPE__  int_hr_t;
+typedef __UINT8_TYPE__ int_uhr_t;
+
+typedef __INT16_TYPE__  int_hk_t;
+typedef __UINT16_TYPE__ int_uhk_t;
+typedef __INT16_TYPE__  int_r_t;
+typedef __UINT16_TYPE__ int_ur_t;
+
+typedef __INT32_TYPE__  int_k_t;
+typedef __UINT32_TYPE__ int_uk_t;
+typedef __INT32_TYPE__  int_lr_t;
+typedef __UINT32_TYPE__ int_ulr_t;
+
+typedef __INT64_TYPE__  int_lk_t;
+typedef __UINT64_TYPE__ int_ulk_t;
+typedef __INT64_TYPE__  int_llr_t;
+typedef __UINT64_TYPE__ int_ullr_t;
+typedef __INT64_TYPE__  int_llk_t;
+typedef __UINT64_TYPE__ int_ullk_t;
+
+typedef __INT16_TYPE__  xint_hr_t;
+typedef __UINT16_TYPE__ xint_uhr_t;
+
+typedef __INT32_TYPE__  xint_hk_t;
+typedef __UINT32_TYPE__ xint_uhk_t;
+typedef __INT32_TYPE__  xint_r_t;
+typedef __UINT32_TYPE__ xint_ur_t;
+
+typedef __INT64_TYPE__  xint_k_t;
+typedef __UINT64_TYPE__ xint_uk_t;
+typedef __INT64_TYPE__  xint_lr_t;
+typedef __UINT64_TYPE__ xint_ulr_t;
+
+#define INThr_MAX __INT8_MAX__
+#define INThr_MIN (-__INT8_MAX__-1)
+#define INTuhr_MAX __UINT8_MAX__
+
+#define INTr_MAX __INT16_MAX__
+#define INTr_MIN (-__INT16_MAX__-1)
+#define INTur_MAX __UINT16_MAX__
+
+#define INThk_MAX __INT16_MAX__
+#define INThk_MIN (-__INT16_MAX__-1)
+#define INTuhk_MAX __UINT16_MAX__
+
+#define INTlr_MAX __INT32_MAX__
+#define INTlr_MIN (-__INT32_MAX__-1)
+#define INTulr_MAX __UINT32_MAX__
+
+#define INTk_MAX __INT32_MAX__
+#define INTk_MIN (-__INT32_MAX__-1)
+#define INTuk_MAX __UINT32_MAX__
+
+#define INTlk_MAX __INT64_MAX__
+#define INTlk_MIN (-__INT64_MAX__-1)
+#define INTulk_MAX __UINT64_MAX__
+
+#define INTllk_MAX __INT64_MAX__
+#define INTllk_MIN (-__INT64_MAX__-1)
+#define INTullk_MAX __UINT64_MAX__
+
+#define SS_FUN(NAME, OP, T, FX)                 \
+  T __attribute__((noinline,noclone))           \
+  NAME##_##FX (T fa, T fb)                      \
+  {                                             \
+    int_##FX##_t ia;                            \
+    int_##FX##_t ib;                            \
+    xint_##FX##_t ic;                           \
+    __builtin_memcpy (&ia, &fa, sizeof (ia));   \
+    __builtin_memcpy (&ib, &fb, sizeof (ib));   \
+    ic = (xint_##FX##_t) ia OP ib;              \
+    if (ic > INT##FX##_MAX)                     \
+      ic = INT##FX##_MAX;                       \
+    else if (ic < INT##FX##_MIN)                \
+      ic = INT##FX##_MIN;                       \
+    ia = (int_##FX##_t) ic;                     \
+    __builtin_memcpy (&fa, &ia, sizeof (ia));   \
+    return fa;                                  \
+  }
+
+#define US_FUN(NAME, OP, T, FX)                 \
+  T __attribute__((noinline,noclone))           \
+  NAME##_##FX (T fa, T fb)                      \
+  {                                             \
+    int_##FX##_t ia;                            \
+    int_##FX##_t ib;                            \
+    xint_##FX##_t ic;                           \
+    __builtin_memcpy (&ia, &fa, sizeof (ia));   \
+    __builtin_memcpy (&ib, &fb, sizeof (ib));   \
+    ic = (xint_##FX##_t) ia OP ib;              \
+    if (ic > INT##FX##_MAX)                     \
+      ic = INT##FX##_MAX;                       \
+    else if (ic < 0)                            \
+      ic = 0;                                   \
+    ia = (int_##FX##_t) ic;                     \
+    __builtin_memcpy (&fa, &ia, sizeof (ia));   \
+    return fa;                                  \
+  }
+
+#define SS_LFUN(NAME, OP, T, FX, CMP)           \
+  T __attribute__((noinline,noclone))           \
+  NAME##_##FX (T fa, T fb)                      \
+  {                                             \
+    int_##FX##_t ia;                            \
+    int_##FX##_t ib;                            \
+    int_##FX##_t ic;                            \
+    __builtin_memcpy (&ia, &fa, sizeof (ia));   \
+    __builtin_memcpy (&ib, &fb, sizeof (ib));   \
+    ic = (int_##FX##_t) ia OP ib;               \
+    if (ic < ia && ib CMP 0)                    \
+      ic = INT##FX##_MAX;                       \
+    else if (ic > ia && 0 CMP ib)               \
+      ic = INT##FX##_MIN;                       \
+    __builtin_memcpy (&fa, &ic, sizeof (ic));   \
+    return fa;                                  \
+  }
+
+#define US_LFUN(NAME, OP, T, FX, CMP)           \
+  T __attribute__((noinline,noclone))           \
+  NAME##_##FX (T fa, T fb)                      \
+  {                                             \
+    int_##FX##_t ia;                            \
+    int_##FX##_t ib;                            \
+    int_##FX##_t ic;                            \
+    __builtin_memcpy (&ia, &fa, sizeof (ia));   \
+    __builtin_memcpy (&ib, &fb, sizeof (ib));   \
+    ic = (int_##FX##_t) ia OP ib;               \
+    if (ia CMP ic && 1 CMP 0)                   \
+      ic = INT##FX##_MAX;                       \
+    if (ia CMP ic && 0 CMP 1)                   \
+      ic = 0;                                   \
+    __builtin_memcpy (&fa, &ic, sizeof (ic));   \
+    return fa;                                  \
+  }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/int24-mul.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/int24-mul.c
new file mode 100644
index 000000000..c85d93277
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/int24-mul.c
@@ -0,0 +1,86 @@
+/* { dg-do run } */
+/* { dg-options "-w" } */
+
+#include <stdlib.h>
+
+const __flash __int24 vals[] =
+  {
+    0, 1, 2, 3, -1, -2, -3, 0xff, 0x100, 0x101,
+    0xffL * 0xff, 0xfffL * 0xfff, 0x101010L, 0xaaaaaaL
+  };
+
+void test_u (void)
+{
+  unsigned int i;
+  unsigned long la, lb, lc;
+  __uint24 a, b, c;
+
+  int S = sizeof (vals) / sizeof (*vals);
+
+  for (i = 0; i < 500; i++)
+    {
+      if (i < S*S)
+        {
+          a = vals[i / S];
+          b = vals[i % S];
+        }
+      else
+        {
+          if (i & 1)
+            a += 0x7654321L;
+          else
+            b += 0x5fe453L;
+        }
+
+      c = a * b;
+
+      la = a;
+      lb = b;
+      lc = 0xffffff & (la * lb);
+      
+      if (c != lc)
+        abort();
+    }
+}
+
+#define TEST_N_U(A1,A2,B)                       \
+  do {                                          \
+    if ((0xffffff & (A1*B)) != A2*B)            \
+      abort();                                  \
+  } while (0)
+
+void test_nu (void)
+{
+  unsigned long la;
+  unsigned int i;
+  int S = sizeof (vals) / sizeof (*vals);
+  __uint24 a;
+  
+  for (i = 0; i < 500; i++)
+    {
+      a = i < S
+        ? vals[i % S]
+        : a + 0x7654321;
+
+      la = a;
+
+      TEST_N_U (la, a, 2);
+      TEST_N_U (la, a, 3);
+      TEST_N_U (la, a, 4);
+      TEST_N_U (la, a, 5);
+      TEST_N_U (la, a, 15);
+      TEST_N_U (la, a, 16);
+      TEST_N_U (la, a, 128);
+      TEST_N_U (la, a, 0x1000);
+    }
+}
+     
+int main (void)
+{
+  test_u();
+  test_nu();
+  
+  exit(0);
+    
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr39633.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr39633.c
new file mode 100644
index 000000000..c5f5b0450
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr39633.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+
+#include <stdlib.h>
+
+char c = 42;
+
+void __attribute__((noinline,noclone))
+pr39633 (char a)
+{
+  a >>= 7;
+  if (a)
+    c = a;
+}
+
+int main()
+{
+  pr39633 (6);
+
+  if (c != 42)
+    abort();
+
+  exit(0);
+    
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr41885.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr41885.c
new file mode 100644
index 000000000..f46bc5a75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr41885.c
@@ -0,0 +1,123 @@
+/* { dg-options "-w -std=c99 -fno-inline" } */
+/* { dg-do run } */
+
+#include <limits.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+
+uint16_t rotl_16a (uint16_t x)
+{
+    return (x << 8) | (x >> 8);
+}
+uint16_t rotl_16b (short dummy, uint16_t x)
+{
+    return (x << 8) | (x >> 8);
+}
+
+uint32_t rotl_32a (uint32_t x)
+{
+    return (x << 8) | (x >> 24);
+}
+uint32_t rotl_32b (short dummy, uint32_t x)
+{
+    return (x << 8) | (x >> 24);
+}
+uint32_t rotl_32c (short dummy, uint32_t x)
+{
+    return (x << 16) | (x >> 16);
+}
+uint32_t rotl_32d (short dummy, uint32_t x)
+{
+    return (x << 24) | (x >> 8);
+}
+uint32_t rotl_32e (long dummy, uint32_t x)
+{
+    return (x << 24) | (x >> 8);
+}
+
+uint64_t rotl_64 (uint64_t x)
+{
+    return (x << 56) | (x >> 8);
+}
+
+uint64_t rotl_64a (short dummy, uint64_t x)
+{
+    return (x << 56) | (x >> 8);
+}
+uint64_t rotl_64b (short dummy, uint64_t x)
+{
+    return (x << 48) | (x >> 16);
+}
+uint64_t rotl_64c (short dummy, uint64_t x)
+{
+    return (x << 40) | (x >> 24);
+}
+uint64_t rotl_64d (short dummy, uint64_t x)
+{
+    return (x << 32) | (x >> 32);
+}
+uint64_t rotl_64e (short dummy, uint64_t x)
+{
+    return (x << 24) | (x >> 40);
+}
+uint64_t rotl_64f (short dummy, uint64_t x)
+{
+    return (x << 16) | (x >> 48);
+}
+uint64_t rotl_64g (short dummy, uint64_t x)
+{
+    return (x << 8) | (x >> 56);
+}
+uint64_t rotl_64h (long dummy, uint64_t x)
+{
+    return (x << 16) | (x >> 48);
+}
+ 
+
+
+
+int main (void)
+{
+  if (rotl_16a(0x1234) != 0x3412)
+    abort();
+  if (rotl_16b(0xAA55,0x1234) != 0x3412)
+    abort();
+
+uint32_t num32 = 0x12345678;  
+
+  if (rotl_32a(num32) != 0x34567812)
+    abort();
+  if (rotl_32b(0xAA55,num32) != 0x34567812)
+    abort();
+  if (rotl_32c(0xAA55,num32) != 0x56781234)
+    abort();
+  if (rotl_32d(0xAA55,num32) != 0x78123456)
+    abort();
+  if (rotl_32e(0x1122AA55,num32) != 0x78123456)
+    abort();
+
+uint64_t num = 0x123456789ABCDEF0ULL;
+
+ if (rotl_64(num) != 0xF0123456789ABCDEULL)
+    abort();
+ if (rotl_64a(0xAA55,num) != 0xF0123456789ABCDEULL)
+    abort();
+ if (rotl_64b(0xAA55,num) != 0xDEF0123456789ABCULL)
+    abort();
+ if (rotl_64c(0xAA55,num) != 0xBCDEF0123456789AULL)
+    abort();
+ if (rotl_64d(0xAA55,num) != 0x9ABCDEF012345678ULL)
+    abort();
+ if (rotl_64e(0xAA55,num) != 0x789ABCDEF0123456ULL)
+    abort();
+ if (rotl_64f(0xAA55,num) != 0x56789ABCDEF01234ULL)
+    abort();
+ if (rotl_64g(0xAA55,num) != 0x3456789ABCDEF012ULL)
+    abort();
+ if (rotl_64h(0x1122AA55,num) != 0x56789ABCDEF01234ULL)
+    abort();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c
new file mode 100644
index 000000000..9c98ea5f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr51374-1.c
@@ -0,0 +1,15 @@
+/* PR rtl-optimization/51374 */
+/* { dg-do compile } */
+
+void vector_18 (void)
+{
+    extern char slot;
+    unsigned char status = (*(volatile unsigned char*) 0x2B);
+    unsigned char data   = (*(volatile unsigned char*) 0x2C);
+
+    if (status & 0x10)
+        slot = 0;
+}
+
+/* { dg-final { scan-assembler-not "\tsbic " } } */
+/* { dg-final { scan-assembler-not "\tsbis " } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr51782-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr51782-1.c
new file mode 100644
index 000000000..ff0f9d45f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr51782-1.c
@@ -0,0 +1,51 @@
+/* PR middle-end/51782 */
+/* { dg-do run } */
+/* { dg-options { "-std=gnu99" } } */
+
+#include <stdlib.h>
+
+struct R { char r; };
+struct RGB { char r,g,b; };
+
+__flash const struct R r1 = { 12 };
+__flash const struct RGB r3 = { 23, 56, 78 };
+
+char __attribute__((noinline,noclone))
+read1_bug (const __flash struct R *s)
+{
+  struct R t = *s;
+  return t.r;
+}
+
+char __attribute__((noinline,noclone))
+read1_ok (const __flash struct R *s)
+{
+  return s->r;
+}
+
+char __attribute__((noinline,noclone))
+read3_bug (const __flash struct RGB *s)
+{
+  struct RGB t = *s;
+  return t.r + t.g + t.b;
+}
+
+char __attribute__((noinline,noclone))
+read3_ok (const __flash struct RGB *s)
+{
+  return s->r + s->g + s->b;
+}
+
+__flash const struct R * volatile p1 = &r1;
+__flash const struct RGB * volatile p3 = &r3;
+
+int main (void)
+{
+  if (read1_bug (p1) != read1_ok (p1))
+    abort();
+  
+  if (read3_bug (p3) != read3_ok (p3))
+    abort();
+  
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr57631.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr57631.c
new file mode 100644
index 000000000..ecefbfc81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/pr57631.c
@@ -0,0 +1,17 @@
+/* PR target/57631 */
+/* { dg-do compile } */
+
+void __attribute__((signal)) func1 (void) __asm ("__vector1");
+void func1  (void)
+{
+}
+
+void __attribute__((signal)) func2 (void)  __asm ("__vecto1");
+void func2  (void) /* { dg-warning "misspelled signal handler" } */
+{
+}
+
+void __attribute__((signal)) __vector_3 (void)  __asm ("__vecto1");
+void __vector_3 (void) /* { dg-warning "misspelled signal handler" } */
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/progmem-1.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/progmem-1.c
new file mode 100644
index 000000000..790c676c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/progmem-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+
+#include "../exit-abort.h"
+#include "../progmem.h"
+
+const char strA[] PROGMEM = "@A";
+const char strc PROGMEM = 'c';
+
+unsigned int volatile s = 2;
+
+int main()
+{
+    char c;
+    
+    c = pgm_read_char (&strA[s-1]);
+    if (c != 'A')
+        abort();
+
+    c = pgm_read_char (&PSTR ("@@B")[s]);
+    if (c != 'B')
+        abort();
+
+    c = pgm_read_char (&strc);
+    if (c != 'c')
+        abort();
+
+    exit (0);
+
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/progmem-1.cpp b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/progmem-1.cpp
new file mode 100644
index 000000000..a1df9e78e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/progmem-1.cpp
@@ -0,0 +1,2 @@
+/* { dg-do run } */
+#include "progmem-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-hr-plus-minus.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-hr-plus-minus.c
new file mode 100644
index 000000000..1e6215e4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-hr-plus-minus.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fwrapv" } */
+
+#include "fix-types.h"
+
+extern void abort (void);
+extern void exit (int);
+
+typedef short _Fract fx_t;
+typedef short _Sat _Fract satfx_t;
+typedef char intfx_t;
+
+SS_FUN (ss_add, +, fx_t, hr)
+SS_FUN (ss_sub, -, fx_t, hr)
+
+#define VAL(N, X)                               \
+    __attribute__((noinline,noclone))           \
+    satfx_t ss_add2_##N (satfx_t a)             \
+    {                                           \
+        return ss_add_hr (a, X##P##-##7hr);     \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t ss_add_##N (satfx_t a)              \
+    {                                           \
+        return a + X##P##-##7hr;                \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t ss_sub2_##N (satfx_t a)             \
+    {                                           \
+        return ss_sub_hr (a, X##P##-##7hr);     \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t ss_sub_##N (satfx_t a)              \
+    {                                           \
+        return a - X##P##-##7hr;                \
+    }
+#include "vals-hr.def"
+#undef VAL
+
+__attribute__((noinline,noclone))
+satfx_t ss_add2_99 (satfx_t a)
+{
+  return ss_add_hr (a, __FRACT_MIN__);
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_add_99 (satfx_t a)
+{
+  return a + __FRACT_MIN__;
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_sub2_99 (satfx_t a)
+{
+  return ss_sub_hr (a, __FRACT_MIN__);
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_sub_99 (satfx_t a)
+{
+  return a - __FRACT_MIN__;
+}
+
+
+satfx_t (* __flash const fun[])(satfx_t) =
+{
+#define VAL(N, X)                               \
+  ss_add_##N, ss_add2_##N,                      \
+  ss_sub_##N, ss_sub2_##N,
+#include "vals-hr.def"
+  VAL (99,)
+#undef VAL
+};
+
+
+const volatile __flash intfx_t vals[] =
+  {
+    0, 1, 2, 0x7f, 0x80, 0x81, 0xff,
+    0x40, 0x3e, 0x3f, 0xbf, 0xc0, 0xc1
+  };
+
+int main (void)
+{
+  for (unsigned int i = 0; i < sizeof (vals) / sizeof (*vals); i++)
+    {
+      satfx_t a, f1, f2;
+      intfx_t val = vals[i];
+      __builtin_memcpy (&a, &val, sizeof (satfx_t));
+      for (unsigned int f = 0; f < sizeof (fun) / sizeof (*fun); f += 2)
+        {
+          if (fun[f](a) != fun[f+1](a))
+            abort();
+        }
+    }
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-k-plus-minus.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-k-plus-minus.c
new file mode 100644
index 000000000..8a26ffeeb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-k-plus-minus.c
@@ -0,0 +1,108 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fwrapv" } */
+
+#include "fix-types.h"
+
+extern void abort (void);
+extern void exit (int);
+
+typedef _Accum fx_t;
+typedef _Sat _Accum satfx_t;
+typedef long intfx_t;
+
+SS_FUN (ss_add, +, fx_t, k)
+SS_FUN (ss_sub, -, fx_t, k)
+
+#define VAL(N, X)                               \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_add2_##N (satfx_t a)               \
+  {                                             \
+    return ss_add_k (a, X##P##-##16k);          \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_add_##N (satfx_t a)                \
+  {                                             \
+    return a + X##P##-##16k;                    \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_sub2_##N (satfx_t a)               \
+  {                                             \
+    return ss_sub_k (a, X##P##-##16k);          \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_sub_##N (satfx_t a)                \
+  {                                             \
+    return a - X##P##-##16k;                    \
+  }
+#include "vals-k.def"
+#undef VAL
+
+__attribute__((noinline,noclone))
+satfx_t ss_add2_99 (satfx_t a)
+{
+  return ss_add_k (a, __ACCUM_MIN__);
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_add_99 (satfx_t a)
+{
+  return a + __ACCUM_MIN__;
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_sub2_99 (satfx_t a)
+{
+  return ss_sub_k (a, __ACCUM_MIN__);
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_sub_99 (satfx_t a)
+{
+  return a - __ACCUM_MIN__;
+}
+
+
+satfx_t (* __flash const fun[])(satfx_t) =
+{
+#define VAL(N, X)                               \
+  ss_add_##N, ss_add2_##N,                      \
+  ss_sub_##N, ss_sub2_##N,
+#include "vals-k.def"
+  VAL (99,)
+#undef VAL
+};
+
+
+const volatile __flash intfx_t vals[] =
+  {
+    0, -1, 1, -2, 2, -127, -128, -129,
+    0x7f, 0x80, 0x81, 0x100,
+    0x40000000, 0x3e800000, 0x3f800000,
+    0x7ffffffe, 0x7fffffff, 0x7f800000,
+    0x7f7f7f7f, 0x7f810080, 0x7f008000,
+    0x7f000001,
+    0x80000000, 0x80000001, 0x80808080,
+    0x80810000, 0x80ffffff, 0x80fffffe,
+    0x81000000, 0x81800000, 0x81800000,
+    0xff000000, 0xffffff01, 0xffffff80,
+    0xffffff7f, 0xff80ff80
+  };
+
+
+int main (void)
+{
+  for (unsigned int i = 0; i < sizeof (vals) / sizeof (*vals); i++)
+    {
+      satfx_t a, f1, f2;
+      intfx_t val = vals[i];
+      __builtin_memcpy (&a, &val, sizeof (satfx_t));
+      for (unsigned int f = 0; f < sizeof (fun) / sizeof (*fun); f += 2)
+        {
+          if (fun[f](a) != fun[f+1](a))
+            abort();
+        }
+    }
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-llk-plus-minus.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-llk-plus-minus.c
new file mode 100644
index 000000000..e81cbb187
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-llk-plus-minus.c
@@ -0,0 +1,108 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fwrapv" } */
+
+#include "fix-types.h"
+
+extern void abort (void);
+extern void exit (int);
+
+typedef long long _Accum fx_t;
+typedef long long _Sat _Accum satfx_t;
+typedef long long intfx_t;
+
+SS_LFUN (ss_add, +, fx_t, llk, >)
+SS_LFUN (ss_sub, -, fx_t, llk, <)
+
+#define VAL(N, X)                               \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_add2_##N (satfx_t a)               \
+  {                                             \
+    return ss_add_llk (a, X##P##-##48llk);      \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_add_##N (satfx_t a)                \
+  {                                             \
+    return a + X##P##-##48llk;                  \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_sub2_##N (satfx_t a)               \
+  {                                             \
+    return ss_sub_llk (a, X##P##-##48llk);      \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_sub_##N (satfx_t a)                \
+  {                                             \
+    return a - X##P##-##48llk;                  \
+  }
+#include "vals-llk.def"
+#undef VAL
+
+__attribute__((noinline,noclone))
+satfx_t ss_add2_99 (satfx_t a)
+{
+  return ss_add_llk (a, __LLACCUM_MIN__);
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_add_99 (satfx_t a)
+{
+  return a + __LLACCUM_MIN__;
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_sub2_99 (satfx_t a)
+{
+  return ss_sub_llk (a, __LLACCUM_MIN__);
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_sub_99 (satfx_t a)
+{
+  return a - __LLACCUM_MIN__;
+}
+
+
+satfx_t (* __flash const fun[])(satfx_t) =
+{
+#define VAL(N, X)                               \
+  ss_add_##N, ss_add2_##N,                      \
+  ss_sub_##N, ss_sub2_##N,
+#include "vals-llk.def"
+  VAL (99,)
+#undef VAL
+};
+
+
+const volatile __flash intfx_t vals[] =
+  {
+    0, -1, 1, -2, 2, -127, -128, -129,
+    0x7f, 0x80, 0x81, 0x100,
+    0x4000000000000000, 0x3e80000000000000, 0x3f80000000000000,
+    0x7ffffffffffffffe, 0x7fffffffffffffff, 0x7f80000000000000,
+    0x7f7f7f7f7f7f7f7f, 0x7f81000000000080, 0x7f00000080000000,
+    0x7f00000000000001,
+    0x8000000000000000, 0x8000000000000001, 0x8080808080808080,
+    0x8081000000000000, 0x80ffffffffffffff, 0x80fffffffffffffe,
+    0x8100000000000000, 0x8180000000000000, 0x818000000000000,
+    0xff00000000000000, 0xffffffffffffff01, 0xffffffffffffff80,
+    0xffffffffffffff7f, 0xff80ff80ff80ff80
+  };
+
+
+int main (void)
+{
+  for (unsigned int i = 0; i < sizeof (vals) / sizeof (*vals); i++)
+    {
+      satfx_t a, f1, f2;
+      intfx_t val = vals[i];
+      __builtin_memcpy (&a, &val, sizeof (satfx_t));
+      for (unsigned int f = 0; f < sizeof (fun) / sizeof (*fun); f += 2)
+        {
+          if (fun[f](a) != fun[f+1](a))
+            abort();
+        }
+    }
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-r-plus-minus.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-r-plus-minus.c
new file mode 100644
index 000000000..e59bcf655
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-r-plus-minus.c
@@ -0,0 +1,107 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fwrapv" } */
+
+#include "fix-types.h"
+
+extern void abort (void);
+extern void exit (int);
+
+typedef _Fract fx_t;
+typedef _Sat _Fract satfx_t;
+typedef int intfx_t;
+
+SS_FUN (ss_add, +, fx_t, r)
+SS_FUN (ss_sub, -, fx_t, r)
+
+#define VAL(N, X)                               \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_add2_##N (satfx_t a)               \
+  {                                             \
+    return ss_add_r (a, X##P##-##15r);          \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_add_##N (satfx_t a)                \
+  {                                             \
+    return a + X##P##-##15r;                    \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_sub2_##N (satfx_t a)               \
+  {                                             \
+    return ss_sub_r (a, X##P##-##15r);          \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t ss_sub_##N (satfx_t a)                \
+  {                                             \
+    return a - X##P##-##15r;                    \
+  }
+#include "vals-r.def"
+#undef VAL
+
+__attribute__((noinline,noclone))
+satfx_t ss_add2_99 (satfx_t a)
+{
+  return ss_add_r (a, __FRACT_MIN__);
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_add_99 (satfx_t a)
+{
+  return a + __FRACT_MIN__;
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_sub2_99 (satfx_t a)
+{
+  return ss_sub_r (a, __FRACT_MIN__);
+}
+
+__attribute__((noinline,noclone))
+satfx_t ss_sub_99 (satfx_t a)
+{
+  return a - __FRACT_MIN__;
+}
+
+
+satfx_t (* __flash const fun[])(satfx_t) =
+{
+#define VAL(N, X)                               \
+  ss_add_##N, ss_add2_##N,                      \
+  ss_sub_##N, ss_sub2_##N,
+#include "vals-r.def"
+  VAL (99,)
+#undef VAL
+};
+
+
+const volatile __flash intfx_t vals[] =
+  {
+    0, -1, 1, -2, 2, -127, -128, -129,
+    0x7f, 0x80, 0x81, 0x100,
+    0x4000, 0x3e80, 0x3f80,
+    0x7ffe, 0x7fff,
+    0x7f7f, 0x7f81, 0x7f80,
+    0x7f01,
+    0x8000, 0x8001, 0x8080,
+    0x8081, 0x80ff, 0x80fe,
+    0x8100, 0x8180, 0x817f,
+    0xff00, 0xff01, 0xff01,
+    0xff7f, 0xff80
+  };
+
+int main (void)
+{
+  for (unsigned int i = 0; i < sizeof (vals) / sizeof (*vals); i++)
+    {
+      satfx_t a, f1, f2;
+      intfx_t val = vals[i];
+      __builtin_memcpy (&a, &val, sizeof (satfx_t));
+      for (unsigned int f = 0; f < sizeof (fun) / sizeof (*fun); f += 2)
+        {
+          if (fun[f](a) != fun[f+1](a))
+            abort();
+        }
+    }
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-uhr-plus-minus.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-uhr-plus-minus.c
new file mode 100644
index 000000000..6dd191f7a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-uhr-plus-minus.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fwrapv" } */
+
+#include "fix-types.h"
+
+extern void abort (void);
+extern void exit (int);
+
+typedef unsigned short _Fract fx_t;
+typedef unsigned short _Sat _Fract satfx_t;
+typedef unsigned char intfx_t;
+
+US_LFUN (us_add, +, fx_t, uhr, >)
+US_LFUN (us_sub, -, fx_t, uhr, <)
+
+#define VAL(N, X)                               \
+  __attribute__((noinline,noclone))             \
+  satfx_t us_add2_##N (satfx_t a)               \
+  {                                             \
+    return us_add_uhr (a, X##P##-##8uhr);       \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t us_add_##N (satfx_t a)                \
+  {                                             \
+    return a + X##P##-##8uhr;                   \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t us_sub2_##N (satfx_t a)               \
+  {                                             \
+    return us_sub_uhr (a, X##P##-##8uhr);       \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t us_sub_##N (satfx_t a)                \
+  {                                             \
+    return a - X##P##-##8uhr;                   \
+  }
+#include "vals-uhr.def"
+#undef VAL
+
+satfx_t (* __flash const fun[])(satfx_t) =
+{
+#define VAL(N, X)                               \
+  us_add_##N, us_add2_##N,                      \
+  us_sub_##N, us_sub2_##N,
+#include "vals-uhr.def"
+#undef VAL
+};
+
+
+const volatile __flash intfx_t vals[] =
+  {
+    0, 1, 2, 0x7f, 0x80, 0x81, 0xff,
+    0x40, 0x3e, 0x3f, 0xbf, 0xc0, 0xc1
+  };
+
+
+int main (void)
+{
+  for (unsigned int i = 0; i < sizeof (vals) / sizeof (*vals); i++)
+    {
+      satfx_t a, f1, f2;
+      intfx_t val = vals[i];
+      __builtin_memcpy (&a, &val, sizeof (satfx_t));
+      for (unsigned int f = 0; f < sizeof (fun) / sizeof (*fun); f += 2)
+        {
+          if (fun[f](a) != fun[f+1](a))
+            abort();
+        }
+    }
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-uk-plus-minus.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-uk-plus-minus.c
new file mode 100644
index 000000000..c9a7cd6ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-uk-plus-minus.c
@@ -0,0 +1,82 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fwrapv" } */
+
+#include "fix-types.h"
+
+extern void abort (void);
+extern void exit (int);
+
+typedef unsigned _Accum fx_t;
+typedef unsigned _Sat _Accum satfx_t;
+typedef unsigned long intfx_t;
+
+US_LFUN (us_add, +, fx_t, uk, >)
+US_LFUN (us_sub, -, fx_t, uk, <)
+
+#define VAL(N, X)                               \
+    __attribute__((noinline,noclone))           \
+    satfx_t us_add2_##N (satfx_t a)             \
+    {                                           \
+        return us_add_uk (a, X##P##-##16uk);    \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t us_add_##N (satfx_t a)              \
+    {                                           \
+        return a + X##P##-##16uk;               \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t us_sub2_##N (satfx_t a)             \
+    {                                           \
+        return us_sub_uk (a, X##P##-##16uk);    \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t us_sub_##N (satfx_t a)              \
+    {                                           \
+        return a - X##P##-##16uk;               \
+    }
+#include "vals-uk.def"
+#undef VAL
+
+satfx_t (* __flash const fun[])(satfx_t) =
+{
+#define VAL(N, X)                               \
+  us_add_##N, us_add2_##N,                      \
+  us_sub_##N, us_sub2_##N,
+#include "vals-uk.def"
+#undef VAL
+};
+
+
+const volatile __flash intfx_t vals[] =
+  {
+    0, -1, 1, -2, 2, -127, -128, -129,
+    0x7f, 0x80, 0x81, 0x100,
+    0x40000000, 0x3e800000, 0x3f800000,
+    0x7ffffffe, 0x7fffffff, 0x7f800000,
+    0x7f7f7f7f, 0x7f810080, 0x7f008000,
+    0x7f000001,
+    0x80000000, 0x80000001, 0x80808080,
+    0x80810000, 0x80ffffff, 0x80fffffe,
+    0x81000000, 0x81800000, 0x81800000,
+    0xff000000, 0xffffff01, 0xffffff80,
+    0xffffff7f, 0xff80ff80
+  };
+
+
+int main (void)
+{
+  for (unsigned int i = 0; i < sizeof (vals) / sizeof (*vals); i++)
+    {
+      satfx_t a, f1, f2;
+      intfx_t val = vals[i];
+      __builtin_memcpy (&a, &val, sizeof (satfx_t));
+      for (unsigned int f = 0; f < sizeof (fun) / sizeof (*fun); f += 2)
+        {
+          if (fun[f](a) != fun[f+1](a))
+            abort();
+        }
+    }
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-ullk-plus-minus.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-ullk-plus-minus.c
new file mode 100644
index 000000000..22ebb8af5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-ullk-plus-minus.c
@@ -0,0 +1,82 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fwrapv" } */
+
+#include "fix-types.h"
+
+extern void abort (void);
+extern void exit (int);
+
+typedef unsigned long long _Accum fx_t;
+typedef unsigned long long _Sat _Accum satfx_t;
+typedef unsigned long long intfx_t;
+
+US_LFUN (us_add, +, fx_t, ullk, >)
+US_LFUN (us_sub, -, fx_t, ullk, <)
+
+#define VAL(N, X)                               \
+  __attribute__((noinline,noclone))             \
+  satfx_t us_add2_##N (satfx_t a)               \
+  {                                             \
+    return us_add_ullk (a, X##P##-##48ullk);    \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t us_add_##N (satfx_t a)                \
+  {                                             \
+    return a + X##P##-##48ullk;                 \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t us_sub2_##N (satfx_t a)               \
+  {                                             \
+    return us_sub_ullk (a, X##P##-##48ullk);    \
+  }                                             \
+  __attribute__((noinline,noclone))             \
+  satfx_t us_sub_##N (satfx_t a)                \
+  {                                             \
+    return a - X##P##-##48ullk;                 \
+  }
+#include "vals-ullk.def"
+#undef VAL
+
+satfx_t (* __flash const fun[])(satfx_t) =
+{
+#define VAL(N, X)                               \
+  us_add_##N, us_add2_##N,                      \
+  us_sub_##N, us_sub2_##N,
+#include "vals-ullk.def"
+#undef VAL
+};
+
+
+const volatile __flash intfx_t vals[] =
+  {
+    0, -1, 1, -2, 2, -127, -128, -129,
+    0x7f, 0x80, 0x81, 0x100,
+    0x4000000000000000, 0x3e80000000000000, 0x3f80000000000000,
+    0x7ffffffffffffffe, 0x7fffffffffffffff, 0x7f80000000000000,
+    0x7f7f7f7f7f7f7f7f, 0x7f81000000000080, 0x7f00000080000000,
+    0x7f00000000000001,
+    0x8000000000000000, 0x8000000000000001, 0x8080808080808080,
+    0x8081000000000000, 0x80ffffffffffffff, 0x80fffffffffffffe,
+    0x8100000000000000, 0x8180000000000000, 0x818000000000000,
+    0xff00000000000000, 0xffffffffffffff01, 0xffffffffffffff80,
+    0xffffffffffffff7f, 0xff80ff80ff80ff80
+  };
+
+
+int main (void)
+{
+  for (unsigned int i = 0; i < sizeof (vals) / sizeof (*vals); i++)
+    {
+      satfx_t a, f1, f2;
+      intfx_t val = vals[i];
+      __builtin_memcpy (&a, &val, sizeof (satfx_t));
+      for (unsigned int f = 0; f < sizeof (fun) / sizeof (*fun); f += 2)
+        {
+          if (fun[f](a) != fun[f+1](a))
+            abort();
+        }
+    }
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-ur-plus-minus.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-ur-plus-minus.c
new file mode 100644
index 000000000..bc3c0bbcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/sat-ur-plus-minus.c
@@ -0,0 +1,82 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -fwrapv" } */
+
+#include "fix-types.h"
+
+extern void abort (void);
+extern void exit (int);
+
+typedef unsigned _Fract fx_t;
+typedef unsigned _Sat _Fract satfx_t;
+typedef unsigned int intfx_t;
+
+US_LFUN (us_add, +, fx_t, ur, >)
+US_LFUN (us_sub, -, fx_t, ur, <)
+
+#define VAL(N, X)                               \
+    __attribute__((noinline,noclone))           \
+    satfx_t us_add2_##N (satfx_t a)             \
+    {                                           \
+        return us_add_ur (a, X##P##-##16ur);    \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t us_add_##N (satfx_t a)              \
+    {                                           \
+        return a + X##P##-##16ur;               \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t us_sub2_##N (satfx_t a)             \
+    {                                           \
+        return us_sub_ur (a, X##P##-##16ur);    \
+    }                                           \
+    __attribute__((noinline,noclone))           \
+    satfx_t us_sub_##N (satfx_t a)              \
+    {                                           \
+        return a - X##P##-##16ur;               \
+    }
+#include "vals-ur.def"
+#undef VAL
+
+satfx_t (* __flash const fun[])(satfx_t) =
+{
+#define VAL(N, X)                               \
+  us_add_##N, us_add2_##N,                      \
+  us_sub_##N, us_sub2_##N,
+#include "vals-ur.def"
+#undef VAL
+};
+
+
+const volatile __flash intfx_t vals[] =
+  {
+    0, -1, 1, -2, 2, -127, -128, -129,
+    0x7f, 0x80, 0x81, 0x100,
+    0x4000, 0x3e80, 0x3f80,
+    0x7ffe, 0x7fff,
+    0x7f7f, 0x7f81, 0x7f80,
+    0x7f01,
+    0x8000, 0x8001, 0x8080,
+    0x8081, 0x80ff, 0x80fe,
+    0x8100, 0x8180, 0x817f,
+    0xff00, 0xff01, 0xff01,
+    0xff7f, 0xff80
+  };
+
+
+int main (void)
+{
+  for (unsigned int i = 0; i < sizeof (vals) / sizeof (*vals); i++)
+    {
+      satfx_t a, f1, f2;
+      intfx_t val = vals[i];
+      __builtin_memcpy (&a, &val, sizeof (satfx_t));
+      for (unsigned int f = 0; f < sizeof (fun) / sizeof (*fun); f += 2)
+        {
+          if (fun[f](a) != fun[f+1](a))
+            abort();
+        }
+    }
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/trivial.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/trivial.c
new file mode 100644
index 000000000..f1beecb1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/trivial.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+
+#include <stdio.h>
+
+#define PROGMEM __attribute__((__progmem__))
+
+const char PROGMEM a1 = 0x12; 
+const int PROGMEM a2 = 0x2345; 
+const long PROGMEM a3 = 0x12345678; 
+
+int main(void)
+{
+  printf ("Hello World\n");
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-hr.def b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-hr.def
new file mode 100644
index 000000000..f6619c2ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-hr.def
@@ -0,0 +1,12 @@
+VAL (01, 0x0)
+VAL (02, 0x1)
+VAL (03, 0x3f)
+VAL (04,-0x3f)
+VAL (07, 0x40)
+VAL (08,-0x40)
+VAL (10,-0x1)
+VAL (12, 0x3f)
+VAL (13,-0x3f)
+VAL (14, 0x7f)
+VAL (15,-0x7f)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-k.def b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-k.def
new file mode 100644
index 000000000..a490c69b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-k.def
@@ -0,0 +1,32 @@
+VAL (01, 0x0)
+VAL (02, 0x1)
+VAL (03, 0x3f)
+VAL (04, 0x80)
+VAL (05, -0x1)
+VAL (06, -0x3f)
+VAL (07, 0x40000000)
+VAL (08,-0x40000000)
+
+VAL (10,-0x7fffffff)
+VAL (11, 0x7fffffff)
+VAL (12, 0x7f800000)
+VAL (13,-0x7f800000)
+VAL (14, 0x7f800001)
+VAL (15,-0x7f800001)
+VAL (16, 0x7f7f7f7f)
+VAL (17,-0x7f7f7f7f)
+VAL (18, 0x7f808080)
+VAL (19,-0x7f808080)
+VAL (20, 0x3e800000)
+VAL (21,-0x3e800000)
+VAL (22, 0x3f800000)
+VAL (23,-0x3f800000)
+VAL (24, 0x400000)
+VAL (25,-0x400000)
+VAL (26, 0x3f000000)
+VAL (27,-0x3f000000)
+VAL (28, 0xffff00)
+VAL (29,-0xffff00)
+VAL (30, 0x00ff00ff)
+VAL (31,-0x00ff00ff)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-llk.def b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-llk.def
new file mode 100644
index 000000000..726a7ebed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-llk.def
@@ -0,0 +1,32 @@
+VAL (01, 0x0)
+VAL (02, 0x1)
+VAL (03, 0x3f)
+VAL (04, 0x80)
+VAL (05, -0x1)
+VAL (06, -0x3f)
+VAL (07, 0x4000000000000000)
+VAL (08,-0x4000000000000000)
+
+VAL (10,-0x7fffffffffffffff)
+VAL (11, 0x7fffffffffffffff)
+VAL (12, 0x7f80000000000000)
+VAL (13,-0x7f80000000000000)
+VAL (14, 0x7f80000000000001)
+VAL (15,-0x7f80000000000001)
+VAL (16, 0x7f7f7f7f7f7f7f7f)
+VAL (17,-0x7f7f7f7f7f7f7f7f)
+VAL (18, 0x7f80808080808000)
+VAL (19,-0x7f80808080808000)
+VAL (20, 0x3e80000000000000)
+VAL (21,-0x3e80000000000000)
+VAL (22, 0x3f80000000000000)
+VAL (23,-0x3f80000000000000)
+VAL (24, 0x40000000000000)
+VAL (25,-0x40000000000000)
+VAL (26, 0x3f000000000000)
+VAL (27,-0x3f000000000000)
+VAL (28, 0xffffff00)
+VAL (29,-0xffffff00)
+VAL (30, 0x00ff00ff00ff00ff)
+VAL (31,-0x00ff00ff00ff00ff)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-r.def b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-r.def
new file mode 100644
index 000000000..0c5f83f7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-r.def
@@ -0,0 +1,30 @@
+VAL (01, 0x0)
+VAL (02, 0x1)
+VAL (03, 0x3f)
+VAL (04, 0x80)
+VAL (05, -0x1)
+VAL (06, -0x3f)
+VAL (07, 0x4000)
+VAL (08,-0x4000)
+
+VAL (10,-0x7fff)
+VAL (11, 0x7fff)
+VAL (12, 0x7f80)
+VAL (13,-0x7f80)
+VAL (14, 0x7f81)
+VAL (15,-0x7f81)
+VAL (16, 0x7f7f)
+VAL (17,-0x7f7f)
+VAL (18, 0x7f80)
+VAL (19,-0x7f80)
+VAL (20, 0x3e80)
+VAL (21,-0x3e80)
+VAL (22, 0x3f80)
+VAL (23,-0x3f80)
+VAL (24, 0x40)
+VAL (25,-0x40)
+VAL (26, 0x3f00)
+VAL (27,-0x3f00)
+VAL (30, 0x00ff)
+VAL (31,-0x00ff)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-uhr.def b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-uhr.def
new file mode 100644
index 000000000..71441567c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-uhr.def
@@ -0,0 +1,13 @@
+VAL (01, 0x0)
+VAL (02, 0x1)
+VAL (03, 0x3f)
+VAL (07, 0x40)
+VAL (08, 0xc0)
+VAL (10, 0xc1)
+VAL (12, 0xff)
+VAL (14, 0x7f)
+VAL (16, 0x81)
+VAL (20, 0xbf)
+
+VAL (99, 0x80)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-uk.def b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-uk.def
new file mode 100644
index 000000000..3e212836f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-uk.def
@@ -0,0 +1,23 @@
+VAL (01, 0x0)
+VAL (02, 0x1)
+VAL (03, 0x3f)
+VAL (04, 0x80)
+VAL (07, 0x40000000)
+VAL (08, 0xc0000000)
+VAL (10, 0x7fffffff)
+VAL (12, 0x7f800000)
+VAL (14, 0x7f800001)
+VAL (16, 0x7f7f7f7f)
+VAL (18, 0x7f808000)
+VAL (20, 0x3e800000)
+VAL (22, 0x3f800000)
+VAL (24, 0x40000000)
+VAL (26, 0x3f000000)
+VAL (28, 0xffff00)
+VAL (30, 0x00ff00ff)
+VAL (31, 0xff00ff00)
+VAL (32, 0x10000000)
+VAL (33, 0xff000000)
+
+VAL (99, 0x80000000)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-ullk.def b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-ullk.def
new file mode 100644
index 000000000..620182be6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-ullk.def
@@ -0,0 +1,20 @@
+VAL (01, 0x0)
+VAL (02, 0x1)
+VAL (03, 0x3f)
+VAL (04, 0x80)
+VAL (07, 0x4000000000000000)
+VAL (08, 0x4000000000000000)
+VAL (10, 0x7fffffffffffffff)
+VAL (12, 0x7f80000000000000)
+VAL (14, 0x7f80000000000001)
+VAL (16, 0x7f7f7f7f7f7f7f7f)
+VAL (18, 0x7f80808080808000)
+VAL (20, 0x3e80000000000000)
+VAL (22, 0x3f80000000000000)
+VAL (24, 0x40000000000000)
+VAL (26, 0x3f000000000000)
+VAL (28, 0xffffff00)
+VAL (30, 0x00ff00ff00ff00ff)
+
+VAL (99, 0x8000000000000000)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-ur.def b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-ur.def
new file mode 100644
index 000000000..d6ea8f1c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/torture/vals-ur.def
@@ -0,0 +1,17 @@
+VAL (01, 0x0)
+VAL (02, 0x1)
+VAL (03, 0x3f)
+VAL (04, 0x80)
+VAL (07, 0x4000)
+VAL (08, 0xc000)
+VAL (10, 0x7fff)
+VAL (12, 0x7f80)
+VAL (14, 0x7f81)
+VAL (16, 0x7f7f)
+VAL (20, 0x3e80)
+VAL (22, 0x3f80)
+VAL (26, 0x3f00)
+VAL (32, 0x100)
+
+VAL (99, 0x8000)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/avr/trivial.c b/gcc-4.9/gcc/testsuite/gcc.target/avr/trivial.c
new file mode 100644
index 000000000..f1beecb1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/avr/trivial.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+
+#include <stdio.h>
+
+#define PROGMEM __attribute__((__progmem__))
+
+const char PROGMEM a1 = 0x12; 
+const int PROGMEM a2 = 0x2345; 
+const long PROGMEM a3 = 0x12345678; 
+
+int main(void)
+{
+  printf ("Hello World\n");
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090411-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090411-1.c
new file mode 100644
index 000000000..e301518a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090411-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target bfin-*-* } } */
+/* { dg-options "-O2" } */
+
+typedef short __v2hi __attribute__ ((vector_size (4)));
+typedef __v2hi raw2x16;
+typedef raw2x16 fract2x16;
+typedef short fract16;
+typedef struct complex_fract16
+{
+  fract16 re;
+  fract16 im;
+} __attribute__ ((aligned (4))) complex_fract16;
+
+
+__inline__ __attribute__ ((always_inline))
+     static complex_fract16 csqu_fr16 (complex_fract16 _a)
+{
+  complex_fract16 _x;
+  fract2x16 i =
+    __builtin_bfin_csqu_fr16 (__builtin_bfin_compose_2x16 ((_a).im, (_a).re));
+  (_x).re = __builtin_bfin_extract_lo (i);
+  (_x).im = __builtin_bfin_extract_hi (i);
+  return _x;
+}
+
+complex_fract16 f (complex_fract16 _a)
+{
+  return csqu_fr16 (_a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-1.c
new file mode 100644
index 000000000..104454057
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-1.c
@@ -0,0 +1,39 @@
+/* { dg-do compile { target bfin-*-* } } */
+
+typedef short __v2hi __attribute__ ((vector_size (4)));
+typedef __v2hi raw2x16;
+typedef raw2x16 fract2x16;
+
+typedef short fract16;
+typedef struct complex_fract16
+{
+  fract16 re;
+  fract16 im;
+} __attribute__ ((aligned (4))) complex_fract16;
+
+typedef union composite_complex_fract16
+{
+  struct complex_fract16 x;
+  long raw;
+} composite_complex_fract16;
+
+__inline__ __attribute__ ((always_inline))
+static complex_fract16 cmsu_fr16 (complex_fract16 _sum,
+				  complex_fract16 _a, complex_fract16 _b)
+{
+  complex_fract16 r;
+  fract2x16 i =
+    __builtin_bfin_cmplx_msu (__builtin_bfin_compose_2x16
+			      ((_sum).im, (_sum).re),
+			      __builtin_bfin_compose_2x16 ((_a).im, (_a).re),
+			      __builtin_bfin_compose_2x16 ((_b).im, (_b).re));
+  (r).re = __builtin_bfin_extract_lo (i);
+  (r).im = __builtin_bfin_extract_hi (i);
+  return r;
+}
+
+composite_complex_fract16
+f (complex_fract16 _sum, complex_fract16 _a, complex_fract16 _b)
+{
+  return (composite_complex_fract16) cmsu_fr16 (_sum, _a, _b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-2.c
new file mode 100644
index 000000000..55255d7a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target bfin-*-* } } */
+
+typedef short fract16;
+typedef short __v2hi __attribute__ ((vector_size (4)));
+typedef __v2hi raw2x16;
+typedef raw2x16 fract2x16;
+typedef struct complex_fract16 {
+  fract16 re;
+  fract16 im;
+} __attribute__((aligned(4))) complex_fract16;
+
+
+__inline__
+__attribute__ ((always_inline))
+static complex_fract16 cmlt_fr16 (complex_fract16 _a,
+				  complex_fract16 _b)
+{
+  complex_fract16 r;
+  fract2x16 i;
+
+  i = __builtin_bfin_cmplx_mul(__builtin_bfin_compose_2x16((_a).im, (_a).re),
+			       __builtin_bfin_compose_2x16((_b).im, (_b).re));
+  (r).re = __builtin_bfin_extract_lo(i);
+  (r).im = __builtin_bfin_extract_hi(i);
+  return r;
+}
+
+
+complex_fract16 f(complex_fract16 a, complex_fract16 b) {
+  return cmlt_fr16(a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-3.c
new file mode 100644
index 000000000..fb0a9e16c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/20090914-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target bfin-*-* } } */
+typedef long fract32;
+main() {
+  fract32 val_tmp;
+  fract32 val1 = 0x7FFFFFFF;
+  fract32 val2 = 0x40000000;
+  val_tmp = __builtin_bfin_mult_fr1x32x32 (0x06666667, val1);
+  val2 = __builtin_bfin_mult_fr1x32x32 (0x79999999, val2);
+  val2 = __builtin_bfin_add_fr1x32 (val_tmp, val2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/arith.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/arith.c
new file mode 100644
index 000000000..35029ed32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/arith.c
@@ -0,0 +1,48 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, c, d;
+  fract16 t1, t2;
+  a = __builtin_bfin_compose_2x16 (0x3000, 0x2000);
+  b = __builtin_bfin_compose_2x16 (0x7000, 0x5000);
+  c = __builtin_bfin_compose_2x16 (0x7000, 0xc000);
+
+  d = __builtin_bfin_add_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x7000 || t2 != 0x7fff)
+    abort ();
+
+  d = __builtin_bfin_sub_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != -0x3000 || t2 != -0x4000)
+    abort ();
+
+  d = __builtin_bfin_negate_fr2x16 (c);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x4000 || t2 != -0x7000)
+    abort ();
+  
+  if (__builtin_bfin_add_fr1x32 (0x7fffffff, 1) != 0x7fffffff)
+    abort ();
+
+  if (__builtin_bfin_add_fr1x32 (0x80000000, -1) != 0x80000000)
+    abort ();
+    
+  if (__builtin_bfin_add_fr1x32 (0x80000001, -1) != 0x80000000)
+    abort ();
+    
+  if (__builtin_bfin_add_fr1x32 (0xFEDCBA98, 0x11111111) != 0x0FEDCBA9)
+    abort ();
+    
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/bfin.exp b/gcc-4.9/gcc/testsuite/gcc.target/bfin/bfin.exp
new file mode 100644
index 000000000..a1b6707e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/bfin.exp
@@ -0,0 +1,87 @@
+# Copyright (C) 2007-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an BFIN target.
+if ![istarget bfin-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Like dg-options, but treats certain Blackfin-specific options specially:
+#
+#    -mcpu=*
+#	Select the target cpu. Skip the test if the multilib flags force
+#	a different cpu.
+proc dg-bfin-options {args} {
+    upvar dg-extra-tool-flags extra_tool_flags
+    upvar dg-do-what do_what
+
+    set multilib_cpu ""
+    set cpu ""
+
+    foreach flag [target_info multilib_flags] {
+	regexp "^-mcpu=(.*)" $flag dummy multilib_cpu
+    }
+
+    set flags [lindex $args 1]
+
+    foreach flag $flags {
+	regexp "^-mcpu=(.*)" $flag dummy cpu
+    }
+
+    if {$multilib_cpu == "" || $multilib_cpu == $cpu} {
+	set extra_tool_flags $flags
+    } else {
+	set do_what [list [lindex $do_what 0] "N" "P"]
+    }
+}
+
+# dg-bfin-processors can be used to specify the processors which can
+# run the test case.
+proc dg-bfin-processors {args} {
+    upvar dg-extra-tool-flags extra_tool_flags
+    upvar dg-do-what do_what
+
+    set multilib_cpu ""
+    set cpu ""
+
+    foreach flag [target_info multilib_flags] {
+	regexp "^-mcpu=([^-]*)" $flag dummy multilib_cpu
+    }
+
+    set cpus [lindex $args 1]
+
+    foreach cpu $cpus {
+	if {$multilib_cpu == $cpu} {
+	    return
+	}
+    }
+
+    set do_what [list [lindex $do_what 0] "N" "P"]
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]]	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-1.c
new file mode 100644
index 000000000..9ca524d29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_abs_fr1x16 (0x7777);
+  if (t1 != 0x7777)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-2.c
new file mode 100644
index 000000000..00ef1dc16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_abs_fr1x16 (0x8000);
+  if (t1 != 0x7fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-1.c
new file mode 100644
index 000000000..a464c02d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_abs_fr1x32 (0x77777777);
+  if (t != 0x77777777)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-2.c
new file mode 100644
index 000000000..9d642b123
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_abs_fr1x32 (0x80000000);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-1.c
new file mode 100644
index 000000000..86badedce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+
+  t = __builtin_bfin_abs_fr2x16 (a);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x5fff || t2 != 0x1)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-2.c
new file mode 100644
index 000000000..80844bdaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/abs_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_abs_fr2x16 (a);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x1001 || t2 != 0x0001)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-1.c
new file mode 100644
index 000000000..bd8f46d83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-1.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_add_fr1x16 (0x3000, 0x2000);
+  if (t1 != 0x5000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-2.c
new file mode 100644
index 000000000..1054e95aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x16-2.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_add_fr1x16 (0x3000, 0xd000);
+  if (t1 != 0x0)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-1.c
new file mode 100644
index 000000000..a14ad688d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_add_fr1x32 (0x40003000, 0x50002000);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-2.c
new file mode 100644
index 000000000..2345cb09e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_add_fr1x32 (0x40003000, 0xc000d000);
+  if (t != 0x00010000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-1.c
new file mode 100644
index 000000000..69736978b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-1.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x4000, 0x2000);
+  b = __builtin_bfin_compose_2x16 (0x8000, 0x5000);
+
+  t = __builtin_bfin_add_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffffc000 || t2 != 0x7000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-2.c
new file mode 100644
index 000000000..f7a309b8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/add_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x7000, 0xc000);
+  b = __builtin_bfin_compose_2x16 (0x8000, 0xc000);
+
+  t = __builtin_bfin_add_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffff000 || t2 != 0xffff8000)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/bfin-builtins.exp b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/bfin-builtins.exp
new file mode 100644
index 000000000..6ab9929e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/bfin-builtins.exp
@@ -0,0 +1,39 @@
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `c-torture.exp' driver, looping over
+# optimization options.
+
+load_lib c-torture.exp
+load_lib target-supports.exp
+load_lib torture-options.exp
+
+if { ![istarget bfin-*-*] } then {
+  return
+}
+
+
+torture-init
+set-torture-options [list {} -Os -O0 -O1 -O2 -O3 {-ffast-math -mfast-fp -O2}  {-mfast-fp -O2}  {-ffast-math -O2}]
+set additional_flags "-W -Wall"
+
+foreach src [lsort [find $srcdir/$subdir *.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	    c-torture-execute [list $src] $additional_flags
+    }
+}
+
+torture-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/circptr.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/circptr.c
new file mode 100644
index 000000000..8419aa680
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/circptr.c
@@ -0,0 +1,29 @@
+#include <stdlib.h>
+
+int t[] = { 1, 2, 3, 4, 5, 6, 7 };
+int expect[] = { 1, 3, 6, 10, 15, 21, 28, 29, 31, 34, 38, 43, 49, 56 };
+
+int foo (int n)
+{
+    int *p = t;
+    int sum = 0;
+    int i;
+    for (i = 0; i < n; i++) {
+	sum += *p;
+	p = __builtin_bfin_circptr (p, sizeof *p, t, sizeof t);
+    }
+    return sum;
+}
+
+int main ()
+{
+    int i;
+    int *p = expect;
+    for (i = 0; i < 14; i++) {
+	int sum = foo (i + 1);
+	if (sum != *p)
+	    abort ();
+	p = __builtin_bfin_circptr (p, sizeof *p, expect, sizeof expect);
+    }
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-1.c
new file mode 100644
index 000000000..17344bf06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-1.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, c, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+  b = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+  c = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+
+  t = __builtin_bfin_cmplx_mac (a, b, c);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x2800 || t2 != 0x0a00)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-2.c
new file mode 100644
index 000000000..994711651
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mac_fr2x16-2.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, c, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+  b = __builtin_bfin_compose_2x16 (0xb000, 0xe000);
+  c = __builtin_bfin_compose_2x16 (0xa000, 0x8000);
+
+  t = __builtin_bfin_cmplx_mac (a, b, c);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x7fff || t2 != 0xfffff400)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-1.c
new file mode 100644
index 000000000..10fcd4ca4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-1.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, c, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x0000, 0x0000);
+  b = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+  c = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+
+  t = __builtin_bfin_cmplx_msu (a, b, c);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffff800 || t2 != 0x600)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-2.c
new file mode 100644
index 000000000..b2a7c5db3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_msu_fr2x16-2.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, c, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+  b = __builtin_bfin_compose_2x16 (0xb000, 0xe000);
+  c = __builtin_bfin_compose_2x16 (0xa000, 0x8000);
+
+  t = __builtin_bfin_cmplx_msu (a, b, c);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffffb800 || t2 != 0x2c00)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-1.c
new file mode 100644
index 000000000..c6b12257e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+  b = __builtin_bfin_compose_2x16 (0x2000, 0x1000);
+
+  t = __builtin_bfin_cmplx_mul (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x800 || t2 != 0xfffffa00)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-2.c
new file mode 100644
index 000000000..d31fc1567
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/cpmlx_mul_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xa000, 0x8000);
+  b = __builtin_bfin_compose_2x16 (0xb000, 0xe000);
+
+  t = __builtin_bfin_cmplx_mul (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x6800 || t2 != 0xffffe400)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-1.c
new file mode 100644
index 000000000..1d1c0f701
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-1.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a;
+  fract16 t;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+
+  t = __builtin_bfin_diff_hl_fr2x16 (a);
+  if (t != 0x6000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-2.c
new file mode 100644
index 000000000..329ff2eb8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_hl_fr2x16-2.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a;
+  fract16 t;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_diff_hl_fr2x16 (a);
+  if (t != 0x1000)
+   abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-1.c
new file mode 100644
index 000000000..02d93e758
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-1.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a;
+  fract16 t;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+
+  t = __builtin_bfin_diff_lh_fr2x16 (a);
+  if (t != 0xffffa000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-2.c
new file mode 100644
index 000000000..1e5dc699f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/diff_lh_fr2x16-2.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a;
+  fract16 t;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_diff_lh_fr2x16 (a);
+  if (t != -0x1000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-1.c
new file mode 100644
index 000000000..cb66ecfb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0x3000);
+  b = __builtin_bfin_compose_2x16 (0x4000, 0x2000);
+
+  t = __builtin_bfin_dspaddsubsat (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x7fff || t2 != 0x1000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-2.c
new file mode 100644
index 000000000..8d6cab691
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspaddsubsat_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xd000, 0x8000);
+  b = __builtin_bfin_compose_2x16 (0x1000, 0x5000);
+
+  t = __builtin_bfin_dspaddsubsat (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffffe000 || t2 != 0xffff8000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-1.c
new file mode 100644
index 000000000..0a16a4894
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0x3000);
+  b = __builtin_bfin_compose_2x16 (0x6000, 0x6000);
+
+  t = __builtin_bfin_dspsubaddsat (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != -0x1000 || t2 != 0x7fff)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-2.c
new file mode 100644
index 000000000..a69451eba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/dspsubaddsat_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xd000, 0xa000);
+  b = __builtin_bfin_compose_2x16 (0x1000, 0xc000);
+
+  t = __builtin_bfin_dspsubaddsat (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffffc000 || t2 != 0xffff8000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/hisilh.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/hisilh.c
new file mode 100644
index 000000000..4efbfd449
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/hisilh.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target bfin*-*-* } } */
+/* { dg-options "-O2" } */
+#include <stdlib.h>
+typedef short raw2x16 __attribute__ ((vector_size(4)));
+
+int x;
+
+int ll(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisill(a, b);
+    return x;
+}
+
+int lh(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisilh(a, b);
+    return x;
+}
+
+int hl(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisihl(a, b);
+    return x;
+}
+
+int hh(raw2x16 a, raw2x16 b)
+{
+    x = __builtin_bfin_mulhisihh(a, b);
+    return x;
+}
+
+int main ()
+{
+    raw2x16 a = __builtin_bfin_compose_2x16 (0x1234, 0x5678);
+    raw2x16 b = __builtin_bfin_compose_2x16 (0xFEDC, 0xBA98);
+    if (ll (a, b) != 0xe88e8740)
+	abort ();
+    if (lh (a, b) != 0xff9d5f20)
+	abort ();
+    if (hl (a, b) != 0xfb1096e0)
+	abort ();
+    if (hh (a, b) != 0xffeb3cb0)
+	abort ();
+    
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-1.c
new file mode 100644
index 000000000..c27d56a96
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_lshl_fr1x16 (0x1101, 4);
+  if (t1 != 0x1010)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-2.c
new file mode 100644
index 000000000..9be2abf88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_lshl_fr1x16 (0x4004, -4);
+  if (t1 != 0x0400)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-1.c
new file mode 100644
index 000000000..b9cf84f18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = __builtin_bfin_lshl_fr2x16 (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffffff0 || t2 != 0xfffffff0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-2.c
new file mode 100644
index 000000000..c2f13d57e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/lshl_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = __builtin_bfin_lshl_fr2x16 (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x0cff || t2 != 0x0fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-1.c
new file mode 100644
index 000000000..1d364b28a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_max_fr1x16 (0x7777, 0x7000);
+  if (t1 != 0x7777)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-2.c
new file mode 100644
index 000000000..eadf2fb05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_max_fr1x16 (0x8000, 0xc000);
+  if (t1 != -0x4000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-1.c
new file mode 100644
index 000000000..90adcef06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_max_fr1x32 (0x77777777, 0x70007000);
+  if (t != 0x77777777)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-2.c
new file mode 100644
index 000000000..b2ed2afa8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_max_fr1x32 (0x80000000, 0xc0000000);
+  if (t != 0xc0000000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-1.c
new file mode 100644
index 000000000..2d968fd33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-1.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+  b = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_max_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x5fff || t2 != 0x0001)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-2.c
new file mode 100644
index 000000000..369c20851
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/max_fr2x16-2.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0xd000);
+  b = __builtin_bfin_compose_2x16 (0xc000, 0x2000);
+
+  t = __builtin_bfin_max_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x5000 || t2 != 0x2000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-1.c
new file mode 100644
index 000000000..686dcdcef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_min_fr1x16 (0x7777, 0x7000);
+  if (t1 != 0x7000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-2.c
new file mode 100644
index 000000000..655804034
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_min_fr1x16 (0x7000, 0xc001);
+  if (t1 != -0x3fff) 
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-1.c
new file mode 100644
index 000000000..a824e76ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_min_fr1x32 (0x77777777, 0x70007000);
+  if (t != 0x70007000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-2.c
new file mode 100644
index 000000000..72151016e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_min_fr1x32 (0x70007000, 0xc000c000);
+  if (t != 0xc000c000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-1.c
new file mode 100644
index 000000000..2f2b401e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-1.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+  b = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_min_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x1001 || t2 != 0xffffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-2.c
new file mode 100644
index 000000000..af564f431
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/min_fr2x16-2.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0xd000);
+  b = __builtin_bfin_compose_2x16 (0xc000, 0x2000);
+
+  t = __builtin_bfin_min_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffffc000 || t2 != 0xffffd000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-1.c
new file mode 100644
index 000000000..06790c94a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-1.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b;
+  int t;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0x7000);
+  b = __builtin_bfin_compose_2x16 (0x4000, 0x2000);
+
+  t = __builtin_bfin_mulhisihh (a, b);
+  if (t != 0x14000000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-2.c
new file mode 100644
index 000000000..ef070584e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihh_fr2x16-2.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b;
+  int t;
+
+  a = __builtin_bfin_compose_2x16 (0xc000, 0xa000);
+  b = __builtin_bfin_compose_2x16 (0x7000, 0x2000);
+
+  t = __builtin_bfin_mulhisihh (a, b);
+  if (t != 0xe4000000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-1.c
new file mode 100644
index 000000000..e2768e399
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-1.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b;
+  int t;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0x7000);
+  b = __builtin_bfin_compose_2x16 (0x4000, 0x2000);
+
+  t = __builtin_bfin_mulhisihl (a, b);
+  if (t != 0xa000000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-2.c
new file mode 100644
index 000000000..b64eabe6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisihl_fr2x16-2.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b;
+  int t;
+
+  a = __builtin_bfin_compose_2x16 (0xa000, 0x7000);
+  b = __builtin_bfin_compose_2x16 (0xe000, 0x5000);
+
+  t = __builtin_bfin_mulhisihl (a, b);
+  if (t != 0xe2000000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-1.c
new file mode 100644
index 000000000..99faef51a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-1.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b;
+  int t;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0x7000);
+  b = __builtin_bfin_compose_2x16 (0x4000, 0x2000);
+
+  t = __builtin_bfin_mulhisilh (a, b);
+  if (t != 0x1c000000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-2.c
new file mode 100644
index 000000000..3aef80cf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisilh_fr2x16-2.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b;
+  int t;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0x7000);
+  b = __builtin_bfin_compose_2x16 (0xa000, 0x5000);
+
+  t = __builtin_bfin_mulhisilh (a, b);
+  if (t != 0xd6000000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-1.c
new file mode 100644
index 000000000..acf1e9e1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-1.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b;
+  int t;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0x7000);
+  b = __builtin_bfin_compose_2x16 (0x4000, 0x2000);
+
+  t = __builtin_bfin_mulhisill (a, b);
+  if (t != 0xe000000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-2.c
new file mode 100644
index 000000000..147d8e14b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mulhisill_fr2x16-2.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short  fract16;
+
+int main ()
+{
+  fract2x16 a, b;
+  int t;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0xa000);
+  b = __builtin_bfin_compose_2x16 (0x4000, 0x2000);
+
+  t = __builtin_bfin_mulhisill (a, b);
+  if (t != 0xf4000000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-1.c
new file mode 100644
index 000000000..614b44441
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_mult_fr1x16 (0x7777, 0x0007);
+  if (t1 != 0x0006)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-2.c
new file mode 100644
index 000000000..aec3b7ccf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_mult_fr1x16 (0x0002, 0x0001);
+  if (t1 != 0x0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-1.c
new file mode 100644
index 000000000..8c8ad87bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_mult_fr1x32 (0x7777, 0x0001);
+  if (t != 0x0000eeee)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-2.c
new file mode 100644
index 000000000..95d4f9d12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_mult_fr1x32 (0x0002, 0x0001);
+  if (t != 0x0004)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-1.c
new file mode 100644
index 000000000..ff41bf5cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_mult_fr1x32x32 (0x80000000, 0x80000000);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-2.c
new file mode 100644
index 000000000..6f5d5cbdb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_mult_fr1x32x32 (0x7fff0000, 0x00000007);
+  if (t != 0x6)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-1.c
new file mode 100644
index 000000000..9bdfae632
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_mult_fr1x32x32NS (0x80000000, 0x80000000);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-2.c
new file mode 100644
index 000000000..cb3f18c50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr1x32x32NS-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_mult_fr1x32x32NS (0x7fff0000, 0x00000007);
+  if (t != 0x6)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-1.c
new file mode 100644
index 000000000..d15dd4516
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-1.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+  b = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_mult_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x0c00 || t2 != 0xffffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-2.c
new file mode 100644
index 000000000..6592eaf86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/mult_fr2x16-2.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0xd000);
+  b = __builtin_bfin_compose_2x16 (0xc000, 0x2000);
+
+  t = __builtin_bfin_mult_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffffd800 || t2 != 0xfffff400)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-1.c
new file mode 100644
index 000000000..3612d9320
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_multr_fr1x16 (0x7777, 0x0007);
+  if (t1 != 0x0007)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-2.c
new file mode 100644
index 000000000..e5fb2173e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_multr_fr1x16 (0x0002, 0x0001);
+  if (t1 != 0x0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-1.c
new file mode 100644
index 000000000..33d5b4a42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-1.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+  b = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_multr_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xc01 || t2 != 0x0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-2.c
new file mode 100644
index 000000000..a2feed2f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/multr_fr2x16-2.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5000, 0xd000);
+  b = __builtin_bfin_compose_2x16 (0xc000, 0x2000);
+
+  t = __builtin_bfin_multr_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffffd800 || t2 != 0xfffff400)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-1.c
new file mode 100644
index 000000000..10b2626c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_negate_fr1x16 (0x7fff);
+  if (t1 != -0x7fff) 
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-2.c
new file mode 100644
index 000000000..c839dce32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_negate_fr1x16 (0x8000);
+  if (t1 != 0x7fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-3.c
new file mode 100644
index 000000000..0462de20a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x16-3.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_negate_fr1x16 (0xc000);
+  if (t1 != 0x4000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-1.c
new file mode 100644
index 000000000..c7ba22c71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_negate_fr1x32 (0x7fffffff);
+  if (t != -0x7fffffff) 
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-2.c
new file mode 100644
index 000000000..70532f4ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_negate_fr1x32 (0x80000000);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-1.c
new file mode 100644
index 000000000..449d8b8ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+
+  t = __builtin_bfin_negate_fr2x16 (a);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != -0x5fff || t2 != 0x1)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-2.c
new file mode 100644
index 000000000..db750648c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/negate_fr2x16-2.c
@@ -0,0 +1,21 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+  t = __builtin_bfin_negate_fr2x16 (a);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != -0x1001 || t2 != -0x1)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-1.c
new file mode 100644
index 000000000..b8a53dd0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-1.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x16 (0x1234);
+  if (a != 2)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-2.c
new file mode 100644
index 000000000..2534e9ff9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-2.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 f = 0x1234, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x16 (f);
+  g = f << a;
+  if (g != (fract16) 0x48d0)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-3.c
new file mode 100644
index 000000000..24b6fcbee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-3.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x16 (0xfedc);
+  if (a != 6)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-4.c
new file mode 100644
index 000000000..986af6c55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-4.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 f = 0xfedc, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x16 (f);
+  g = f << a;
+  if (g != (fract16) 0xb700)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-5.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-5.c
new file mode 100644
index 000000000..f85ce96ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-5.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x16 (0);
+  if (a != 15)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-6.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-6.c
new file mode 100644
index 000000000..bc30f23da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-6.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short fract16; 
+
+int main ()
+{
+  fract16 f = 0, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x16 (f);
+  g = f << a;
+  if (g != (fract16) 0)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-7.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-7.c
new file mode 100644
index 000000000..4edb00f34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-7.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x16 (0xffff);
+  if (a != 15)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-8.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-8.c
new file mode 100644
index 000000000..c04219f4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm16-8.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 f = 0xffff, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x16 (f);
+  g = f << a;
+  if (g != (fract16) 0x8000)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-1.c
new file mode 100644
index 000000000..f8c6b93ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-1.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (0x12345678);
+  if (a != 2)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-10.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-10.c
new file mode 100644
index 000000000..ba4ad920c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-10.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef int fract32;
+
+int main ()
+{
+  fract32 f = 0x1234, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (f);
+  g = f << a;
+  if (g != 0x48d00000)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-11.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-11.c
new file mode 100644
index 000000000..ae675b0d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-11.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (0xfffffedc);
+  if (a != 22)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-12.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-12.c
new file mode 100644
index 000000000..b7fbea7ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-12.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef int fract32;
+
+int main ()
+{
+  fract32 f = 0xfffffedc, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (f);
+  g = f << a;
+  if (g != 0xb7000000)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-2.c
new file mode 100644
index 000000000..4972ed43d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-2.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef int fract32;
+
+int main ()
+{
+  fract32 f = 0x12345678, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (f);
+  g = f << a;
+  if (g != 0x48d159e0)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-3.c
new file mode 100644
index 000000000..cc565b729
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-3.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (0xfedcba98);
+  if (a != 6)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-4.c
new file mode 100644
index 000000000..1b3ae8dde
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-4.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef int fract32;
+
+int main ()
+{
+  fract32 f = 0xfedcba98, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (f);
+  g = f << a;
+  if (g != 0xb72ea600)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-5.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-5.c
new file mode 100644
index 000000000..33c927917
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-5.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (0);
+  if (a != 31)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-6.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-6.c
new file mode 100644
index 000000000..2150c5a98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-6.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef int fract32;
+
+int main ()
+{
+  fract32 f = 0, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (f);
+  g = f << a;
+  if (g != 0)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-7.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-7.c
new file mode 100644
index 000000000..87f4579f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-7.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (0xffffffff);
+  if (a != 31)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-8.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-8.c
new file mode 100644
index 000000000..4918a06a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-8.c
@@ -0,0 +1,18 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef int fract32;
+
+int main ()
+{
+  fract32 f = 0xffffffff, g;
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (f);
+  g = f << a;
+  if (g != 0x80000000)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-9.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-9.c
new file mode 100644
index 000000000..08468ac3d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm32-9.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  int a;
+
+  a = __builtin_bfin_norm_fr1x32 (0x1234);
+  if (a != 18)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-1.c
new file mode 100644
index 000000000..ad80cd4c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  int m;
+
+  m = __builtin_bfin_norm_fr1x16 (0x1000);
+  if (m != 2)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-2.c
new file mode 100644
index 000000000..59e868daa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  int m;
+
+  m = __builtin_bfin_norm_fr1x16 (0x4000);
+  if (m != 0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-3.c
new file mode 100644
index 000000000..c769240b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x16-3.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  int m;
+
+  m = __builtin_bfin_norm_fr1x16 (0xe000);
+  if (m != 2)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-1.c
new file mode 100644
index 000000000..fe476f58f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-1.c
@@ -0,0 +1,13 @@
+extern void abort (void);
+
+int main ()
+{
+  int m;
+
+  m = __builtin_bfin_norm_fr1x32 (0xefffeff1);
+  if (m != 2)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-2.c
new file mode 100644
index 000000000..7cf1ebeca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/norm_fr1x32-2.c
@@ -0,0 +1,13 @@
+extern void abort (void);
+
+int main ()
+{
+  int m;
+
+  m = __builtin_bfin_norm_fr1x32 (0x0000eff1);
+  if (m != 15)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-1.c
new file mode 100644
index 000000000..f234bc9bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_shl_fr1x16 (0x1101, 4);
+  if (t1 != 0x7fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-2.c
new file mode 100644
index 000000000..95e3bfb0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_shl_fr1x16 (0x4004, -4);
+  if (t1 != 0x0400)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-3.c
new file mode 100644
index 000000000..1c77a7c01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-3.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_shl_fr1x16 (0xc101, 4);
+  if (t1 != 0xffff8000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-4.c
new file mode 100644
index 000000000..7cb9e8c68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-4.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_shl_fr1x16 (0xd004, -4);
+  if (t1 != 0xfffffd00)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-5.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-5.c
new file mode 100644
index 000000000..251ff1e18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-5.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short fract16;
+
+fract16 foo (fract16 f, short n)
+{
+  return __builtin_bfin_shl_fr1x16 (f, n);
+}
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = foo (0x1101, 4);
+  if (t1 != 0x7fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-6.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-6.c
new file mode 100644
index 000000000..8d50f2091
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-6.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short fract16;
+
+fract16 foo (fract16 f, short n)
+{
+  return __builtin_bfin_shl_fr1x16 (f, n);
+}
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = foo (0x4004, -4);
+  if (t1 != 0x0400)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-7.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-7.c
new file mode 100644
index 000000000..f78303a18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-7.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short fract16;
+
+fract16 foo (fract16 f, short n)
+{
+  return __builtin_bfin_shl_fr1x16 (f, n);
+}
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = foo (0xc101, 4);
+  if (t1 != 0xffff8000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-8.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-8.c
new file mode 100644
index 000000000..cea723f33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x16-8.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short fract16;
+
+fract16 foo (fract16 f, short n)
+{
+  return __builtin_bfin_shl_fr1x16 (f, n);
+}
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = foo (0xd004, -4);
+  if (t1 != 0xfffffd00)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-1.c
new file mode 100644
index 000000000..c85adfe56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_shl_fr1x32 (0x7feff4ff, 4);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-2.c
new file mode 100644
index 000000000..0a42ddc76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_shl_fr1x32 (0x7feff4ff, -4);
+  if (t != 0x7feff4f)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-3.c
new file mode 100644
index 000000000..a98bc0c98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-3.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_shl_fr1x32 (0xc000e4ff, 4);
+  if (t != 0x80000000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-4.c
new file mode 100644
index 000000000..f2d18b370
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-4.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_shl_fr1x32 (0xc000e4ff, -4);
+  if (t != 0xfc000e4f)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-5.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-5.c
new file mode 100644
index 000000000..2883c1875
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-5.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shl_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 t;
+
+  t = foo (0x7feff4ff, 4);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-6.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-6.c
new file mode 100644
index 000000000..94a4cde1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-6.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shl_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 t;
+
+  t = foo (0x7feff4ff, -4);
+  if (t != 0x7feff4f)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-7.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-7.c
new file mode 100644
index 000000000..f32423500
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-7.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shl_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 t;
+
+  t = foo (0xc000e4ff, 4);
+  if (t != 0x80000000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-8.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-8.c
new file mode 100644
index 000000000..930065085
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-8.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shl_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 t;
+
+  t = foo (0xc000e4ff, -4);
+  if (t != 0xfc000e4f)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-9.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-9.c
new file mode 100644
index 000000000..f24a266cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32-9.c
@@ -0,0 +1,19 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shl_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 f;
+
+  f = foo (0x12345678, 4);
+  if (f != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32.c
new file mode 100644
index 000000000..029378ad8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr1x32.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+
+typedef int fract32;
+
+extern void abort (void);
+
+int main ()
+{
+  fract32 f;
+
+  f = __builtin_bfin_shl_fr1x32 (0x12345678, 4);
+  if (f != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-1.c
new file mode 100644
index 000000000..53ca96047
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = __builtin_bfin_shl_fr2x16 (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffff8000 || t2 != 0xfffffff0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-2.c
new file mode 100644
index 000000000..9e24db38b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = __builtin_bfin_shl_fr2x16 (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffffcff || t2 != 0xffffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-3.c
new file mode 100644
index 000000000..6d91625d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-3.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_shl_fr2x16 (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x7fff || t2 != 0x10)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-4.c
new file mode 100644
index 000000000..9b12e847a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-4.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_shl_fr2x16 (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x100 || t2 != 0x0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-5.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-5.c
new file mode 100644
index 000000000..af9ac3f15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-5.c
@@ -0,0 +1,27 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+fract2x16 foo (fract2x16 f, short n)
+{
+  return __builtin_bfin_shl_fr2x16 (f, n);
+}
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = foo (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffff8000 || t2 != 0xfffffff0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-6.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-6.c
new file mode 100644
index 000000000..cc0808678
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-6.c
@@ -0,0 +1,27 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+fract2x16 foo (fract2x16 f, short n)
+{
+  return __builtin_bfin_shl_fr2x16 (f, n);
+}
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = foo (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffffcff || t2 != 0xffffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-7.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-7.c
new file mode 100644
index 000000000..dd235c891
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-7.c
@@ -0,0 +1,27 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+fract2x16 foo (fract2x16 f, short n)
+{
+  return __builtin_bfin_shl_fr2x16 (f, n);
+}
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = foo (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x7fff || t2 != 0x10)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-8.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-8.c
new file mode 100644
index 000000000..ed90541a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shl_fr2x16-8.c
@@ -0,0 +1,27 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+fract2x16 foo (fract2x16 f, short n)
+{
+  return __builtin_bfin_shl_fr2x16 (f, n);
+}
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = foo (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x100 || t2 != 0x0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-1.c
new file mode 100644
index 000000000..5a9df3de2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_shr_fr1x16 (0x1101, -4);
+  if (t1 != 0x7fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-2.c
new file mode 100644
index 000000000..39dd3a999
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_shr_fr1x16 (0x4004, 4);
+  if (t1 != 0x0400)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-3.c
new file mode 100644
index 000000000..fff331f6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-3.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short fract16;
+
+fract16 foo (fract16 f, short n)
+{
+  return __builtin_bfin_shr_fr1x16 (f, n);
+}
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = foo (0x1101, -4);
+  if (t1 != 0x7fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-4.c
new file mode 100644
index 000000000..8425b7a83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x16-4.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short fract16;
+
+fract16 foo (fract16 f, short n)
+{
+  return __builtin_bfin_shr_fr1x16 (f, n);
+}
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = foo (0x4004, 4);
+  if (t1 != 0x0400)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-1.c
new file mode 100644
index 000000000..3a5e12fd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_shr_fr1x32 (0x7feff4ff, -4);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-2.c
new file mode 100644
index 000000000..6f73462cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_shr_fr1x32 (0x7feff4ff, 4);
+  if (t != 0x7feff4f)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-3.c
new file mode 100644
index 000000000..664516365
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-3.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_shr_fr1x32 (0xc000e4ff, -4);
+  if (t != 0x80000000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-4.c
new file mode 100644
index 000000000..56ffe17c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-4.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_shr_fr1x32 (0xc000e4ff, 4);
+  if (t != 0xfc000e4f)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-5.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-5.c
new file mode 100644
index 000000000..6dbb7f2e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-5.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shr_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 t;
+
+  t = foo (0x7feff4ff, -4);
+  if (t != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-6.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-6.c
new file mode 100644
index 000000000..ef8915474
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-6.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shr_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 t;
+
+  t = foo (0x7feff4ff, 4);
+  if (t != 0x7feff4f)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-7.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-7.c
new file mode 100644
index 000000000..720546a71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-7.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shr_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 t;
+
+  t = foo (0xc000e4ff, -4);
+  if (t != 0x80000000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-8.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-8.c
new file mode 100644
index 000000000..9422f790b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-8.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shr_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 t;
+
+  t = foo (0xc000e4ff, 4);
+  if (t != 0xfc000e4f)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-9.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-9.c
new file mode 100644
index 000000000..caf17203d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32-9.c
@@ -0,0 +1,19 @@
+extern void abort (void);
+
+typedef long fract32;
+
+fract32 foo (fract32 f, short n)
+{
+  return __builtin_bfin_shr_fr1x32 (f, n);
+}
+
+int main ()
+{
+  fract32 f;
+
+  f = foo (0x87654321, 4);
+  if (f != 0xf8765432)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32.c
new file mode 100644
index 000000000..8be9ecfd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr1x32.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+
+typedef int fract32;
+
+extern void abort (void);
+
+int main ()
+{
+  fract32 f;
+
+  f = __builtin_bfin_shr_fr1x32 (0x87654321, 4);
+  if (f != 0xf8765432)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-1.c
new file mode 100644
index 000000000..6e9369547
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = __builtin_bfin_shr_fr2x16 (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffff8000 || t2 != 0xfffffff0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-2.c
new file mode 100644
index 000000000..1c83d2914
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = __builtin_bfin_shr_fr2x16 (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffffcff || t2 != 0xffffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-3.c
new file mode 100644
index 000000000..5b6af8b4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-3.c
@@ -0,0 +1,27 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+fract2x16 foo (fract2x16 f, short n)
+{
+  return __builtin_bfin_shr_fr2x16 (f, n);
+}
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = foo (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xffff8000 || t2 != 0xfffffff0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-4.c
new file mode 100644
index 000000000..63bbb8bc7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shr_fr2x16-4.c
@@ -0,0 +1,27 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+fract2x16 foo (fract2x16 f, short n)
+{
+  return __builtin_bfin_shr_fr2x16 (f, n);
+}
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = foo (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffffcff || t2 != 0xffffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-1.c
new file mode 100644
index 000000000..0de251ee2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_shrl_fr1x16 (0x8101, 4);
+  if (t1 != 0x0810)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-2.c
new file mode 100644
index 000000000..c6b88b6d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_shrl_fr1x16 (0x4004, -4);
+  if (t1 != 0x0040)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-3.c
new file mode 100644
index 000000000..0f8e168f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-3.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short fract16;
+
+fract16 foo (fract16 f, short n)
+{
+  return __builtin_bfin_shrl_fr1x16 (f, n);
+}
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = foo (0x8101, 4);
+  if (t1 != 0x0810)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-4.c
new file mode 100644
index 000000000..d266ce095
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr1x16-4.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short fract16;
+
+fract16 foo (fract16 f, short n)
+{
+  return __builtin_bfin_shrl_fr1x16 (f, n);
+}
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = foo (0x4004, -4);
+  if (t1 != 0x0040)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-1.c
new file mode 100644
index 000000000..1252b4d75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-1.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = __builtin_bfin_shrl_fr2x16 (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffffff0 || t2 != 0xfffffff0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-2.c
new file mode 100644
index 000000000..b4bec6e6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-2.c
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = __builtin_bfin_shrl_fr2x16 (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x0cff || t2 != 0x0fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-3.c
new file mode 100644
index 000000000..4036dbf53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-3.c
@@ -0,0 +1,27 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+fract2x16 foo (fract2x16 f, short n)
+{
+  return __builtin_bfin_shrl_fr2x16 (f, n);
+}
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = foo (a, -4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0xfffffff0 || t2 != 0xfffffff0)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-4.c
new file mode 100644
index 000000000..b6473fa4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/shrl_fr2x16-4.c
@@ -0,0 +1,27 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+fract2x16 foo (fract2x16 f, short n)
+{
+  return __builtin_bfin_shrl_fr2x16 (f, n);
+}
+
+int main ()
+{
+  fract2x16 a, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0xcfff, 0xffff);
+
+  t = foo (a, 4);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x0cff || t2 != 0x0fff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-1.c
new file mode 100644
index 000000000..b97bf8d63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-1.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_sub_fr1x16 (0x3000, 0x2000);
+  if (t1 != 0x1000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-2.c
new file mode 100644
index 000000000..5e4568034
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x16-2.c
@@ -0,0 +1,14 @@
+extern void abort (void);
+
+typedef short fract16;
+
+int main ()
+{
+  fract16 t1;
+
+  t1 = __builtin_bfin_sub_fr1x16 (0x3000, 0x4000);
+  if (t1 != -0x1000)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-1.c
new file mode 100644
index 000000000..5aedd9199
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-1.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t1;
+
+  t1 = __builtin_bfin_sub_fr1x32 (0x40003000, 0xc0003000);
+  if (t1 != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-2.c
new file mode 100644
index 000000000..8ac4a5aad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr1x32-2.c
@@ -0,0 +1,15 @@
+extern void abort (void);
+
+typedef long fract32;
+
+int main ()
+{
+  fract32 t;
+
+  t = __builtin_bfin_sub_fr1x32 (0x40003000, 0x70002000);
+  if (t != 0xd0001000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-1.c
new file mode 100644
index 000000000..34b8ac87d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-1.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x4000, 0x2000);
+  b = __builtin_bfin_compose_2x16 (0x8000, 0x5000);
+
+  t = __builtin_bfin_sub_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x7fff || t2 != -0x3000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-2.c
new file mode 100644
index 000000000..52f7d8052
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sub_fr2x16-2.c
@@ -0,0 +1,23 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, t;
+  fract16 t1, t2;
+
+  a = __builtin_bfin_compose_2x16 (0x7000, 0xc000);
+  b = __builtin_bfin_compose_2x16 (0xc000, 0xd000);
+
+  t = __builtin_bfin_sub_fr2x16 (a, b);
+  t1 = __builtin_bfin_extract_hi (t);
+  t2 = __builtin_bfin_extract_lo (t);
+  if (t1 != 0x7fff || t2 != -0x1000)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-1.c
new file mode 100644
index 000000000..56c4f191e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-1.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a;
+  fract16 t;
+
+  a = __builtin_bfin_compose_2x16 (0x5fff, 0xffff);
+
+  t = __builtin_bfin_sum_fr2x16 (a);
+  if (t != 0x5ffe)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-2.c
new file mode 100644
index 000000000..2f75bfdfc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/builtins/sum_fr2x16-2.c
@@ -0,0 +1,20 @@
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a;
+  fract16 t;
+
+  a = __builtin_bfin_compose_2x16 (0x1001, 0x0001);
+
+  t = __builtin_bfin_sum_fr2x16 (a);
+  if (t != 0x1002)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/frmul.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/frmul.c
new file mode 100644
index 000000000..61930bae5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/frmul.c
@@ -0,0 +1,149 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+#define GETVECT(HILO1,HILO2,IN1,IN2)					\
+  __builtin_bfin_compose_2x16 ((HILO2) ? __builtin_bfin_extract_hi (IN1) : __builtin_bfin_extract_lo (IN1), \
+			  (HILO1) ? __builtin_bfin_extract_hi (IN2) : __builtin_bfin_extract_lo (IN2))
+#define DOTEST(IN1, IN2, HL1, HL2, HL3, HL4)					\
+  __builtin_bfin_multr_fr2x16 (GETVECT (HL1, HL2, IN1, IN1), \
+			  GETVECT (HL3, HL4, IN2, IN2))
+
+#define FUNC(HL1, HL2, HL3, HL4) \
+  fract2x16 foo ## HL1 ## HL2 ## HL3 ## HL4 (fract2x16 a, fract2x16 b)\
+  { \
+    return DOTEST(a, b, HL1, HL2, HL3, HL4);\
+  }
+
+FUNC (0, 0, 0, 0)
+FUNC (1, 0, 0, 0)
+FUNC (0, 1, 0, 0)
+FUNC (1, 1, 0, 0)
+FUNC (0, 0, 1, 0)
+FUNC (1, 0, 1, 0)
+FUNC (0, 1, 1, 0)
+FUNC (1, 1, 1, 0)
+FUNC (0, 0, 0, 1)
+FUNC (1, 0, 0, 1)
+FUNC (0, 1, 0, 1)
+FUNC (1, 1, 0, 1)
+FUNC (0, 0, 1, 1)
+FUNC (1, 0, 1, 1)
+FUNC (0, 1, 1, 1)
+FUNC (1, 1, 1, 1)
+
+#define RES1 0x1400
+#define RES2 0x1e00
+#define RES3 0x1c00
+#define RES4 0x2a00
+
+
+int main ()
+{
+  fract2x16 a, b, c;
+  fract16 t1, t2;
+  a = __builtin_bfin_compose_2x16 (0x3000, 0x2000);
+  b = __builtin_bfin_compose_2x16 (0x7000, 0x5000);
+
+  c = foo0000 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES1 || t2 != RES1)
+    abort ();
+
+  c = foo1000 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES2 || t2 != RES1)
+    abort ();
+
+  c = foo0100 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES1 || t2 != RES2)
+    abort ();
+
+  c = foo1100 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES2 || t2 != RES2)
+    abort ();
+
+  c = foo0010 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES3 || t2 != RES1)
+    abort ();
+
+  c = foo1010 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES4 || t2 != RES1)
+    abort ();
+
+  c = foo0110 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES3 || t2 != RES2)
+    abort ();
+
+  c = foo1110 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES4 || t2 != RES2)
+    abort ();
+
+  c = foo0001 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES1 || t2 != RES3)
+    abort ();
+
+  c = foo1001 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES2 || t2 != RES3)
+    abort ();
+
+  c = foo0101 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES1 || t2 != RES4)
+    abort ();
+
+  c = foo1101 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES2 || t2 != RES4)
+    abort ();
+
+  c = foo0011 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES3 || t2 != RES3)
+    abort ();
+
+  c = foo1011 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES4 || t2 != RES3)
+    abort ();
+
+  c = foo0111 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES3 || t2 != RES4)
+    abort ();
+
+  c = foo1111 (a, b);
+  t1 = __builtin_bfin_extract_lo (c);
+  t2 = __builtin_bfin_extract_hi (c);
+  if (t1 != RES4 || t2 != RES4)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/l2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/l2.c
new file mode 100644
index 000000000..56f64cc82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/l2.c
@@ -0,0 +1,38 @@
+/* { dg-do run { target bfin-*-linux-uclibc } } */
+/* { dg-bfin-processors bf544 bf547 bf548 bf549 bf561} */
+
+#if defined(__ADSPBF544__)
+#define L2_START 0xFEB00000
+#define L2_LENGTH 0x10000
+#else
+#define L2_START 0xFEB00000
+#define L2_LENGTH 0x20000
+#endif
+
+int n __attribute__ ((l2));
+
+int foo (int i) __attribute__ ((l2));
+
+int foo (int a)
+{
+  return a + 1;
+}
+
+int main ()
+{
+  int r;
+  unsigned long *p;
+
+  p = (unsigned long *) foo;
+  if (*p < L2_START || *p >= L2_START + L2_LENGTH)
+    return 1;
+
+  p = (unsigned long *) &n;
+  if ((unsigned long) p < L2_START || (unsigned long) p >= L2_START + L2_LENGTH)
+    return 2;
+
+  if (foo (0) != 1)
+    return 3;
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/longcall-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/longcall-1.c
new file mode 100644
index 000000000..138707e9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/longcall-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile { target bfin-*-* } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "call\[^\\n\]*foo" } } */
+/* { dg-final { scan-assembler-not "jump\[^\\n\]*foo" } } */
+/* { dg-final { scan-assembler "call\[^\\n\]*baz" } } */
+/* { dg-final { scan-assembler "jump\[^\\n\]*baz" } } */
+/* { dg-final { scan-assembler "call\[^\\n\]*bar" } } */
+/* { dg-final { scan-assembler "jump\[^\\n\]*bar" } } */
+
+extern void foo () __attribute__((longcall));
+extern void bar () __attribute__((shortcall));
+extern void baz ();
+
+int t1 ()
+{
+    foo ();
+    bar ();
+    baz ();
+    return 4;
+}
+
+void t2 ()
+{
+    foo ();
+}
+void t3 ()
+{
+    bar ();
+}
+void t4 ()
+{
+    baz ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/longcall-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/longcall-2.c
new file mode 100644
index 000000000..33189b01f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/longcall-2.c
@@ -0,0 +1,33 @@
+/* { dg-do compile { target bfin-*-* } } */
+/* { dg-options "-O2 -mlong-calls" } */
+/* { dg-final { scan-assembler-not "call\[^\\n\]*foo" } } */
+/* { dg-final { scan-assembler-not "jump\[^\\n\]*foo" } } */
+/* { dg-final { scan-assembler-not "call\[^\\n\]*baz" } } */
+/* { dg-final { scan-assembler-not "jump\[^\\n\]*baz" } } */
+/* { dg-final { scan-assembler "call\[^\\n\]*bar" } } */
+/* { dg-final { scan-assembler "jump\[^\\n\]*bar" } } */
+
+extern void foo () __attribute__((longcall));
+extern void bar () __attribute__((shortcall));
+extern void baz ();
+
+int t1 ()
+{
+    foo ();
+    bar ();
+    baz ();
+    return 4;
+}
+
+void t2 ()
+{
+    foo ();
+}
+void t3 ()
+{
+    bar ();
+}
+void t4 ()
+{
+    baz ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/loop-autoinc.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/loop-autoinc.c
new file mode 100644
index 000000000..3dc718298
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/loop-autoinc.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler " = \\\[\[PI\].\\+\\+\\\];" } } */
+extern int x[];
+extern void bar();
+int foo ()
+{
+  int i;
+  int sum = 0;
+  for (i = 0; i < 100; i++) {
+    sum += x[i];
+    if (sum & 1)
+      sum *= sum;
+  }
+  return sum;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c
new file mode 100644
index 000000000..fa2d56d1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf512.c
@@ -0,0 +1,31 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf512" } */
+
+#ifndef __ADSPBF512__
+#error "__ADSPBF512__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c
new file mode 100644
index 000000000..f6c082911
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf514.c
@@ -0,0 +1,31 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf514" } */
+
+#ifndef __ADSPBF514__
+#error "__ADSPBF514__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c
new file mode 100644
index 000000000..439b3f40e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf516.c
@@ -0,0 +1,31 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf516" } */
+
+#ifndef __ADSPBF516__
+#error "__ADSPBF516__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c
new file mode 100644
index 000000000..aff7f6989
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf518.c
@@ -0,0 +1,31 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf518" } */
+
+#ifndef __ADSPBF518__
+#error "__ADSPBF518__ is not defined"
+#endif
+
+#ifndef __ADSPBF51x__
+#error "__ADSPBF51x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
new file mode 100644
index 000000000..58c325e0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf522.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf522" } */
+
+#ifndef __ADSPBF522__
+#error "__ADSPBF522__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
new file mode 100644
index 000000000..10f71eddb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf523.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf523" } */
+
+#ifndef __ADSPBF523__
+#error "__ADSPBF523__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
new file mode 100644
index 000000000..d8e30c4f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf524.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf524" } */
+
+#ifndef __ADSPBF524__
+#error "__ADSPBF524__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
new file mode 100644
index 000000000..0e021e46f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf525.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf525" } */
+
+#ifndef __ADSPBF525__
+#error "__ADSPBF525__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
new file mode 100644
index 000000000..e3e248a9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf526.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf526" } */
+
+#ifndef __ADSPBF526__
+#error "__ADSPBF526__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
new file mode 100644
index 000000000..41f493114
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf527.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf527" } */
+
+#ifndef __ADSPBF527__
+#error "__ADSPBF527__ is not defined"
+#endif
+
+#ifndef __ADSPBF52x__
+#error "__ADSPBF52x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0002
+#error "__SILICON_REVISION__ is not 0x0002"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf531.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf531.c
new file mode 100644
index 000000000..ebcf39822
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf531.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf531" } */
+
+#ifndef __ADSPBF531__
+#error "__ADSPBF531__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0006
+#error "__SILICON_REVISION__ is not 0x0006"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0005
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf532.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf532.c
new file mode 100644
index 000000000..18ff74a4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf532.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf532" } */
+
+#ifndef __ADSPBF532__
+#error "__ADSPBF532__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0006
+#error "__SILICON_REVISION__ is not 0x0006"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0005
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf533.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf533.c
new file mode 100644
index 000000000..d961d7a72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf533.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf533" } */
+
+#ifndef __ADSPBF533__
+#error "__ADSPBF533__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0006
+#error "__SILICON_REVISION__ is not 0x0006"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0005
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf534.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf534.c
new file mode 100644
index 000000000..cd354596d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf534.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf534" } */
+
+#ifndef __ADSPBF534__
+#error "__ADSPBF534__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf536.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf536.c
new file mode 100644
index 000000000..0ac9ebf9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf536.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf536" } */
+
+#ifndef __ADSPBF536__
+#error "__ADSPBF536__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf537.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf537.c
new file mode 100644
index 000000000..66a87c045
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf537.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf538.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf538.c
new file mode 100644
index 000000000..188f8708c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf538.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf538" } */
+
+#ifndef __ADSPBF538__
+#error "__ADSPBF538__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0005
+#error "__SILICON_REVISION__ is not 0x0005"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0004
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf539.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf539.c
new file mode 100644
index 000000000..acb0d8936
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf539.c
@@ -0,0 +1,33 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf539" } */
+
+#ifndef __ADSPBF539__
+#error "__ADSPBF539__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0005
+#error "__SILICON_REVISION__ is not 0x0005"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0004
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
new file mode 100644
index 000000000..c8999713d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf542.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf542" } */
+
+#ifndef __ADSPBF542__
+#error "__ADSPBF542__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0004
+#error "__SILICON_REVISION__ is not 0x0004"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf542m.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf542m.c
new file mode 100644
index 000000000..74d377045
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf542m.c
@@ -0,0 +1,41 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf542m" } */
+
+#ifndef __ADSPBF542__
+#error "__ADSPBF542__ is not defined"
+#endif
+
+#ifndef __ADSPBF542M__
+#error "__ADSPBF542M__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
new file mode 100644
index 000000000..926978505
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf544.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf544" } */
+
+#ifndef __ADSPBF544__
+#error "__ADSPBF544__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0004
+#error "__SILICON_REVISION__ is not 0x0004"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf544m.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf544m.c
new file mode 100644
index 000000000..a0289378c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf544m.c
@@ -0,0 +1,41 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf544m" } */
+
+#ifndef __ADSPBF544__
+#error "__ADSPBF544__ is not defined"
+#endif
+
+#ifndef __ADSPBF544M__
+#error "__ADSPBF544M__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
new file mode 100644
index 000000000..8f724335c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf547.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf547" } */
+
+#ifndef __ADSPBF547__
+#error "__ADSPBF547__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0004
+#error "__SILICON_REVISION__ is not 0x0004"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf547m.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf547m.c
new file mode 100644
index 000000000..e5e1f9b30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf547m.c
@@ -0,0 +1,41 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf547m" } */
+
+#ifndef __ADSPBF547__
+#error "__ADSPBF547__ is not defined"
+#endif
+
+#ifndef __ADSPBF547M__
+#error "__ADSPBF547M__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
new file mode 100644
index 000000000..7b1d2ff2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf548.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf548" } */
+
+#ifndef __ADSPBF548__
+#error "__ADSPBF548__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0004
+#error "__SILICON_REVISION__ is not 0x0004"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf548m.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf548m.c
new file mode 100644
index 000000000..47afafffe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf548m.c
@@ -0,0 +1,41 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf548m" } */
+
+#ifndef __ADSPBF548__
+#error "__ADSPBF548__ is not defined"
+#endif
+
+#ifndef __ADSPBF548M__
+#error "__ADSPBF548M__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
new file mode 100644
index 000000000..83c79de3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf549.c
@@ -0,0 +1,37 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf549" } */
+
+#ifndef __ADSPBF549__
+#error "__ADSPBF549__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0004
+#error "__SILICON_REVISION__ is not 0x0004"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf549m.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf549m.c
new file mode 100644
index 000000000..8aa7ad560
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf549m.c
@@ -0,0 +1,41 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf549m" } */
+
+#ifndef __ADSPBF549__
+#error "__ADSPBF549__ is not defined"
+#endif
+
+#ifndef __ADSPBF549M__
+#error "__ADSPBF549M__ is not defined"
+#endif
+
+#ifndef __ADSPBF54x__
+#error "__ADSPBF54x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#if __SILICON_REVISION__ <= 0x0001
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+#else
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf561.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf561.c
new file mode 100644
index 000000000..e2eab3ba3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf561.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf561" } */
+
+#ifndef __ADSPBF561__
+#error "__ADSPBF561__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0005
+#error "__SILICON_REVISION__ is not 0x0005"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf592.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf592.c
new file mode 100644
index 000000000..27e865e55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-bf592.c
@@ -0,0 +1,31 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf592" } */
+
+#ifndef __ADSPBF592__
+#error "__ADSPBF592__ is not defined"
+#endif
+
+#ifndef __ADSPBF59x__
+#error "__ADSPBF59x__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0001
+#error "__SILICON_REVISION__ is not 0x0001"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-default.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-default.c
new file mode 100644
index 000000000..9109701cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mcpu-default.c
@@ -0,0 +1,93 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "" } */
+
+#ifdef __ADSPBF522__
+#error "__ADSPBF522__ is defined"
+#endif
+#ifdef __ADSPBF523__
+#error "__ADSPBF523__ is defined"
+#endif
+#ifdef __ADSPBF524__
+#error "__ADSPBF524__ is defined"
+#endif
+#ifdef __ADSPBF525__
+#error "__ADSPBF525__ is defined"
+#endif
+#ifdef __ADSPBF526__
+#error "__ADSPBF526__ is defined"
+#endif
+#ifdef __ADSPBF527__
+#error "__ADSPBF527__ is defined"
+#endif
+
+
+#ifdef __ADSPBF531__
+#error "__ADSPBF531__ is defined"
+#endif
+#ifdef __ADSPBF532__
+#error "__ADSPBF532__ is defined"
+#endif
+#ifdef __ADSPBF533__
+#error "__ADSPBF533__ is defined"
+#endif
+#ifdef __ADSPBF534__
+#error "__ADSPBF534__ is defined"
+#endif
+#ifdef __ADSPBF536__
+#error "__ADSPBF536__ is defined"
+#endif
+#ifdef __ADSPBF537__
+#error "__ADSPBF537__ is defined"
+#endif
+#ifdef __ADSPBF538__
+#error "__ADSPBF538__ is defined"
+#endif
+#ifdef __ADSPBF539__
+#error "__ADSPBF539__ is defined"
+#endif
+
+#ifdef __ADSPBF542__
+#error "__ADSPBF542__ is defined"
+#endif
+#ifdef __ADSPBF544__
+#error "__ADSPBF544__ is defined"
+#endif
+#ifdef __ADSPBF547__
+#error "__ADSPBF547__ is defined"
+#endif
+#ifdef __ADSPBF548__
+#error "__ADSPBF548__ is defined"
+#endif
+#ifdef __ADSPBF549__
+#error "__ADSPBF548__ is defined"
+#endif
+
+#ifdef __ADSPBF561__
+#error "__ADSPBF561__ is defined"
+#endif
+
+
+#ifndef __SILICON_REVISION__
+#error "__SILICON_REVISION__ is not defined"
+#else
+#if __SILICON_REVISION__ != 0xffff
+#error "__SILICON_REVISION__ is not 0xFFFF"
+#endif
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is not defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/mul-combine.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mul-combine.c
new file mode 100644
index 000000000..2a811b332
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/mul-combine.c
@@ -0,0 +1,45 @@
+/* Make sure combine eliminates all unnecessary instructions for the
+   sixteen cases of hi/lo multiplications.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "<<" } } */
+/* { dg-final { scan-assembler-not "PACK" } } */
+
+extern void abort (void);
+extern void exit (int);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+#define GETVECT(HILO1,HILO2,IN1,IN2)					\
+  __builtin_bfin_compose_2x16 ((HILO2) ? __builtin_bfin_extract_hi (IN1) : __builtin_bfin_extract_lo (IN1), \
+			  (HILO1) ? __builtin_bfin_extract_hi (IN2) : __builtin_bfin_extract_lo (IN2))
+#define DOTEST(IN1, IN2, HL1, HL2, HL3, HL4)					\
+  __builtin_bfin_multr_fr2x16 (GETVECT (HL1, HL2, IN1, IN1), \
+			  GETVECT (HL3, HL4, IN2, IN2))
+
+#define FUNC(HL1, HL2, HL3, HL4) \
+  fract2x16 foo ## HL1 ## HL2 ## HL3 ## HL4 (fract2x16 a, fract2x16 b)\
+  { \
+    return DOTEST(a, b, HL1, HL2, HL3, HL4);\
+  }
+
+FUNC (0, 0, 0, 0)
+FUNC (1, 0, 0, 0)
+FUNC (0, 1, 0, 0)
+FUNC (1, 1, 0, 0)
+FUNC (0, 0, 1, 0)
+FUNC (1, 0, 1, 0)
+FUNC (0, 1, 1, 0)
+FUNC (1, 1, 1, 0)
+FUNC (0, 0, 0, 1)
+FUNC (1, 0, 0, 1)
+FUNC (0, 1, 0, 1)
+FUNC (1, 1, 0, 1)
+FUNC (0, 0, 1, 1)
+FUNC (1, 0, 1, 1)
+FUNC (0, 1, 1, 1)
+FUNC (1, 1, 1, 1)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/saveall.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/saveall.c
new file mode 100644
index 000000000..19f9decd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/saveall.c
@@ -0,0 +1,14 @@
+/* { dg-do run { target bfin*-*-* } } */
+/* { dg-options "-fomit-frame-pointer" } */
+
+void foo (void) __attribute__ ((saveall));
+void foo ()
+{
+  asm ("R0 = 0; RETS = R0;");
+}
+
+int main ()
+{
+  foo ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/shift.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/shift.c
new file mode 100644
index 000000000..4a0e9175c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/shift.c
@@ -0,0 +1,73 @@
+extern void abort (void);
+extern void exit (int);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+typedef __v2hi fract2x16;
+typedef short fract16;
+
+int main ()
+{
+  fract2x16 a, b, c, d;
+  fract16 t1, t2;
+  a = __builtin_bfin_compose_2x16 (0xe005, 0x1000);
+  b = __builtin_bfin_compose_2x16 (0x7000, 0x5000);
+  c = __builtin_bfin_compose_2x16 (0x7000, 0xc000);
+
+  d = __builtin_bfin_shl_fr2x16 (c, 2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if ((unsigned short)t1 != 0x8000 || t2 != 0x7fff)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (c, -2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if ((unsigned short)t1 != 0xf000 || t2 != 0x1c00)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (a, 2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x4000 || (unsigned short)t2 != 0x8014)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (c, -4);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if ((unsigned short)t1 != 0xfc00 || t2 != 0x0700)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (c, 2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if ((unsigned short)t1 != 0x8000 || t2 != 0x7fff)
+    abort ();
+
+  d = __builtin_bfin_shl_fr2x16 (a, -2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x0400 || (unsigned short)t2 != 0xf801)
+    abort ();
+
+  /* lsh */
+  d = __builtin_bfin_lshl_fr2x16 (c, -4);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x0c00 || t2 != 0x0700)
+    abort ();
+
+  d = __builtin_bfin_lshl_fr2x16 (c, 2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x0000 || t2 != -0x4000)
+    abort ();
+
+  d = __builtin_bfin_lshl_fr2x16 (a, -2);
+  t1 = __builtin_bfin_extract_lo (d);
+  t2 = __builtin_bfin_extract_hi (d);
+  if (t1 != 0x0400 || (unsigned short)t2 != 0x3801)
+    abort ();
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/wmul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/wmul-1.c
new file mode 100644
index 000000000..f17fc199e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/wmul-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int mac(const short *a, const short *b, int sqr, int *sum)
+{
+  int i;
+  int dotp = *sum;
+
+  for (i = 0; i < 150; i++) {
+    dotp += b[i] * a[i];
+    sqr += b[i] * b[i];
+  }
+
+  *sum = dotp;
+  return sqr;
+}
+
+/* { dg-final { scan-assembler-times "\\(IS\\)" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/wmul-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/wmul-2.c
new file mode 100644
index 000000000..2f2d2527e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/wmul-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void vec_mpy(int y[], const short x[], short scaler)
+{
+ int i;
+
+ for (i = 0; i < 150; i++)
+   y[i] += ((scaler * x[i]) >> 31);
+}
+
+/* { dg-final { scan-assembler-times "\\(IS\\)" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-1.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-1.c
new file mode 100644
index 000000000..53ca1d7b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-1.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcsync-anomaly -mcpu=bf537" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-2.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-2.c
new file mode 100644
index 000000000..c639a204e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-2.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mno-specld-anomaly -mcpu=bf537" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0x0003
+#error "__SILICON_REVISION__ is not 0x0003"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-3.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-3.c
new file mode 100644
index 000000000..3209f2348
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-3.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537-none" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#ifdef __SILICON_REVISION__
+#error "__SILICON_REVISION__ is defined"
+#endif
+
+#ifdef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-4.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-4.c
new file mode 100644
index 000000000..62bd382b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-4.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537-any" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0xffff
+#error "__SILICON_REVISION__ is not 0xffff"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-any.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-any.c
new file mode 100644
index 000000000..62bd382b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-any.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537-any" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#if __SILICON_REVISION__ != 0xffff
+#error "__SILICON_REVISION__ is not 0xffff"
+#endif
+
+#ifndef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is not defined"
+#endif
+
+#ifndef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is not defined"
+#endif
+
+#ifndef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-none.c b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-none.c
new file mode 100644
index 000000000..3209f2348
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/bfin/workarounds-none.c
@@ -0,0 +1,27 @@
+/* Test for -mcpu=.  */
+/* { dg-do preprocess } */
+/* { dg-bfin-options "-mcpu=bf537-none" } */
+
+#ifndef __ADSPBF537__
+#error "__ADSPBF537__ is not defined"
+#endif
+
+#ifdef __SILICON_REVISION__
+#error "__SILICON_REVISION__ is defined"
+#endif
+
+#ifdef __WORKAROUNDS_ENABLED
+#error "__WORKAROUNDS_ENABLED is defined"
+#endif
+
+#ifdef __WORKAROUND_RETS
+#error "__WORKAROUND_RETS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_LOADS
+#error "__WORKAROUND_SPECULATIVE_LOADS is defined"
+#endif
+
+#ifdef __WORKAROUND_SPECULATIVE_SYNCS
+#error "__WORKAROUND_SPECULATIVE_SYNCS is defined"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/20011127-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/20011127-1.c
new file mode 100644
index 000000000..298a8b9fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/20011127-1.c
@@ -0,0 +1,29 @@
+/* Copyright (C) 2001, 2007  Free Software Foundation.
+   by Hans-Peter Nilsson  <hp@axis.com>
+
+   Making sure that invalid asm operand modifiers don't cause an ICE.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-message "reg:SI|const_double:DF" "prune debug_rtx output" { target *-*-* } 0 } */
+
+void
+foo (void)
+{
+  /* The first case symbolizes the default case for CRIS.  */
+  asm ("\n;# %w0" : : "r" (0));	/* { dg-error "modifier" } */
+
+  /* These are explicit cases.  Luckily, a register is invalid in most of
+     them.  */
+  asm ("\n;# %b0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %v0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %p0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %z0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %H0" : : "F" (0.5));	/* { dg-error "modifier" } */
+  asm ("\n;# %e0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %m0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %A0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %D0" : : "r" (0));		/* { dg-error "modifier" } */
+  asm ("\n;# %T0" : : "r" (0));		/* { dg-error "modifier" } */
+  /* Add more must-not-ICE asm errors here as we find them ICEing.  */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-b-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-b-1.c
new file mode 100644
index 000000000..5417c047d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-b-1.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+/* Checking that the "b" constraint is accepted, for all target variants.  */
+
+long sys_ipc (void)
+{
+  long __gu_err = -14;
+  long dummy_for_get_user_asm_64_;
+  __asm__ __volatile__( "move.d [%1+],%0\n"
+			: "=r" (__gu_err), "=b" (dummy_for_get_user_asm_64_)
+			: "0" (__gu_err));
+
+  return __gu_err;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-other.S b/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-other.S
new file mode 100644
index 000000000..4fe7ebfc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-other.S
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can assemble for the "other" variant, with the twist
+   that the gcc option -march=v0 isn't valid for the assembler.  */
+        .text
+#if OTHER_ISA == 32
+	addoq 42,$r1,$acr
+#else
+0:
+	move.d [$r2=$r0+42],$r1
+	bwf 0b
+	nop
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-v10.S b/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-v10.S
new file mode 100644
index 000000000..c85ebe293
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-v10.S
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized.  */
+
+#include "asm-other.S"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-v8.S b/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-v8.S
new file mode 100644
index 000000000..3fba31884
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/asm-v8.S
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized.  */
+
+#include "asm-other.S"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/asmreg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/asmreg-1.c
new file mode 100644
index 000000000..f430fafbe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/asmreg-1.c
@@ -0,0 +1,73 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "\\\.ifnc \\\$r9-\\\$r10-\\\$r11-\\\$r12" } } */
+
+/* Sanity check for asm register operands in syscall failed for
+   cris-axis-linux-gnu due to regmove bug.
+   Hans-Peter Nilsson <hp@axis.com>.  */
+
+extern void lseek64 (int, long long, int);
+extern int *__errno_location (void);
+struct dirent64
+{
+  long long d_off;
+  unsigned short int d_reclen;
+  char d_name[256];
+};
+struct kernel_dirent64
+{   
+  long long d_off;
+  unsigned short d_reclen;
+  char d_name[256];
+};
+
+static inline int __attribute__ ((__always_inline__))
+__syscall_getdents64 (int fd, char * dirp, unsigned count)
+{
+  register unsigned long __sys_res asm ("r10");
+  register unsigned long __r10 __asm__ ("r10") = (unsigned long) fd;
+  register unsigned long __r11 __asm__ ("r11") = (unsigned long) dirp;
+  register unsigned long __r12 __asm__ ("r12") = (unsigned long) count;
+  register unsigned long __callno asm ("r9") = (220);
+  asm volatile (".ifnc %1-%0-%3-%4,$r9-$r10-$r11-$r12\n\t"
+		".err\n\t"
+		".endif\n\t"
+		"break 13"
+		: "=r" (__sys_res)
+		: "r" (__callno), "0" (__r10), "r" (__r11), "r" (__r12)
+		: "memory");
+  if (__sys_res >= (unsigned long) -4096)
+    {
+      (*__errno_location ()) = - __sys_res;
+      __sys_res = -1;
+    }
+  return __sys_res;
+}
+
+int
+__getdents64 (int fd, char *buf, unsigned nbytes)
+{   
+  struct dirent64 *dp;
+  long long last_offset = -1;
+  int retval;
+  struct kernel_dirent64 *skdp, *kdp;
+  dp = (struct dirent64 *) buf;
+  skdp = kdp = __builtin_alloca (nbytes);
+  retval = __syscall_getdents64(fd, (char *)kdp, nbytes);
+  if (retval == -1)
+    return -1;
+  while ((char *) kdp < (char *) skdp + retval)
+    {
+      if ((char *) dp > buf + nbytes)
+	{
+	  lseek64(fd, last_offset, 0);
+	  break;
+	}
+      last_offset = kdp->d_off;
+      __builtin_memcpy (dp->d_name, kdp->d_name, kdp->d_reclen - 10);
+      dp = (struct dirent64 *) ((char *) dp + sizeof (*dp));
+      kdp = (struct kernel_dirent64 *) (((char *) kdp) + kdp->d_reclen);
+    }
+
+  return (char *) dp - buf;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/biap.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/biap.c
new file mode 100644
index 000000000..1f3b4368a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/biap.c
@@ -0,0 +1,11 @@
+/* Make sure ADDI is combined and emitted successfully.
+   See also PR37939.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "addi" } } */
+/* { dg-final { scan-assembler-not "lsl" } } */
+
+int xyzzy (int r10, int r11)
+{
+  return r11 * 4 + r10;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c
new file mode 100644
index 000000000..1230d4b59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_bswap_v3.c
@@ -0,0 +1,12 @@
+/* Check that we don't use the swap insn for bswap by checking assembler 
+   output.  The swap instruction was added in v8.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v3" } */
+/* { dg-final { scan-assembler-not "\[ \t\]swapwb\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_bswap32(a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c
new file mode 100644
index 000000000..b7a8d2684
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_bswap_v8.c
@@ -0,0 +1,12 @@
+/* Check that we use the swap insn for bswap by checking assembler
+   output.  The swap instruction was added in v8.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v8" } */
+/* { dg-final { scan-assembler "\[ \t\]swapwb\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_bswap32(a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_clz_v0.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_clz_v0.c
new file mode 100644
index 000000000..318402faa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_clz_v0.c
@@ -0,0 +1,12 @@
+/* Check that we don't use the lz insn for clz by checking assembler output.
+   The lz insn was implemented in CRIS v3 (ETRAX 4).  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v0" } */
+/* { dg-final { scan-assembler-not "\[ \t\]lz\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_clz(a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_clz_v3.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_clz_v3.c
new file mode 100644
index 000000000..ecf039048
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_clz_v3.c
@@ -0,0 +1,12 @@
+/* Check that we use the lz insn for clz by checking assembler output.
+   The lz insn was implemented in CRIS v3 (ETRAX 4).  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v3" } */
+/* { dg-final { scan-assembler "\[ \t\]lz\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_clz(a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c
new file mode 100644
index 000000000..8971a47a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_ctz_v3.c
@@ -0,0 +1,12 @@
+/* Check that we don't use the swap insn for ctz by checking
+   assembler output.  The swap instruction was implemented in v8.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v3" } */
+/* { dg-final { scan-assembler-not "\[ \t\]swapwbr\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_ctz(a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c
new file mode 100644
index 000000000..853b1740a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/builtin_ctz_v8.c
@@ -0,0 +1,12 @@
+/* Check that we use the swap insn for ctz by checking assembler output.
+   The swap instruction was implemented in v8.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
+/* { dg-options "-O2 -march=v8" } */
+/* { dg-final { scan-assembler "\[ \t\]swapwbr\[ \t\]" } } */
+
+int
+f (int a)
+{
+	return __builtin_ctz(a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/cris.exp b/gcc-4.9/gcc/testsuite/gcc.target/cris/cris.exp
new file mode 100644
index 000000000..4a04d1920
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/cris.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `gcc-dg.exp' driver, just a single option, no
+# looping over tests.
+
+# Exit immediately if this isn't a CRIS target.
+if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] "" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-other.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-other.c
new file mode 100644
index 000000000..c1c043f56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-other.c
@@ -0,0 +1,23 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can (generate code and) assemble for the "other"
+   variant, with the twist that the gcc option -march=v0 isn't
+   valid for the assembler.  We don't check that the generated code
+   is for the other variant; other tests cover that already, but they
+   don't *assemble* the result.  We can't trust the prologue and
+   epilogue to contain incompatible insns (they actually deliberately
+   don't, usually and it'd be brittle to tweak the function signature
+   to make it so), so we force some with inline asm.  */
+
+void f(void)
+{
+#if OTHER_ISA == 32
+  asm volatile ("addoq 42,$r11,$acr");
+#else
+  asm volatile ("0: move.d [$r12=$sp+42],$r10\n\t"
+		"bwf 0b\n\t"
+		"nop");
+#endif
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-v10.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-v10.c
new file mode 100644
index 000000000..75379b3c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-v10.c
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized.  */
+
+#include "inasm-other.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-v8.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-v8.c
new file mode 100644
index 000000000..b2fb3053c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/inasm-v8.c
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized.  */
+
+#include "inasm-other.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-andu1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-andu1.c
new file mode 100644
index 000000000..3b54c3295
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-andu1.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-not "and.d " } } */
+/* { dg-final { scan-assembler-not "move.d " } } */
+/* { dg-final { scan-assembler "cLear.b" } } */
+/* { dg-final { scan-assembler "movu.b" } } */
+/* { dg-final { scan-assembler "and.b" } } */
+/* { dg-final { scan-assembler "movu.w" } } */
+/* { dg-final { scan-assembler "and.w" } } */
+/* { dg-final { scan-assembler "andq" } } */
+/* { dg-options "-O2" } */
+
+/* Test the "andu" peephole2 trivially, memory operand.  */
+
+int
+clearb (int x, int *y)
+{
+  return *y & 0xff00;
+}
+
+int
+andb (int x, int *y)
+{
+  return *y & 0x3f;
+}
+
+int
+andw (int x, int *y)
+{
+  return *y & 0xfff;
+}
+
+int
+andq (int x, int *y)
+{
+  return *y & 0xf0;
+}
+
+int
+andq2 (int x, int *y)
+{
+  return *y & 0xfff0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-andu2.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-andu2.c
new file mode 100644
index 000000000..fd19cdd90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-andu2.c
@@ -0,0 +1,39 @@
+/* { dg-do assemble } */
+/* { dg-final { scan-assembler "movu.w \\\$r10,\\\$|movu.w 2047," } } */
+/* { dg-final { scan-assembler "and.w 2047,\\\$|and.d \\\$r10," } } */
+/* { dg-final { scan-assembler-not "move.d \\\$r10,\\\$" } } */
+/* { dg-final { scan-assembler "movu.b \\\$r10,\\\$|movu.b 95," } } */
+/* { dg-final { scan-assembler "and.b 95,\\\$|and.d \\\$r10," } } */
+/* { dg-final { scan-assembler "andq -2,\\\$" } } */
+/* { dg-final { scan-assembler-not "movu.b 254,\\\$" } } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Originally used to test the "andu" peephole2 trivially, register operand.
+   Due to reload changes (r186861), the suboptimal sequence isn't
+   generated and the peephole2 doesn't trig for this trivial code
+   anymore.  Another minimal sequence is generated, where the constant
+   is loaded to a free register first.  Instead another case is exposed;
+   handled by the "andqu" peephole2, trigged by and_peep2_q (the andq
+   and scan-assembler-not-movu.b lines above).  */
+
+unsigned int
+and_peep2_hi (unsigned int y, unsigned int *x)
+{
+  *x = y & 0x7ff;
+  return y;
+}
+
+unsigned int
+and_peep2_qi (unsigned int y, unsigned int *x)
+{
+  *x = y & 0x5f;
+  return y;
+}
+
+
+unsigned int
+and_peep2_q (unsigned int y, unsigned int *x)
+{
+  *x = y & 0xfe;
+  return y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-xsrand.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-xsrand.c
new file mode 100644
index 000000000..df0e76886
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-xsrand.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "and.w " } } */
+/* { dg-final { scan-assembler "and.b " } } */
+/* { dg-final { scan-assembler-not "and.d" } } */
+/* { dg-options "-O2" } */
+
+/* Test the "asrandb", "asrandw", "lsrandb" and "lsrandw" peephole2:s
+   trivially.  */
+
+unsigned int
+andwlsr (unsigned int x)
+{
+  return (x >> 17) & 0x7ff;
+}
+
+unsigned int
+andblsr (unsigned int x)
+{
+  return (x >> 25) & 0x5f;
+}
+
+int
+andwasr (int x)
+{
+  return (x >> 17) & 0x7ff;
+}
+
+int
+andbasr (int x)
+{
+  return (x >> 25) & 0x5f;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-xsrand2.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-xsrand2.c
new file mode 100644
index 000000000..5d6ca788d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/peep2-xsrand2.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "and.w -137," } } */
+/* { dg-final { scan-assembler "and.b -64," } } */
+/* { dg-final { scan-assembler "and.w -139," } } */
+/* { dg-final { scan-assembler "and.b -63," } } */
+/* { dg-final { scan-assembler-not "and.d" } } */
+/* { dg-options "-O2" } */
+
+/* PR target/17984.  Test-case based on
+   testsuite/gcc.dg/cris-peep2-xsrand.c.  */
+
+unsigned int
+andwlsr (unsigned int x)
+{
+  return (x >> 16) & 0xff77;
+}
+
+unsigned int
+andblsr (unsigned int x)
+{
+  return (x >> 24) & 0xc0;
+}
+
+int
+andwasr (int x)
+{
+  return (x >> 16) & 0xff75;
+}
+
+int
+andbasr (int x)
+{
+  return (x >> 24) & 0xc1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/rld-legit1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/rld-legit1.c
new file mode 100644
index 000000000..53a38af2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/rld-legit1.c
@@ -0,0 +1,21 @@
+/* Check that we don't get unnecessary insns due to reload using more
+   insns than needed due to reloading of more locations than
+   needed.  */
+/* { dg-options -O2 } */
+/* { dg-final { scan-assembler-not "movs.w" } } */
+/* { dg-final { scan-assembler-not "move.w" } } */
+
+/* As torture/pr24750-2.c, except we need to clobber R8 for thorough
+   testing and know we can do, since we replace the frame-pointer.  */
+
+int
+f (short *a, char *y)
+{
+  __asm__ ("" : : :
+#ifndef __PIC__
+	   "r0",
+#endif
+	   "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
+	   "r9", "r10", "r11", "r12", "r13");
+  return y[*a];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/rld-legit2.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/rld-legit2.c
new file mode 100644
index 000000000..0add3e2b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/rld-legit2.c
@@ -0,0 +1,16 @@
+/* A variant of rld-legit1.c only for full code coverage of the
+   initial version of cris_reload_address_legitimized.  */
+/* { dg-options -O2 } */
+
+short *
+g (short *a, char *y)
+{
+  __asm__ ("" : : :
+#ifndef __PIC__
+	   "r0",
+#endif
+	   "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
+	   "r9", "r10", "r11", "r12", "r13");
+  y[*a++] = 0;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1-v10.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1-v10.c
new file mode 100644
index 000000000..6c8dd1a40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1-v10.c
@@ -0,0 +1,5 @@
+/* Check that we can assemble both base atomic variants.  */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -march=v10" } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1-v32.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1-v32.c
new file mode 100644
index 000000000..3c1d076ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1-v32.c
@@ -0,0 +1,5 @@
+/* Check that we can assemble both base atomic variants.  */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -march=v32" } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1.c
new file mode 100644
index 000000000..1bc9a674c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-1.c
@@ -0,0 +1,35 @@
+/* Check that we can assemble both base atomic variants, for v0.  */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -march=v0" } */
+
+#ifndef type
+#define type char
+#endif
+
+#if !defined(op) && !defined(xchg)
+#define op 1
+#define xchg 1
+#endif
+
+#ifndef op
+#define op 0
+#endif
+
+#ifndef xchg
+#define xchg 0
+#endif
+
+#if op
+int sfa (type *p, type *q, int a)
+{
+  return __atomic_fetch_nand (p, a, __ATOMIC_ACQ_REL)
+    + __atomic_fetch_add (q, a, __ATOMIC_SEQ_CST);
+}
+#endif
+
+#if xchg
+void acen (type *ptr, type *val, type *ret)
+{
+  __atomic_exchange (ptr, val, ret, __ATOMIC_SEQ_CST);
+}
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2c.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2c.c
new file mode 100644
index 000000000..80e646c20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2c.c
@@ -0,0 +1,8 @@
+/* Check that we don't get alignment-checking code, char.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\tbreak\[ \t\]" } } */
+/* { dg-final { scan-assembler-not "\tbtstq\[ \t\]\[^5\]" } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+/* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2i.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2i.c
new file mode 100644
index 000000000..d491d3c08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2i.c
@@ -0,0 +1,10 @@
+/* Check that we get the expected alignment-checking code, op variant, int.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Dop -Dtype=int" } */
+/* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+/* { dg-final { scan-assembler "\tbreak 8" } } */
+/* { dg-final { scan-assembler "\tbtstq \\(2-1\\)," } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+/* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2s.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2s.c
new file mode 100644
index 000000000..06ff98a27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-2s.c
@@ -0,0 +1,10 @@
+/* Check that we get the expected alignment-checking code, op variant, short.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Dop -Dtype=short" } */
+/* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+/* { dg-final { scan-assembler "\tbreak 8" } } */
+/* { dg-final { scan-assembler "\tbtstq \\(1-1\\)," } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+/* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-3i.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-3i.c
new file mode 100644
index 000000000..9e67d61cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-3i.c
@@ -0,0 +1,12 @@
+/* Check that we get the expected alignment-checking code, xchg variant, int.
+   Unfortunately, PRE moves the "and" to a different BB, so combine doesn't
+   see it with the compare to make it a btstq.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Dxchg -Dtype=int" } */
+/* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+/* { dg-final { scan-assembler "\tbreak 8" } } */
+/* { dg-final { scan-assembler "\tbtstq \\(2-1\\)," { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-not "\tand" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-3s.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-3s.c
new file mode 100644
index 000000000..8e87a3b62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-3s.c
@@ -0,0 +1,12 @@
+/* Check that we get the expected alignment-checking code, xchg variant, short.
+   Unfortunately, PRE moves the "and" to a different BB, so combine doesn't
+   see it with the compare to make it a btstq.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Dxchg -Dtype=short" } */
+/* { dg-additional-options "-mtrap-using-break8 -mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+/* { dg-final { scan-assembler "\tbreak 8" } } */
+/* { dg-final { scan-assembler "\tbtstq \\(1-1\\)," { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-not "\tand" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4c.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4c.c
new file mode 100644
index 000000000..e8cb69267
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4c.c
@@ -0,0 +1,8 @@
+/* Check that we get don't alignment-checking code, xchg variant, char.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-trap-unaligned-atomic" } */
+/* { dg-final { scan-assembler-not "\tbreak\[ \t\]" } } */
+/* { dg-final { scan-assembler-not "\tbtstq\[ \t\]\[^5\]" } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+/* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4i.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4i.c
new file mode 100644
index 000000000..78a7012cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4i.c
@@ -0,0 +1,9 @@
+/* Check that we don't get alignment-checking code, int.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Dtype=int -mno-trap-unaligned-atomic" } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+/* { dg-final { scan-assembler-not "\tbreak\[ \t\]" } } */
+/* { dg-final { scan-assembler-not "\tbtstq\[ \t\]\[^5\]" } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+/* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4s.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4s.c
new file mode 100644
index 000000000..6691a4828
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-4s.c
@@ -0,0 +1,9 @@
+/* Check that we don't get alignment-checking code, short.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Dtype=short -mno-trap-unaligned-atomic" } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+/* { dg-final { scan-assembler-not "\tbreak\[ \t\]" } } */
+/* { dg-final { scan-assembler-not "\tbtstq\[ \t\]\[^5\]" } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+/* { dg-final { scan-assembler-not "\t\[jb\]sr" } } */
+#include "sync-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-xchg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-xchg-1.c
new file mode 100644
index 000000000..21bb7d4ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/sync-xchg-1.c
@@ -0,0 +1,21 @@
+/* Check that the basic library call variant is sane; no other calls, no
+   checks compares or branches.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -munaligned-atomic-may-use-library" } */
+/* { dg-final { scan-assembler-not "\tdi" } } */
+/* { dg-final { scan-assembler-not "\tbtstq" } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+/* { dg-final { scan-assembler-not "\tclearf" } } */
+/* { dg-final { scan-assembler-not "\tmove.d" } } */
+/* { dg-final { scan-assembler-not "\tcmp" } } */
+/* { dg-final { scan-assembler-not "\tb\[^s\]" } } */
+/* { dg-final { scan-assembler-times "\t\[JjBb\]sr" 1 } } */
+
+#ifndef type
+#define type int
+#endif
+
+type svcsw (type *ptr, type oldval, type newval)
+{
+  return __sync_val_compare_and_swap (ptr, oldval, newval);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp
new file mode 100644
index 000000000..cf517fcaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/cris-torture.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `gcc-dg.exp' driver, looping over
+# optimization options.
+
+# Exit immediately if this isn't a CRIS target.
+if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/no-pro-epi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/no-pro-epi-1.c
new file mode 100644
index 000000000..728a34c23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/no-pro-epi-1.c
@@ -0,0 +1,4 @@
+/* { dg-options -mno-prologue-epilogue } */
+void f (void)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/pr24750-2.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/pr24750-2.c
new file mode 100644
index 000000000..281fb47b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/pr24750-2.c
@@ -0,0 +1,20 @@
+/* As the invalid insn in this test got as far as to the target output
+   code and was "near enough" to output invalid assembly-code, we need
+   to pass it through the assembler as well.
+   { dg-do assemble } */
+
+int
+f (short *a, char *y)
+{
+  __asm__ ("" : : :
+#ifndef __PIC__
+	   "r0",
+#endif
+	   "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+	   /* Register R8 is frame-pointer, and we don't have a means
+	      to not clobber it for the test-runs that don't eliminate
+	      it.  But that's ok; we have enough general-register
+	      pressure to repeat the bug without that.  */
+	   "r9", "r10", "r11", "r12", "r13");
+  return y[*a];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/pr34773.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/pr34773.c
new file mode 100644
index 000000000..d3723e38f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/pr34773.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+union double_union
+{
+  double d;
+  int i[2];
+};
+void _dtoa_r (double) __attribute__ ((__noinline__));
+void _vfprintf_r (double) __attribute__ ((__noinline__));
+void
+__sprint_r(int);
+void
+_vfprintf_r(double da)
+{
+ double ffp = da;
+ double value = ffp;
+ union double_union tmp;
+
+ tmp.d = value;
+
+ if ((tmp.i[1]) & ((unsigned)0x80000000L)) {
+   value = -value;
+ }
+
+ _dtoa_r (value);
+
+ if (ffp != 0)
+   __sprint_r(value == 0);
+ __asm__ ("");
+}
+
+
+double dd = -.012;
+double ff = .012;
+
+void exit (int) __attribute__ ((__noreturn__));
+void abort (void) __attribute__ ((__noreturn__));
+void *memset(void *s, int c, __SIZE_TYPE__ n);
+void _dtoa_r (double d)
+{
+  if (d != ff)
+    abort ();
+  __asm__ ("");
+}
+
+void __sprint_r (int i)
+{
+  if (i != 0)
+    abort ();
+  __asm__ ("");
+}
+
+int clearstack (void) __attribute__ ((__noinline__));
+int clearstack (void)
+{
+  char doodle[128];
+  memset (doodle, 0, sizeof doodle);
+  __asm__ volatile ("" : : "g" (doodle) : "memory");
+  return doodle[127];
+}
+
+void doit (void) __attribute__ ((__noinline__));
+void doit (void)
+{
+  _vfprintf_r (dd);
+  _vfprintf_r (ff);
+  __asm__ ("");
+}
+
+int main(void)
+{
+  clearstack ();
+  doit ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1.c
new file mode 100644
index 000000000..dd8704cc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -mno-unaligned-atomic-may-use-library" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1a.c
new file mode 100644
index 000000000..8055fd380
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -DTRAP_USING_ABORT -mno-trap-using-break8" } */
+/* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1ml.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1ml.c
new file mode 100644
index 000000000..c8cef1841
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-1ml.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -Dmis_ok" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2.c
new file mode 100644
index 000000000..3c162e96a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -Dmisalignment=2 -mno-unaligned-atomic-may-use-library" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2a.c
new file mode 100644
index 000000000..61e1c2047
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -Dmisalignment=2 -DTRAP_USING_ABORT -mno-trap-using-break8" } */
+/* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2ml.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2ml.c
new file mode 100644
index 000000000..0d78e9001
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-2ml.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -Dmisalignment=2 -Dmis_ok" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3.c
new file mode 100644
index 000000000..626a3d5cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -Dmisalignment=3 -mno-unaligned-atomic-may-use-library" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3a.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3a.c
new file mode 100644
index 000000000..339e74cd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3a.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -Dmisalignment=3 -DTRAP_USING_ABORT -mno-trap-using-break8" } */
+/* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3ml.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3ml.c
new file mode 100644
index 000000000..17c6d34d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-i-3ml.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=int -Dmisalignment=3 -Dmis_ok" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1.c
new file mode 100644
index 000000000..f2835aa06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1.c
@@ -0,0 +1,126 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=short -mno-unaligned-atomic-may-use-library" } */
+
+/* Make sure we get a SIGTRAP or equivalent when passing unaligned
+   but otherwise valid pointers to the atomic builtins.  */
+
+#include <signal.h>
+#include <stdlib.h>
+
+#ifndef type
+#error type not defined
+#endif
+
+#ifndef op
+#define op 0
+#endif
+
+#ifndef xchg
+#define xchg 0
+#endif
+
+#if op
+int sfa (type *p, type *q, int a);
+#endif
+
+#if xchg
+void acen (type *ptr, type *val, type *ret);
+#endif
+
+#ifndef misalignment
+#define misalignment 1
+#endif
+
+volatile int trap_expected = 0;
+
+struct { char x[misalignment]; type i; } s __attribute__ ((__aligned__ (4)))
+  = { {0}, (type) 0xdeadbeef };
+type x = 2;
+type ret = 42;
+
+#ifdef TRAP_USING_ABORT
+#define SYMSTR(x) STR1(__USER_LABEL_PREFIX__, x)
+#define STR1(x,y) STR2(x, y)
+#define STR2(x,y) #x #y
+/* LTO requires marking seemingly-unused-but-used global functions.  */
+void my_abort (void) __asm__ (SYMSTR (abort)) __attribute__ ((__used__));
+void my_abort (void)
+#else
+#ifdef __gnu_linux__
+void trap_handler(int signum)
+#else
+#error "can't catch break 8"
+#endif
+#endif
+{
+  if (1
+#ifndef TRAP_USING_ABORT
+      && signum == SIGTRAP
+#endif
+      && trap_expected
+      && s.i == (type) 0xdeadbeef
+      && x == 2 && ret == 42)
+    exit (0);
+
+#ifdef TRAP_USING_ABORT
+  /* We might be able to trust the exit-value getting through, but add
+     a NULL-dereference SEGV just in case.  Make sure gcc doesn't
+     understand the NULL.  */
+  *({ int *p; asm ("" : "=rm" (p) : "0" (0)); p; }) = 0xdead;
+  exit (2);
+#else
+  abort ();
+#endif
+}
+
+int main(void)
+{
+  type ret;
+
+#ifndef TRAP_USING_ABORT
+#ifdef __gnu_linux__
+  if (signal (SIGTRAP, trap_handler) == SIG_ERR)
+    abort ();
+#endif
+#endif
+
+#ifndef mis_ok
+  trap_expected = 1;
+#endif
+
+#if op
+  sfa (&s.i, &s.i, 42);
+
+  /* We should have fallen into the trap now.  But don't call abort
+     yet: if the trap is implemented as a call to abort, we have to
+     tell the difference.  Set a global variable *and* make sure the
+     setting isn't eliminated by optimizers: another call to sfa
+     should do it.  */
+  trap_expected = 0;
+
+#ifdef mis_ok
+  /* We're missing a sequence point, but we shouldn't have the initial
+     value.  */
+  if (s.i == (type) 0xdeadbeef)
+    abort ();
+  exit (0);
+#endif
+
+  sfa (&x, &x, 1);
+#else
+  acen (&s.i, &x, &ret);
+
+#ifdef mis_ok
+  if (s.i != 2 || x != 2 || ret != (type) 0xdeadbeef)
+    abort ();
+  exit (0);
+#endif
+
+  trap_expected = 0;
+
+  acen (&x, &x, &ret);
+#endif
+
+  abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1a.c
new file mode 100644
index 000000000..ba639172b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=short -DTRAP_USING_ABORT -mno-trap-using-break8" } */
+/* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1ml.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1ml.c
new file mode 100644
index 000000000..3685c5047
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-op-s-1ml.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dop -Dtype=short -Dmis_ok" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1.c
new file mode 100644
index 000000000..da25614e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -mno-unaligned-atomic-may-use-library" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1a.c
new file mode 100644
index 000000000..09a7a9ea3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -DTRAP_USING_ABORT -mno-trap-using-break8" } */
+/* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1ml.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1ml.c
new file mode 100644
index 000000000..d757a683b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-1ml.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -Dmis_ok" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2.c
new file mode 100644
index 000000000..e8a425328
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=2 -mno-unaligned-atomic-may-use-library" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2a.c
new file mode 100644
index 000000000..2b97613de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=2 -DTRAP_USING_ABORT -mno-trap-using-break8" } */
+/* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2ml.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2ml.c
new file mode 100644
index 000000000..fb711e0ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-2ml.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=2 -Dmis_ok" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3.c
new file mode 100644
index 000000000..4a3511bf2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=3 -mno-unaligned-atomic-may-use-library" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3a.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3a.c
new file mode 100644
index 000000000..94a25e37f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3a.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=3 -DTRAP_USING_ABORT -mno-trap-using-break8" } */
+/* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3ml.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3ml.c
new file mode 100644
index 000000000..32f8ebbd9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-i-3ml.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=int -Dmisalignment=3 -Dmis_ok" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1.c
new file mode 100644
index 000000000..d8dede9c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=short -mno-unaligned-atomic-may-use-library" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1a.c
new file mode 100644
index 000000000..6f5eb02af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do run } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=short -DTRAP_USING_ABORT -mno-trap-using-break8" } */
+/* { dg-additional-options "-mtrap-unaligned-atomic" { target cris-*-elf } } */
+/* { dg-additional-options "-mno-unaligned-atomic-may-use-library" { target cris*-*-linux* } } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1ml.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1ml.c
new file mode 100644
index 000000000..a6f501c10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/sync-mis-xchg-s-1ml.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target *-*-linux* } } */
+/* { dg-additional-sources "../sync-1.c" } */
+/* { dg-options "-Dxchg -Dtype=short -Dmis_ok" } */
+#include "sync-mis-op-s-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-1.c
new file mode 100644
index 000000000..48363fbb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-1.c
@@ -0,0 +1,13 @@
+/* Check that "break 8" defaults according to CPU version.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "*-*-*" } { "-march*" } { "" } } */
+/* { dg-final { scan-assembler "break 8" { target { ! cris-*-elf } } } } */
+/* { dg-final { scan-assembler-not "bsr" { target { ! cris-*-elf } } } } */
+/* { dg-final { scan-assembler-not "jsr" { target { ! cris-*-elf } } } } */
+/* { dg-final { scan-assembler-not "break\[ \t\]" { target cris-*-elf } } } */
+/* { dg-final { scan-assembler "\[jb\]sr \[_\]\?abort" { target cris-*-elf } } } */
+
+void do_trap (void)
+{
+  __builtin_trap ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-2.c
new file mode 100644
index 000000000..155d5fe42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-2.c
@@ -0,0 +1,11 @@
+/* As trap-1.c but forcing on.  */
+/* { dg-do compile } */
+/* { dg-options "-mtrap-using-break8" } */
+/* { dg-final { scan-assembler "break 8" } } */
+/* { dg-final { scan-assembler-not "bsr" } } */
+/* { dg-final { scan-assembler-not "jsr" } } */
+
+void do_trap (void)
+{
+  __builtin_trap ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-3.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-3.c
new file mode 100644
index 000000000..dfa092445
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-3.c
@@ -0,0 +1,10 @@
+/* Like trap-1.c and trap-2.c but force calls to abort.  */
+/* { dg-do compile } */
+/* { dg-options "-mno-trap-using-break8" } */
+/* { dg-final { scan-assembler-not "break\[ \t\]" } } */
+/* { dg-final { scan-assembler "\[jb\]sr \[_\]\?abort" } } */
+
+void do_trap (void)
+{
+  __builtin_trap ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-v0.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-v0.c
new file mode 100644
index 000000000..084fb28d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-v0.c
@@ -0,0 +1,11 @@
+/* As trap-1.c but with CPU version specified, excluding.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "*-*-*" } { "-march=*" } { "" } } */
+/* { dg-options "-march=v0" } */
+/* { dg-final { scan-assembler-not "break\[ \t\]" } } */
+/* { dg-final { scan-assembler "\[jb\]sr \[_\]\?abort" } } */
+
+void do_trap (void)
+{
+  __builtin_trap ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-v3.c b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-v3.c
new file mode 100644
index 000000000..e004c5bc8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/cris/torture/trap-v3.c
@@ -0,0 +1,12 @@
+/* As trap-1.c but with CPU version specified, including.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { "*-*-*" } { "-march=*" } { "" } } */
+/* { dg-options "-march=v3" } */
+/* { dg-final { scan-assembler "break 8" } } */
+/* { dg-final { scan-assembler-not "bsr" } } */
+/* { dg-final { scan-assembler-not "jsr" } } */
+
+void do_trap (void)
+{
+  __builtin_trap ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/epiphany/epiphany.exp b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/epiphany.exp
new file mode 100644
index 000000000..59226ae15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/epiphany.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2007-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an epiphany target.
+if ![istarget epiphany*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fmadd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fmadd-1.c
new file mode 100644
index 000000000..868d5bd02
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fmadd-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "fmadd\[ \ta-zA-Z0-9\]*," 2 } } */
+
+#include <epiphany_intrinsics.h>
+
+float
+f1 (float a, float b, float c)
+{
+  return __builtin_epiphany_fmadd (a, b, c);
+}
+
+float
+f2 (float a, float b, float c)
+{
+  return a + b * c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fmsub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fmsub-1.c
new file mode 100644
index 000000000..ff7fefa7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fmsub-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "fmsub\[ \ta-zA-Z0-9\]*," 2 } } */
+
+#include <epiphany_intrinsics.h>
+
+float
+f1 (float a, float b, float c)
+{
+  return __builtin_epiphany_fmsub (a, b, c);
+}
+
+float
+f2 (float a, float b, float c)
+{
+  return a - b * c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fnma-1.c b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fnma-1.c
new file mode 100644
index 000000000..3155079f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/fnma-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "fmsub\[ \ta-zA-Z0-9\]*," 1 } } */
+
+float
+f (float ar, float ai, float br, float bi)
+{
+  return ar * br - ai * bi;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/epiphany/interrupt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/interrupt-2.c
new file mode 100644
index 000000000..4c0de6c5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/interrupt-2.c
@@ -0,0 +1,24 @@
+/* { dg-options "-g" } */
+
+void __attribute__((interrupt))
+universal_handler (void)
+{
+}
+
+void __attribute__((interrupt("dma0","Vss","dma1")))
+g (void)
+{ /* { dg-warning "is not \"reset\"" } */
+}
+
+void __attribute__((interrupt("dma0","dma1","timer1","reset"),
+		    forwarder_section("test")))
+misc_handler (void)
+{
+}
+
+void __attribute__((interrupt(dma0,42)))
+h (void)
+{ /* { dg-warning "is not a string constant" } */
+}
+
+/* { dg-final { scan-assembler-times "b\[ \t\]*_misc_handler" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/epiphany/interrupt.c b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/interrupt.c
new file mode 100644
index 000000000..86fb25561
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/epiphany/interrupt.c
@@ -0,0 +1,18 @@
+/* { dg-options "-g" } */
+
+void __attribute__((interrupt("dma0")))
+dma0_handler (void)
+{
+}
+
+void __attribute__((interrupt("Vss")))
+g (void)
+{ /* { dg-warning "is not \"reset\"" } */
+}
+
+void __attribute__((interrupt(42)))
+h (void)
+{ /* { dg-warning "is not a string constant" } */
+}
+
+/* { dg-final { scan-assembler-times "b\[ \t\]*_dma0_handler" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-accs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-accs-1.c
new file mode 100644
index 000000000..cb4232b3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-accs-1.c
@@ -0,0 +1,65 @@
+/* Check that ACCs and ACCGs are treated as global variables even if
+   media.h isn't included.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+void
+set ()
+{
+#define SET(X) __MWTACC (X, (X) | 0x100), __MWTACCG (X, X)
+  SET (0);
+  SET (1);
+  SET (2);
+  SET (3);
+#if defined (__CPU_FR450__)
+  SET (8);
+  SET (9);
+  SET (10);
+  SET (11);
+#elif __FRV_ACC__ > 4
+  SET (4);
+  SET (5);
+  SET (6);
+  SET (7);
+#endif
+#undef SET
+}
+
+void
+check ()
+{
+  int diff1, diff2;
+
+  diff1 = diff2 = 0;
+
+#define CHECK(X) \
+	(diff1 |= (__MRDACC (X) ^ (X | 0x100)), \
+	 diff2 |= (__MRDACCG (X) ^ X))
+  CHECK (0);
+  CHECK (1);
+  CHECK (2);
+  CHECK (3);
+#if defined (__CPU_FR450__)
+  CHECK (8);
+  CHECK (9);
+  CHECK (10);
+  CHECK (11);
+#elif __FRV_ACC__ > 4
+  CHECK (4);
+  CHECK (5);
+  CHECK (6);
+  CHECK (7);
+#endif
+#undef CHECK
+  if ((diff1 | diff2) != 0)
+    abort ();
+}
+
+int
+main ()
+{
+  set ();
+  check ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-mclracca-1.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-mclracca-1.c
new file mode 100644
index 000000000..28ab497ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-mclracca-1.c
@@ -0,0 +1,24 @@
+/* GCSE used to reuse the value of __MRDACC.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+void foo (int *z)
+{
+  __MWTACC (3, 1);
+  if (__MRDACC (3) != 1)
+    *z = 1;
+  __MCLRACCA ();
+  if (__MRDACC (3) != 1)
+    *z = 2;
+}
+
+int main ()
+{
+  int z = 3;
+
+  foo (&z);
+  if (z != 2)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-mdpackh-1.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-mdpackh-1.c
new file mode 100644
index 000000000..837423773
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-mdpackh-1.c
@@ -0,0 +1,16 @@
+/* Test the new (Fujitsu-compatible) __MDPACKH() interface.  */
+/* { dg-do run } */
+extern void exit (int);
+extern void abort (void);
+
+unsigned short x[] = { 0x8765, 0x1234, 0x2222, 0xeeee };
+
+int
+main ()
+{
+  if (__MDPACKH (x[0], x[1], x[2], x[3]) != 0x876522221234eeeeULL)
+    abort ();
+  if (__MDPACKH (0x1111, 0x8001, 0xeeee, 0x7002) != 0x1111eeee80017002ULL)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-read-write-1.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-read-write-1.c
new file mode 100644
index 000000000..8496a58ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-read-write-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+volatile unsigned long long x[2];
+
+int main ()
+{
+  volatile char *addr = (volatile char *) &x[0];
+
+  x[0] = ~0ULL;
+  x[1] = ~0ULL;
+  __builtin_write64 (addr, 0x1122334455667788ULL);
+  __builtin_write32 (addr + 8, 0x12345678);
+  __builtin_write16 (addr + 12, 0xaabb);
+  __builtin_write8 (addr + 14, 0xcc);
+
+  if (x[0] != 0x1122334455667788ULL
+      || x[1] != 0x12345678aabbccffULL
+      || __builtin_read8 (addr) != 0x11
+      || __builtin_read16 (addr + 2) != 0x3344
+      || __builtin_read32 (addr + 4) != 0x55667788
+      || __builtin_read64 (addr + 8) != 0x12345678aabbccffULL)
+    abort ();
+
+  __builtin_write64 (addr, 0);
+  __builtin_write32 (addr + 8, 0);
+  __builtin_write16 (addr + 12, 0);
+  __builtin_write8 (addr + 14, 0);
+  if (x[0] != 0 || x[1] != 0xff)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-global-dynamic.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-global-dynamic.c
new file mode 100644
index 000000000..2135090f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-global-dynamic.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=global-dynamic -fpic -mfdpic -mno-inline-plt" } */
+/* { dg-do compile } */
+extern __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "call #gettlsoff.x." } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-initial-exec-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-initial-exec-pic.c
new file mode 100644
index 000000000..b51e34df6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-initial-exec-pic.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=initial-exec -fpic -mfdpic" } */
+/* { dg-do compile } */
+extern __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "ld.*#gottlsoff12" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-initial-exec.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-initial-exec.c
new file mode 100644
index 000000000..fa755a299
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-initial-exec.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=initial-exec -mfdpic" } */
+/* { dg-do compile } */
+extern __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "ld.*#tlsoff.x.@" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt-pic.c
new file mode 100644
index 000000000..3eabe1c6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt-pic.c
@@ -0,0 +1,13 @@
+/* { dg-options "-ftls-model=local-dynamic -minline-plt -fpic -mfdpic" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "lddi.*gottlsdesc12" } } */
+/* { dg-final { scan-assembler "calll.*#gettlsoff\\(0\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt.c
new file mode 100644
index 000000000..5c2de9384
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic-plt.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=local-dynamic -minline-plt -fPIC -mfdpic" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "ldd.*tlsdesc\\(0\\)@" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic.c
new file mode 100644
index 000000000..4680a98f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-dynamic.c
@@ -0,0 +1,13 @@
+/* { dg-options "-ftls-model=local-dynamic -fpic -mfdpic" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "gettlsoff\\(0\\)" } } */
+/* { dg-final { scan-assembler "tlsmoff12" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-exec-TLS.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-exec-TLS.c
new file mode 100644
index 000000000..83f78de4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-exec-TLS.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=local-exec -mfdpic -mTLS" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler "sethi.*tlsmoffhi\\(x\\)," } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-exec.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-exec.c
new file mode 100644
index 000000000..dd1b86a05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/all-tls-local-exec.c
@@ -0,0 +1,12 @@
+/* { dg-options "-ftls-model=local-exec -mfdpic" } */
+/* { dg-do compile } */
+static __thread int x;
+extern void bar ();
+int *y;
+
+void foo (void)
+{
+  bar ();
+  y = &x;
+}
+/* { dg-final { scan-assembler ".*tlsmoff12" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr400-builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr400-builtins-1.c
new file mode 100644
index 000000000..85ca7cfbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr400-builtins-1.c
@@ -0,0 +1,28 @@
+/* Test prefetch support.  */
+/* { dg-options "-mcpu=fr400" } */
+/* { dg-do run } */
+
+unsigned char global[64];
+
+int foo (unsigned int *x, int n)
+{
+  unsigned short local[16];
+
+  __data_prefetch0 (x);
+  __data_prefetch0 (&x[8]);
+  __data_prefetch0 (&x[n]);
+  __data_prefetch0 (local);
+  __data_prefetch0 (&local[16]);
+  __data_prefetch0 (&local[n]);
+  __data_prefetch0 (global);
+  __data_prefetch0 (&global[32]);
+  __data_prefetch0 (&global[n]);
+}
+
+int main ()
+{
+  unsigned int i[16];
+
+  foo (i, 2);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr400-builtins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr400-builtins-2.c
new file mode 100644
index 000000000..66f30055e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr400-builtins-2.c
@@ -0,0 +1,10 @@
+/* Test prefetch support.  */
+/* { dg-options "-mcpu=fr400" } */
+/* { dg-do compile } */
+
+void foo (void *x)
+{
+  __data_prefetch0 (x);
+}
+
+/* { dg-final { scan-assembler "\tdcpl " } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-1.c
new file mode 100644
index 000000000..98e304e27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-1.c
@@ -0,0 +1,39 @@
+/* Test the IACC multiply/accumulate instructions.  Also test the IACC
+   read/write functions.  */
+/* { dg-options "-mcpu=fr405" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  long long res, res1, res2, res3;
+
+  __SMU (0x12345678, 0x40004000);
+  __SMASS (0x12000000, 0x11223344);
+  __SMSSS (0x01020304, 0x54321000);
+
+  res = __IACCreadll (0);
+  res1 = 0x12345678LL * 0x40004000LL;
+  res2 = 0x12000000LL * 0x11223344LL;
+  res3 = 0x01020304LL * 0x54321000LL;
+  if (res != res1 + res2 - res3)
+    abort ();
+
+  __IACCsetll (0, 0x7ffffffffffffff0LL);
+  __SMASS (0x100, 0x100);
+  if (__IACCreadll (0) != 0x7fffffffffffffffLL)
+    abort ();
+
+  __IACCsetl (0, -0x7ffffffe);
+  __IACCsetl (1, 0);
+  __SMSSS (0x10001, 0x10000);
+  if (__IACCreadl (0) != -0x7fffffff - 1 || __IACCreadl (1) != -0x10000)
+    abort ();
+
+  __SMSSS (0x10001, 0x10000);
+  if (__IACCreadl (0) != -0x7fffffff - 1 || __IACCreadl (1) != 0)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-2.c
new file mode 100644
index 000000000..778547c4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-2.c
@@ -0,0 +1,69 @@
+/* Test the SCUTSS instruction.  */
+/* { dg-options "-mcpu=fr405" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  struct {
+    long long value;
+    int cut_point;
+    int result;
+  } values[] = {
+    /* Non-saturating values */
+
+    { +0x0000000000001234LL, 44, +0x01234000 },
+    { ~0x0000000000001234LL, 44, ~0x01234fff },
+
+    { +0x0000011223300fffLL, 20, +0x11223301 },
+    { ~0x0000011223300fffLL, 20, ~0x11223300 },
+    { +0x0000011223300800LL, 20, +0x11223301 },
+    { ~0x0000011223300800LL, 20, ~0x11223300 },
+    { +0x00000112233007ffLL, 20, +0x11223300 },
+    { ~0x00000112233007ffLL, 20, ~0x112232ff },
+    { +0x0000011223300000LL, 20, +0x11223300 },
+    { ~0x0000011223300000LL, 20, ~0x112232ff },
+
+    { +0x1234567fffffffffLL, -4, +0x01234568 },
+    { ~0x1234567fffffffffLL, -4, ~0x01234567 },
+    { +0x1234567800000000LL, -4, +0x01234568 },
+    { ~0x1234567800000000LL, -4, ~0x01234567 },
+    { +0x12345677ffffffffLL, -4, +0x01234567 },
+    { ~0x12345677ffffffffLL, -4, ~0x01234566 },
+    { +0x1234567000000000LL, -4, +0x01234567 },
+    { ~0x1234567000000000LL, -4, ~0x01234566 },
+
+    /* Saturation tests */
+
+    { +0x4000000000000000LL, 44, +0x7fffffff },
+    { ~0x4000000000000000LL, 44, ~0x7fffffff },
+    { +0x0000000000080000LL, 44, +0x7fffffff },
+    { ~0x0000000000080000LL, 44, ~0x7fffffff },
+    { +0x000000000007ffffLL, 44, +0x7ffff000 },
+    { ~0x000000000007ffffLL, 44, ~0x7fffffff },
+    { +0x000000000007fffeLL, 44, +0x7fffe000 },
+    { ~0x000000000007fffeLL, 44, ~0x7fffefff },
+
+    { +0x4000000000000000LL, 20, +0x7fffffff },
+    { ~0x4000000000000000LL, 20, ~0x7fffffff },
+    { +0x0000080000000000LL, 20, +0x7fffffff },
+    { ~0x0000080000000000LL, 20, ~0x7fffffff },
+    { +0x000007ffffffffffLL, 20, +0x7fffffff },
+    { ~0x000007ffffffffffLL, 20, ~0x7fffffff },
+    { +0x000007fffffff000LL, 20, +0x7fffffff },
+    { ~0x000007fffffff000LL, 20, ~0x7ffffffe },
+    { +0x000007ffffffe000LL, 20, +0x7ffffffe },
+    { ~0x000007ffffffefffLL, 20, ~0x7ffffffe }
+  };
+
+  unsigned int i;
+
+  for (i = 0; i < sizeof (values) / sizeof (values[0]); i++)
+    {
+      __IACCsetll (0, values[i].value);
+      if (__SCUTSS (values[i].cut_point) != values[i].result)
+	abort ();
+    }
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-3.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-3.c
new file mode 100644
index 000000000..91fd96d7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr405-builtins-3.c
@@ -0,0 +1,58 @@
+/* Test the remaining integer instructions.  */
+/* { dg-options "-mcpu=fr405" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  if (__SLASS (0x112233, 4) != 0x1122330)
+    abort ();
+
+  if (__SLASS (0x7ffff, 12) != 0x7ffff000)
+    abort ();
+
+  if (__SLASS (0x80000, 12) != 0x7fffffff)
+    abort ();
+
+  if (__SLASS (-0x7ffff, 12) != -0x7ffff000)
+    abort ();
+
+  if (__SLASS (-0x80000, 12) != -0x7fffffff - 1)
+    abort ();
+
+  if (__SLASS (-0x80001, 12) != -0x7fffffff - 1)
+    abort ();
+
+  if (__ADDSS (0x7fffffff, 1) != 0x7fffffff)
+    abort ();
+
+  if (__ADDSS (0x7ffffffd, 1) != 0x7ffffffe)
+    abort ();
+
+  if (__ADDSS (-0x7fffffff, -2) != -0x7fffffff - 1)
+    abort ();
+
+  if (__ADDSS (-0x7ffffffd, -2) != -0x7fffffff)
+    abort ();
+
+  if (__SUBSS (0x7fffffff, -1) != 0x7fffffff)
+    abort ();
+
+  if (__SUBSS (0x7ffffffd, -1) != 0x7ffffffe)
+    abort ();
+
+  if (__SUBSS (-0x7fffffff, 2) != -0x7fffffff - 1)
+    abort ();
+
+  if (__SUBSS (-0x7ffffffd, 2) != -0x7fffffff)
+    abort ();
+
+  if (__SCAN (0x12345678, 0) != 3)
+    abort ();
+
+  if (__SCAN (0x12345678, 0x24680000) != 17)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-1.c
new file mode 100644
index 000000000..cb7986ddb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-1.c
@@ -0,0 +1,27 @@
+/* Test __MQLCLRHS.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  struct { unsigned long long a, b, c; } entries[] = {
+    { 0x10002000e800d800ULL, 0x0800080008000800ULL, 0x10002000e800d800ULL },
+    { 0x10002000e800d800ULL, 0xf800f800f800f800ULL, 0xf000e00018002800ULL },
+    { 0x1000100010001000ULL, 0xf000f80008001000ULL, 0x0000f00010000000ULL },
+    { 0xf000f000f000f000ULL, 0xf000f80008001000ULL, 0x00001000f0000000ULL },
+    { 0x8000800080008000ULL, 0x80007fff80010000ULL, 0x000080007fff8000ULL },
+    { 0x7fff7fff7fff7fffULL, 0x80007fff80010000ULL, 0x0000000000007fffULL },
+    { 0x8001800180018001ULL, 0x80007fff80010000ULL, 0x0000000000008001ULL },
+    { 0x800080000001ffffULL, 0x0001ffff80008000ULL, 0x80007fff00000000ULL }
+  };
+
+  unsigned int i;
+
+  for (i = 0; i < sizeof (entries) / sizeof (entries[0]); i++)
+    if (__MQLCLRHS (entries[i].a, entries[i].b) != entries[i].c)
+      abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-2.c
new file mode 100644
index 000000000..663d735cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-2.c
@@ -0,0 +1,27 @@
+/* Test __MLMTHS.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  struct { unsigned long long a, b, c; } entries[] = {
+    { 0x10002000e800d800ULL, 0x0800080008000800ULL, 0x08000800f800f800ULL },
+    { 0x10002000e800d800ULL, 0xf800f800f800f800ULL, 0xf800f80008000800ULL },
+    { 0x1000100010001000ULL, 0xe800f80008001800ULL, 0x1000f80008001000ULL },
+    { 0xf000f000f000f000ULL, 0xe800f80008001800ULL, 0xf0000800f800f000ULL },
+    { 0x8000800080008000ULL, 0x80007fff80010000ULL, 0x7fff80017fff0000ULL },
+    { 0x7fff7fff7fff7fffULL, 0x80007fff80010000ULL, 0x7fff7fff80010000ULL },
+    { 0x8001800180018001ULL, 0x80007fff80010000ULL, 0x800180017fff0000ULL },
+    { 0x800080000001ffffULL, 0x0001ffff80008000ULL, 0xffff00010001ffffULL }
+  };
+
+  unsigned int i;
+
+  for (i = 0; i < sizeof (entries) / sizeof (entries[0]); i++)
+    if (__MQLMTHS (entries[i].a, entries[i].b) != entries[i].c)
+      abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-3.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-3.c
new file mode 100644
index 000000000..00478a4ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-3.c
@@ -0,0 +1,25 @@
+/* Test __MQSLLHI.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  if (__MQSLLHI (0x0001000200030004ULL, 1) != 0x0002000400060008ULL)
+    abort ();
+
+  if (__MQSLLHI (0xfffffffefffcfff8ULL, 1) != 0xfffefffcfff8fff0ULL)
+    abort ();
+
+  if (__MQSLLHI (0xfffffffefffcfff8ULL, 12) != 0xf000e000c0008000ULL)
+    abort ();
+
+  if (__MQSLLHI (0x123456789abcdef0ULL, 12) != 0x40008000c0000000ULL)
+    abort ();
+
+  if (__MQSLLHI (0x123456789abcdef0ULL, 16) != 0x123456789abcdef0ULL)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-4.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-4.c
new file mode 100644
index 000000000..1eee1861a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-4.c
@@ -0,0 +1,25 @@
+/* Test __MQSRAHI.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int main ()
+{
+  if (__MQSRAHI (0x0001000200030004ULL, 1) != 0x0000000100010002ULL)
+    abort ();
+
+  if (__MQSRAHI (0xfffffffefffcfff8ULL, 1) != 0xfffffffffffefffcULL)
+    abort ();
+
+  if (__MQSRAHI (0x8000c000e000f000ULL, 12) != 0xfff8fffcfffeffffULL)
+    abort ();
+
+  if (__MQSRAHI (0x123456789abcdef0ULL, 12) != 0x00010005fff9fffdULL)
+    abort ();
+
+  if (__MQSRAHI (0x123456789abcdef0ULL, 16) != 0x123456789abcdef0ULL)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-5.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-5.c
new file mode 100644
index 000000000..c94e8ff80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-5.c
@@ -0,0 +1,35 @@
+/* Test that all accumulator registers are accessible.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+#define TEST_ACC(X) \
+  (__MWTACC (X, 0x11220000 | X), __MRDACC (X) ^ (0x11220000 | X))
+
+#define TEST_ACCG(X) \
+  (__MWTACCG (X, X), __MRDACCG (X) ^ X)
+
+#define ZERO_ACC(X) \
+  (__MRDACC (X) | __MRDACCG (X))
+
+int
+main ()
+{
+  if (TEST_ACC (0) | TEST_ACC (1) | TEST_ACC (2) | TEST_ACC (3))
+    abort ();
+  if (TEST_ACC (8) | TEST_ACC (9) | TEST_ACC (10) | TEST_ACC (11))
+    abort ();
+  if (TEST_ACCG (0) | TEST_ACCG (1) | TEST_ACCG (2) | TEST_ACCG (3))
+    abort ();
+  if (TEST_ACCG (8) | TEST_ACCG (9) | TEST_ACCG (10) | TEST_ACCG (11))
+    abort ();
+
+  __MCLRACCA ();
+  if (ZERO_ACC (0) | ZERO_ACC (1) | ZERO_ACC (2) | ZERO_ACC (3))
+    abort ();
+  if (ZERO_ACC (8) | ZERO_ACC (9) | ZERO_ACC (10) | ZERO_ACC (11))
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-6.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-6.c
new file mode 100644
index 000000000..0624eb1f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-6.c
@@ -0,0 +1,23 @@
+/* Test a situation in which an M5 instruction (mrdacc) and M4 instruction
+   (mqmulhu) can be issued together.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MQMULHU (0, 0x0011002200330044ULL, 0x0002000300040001ULL);
+  __MQMULHU (8, 0x0100020003000400ULL, 0x0001000200030004ULL);
+
+  /* 0x22 + 0x66 + 0xcc + 0x44 = 0x198 */
+  /* 0x100 + 0x400 + 0x900 + 0x1000 = 0x1e00 */
+  if (__MRDACC (0) + __MRDACC (1)
+      + __MRDACC (2) + __MRDACC (3)
+      + __MRDACC (8) + __MRDACC (9)
+      + __MRDACC (10) + __MRDACC (11) != 0x1f98)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-7.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-7.c
new file mode 100644
index 000000000..dbba44a85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-7.c
@@ -0,0 +1,24 @@
+/* Test that the code from fr450-builtins-6.c packs together an
+   M4 and M5 instruction.  */
+/* { dg-options "-O2 -mcpu=fr450" } */
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "mqmulhu.p\[^\t\]*\t*mrdacc" } } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MQMULHU (0, 0x0011002200330044ULL, 0x0002000300040001ULL);
+  __MQMULHU (8, 0x0100020003000400ULL, 0x0001000200030004ULL);
+
+  /* 0x22 + 0x66 + 0xcc + 0x44 = 0x198 */
+  /* 0x100 + 0x400 + 0x900 + 0x1000 = 0x1e00 */
+  if (__MRDACC (0) + __MRDACC (1)
+      + __MRDACC (2) + __MRDACC (3)
+      + __MRDACC (8) + __MRDACC (9)
+      + __MRDACC (10) + __MRDACC (11) != 0x1f98)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-8.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-8.c
new file mode 100644
index 000000000..2c23f8cd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-8.c
@@ -0,0 +1,22 @@
+/* Test a situation in which an M6 instruction (mdcutssi) and M4 instruction
+   (mqmulhu) can be issued together.  */
+/* { dg-options "-mcpu=fr450" } */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MQMULHU (0, 0x0001001101111111ULL, 0x0001000200030004ULL);
+  __MQMULHU (8, 0x0002002202222222ULL, 0x0004000400040004ULL);
+  if (__MDCUTSSI (0, 8)
+      + __MDCUTSSI (2, 8)
+      + __MDCUTSSI (8, 8)
+      + __MDCUTSSI (10, 8)
+      != (0x0000000100000022ULL + 0x0000033300004444ULL
+	  + 0x0000000800000088ULL + 0x0000088800008888ULL))
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-9.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-9.c
new file mode 100644
index 000000000..5f32ba281
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr450-builtins-9.c
@@ -0,0 +1,23 @@
+/* Test a situation in which an M6 instruction (mdcutssi) and M4 instruction
+   (mqmulhu) can be issued together.  */
+/* { dg-options "-O2 -mcpu=fr450" } */
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "mqmulhu.p\[^\t\]*\t*mdcutssi" } } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MQMULHU (0, 0x0001001101111111ULL, 0x0001000200030004ULL);
+  __MQMULHU (8, 0x0002002202222222ULL, 0x0004000400040004ULL);
+  if (__MDCUTSSI (0, 8)
+      + __MDCUTSSI (2, 8)
+      + __MDCUTSSI (8, 8)
+      + __MDCUTSSI (10, 8)
+      != (0x0000000100000022ULL + 0x0000033300004444ULL
+	  + 0x0000000800000088ULL + 0x0000088800008888ULL))
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-1.c
new file mode 100644
index 000000000..d728f12a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-1.c
@@ -0,0 +1,42 @@
+/* Test prefetch support.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+unsigned char global[64];
+
+void
+foo (unsigned int *x, int n)
+{
+  unsigned short local[16];
+
+  __data_prefetch0 (x);
+  __data_prefetch0 (&x[8]);
+  __data_prefetch0 (&x[n]);
+  __data_prefetch0 (local);
+  __data_prefetch0 (&local[16]);
+  __data_prefetch0 (&local[n]);
+  __data_prefetch0 (global);
+  __data_prefetch0 (&global[32]);
+  __data_prefetch0 (&global[n]);
+
+#if __FRV_VLIW__ > 1
+  __data_prefetch (x);
+  __data_prefetch (&x[8]);
+  __data_prefetch (&x[n]);
+  __data_prefetch (local);
+  __data_prefetch (&local[16]);
+  __data_prefetch (&local[n]);
+  __data_prefetch (global);
+  __data_prefetch (&global[32]);
+  __data_prefetch (&global[n]);
+#endif
+}
+
+int main ()
+{
+  unsigned int i[16];
+
+  foo (i, 2);
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-2.c
new file mode 100644
index 000000000..ce39f462c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-2.c
@@ -0,0 +1,9 @@
+/* Test prefetch support.  */
+/* { dg-do compile } */
+
+void foo (void *x)
+{
+  __data_prefetch0 (x);
+}
+
+/* { dg-final { scan-assembler "\tdcpl " } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-3.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-3.c
new file mode 100644
index 000000000..b5347de74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-3.c
@@ -0,0 +1,13 @@
+/* Test prefetch support.  */
+/* { dg-do compile } */
+
+#if __FRV_VLIW__ > 1
+void foo (void *x)
+{
+  __data_prefetch (x);
+}
+#else
+asm (";\tnop.p\n;\tnldub ");
+#endif
+
+/* { dg-final { scan-assembler "\tnop.p.*\tnldub " } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-4.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-4.c
new file mode 100644
index 000000000..801dfee20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-4.c
@@ -0,0 +1,48 @@
+/* Test the __M{,D}{ADD,SUB}ACC functions.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MWTACC (6, 10);
+  __MWTACC (7, 25);
+  __MADDACCS (5, 6);
+  if (__MRDACC (5) != 35)
+    abort ();
+  __MSUBACCS (4, 6);
+  if (__MRDACC (4) != -15)
+    abort ();
+  __MASACCS (4, 6);
+  if (__MRDACC (4) != 35 || __MRDACC (5) != -15)
+    abort ();
+
+  __MWTACC (0, 100);
+  __MWTACC (1, 150);
+  __MWTACC (2, 1000);
+  __MWTACC (3, 1500);
+  __MDADDACCS (2, 0);
+  if (__MRDACC (2) != 250 || __MRDACC (3) != 2500)
+    abort ();
+
+  __MWTACC (0, 100);
+  __MWTACC (1, 150);
+  __MWTACC (2, 1000);
+  __MWTACC (3, 1500);
+  __MDSUBACCS (2, 0);
+  if (__MRDACC (2) != -50 || __MRDACC (3) != -500)
+    abort ();
+
+  __MWTACC (0, 100);
+  __MWTACC (1, 150);
+  __MWTACC (2, 1000);
+  __MWTACC (3, 1500);
+  __MDASACCS (0, 0);
+  if (__MRDACC (0) != 250 || __MRDACC (1) != -50)
+    abort ();
+  if (__MRDACC (2) != 2500 || __MRDACC (3) != -500)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-5.c b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-5.c
new file mode 100644
index 000000000..ff75ea17d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/fr550-builtins-5.c
@@ -0,0 +1,25 @@
+/* Test that __MADDACC only changes the registers it's supposed to.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  __MWTACC (0, 1);
+  __MWTACC (1, 1);
+  __MWTACC (2, 1);
+  __MWTACC (3, 1);
+  __MWTACC (4, 1);
+  __MWTACC (5, 1);
+  __MWTACC (6, 1);
+  __MWTACC (7, 1);
+  __MADDACCS (0, 2);
+  __MADDACCS (4, 6);
+  if ((__MRDACC (0) - 2)
+      | (__MRDACC (1) - 1)
+      | (__MRDACC (4) - 2)
+      | (__MRDACC (5) - 1))
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/frv/frv.exp b/gcc-4.9/gcc/testsuite/gcc.target/frv/frv.exp
new file mode 100644
index 000000000..b3dcc2591
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/frv/frv.exp
@@ -0,0 +1,53 @@
+# Copyright (C) 2004-2014 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# The name of each test starts with the architecture it requires.  Tests that
+# work on all variants start with "all".
+
+if {![istarget frv-*-*]} {
+    return 0
+}
+
+load_lib gcc-dg.exp
+
+# Find out which architecture is used by default.
+set mainarch "fr500"
+foreach flag [target_info multilib_flags] {
+    regexp "^-mcpu=(.*)" $flag dummy mainarch
+    if {$flag == "-mno-pack"} {
+	# -mno-pack disables media intrinsics.
+	return 0
+    }
+}
+
+# Set $archs to "all" plus the list of architectures we can test.
+set archs [list "all" $mainarch]
+switch $mainarch {
+    fr405 { lappend archs fr400 }
+    fr450 { lappend archs fr405 fr400 }
+}
+
+# Set $files to the list of files we can test.
+set files ""
+foreach arch $archs {
+    lappend files [lsort [glob -nocomplain $srcdir/$subdir/${arch}*.c]]
+}
+
+dg-init
+gcc-dg-runtest [eval concat $files] ""
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/h8300/h8300.exp b/gcc-4.9/gcc/testsuite/gcc.target/h8300/h8300.exp
new file mode 100644
index 000000000..8523a1285
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/h8300/h8300.exp
@@ -0,0 +1,82 @@
+# Copyright (C) 2013-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a h8300 target.
+if ![istarget h8300*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
+# Copyright (C) 2013-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a h8300 target.
+if ![istarget h8300*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr.c b/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr.c
new file mode 100644
index 000000000..24fba30d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr.c
@@ -0,0 +1,40 @@
+/* Check whether rte is generated for two ISRs.  */
+/* { dg-do compile { target h8300-*-* } }  */
+/* { dg-options "-O3" }  */
+/* { dg-final { scan-assembler-times "rte" 2} }  */
+
+extern void foo (void);
+
+#pragma interrupt
+void
+isr1 (void)
+{
+  foo ();
+}
+
+#pragma interrupt
+void
+isr2 (void)
+{
+  foo ();
+}
+/* Check whether rte is generated for two ISRs.  */
+/* { dg-do compile { target h8300-*-* } }  */
+/* { dg-options "-O3" }  */
+/* { dg-final { scan-assembler-times "rte" 2} }  */
+
+extern void foo (void);
+
+#pragma interrupt
+void
+isr1 (void)
+{
+  foo ();
+}
+
+#pragma interrupt
+void
+isr2 (void)
+{
+  foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr2.c b/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr2.c
new file mode 100644
index 000000000..7c242ec31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/h8300/pragma-isr2.c
@@ -0,0 +1,42 @@
+/* Check whether rte is generated only for an ISR.  */
+/* { dg-do compile { target h8300-*-* } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler-times "rte" 1 } }  */
+
+#pragma interrupt
+void
+isr (void)
+{
+}
+
+void
+delay (int a)
+{
+}
+
+int
+main (void)
+{
+  return 0;
+}
+/* Check whether rte is generated only for an ISR.  */
+/* { dg-do compile { target h8300-*-* } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler-times "rte" 1 } }  */
+
+#pragma interrupt
+void
+isr (void)
+{
+}
+
+void
+delay (int a)
+{
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20000609-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000609-1.c
new file mode 100644
index 000000000..a083a5d53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000609-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O1 -ffast-math -march=i686" } */
+
+
+/* Sanity check for fp_jcc_* with TARGET_CMOVE.  */
+
+extern void abort (void);
+
+static int test(double a)
+{
+  if (a)
+    return 0;
+}
+
+static double zero = 0.0;
+
+int main ()
+{
+  test (zero);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20000614-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000614-1.c
new file mode 100644
index 000000000..5e86f02e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000614-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+void bar(char *p)
+{
+}
+
+static inline void foo (unsigned long base, unsigned char val)
+{
+  val ^= (1<<2);
+  bar (val & (1<<5) ? "1" : "2");
+  bar (val & (1<<4) ? "1" : "2");
+  bar (val & (1<<3) ? "1" : "2");
+  bar (val & (1<<2) ? "1" : "2");
+  bar (val & (1<<1) ? "1" : "2");
+  bar (val & (1<<0) ? "1" : "2");
+  asm volatile ("": :"a" (val), "d" (base));
+}
+
+int main (void)
+{
+  foo (23, 1);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20000614-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000614-2.c
new file mode 100644
index 000000000..5b0490707
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000614-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+extern void exit (int);
+
+char buf[8];
+
+void bar(char *p)
+{
+}
+
+int main()
+{
+  union {
+    unsigned int val;
+    unsigned char p[4];
+  } serial;
+
+  int i;
+  serial.val = 0;
+  bar(buf);
+  for(i = 0; i < 8; i += 4)
+    {
+      serial.p [0] += buf [i + 0];
+      serial.p [1] += buf [i + 1];
+      serial.p [2] += buf [i + 2];
+      serial.p [3] += buf [i + 3];
+    }
+  if (serial.val)
+    abort();
+  exit(0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20000720-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000720-1.c
new file mode 100644
index 000000000..84e136c52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000720-1.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mpreferred-stack-boundary=2 -march=i586 -O2 -fomit-frame-pointer" } */
+
+extern void *foo(void *a, const void *b, unsigned c);
+
+extern inline void *
+bar(void *a, const void *b, unsigned c)
+{
+  int d0, d1, d2;
+  __asm__ __volatile__(
+    "" :
+    "=&c" (d0), "=&D" (d1), "=&S" (d2) :
+    "0" (c/4), "q" (c), "1" (a), "2" (b) :
+    "memory");
+  return a;
+}
+
+typedef struct {
+  unsigned char a;
+  unsigned b : 2;
+  unsigned c : 4;
+  unsigned d : 2;
+} *baz;
+
+static int
+dead(unsigned short *v, char *w, unsigned char *x, int y, int z)
+{
+  int i = 0;
+  unsigned short j = *v;
+
+  while (y > 0) {
+    ((baz)x)->a = j;
+    ((baz)x)->b = 0;
+    ((baz)x)->c = 0;
+    ((baz)x)->d = 0;
+    __builtin_constant_p(i) ? foo(x, w, i) : bar(x, w, i);
+  }
+  return z - y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20000724-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000724-1.c
new file mode 100644
index 000000000..e4acdd7e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000724-1.c
@@ -0,0 +1,72 @@
+/* { dg-do run { target *-*-linux* *-*-gnu* } } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+extern void abort (void);
+extern void exit (int);
+
+struct s {
+  struct { int a; } a;
+  int b;
+  struct { struct { int a; } a; struct t { struct t *a, *b; } b; } c;
+};
+
+int bar(int (*fn)(void *), void *arg, unsigned long flags)
+{
+  return 0;
+}
+
+int baz(void *x)
+{
+  return 0;
+}
+
+void do_check (struct s *) asm ("do_check") __attribute__((regparm(1)));
+
+void __attribute__((regparm(1))) do_check(struct s *x)
+{
+  if (x->a.a || x->b || x->c.a.a)
+    abort();
+  if (x->c.b.a != &x->c.b || x->c.b.b != &x->c.b)
+    abort();
+}
+
+#define NT "\n\t"
+
+asm ("\n"
+"___checkme:"
+NT	"pushl %eax; pushl %ebx; pushl %ecx; pushl %edx; pushl %esi; pushl %edi"
+
+NT	"pushl $0; pushl $0; pushl $0; pushl $0; pushl $0"
+NT	"pushl $0; pushl $0; pushl $0; pushl $0; pushl $0"
+
+NT	"movl %ecx, %eax"
+NT	"call do_check"
+
+NT	"popl %eax; popl %eax; popl %eax; popl %eax; popl %eax"
+NT	"popl %eax; popl %eax; popl %eax; popl %eax; popl %eax"
+
+NT	"popl %edi; popl %esi; popl %edx; popl %ecx; popl %ebx;	popl %eax"
+NT	"ret"
+);
+
+extern inline void do_asm(struct s * x)
+{
+  asm volatile("call ___checkme" : : "c" (x) : "memory");
+}
+
+int foo(void)
+{
+  struct s x = { { 0 }, 0, { { 0 }, { &x.c.b, &x.c.b } } };
+  bar(baz, &x, 1);
+  do_asm(&x);
+  bar(baz, &x, 1);
+  do_asm(&x);
+  return 0;
+}
+
+int main()
+{
+  foo();
+  exit(0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20000807-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000807-1.c
new file mode 100644
index 000000000..efdf97b14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000807-1.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-Os -fpic" } */
+
+#include <string.h>
+
+typedef struct
+{
+  char *a;
+  char *b;
+} *foo;
+
+void
+bar (foo x)
+{
+  char *c = x->b;
+  char *d = (void *)0;
+  unsigned int e = 0, f = 0, g;
+  while (*c != ':')
+    if (*c == '%')
+      {
+        ++c;
+        switch (*c++)
+          {
+          case 'N':
+            g = strlen (x->a);
+            if (e + g >= f) {
+		char *h = d;
+		f += 256 + g;
+		d = (char *) __builtin_alloca (f);
+		memcpy (d, h, e);
+	    };
+            memcpy (&d[e], x->a, g);
+            e += g;
+            break;
+	  }
+      }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20000904-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000904-1.c
new file mode 100644
index 000000000..0fbce57e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20000904-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O0 -fpic" } */
+
+static struct {
+  unsigned short a, b, c, d;
+} x[10];
+
+int foo(int i)
+{
+  return ((*((char *)&x[i] + i)) | (*((char *)&x[i] + i)));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20001127-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20001127-1.c
new file mode 100644
index 000000000..b62c6f979
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20001127-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern inline float bar (float x)
+{
+  register long double value;
+  asm volatile ("frndint" : "=t" (value) : "0" (x));
+  return value;
+}
+
+float a;
+
+float foo (float b)
+{
+  return a + bar (b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20010520-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20010520-1.c
new file mode 100644
index 000000000..ab4ed16ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20010520-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-w" } */
+
+void f ()
+{
+  int i __asm__ ("%eax");
+  __asm__ volatile ("" : "=a" (i));
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20011009-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20011009-1.c
new file mode 100644
index 000000000..e79a475a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20011009-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+extern void exit (int);
+
+#ifdef __sun__
+#define COMMENT "/"
+#else
+#define COMMENT "#"
+#endif
+
+int main ()
+{
+  int x;
+
+  asm ("movl $26, %0 " COMMENT " 26 |-> reg \n\t"
+       "movl $28, %0" : "=r" (x));
+  if (x != 28)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20011029-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20011029-2.c
new file mode 100644
index 000000000..c1068de6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20011029-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int foo (int s)
+{
+  for (;;)
+    {
+      int a[32];
+      int y, z;
+      __asm__ __volatile__ ("" : "=c" (y), "=D" (z)
+			    : "a" (0), "0" (32), "1" (a) : "memory");
+      if (({ register char r;
+	     __asm__ __volatile__ ("" : "=q" (r)
+				   : "r" (s % 32), "m" (a[s / 32])
+				   : "cc"); r; }))
+        continue;
+      else if (({ register char r;
+		  __asm__ __volatile__ ("" : "=q" (r)
+					: "r" (0), "m" (a[0])
+					: "cc"); r; }))
+        continue;
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20011107-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20011107-1.c
new file mode 100644
index 000000000..c1cfe88a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20011107-1.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -mtune=k6" } */
+
+void
+foo (unsigned char *x, const unsigned char *y)
+{
+  int a = 6;
+  unsigned char *b;
+  for (;;)
+    {
+      unsigned char *c = x;
+
+      while (1)
+	{
+	  if (c + 2 < y)
+	    c += 3;
+	  else
+	    break;
+	}
+      b = x + a;
+      if (*c == 4 || *c == 5)
+	{
+	  unsigned char d = c[2];
+
+	  if (b[3] == 7 || b[3] == 8)
+	    {
+	      int e = b[3] == 8;
+	      if (d < b[4] * 8 && b[5 + d / 8] & (1 << (d % 8)))
+		e = !e;
+	      if (!e)
+		x[-3] = 26;
+	    }
+	}
+      else if (*c == 7 && b[3] == 8)
+	{
+	  int f;
+	  for (f = 0; f < (int) c[1]; f++)
+	    if (!(c[2 + f] == 0))
+	      break;
+	  if (f == c[1])
+	    x[-3] = 26;
+	}
+      x -= 2;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20011119-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20011119-1.c
new file mode 100644
index 000000000..9e85f6f5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20011119-1.c
@@ -0,0 +1,82 @@
+/* Test for reload failing to eliminate from argp to sp.  */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+static int ustrsize (const char *s);
+static int (*ucwidth) (int c);
+static int (*ugetxc) (const char **s);
+static int (*usetc) (char *s, int c);
+
+char *ustrzcat(char *dest, int size, const char *src)
+{
+   int pos = ustrsize(dest);
+   int c;
+
+   size -= pos + ucwidth(0);
+
+   while ((c = ugetxc(&src)) != 0) {
+      size -= ucwidth(c);
+      if (size < 0)
+         break;
+
+      pos += usetc(dest+pos, c);
+   }
+
+   usetc(dest+pos, 0);
+
+   return dest;
+}
+
+static int __attribute__((noinline))
+ustrsize (const char *s)
+{
+  return 0;
+}
+
+static int
+ucwidth_ (int c)
+{
+  return 1;
+}
+
+static int
+ugetxc_ (const char **s)
+{
+  return '\0';
+}
+
+static int
+usetc_ (char *s, int c)
+{
+  return 1;
+}
+
+int
+main()
+{
+  ucwidth = ucwidth_;
+  ugetxc = ugetxc_;
+  usetc = usetc_;
+
+  /* ??? It is impossible to explicitly modify the hard frame pointer.
+     This will run afoul of code in flow.c that declines to mark regs
+     in eliminate_regs in regs_ever_used.  Apparently, we have to wait
+     for reload to decide that it won't need a frame pointer before a
+     variable can be allocated to %ebp.
+
+     So save, restore, and clobber %ebp by hand.  */
+
+  asm ("pushl %%ebp\n\t"
+       "movl $-1, %%ebp\n\t"
+       "pushl $0\n\t"
+       "pushl $0\n\t"
+       "pushl $0\n\t"
+       "call %P0\n\t"
+       "addl $12, %%esp\n\t"
+       "popl %%ebp"
+       : : "i"(ustrzcat) : "memory" );
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20020201-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020201-3.c
new file mode 100644
index 000000000..9d7265457
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020201-3.c
@@ -0,0 +1,16 @@
+/* This testcase ICEd because a SFmode variable was given a MMX register
+   for which there is no movsf exists.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=i686 -mmmx -fno-strict-aliasing" } */
+
+struct A { unsigned int a, b; };
+
+void foo (struct A *x, int y, int z)
+{
+   const float d = 1.0;
+   float e = (float) y + z;
+
+   x->a = *(unsigned int *) &d;
+   x->b = *(unsigned int *) &e;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20020218-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020218-1.c
new file mode 100644
index 000000000..4d3d256af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020218-1.c
@@ -0,0 +1,35 @@
+/* Verify that X86-64 only SSE registers aren't restored on IA-32.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-final { scan-assembler-not "xmm8" } } */
+
+extern void abort (void);
+extern void exit (int);
+
+void *bar (void *p, void *q)
+{
+  if (p != (void *) 26 || q != (void *) 35)
+    abort ();
+  return (void *) 76;
+}
+
+void *foo (void **args)
+{
+  void *argcookie = &args[1];
+
+  __builtin_return (__builtin_apply (args[0], &argcookie,
+				     2 * sizeof (void *)));
+}
+
+int main (void)
+{
+  void *args[3];
+
+  args[0] = (void *) bar;
+  args[1] = (void *) 26;
+  args[2] = (void *) 35;
+  if (foo (args) != (void *) 76)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20020224-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020224-1.c
new file mode 100644
index 000000000..2905719fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020224-1.c
@@ -0,0 +1,41 @@
+/* PR target/5755
+   This testcase failed because the caller of a function returning struct
+   expected the callee to pop up the hidden return structure pointer,
+   while callee was actually not poping it up (as the hidden argument
+   was passed in register).  */
+/* { dg-do run } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+extern void abort (void);
+extern void exit (int);
+
+typedef struct {
+   int a1, a2;
+} A;
+
+A a;
+
+A __attribute__ ((regparm (2)))
+foo (int x)
+{
+  return a;
+}
+
+int __attribute__ ((regparm (2)))
+bar (int x)
+{
+  int r = foo(0).a2;
+  return r;
+}
+
+int
+main ()
+{
+  int f;
+  a.a1 = 530;
+  a.a2 = 980;
+  f = bar (0);
+  if (f != 980)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20020426-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020426-1.c
new file mode 100644
index 000000000..57690f1d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020426-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-msoft-float -mfp-ret-in-387" } */
+
+void f() {
+  __builtin_apply(0, 0, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20020523.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020523.c
new file mode 100644
index 000000000..0684d5feb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020523.c
@@ -0,0 +1,41 @@
+/* PR target/6753
+   This testcase was miscompiled because sse_mov?fcc_const0*
+   patterns were missing earlyclobber.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -msse -mfpmath=sse -ffast-math" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+float one = 1.f;
+
+void bar (float f)
+{
+  if (__builtin_memcmp (&one, &f, sizeof (float)))
+    abort ();
+}
+
+float foo (void)
+{
+  return 1.f;
+}
+
+typedef struct
+{
+  float t;
+} T;
+
+static void
+sse_test (void)
+{
+  int i;
+  T x[1];
+
+  for (i = 0; i < 1; i++)
+    {
+      x[i].t = foo ();
+      x[i].t = 0.f > x[i].t ? 0.f : x[i].t;
+      bar (x[i].t);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20020531-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020531-1.c
new file mode 100644
index 000000000..cd7cac347
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020531-1.c
@@ -0,0 +1,21 @@
+/* PR optimization/6842
+   This testcase caused ICE when trying to optimize V8QI subreg of VOIDmode
+   CONST_DOUBLE.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+
+typedef char __v8qi __attribute__ ((vector_size (8)));
+extern void abort (void);
+extern void exit (int);
+
+void foo (void)
+{
+  unsigned long long a = 0x0102030405060708LL;
+  unsigned long long b = 0x1020304050607080LL;
+  unsigned long long c;
+
+  c = (unsigned long long) __builtin_ia32_paddusb ((__v8qi) a, (__v8qi) b);
+  __builtin_ia32_emms ();
+  if (c != 0x1122334455667788LL)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20020616-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020616-1.c
new file mode 100644
index 000000000..5641826b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020616-1.c
@@ -0,0 +1,35 @@
+/* PR opt/6722 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#if !__PIC__
+register int k asm("%ebx");
+#elif __amd64
+register int k asm("%r12");
+#else
+register int k asm("%esi");
+#endif
+
+void __attribute__((noinline))
+foo()
+{
+  k = 1;
+}
+
+void test()
+{
+  int i;
+  for (i = 0; i < 10; i += k)
+    {
+      k = 0;
+      foo();
+    }
+}
+
+int main()
+{
+  int old = k;
+  test();
+  k = old;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20020729-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020729-1.c
new file mode 100644
index 000000000..7e1abafd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20020729-1.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=k6" } */
+
+static inline void *
+baz (void *s, unsigned long c, unsigned int count)
+{
+  int d0, d1;
+  __asm__ __volatile__ (""
+			: "=&c" (d0), "=&D" (d1)
+			:"a" (c), "q" (count), "0" (count / 4), "1" ((long) s)
+			:"memory");
+  return s;
+}
+
+struct A
+{
+  unsigned long *a;
+};
+
+inline static void *
+bar (struct A *x, int y)
+{
+  char *ptr;
+
+  ptr = (void *) x->a[y >> 12];
+  ptr += y % (1UL << 12);
+  return (void *) ptr;
+}
+
+int
+foo (struct A *x, unsigned int *y, int z, int u)
+{
+  int a, b, c, d, e;
+
+  z += *y;
+  c = z + u;
+  a = (z >> 12) + 1;
+  do
+    {
+      b = (a << 12);
+      d = b - z;
+      e = c - z;
+      if (e < d)
+	d = e;
+      baz (bar (x, z), 0, d);
+      z = b;
+      a++;
+    }
+  while (z < c);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20030217-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20030217-1.c
new file mode 100644
index 000000000..d2b24802b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20030217-1.c
@@ -0,0 +1,19 @@
+/* Test whether denormal floating point constants in hexadecimal notation
+   are parsed correctly.  */
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+/* { dg-require-effective-target large_long_double } */
+
+long double d = 0x0.0000003ffffffff00000p-16357L;
+long double e = 0x0.0000003ffffffff00000p-16356L;
+
+extern void abort (void);
+extern void exit (int);
+
+int
+main (void)
+{
+  if (d != e / 2.0)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20030217-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20030217-2.c
new file mode 100644
index 000000000..d0606a242
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20030217-2.c
@@ -0,0 +1,23 @@
+/* Test whether denormal floating point constants in hexadecimal notation
+   are parsed correctly.  */
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+
+long double d;
+long double e;
+
+long double f = 2.2250738585072014E-308L;
+
+extern void abort (void);
+extern void exit (int);
+
+int
+main (void)
+{
+   d = 0x0.0000003ffffffff00000p-1048L;
+   e = 0x0.0000003ffffffff00000p-1047L;
+  if (d != e / 2.0)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20030926-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20030926-1.c
new file mode 100644
index 000000000..ebde34085
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20030926-1.c
@@ -0,0 +1,18 @@
+/* PR optimization/11741  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -minline-all-stringops" } */
+/* { dg-options "-O2 -minline-all-stringops -march=pentium4" { target ia32 } } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+extern __SIZE_TYPE__ strlen (const char *);
+
+void
+foo (char *p)
+{
+  for (;;)
+    {
+      memcpy (p, p + 1, strlen (p));
+      p++;
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20040112-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20040112-1.c
new file mode 100644
index 000000000..168fd2f0b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20040112-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "testb" } } */
+ftn (char *sp)
+{
+  char status;
+
+  while (1)
+    {
+      *sp = 0xE8;
+      status = *(volatile char *) sp;
+      if (status & 0x80)
+	break;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20050113-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20050113-1.c
new file mode 100644
index 000000000..44deb30cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20050113-1.c
@@ -0,0 +1,6 @@
+/* PR middle-end/19164 */
+/* { dg-do compile } */
+/* { dg-options "-mmmx" } */
+
+typedef short int V __attribute__ ((vector_size (8)));
+static V v = (V) 0x00FF00FF00FF00FFLL;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20060125-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060125-1.c
new file mode 100644
index 000000000..ed9dcce84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060125-1.c
@@ -0,0 +1,30 @@
+/* PR rtl-optimization/25703 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -mtune=i486" } */
+
+extern void abort (void);
+
+struct a
+{
+        int a;
+        char b,c,d,e;
+};
+
+__attribute__ ((noinline))
+__attribute__ ((regparm(1))) t(struct a a)
+{
+        if (a.a!=1 || a.b!=1 || a.c!=1)
+                        abort();
+}
+
+int main()
+{
+        struct a a;
+        a.c=1;
+        a.a=1;
+        a.b=1;
+        t(a);
+        return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20060125-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060125-2.c
new file mode 100644
index 000000000..1747a634d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060125-2.c
@@ -0,0 +1,30 @@
+/* PR rtl-optimization/25703 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -mtune=pentiumpro" } */
+
+extern void abort (void);
+
+struct a
+{
+        int a;
+        char b,c,d,e;
+};
+
+__attribute__ ((noinline))
+__attribute__ ((regparm(1))) t(struct a a)
+{
+        if (a.a!=1 || a.b!=1 || a.c!=1)
+                        abort();
+}
+
+int main()
+{
+        struct a a;
+        a.c=1;
+        a.a=1;
+        a.b=1;
+        t(a);
+        return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20060218-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060218-1.c
new file mode 100644
index 000000000..b94cbd8c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060218-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+void
+foo (void)
+{
+  register int cc __asm ("cc"); /* { dg-error "invalid register name" } */
+  __asm ("" : : "r" (cc) : "cc");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-1.c
new file mode 100644
index 000000000..374d18aea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-std=gnu99 -msse2 -mpreferred-stack-boundary=4" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+__m128i __attribute__ ((__noinline__))
+vector_using_function ()
+{
+  volatile __m128i vx;	/* We want to force a vector-aligned store into the stack.  */
+  vx = _mm_xor_si128 (vx, vx);
+  return vx;
+}
+int __attribute__ ((__noinline__, __force_align_arg_pointer__))
+self_aligning_function (int x, int y)
+{
+  __m128i ignored = vector_using_function ();
+  return (x + y);
+}
+int g_1 = 20;
+int g_2 = 22;
+
+static void
+sse2_test (void)
+{
+  int result;
+  asm ("pushl %esi");		/* Disalign runtime stack.  */
+  result = self_aligning_function (g_1, g_2);
+  if (result != 42)
+    abort ();
+  asm ("popl %esi");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-2.c
new file mode 100644
index 000000000..d3a779cb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-std=gnu99 -mpreferred-stack-boundary=4" } */
+int
+outer_function (int x, int y)
+{
+  int __attribute__ ((__noinline__, __force_align_arg_pointer__))
+  nested_function (int x, int y)
+    {
+      return (x + y);
+    }
+  return (3 + nested_function (x, y));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-3.c
new file mode 100644
index 000000000..3370b9ec2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-3.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-std=gnu99 -msse2 -mstackrealign -mpreferred-stack-boundary=4" } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+__m128i __attribute__ ((__noinline__))
+vector_using_function ()
+{
+  volatile __m128i vx;	/* We want to force a vector-aligned store into the stack.  */
+  vx = _mm_xor_si128 (vx, vx);
+  return vx;
+}
+int __attribute__ ((__noinline__))
+self_aligning_function (int x, int y)
+{
+  __m128i ignored = vector_using_function ();
+  return (x + y);
+}
+int g_1 = 20;
+int g_2 = 22;
+
+static void
+sse2_test (void)
+{
+  int result;
+  asm ("pushl %esi");		/* Disalign runtime stack.  */
+  result = self_aligning_function (g_1, g_2);
+  if (result != 42)
+    abort ();
+  asm ("popl %esi");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-4.c
new file mode 100644
index 000000000..bf7693799
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060512-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mstackrealign -mpreferred-stack-boundary=4" } */
+int
+outer_function (int x, int y)
+{
+  int __attribute__ ((__noinline__))
+  nested_function (int x, int y)
+    {
+      return (x + y);
+    }
+  return (3 + nested_function (x, y));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20060821-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060821-1.c
new file mode 100644
index 000000000..29a9afe87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20060821-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3" } */
+/* { dg-final { scan-assembler-not "%mm" } } */
+/* PR 28825 */
+#include <pmmintrin.h>
+__m128 ggg(float* m)
+{
+  return (__m128) {m[0], m[5], m[10], m[10]};
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/20080723-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/20080723-1.c
new file mode 100644
index 000000000..a2ed5bf86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/20080723-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+extern void exit (int);
+
+static inline __attribute__((always_inline))
+void
+prefetch (void *x)
+{
+  asm volatile("prefetcht0 %0" : : "m" (*(unsigned long *)x));
+}
+
+struct hlist_head
+{
+  struct hlist_node *first;
+};
+
+struct hlist_node
+{
+  struct hlist_node *next;
+  unsigned long i_ino;
+};
+
+struct hlist_node * find_inode_fast(struct hlist_head *head, unsigned long ino)
+{
+  struct hlist_node *node;
+
+  for (node = head->first;
+       node && (prefetch (node->next), 1);
+       node = node->next)
+    {
+      if (node->i_ino == ino)
+	break;
+    }
+  return node ? node : 0;
+}
+
+struct hlist_node g2;
+struct hlist_node g1 = { &g2 };
+struct hlist_head h = { &g1 };
+
+int
+main()
+{
+  if (find_inode_fast (&h, 1) != 0)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-1.c
new file mode 100644
index 000000000..c4ea1e7d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-1.c
@@ -0,0 +1,22 @@
+/* Verify that -mno-fancy-math-387 works.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */
+/* { dg-final { scan-assembler "call\t(.*)sin" } } */
+/* { dg-final { scan-assembler "call\t(.*)cos" } } */
+/* { dg-final { scan-assembler "call\t(.*)sqrt" } } */
+/* { dg-final { scan-assembler "call\t(.*)atan2" } } */
+/* { dg-final { scan-assembler "call\t(.*)log" } } */
+/* { dg-final { scan-assembler "call\t(.*)exp" } } */
+/* { dg-final { scan-assembler "call\t(.*)tan" } } */
+/* { dg-final { scan-assembler "call\t(.*)fmod" } } */
+
+double f1(double x) { return __builtin_sin(x); }
+double f2(double x) { return __builtin_cos(x); }
+double f3(double x) { return __builtin_sqrt(x); }
+double f4(double x, double y) { return __builtin_atan2(x,y); }
+double f5(double x) { return __builtin_log(x); }
+double f6(double x) { return __builtin_exp(x); }
+double f7(double x) { return __builtin_tan(x); }
+double f8(double x, double y) { return __builtin_fmod(x,y); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-10.c
new file mode 100644
index 000000000..0ff1b2a7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-10.c
@@ -0,0 +1,20 @@
+/* PR tree-optimization/24964 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpmath=387 -mfancy-math-387" } */
+
+double fabs(double x);
+
+double test1(double x)
+{
+  double t = fabs(x);
+  return t*t;
+}
+
+double test2(double x)
+{
+  double t = -x;
+  return t*t;
+}
+
+/* { dg-final { scan-assembler-not "fchs" } } */
+/* { dg-final { scan-assembler-not "fabs" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-11.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-11.c
new file mode 100644
index 000000000..869f6061c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-11.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpmath=387 -mfancy-math-387" } */
+
+double foo(double x, double y)
+{
+  double t = -x * y;
+  return -t;
+}
+
+/* { dg-final { scan-assembler-not "fchs" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-12.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-12.c
new file mode 100644
index 000000000..62c1d483c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-12.c
@@ -0,0 +1,16 @@
+/* PR target/26915 */
+/* { dg-do compile } */
+/* { dg-options "-O -mfpmath=387 -mfancy-math-387" } */
+
+double testm0(void)
+{
+	return -0.0;
+}
+
+double testm1(void)
+{
+	return -1.0;
+}
+
+/* { dg-final { scan-assembler "fldz" } } */
+/* { dg-final { scan-assembler "fld1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-2.c
new file mode 100644
index 000000000..8d5dba1f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-2.c
@@ -0,0 +1,22 @@
+/* Verify that -march overrides -mno-fancy-math-387.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i686" } } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -march=i686 -mno-fancy-math-387" } */
+/* { dg-final { scan-assembler "fsin" } } */
+/* { dg-final { scan-assembler "fcos" } } */
+/* { dg-final { scan-assembler "fsqrt" } } */
+/* { dg-final { scan-assembler "fpatan" } } */
+/* { dg-final { scan-assembler "fyl2x" } } */
+/* { dg-final { scan-assembler "f2xm1" } } */
+/* { dg-final { scan-assembler "fptan" } } */
+/* { dg-final { scan-assembler "fprem" } } */
+
+double f1(double x) { return __builtin_sin(x); }
+double f2(double x) { return __builtin_cos(x); }
+double f3(double x) { return __builtin_sqrt(x); }
+double f4(double x, double y) { return __builtin_atan2(x,y); }
+double f5(double x) { return __builtin_log(x); }
+double f6(double x) { return __builtin_exp(x); }
+double f7(double x) { return __builtin_tan(x); }
+double f8(double x, double y) { return __builtin_fmod(x,y); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-3.c
new file mode 100644
index 000000000..1b8dc8bab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-3.c
@@ -0,0 +1,11 @@
+/* Verify that 387 mathematical constants are recognized.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpmath=387 -mfancy-math-387" } */
+/* { dg-final { scan-assembler "fldpi" } } */
+/* { dg-require-effective-target large_long_double } */
+
+long double add_pi(long double x)
+{
+  return x + 3.1415926535897932385128089594061862044L;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-4.c
new file mode 100644
index 000000000..27c48ed20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfancy-math-387" } */
+/* { dg-final { scan-assembler "fldpi" } } */
+/* { dg-require-effective-target large_long_double } */
+
+long double atanl (long double);
+
+long double pi()
+{
+  return 4.0 * atanl (1.0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-5.c
new file mode 100644
index 000000000..a39f77a58
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-5.c
@@ -0,0 +1,12 @@
+/* Verify that -mno-fancy-math-387 works.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */
+/* { dg-final { scan-assembler "call\t(.*)atan" } } */
+/* { dg-final { scan-assembler "call\t(.*)log1p" } } */
+/* { dg-final { scan-assembler "call\t(.*)drem" } } */
+
+double f1(double x) { return __builtin_atan(x); }
+double f2(double x) { return __builtin_log1p(x); }
+double f3(double x, double y) { return __builtin_drem(x,y); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-6.c
new file mode 100644
index 000000000..f9506ba79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-6.c
@@ -0,0 +1,12 @@
+/* Verify that -march overrides -mno-fancy-math-387.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i686" } } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -march=i686 -mno-fancy-math-387" } */
+/* { dg-final { scan-assembler "fpatan" } } */
+/* { dg-final { scan-assembler "fyl2xp1" } } */
+/* { dg-final { scan-assembler "fprem1" } } */
+
+double f1(double x) { return __builtin_atan(x); }
+double f2(double x) { return __builtin_log1p(x); }
+double f3(double x, double y) { return __builtin_drem(x,y); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-7.c
new file mode 100644
index 000000000..e01ed2e05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-7.c
@@ -0,0 +1,13 @@
+/* Verify that 387 fsincos instruction is generated.  */
+/* { dg-do compile } */
+/* { dg-options "-O -ffast-math -mfpmath=387 -mfancy-math-387" } */
+/* { dg-final { scan-assembler "fsincos" } } */
+
+extern double sin (double);
+extern double cos (double);
+
+double f1(double x)
+{
+  return sin(x) + cos (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-8.c
new file mode 100644
index 000000000..2dbcd740f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-8.c
@@ -0,0 +1,15 @@
+/* Verify that 387 fptan instruction is generated. Also check that
+   inherent load of 1.0 is used in further calculations.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -mfpmath=387 -mfancy-math-387" } */
+/* { dg-final { scan-assembler "fptan" } } */
+/* { dg-final { scan-assembler-not "fld1" } } */
+
+extern double tan (double);
+
+double f1(double x)
+{
+  return 1.0 / tan(x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/387-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-9.c
new file mode 100644
index 000000000..2667aa468
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/387-9.c
@@ -0,0 +1,35 @@
+/* Verify that 387 fsincos instruction is generated.  */
+/* { dg-do compile } */
+/* { dg-options "-O -funsafe-math-optimizations -mfpmath=387 -mfancy-math-387" } */
+
+extern double sin (double);
+extern double cos (double);
+extern void sincos (double, double *, double *);
+
+double f1(double x)
+{
+  double s, c;
+  sincos (x, &s, &c);
+  return s + c;
+}
+
+double f2(double x)
+{
+  double s, c, tmp;
+  sincos (x, &s, &tmp);
+  c = cos (x);
+  return s + c;
+}
+
+double f3(double x)
+{
+  double s, c, tmp;
+  sincos (x, &tmp, &c);
+  s = sin (x);
+  return s + c;
+}
+
+/* { dg-final { scan-assembler "fsincos" } } */
+/* { dg-final { scan-assembler-not "fsin " } } */
+/* { dg-final { scan-assembler-not "fcos" } } */
+/* { dg-final { scan-assembler-not "call" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnow-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnow-1.c
new file mode 100644
index 000000000..953dc2aef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnow-1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target 3dnow } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -m3dnow" } */
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mm3dnow.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnow-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnow-2.c
new file mode 100644
index 000000000..84b854087
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnow-2.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target 3dnow } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -m3dnow" } */
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mm3dnow.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnowA-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnowA-1.c
new file mode 100644
index 000000000..e502dc98f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnowA-1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target 3dnow } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow" } */
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mm3dnow.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnowA-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnowA-2.c
new file mode 100644
index 000000000..8475094ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/3dnowA-2.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target 3dnow } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow" } */
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mm3dnow.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/47698.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/47698.c
new file mode 100644
index 000000000..2c751093a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/47698.c
@@ -0,0 +1,10 @@
+/* { dg-options "-Os" } */
+/* { dg-final { scan-assembler-not "cmov" } } */
+
+extern volatile unsigned long mmio;
+unsigned long foo(int cond)
+{
+      if (cond)
+              return mmio;
+        return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/980211-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/980211-1.c
new file mode 100644
index 000000000..ad6312b37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/980211-1.c
@@ -0,0 +1,29 @@
+/* Test long double on x86 and x86-64. */
+
+/* { dg-do run } */
+/* { dg-options -O2 } */
+
+extern void abort (void);
+
+__inline int
+__signbitl0 (long double __x)
+{
+  union { long double __l; int __i[3]; } __u = { __l: __x };
+
+  return (__u.__i[2] & 0x8000) != 0;
+}
+
+void
+foo (long double x, long double y)
+{
+  long double z = x / y;
+  if (__signbitl0 (x) && __signbitl0 (z))
+    abort ();
+}
+
+int main()
+{
+  if (sizeof (long double) > sizeof (double))
+    foo (-0.0, -1.0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/980226-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/980226-1.c
new file mode 100644
index 000000000..d5587c71b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/980226-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+extern int printf (const char *, ...);
+extern double bar (double);
+
+int
+baz (double d)
+{
+  double e = bar (d);
+  asm volatile ("" : : : "st");
+  return printf ("%lg\n", e);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/980312-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/980312-1.c
new file mode 100644
index 000000000..3a125f259
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/980312-1.c
@@ -0,0 +1,25 @@
+/* { dg-do link } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+
+extern __inline  double
+__expm1 (double __x)
+{
+  double __temp;
+  __temp = 1.0;
+  return __temp;
+}
+extern __inline  double
+__sgn1 (double __x)
+{
+  return __x >= 0.0 ? 1.0 : -1.0;
+}
+double
+tanh (double __x)
+{
+  return  __expm1 (__x) * __sgn1 (-__x);
+}
+main ()
+{
+  return tanh (3.45) != 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/980313-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/980313-1.c
new file mode 100644
index 000000000..8698aa61c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/980313-1.c
@@ -0,0 +1,26 @@
+/* { dg-do link } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+
+extern __inline  double
+__expm1 (double __x)
+{
+  double __temp;
+  __temp -= 1.0;
+  return __temp;
+}
+extern __inline  double
+__sgn1 (double __x)
+{
+  return __x >= 0.0 ? 1.0 : -1.0;
+}
+double
+tanh (double __x)
+{
+  register double __exm1 = __expm1 (__x);
+  return __exm1 / (__exm1 + 2.0) * __sgn1 (-__x);
+}
+main ()
+{
+  return tanh (3.45) != 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/980414-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/980414-1.c
new file mode 100644
index 000000000..6a2130a59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/980414-1.c
@@ -0,0 +1,78 @@
+/* Test double on x86. */
+
+/* { dg-do run } */
+/* { dg-options -O2 } */
+
+extern void abort (void);
+
+static __inline  double
+mypow (double __x, double __y)
+{
+  register double __value, __exponent;
+  long __p = (long) __y;
+  if (__y == (double) __p)
+    {
+      double __r = 1.0;
+      if (__p == 0)
+	return 1.0;
+      if (__p < 0)
+	{
+	  __p = -__p;
+	  __x = 1.0 / __x;
+	}
+      while (1)
+	{
+	  if (__p & 1)
+	    __r *= __x;
+	  __p >>= 1;
+	  if (__p == 0)
+	    return __r;
+	  __x *= __x;
+	}
+    }
+  __asm __volatile__
+    ("fmul	%%st(1),%%st\n\t"	/* y * log2(x) */
+     "fst	%%st(1)\n\t"
+     "frndint\n\t"			/* int(y * log2(x)) */
+     "fxch  %%st(1)\n\t"
+     "fsub	%%st(1),%%st\n\t"	/* fract(y * log2(x)) */
+     "f2xm1\n\t"			/* 2^(fract(y * log2(x))) - 1 */
+     : "=t" (__value), "=u" (__exponent) :  "0" (__x), "1" (__y));
+  __value += 1.0;
+  __asm __volatile__
+    ("fscale"
+     : "=t" (__value) : "0" (__value), "u" (__exponent));
+  return __value;
+}
+
+const double E1 = 2.71828182845904523536028747135;
+
+double fact (double x)
+{
+  double corr;
+  corr = 1.0;
+  return corr * mypow(x/E1, x);
+}
+
+int main ()
+{
+  double y, z;
+
+  y = fact (46.2);
+  z = mypow (46.2/E1, 46.2);
+
+#if 0
+  printf ("%26.19e, %26.19e\n", y, z);
+#endif
+
+  if (y > z)
+    y -= z;
+  else
+    y = z - y;
+
+  y /= z;
+  if (y > 0.1)
+    abort ();
+ 
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/980520-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/980520-1.c
new file mode 100644
index 000000000..f4393307c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/980520-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+int bug(void)
+{
+        unsigned long a, b;
+   
+        __asm__(""
+                : "=d" (a)
+                :
+                : "memory");
+        __asm__ __volatile__(""
+                             :
+                             : "g" (b)
+                             : "memory");
+        return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/980709-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/980709-1.c
new file mode 100644
index 000000000..595b7cbaa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/980709-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options -O2 } */
+
+extern __inline__ int test_and_set_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+	__asm__ __volatile__( "" 
+		"btsl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (addr)
+		:"ir" (nr));
+	return oldbit;
+}
+struct buffer_head {
+	unsigned long b_state;		 
+};
+extern void lock_buffer(struct buffer_head * bh)
+{
+	while (test_and_set_bit(2 , &bh->b_state))
+		__wait_on_buffer(bh);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/990117-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/990117-1.c
new file mode 100644
index 000000000..a89dad119
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/990117-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+
+extern __inline  double
+fabs (double __x)
+{
+  register double __value;
+  __asm __volatile__
+    ("fabs"
+     : "=t" (__value) : "0" (__x));
+  return __value;
+}
+int
+foo ()
+{
+  int i, j, k;
+  double x = 0, y = ((i == j) ? 1 : 0);
+  for (i = 0; i < 10; i++)
+    ;
+  fabs (x - y);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/990130-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/990130-1.c
new file mode 100644
index 000000000..b2754fb08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/990130-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options -O0 } */
+
+typedef 	 int SItype	__attribute__ ((mode (SI)));
+typedef		 int DItype	__attribute__ ((mode (DI)));
+typedef unsigned int USItype	__attribute__ ((mode (SI)));
+  struct DIstruct {SItype low, high;};
+typedef union
+{
+  struct DIstruct s;
+  DItype ll;
+} DIunion;
+DItype
+__muldi3 (DItype u, DItype v)
+{
+  DIunion w;
+  DIunion uu, vv;
+  uu.ll = u,
+  vv.ll = v;
+  w.ll = ({DIunion __w;	__asm__ ("mull %3"	: "=a" ((USItype) (  __w.s.low )),	"=d" ((USItype) ( __w.s.high ))	: "%0" ((USItype) (   uu.s.low  )),	"rm" ((USItype) (    vv.s.low  ))) ;	__w.ll; }) ;
+  w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+	       + (USItype) uu.s.high * (USItype) vv.s.low);
+  return w.ll;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/990213-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/990213-2.c
new file mode 100644
index 000000000..21392bfca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/990213-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-fPIC" } */
+
+struct normal_encoding {};
+struct unknown_encoding {};
+static const struct normal_encoding latin1_encoding = {};
+
+struct encoding*
+XmlInitUnknownEncoding(void *mem)
+{
+  int i;
+  struct unknown_encoding *e = mem;
+  for (i = 0; i < sizeof(struct normal_encoding); i++)
+    ((char *)mem)[i] = ((char *)&latin1_encoding)[i];
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/990214-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/990214-1.c
new file mode 100644
index 000000000..3c203e9f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/990214-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-fPIC" } */
+
+typedef int int64_t __attribute__ ((__mode__ (  __DI__ ))) ;
+unsigned *
+bar (int64_t which)
+{
+	switch (which & 15 ) {
+	case 0 :
+		break;
+	case 1 :
+	case 5 :
+	case 2 : ;
+	}
+
+	return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/990424-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/990424-1.c
new file mode 100644
index 000000000..dd2913992
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/990424-1.c
@@ -0,0 +1,30 @@
+/* Test that stack alignment is preserved with pending_stack_adjust
+   with stdcall functions.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options -mpreferred-stack-boundary=4 } */
+
+void __attribute__((stdcall)) foo(int a, int b, int c);
+
+extern void abort (void);
+extern void exit (int);
+
+int
+main ()
+{
+  foo(1, 2, 3);
+  foo(1, 2, 3);
+  exit (0);
+}
+
+void __attribute__((stdcall))
+foo(int a, int b, int c)
+{
+  static int last_align = -1;
+  int dummy, align = (int)&dummy & 15;
+  if (last_align < 0)
+    last_align = align;
+  else if (align != last_align)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/990524-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/990524-1.c
new file mode 100644
index 000000000..295ffacc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/990524-1.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+
+typedef struct t_anim_info {
+   char        *new_filename;
+   long         first_frame_nr; 
+} t_anim_info;
+static int
+p_frames_to_multilayer(t_anim_info *ainfo_ptr,
+                      long range_from, long range_to)
+{
+  long    l_cur_frame_nr;
+  long    l_step, l_begin, l_end;
+  int  l_tmp_image_id;
+  int  l_new_image_id;
+  if(range_from > range_to)
+  {
+    l_step  = -1;      
+    if(range_to < ainfo_ptr->first_frame_nr)
+    { l_begin = ainfo_ptr->first_frame_nr; 
+     }
+  }
+  else
+  {
+    l_step  = 1;       
+  }
+  l_cur_frame_nr = l_begin;
+  while(1)
+  {
+    if(ainfo_ptr->new_filename == ((void *)0) )
+    if(l_tmp_image_id < 0)
+      gimp_image_delete(l_tmp_image_id);
+    if(l_cur_frame_nr == l_end)
+       break;
+    l_cur_frame_nr += l_step;
+  }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/991129-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/991129-1.c
new file mode 100644
index 000000000..038979a77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/991129-1.c
@@ -0,0 +1,16 @@
+/* Test against a problem in push_reload.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+unsigned long foo (unsigned long long x, unsigned long y)
+{
+    unsigned long a;
+
+    x += y;
+
+    asm ("" : "=a" (a) : "A" (x), "rm" (y));
+
+    return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/991209-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/991209-1.c
new file mode 100644
index 000000000..15a46cfc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/991209-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-ansi -pedantic" } */
+
+int foo ()
+{
+  return 1;
+}
+
+register char *stack_ptr __asm ("%esp"); /* { dg-warning "file-scope declaration of 'stack_ptr' specifies 'register'" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/991214-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/991214-1.c
new file mode 100644
index 000000000..74b603da7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/991214-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+/* Test against a problem with the combiner substituting explicit hard reg
+   references when it shouldn't.  */
+void foo (int, int) __attribute__ ((regparm (3)));
+void __attribute__((regparm(3))) foo (int x, int y)
+{
+  __asm__ __volatile__("" : : "d" (x), "r" (y));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/991230-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/991230-1.c
new file mode 100644
index 000000000..2c9f011ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/991230-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O -ffast-math -mtune=i486" } */
+
+/* Test that floating point greater-than tests are compiled correctly with
+   -ffast-math.  */
+
+extern void abort (void);
+
+static int gt (double a, double b)
+{
+  if (a > b)
+    return 4;
+  return 0;
+}
+
+static double zero = 0.0;
+
+int main ()
+{
+  if (gt (zero, zero))
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/abi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/abi-1.c
new file mode 100644
index 000000000..62b80ef40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/abi-1.c
@@ -0,0 +1,8 @@
+/* Make certain that we pass V2DF in the correct register for SSE1.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse -mno-sse2" } */
+
+typedef double v2df __attribute__((vector_size (16)));
+v2df foo (void) { return (v2df){ 1.0, 2.0 }; }
+
+/* { dg-final { scan-assembler-times "xmm0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/abi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/abi-2.c
new file mode 100644
index 000000000..39eafc250
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/abi-2.c
@@ -0,0 +1,9 @@
+/* Make certain that we pass __m256i in the correct register for AVX.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -mavx" } */
+/* { dg-options "-mabi=sysv -O1 -mavx" { target x86_64-*-mingw* } } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32)));
+__m256i foo (void) { return (__m256i){ 1, 2, 3, 4 }; }
+
+/* { dg-final { scan-assembler-times "ymm0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/addr-sel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/addr-sel-1.c
new file mode 100644
index 000000000..27623ffd9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/addr-sel-1.c
@@ -0,0 +1,17 @@
+/* PR rtl-optimization/28940 */
+/* Origin: Lev Makhlis <lmakhlis@bmc.com> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -mtune=i686" } */
+
+char a[10], b[10];
+
+int f(int i)
+{
+  return a[i+1] + b[i+1];
+}
+
+/* { dg-final { scan-assembler "a\\+1" } } */
+/* { dg-final { scan-assembler "b\\+1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c
new file mode 100644
index 000000000..daf5779b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-madx -O2" } */
+/* { dg-final { scan-assembler "adcx" } } */
+
+#include <x86intrin.h>
+
+volatile unsigned char c;
+volatile unsigned int x, y;
+unsigned int *sum;
+
+void extern
+adx_test (void)
+{
+    c = _addcarryx_u32 (c, x, y, sum);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c
new file mode 100644
index 000000000..d38d7ee78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-madx -O2" } */
+/* { dg-require-effective-target adx } */
+
+#include <x86intrin.h>
+#include "adx-check.h"
+
+static void
+adx_test (void)
+{
+  volatile unsigned char c;
+  unsigned int x;
+  volatile unsigned int y, sum_ref;
+
+  c = 0;
+  x = y = 0xFFFFFFFF;
+  sum_ref = 0xFFFFFFFE;
+
+  /* X = 0xFFFFFFFF, Y = 0xFFFFFFFF, C = 0.  */
+  c = _addcarryx_u32 (c, x, y, &x);
+  /* X = 0xFFFFFFFE, Y = 0xFFFFFFFF, C = 1.  */
+  c = _addcarryx_u32 (c, x, y, &x);
+  /* X = 0xFFFFFFFE, Y = 0xFFFFFFFF, C = 1.  */
+
+  if (x != sum_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-3.c
new file mode 100644
index 000000000..0ed33a950
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx32-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-adx -O2" } */
+/* { dg-final { scan-assembler "adcl" } } */
+
+#include <x86intrin.h>
+
+volatile unsigned char c;
+volatile unsigned int x, y;
+unsigned int *sum;
+
+void extern
+adx_test (void)
+{
+    c = _addcarryx_u32 (c, x, y, sum);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c
new file mode 100644
index 000000000..45beca851
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-madx -O2" } */
+/* { dg-final { scan-assembler "adcx" } } */
+
+#include <x86intrin.h>
+
+volatile unsigned char c;
+volatile unsigned long long x, y;
+unsigned long long *sum;
+
+void extern
+adx_test (void)
+{
+    c = _addcarryx_u64 (c, x, y, sum);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c
new file mode 100644
index 000000000..6aa2539c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run { target { ! ia32 } } } */
+/* { dg-options "-madx -O2" } */
+/* { dg-require-effective-target adx } */
+
+#include <x86intrin.h>
+#include "adx-check.h"
+
+static void
+adx_test (void)
+{
+  volatile unsigned char c;
+  unsigned long long x;
+  volatile unsigned long long y, sum_ref;
+
+  c = 0;
+  x = y = 0xFFFFFFFFFFFFFFFFLL;
+  sum_ref = 0xFFFFFFFFFFFFFFFELL;
+
+  /* X = 0xFFFFFFFFFFFFFFFF, Y = 0xFFFFFFFFFFFFFFFF, C = 0.  */
+  c = _addcarryx_u64 (c, x, y, &x);
+  /* X = 0xFFFFFFFFFFFFFFFE, Y = 0xFFFFFFFFFFFFFFFF, C = 1.  */
+  c = _addcarryx_u64 (c, x, y, &x);
+  /* X = 0xFFFFFFFFFFFFFFFE, Y = 0xFFFFFFFFFFFFFFFF, C = 1.  */
+
+  if (x != sum_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-3.c
new file mode 100644
index 000000000..4bbf74bfc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-addcarryx64-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mno-adx -O2" } */
+/* { dg-final { scan-assembler "adcq" } } */
+
+#include <x86intrin.h>
+
+volatile unsigned char c;
+volatile unsigned long long x, y;
+unsigned long long *sum;
+
+void extern
+adx_test (void)
+{
+    c = _addcarryx_u64 (c, x, y, sum);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-check.h
new file mode 100644
index 000000000..580cb49ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/adx-check.h
@@ -0,0 +1,40 @@
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void adx_test (void);
+
+static void __attribute__ ((noinline)) do_test (void)
+{
+  adx_test ();
+}
+
+  int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run ADX test only if host has ADX support.  */
+
+  if (__get_cpuid_max (0, NULL) < 7)
+    return 0;
+
+  __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+  if ((ebx & bit_ADX) == bit_ADX)
+    {
+      do_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+      return 0;
+    }
+#ifdef DEBUG
+  printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aes-avx-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/aes-avx-check.h
new file mode 100644
index 000000000..f2a4ead40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aes-avx-check.h
@@ -0,0 +1,41 @@
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+#include <stdlib.h>
+#include "cpuid.h"
+#include "avx-os-support.h"
+
+static void aes_avx_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  aes_avx_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AES + AVX test only if host has AES + AVX support.  */
+  if (((ecx & (bit_AVX | bit_OSXSAVE | bit_AES))
+       == (bit_AVX | bit_OSXSAVE | bit_AES))
+      && avx_os_support ())
+    {
+      do_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aes-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/aes-check.h
new file mode 100644
index 000000000..7e794423e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aes-check.h
@@ -0,0 +1,37 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void aes_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  aes_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AES test only if host has AES support.  */
+  if (ecx & bit_AES)
+    {
+      do_test ();
+#ifdef DEBUG
+    printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aesdec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesdec.c
new file mode 100644
index 000000000..affe3d19c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesdec.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i src2[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).  */
+static void
+init_data (__m128i *s1, __m128i *s2, __m128i *d)
+{
+  int i;
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
+			      0x68617929, 0x48692853);
+      d[i]  = _mm_setr_epi32 (0xb730392a, 0xb58eb95e,
+			      0xfaea2787, 0x138ac342);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, src2, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesdec_si128 (src1[i], src2[i]);
+      resdst[i + 1] = _mm_aesdec_si128 (src1[i + 1], src2[i + 1]);
+      resdst[i + 2] = _mm_aesdec_si128 (src1[i + 2], src2[i + 2]);
+      resdst[i + 3] = _mm_aesdec_si128 (src1[i + 3], src2[i + 3]);
+      resdst[i + 4] = _mm_aesdec_si128 (src1[i + 4], src2[i + 4]);
+      resdst[i + 5] = _mm_aesdec_si128 (src1[i + 5], src2[i + 5]);
+      resdst[i + 6] = _mm_aesdec_si128 (src1[i + 6], src2[i + 6]);
+      resdst[i + 7] = _mm_aesdec_si128 (src1[i + 7], src2[i + 7]);
+      resdst[i + 8] = _mm_aesdec_si128 (src1[i + 8], src2[i + 8]);
+      resdst[i + 9] = _mm_aesdec_si128 (src1[i + 9], src2[i + 9]);
+      resdst[i + 10] = _mm_aesdec_si128 (src1[i + 10], src2[i + 10]);
+      resdst[i + 11] = _mm_aesdec_si128 (src1[i + 11], src2[i + 11]);
+      resdst[i + 12] = _mm_aesdec_si128 (src1[i + 12], src2[i + 12]);
+      resdst[i + 13] = _mm_aesdec_si128 (src1[i + 13], src2[i + 13]);
+      resdst[i + 14] = _mm_aesdec_si128 (src1[i + 14], src2[i + 14]);
+      resdst[i + 15] = _mm_aesdec_si128 (src1[i + 15], src2[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp (edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aesdeclast.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesdeclast.c
new file mode 100644
index 000000000..417264a13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesdeclast.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i src2[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set of
+   input/output vectors).  */
+
+static void
+init_data (__m128i *s1, __m128i *s2, __m128i *d)
+{
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
+			      0x68617929, 0x48692853);
+      d[i] = _mm_setr_epi32 (0x72a593d0, 0xd410637b,
+			     0x6b317f95, 0xc5a391ef);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, src2, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesdeclast_si128 (src1[i], src2[i]);
+      resdst[i + 1] = _mm_aesdeclast_si128 (src1[i + 1], src2[i + 1]);
+      resdst[i + 2] = _mm_aesdeclast_si128 (src1[i + 2], src2[i + 2]);
+      resdst[i + 3] = _mm_aesdeclast_si128 (src1[i + 3], src2[i + 3]);
+      resdst[i + 4] = _mm_aesdeclast_si128 (src1[i + 4], src2[i + 4]);
+      resdst[i + 5] = _mm_aesdeclast_si128 (src1[i + 5], src2[i + 5]);
+      resdst[i + 6] = _mm_aesdeclast_si128 (src1[i + 6], src2[i + 6]);
+      resdst[i + 7] = _mm_aesdeclast_si128 (src1[i + 7], src2[i + 7]);
+      resdst[i + 8] = _mm_aesdeclast_si128 (src1[i + 8], src2[i + 8]);
+      resdst[i + 9] = _mm_aesdeclast_si128 (src1[i + 9], src2[i + 9]);
+      resdst[i + 10] = _mm_aesdeclast_si128 (src1[i + 10], src2[i + 10]);
+      resdst[i + 11] = _mm_aesdeclast_si128 (src1[i + 11], src2[i + 11]);
+      resdst[i + 12] = _mm_aesdeclast_si128 (src1[i + 12], src2[i + 12]);
+      resdst[i + 13] = _mm_aesdeclast_si128 (src1[i + 13], src2[i + 13]);
+      resdst[i + 14] = _mm_aesdeclast_si128 (src1[i + 14], src2[i + 14]);
+      resdst[i + 15] = _mm_aesdeclast_si128 (src1[i + 15], src2[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp (edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aesenc.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesenc.c
new file mode 100644
index 000000000..d2a8b6031
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesenc.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i src2[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).  */
+
+static void
+init_data (__m128i *s1, __m128i *s2, __m128i *d)
+{
+  int i;
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
+			      0x68617929, 0x48692853);
+      d[i] = _mm_setr_epi32 (0xded7e595, 0x8b104b58,
+			     0x9fdba3c5, 0xa8311c2f);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, src2, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesenc_si128 (src1[i], src2[i]);
+      resdst[i + 1] = _mm_aesenc_si128 (src1[i + 1], src2[i + 1]);
+      resdst[i + 2] = _mm_aesenc_si128 (src1[i + 2], src2[i + 2]);
+      resdst[i + 3] = _mm_aesenc_si128 (src1[i + 3], src2[i + 3]);
+      resdst[i + 4] = _mm_aesenc_si128 (src1[i + 4], src2[i + 4]);
+      resdst[i + 5] = _mm_aesenc_si128 (src1[i + 5], src2[i + 5]);
+      resdst[i + 6] = _mm_aesenc_si128 (src1[i + 6], src2[i + 6]);
+      resdst[i + 7] = _mm_aesenc_si128 (src1[i + 7], src2[i + 7]);
+      resdst[i + 8] = _mm_aesenc_si128 (src1[i + 8], src2[i + 8]);
+      resdst[i + 9] = _mm_aesenc_si128 (src1[i + 9], src2[i + 9]);
+      resdst[i + 10] = _mm_aesenc_si128 (src1[i + 10], src2[i + 10]);
+      resdst[i + 11] = _mm_aesenc_si128 (src1[i + 11], src2[i + 11]);
+      resdst[i + 12] = _mm_aesenc_si128 (src1[i + 12], src2[i + 12]);
+      resdst[i + 13] = _mm_aesenc_si128 (src1[i + 13], src2[i + 13]);
+      resdst[i + 14] = _mm_aesenc_si128 (src1[i + 14], src2[i + 14]);
+      resdst[i + 15] = _mm_aesenc_si128 (src1[i + 15], src2[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp (edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aesenclast.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesenclast.c
new file mode 100644
index 000000000..fd72597e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesenclast.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i src2[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one
+   set of input/output vectors).  */
+
+static void
+init_data (__m128i *s1, __m128i *s2, __m128i *d)
+{
+  int i;
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      s2[i] = _mm_setr_epi32 (0x726f6e5d, 0x5b477565,
+			      0x68617929, 0x48692853);
+      d[i] = _mm_setr_epi32 (0x53fdc611, 0x177ec425,
+			     0x938c5964, 0xc7fb881e);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, src2, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesenclast_si128 (src1[i], src2[i]);
+      resdst[i + 1] = _mm_aesenclast_si128 (src1[i + 1], src2[i + 1]);
+      resdst[i + 2] = _mm_aesenclast_si128 (src1[i + 2], src2[i + 2]);
+      resdst[i + 3] = _mm_aesenclast_si128 (src1[i + 3], src2[i + 3]);
+      resdst[i + 4] = _mm_aesenclast_si128 (src1[i + 4], src2[i + 4]);
+      resdst[i + 5] = _mm_aesenclast_si128 (src1[i + 5], src2[i + 5]);
+      resdst[i + 6] = _mm_aesenclast_si128 (src1[i + 6], src2[i + 6]);
+      resdst[i + 7] = _mm_aesenclast_si128 (src1[i + 7], src2[i + 7]);
+      resdst[i + 8] = _mm_aesenclast_si128 (src1[i + 8], src2[i + 8]);
+      resdst[i + 9] = _mm_aesenclast_si128 (src1[i + 9], src2[i + 9]);
+      resdst[i + 10] = _mm_aesenclast_si128 (src1[i + 10], src2[i + 10]);
+      resdst[i + 11] = _mm_aesenclast_si128 (src1[i + 11], src2[i + 11]);
+      resdst[i + 12] = _mm_aesenclast_si128 (src1[i + 12], src2[i + 12]);
+      resdst[i + 13] = _mm_aesenclast_si128 (src1[i + 13], src2[i + 13]);
+      resdst[i + 14] = _mm_aesenclast_si128 (src1[i + 14], src2[i + 14]);
+      resdst[i + 15] = _mm_aesenclast_si128 (src1[i + 15], src2[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp(edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aesimc.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesimc.c
new file mode 100644
index 000000000..676f919f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aesimc.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i src1[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).   */
+
+static void
+init_data (__m128i *s1, __m128i *d)
+{
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x5d53475d, 0x63746f72,
+			      0x73745665, 0x7b5b5465);
+      d[i] = _mm_setr_epi32 (0x81c3b3e5, 0x2b18330a,
+			     0x44b109c8, 0x627a6f66);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i] = _mm_aesimc_si128 (src1[i]);
+      resdst[i + 1] = _mm_aesimc_si128 (src1[i + 1]);
+      resdst[i + 2] = _mm_aesimc_si128 (src1[i + 2]);
+      resdst[i + 3] = _mm_aesimc_si128 (src1[i + 3]);
+      resdst[i + 4] = _mm_aesimc_si128 (src1[i + 4]);
+      resdst[i + 5] = _mm_aesimc_si128 (src1[i + 5]);
+      resdst[i + 6] = _mm_aesimc_si128 (src1[i + 6]);
+      resdst[i + 7] = _mm_aesimc_si128 (src1[i + 7]);
+      resdst[i + 8] = _mm_aesimc_si128 (src1[i + 8]);
+      resdst[i + 9] = _mm_aesimc_si128 (src1[i + 9]);
+      resdst[i + 10] = _mm_aesimc_si128 (src1[i + 10]);
+      resdst[i + 11] = _mm_aesimc_si128 (src1[i + 11]);
+      resdst[i + 12] = _mm_aesimc_si128 (src1[i + 12]);
+      resdst[i + 13] = _mm_aesimc_si128 (src1[i + 13]);
+      resdst[i + 14] = _mm_aesimc_si128 (src1[i + 14]);
+      resdst[i + 15] = _mm_aesimc_si128 (src1[i + 15]);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp(edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aeskeygenassist.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aeskeygenassist.c
new file mode 100644
index 000000000..f033bd6a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aeskeygenassist.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-require-effective-target aes } */
+/* { dg-options "-O2 -maes" } */
+
+#ifndef CHECK_H
+#define CHECK_H "aes-check.h"
+#endif
+
+#ifndef TEST
+#define TEST aes_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+#define IMM8 1
+
+static __m128i src1[NUM];
+static __m128i edst[NUM];
+
+static __m128i resdst[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).  */
+
+static void
+init_data (__m128i *s1, __m128i *d)
+{
+  int i;
+  for (i = 0; i < NUM; i++)
+    {
+      s1[i] = _mm_setr_epi32 (0x16157e2b, 0xa6d2ae28,
+			      0x8815f7ab, 0x3c4fcf09);
+      d[i] = _mm_setr_epi32 (0x24b5e434, 0x3424b5e5,
+			     0xeb848a01, 0x01eb848b);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (src1, edst);
+
+  for (i = 0; i < NUM; i += 16)
+    {
+      resdst[i]  = _mm_aeskeygenassist_si128 (src1[i], IMM8);
+      resdst[i + 1] = _mm_aeskeygenassist_si128 (src1[i + 1], IMM8);
+      resdst[i + 2] = _mm_aeskeygenassist_si128 (src1[i + 2], IMM8);
+      resdst[i + 3] = _mm_aeskeygenassist_si128 (src1[i + 3], IMM8);
+      resdst[i + 4] = _mm_aeskeygenassist_si128 (src1[i + 4], IMM8);
+      resdst[i + 5] = _mm_aeskeygenassist_si128 (src1[i + 5], IMM8);
+      resdst[i + 6] = _mm_aeskeygenassist_si128 (src1[i + 6], IMM8);
+      resdst[i + 7] = _mm_aeskeygenassist_si128 (src1[i + 7], IMM8);
+      resdst[i + 8] = _mm_aeskeygenassist_si128 (src1[i + 8], IMM8);
+      resdst[i + 9] = _mm_aeskeygenassist_si128 (src1[i + 9], IMM8);
+      resdst[i + 10] = _mm_aeskeygenassist_si128 (src1[i + 10], IMM8);
+      resdst[i + 11] = _mm_aeskeygenassist_si128 (src1[i + 11], IMM8);
+      resdst[i + 12] = _mm_aeskeygenassist_si128 (src1[i + 12], IMM8);
+      resdst[i + 13] = _mm_aeskeygenassist_si128 (src1[i + 13], IMM8);
+      resdst[i + 14] = _mm_aeskeygenassist_si128 (src1[i + 14], IMM8);
+      resdst[i + 15] = _mm_aeskeygenassist_si128 (src1[i + 15], IMM8);
+    }
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp(edst + i, resdst + i, sizeof (__m128i)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret1.c
new file mode 100644
index 000000000..6d46dc5ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret1.c
@@ -0,0 +1,29 @@
+/* target/36834 */
+/* Check that, with keep_aggregate_return_pointer attribute,  callee does
+   not pop the stack for the implicit pointer arg when returning a large
+   structure in memory.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+
+struct foo {
+  int a;
+  int b;
+  int c;
+  int d;
+};
+
+__attribute__ ((callee_pop_aggregate_return(0)))
+struct foo
+bar (void)
+{
+  struct foo retval;
+  retval.a = 1;
+  retval.b = 2;
+  retval.c = 3;
+  retval.d = 4;
+  return retval;
+}
+
+/* { dg-final { scan-assembler-not "ret\[ \t\]\\\$4" } } */
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret2.c
new file mode 100644
index 000000000..16e0109ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret2.c
@@ -0,0 +1,29 @@
+/* target/36834 */
+/* Check that, with dont_keep_aggregate_return_pointer attribute,  callee
+   pops the stack for the implicit pointer arg when returning a large
+   structure in memory.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+
+struct foo {
+  int a;
+  int b;
+  int c;
+  int d;
+};
+
+__attribute__ ((callee_pop_aggregate_return(1)))
+struct foo
+bar (void)
+{
+  struct foo retval;
+  retval.a = 1;
+  retval.b = 2;
+  retval.c = 3;
+  retval.d = 4;
+  return retval;
+}
+
+/* { dg-final { scan-assembler "ret\[ \t\]\\\$4" } } */
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret3.c
new file mode 100644
index 000000000..e3c5b0943
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret3.c
@@ -0,0 +1,28 @@
+/* Check that, with keep_aggregate_return_pointer attribute,  callee does
+   not pop the stack for the implicit pointer arg when returning a large
+   structure in memory.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+
+struct foo {
+  int a;
+  int b;
+  int c;
+  int d;
+};
+
+__attribute__ ((ms_abi))
+struct foo
+bar (void)
+{
+  struct foo retval;
+  retval.a = 1;
+  retval.b = 2;
+  retval.c = 3;
+  retval.d = 4;
+  return retval;
+}
+
+/* { dg-final { scan-assembler-not "ret\[ \t\]\\\$4" } } */
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret4.c
new file mode 100644
index 000000000..6e70f49f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/aggregate-ret4.c
@@ -0,0 +1,28 @@
+/* Check that, with dont_keep_aggregate_return_pointer attribute,  callee
+   pops the stack for the implicit pointer arg when returning a large
+   structure in memory.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+
+struct foo {
+  int a;
+  int b;
+  int c;
+  int d;
+};
+
+__attribute__ ((sysv_abi))
+struct foo
+bar (void)
+{
+  struct foo retval;
+  retval.a = 1;
+  retval.b = 2;
+  retval.c = 3;
+  retval.d = 4;
+  return retval;
+}
+
+/* { dg-final { scan-assembler "ret\[ \t\]\\\$4" } } */
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/alias-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/alias-1.c
new file mode 100644
index 000000000..a556259a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/alias-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-alias "" } */
+
+int yum;
+void dessert (void) { ++yum; }
+extern void jelly (void) __attribute__ ((alias ("dessert"), weak));
+extern void wobbly (void) __attribute__ ((alias ("jelly"), weak));
+
+/* { dg-final { scan-assembler "wobbly" } } */
+/* { dg-final { scan-assembler "jelly" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-1.c
new file mode 100644
index 000000000..f62284f43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-1.c
@@ -0,0 +1,28 @@
+/* Test for stack alignment when PREFERRED_STACK_BOUNDARY < alignment
+   of local variable.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */
+/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } { "*" } { "" } } */
+
+#include <stddef.h>
+
+#define ALIGNMENT 128
+
+typedef int aligned __attribute__((aligned(ALIGNMENT)));
+extern void abort(void);
+
+__attribute__ ((noinline))
+void check(void * a)
+{
+  if (((ptrdiff_t)a & (ALIGNMENT-1)) != 0)
+    abort();
+}
+
+int main()
+{
+  aligned a = 1;
+  check(&a);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-2.c
new file mode 100644
index 000000000..b81758918
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-2.c
@@ -0,0 +1,26 @@
+/* Test for stack alignment when PREFERRED_STACK_BOUNDARY > alignment
+   of local variable.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */
+/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-skip-if "Options about stack-boundary aren't support" { x86_64-*-mingw* } { "*" } { "" } } */
+#include <stddef.h>
+
+#define ALIGNMENT 32
+typedef int aligned __attribute__((aligned(ALIGNMENT)));
+extern void abort(void);
+
+__attribute__ ((noinline))
+void check(void * a)
+{
+  if (((ptrdiff_t)a & (ALIGNMENT-1)) != 0)
+    abort();
+}
+
+int main()
+{
+  aligned a = 1;
+  check(&a);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-3.c
new file mode 100644
index 000000000..b3a000ace
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/align-main-3.c
@@ -0,0 +1,14 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target { { *-*-linux* *-*-gnu* } && ia32 } } } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=4 -mincoming-stack-boundary=2" } */
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*foo" } } */
+/* { dg-final { scan-assembler-not "jmp\[\\t \]*foo" } } */
+
+extern int foo (void);
+
+int
+main ()
+{
+  return foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/all_one_m128i.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/all_one_m128i.c
new file mode 100644
index 000000000..fa973e420
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/all_one_m128i.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+__m128i foo ()
+{
+  __m128i minus_1 = (__m128i) (__v4si) { -1, -1, -1, -1 };
+
+  return minus_1;
+}
+
+/* { dg-final { scan-assembler "pcmpeqd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/all_one_m256i.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/all_one_m256i.c
new file mode 100644
index 000000000..1c3ca08b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/all_one_m256i.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx2" } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32)));
+typedef int __v8si __attribute__ ((__vector_size__ (32)));
+
+__m256i foo ()
+{
+  __m256i minus_1 = (__m256i) (__v8si) { -1, -1, -1, -1, -1, -1, -1, -1 };
+
+  return minus_1;
+}
+
+/* { dg-final { scan-assembler "vpcmpeqd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-1.c
new file mode 100644
index 000000000..8988f79c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-mno-sse" } */
+/* { dg-additional-options "-mabi=sysv" { target *-*-mingw* } } */
+
+double foo(void) { return 0; }	/* { dg-error "SSE disabled" } */
+void bar(double x) { }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-2.c
new file mode 100644
index 000000000..6146e8efa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-2.c
@@ -0,0 +1,8 @@
+/* PR target/26223 */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-mno-80387" } */
+/* { dg-additional-options "-mabi=sysv" { target *-*-mingw* } } */
+
+long double foo(long double x) { return x; } /* { dg-error "x87 disabled" } */
+long double bar(long double x) { return x; }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-3.c
new file mode 100644
index 000000000..6b7bf6a6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -fomit-frame-pointer -mno-sse -mtune=k8" } */
+/* { dg-final { scan-assembler "subq\[\\t \]*\\\$88,\[\\t \]*%rsp" } } */
+/* { dg-final { scan-assembler-not "subq\[\\t \]*\\\$216,\[\\t \]*%rsp" } } */
+
+#include <stdarg.h>
+
+void foo (va_list va_arglist);
+
+void
+test (int a1, ...)
+{
+  va_list va_arglist;
+  va_start (va_arglist, a1);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-4.c
new file mode 100644
index 000000000..e88fde6af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-4.c
@@ -0,0 +1,46 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mno-sse" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+int n1 = 30;
+int n2 = 324;
+void *n3 = (void *) &n2;
+int n4 = 407;
+
+int e1;
+int e2;
+void *e3;
+int e4;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e2 = va_arg (va_arglist, int);
+  e3 = va_arg (va_arglist, void *);
+  e4 = va_arg (va_arglist, int);
+}
+
+static void
+__attribute__((noinline))
+test (int a1, ...)
+{
+  e1 = a1;
+  va_list va_arglist;
+  va_start (va_arglist, a1);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+int
+main ()
+{
+  test (n1, n2, n3, n4);
+  assert (n1 == e1);
+  assert (n2 == e2);
+  assert (n3 == e3);
+  assert (n4 == e4);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-5.c
new file mode 100644
index 000000000..da2a14ee4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-5.c
@@ -0,0 +1,63 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-O2" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+int n1 = 30;
+double n2 = 324;
+double n3 = 39494.94;
+double n4 = 407;
+double n5 = 32.304;
+double n6 = 394.14;
+double n7 = 4.07;
+double n8 = 32.4;
+double n9 = 314.194;
+double n10 = 0.1407;
+
+int e1;
+double e2;
+double e3;
+double e4;
+double e5;
+double e6;
+double e7;
+double e8;
+double e9;
+double e10;
+
+static void
+__attribute__((noinline))
+test (int a1, ...)
+{
+  e1 = a1;
+  va_list va_arglist;
+  va_start (va_arglist, a1);
+  e2 = va_arg (va_arglist, double);
+  e3 = va_arg (va_arglist, double);
+  e4 = va_arg (va_arglist, double);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, double);
+  e7 = va_arg (va_arglist, double);
+  e8 = va_arg (va_arglist, double);
+  e9 = va_arg (va_arglist, double);
+  e10 = va_arg (va_arglist, double);
+  va_end (va_arglist);
+}
+
+int
+main ()
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10);
+  assert (n1 == e1);
+  assert (n2 == e2);
+  assert (n3 == e3);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (n6 == e6);
+  assert (n7 == e7);
+  assert (n8 == e8);
+  assert (n9 == e9);
+  assert (n10 == e10);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-6.c
new file mode 100644
index 000000000..6d076ad38
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/amd64-abi-6.c
@@ -0,0 +1,70 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-O2" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+int n1 = 30;
+double n2 = 324;
+double n3 = 39494.94;
+double n4 = 407;
+double n5 = 32.304;
+double n6 = 394.14;
+double n7 = 4.07;
+double n8 = 32.4;
+double n9 = 314.194;
+double n10 = 0.1407;
+
+int e1;
+double e2;
+double e3;
+double e4;
+double e5;
+double e6;
+double e7;
+double e8;
+double e9;
+double e10;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e2 = va_arg (va_arglist, double);
+  e3 = va_arg (va_arglist, double);
+  e4 = va_arg (va_arglist, double);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, double);
+  e7 = va_arg (va_arglist, double);
+  e8 = va_arg (va_arglist, double);
+  e9 = va_arg (va_arglist, double);
+  e10 = va_arg (va_arglist, double);
+}
+
+static void
+__attribute__((noinline))
+test (int a1, ...)
+{
+  va_list va_arglist;
+  e1 = a1;
+  va_start (va_arglist, a1);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+int
+main ()
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10);
+  assert (n1 == e1);
+  assert (n2 == e2);
+  assert (n3 == e3);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (n6 == e6);
+  assert (n7 == e7);
+  assert (n8 == e8);
+  assert (n9 == e9);
+  assert (n10 == e10);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/andor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/andor-1.c
new file mode 100644
index 000000000..6cc12b348
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/andor-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "andl" } } */
+
+unsigned int foo(unsigned int x)
+{
+  unsigned int t = x & ~1;
+  return t | 1;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/andor-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/andor-2.c
new file mode 100644
index 000000000..eacc7b1e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/andor-2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic" } */
+
+int h(int x, int y)
+{
+  if ((x >= 0 && x <= 1) && (y >= 0 && y <= 1))
+    return x && y;
+  else
+    return -1;
+}
+
+int g(int x, int y)
+{
+  if ((x >= 0 && x <= 1) && (y >= 0 && y <= 1))
+    return x || y;
+  else
+    return -1;
+}
+
+int f(int x, int y)
+{
+  if (x != 0 && x != 1)
+    return -2;
+
+  else
+    return !x;
+}
+
+/* { dg-final { scan-assembler-not "setne" } } */
+/* { dg-final { scan-assembler-not "sete" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-1.c
new file mode 100644
index 000000000..cd60a09bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "" } */
+
+register unsigned int EAX asm ("r14"); /* { dg-error "register name" } */
+
+void foo ()
+{
+  EAX = 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-2.c
new file mode 100644
index 000000000..09a545517
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-2.c
@@ -0,0 +1,62 @@
+/* PR opt/13862 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O" } */
+
+typedef struct _fame_syntax_t_ {
+} fame_syntax_t;
+
+typedef struct _fame_bitbuffer_t_
+{
+  unsigned char * base;
+  unsigned char * data;
+  unsigned long shift;
+} fame_bitbuffer_t;
+
+#define fast_bitbuffer_write(data, shift, c, l)				\
+{									\
+  int d;								\
+									\
+  asm("add %1, %%ecx\n"            /* ecx = shift + length */		\
+      "shrd %%cl, %2, %3\n"        /* adjust code to fit in */		\
+      "shr %%cl, %2\n"             /* adjust code to fit in */		\
+      "mov %%ecx, %1\n"            /* shift += length */		\
+      "bswap %2\n"                 /* reverse byte order of code */	\
+      "shr $5, %%ecx\n"            /* get dword increment */            \
+      "or %2, (%0)\n"              /* put first 32 bits */		\
+      "bswap %3\n"                 /* reverse byte order of code */	\
+      "lea   (%0, %%ecx, 4), %0\n" /* data += (ecx>32) */		\
+      "andl $31, %1\n"             /* mask shift */			\
+      "orl %3, (%0)\n"             /* put last 32 bits */		\
+      : "=r"(data), "=r"(shift), "=a"(d), "=d"(d), "=c"(d)		\
+      : "0"(data), "1"(shift), "2"((unsigned long) c), "3"(0),		\
+	"c"((unsigned long) l)						\
+      : "memory");							\
+}
+
+#define bitbuffer_write(bb, c, l) \
+  fast_bitbuffer_write((bb)->data, (bb)->shift, c, l)
+
+typedef enum { frame_type_I, frame_type_P } frame_type_t;
+
+typedef struct _fame_syntax_mpeg1_t_ {
+  fame_bitbuffer_t buffer;
+  frame_type_t frame_type;
+} fame_syntax_mpeg1_t;
+
+#define FAME_SYNTAX_MPEG1(x) ((fame_syntax_mpeg1_t *) x)
+
+void mpeg1_start_picture(fame_syntax_t *syntax)
+{
+  fame_syntax_mpeg1_t *syntax_mpeg1 = FAME_SYNTAX_MPEG1(syntax);
+  bitbuffer_write(&syntax_mpeg1->buffer, 0xFFFF, 16); 
+
+  switch(syntax_mpeg1->frame_type) {
+    case frame_type_I:
+      bitbuffer_write(&syntax_mpeg1->buffer, 0, 1);  
+    break;
+    case frame_type_P:
+      bitbuffer_write(&syntax_mpeg1->buffer, 0, 1);
+    break;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-3.c
new file mode 100644
index 000000000..ec37898ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-3.c
@@ -0,0 +1,35 @@
+/* PR inline-asm/6806 */
+/* { dg-do run } */
+/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+volatile int out = 1;
+volatile int a = 2;
+volatile int b = 4;
+volatile int c = 8;
+volatile int d = 16;
+volatile int e = 32;
+volatile int f = 64;
+
+int
+main ()
+{
+  asm volatile ("xorl %%eax, %%eax	\n\t"
+		"xorl %%esi, %%esi	\n\t"
+		"addl %1, %0		\n\t"
+		"addl %2, %0		\n\t"
+		"addl %3, %0		\n\t"
+		"addl %4, %0		\n\t"
+		"addl %5, %0		\n\t"
+		"addl %6, %0"
+		: "+r" (out)
+		: "r" (a), "r" (b), "r" (c), "g" (d), "g" (e), "g" (f)
+		: "%eax", "%esi");
+
+  if (out != 127)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-4.c
new file mode 100644
index 000000000..b86801032
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-4.c
@@ -0,0 +1,47 @@
+/* Test if functions marked __attribute__((used)), but with address never
+   taken in C code, don't use alternate calling convention for local
+   functions on IA-32.  */
+/* { dg-do run } */
+/* The asm in this test uses an absolute address.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+static int foo (int, int, int, int) __asm ("foo");
+static __attribute__((noinline, used)) int
+foo (int i, int j, int k, int l)
+{
+  return i + j + k + l;
+}
+
+void
+bar (void)
+{
+  if (foo (1, 2, 3, 4) != 10)
+    abort ();
+}
+
+int (*fn) (int, int, int, int);
+
+void
+baz (void)
+{
+  /* Darwin loads 64-bit regions above the 4GB boundary so
+     we need to use this instead.  */
+#if defined (__LP64__) && defined (__MACH__)
+  __asm ("leaq foo(%%rip), %0" : "=r" (fn));
+#else
+  __asm ("movl $foo, %k0" : "=r" (fn));
+#endif
+  if (fn (2, 3, 4, 5) != 14)
+    abort ();
+}
+
+int
+main (void)
+{
+  bar ();
+  baz ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-5.c
new file mode 100644
index 000000000..d41298023
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-5.c
@@ -0,0 +1,26 @@
+/* PR inline-asm/11676 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+static int bar(int x) __asm__("bar") __attribute__((regparm(1)));
+static int __attribute__((regparm(1), noinline, used))
+bar(int x)
+{
+  if (x != 0)
+    abort ();
+}
+
+static int __attribute__((regparm(1), noinline))
+foo(int x)
+{
+  x = 0;
+  __asm__ __volatile__("call bar" : "=a"(x) : "a"(x));
+}
+
+int main()
+{
+  foo(1);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-6.c
new file mode 100644
index 000000000..6aa37ef42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-6.c
@@ -0,0 +1,16 @@
+/* PR rtl-optimization/44174 */
+/* Testcase by Jakub Jelinek <jakub@gcc.gnu.org> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -fpic" { target fpic } } */
+
+int f0 (int, int, int, int, int);
+int f1 (void);
+
+void
+f2 (void)
+{
+  unsigned v1, v2, v3, v4;
+  __asm__ ("" : "=a" (v1), "=d" (v2), "=c" (v3), "=r" (v4));
+  f0 (f1 (), f1 (), f1 (), f1 (), (v4 >> 8) & 0xff);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-dialect-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-dialect-1.c
new file mode 100644
index 000000000..b29017eeb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-dialect-1.c
@@ -0,0 +1,16 @@
+/* { dg-options "-masm=intel" } */
+/* { dg-require-effective-target masm_intel } */
+
+extern void abort (void);
+
+int
+main (void)
+{
+  int f = 0;
+  asm ("{movl $42, %%eax | mov eax, 42}" : :);
+  asm ("{movl $41, %0||mov %0, 43}" : "=r"(f));
+  if (f != 42)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-dialect-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-dialect-2.c
new file mode 100644
index 000000000..8386d64e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/asm-dialect-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-masm=att" } */
+/* { dg-final { scan-assembler "%{a}|" } } */
+
+int a, b;
+
+void f()
+{
+  /* Check for escaped curly braces support.  */
+  asm volatile ("{%%%{a%}%||%%%}b}" : :);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c
new file mode 100644
index 000000000..cd820d276
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/attr-returns_twice-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-Wclobbered" } */
+
+int newsetjmp(void) __attribute__((returns_twice));
+void g(int);
+
+int
+main (void)
+{
+  register int reg asm ("esi") = 1; /* { dg-warning "might be clobbered" "" } */
+
+  if (!newsetjmp ())
+    {
+      reg = 2;
+      g (reg);
+    }
+  else
+    {
+      g (reg);
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/attributes-error.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/attributes-error.c
new file mode 100644
index 000000000..405eda501
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/attributes-error.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+
+void foo1(int i, int j) __attribute__((fastcall, cdecl)); /* { dg-error "not compatible" } */
+void foo2(int i, int j) __attribute__((fastcall, stdcall)); /* { dg-error "not compatible" } */
+void foo3(int i, int j) __attribute__((fastcall, regparm(2))); /* { dg-error "not compatible" } */
+void foo4(int i, int j) __attribute__((stdcall, cdecl)); /* { dg-error "not compatible" } */
+void foo5(int i, int j) __attribute__((stdcall, fastcall)); /* { dg-error "not compatible" } */
+void foo6(int i, int j) __attribute__((cdecl, fastcall)); /* { dg-error "not compatible" } */
+void foo7(int i, int j) __attribute__((cdecl, stdcall)); /* { dg-error "not compatible" } */
+void foo8(int i, int j) __attribute__((regparm(2), fastcall)); /* { dg-error "not compatible" } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-1.c
new file mode 100644
index 000000000..8f28921ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -0,0 +1,375 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -maes -mpclmul" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,g,a,b}mmintrin.h and
+   mm3dnow.h that reference the proper builtin functions.  Defining away
+   "extern" and "__inline" results in all of them being compiled as proper
+   functions.  */
+
+#define extern
+#define __inline
+
+/* Following intrinsics require immediate arguments. */
+
+/* ammintrin.h */
+#define __builtin_ia32_extrqi(X, I, L)  __builtin_ia32_extrqi(X, 1, 1)
+#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1)
+
+/* immintrin.h */
+#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1)
+#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1)
+#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1)
+#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1)
+#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1)
+#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1)
+#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1)
+#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1)
+#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1)
+#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1)
+#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1)
+#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1)
+#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1)
+#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1)
+#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1)
+#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1)
+#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1)
+#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1)
+#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1)
+#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1)
+#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
+#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
+#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
+#define __builtin_ia32_mpsadbw256(X, Y, M) __builtin_ia32_mpsadbw256(X, Y, 1)
+#define __builtin_ia32_palignr256(X, Y, M) __builtin_ia32_palignr256(X, Y, 8)
+#define __builtin_ia32_pblendw256(X, Y, M) __builtin_ia32_pblendw256(X, Y, 8)
+#define __builtin_ia32_pshufd256(X, M) __builtin_ia32_pshufd256(X, 8)
+#define __builtin_ia32_pshufhw256(X, M) __builtin_ia32_pshufhw256(X, 8)
+#define __builtin_ia32_pshuflw256(X, M) __builtin_ia32_pshuflw256(X, 8)
+#define __builtin_ia32_pslldqi256(X, M) __builtin_ia32_pslldqi256(X, 8)
+#define __builtin_ia32_psrldqi256(X, M) __builtin_ia32_psrldqi256(X, 8)
+#define __builtin_ia32_pblendd128(X, Y, M) __builtin_ia32_pblendd128(X, Y, 1)
+#define __builtin_ia32_pblendd256(X, Y, M) __builtin_ia32_pblendd256(X, Y, 1)
+#define __builtin_ia32_permdf256(X, M) __builtin_ia32_permdf256(X, 1)
+#define __builtin_ia32_permdi256(X, M) __builtin_ia32_permdi256(X, 1)
+#define __builtin_ia32_permti256(X, Y, M) __builtin_ia32_permti256(X, Y, 1)
+#define __builtin_ia32_extract128i256(X, M) __builtin_ia32_extract128i256(X, 1)
+#define __builtin_ia32_insert128i256(X, Y, M) __builtin_ia32_insert128i256(X, Y, 1)
+#define __builtin_ia32_gathersiv2df(A, B, C, D, M) __builtin_ia32_gathersiv2df(A, B, C, D, 1)
+#define __builtin_ia32_gathersiv4df(A, B, C, D, M) __builtin_ia32_gathersiv4df(A, B, C, D, 1)
+#define __builtin_ia32_gatherdiv2df(A, B, C, D, M) __builtin_ia32_gatherdiv2df(A, B, C, D, 1)
+#define __builtin_ia32_gatherdiv4df(A, B, C, D, M) __builtin_ia32_gatherdiv4df(A, B, C, D, 1)
+#define __builtin_ia32_gathersiv4sf(A, B, C, D, M) __builtin_ia32_gathersiv4sf(A, B, C, D, 1)
+#define __builtin_ia32_gathersiv8sf(A, B, C, D, M) __builtin_ia32_gathersiv8sf(A, B, C, D, 1)
+#define __builtin_ia32_gatherdiv4sf(A, B, C, D, M) __builtin_ia32_gatherdiv4sf(A, B, C, D, 1)
+#define __builtin_ia32_gatherdiv4sf256(A, B, C, D, M) \
+  __builtin_ia32_gatherdiv4sf256(A, B, C, D, 1)
+#define __builtin_ia32_gathersiv2di(A, B, C, D, M) __builtin_ia32_gathersiv2di(A, B, C, D, 1)
+#define __builtin_ia32_gathersiv4di(A, B, C, D, M) __builtin_ia32_gathersiv4di(A, B, C, D, 1)
+#define __builtin_ia32_gatherdiv2di(A, B, C, D, M) __builtin_ia32_gatherdiv2di(A, B, C, D, 1)
+#define __builtin_ia32_gatherdiv4di(A, B, C, D, M) __builtin_ia32_gatherdiv4di(A, B, C, D, 1)
+#define __builtin_ia32_gathersiv4si(A, B, C, D, M) __builtin_ia32_gathersiv4si(A, B, C, D, 1)
+#define __builtin_ia32_gathersiv8si(A, B, C, D, M) __builtin_ia32_gathersiv8si(A, B, C, D, 1)
+#define __builtin_ia32_gatherdiv4si(A, B, C, D, M) __builtin_ia32_gatherdiv4si(A, B, C, D, 1)
+#define __builtin_ia32_gatherdiv4si256(A, B, C, D, M) \
+  __builtin_ia32_gatherdiv4si256(A, B, C, D, 1)
+
+/* wmmintrin.h */
+#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1)
+#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1)
+
+/* smmintrin.h */
+#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1)
+#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1)
+#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1)
+#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1)
+
+#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1)
+#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1)
+#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1)
+#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1)
+#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1)
+#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1)
+#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1)
+#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1)
+#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1)
+#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1)
+#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1)
+#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1)
+#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1)
+#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1)
+#define __builtin_ia32_pcmpistrm128(X, Y, M) \
+  __builtin_ia32_pcmpistrm128(X, Y, 1)
+#define __builtin_ia32_pcmpistri128(X, Y, M) \
+  __builtin_ia32_pcmpistri128(X, Y, 1)
+#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpistria128(X, Y, M) \
+  __builtin_ia32_pcmpistria128(X, Y, 1)
+#define __builtin_ia32_pcmpistric128(X, Y, M) \
+  __builtin_ia32_pcmpistric128(X, Y, 1)
+#define __builtin_ia32_pcmpistrio128(X, Y, M) \
+  __builtin_ia32_pcmpistrio128(X, Y, 1)
+#define __builtin_ia32_pcmpistris128(X, Y, M) \
+  __builtin_ia32_pcmpistris128(X, Y, 1)
+#define __builtin_ia32_pcmpistriz128(X, Y, M) \
+  __builtin_ia32_pcmpistriz128(X, Y, 1)
+#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1)
+
+/* tmmintrin.h */
+#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8)
+#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8)
+
+/* emmintrin.h */
+#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8)
+#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8)
+#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0)
+#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0)
+#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0)
+#define __builtin_ia32_vec_set_v8hi(A, D, N) \
+  __builtin_ia32_vec_set_v8hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0)
+#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
+
+/* xmmintrin.h */
+#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, 0, _MM_HINT_NTA)
+#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
+#define __builtin_ia32_vec_set_v4hi(A, D, N) \
+  __builtin_ia32_vec_set_v4hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
+#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
+
+/* f16cintrin.h */
+#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 0)
+#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 0)
+
+/* rtmintrin.h */
+#define __builtin_ia32_xabort(I) __builtin_ia32_xabort(0)
+
+/* avx512fintrin.h */
+#define __builtin_ia32_addpd512_mask(A, B, C, D, E) __builtin_ia32_addpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_addps512_mask(A, B, C, D, E) __builtin_ia32_addps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_addsd_round(A, B, C) __builtin_ia32_addsd_round(A, B, 8)
+#define __builtin_ia32_addss_round(A, B, C) __builtin_ia32_addss_round(A, B, 8)
+#define __builtin_ia32_alignd512_mask(A, B, F, D, E) __builtin_ia32_alignd512_mask(A, B, 1, D, E)
+#define __builtin_ia32_alignq512_mask(A, B, F, D, E) __builtin_ia32_alignq512_mask(A, B, 1, D, E)
+#define __builtin_ia32_cmpd512_mask(A, B, E, D) __builtin_ia32_cmpd512_mask(A, B, 1, D)
+#define __builtin_ia32_cmppd512_mask(A, B, F, D, E) __builtin_ia32_cmppd512_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpps512_mask(A, B, F, D, E) __builtin_ia32_cmpps512_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpq512_mask(A, B, E, D) __builtin_ia32_cmpq512_mask(A, B, 1, D)
+#define __builtin_ia32_cmpsd_mask(A, B, F, D, E) __builtin_ia32_cmpsd_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpss_mask(A, B, F, D, E) __builtin_ia32_cmpss_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cvtdq2ps512_mask(A, B, C, D) __builtin_ia32_cvtdq2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2dq512_mask(A, B, C, D) __builtin_ia32_cvtpd2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2ps512_mask(A, B, C, D) __builtin_ia32_cvtpd2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2udq512_mask(A, B, C, D) __builtin_ia32_cvtpd2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2dq512_mask(A, B, C, D) __builtin_ia32_cvtps2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2pd512_mask(A, B, C, D) __builtin_ia32_cvtps2pd512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2udq512_mask(A, B, C, D) __builtin_ia32_cvtps2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtsd2ss_round(A, B, C) __builtin_ia32_cvtsd2ss_round(A, B, 8)
+#define __builtin_ia32_cvtss2sd_round(A, B, C) __builtin_ia32_cvtss2sd_round(A, B, 4)
+#define __builtin_ia32_cvtsi2sd64(A, B, C) __builtin_ia32_cvtsi2sd64(A, B, 8)
+#define __builtin_ia32_cvtsi2ss32(A, B, C) __builtin_ia32_cvtsi2ss32(A, B, 8)
+#define __builtin_ia32_cvtsi2ss64(A, B, C) __builtin_ia32_cvtsi2ss64(A, B, 8)
+#define __builtin_ia32_cvttpd2dq512_mask(A, B, C, D) __builtin_ia32_cvttpd2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttpd2udq512_mask(A, B, C, D) __builtin_ia32_cvttpd2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttps2dq512_mask(A, B, C, D) __builtin_ia32_cvttps2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttps2udq512_mask(A, B, C, D) __builtin_ia32_cvttps2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtudq2ps512_mask(A, B, C, D) __builtin_ia32_cvtudq2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtusi2sd64(A, B, C) __builtin_ia32_cvtusi2sd64(A, B, 8)
+#define __builtin_ia32_cvtusi2ss32(A, B, C) __builtin_ia32_cvtusi2ss32(A, B, 8)
+#define __builtin_ia32_cvtusi2ss64(A, B, C) __builtin_ia32_cvtusi2ss64(A, B, 8)
+#define __builtin_ia32_divpd512_mask(A, B, C, D, E) __builtin_ia32_divpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_divps512_mask(A, B, C, D, E) __builtin_ia32_divps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_divsd_round(A, B, C) __builtin_ia32_divsd_round(A, B, 8)
+#define __builtin_ia32_divss_round(A, B, C) __builtin_ia32_divss_round(A, B, 8)
+#define __builtin_ia32_extractf32x4_mask(A, E, C, D) __builtin_ia32_extractf32x4_mask(A, 1, C, D)
+#define __builtin_ia32_extractf64x4_mask(A, E, C, D) __builtin_ia32_extractf64x4_mask(A, 1, C, D)
+#define __builtin_ia32_extracti32x4_mask(A, E, C, D) __builtin_ia32_extracti32x4_mask(A, 1, C, D)
+#define __builtin_ia32_extracti64x4_mask(A, E, C, D) __builtin_ia32_extracti64x4_mask(A, 1, C, D)
+#define __builtin_ia32_fixupimmpd512_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmpd512_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmpd512_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmpd512_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmps512_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmps512_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmps512_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmps512_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmsd_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmsd_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmsd_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmsd_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmss_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmss_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmss_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmss_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_gatherdiv8df(A, B, C, D, F) __builtin_ia32_gatherdiv8df(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv8di(A, B, C, D, F) __builtin_ia32_gatherdiv8di(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv16sf(A, B, C, D, F) __builtin_ia32_gatherdiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv16si(A, B, C, D, F) __builtin_ia32_gatherdiv16si(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv16sf(A, B, C, D, F) __builtin_ia32_gathersiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv16si(A, B, C, D, F) __builtin_ia32_gathersiv16si(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv8df(A, B, C, D, F) __builtin_ia32_gathersiv8df(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv8di(A, B, C, D, F) __builtin_ia32_gathersiv8di(A, B, C, D, 8)
+#define __builtin_ia32_getexppd512_mask(A, B, C, D) __builtin_ia32_getexppd512_mask(A, B, C, 8)
+#define __builtin_ia32_getexpps512_mask(A, B, C, D) __builtin_ia32_getexpps512_mask(A, B, C, 8)
+#define __builtin_ia32_getexpsd128_round(A, B, C) __builtin_ia32_getexpsd128_round(A, B, 4)
+#define __builtin_ia32_getexpss128_round(A, B, C) __builtin_ia32_getexpss128_round(A, B, 4)
+#define __builtin_ia32_getmantpd512_mask(A, F, C, D, E) __builtin_ia32_getmantpd512_mask(A, 1, C, D, 8)
+#define __builtin_ia32_getmantps512_mask(A, F, C, D, E) __builtin_ia32_getmantps512_mask(A, 1, C, D, 8)
+#define __builtin_ia32_getmantsd_round(A, B, C, D) __builtin_ia32_getmantsd_round(A, B, 1, 4)
+#define __builtin_ia32_getmantss_round(A, B, C, D) __builtin_ia32_getmantss_round(A, B, 1, 4)
+#define __builtin_ia32_insertf32x4_mask(A, B, F, D, E) __builtin_ia32_insertf32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_insertf64x4_mask(A, B, F, D, E) __builtin_ia32_insertf64x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_inserti32x4_mask(A, B, F, D, E) __builtin_ia32_inserti32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_inserti64x4_mask(A, B, F, D, E) __builtin_ia32_inserti64x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_maxpd512_mask(A, B, C, D, E) __builtin_ia32_maxpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_maxps512_mask(A, B, C, D, E) __builtin_ia32_maxps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_maxsd_round(A, B, C) __builtin_ia32_maxsd_round(A, B, 4)
+#define __builtin_ia32_maxss_round(A, B, C) __builtin_ia32_maxss_round(A, B, 4)
+#define __builtin_ia32_minpd512_mask(A, B, C, D, E) __builtin_ia32_minpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_minps512_mask(A, B, C, D, E) __builtin_ia32_minps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_minsd_round(A, B, C) __builtin_ia32_minsd_round(A, B, 4)
+#define __builtin_ia32_minss_round(A, B, C) __builtin_ia32_minss_round(A, B, 4)
+#define __builtin_ia32_mulpd512_mask(A, B, C, D, E) __builtin_ia32_mulpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_mulps512_mask(A, B, C, D, E) __builtin_ia32_mulps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_mulsd_round(A, B, C) __builtin_ia32_mulsd_round(A, B, 8)
+#define __builtin_ia32_mulss_round(A, B, C) __builtin_ia32_mulss_round(A, B, 8)
+#define __builtin_ia32_permdf512_mask(A, E, C, D) __builtin_ia32_permdf512_mask(A, 1, C, D)
+#define __builtin_ia32_permdi512_mask(A, E, C, D) __builtin_ia32_permdi512_mask(A, 1, C, D)
+#define __builtin_ia32_prold512_mask(A, E, C, D) __builtin_ia32_prold512_mask(A, 1, C, D)
+#define __builtin_ia32_prolq512_mask(A, E, C, D) __builtin_ia32_prolq512_mask(A, 1, C, D)
+#define __builtin_ia32_prord512_mask(A, E, C, D) __builtin_ia32_prord512_mask(A, 1, C, D)
+#define __builtin_ia32_prorq512_mask(A, E, C, D) __builtin_ia32_prorq512_mask(A, 1, C, D)
+#define __builtin_ia32_pshufd512_mask(A, E, C, D) __builtin_ia32_pshufd512_mask(A, 1, C, D)
+#define __builtin_ia32_pslldi512_mask(A, E, C, D) __builtin_ia32_pslldi512_mask(A, 1, C, D)
+#define __builtin_ia32_psllqi512_mask(A, E, C, D) __builtin_ia32_psllqi512_mask(A, 1, C, D)
+#define __builtin_ia32_psradi512_mask(A, E, C, D) __builtin_ia32_psradi512_mask(A, 1, C, D)
+#define __builtin_ia32_psraqi512_mask(A, E, C, D) __builtin_ia32_psraqi512_mask(A, 1, C, D)
+#define __builtin_ia32_psrldi512_mask(A, E, C, D) __builtin_ia32_psrldi512_mask(A, 1, C, D)
+#define __builtin_ia32_psrlqi512_mask(A, E, C, D) __builtin_ia32_psrlqi512_mask(A, 1, C, D)
+#define __builtin_ia32_pternlogd512_mask(A, B, C, F, E) __builtin_ia32_pternlogd512_mask(A, B, C, 1, E)
+#define __builtin_ia32_pternlogd512_maskz(A, B, C, F, E) __builtin_ia32_pternlogd512_maskz(A, B, C, 1, E)
+#define __builtin_ia32_pternlogq512_mask(A, B, C, F, E) __builtin_ia32_pternlogq512_mask(A, B, C, 1, E)
+#define __builtin_ia32_pternlogq512_maskz(A, B, C, F, E) __builtin_ia32_pternlogq512_maskz(A, B, C, 1, E)
+#define __builtin_ia32_rndscalepd_mask(A, F, C, D, E) __builtin_ia32_rndscalepd_mask(A, 1, C, D, 8)
+#define __builtin_ia32_rndscaleps_mask(A, F, C, D, E) __builtin_ia32_rndscaleps_mask(A, 1, C, D, 8)
+#define __builtin_ia32_rndscalesd_round(A, B, C, D) __builtin_ia32_rndscalesd_round(A, B, 1, 4)
+#define __builtin_ia32_rndscaless_round(A, B, C, D) __builtin_ia32_rndscaless_round(A, B, 1, 4)
+#define __builtin_ia32_scalefpd512_mask(A, B, C, D, E) __builtin_ia32_scalefpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_scalefps512_mask(A, B, C, D, E) __builtin_ia32_scalefps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_scalefsd_round(A, B, C) __builtin_ia32_scalefsd_round(A, B, 8)
+#define __builtin_ia32_scalefss_round(A, B, C) __builtin_ia32_scalefss_round(A, B, 8)
+#define __builtin_ia32_scatterdiv8df(A, B, C, D, F) __builtin_ia32_scatterdiv8df(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv8di(A, B, C, D, F) __builtin_ia32_scatterdiv8di(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv16sf(A, B, C, D, F) __builtin_ia32_scatterdiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv16si(A, B, C, D, F) __builtin_ia32_scatterdiv16si(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv16sf(A, B, C, D, F) __builtin_ia32_scattersiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv16si(A, B, C, D, F) __builtin_ia32_scattersiv16si(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv8df(A, B, C, D, F) __builtin_ia32_scattersiv8df(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv8di(A, B, C, D, F) __builtin_ia32_scattersiv8di(A, B, C, D, 8)
+#define __builtin_ia32_shuf_f32x4_mask(A, B, F, D, E) __builtin_ia32_shuf_f32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_f64x2_mask(A, B, F, D, E) __builtin_ia32_shuf_f64x2_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_i32x4_mask(A, B, F, D, E) __builtin_ia32_shuf_i32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_i64x2_mask(A, B, F, D, E) __builtin_ia32_shuf_i64x2_mask(A, B, 1, D, E)
+#define __builtin_ia32_shufpd512_mask(A, B, F, D, E) __builtin_ia32_shufpd512_mask(A, B, 1, D, E)
+#define __builtin_ia32_shufps512_mask(A, B, F, D, E) __builtin_ia32_shufps512_mask(A, B, 1, D, E)
+#define __builtin_ia32_sqrtpd512_mask(A, B, C, D) __builtin_ia32_sqrtpd512_mask(A, B, C, 8)
+#define __builtin_ia32_sqrtps512_mask(A, B, C, D) __builtin_ia32_sqrtps512_mask(A, B, C, 8)
+#define __builtin_ia32_sqrtss_round(A, B, C) __builtin_ia32_sqrtss_round(A, B, 8)
+#define __builtin_ia32_sqrtsd_round(A, B, C) __builtin_ia32_sqrtsd_round(A, B, 8)
+#define __builtin_ia32_subpd512_mask(A, B, C, D, E) __builtin_ia32_subpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_subps512_mask(A, B, C, D, E) __builtin_ia32_subps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_subsd_round(A, B, C) __builtin_ia32_subsd_round(A, B, 8)
+#define __builtin_ia32_subss_round(A, B, C) __builtin_ia32_subss_round(A, B, 8)
+#define __builtin_ia32_ucmpd512_mask(A, B, E, D) __builtin_ia32_ucmpd512_mask(A, B, 1, D)
+#define __builtin_ia32_ucmpq512_mask(A, B, E, D) __builtin_ia32_ucmpq512_mask(A, B, 1, D)
+#define __builtin_ia32_vcomisd(A, B, C, D) __builtin_ia32_vcomisd(A, B, 1, 8)
+#define __builtin_ia32_vcomiss(A, B, C, D) __builtin_ia32_vcomiss(A, B, 1, 8)
+#define __builtin_ia32_vcvtph2ps512_mask(A, B, C, D) __builtin_ia32_vcvtph2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_vcvtps2ph512_mask(A, E, C, D) __builtin_ia32_vcvtps2ph512_mask(A, 1, C, D)
+#define __builtin_ia32_vcvtsd2si32(A, B) __builtin_ia32_vcvtsd2si32(A, 8)
+#define __builtin_ia32_vcvtsd2si64(A, B) __builtin_ia32_vcvtsd2si64(A, 8)
+#define __builtin_ia32_vcvtsd2usi32(A, B) __builtin_ia32_vcvtsd2usi32(A, 8)
+#define __builtin_ia32_vcvtsd2usi64(A, B) __builtin_ia32_vcvtsd2usi64(A, 8)
+#define __builtin_ia32_vcvtss2si32(A, B) __builtin_ia32_vcvtss2si32(A, 8)
+#define __builtin_ia32_vcvtss2si64(A, B) __builtin_ia32_vcvtss2si64(A, 8)
+#define __builtin_ia32_vcvtss2usi32(A, B) __builtin_ia32_vcvtss2usi32(A, 8)
+#define __builtin_ia32_vcvtss2usi64(A, B) __builtin_ia32_vcvtss2usi64(A, 8)
+#define __builtin_ia32_vcvttsd2si32(A, B) __builtin_ia32_vcvttsd2si32(A, 8)
+#define __builtin_ia32_vcvttsd2si64(A, B) __builtin_ia32_vcvttsd2si64(A, 8)
+#define __builtin_ia32_vcvttsd2usi32(A, B) __builtin_ia32_vcvttsd2usi32(A, 8)
+#define __builtin_ia32_vcvttsd2usi64(A, B) __builtin_ia32_vcvttsd2usi64(A, 8)
+#define __builtin_ia32_vcvttss2si32(A, B) __builtin_ia32_vcvttss2si32(A, 8)
+#define __builtin_ia32_vcvttss2si64(A, B) __builtin_ia32_vcvttss2si64(A, 8)
+#define __builtin_ia32_vcvttss2usi32(A, B) __builtin_ia32_vcvttss2usi32(A, 8)
+#define __builtin_ia32_vcvttss2usi64(A, B) __builtin_ia32_vcvttss2usi64(A, 8)
+#define __builtin_ia32_vfmaddpd512_mask(A, B, C, D, E) __builtin_ia32_vfmaddpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddpd512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddpd512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_mask(A, B, C, D, E) __builtin_ia32_vfmaddps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddps512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsd3_round(A, B, C, D) __builtin_ia32_vfmaddsd3_round(A, B, C, 8)
+#define __builtin_ia32_vfmaddss3_round(A, B, C, D) __builtin_ia32_vfmaddss3_round(A, B, C, 8)
+#define __builtin_ia32_vfmaddsubpd512_mask(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubpd512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_mask(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubaddpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubaddpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubaddps512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubaddps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubsd3_mask3(A, B, C, D, E) __builtin_ia32_vfmsubsd3_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubss3_mask3(A, B, C, D, E) __builtin_ia32_vfmsubss3_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd512_mask(A, B, C, D, E) __builtin_ia32_vfnmaddpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps512_mask(A, B, C, D, E) __builtin_ia32_vfnmaddps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubpd512_mask(A, B, C, D, E) __builtin_ia32_vfnmsubpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubps512_mask(A, B, C, D, E) __builtin_ia32_vfnmsubps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vpermilpd512_mask(A, E, C, D) __builtin_ia32_vpermilpd512_mask(A, 1, C, D)
+#define __builtin_ia32_vpermilps512_mask(A, E, C, D) __builtin_ia32_vpermilps512_mask(A, 1, C, D)
+
+/* avx512erintrin.h */
+#define __builtin_ia32_exp2ps_mask(A, B, C, D) __builtin_ia32_exp2ps_mask(A, B, C, 8)
+#define __builtin_ia32_exp2pd_mask(A, B, C, D) __builtin_ia32_exp2pd_mask(A, B, C, 8)
+#define __builtin_ia32_rcp28ps_mask(A, B, C, D) __builtin_ia32_rcp28ps_mask(A, B, C, 8)
+#define __builtin_ia32_rcp28pd_mask(A, B, C, D) __builtin_ia32_rcp28pd_mask(A, B, C, 8)
+#define __builtin_ia32_rsqrt28ps_mask(A, B, C, D) __builtin_ia32_rsqrt28ps_mask(A, B, C, 8)
+#define __builtin_ia32_rsqrt28pd_mask(A, B, C, D) __builtin_ia32_rsqrt28pd_mask(A, B, C, 8)
+#define __builtin_ia32_rcp28ss_round(A, B, C) __builtin_ia32_rcp28ss_round(A, B, 8)
+#define __builtin_ia32_rcp28sd_round(A, B, C) __builtin_ia32_rcp28sd_round(A, B, 8)
+#define __builtin_ia32_rsqrt28ss_round(A, B, C) __builtin_ia32_rsqrt28ss_round(A, B, 8)
+#define __builtin_ia32_rsqrt28sd_round(A, B, C) __builtin_ia32_rsqrt28sd_round(A, B, 8)
+
+/* avx512pfintrin.h */
+#define __builtin_ia32_gatherpfdps(A, B, C, D, E) __builtin_ia32_gatherpfdps(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_gatherpfqps(A, B, C, D, E) __builtin_ia32_gatherpfqps(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_scatterpfdps(A, B, C, D, E) __builtin_ia32_scatterpfdps(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_scatterpfqps(A, B, C, D, E) __builtin_ia32_scatterpfqps(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_gatherpfdpd(A, B, C, D, E) __builtin_ia32_gatherpfdpd(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_gatherpfqpd(A, B, C, D, E) __builtin_ia32_gatherpfqpd(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_scatterpfdpd(A, B, C, D, E) __builtin_ia32_scatterpfdpd(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_scatterpfqpd(A, B, C, D, E) __builtin_ia32_scatterpfqpd(A, B, C, 1, _MM_HINT_T0)
+
+/* shaintrin.h */
+#define __builtin_ia32_sha1rnds4(A, B, C) __builtin_ia32_sha1rnds4(A, B, 1)
+
+#include <wmmintrin.h>
+#include <immintrin.h>
+#include <mm3dnow.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-2.c
new file mode 100644
index 000000000..17bc64e4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-2.c
@@ -0,0 +1,162 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mavx2 -msse4a -maes -mpclmul" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,g,a,b}mmintrin.h and
+   mm3dnow.h that reference the proper builtin functions.  Defining away
+   "extern" and "__inline" results in all of them being compiled as proper
+   functions.  */
+
+#define extern
+#define __inline
+
+#include <wmmintrin.h>
+#include <immintrin.h>
+#include <ammintrin.h>
+#include <mm3dnow.h>
+
+#define _CONCAT(x,y) x ## y
+
+#define test_1(func, type, op1_type, imm)				\
+  type _CONCAT(_,func) (op1_type A, int const I)			\
+  { return func (A, imm); }
+
+#define test_1x(func, type, op1_type, imm1, imm2)			\
+  type _CONCAT(_,func) (op1_type A, int const I, int const L)		\
+  { return func (A, imm1, imm2); }
+
+#define test_2(func, type, op1_type, op2_type, imm)			\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I)		\
+  { return func (A, B, imm); }
+
+#define test_2x(func, type, op1_type, op2_type, imm1, imm2)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
+  { return func (A, B, imm1, imm2); }
+
+#define test_3(func, type, op1_type, op2_type, op3_type, imm)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I)		\
+  { return func (A, B, C, imm); }
+
+#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, op4_type D, int const I)		\
+  { return func (A, B, C, D, imm); }
+
+
+/* Following intrinsics require immediate arguments.  They
+   are defined as macros for non-optimized compilations. */
+
+/* ammintrin.h */
+test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
+test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
+
+/* immintrin.h */
+test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1)
+test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1)
+test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1)
+test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1)
+test_1 (_mm256_extractf128_ps, __m128, __m256, 1)
+test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1)
+test_1 (_mm256_extract_epi8, int, __m256i, 20)
+test_1 (_mm256_extract_epi16, int, __m256i, 13)
+test_1 (_mm256_extract_epi32, int, __m256i, 6)
+#ifdef __x86_64__
+test_1 (_mm256_extract_epi64, long long, __m256i, 2)
+#endif
+test_1 (_mm_permute_pd, __m128d, __m128d, 1)
+test_1 (_mm256_permute_pd, __m256d, __m256d, 1)
+test_1 (_mm_permute_ps, __m128, __m128, 1)
+test_1 (_mm256_permute_ps, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1)
+test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1)
+test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1)
+test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1)
+test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30)
+test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7)
+test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3)
+#ifdef __x86_64__
+test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1)
+#endif
+test_1 (_mm256_round_pd, __m256d, __m256d, 1)
+test_1 (_mm256_round_ps, __m256, __m256, 1)
+
+/* wmmintrin.h */
+test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
+test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
+
+/* smmintrin.h */
+test_1 (_mm_round_pd, __m128d, __m128d, 1)
+test_1 (_mm_round_ps, __m128, __m128, 1)
+test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_round_ss, __m128, __m128, __m128, 1)
+
+test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_dp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_insert_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_ps, int, __m128, 1)
+test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1)
+test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1)
+#ifdef __x86_64__
+test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1)
+#endif
+test_1 (_mm_extract_epi8, int, __m128i, 1)
+test_1 (_mm_extract_epi32, int, __m128i, 1)
+#ifdef __x86_64__
+test_1 (_mm_extract_epi64, long long, __m128i, 1)
+#endif
+test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistri, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1)
+test_2 (_mm_cmpistra, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistro, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
+
+/* tmmintrin.h */
+test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1)
+
+/* emmintrin.h */
+test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1)
+test_1 (_mm_srli_si128, __m128i, __m128i, 1)
+test_1 (_mm_slli_si128, __m128i, __m128i, 1)
+test_1 (_mm_extract_epi16, int, __m128i, 1)
+test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1)
+test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1)
+
+/* xmmintrin.h */
+test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_pi16, int, __m64, 1)
+test_1 (_m_pextrw, int, __m64, 1)
+test_2 (_mm_insert_pi16, __m64, __m64, int, 1)
+test_2 (_m_pinsrw, __m64, __m64, int, 1)
+test_1 (_mm_shuffle_pi16, __m64, __m64, 1)
+test_1 (_m_pshufw, __m64, __m64, 1)
+test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-3.c
new file mode 100644
index 000000000..6a180fa88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O2 -mavx -std=gnu99" } */
+
+_Decimal128
+foo128 (_Decimal128 z)
+{
+  return z + 1.0dl;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-additional-reg-names.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-additional-reg-names.c
new file mode 100644
index 000000000..d984bff44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-additional-reg-names.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx" } */
+
+void foo ()
+{
+  register int ymm_var asm ("ymm4");
+
+  __asm__ __volatile__("vxorpd %%ymm0, %%ymm0, %%ymm7\n" : : : "ymm7" );
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c
new file mode 100644
index 000000000..bf48b8071
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-2-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double ceil (double);
+
+#define NUM 4
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) ceil (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) ceil (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c
new file mode 100644
index 000000000..ac0911fe8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-sfix-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ceil-sfix-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c
new file mode 100644
index 000000000..0e76ab802
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceil-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ceil-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c
new file mode 100644
index 000000000..789b78e76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceilf-sfix-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ceilf-sfix-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c
new file mode 100644
index 000000000..c324a9b4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-ceilf-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ceilf-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-check.h
new file mode 100644
index 000000000..7ddca9d7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-check.h
@@ -0,0 +1,38 @@
+#include <stdlib.h>
+#include "cpuid.h"
+#include "m256-check.h"
+#include "avx-os-support.h"
+
+static void avx_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  avx_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AVX test only if host has AVX support.  */
+  if (((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE))
+      && avx_os_support ())
+    {
+      do_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c
new file mode 100644
index 000000000..7898606b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpsd-1.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cmpsd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpsd-2.c
new file mode 100644
index 000000000..3162912b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpsd-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+#include <emmintrin.h>
+
+__m128d
+foo (__m128d x, __m128d y)
+{
+  return _mm_cmpeq_sd (x, y);
+}
+
+
+/* { dg-final { scan-assembler "vcmpeqsd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c
new file mode 100644
index 000000000..e0ee934da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpss-1.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cmpss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpss-2.c
new file mode 100644
index 000000000..0fcc620c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cmpss-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+#include <xmmintrin.h>
+
+__m128
+foo (__m128 x, __m128 y)
+{
+  return _mm_cmpeq_ss (x, y);
+}
+
+
+/* { dg-final { scan-assembler "vcmpeqss" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cond-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cond-1.c
new file mode 100644
index 000000000..e233ec962
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cond-1.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mavx" } */
+/* { dg-require-effective-target avx_runtime } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#include "sse4_1-cond-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c
new file mode 100644
index 000000000..9b45a093a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-copysign-vec.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-copysign-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c
new file mode 100644
index 000000000..00aa6f57f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-copysignf-vec.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-copysignf-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-1.c
new file mode 100644
index 000000000..ce651649d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-1.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mavx -mno-avx2" } */
+/* { dg-require-effective-target avx_runtime } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#include "sse2-cvt-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c
new file mode 100644
index 000000000..0081dcf38
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-2-vec.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+#define NUM 4
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=sse")))
+TEST (void)
+{
+  double a[NUM];
+  float r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (float) a[i];
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (float) a[i])
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-2.c
new file mode 100644
index 000000000..de1afecca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx -mno-avx2 -mtune=generic -fdump-tree-vect-details" } */
+
+#include "avx-cvt-1.c"
+
+/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */
+/* { dg-final { scan-assembler "vcvttpd2dq(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */
+/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*ymm" } } */
+/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */
+/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*ymm" } } */
+/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */
+/* { dg-final { scan-assembler "vcvtpd2ps(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-3.c
new file mode 100644
index 000000000..a9b898a95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-3.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx -mno-avx2 -mtune=generic -mprefer-avx128 -fdump-tree-vect-details" } */
+
+#include "avx-cvt-1.c"
+
+/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */
+/* { dg-final { scan-assembler "vcvttpd2dq(x\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*XMMWORD PTR)" } } */
+/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*xmm" } } */
+/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%xmm|xmm\[^\n\r\]*xmm)" } } */
+/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*xmm" } } */
+/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*xmm\[^\n\r\]*xmm" } } */
+/* { dg-final { scan-assembler "vcvtpd2ps(x\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*XMMWORD PTR)" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c
new file mode 100644
index 000000000..4dcfa3989
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-cvt-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvt-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-extract-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-extract-1.c
new file mode 100644
index 000000000..2684125f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-extract-1.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx" } */
+/* { dg-require-effective-target avx_runtime } */
+
+#include "sse2-extract-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c
new file mode 100644
index 000000000..275199cf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-sfix-2-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double floor (double);
+
+#define NUM 4
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) floor (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) floor (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c
new file mode 100644
index 000000000..efa557cf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-sfix-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-floor-sfix-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-vec.c
new file mode 100644
index 000000000..1d7fe5043
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floor-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-floor-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c
new file mode 100644
index 000000000..0c1587a12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floorf-sfix-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-floorf-sfix-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c
new file mode 100644
index 000000000..73da85be9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-floorf-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-floorf-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-inline.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-inline.c
new file mode 100644
index 000000000..05df95e05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-inline.c
@@ -0,0 +1,20 @@
+/* Check if avx target functions can inline lower target functions.   */
+/* { dg-do compile } */
+/* { dg-options "-O0 -mno-avx -mno-sse3" } */
+
+__attribute__((always_inline,target("sse3")))
+inline int callee ()
+{
+  return 0;
+}
+
+__attribute__((target("avx")))
+inline int caller ()
+{
+  return callee ();
+}
+
+int main ()
+{
+  return caller ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c
new file mode 100644
index 000000000..2df65d203
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-lrint-vec.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-lrint-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c
new file mode 100644
index 000000000..e08b2f565
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-lrintf-vec.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-lrintf-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-mul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-mul-1.c
new file mode 100644
index 000000000..0d511c95c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-mul-1.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -mavx" } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#include "sse2-mul-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-os-support.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-os-support.h
new file mode 100644
index 000000000..fb1ce7562
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-os-support.h
@@ -0,0 +1,18 @@
+/* Check if the OS supports executing AVX instructions.  */
+
+#define XCR_XFEATURE_ENABLED_MASK	0x0
+
+#define XSTATE_FP	0x1
+#define XSTATE_SSE	0x2
+#define XSTATE_YMM	0x4
+
+static int
+avx_os_support (void)
+{
+  unsigned int eax, edx;
+  unsigned int ecx = XCR_XFEATURE_ENABLED_MASK;
+
+  __asm__ ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (ecx));
+
+  return (eax & (XSTATE_SSE | XSTATE_YMM)) == (XSTATE_SSE | XSTATE_YMM);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr51581-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr51581-1.c
new file mode 100644
index 000000000..a1d84bf68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr51581-1.c
@@ -0,0 +1,23 @@
+/* PR tree-optimization/51581 */
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -fno-vect-cost-model" } */
+/* { dg-require-effective-target avx } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#define main main1
+#include "../../gcc.c-torture/execute/pr51581-1.c"
+#undef main
+
+#include CHECK_H
+
+static void
+TEST (void)
+{
+  main1 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr51581-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr51581-2.c
new file mode 100644
index 000000000..6ff54d997
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-pr51581-2.c
@@ -0,0 +1,23 @@
+/* PR tree-optimization/51581 */
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -fno-vect-cost-model" } */
+/* { dg-require-effective-target avx } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#define main main1
+#include "../../gcc.c-torture/execute/pr51581-2.c"
+#undef main
+
+#include CHECK_H
+
+static void
+TEST (void)
+{
+  main1 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-recip-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-recip-vec.c
new file mode 100644
index 000000000..efeff7ece
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-recip-vec.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mfpmath=sse -mrecip" } */
+/* { dg-require-effective-target avx } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-recip-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-reduc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-reduc-1.c
new file mode 100644
index 000000000..1df1ee032
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-reduc-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mavx" } */
+/* { dg-require-effective-target avx_runtime } */
+
+extern void abort (void);
+double ad[1024];
+float af[1024];
+short as[1024];
+int ai[1024];
+long long all[1024];
+unsigned short aus[1024];
+unsigned int au[1024];
+unsigned long long aull[1024];
+
+#define F(var) \
+__attribute__((noinline, noclone)) __typeof (var[0]) \
+f##var (void) \
+{ \
+  int i; \
+  __typeof (var[0]) r = 0; \
+  for (i = 0; i < 1024; i++) \
+    r = r > var[i] ? r : var[i]; \
+  return r; \
+}
+
+#define TESTS \
+F (ad) F (af) F (as) F (ai) F (all) F (aus) F (au) F (aull)
+
+TESTS
+
+int
+main ()
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    {
+#undef F
+#define F(var) var[i] = i;
+      TESTS
+    }
+  for (i = 1023; i < 32 * 1024; i += 1024 + 271)
+    {
+#undef F
+#define F(var) var[i & 1023] = i; if (f##var () != i) abort ();
+      TESTS
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c
new file mode 100644
index 000000000..9f273af5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-sfix-2-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double rint (double);
+
+#define NUM 4
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) rint (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) rint (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c
new file mode 100644
index 000000000..824f2eb7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-sfix-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-rint-sfix-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-vec.c
new file mode 100644
index 000000000..c1d420c6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rint-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-rint-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c
new file mode 100644
index 000000000..e5ddf790d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rintf-sfix-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-rintf-sfix-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c
new file mode 100644
index 000000000..caf365da6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-rintf-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-rintf-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c
new file mode 100644
index 000000000..ddb46d925
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-sfix-2-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double round (double);
+
+#define NUM 4
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) round (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) round (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c
new file mode 100644
index 000000000..5adfffa5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-sfix-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-round-sfix-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-vec.c
new file mode 100644
index 000000000..c43c05704
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-round-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-round-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c
new file mode 100644
index 000000000..1fd459123
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-roundf-sfix-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-roundf-sfix-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c
new file mode 100644
index 000000000..978013eb1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-roundf-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-roundf-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c
new file mode 100644
index 000000000..e85784890
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short *v)
+{
+  return _mm256_set_epi16 (v[15], v[14], v[13], v[12],
+			   v[11], v[10], v[9], v[8],
+			   v[7], v[6], v[5], v[4],
+			   v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  short v[16] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68
+    };
+  union256i_w u;
+
+  u.x = foo (v);
+  if (check_union256i_w (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c
new file mode 100644
index 000000000..ac1fc458b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short x1, short x2, short x3, short x4,
+     short x5, short x6, short x7, short x8,
+     short x9, short x10, short x11, short x12,
+     short x13, short x14, short x15, short x16)
+{
+  return _mm256_set_epi16 (x1, x2, x3, x4, x5, x6, x7, x8,
+			   x9, x10, x11, x12, x13, x14, x15, x16);
+}
+
+static void
+avx_test (void)
+{
+  short v[16] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68
+    };
+  union256i_w u;
+
+  u.x = foo (v[15], v[14], v[13], v[12],
+	     v[11], v[10], v[9], v[8],
+	     v[7], v[6], v[5], v[4],
+	     v[3], v[2], v[1], v[0]);
+  if (check_union256i_w (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c
new file mode 100644
index 000000000..c215d5675
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-3.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short x)
+{
+  return _mm256_set_epi16 (x, x, x, x, x, x, x, x,
+			   x, x, x, x, x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  short e = 345;
+  short v[16];
+  union256i_w u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256i_w (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c
new file mode 100644
index 000000000..a707fc8dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-4.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm256_set_epi16 (x, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 14:
+      return _mm256_set_epi16 (0, x, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 13:
+      return _mm256_set_epi16 (0, 0, x, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 12:
+      return _mm256_set_epi16 (0, 0, 0, x, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 11:
+      return _mm256_set_epi16 (0, 0, 0, 0, x, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 10:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, x, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 9:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, x, 0,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 8:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, x,
+			       0, 0, 0, 0, 0, 0, 0, 0);
+    case 7:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm256_set_epi16 (0, 0, 0, 0, 0, 0, 0, 0,
+			       0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  short e = 0xbeef;
+  short v[16];
+  union256i_w u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_w (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c
new file mode 100644
index 000000000..ad77eda29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v16hi-5.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (short x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm256_set_epi16 (x, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 14:
+      return _mm256_set_epi16 (1, x, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 13:
+      return _mm256_set_epi16 (1, 1, x, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 12:
+      return _mm256_set_epi16 (1, 1, 1, x, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm256_set_epi16 (1, 1, 1, 1, x, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, x, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, x, 1,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, x,
+			       1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm256_set_epi16 (1, 1, 1, 1, 1, 1, 1, 1,
+			       1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  short e = 0xbeef;
+  short v[16];
+  union256i_w u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_w (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c
new file mode 100644
index 000000000..9d9381578
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char *v)
+{
+  return _mm256_set_epi8 (v[31], v[30], v[29], v[28],
+			  v[27], v[26], v[25], v[24],
+			  v[23], v[22], v[21], v[20],
+			  v[19], v[18], v[17], v[16],
+			  v[15], v[14], v[13], v[12],
+			  v[11], v[10], v[9], v[8],
+			  v[7], v[6], v[5], v[4],
+			  v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  char v[32] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68,
+      -13, 30, 78, 149, -70, -37, 98, 38,
+      41, 73, 89, 14, 80, 117, 108, 8
+    };
+  union256i_b u;
+
+  u.x = foo (v);
+  if (check_union256i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c
new file mode 100644
index 000000000..508ed51a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char x1, char x2, char x3, char x4,
+     char x5, char x6, char x7, char x8,
+     char x9, char x10, char x11, char x12,
+     char x13, char x14, char x15, char x16,
+     char x17, char x18, char x19, char x20,
+     char x21, char x22, char x23, char x24,
+     char x25, char x26, char x27, char x28,
+     char x29, char x30, char x31, char x32)
+{
+  return _mm256_set_epi8 (x1, x2, x3, x4, x5, x6, x7, x8,
+			  x9, x10, x11, x12, x13, x14, x15, x16,
+			  x17, x18, x19, x20, x21, x22, x23, x24,
+			  x25, x26, x27, x28, x29, x30, x31, x32);
+}
+
+static void
+avx_test (void)
+{
+  char v[32] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68,
+      -13, 30, 78, 149, -70, -37, 98, 38,
+      41, 73, 89, 14, 80, 117, 108, 8
+    };
+  union256i_b u;
+
+  u.x = foo (v[31], v[30], v[29], v[28],
+	     v[27], v[26], v[25], v[24],
+	     v[23], v[22], v[21], v[20],
+	     v[19], v[18], v[17], v[16],
+	     v[15], v[14], v[13], v[12],
+	     v[11], v[10], v[9], v[8],
+	     v[7], v[6], v[5], v[4],
+	     v[3], v[2], v[1], v[0]);
+  if (check_union256i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c
new file mode 100644
index 000000000..da92c8e2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-3.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char x)
+{
+  return _mm256_set_epi8 (x, x, x, x, x, x, x, x,
+			  x, x, x, x, x, x, x, x,
+			  x, x, x, x, x, x, x, x,
+			  x, x, x, x, x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  char e = -45;
+  char v[32];
+  union256i_b u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c
new file mode 100644
index 000000000..7220695ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-4.c
@@ -0,0 +1,131 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char x, int i)
+{
+  switch (i)
+    {
+    case 31:
+      return _mm256_set_epi8 (x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 30:
+      return _mm256_set_epi8 (0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 29:
+      return _mm256_set_epi8 (0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 28:
+      return _mm256_set_epi8 (0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 27:
+      return _mm256_set_epi8 (0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 26:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 25:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 24:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 23:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 22:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 21:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 20:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 19:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 18:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 17:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 16:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 15:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 14:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 13:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 12:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 11:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 10:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 9:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 8:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 7:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm256_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+			      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  char e = 0xa1;
+  char v[32];
+  union256i_b u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_b (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c
new file mode 100644
index 000000000..0fcadda91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v32qi-5.c
@@ -0,0 +1,131 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (char x, int i)
+{
+  switch (i)
+    {
+    case 31:
+      return _mm256_set_epi8 (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 30:
+      return _mm256_set_epi8 (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 29:
+      return _mm256_set_epi8 (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 28:
+      return _mm256_set_epi8 (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 27:
+      return _mm256_set_epi8 (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 26:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 25:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 24:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 23:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 22:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 21:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 20:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 19:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 18:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 17:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 16:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 15:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 14:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 13:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 12:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm256_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			      1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  char e = 0xa1;
+  char v[32];
+  union256i_b u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_b (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c
new file mode 100644
index 000000000..89e6ec2f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double *v)
+{
+  return _mm256_set_pd (v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  double v[4] = { -3, 2, 1, 9 };
+  union256d u;
+
+  u.x = foo (v);
+  if (check_union256d (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c
new file mode 100644
index 000000000..51df025ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-2.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double x1, double x2, double x3, double x4)
+{
+  return _mm256_set_pd (x1, x2, x3, x4);
+}
+
+static void
+avx_test (void)
+{
+  double v[4] = { -3, 2, 1, 9 };
+  union256d u;
+
+  u.x = foo (v[3], v[2], v[1], v[0]);
+  if (check_union256d (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c
new file mode 100644
index 000000000..01b2ff51d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double x)
+{
+  return _mm256_set_pd (x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  double e = 34.5;
+  double v[4];
+  union256d u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256d (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c
new file mode 100644
index 000000000..e2f6300a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-4.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double x, int i)
+{
+  switch (i)
+    {
+    case 3:
+      return _mm256_set_pd (x, 0, 0, 0);
+    case 2:
+      return _mm256_set_pd (0, x, 0, 0);
+    case 1:
+      return _mm256_set_pd (0, 0, x, 0);
+    case 0:
+      return _mm256_set_pd (0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  double e = -3.234;
+  double v[4];
+  union256d u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256d (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c
new file mode 100644
index 000000000..6f418a668
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4df-5.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline))
+foo (double x, int i)
+{
+  switch (i)
+    {
+    case 3:
+      return _mm256_set_pd (x, 1, 1, 1);
+    case 2:
+      return _mm256_set_pd (1, x, 1, 1);
+    case 1:
+      return _mm256_set_pd (1, 1, x, 1);
+    case 0:
+      return _mm256_set_pd (1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  double e = -3.234;
+  double v[4];
+  union256d u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256d (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c
new file mode 100644
index 000000000..84b6278a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long *v)
+{
+  return _mm256_set_epi64x (v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  long long v[4]
+    = { 0x12e9e94645ad8LL, 0x851c0b39446LL,
+	0x786784645245LL, 0x9487731234LL };
+  union256i_q u;
+
+  u.x = foo (v);
+  if (check_union256i_q (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c
new file mode 100644
index 000000000..f3dc138a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long x1, long long x2, long long x3, long long x4)
+{
+  return _mm256_set_epi64x (x1, x2, x3, x4);
+}
+
+static void
+avx_test (void)
+{
+  long long v[4]
+    = { 0x12e9e94645ad8LL, 0x851c0b39446LL,
+	0x786784645245LL, 0x9487731234LL };
+  union256i_q u;
+
+  u.x = foo (v[3], v[2], v[1], v[0]);
+  if (check_union256i_q (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c
new file mode 100644
index 000000000..95710d822
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long x)
+{
+  return _mm256_set_epi64x (x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  long long e = 0xfed178ab134badf1LL;
+  long long v[4];
+  union256i_q u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256i_q (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c
new file mode 100644
index 000000000..83f8c15fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-4.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long x, int i)
+{
+  switch (i)
+    {
+    case 3:
+      return _mm256_set_epi64x (x, 0, 0, 0);
+    case 2:
+      return _mm256_set_epi64x (0, x, 0, 0);
+    case 1:
+      return _mm256_set_epi64x (0, 0, x, 0);
+    case 0:
+      return _mm256_set_epi64x (0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  long long e = 0xabadbeef01234567LL;
+  long long v[4];
+  union256i_q u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_q (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c
new file mode 100644
index 000000000..7bc260c7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v4di-5.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (long long x, int i)
+{
+  switch (i)
+    {
+    case 3:
+      return _mm256_set_epi64x (x, 1, 1, 1);
+    case 2:
+      return _mm256_set_epi64x (1, x, 1, 1);
+    case 1:
+      return _mm256_set_epi64x (1, 1, x, 1);
+    case 0:
+      return _mm256_set_epi64x (1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  long long e = 0xabadbeef01234567LL;
+  long long v[4];
+  union256i_q u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_q (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c
new file mode 100644
index 000000000..6f1ba7101
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256 
+__attribute__((noinline))
+foo (float *v)
+{
+  return _mm256_set_ps (v[7], v[6], v[5], v[4],
+			v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  float v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 };
+  union256 u;
+
+  u.x = foo (v);
+  if (check_union256 (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c
new file mode 100644
index 000000000..4d809d7ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+__m256
+__attribute__((noinline))
+foo (float x1, float x2, float x3, float x4,
+     float x5, float x6, float x7, float x8)
+{
+  return _mm256_set_ps (x1, x2, x3, x4, x5, x6, x7, x8);
+}
+
+void
+avx_test (void)
+{
+  float v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 };
+  union256 u;
+
+  u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union256 (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c
new file mode 100644
index 000000000..96f5e3318
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline))
+foo (float x)
+{
+  return _mm256_set_ps (x, x, x, x, x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  float e = 34.5;
+  float v[8];
+  union256 u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256 (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c
new file mode 100644
index 000000000..73be30369
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline))
+foo (float x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm256_set_ps (x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm256_set_ps (0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm256_set_ps (0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm256_set_ps (0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm256_set_ps (0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm256_set_ps (0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm256_set_ps (0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm256_set_ps (0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  float e = -3.234;
+  float v[8];
+  union256 u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256 (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c
new file mode 100644
index 000000000..80dc156d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8sf-5.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline))
+foo (float x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm256_set_ps (x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm256_set_ps (1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm256_set_ps (1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm256_set_ps (1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm256_set_ps (1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm256_set_ps (1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm256_set_ps (1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm256_set_ps (1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  float e = -3.234;
+  float v[8];
+  union256 u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256 (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c
new file mode 100644
index 000000000..7aa029ea5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (int *v)
+{
+  return _mm256_set_epi32 (v[7], v[6], v[5], v[4],
+			   v[3], v[2], v[1], v[0]);
+}
+
+static void
+avx_test (void)
+{
+  int v[8]
+    = { 19832468, 6576856, 8723467, 234566,
+	786784, 645245, 948773, 1234 };
+  union256i_d u;
+
+  u.x = foo (v);
+  if (check_union256i_d (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c
new file mode 100644
index 000000000..e822c785b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+__m256i
+__attribute__((noinline))
+foo (int x1, int x2, int x3, int x4,
+     int x5, int x6, int x7, int x8)
+{
+  return _mm256_set_epi32 (x1, x2, x3, x4, x5, x6, x7, x8);
+}
+
+static void
+avx_test (void)
+{
+  int v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 };
+  union256i_d u;
+
+  u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union256i_d (u, v))
+     abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c
new file mode 100644
index 000000000..594436b37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (int x)
+{
+  return _mm256_set_epi32 (x, x, x, x, x, x, x, x);
+}
+
+static void
+avx_test (void)
+{
+  int e = 0xabadbeef;
+  int v[8];
+  union256i_d u;
+  int i;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    v[i] = e;
+  u.x = foo (e);
+  if (check_union256i_d (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c
new file mode 100644
index 000000000..2cad62769
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (int x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm256_set_epi32 (x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm256_set_epi32 (0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm256_set_epi32 (0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm256_set_epi32 (0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm256_set_epi32 (0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm256_set_epi32 (0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm256_set_epi32 (0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm256_set_epi32 (0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  int e = 0xabadbeef;
+  int v[8];
+  union256i_d u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 0;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_d (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c
new file mode 100644
index 000000000..456e87772
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set-v8si-5.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__((noinline))
+foo (int x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm256_set_epi32 (x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm256_set_epi32 (1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm256_set_epi32 (1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm256_set_epi32 (1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm256_set_epi32 (1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm256_set_epi32 (1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm256_set_epi32 (1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm256_set_epi32 (1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx_test (void)
+{
+  int e = 0xabadbeef;
+  int v[8];
+  union256i_d u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union256i_d (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c
new file mode 100644
index 000000000..2d774aef3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-epi32-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256i_d u;
+  int e [8];
+  int source[1] = {1234};
+
+  u.x = _mm256_set1_epi32 (source[0]);
+
+  for (i = 0; i < 8; i++)
+    e[i] = source[0];
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c
new file mode 100644
index 000000000..21aea2940
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-pd-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u;
+  double e [4];
+  double source[1] = {26156.643};
+
+  u.x = _mm256_set1_pd (source[0]);
+
+  for (i = 0; i < 4; i++)
+    e[i] = source[0];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c
new file mode 100644
index 000000000..c5f2d1023
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-set1-ps-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u;
+  float e [8];
+  float	 source[1] = {1234.234f};
+
+  u.x = _mm256_set1_ps (source[0]);
+
+  for (i = 0; i < 8; i++)
+    e[i] = source[0];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c
new file mode 100644
index 000000000..43656cf81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-pd-256-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u;
+  double e [4];
+
+  u.x = _mm256_setzero_pd ();
+
+  for (i = 0; i < 4; i++)
+    e[i] = 0.0;
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c
new file mode 100644
index 000000000..ffbf431fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-ps-256-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u;
+  float e [8];
+
+  u.x = _mm256_setzero_ps ();
+
+  for (i = 0; i < 8; i++)
+    e[i] = 0.0;
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c
new file mode 100644
index 000000000..01eef2a4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-setzero-si256-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256i_q u;
+  long long e [4];
+
+  u.x = _mm256_setzero_si256 ();
+
+  for (i = 0; i < 4; i++)
+    e[i] = 0;
+
+  if (check_union256i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c
new file mode 100644
index 000000000..a1ee6d461
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-trunc-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-truncf-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c
new file mode 100644
index 000000000..a1ee6d461
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-truncf-vec.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx" } */
+/* { dg-require-effective-target avx } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-truncf-vec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c
new file mode 100644
index 000000000..afed3d035
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-addpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c
new file mode 100644
index 000000000..2d0394354
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_add_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c
new file mode 100644
index 000000000..ba905097f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-addps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c
new file mode 100644
index 000000000..363a4dedb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_add_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c
new file mode 100644
index 000000000..5c562a01d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-addsd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c
new file mode 100644
index 000000000..093f61b63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-addss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c
new file mode 100644
index 000000000..7c0fc2fdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-addsubpd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c
new file mode 100644
index 000000000..7f431ec36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubpd-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_addsub_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    if (i % 2)
+      e[i] = s1.a[i] + s2.a[i];
+    else 
+      e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c
new file mode 100644
index 000000000..1dbe3f353
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-addsubps.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c
new file mode 100644
index 000000000..e6977f9b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaddsubps-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_addsub_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    if (i % 2)
+      e[i] = s1.a[i] + s2.a[i];
+    else 
+      e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c
new file mode 100644
index 000000000..c926dd197
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesdec-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesdec.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c
new file mode 100644
index 000000000..467462606
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesdeclast-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesdeclast.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c
new file mode 100644
index 000000000..313f10105
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesenc-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesenc.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c
new file mode 100644
index 000000000..0df9130ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesenclast-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesenclast.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c
new file mode 100644
index 000000000..29f910a47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaesimc-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aesimc.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c
new file mode 100644
index 000000000..7c0d564a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vaeskeygenassist-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vaes } */
+/* { dg-options "-O2 -maes -mavx" } */
+
+#define CHECK_H "aes-avx-check.h"
+#define TEST aes_avx_test
+
+#include "aeskeygenassist.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c
new file mode 100644
index 000000000..c5f3c1d38
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-andnpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c
new file mode 100644
index 000000000..27e4ccdd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnpd-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  long long source1[4]={34545, 95567, 23443, 5675};
+  long long source2[4]={674, 57897, 93459, 45624};
+  long long d[4];
+  long long e[4];
+
+  s1.x = _mm256_loadu_pd ((double *)source1);
+  s2.x = _mm256_loadu_pd ((double *)source2);
+  u.x = _mm256_andnot_pd (s1.x, s2.x);
+
+  _mm256_storeu_pd ((double *)d, u.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (~source1[i]) & source2[i];
+
+  if (checkVl (d, e, 4))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c
new file mode 100644
index 000000000..357db7e8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-andnps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c
new file mode 100644
index 000000000..7b5a3dbe8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandnps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  int source1[8]={34545, 95567, 23443, 5675, 2323, 67, 2345, 45667};
+  int source2[8]={674, 57897, 93459, 45624, 54674, 1237, 67436, 79608};
+  int d[8];
+  int e[8];
+
+  s1.x = _mm256_loadu_ps ((float *)source1);
+  s2.x = _mm256_loadu_ps ((float *)source2);
+  u.x = _mm256_andnot_ps (s1.x, s2.x);
+
+  _mm256_storeu_ps ((float *)d, u.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (~source1[i]) & source2[i];
+
+  if (checkVi (d, e, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c
new file mode 100644
index 000000000..0a9532d5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-andpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c
new file mode 100644
index 000000000..b0675ec65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandpd-256-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+
+  union
+  {
+     double d[4];
+     long long ll[4];
+  }source1, source2, e;
+
+  s1.x = _mm256_set_pd (345.45, 95567, 2344.3, 567.5);
+  s2.x = _mm256_set_pd (674, 57.897, 934.59, 4562.4);
+
+  _mm256_storeu_pd (source1.d, s1.x);
+  _mm256_storeu_pd (source2.d, s2.x);
+
+  u.x = _mm256_and_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e.ll[i] = source1.ll[i] & source2.ll[i];
+
+  if (check_union256d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandps-1.c
new file mode 100644
index 000000000..54bba79ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-andps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c
new file mode 100644
index 000000000..4dc123bf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vandps-256-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  
+  union
+  {
+    float f[8];
+    int   i[8];
+  }source1, source2, e;
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+  
+  _mm256_storeu_ps (source1.f, s1.x);
+  _mm256_storeu_ps (source2.f, s2.x);
+
+  u.x = _mm256_and_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e.i[i] = source1.i[i] & source2.i[i];
+
+  if (check_union256 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c
new file mode 100644
index 000000000..0a9031f44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-blendpd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c
new file mode 100644
index 000000000..39e7c1bd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendpd-256-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 12
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (34545, 95567, 23443, 5675);
+  s2.x = _mm256_set_pd (674, 57897, 93459, 45624);
+  u.x = _mm256_blend_pd (s1.x, s2.x, MASK);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (MASK & (0x01 << i)) ? s2.a[i] : s1.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c
new file mode 100644
index 000000000..9f5dde29f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendps-256-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 114
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+  u.x = _mm256_blend_ps (s1.x, s2.x, MASK);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (MASK & (0x01 << i)) ? s2.a[i] : s1.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c
new file mode 100644
index 000000000..2f668c22e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendvpd-256-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 6
+#endif
+
+#define mask_v(pos) (((MASK >> (pos)) & 1ULL) << 63)
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, mask, s1, s2;
+  long long m[4]={mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+  double e [4];
+
+  s1.x = _mm256_set_pd (34545, 95567, 23443, 5675);
+  s2.x = _mm256_set_pd (674, 57897, 93459, 45624);
+  mask.x = _mm256_set_pd (m[0], m[1], m[2], m[3]);
+
+  u.x = _mm256_blendv_pd (s1.x, s2.x, mask.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (m[i] & (1ULL << 63)) ? s2.a[i] : s1.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c
new file mode 100644
index 000000000..0e48d690e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vblendvps-256-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 214
+#endif
+
+#define mask_v(pos) (((MASK >> (pos)) & 1U) << 31)
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, mask, s1, s2;
+  int m[8]={mask_v(0), mask_v(1), mask_v(2), mask_v(3), 
+            mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
+  float e [8];
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+  mask.x = _mm256_loadu_ps ((float *)m);
+
+  u.x = _mm256_blendv_ps (s1.x, s2.x, mask.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (m[i] & (1ULL << 31)) ? s2.a[i] : s1.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c
new file mode 100644
index 000000000..e0cddd1a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u;
+  union128 s;
+  float e [8];
+
+  s.x = _mm_set_ps(24.43, 68.346, 43.35, 546.46);
+  u.x = _mm256_broadcast_ps (&s.x);
+
+  for (i = 0; i < 4; i++)
+    e[i+4] = e[i] = s.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c
new file mode 100644
index 000000000..eb4ec579b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastf128-256-2.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u;
+  union128d s;
+  double e [4];
+
+  s.x = _mm_set_pd(24.43, 68.346);
+  u.x = _mm256_broadcast_pd (&s.x);
+
+  e[0] = e[2] = s.a[0];
+  e[1] = e[3] = s.a[1];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c
new file mode 100644
index 000000000..329405f31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastsd-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  double s = 39678;
+  union256d u;
+  double e [4];
+
+  u.x = _mm256_broadcast_sd (&s);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s;
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c
new file mode 100644
index 000000000..d6bf2ce61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  float s = 39678.3452;
+  union256 u;
+  float e [8];
+
+  u.x = _mm256_broadcast_ss (&s);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s;
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c
new file mode 100644
index 000000000..56723cb28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vbroadcastss-2.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  float s = 39678.3452;
+  union128 u;
+  float e [4];
+
+  u.x = _mm_broadcast_ss (&s);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s;
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c
new file mode 100644
index 000000000..f9646a10d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmppd-1.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+double s1[2]={2134.3343,6678.346};
+double s2[2]={41124.234,6678.346};
+long long  e[2];
+
+union
+{
+  double d[2];
+  long long ll[2];
+}d;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVl(d.ll, e, 2)){
+	printf("mm_cmp_pd(%s: 0x%x) FAILED\n", id, imm);
+    }
+}
+
+#define CMP(imm, rel)					\
+    for (i = 0; i < 2; i++) e[i] = rel ? -1 : 0;	\
+    source1 = _mm_loadu_pd(s1);				\
+    source2 = _mm_loadu_pd(s2);				\
+    dest = _mm_cmp_pd(source1, source2, imm);		\
+    _mm_storeu_pd(d.d, dest);			\
+    check(imm, "" #imm "");
+
+static void
+avx_test ()
+{
+    __m128d source1, source2, dest;
+    int i;
+
+    d.ll[0] = e[0] = 222;
+    d.ll[1] = e[1] = -33;
+    
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1);
+    
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c
new file mode 100644
index 000000000..1c169f5ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmppd-256-1.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+double s1[4]={2134.3343,6678.346,453.345635,54646.464356};
+double s2[4]={41124.234,6678.346,8653.65635,856.43576};
+long long e[4];
+
+union
+{
+  double d[4];
+  long long ll[4];
+}d;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVl(d.ll, e, 4)){
+	printf("mm256_cmp_pd(%s: 0x%x) FAILED\n", id, imm);
+    }
+}
+
+#define CMP(imm, rel)					\
+    for (i = 0; i < 4; i++) e[i] = rel ? -1 : 0;	\
+    source1 = _mm256_loadu_pd(s1);			\
+    source2 = _mm256_loadu_pd(s2);			\
+    dest = _mm256_cmp_pd(source1, source2, imm);	\
+    _mm256_storeu_pd(d.d, dest);		\
+    check(imm, "" #imm "");
+
+static void
+avx_test ()
+{
+    __m256d source1, source2, dest;
+    int i;
+    
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1);
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c
new file mode 100644
index 000000000..888f9eb28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpps-1.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+float s1[4]={2134.3343,6678.346,453.345635,54646.464356};
+float s2[4]={41124.234,6678.346,8653.65635,856.43576};
+int e[4];
+
+union
+{
+  float f[4];
+  int   i[4];
+}d;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVi(d.i, e, 4)){
+	printf("mm_cmp_ps(0x%x, %s) FAILED\n", imm, id);
+    }
+}
+
+static void
+avx_test ()
+{
+    __m128 source1, source2, dest;
+    int i;
+
+#define CMP(imm, rel)					\
+    for (i = 0; i < 4; i++) e[i] = rel ? -1 : 0;	\
+    source1 = _mm_loadu_ps(s1);				\
+    source2 = _mm_loadu_ps(s2);				\
+    dest = _mm_cmp_ps(source1, source2, imm);		\
+    _mm_storeu_ps(d.f, dest);			\
+    check(imm, "" #imm "");
+
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c
new file mode 100644
index 000000000..b82abb6dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpps-256-1.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+float s1[8]={2134.3343,6678.346,453.345635,54646.464356,456,678567,123,2346};
+float s2[8]={41124.234,6678.346,8653.65635,856.43576,7456,134,539,54674};
+int e[8];
+
+union
+{
+  float f[8];
+  int   i[8];
+}d;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVi(d.i, e, 8)){
+	printf("mm256_cmp_ps(0x%x, %s) FAILED\n", imm, id);
+    }
+}
+
+static void
+avx_test ()
+{
+    __m256 source1, source2, dest;
+    int i;
+
+#define CMP(imm, rel)					\
+    for (i = 0; i < 8; i++) e[i] = rel ? -1 : 0;	\
+    source1 = _mm256_loadu_ps(s1);			\
+    source2 = _mm256_loadu_ps(s2);			\
+    dest = _mm256_cmp_ps(source1, source2, imm);	\
+    _mm256_storeu_ps(d.f, dest);		        \
+    check(imm, "" #imm "");
+
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c
new file mode 100644
index 000000000..9b6d58028
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpsd-1.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+double s1[] = {2134.3343, 6678.346};
+double s2[] = {41124.234, 6678.346};
+long long dd[] =  {1, 2}, d[2];
+union{long long l[2]; double d[2];} e;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVl(d, e.l, 2)){
+	printf("mm_cmp_sd(%s: 0x%x) FAILED\n", id, imm);
+    }
+}
+
+#define CMP(imm, rel)					\
+    e.l[0] = rel ? -1 : 0;	                        \
+    dest = _mm_loadu_pd((double*)dd);	      		\
+    source1 = _mm_loadu_pd(s1);				\
+    source2 = _mm_loadu_pd(s2);				\
+    dest = _mm_cmp_sd(source1, source2, imm);		\
+    _mm_storeu_pd((double*) d, dest);			\
+    check(imm, "" #imm "");
+
+static void
+avx_test ()
+{
+    __m128d source1, source2, dest;
+
+    e.d[1] = s1[1];
+    
+    CMP(_CMP_EQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OS, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OS, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_US, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_US, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[0], s2[0]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_US, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_US, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OS, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OS, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_S, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_US, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_S, !isunordered(s1[0], s2[0]));
+    CMP(_CMP_EQ_US, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_US, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c
new file mode 100644
index 000000000..0dd1b0922
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcmpss-1.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx -std=c99" } */
+
+#include "avx-check.h"
+#include <math.h>
+
+float s1[]={2134.3343, 6678.346, 453.345635, 54646.464356};
+float s2[]={41124.234, 6678.346, 8653.65635, 856.43576};
+int dd[] = {1, 2, 3, 4};
+float d[4];
+union{int i[4]; float f[4];} e;
+
+void check(unsigned imm, char *id)
+{
+    if(checkVi((int*)d, e.i, 4)){
+	printf("mm_cmp_ss(0x%x, %s) FAILED\n", imm, id);
+    }
+}
+
+static void
+avx_test ()
+{
+    __m128 source1, source2, dest;
+    int i;
+
+#define CMP(imm, rel)					\
+    e.i[0] = rel ? -1 : 0;	                        \
+    dest = _mm_loadu_ps((float*)dd);			\
+    source1 = _mm_loadu_ps(s1);				\
+    source2 = _mm_loadu_ps(s2);				\
+    dest = _mm_cmp_ss(source1, source2, imm);		\
+    _mm_storeu_ps(d, dest);			        \
+    check(imm, "" #imm "");
+
+    for(i = 1; i < 4; i++) e.f[i] = s1[i];
+    
+    CMP(_CMP_EQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OS, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OS, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_US, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_US, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[0], s2[0]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_US, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_US, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OS, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OS, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_S, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_US, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_S, !isunordered(s1[0], s2[0]));
+    CMP(_CMP_EQ_US, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_US, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c
new file mode 100644
index 000000000..419249b46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c
new file mode 100644
index 000000000..9f757ef04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c
new file mode 100644
index 000000000..3bb5453c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c
new file mode 100644
index 000000000..f5c7a5d3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-4.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c
new file mode 100644
index 000000000..314cb09ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-5.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-5.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c
new file mode 100644
index 000000000..72f54138f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomisd-6.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-comisd-6.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c
new file mode 100644
index 000000000..6b214fd11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c
new file mode 100644
index 000000000..f83b977a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c
new file mode 100644
index 000000000..a2db9e91c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c
new file mode 100644
index 000000000..530dfc0c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-4.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c
new file mode 100644
index 000000000..b149736b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-5.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-5.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c
new file mode 100644
index 000000000..45e94daf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcomiss-6.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-comiss-6.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c
new file mode 100644
index 000000000..5d08be902
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtdq2pd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c
new file mode 100644
index 000000000..4b39ffe9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2pd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union128i_d s1;
+  union256d u;
+  double e [4];
+
+  s1.x = _mm_set_epi32 (2134.3343,1234.635654,453.345635,54646.464356);
+  u.x = _mm256_cvtepi32_pd (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (double)s1.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c
new file mode 100644
index 000000000..1e2ad6254
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtdq2ps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtdq2ps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c
new file mode 100644
index 000000000..752497514
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtpd2dq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c
new file mode 100644
index 000000000..30e93af92
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2dq-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d s1;
+  union128i_d u;
+  int e [4];
+
+  s1.x = _mm256_set_pd (2.78, 7777768.82, 23.67, 536.46);
+  u.x = _mm256_cvtpd_epi32 (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (int)(s1.a[i] + 0.5);
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c
new file mode 100644
index 000000000..5bc43d561
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtpd2ps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c
new file mode 100644
index 000000000..987f2b263
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtpd2ps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d s1;
+  union128 u;
+  float e [4];
+
+  s1.x = _mm256_set_pd (2.43, 68.46, 23.35, 536.46);
+  u.x = _mm256_cvtpd_ps (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (float)s1.a[i];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c
new file mode 100644
index 000000000..36d90a265
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtps2dq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c
new file mode 100644
index 000000000..47ec12b8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2dq-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 s1;
+  union256i_d u;
+  int e [8];
+
+  s1.x = _mm256_set_ps (2.78, 77768.82, 23.67, 536.46, 4564.6575, 568.1263, 9889.2422, 7352.4563);
+  u.x = _mm256_cvtps_epi32 (s1.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (int)(s1.a[i] + 0.5);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c
new file mode 100644
index 000000000..114a71976
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtps2pd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c
new file mode 100644
index 000000000..9d48998a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtps2pd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union128 s1;
+  union256d u;
+  double e [4];
+
+  s1.x = _mm_set_ps (2.43, 68.46, 23.35, 536.46);
+  u.x = _mm256_cvtps_pd (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (double)s1.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c
new file mode 100644
index 000000000..53c61a2ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsd2si-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c
new file mode 100644
index 000000000..f462c6365
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2si-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsd2si-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c
new file mode 100644
index 000000000..c0e224d06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsd2ss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsd2ss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c
new file mode 100644
index 000000000..35da346d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsi2sd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c
new file mode 100644
index 000000000..36f411e59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2sd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtsi2sd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c
new file mode 100644
index 000000000..12ac36c72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvtsi2ss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c
new file mode 100644
index 000000000..8dc0b35c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtsi2ss-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvtsi2ss-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c
new file mode 100644
index 000000000..0f6365c35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2sd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvtss2sd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c
new file mode 100644
index 000000000..3a51ff168
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvtss2si-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c
new file mode 100644
index 000000000..b9afab7f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvtss2si-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvtss2si-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c
new file mode 100644
index 000000000..f27160a6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvttpd2dq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c
new file mode 100644
index 000000000..16edf8ac7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttpd2dq-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d s1;
+  union128i_d u;
+  int e [4];
+
+  s1.x = _mm256_set_pd (2.43, 68.78, 23.61, 536.46);
+  u.x = _mm256_cvttpd_epi32 (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (int)s1.a[i];
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c
new file mode 100644
index 000000000..f8ab025db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvttps2dq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c
new file mode 100644
index 000000000..0a580f015
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttps2dq-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 s1;
+  union256i_d u;
+  int e [8];
+
+  s1.x = _mm256_set_ps (45.64, 4564.56, 2.3, 5.5, 57.57, 89.34, 54.12, 954.67);
+  u.x = _mm256_cvttps_epi32 (s1.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (int)s1.a[i];
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c
new file mode 100644
index 000000000..b9963d4ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvttsd2si-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c
new file mode 100644
index 000000000..84bdb9f3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttsd2si-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-cvttsd2si-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c
new file mode 100644
index 000000000..94c94c1d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvttss2si-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c
new file mode 100644
index 000000000..b3c68eaf6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vcvttss2si-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-cvttss2si-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c
new file mode 100644
index 000000000..57ddfd1f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-divpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c
new file mode 100644
index 000000000..1840e3d56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_div_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] / s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c
new file mode 100644
index 000000000..d4fcaebdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-divps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c
new file mode 100644
index 000000000..3ff4c7ee2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e[8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_div_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] / s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c
new file mode 100644
index 000000000..faca3ed1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-divsd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c
new file mode 100644
index 000000000..f5740eba4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdivss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-divss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c
new file mode 100644
index 000000000..7d04cc4bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdppd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-dppd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c
new file mode 100644
index 000000000..6e30faf45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdppd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-dppd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c
new file mode 100644
index 000000000..75ba0be5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdpps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-dpps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c
new file mode 100644
index 000000000..b54b90969
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vdpps-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-dpps-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c
new file mode 100644
index 000000000..4919d640f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 1
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  union256d s1;
+  union128d u;
+  double e [2];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  u.x = _mm256_extractf128_pd (s1.x, OFFSET);
+
+  __builtin_memcpy (e, s1.a + OFFSET * 2, sizeof e);
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c
new file mode 100644
index 000000000..db26e181c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 1
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  union256 s1;
+  union128 u;
+  float e [4];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  u.x = _mm256_extractf128_ps (s1.x, OFFSET);
+
+  __builtin_memcpy (e, s1.a + OFFSET * 4, sizeof e);
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-3.c
new file mode 100644
index 000000000..b7d4a3731
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-3.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define OFFSET 0
+
+#include "avx-vextractf128-256-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-4.c
new file mode 100644
index 000000000..973fa58b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractf128-256-4.c
@@ -0,0 +1,7 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define OFFSET 0
+
+#include "avx-vextractf128-256-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c
new file mode 100644
index 000000000..4215c34dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vextractps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-extractps.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c
new file mode 100644
index 000000000..7809c850c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-haddpd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c
new file mode 100644
index 000000000..b9245a368
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddpd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_hadd_pd (s1.x, s2.x);
+
+  e[0] = s1.a[0] + s1.a[1];
+  e[1] = s2.a[0] + s2.a[1];
+  e[2] = s1.a[2] + s1.a[3];
+  e[3] = s2.a[2] + s2.a[3];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c
new file mode 100644
index 000000000..73dcfb6c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-haddps.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c
new file mode 100644
index 000000000..fbc58238a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhaddps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_hadd_ps (s1.x, s2.x);
+
+  e[0] = s1.a[0] + s1.a[1];
+  e[1] = s1.a[2] + s1.a[3];
+  e[2] = s2.a[0] + s2.a[1];
+  e[3] = s2.a[2] + s2.a[3];
+  e[4] = s1.a[4] + s1.a[5];
+  e[5] = s1.a[6] + s1.a[7];
+  e[6] = s2.a[4] + s2.a[5];
+  e[7] = s2.a[6] + s2.a[7];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c
new file mode 100644
index 000000000..68d14327a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-hsubpd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c
new file mode 100644
index 000000000..df710d7f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubpd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_hsub_pd (s1.x, s2.x);
+
+  e[0] = s1.a[0] - s1.a[1];
+  e[1] = s2.a[0] - s2.a[1];
+  e[2] = s1.a[2] - s1.a[3];
+  e[3] = s2.a[2] - s2.a[3];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c
new file mode 100644
index 000000000..2ddd2c0c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-hsubps.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c
new file mode 100644
index 000000000..aa601c8a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vhsubps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_hsub_ps (s1.x, s2.x);
+
+  e[0] = s1.a[0] - s1.a[1];
+  e[1] = s1.a[2] - s1.a[3];
+  e[2] = s2.a[0] - s2.a[1];
+  e[3] = s2.a[2] - s2.a[3];
+  e[4] = s1.a[4] - s1.a[5];
+  e[5] = s1.a[6] - s1.a[7];
+  e[6] = s2.a[4] - s2.a[5];
+  e[7] = s2.a[6] - s2.a[7];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c
new file mode 100644
index 000000000..2390e5c7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 1
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1;
+  union128d s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm_set_pd (68543.731254, 3452.578238);
+  u.x = _mm256_insertf128_pd (s1.x, s2.x, OFFSET);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i];
+
+  for (i=0; i < 2; i++)
+    e[i + (OFFSET * 2)] = s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c
new file mode 100644
index 000000000..ce0b23bbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 0
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1;
+  union128 s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (39.467, 45.789, 78.342, 67.892, 76.678, 12.963, 29.746, 24.753);
+  s2.x = _mm_set_ps (57.493, 38.395, 22.479, 31.614);
+  u.x = _mm256_insertf128_ps (s1.x, s2.x, OFFSET);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i];
+
+  for (i=0; i < 4; i++)
+    e[i + (OFFSET * 4)] = s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c
new file mode 100644
index 000000000..89834d554
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertf128-256-3.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef OFFSET
+#define OFFSET 0
+#endif
+
+#if OFFSET < 0 || OFFSET > 1
+#error OFFSET must be within [0..1]
+#endif
+
+void static
+avx_test (void)
+{
+  int i;
+  union256i_d u, s1;
+  union128i_d s2;
+  int e [8];
+
+  s1.x = _mm256_set_epi32 (39467, 45789, 78342, 67892, 76678, 12963, 29746, 24753);
+  s2.x = _mm_set_epi32 (57493, 38395, 22479, 31614);
+  u.x = _mm256_insertf128_si256 (s1.x, s2.x, OFFSET);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i];
+
+  for (i=0; i < 4; i++)
+    e[i + (OFFSET * 4)] = s2.a[i];
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c
new file mode 100644
index 000000000..ad1f33308
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-insertps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c
new file mode 100644
index 000000000..7b93174aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-insertps-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c
new file mode 100644
index 000000000..515ee418c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target ia32 } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -mtune=geode" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-insertps-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-4.c
new file mode 100644
index 000000000..527b070f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vinsertps-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-insertps-4.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c
new file mode 100644
index 000000000..7ecea79e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vlddqu-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-lddqu.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c
new file mode 100644
index 000000000..82c0ed580
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vlddqu-256-1.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int e[8]={ 23, 67, 53, 6, 4, 6, 85, 234};
+  union256i_d u;
+
+  u.x = _mm256_lddqu_si256 ((__m256i *) e);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c
new file mode 100644
index 000000000..24b5bba77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovdqu.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-maskmovdqu.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c
new file mode 100644
index 000000000..6204ebd28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 7
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx_test (void)
+{
+  int i;
+  long long m[2] = {mask_v(0), mask_v(1)};
+  double s[2] = {1.1, 2.2};
+  union128d u;
+  union128i_q mask;
+  double e[2] = {0.0};
+
+  mask.x = _mm_loadu_si128 ((__m128i *)m);
+  u.x = _mm_maskload_pd (s, mask.x);
+
+  for (i = 0 ; i < 2; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c
new file mode 100644
index 000000000..6bc620755
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 6
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx_test (void)
+{
+  int i;
+  long long m[2] = {mask_v(0), mask_v(1)};
+  double s[2] = {1.1, 2.2};
+  double e[2] = {0.0};
+  double d[2] = {0.0};
+  union128d src;
+  union128i_q mask;
+  
+  src.x = _mm_loadu_pd (s);
+  mask.x = _mm_loadu_si128 ((__m128i *)m);
+  _mm_maskstore_pd (d, mask.x, src.x);
+
+  for (i = 0 ; i < 2; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (checkVd (d, e, 2))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c
new file mode 100644
index 000000000..e591c05c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 7
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx_test (void)
+{
+  int i;
+  long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+  double s[4] = {1.1, 2.2, 3.3, 4.4};
+  union256d u;
+  union256i_q mask;
+  double e [4] = {0.0};
+
+  mask.x = _mm256_loadu_si256 ((__m256i *)m);
+  u.x = _mm256_maskload_pd (s, mask.x);
+
+  for (i = 0 ; i < 4; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c
new file mode 100644
index 000000000..5df2f94ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 6
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx_test (void)
+{
+  int i;
+  long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+  double s[4] = {1.1, 2.2, 3.3, 4.4};
+  double e [4] = {0.0};
+  double d [4] = {0.0};
+  union256d src;
+  union256i_q mask;
+  
+  src.x = _mm256_loadu_pd (s);
+  mask.x = _mm256_loadu_si256 ((__m256i *)m);
+  _mm256_maskstore_pd (d, mask.x, src.x);
+
+  for (i = 0 ; i < 4; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (checkVd (d, e, 4))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c
new file mode 100644
index 000000000..360a04dba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 134
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx_test (void)
+{
+  int i;
+  int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+  float s[4] = {1,2,3,4};
+  union128 u;
+  union128i_d mask;
+  float e[4] = {0.0};
+
+  mask.x = _mm_loadu_si128 ((__m128i *)m);
+  u.x = _mm_maskload_ps (s, mask.x);
+
+  for (i = 0 ; i < 4; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c
new file mode 100644
index 000000000..3dde96557
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 214
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx_test (void)
+{
+  int i;
+  int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+  float s[4] = {1,2,3,4};
+  union128 src;
+  union128i_d mask;
+  float e[4] = {0.0};
+  float d[4] = {0.0};
+
+  src.x = _mm_loadu_ps (s);
+  mask.x = _mm_loadu_si128 ((__m128i *)m);
+  _mm_maskstore_ps (d, mask.x, src.x);
+
+  for (i = 0 ; i < 4; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (checkVf (d, e, 4))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c
new file mode 100644
index 000000000..647ce3f6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 134
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx_test (void)
+{
+  int i;
+  int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
+  float s[8] = {1,2,3,4,5,6,7,8};
+  union256 u;
+  union256i_d mask;
+  float e [8] = {0.0};
+
+  mask.x = _mm256_loadu_si256 ((__m256i *)m);
+  u.x = _mm256_maskload_ps (s, mask.x);
+
+  for (i = 0 ; i < 8; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c
new file mode 100644
index 000000000..016904d46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 214
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx_test (void)
+{
+  int i;
+  int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
+  float s[8] = {1,2,3,4,5,6,7,8};
+  union256 src;
+  union256i_d mask;
+  float e [8] = {0.0};
+  float d [8] = {0.0};
+
+  src.x = _mm256_loadu_ps (s);
+  mask.x = _mm256_loadu_si256 ((__m256i *)m);
+  _mm256_maskstore_ps (d, mask.x, src.x);
+
+  for (i = 0 ; i < 8; i++) 
+    e[i] = m[i] ? s[i] : 0;
+   
+  if (checkVf (d, e, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c
new file mode 100644
index 000000000..981e2a5b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-maxpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c
new file mode 100644
index 000000000..7b9c91c03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_max_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] > s2.a[i] ? s1.a[i] : s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c
new file mode 100644
index 000000000..e4c41450d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-maxps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c
new file mode 100644
index 000000000..44bb7ed9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9);
+  u.x = _mm256_max_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] > s2.a[i] ? s1.a[i] : s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c
new file mode 100644
index 000000000..e24410cd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-maxsd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c
new file mode 100644
index 000000000..afe5d0adb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmaxss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-maxss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c
new file mode 100644
index 000000000..a7eb64972
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-minpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c
new file mode 100644
index 000000000..555e029bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_min_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] < s2.a[i] ? s1.a[i] : s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminps-1.c
new file mode 100644
index 000000000..dfb07ba23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-minps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c
new file mode 100644
index 000000000..19ac83a72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9);
+  u.x = _mm256_min_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] < s2.a[i] ? s1.a[i] : s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c
new file mode 100644
index 000000000..5aa1d9aa0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-minsd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminss-1.c
new file mode 100644
index 000000000..c2e6f2799
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vminss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-minss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c
new file mode 100644
index 000000000..5d97a5d2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movapd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c
new file mode 100644
index 000000000..9856d2907
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movapd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c
new file mode 100644
index 000000000..cc524c8a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline, unused))
+test (double *e)
+{
+  return _mm256_load_pd (e);
+}
+
+void static
+avx_test (void)
+{
+  union256d u;
+  double e [4] __attribute__ ((aligned (32)))  = {41124.234,2344.2354,8653.65635,856.43576};
+
+  u.x = test (e);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c
new file mode 100644
index 000000000..9224484ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovapd-256-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m256d a)
+{
+  return _mm256_store_pd (e, a);
+}
+
+void static
+avx_test (void)
+{
+  union256d u;
+  double e [4] __attribute__ ((aligned (32))) = {0.0};
+
+  u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);
+
+  test (e, u.x);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c
new file mode 100644
index 000000000..a10894c35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movaps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c
new file mode 100644
index 000000000..ad0cf47c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movaps-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c
new file mode 100644
index 000000000..74681c326
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm256_load_ps (e);
+}
+
+void static
+avx_test (void)
+{
+  union256 u;
+  float e [8] __attribute__ ((aligned (32)))  = {24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4};
+
+  u.x = test (e);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c
new file mode 100644
index 000000000..dbd5227c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovaps-256-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m256 a)
+{
+  return _mm256_store_ps (e, a);
+}
+
+void static
+avx_test (void)
+{
+  union256 u;
+  float e [8] __attribute__ ((aligned (32))) = {0.0};
+
+  u.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9);
+
+  test (e, u.x);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c
new file mode 100644
index 000000000..cdaec13cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c
new file mode 100644
index 000000000..02b0d2229
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c
new file mode 100644
index 000000000..4db42e137
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovddup-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-movddup.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c
new file mode 100644
index 000000000..a971dbf4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovddup-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1;
+  double e [4];
+
+  s1.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);
+  u.x = _mm256_movedup_pd (s1.x);
+
+  for (i = 0; i < 2; i++)
+    e[2*i] = e[2*i+1] = s1.a[2*i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c
new file mode 100644
index 000000000..b14aeaff9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movdqa-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c
new file mode 100644
index 000000000..94a758d2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movdqa-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c
new file mode 100644
index 000000000..abe62880e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256i
+__attribute__ ((noinline, unused))
+test (__m256i *p)
+{
+  return _mm256_load_si256 (p);
+}
+
+void static
+avx_test (void)
+{
+  union256i_d u;
+  int e [8] __attribute__ ((aligned (32))) = {23, 67, 53, 6, 4, 6, 85, 234};
+
+  u.x = test ((__m256i *)e);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c
new file mode 100644
index 000000000..41f3ed0e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqa-256-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256i_d u;
+  int e [8] __attribute__ ((aligned (32))) = {0};
+
+  u.x = _mm256_set_epi32(23, 67, 53, 6, 4, 6, 85, 234);
+  _mm256_store_si256 ((__m256i *)e, u.x);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c
new file mode 100644
index 000000000..7785b40ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movdqu-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c
new file mode 100644
index 000000000..f0eead700
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movdqu-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c
new file mode 100644
index 000000000..849df7bc3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-1.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256i_d u;
+  int e [8] = {23, 67, 53, 6, 4, 6, 85, 234};
+
+  u.x = _mm256_loadu_si256 ((__m256i *) e); 
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c
new file mode 100644
index 000000000..eb0af202c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovdqu-256-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256i_d u;
+  int e [8] = {0};
+
+  u.x = _mm256_set_epi32(23, 67, 53, 6, 4, 6, 85, 234);
+  _mm256_storeu_si256 ((__m256i *)e, u.x);
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c
new file mode 100644
index 000000000..25beca971
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhlps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movhlps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c
new file mode 100644
index 000000000..246275cd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movhpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c
new file mode 100644
index 000000000..1cfdf59c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhpd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movhpd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c
new file mode 100644
index 000000000..8cf1eec8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movhps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c
new file mode 100644
index 000000000..c835f1512
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovhps-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movhps-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c
new file mode 100644
index 000000000..8f8234b31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlhps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movlhps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c
new file mode 100644
index 000000000..64d90c6cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movlpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c
new file mode 100644
index 000000000..081956a9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovlpd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movlpd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c
new file mode 100644
index 000000000..07eb85185
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movmskpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c
new file mode 100644
index 000000000..71353c44d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskpd-256-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  int d;
+  union256d s1;
+  double source[4] = {-45, -3, -34.56, 35};
+  int e = 0;
+
+  s1.x = _mm256_loadu_pd (source);
+  d = _mm256_movemask_pd (s1.x);
+  
+  for (i = 0; i < 4; i++)
+    if (source[i] < 0)
+      e |= (1 << i);
+
+  if (checkVi (&d, &e, 1))
+    abort ();  
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c
new file mode 100644
index 000000000..df4d1e78d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movmskps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c
new file mode 100644
index 000000000..4b81d0413
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovmskps-256-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  int d;
+  union256 s1;
+  float source[8] = {-45, -3, -34.56, 35, 5.46,46, -464.3, 56};
+  int e = 0;
+
+  s1.x = _mm256_loadu_ps (source);
+  d = _mm256_movemask_ps (s1.x);
+  
+  for (i = 0; i < 8; i++)
+    if (source[i] < 0)
+      e |= (1 << i);
+
+  if (checkVi (&d, &e, 1))
+    abort ();  
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c
new file mode 100644
index 000000000..166d46f20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movntdq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c
new file mode 100644
index 000000000..5caf34e6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdq-256-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline))
+test (__m256i *p, __m256i s)
+{
+  return _mm256_stream_si256 (p, s); 
+}
+
+static void
+avx_test (void)
+{
+  union256i_d u;
+  int e[8] __attribute__ ((aligned(32))) = {1,1,1,1,1,1,1,1};
+
+  u.x = _mm256_set_epi32 (2434, 6845, 3789, 4683,
+			  4623, 2236, 8295, 1084);
+
+  test ((__m256i *)e, u.x);
+  
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c
new file mode 100644
index 000000000..c884d1e5e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntdqa-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-movntdqa.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c
new file mode 100644
index 000000000..d547a2a9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntpd-1.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movntpd-1.c"
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c
new file mode 100644
index 000000000..f17deafaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntpd-256-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void 
+__attribute__((noinline))
+test (double *p, __m256d s)
+{
+  return _mm256_stream_pd (p, s); 
+}
+
+static void
+avx_test (void)
+{
+  union256d u;
+  double e[4] __attribute__ ((aligned(32))) = {1,1,1,1};
+   
+  u.x = _mm256_set_pd (2134.3343, 1234.635654, -13443.35, 43.35345);
+  test (e, u.x); 
+   
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c
new file mode 100644
index 000000000..b9732f26d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movntps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c
new file mode 100644
index 000000000..9f79403f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovntps-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void 
+__attribute__((noinline))
+test (float *p, __m256 s)
+{
+  return _mm256_stream_ps (p, s); 
+}
+
+static void
+avx_test (void)
+{
+  union256 u;
+  float e[8] __attribute__ ((aligned(32)));
+
+  u.x = _mm256_set_ps (24.43, 68.346, -43.35, 546.46,
+		       46.9, -2.78, 82.9, -0.4);
+  test (e, u.x); 
+  
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c
new file mode 100644
index 000000000..44d202308
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c
new file mode 100644
index 000000000..8306d39cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movq-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c
new file mode 100644
index 000000000..a6d624749
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovq-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movq-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c
new file mode 100644
index 000000000..185784419
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movsd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c
new file mode 100644
index 000000000..672b25bfd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movsd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c
new file mode 100644
index 000000000..ee995e3a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovshdup-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-movshdup.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c
new file mode 100644
index 000000000..a4b57a0c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovshdup-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1;
+  float e[8];
+
+  s1.x = _mm256_set_ps (134.3, 1234.54, 45.335, 646.456, 43.54, 473.34, 78, 89.54);
+  u.x = _mm256_movehdup_ps (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[2*i] = e[2*i+1] = s1.a[2*i+1];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c
new file mode 100644
index 000000000..67ea717ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsldup-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse3-movsldup.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c
new file mode 100644
index 000000000..52127bec2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovsldup-256-1.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1;
+  float e[8];
+
+  s1.x = _mm256_set_ps (134.3, 1234.54, 45.335, 646.456, 43.54, 473.34, 78, 89.54);
+  u.x = _mm256_moveldup_ps (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[2*i] = e[2*i+1] = s1.a[2*i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c
new file mode 100644
index 000000000..ff983e6b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c
new file mode 100644
index 000000000..e9a8bdc59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movss-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c
new file mode 100644
index 000000000..b73e2af06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovss-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movss-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c
new file mode 100644
index 000000000..67f08744a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movupd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c
new file mode 100644
index 000000000..cb6f27763
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-movupd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c
new file mode 100644
index 000000000..8683a78da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256d
+__attribute__((noinline, unused))
+test (double *e)
+{
+  return _mm256_loadu_pd (e);
+}
+
+void static
+avx_test (void)
+{
+  union256d u;
+  double e [4]  = {41124.234,2344.2354,8653.65635,856.43576};
+
+  u.x = test (e);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c
new file mode 100644
index 000000000..4cbd0e7e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovupd-256-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m256d a)
+{
+  return _mm256_storeu_pd (e, a);
+}
+
+void static
+avx_test (void)
+{
+  union256d u;
+  double e [4] = {0.0};
+
+  u.x = _mm256_set_pd (39578.467285, 7856.342941, 85632.783567, 47563.234215);
+
+  test (e, u.x);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c
new file mode 100644
index 000000000..5b9a98b05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movups-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c
new file mode 100644
index 000000000..e5668a29a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-movups-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c
new file mode 100644
index 000000000..87d840998
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static __m256
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm256_loadu_ps (e);
+}
+
+void static
+avx_test (void)
+{
+  union256 u;
+  float e [8]  = {24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4};
+
+  u.x = test (e);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c
new file mode 100644
index 000000000..c1781979a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmovups-256-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m256 a)
+{
+  return _mm256_storeu_ps (e, a);
+}
+
+void static
+avx_test (void)
+{
+  union256 u;
+  float e [8]  = {0.0};
+
+  u.x = _mm256_set_ps (1.17, 24567.16, 3.15, 4567.14, 5.13, 65467.12, 788.11, 8.9);
+
+  test (e, u.x);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c
new file mode 100644
index 000000000..403423e66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmpsadbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-mpsadbw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c
new file mode 100644
index 000000000..0fa0f1ad7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-mulpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c
new file mode 100644
index 000000000..c6d9c4770
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_mul_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] * s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c
new file mode 100644
index 000000000..bb29e1945
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-mulps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c
new file mode 100644
index 000000000..518a9477d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_mul_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] * s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c
new file mode 100644
index 000000000..16adcde80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-mulsd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c
new file mode 100644
index 000000000..9ff6e3d14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vmulss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-mulss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c
new file mode 100644
index 000000000..221849ff1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-orpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c
new file mode 100644
index 000000000..ca60e24fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorpd-256-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+
+  union
+  {
+    double d[4];
+    long long ll[4];
+  }source1, source2, e;
+
+  s1.x = _mm256_set_pd (34545, 95567, 23443, 5675);
+  s2.x = _mm256_set_pd (674, 57897, 93459, 45624);
+
+  _mm256_storeu_pd (source1.d, s1.x);
+  _mm256_storeu_pd (source2.d, s2.x);
+
+  u.x = _mm256_or_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e.ll[i] = source1.ll[i] | source2.ll[i];
+
+  if (check_union256d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorps-1.c
new file mode 100644
index 000000000..fd501dd15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-orps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c
new file mode 100644
index 000000000..ef1c51b1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vorps-256-1.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+
+  union256 u, s1, s2;
+
+  union
+  {
+    float f[8];
+    int   i[8];
+  }source1, source2, e;
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+
+  _mm256_storeu_ps (source1.f, s1.x);
+  _mm256_storeu_ps (source2.f, s2.x);
+
+  u.x = _mm256_or_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e.i[i] = source1.i[i] | source2.i[i];
+
+  if (check_union256 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c
new file mode 100644
index 000000000..bd5b1fbe9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pabsb.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c
new file mode 100644
index 000000000..3ea84d808
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pabsd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c
new file mode 100644
index 000000000..6de79a5b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpabsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pabsw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c
new file mode 100644
index 000000000..f302ce716
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackssdw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-packssdw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c
new file mode 100644
index 000000000..14fd680a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpacksswb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-packsswb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c
new file mode 100644
index 000000000..81991d951
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackusdw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-packusdw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c
new file mode 100644
index 000000000..d06f3c779
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpackuswb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-packuswb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c
new file mode 100644
index 000000000..fa06c1e30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c
new file mode 100644
index 000000000..fc2ee2932
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c
new file mode 100644
index 000000000..bb913be9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c
new file mode 100644
index 000000000..56dc00b73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddsb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c
new file mode 100644
index 000000000..c326420e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddsw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c
new file mode 100644
index 000000000..a83bf6b7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddusb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddusb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c
new file mode 100644
index 000000000..8cbf06092
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddusw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddusw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c
new file mode 100644
index 000000000..caaa46666
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpaddw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-paddw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c
new file mode 100644
index 000000000..1a60b467f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpalignr-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-palignr.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpand-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpand-1.c
new file mode 100644
index 000000000..22e05701c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpand-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pand-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c
new file mode 100644
index 000000000..fbd7e25ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpandn-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pandn-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c
new file mode 100644
index 000000000..1474d2b1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpavgb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pavgb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c
new file mode 100644
index 000000000..1c7c3c89d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpavgw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pavgw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c
new file mode 100644
index 000000000..001799776
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpblendvb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pblendvb.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c
new file mode 100644
index 000000000..241dbcc6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpblendw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pblendw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c
new file mode 100644
index 000000000..9b015abcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpclmulqdq.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target vpclmul } */
+/* { dg-options "-O2 -mpclmul -mavx" } */
+
+#define CHECK_H "pclmul-avx-check.h"
+#define TEST pclmul_avx_test
+
+#include "pclmulqdq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c
new file mode 100644
index 000000000..9cd2bbcc1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpeqb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c
new file mode 100644
index 000000000..b1d1dd2d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpeqd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c
new file mode 100644
index 000000000..541b52c4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pcmpeqq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c
new file mode 100644
index 000000000..0e0397abd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpeqw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpeqw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c
new file mode 100644
index 000000000..806000f9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpestri-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c
new file mode 100644
index 000000000..6d683ef89
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestri-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpestri-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c
new file mode 100644
index 000000000..95b2bdc0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpestrm-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c
new file mode 100644
index 000000000..b2f6ad33d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpestrm-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpestrm-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c
new file mode 100644
index 000000000..ed9fd4d21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpgtb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c
new file mode 100644
index 000000000..344741eef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpgtd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c
new file mode 100644
index 000000000..1332215a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpgtq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c
new file mode 100644
index 000000000..c4f2007e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpgtw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pcmpgtw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c
new file mode 100644
index 000000000..4cb13535d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpistri-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c
new file mode 100644
index 000000000..ec2af713d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistri-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpistri-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c
new file mode 100644
index 000000000..7a6a4d4d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpistrm-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c
new file mode 100644
index 000000000..82857d813
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpcmpistrm-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_2-pcmpistrm-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c
new file mode 100644
index 000000000..99abca189
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-1.c
@@ -0,0 +1,63 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#define CONTROL 0xCC
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8);
+  s2.x = _mm256_set_ps (9, 10, 11, 12, 13, 14, 15, 16);
+  u.x = _mm256_permute2f128_ps (s1.x, s2.x, CONTROL);
+
+  switch (CONTROL & 0x3)
+    {
+      case 0:
+        __builtin_memcpy (e, s1.a, 16);
+        break;
+      case 1: 
+        __builtin_memcpy (e, s1.a+4, 16);
+        break;
+      case 2:
+        __builtin_memcpy (e, s2.a, 16);
+        break;
+      case 3:
+        __builtin_memcpy (e, s2.a+4, 16);
+        break;
+      default:
+        abort ();
+    }
+
+ switch ((CONTROL & 0xc)>>2)
+    {
+      case 0:
+        __builtin_memcpy (e+4, s1.a, 16);
+        break;
+      case 1: 
+        __builtin_memcpy (e+4, s1.a+4, 16);
+        break;
+      case 2:
+        __builtin_memcpy (e+4, s2.a, 16);
+        break;
+      case 3:
+        __builtin_memcpy (e+4, s2.a+4, 16);
+        break;
+      default:
+        abort ();
+    }
+
+  if (CONTROL & (1<<3))
+    __builtin_memset (e, 0, 16);
+
+  if (CONTROL & (1<<7))
+    __builtin_memset (e+4, 0, 16);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c
new file mode 100644
index 000000000..db9c65bce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef IMM8
+#  define IMM8 99
+#endif
+
+
+void static
+avx_test ()
+{
+    union256d source1, source2, u;
+    double  s1[4]={1, 2, 3, 4};
+    double  s2[4]={5, 6, 7, 8};
+    double   e[4];
+
+    source1.x = _mm256_loadu_pd(s1);
+    source2.x = _mm256_loadu_pd(s2);
+    u.x = _mm256_permute2f128_pd(source1.x, source2.x, IMM8);
+
+    if(IMM8 & 8) e[0] = e[1] = 0;
+    else{
+        e[0] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2];
+        e[1] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2 + 1];
+    }
+    if(IMM8 & 128) e[3] = e[3] = 0;
+    else{
+        unsigned m = (IMM8 >> 4) & 3;
+        e[2] = (m & 2 ? s2 : s1)[(m & 1) * 2];
+        e[3] = (m & 2 ? s2 : s1)[(m & 1) * 2 + 1];
+    }
+  
+   if (check_union256d (u, e))
+     abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c
new file mode 100644
index 000000000..7b00c4b76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vperm2f128-256-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef IMM8
+#  define IMM8 100
+#endif
+
+void static
+avx_test ()
+{
+    union256i_q source1, source2, u;
+    long long  s1[4]={1, 2, 3, 4};
+    long long  s2[4]={5, 6, 7, 8};
+    long long   e[4];
+
+    source1.x = _mm256_loadu_si256((__m256i*)s1);
+    source2.x = _mm256_loadu_si256((__m256i*)s2);
+    u.x = _mm256_permute2f128_si256(source1.x, source2.x, IMM8);
+
+    if(IMM8 & 8) e[0] = e[1] = 0;
+    else{
+        e[0] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2];
+        e[1] = (IMM8 & 2 ? s2 : s1)[(IMM8 & 1) * 2 + 1];
+    }
+    if(IMM8 & 128) e[3] = e[3] = 0;
+    else{
+        unsigned m = (IMM8 >> 4) & 3;
+        e[2] = (m & 2 ? s2 : s1)[(m & 1) * 2];
+        e[3] = (m & 2 ? s2 : s1)[(m & 1) * 2 + 1];
+    }
+   
+   if (check_union256i_q (u, e))
+     abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c
new file mode 100644
index 000000000..6379cdb4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 1
+#endif
+
+void static
+avx_test ()
+{
+    union128d u, src;
+    double s[2] = {9674.67456, 13543.9788};
+    double e[2];
+
+    src.x=_mm_loadu_pd(s);
+    u.x=_mm_permute_pd(src.x, CTRL);
+
+    e[0] = s[ (CTRL & 0x01)];
+    e[1] = s[((CTRL & 0x02) >> 1)];
+
+    if (check_union128d (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c
new file mode 100644
index 000000000..a6d7a0d67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 2
+#endif
+
+#define mask_v(pos) (((CTRL & (1ULL << (pos))) >> (pos)) << 1)
+
+void static
+avx_test ()
+{
+    union128d u, src;
+    union128i_q ctl;
+ 
+    double  s[2] = {9674.67456, 13543.9788};
+    long long m[2] = {mask_v(0), mask_v(1)};
+    double  e[2];
+
+    src.x = _mm_loadu_pd(s);
+    ctl.x = _mm_loadu_si128((__m128i*) m);
+    u.x = _mm_permutevar_pd(src.x, ctl.x);
+
+    e[0] = s[((m[0] & 0x02) >> 1)];
+    e[1] = s[((m[1] & 0x02) >> 1)];
+
+    if (check_union128d (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c
new file mode 100644
index 000000000..ca93474b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#define CONTROL 5
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  u.x = _mm256_permute_pd (s1.x, CONTROL);
+
+  e[0] = (CONTROL&0x01) ? s1.a[1] : s1.a[0];
+  e[1] = (CONTROL&0x02) ? s1.a[1] : s1.a[0];
+  e[2] = (CONTROL&0x04) ? s1.a[3] : s1.a[2];
+  e[3] = (CONTROL&0x08) ? s1.a[3] : s1.a[2];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c
new file mode 100644
index 000000000..1cd5c3a62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilpd-256-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 6
+#endif
+
+#define mask_v(pos) (((CTRL & (1ULL << (pos))) >> (pos)) << 1)
+
+void static
+avx_test ()
+{
+    union256d u, src; 
+    union256i_q ctl;
+
+    double  s[4] = {39578.467285, 7856.342941, 9674.67456, 13543.9788};
+    long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+    double  e[4] = {0.0};
+
+    src.x = _mm256_loadu_pd(s);
+    ctl.x  = _mm256_loadu_si256((__m256i*) m);
+    u.x = _mm256_permutevar_pd(src.x, ctl.x);
+
+    e[0] = s[0 + ((m[0] & 0x02) >> 1)];
+    e[1] = s[0 + ((m[1] & 0x02) >> 1)];
+    e[2] = s[2 + ((m[2] & 0x02) >> 1)];
+    e[3] = s[2 + ((m[3] & 0x02) >> 1)];
+
+    if (check_union256d (u, e))
+      abort ();
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c
new file mode 100644
index 000000000..146f55567
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 11
+#endif
+
+void static
+avx_test ()
+{
+  union128 u, s;
+  float e[4];
+
+  s.x = _mm_set_ps (1, 2, 3, 4);
+  u.x = _mm_permute_ps(s.x, CTRL);
+
+  e[0] = s.a[ (CTRL & 0x03)];
+  e[1] = s.a[((CTRL & 0x0c) >> 2)];
+  e[2] = s.a[((CTRL & 0x30) >> 4)];
+  e[3] = s.a[((CTRL & 0xc0) >> 6)];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c
new file mode 100644
index 000000000..ca0fbae4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 233
+#endif
+
+#define mask_v(pos) ((CTRL & (0x3 << (pos))) >> (pos))
+
+void static
+avx_test ()
+{
+    union128 u, s;
+    union128i_q ctl;
+    int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
+    float e[4];
+
+    s.x = _mm_set_ps (1, 2, 3, 4);
+    ctl.x = _mm_loadu_si128((__m128i*) m);
+    u.x = _mm_permutevar_ps(s.x, ctl.x);
+
+    e[0] = s.a[0 + (m[0] & 0x03)];
+    e[1] = s.a[0 + (m[1] & 0x03)];
+    e[2] = s.a[0 + (m[2] & 0x03)];
+    e[3] = s.a[0 + (m[3] & 0x03)];
+
+    if (check_union128 (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c
new file mode 100644
index 000000000..b9291498d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 129
+#endif
+
+void static
+avx_test ()
+{
+    union256 src, u;
+    float e[8] = {0.0};
+
+    src.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8);
+    u.x = _mm256_permute_ps(src.x, CTRL);
+
+    e[0] = src.a[0 +  (CTRL & 0x03)];
+    e[1] = src.a[0 + ((CTRL & 0x0c) >> 2)];
+    e[2] = src.a[0 + ((CTRL & 0x30) >> 4)];
+    e[3] = src.a[0 + ((CTRL & 0xc0) >> 6)];
+    e[4] = src.a[4 +  (CTRL & 0x03)];
+    e[5] = src.a[4 + ((CTRL & 0x0c) >> 2)];
+    e[6] = src.a[4 + ((CTRL & 0x30) >> 4)];
+    e[7] = src.a[4 + ((CTRL & 0xc0) >> 6)];
+
+    if (check_union256 (u, e))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c
new file mode 100644
index 000000000..9890410b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpermilps-256-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef CTRL
+#define CTRL 233
+#endif
+
+#define mask_v(pos) ((CTRL & (0x3 << (pos))) >> (pos))
+
+void static
+avx_test ()
+{
+    union256 u, s;
+    union256i_q ctl;
+    int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
+    float e[8];
+
+    s.x = _mm256_set_ps (1, 2, 3, 4, 5, 6, 7, 8);
+    ctl.x = _mm256_loadu_si256((__m256i*) m);
+    u.x = _mm256_permutevar_ps(s.x, ctl.x);
+
+    e[0] = s.a[0 + (m[0] & 0x03)];
+    e[1] = s.a[0 + (m[1] & 0x03)];
+    e[2] = s.a[0 + (m[2] & 0x03)];
+    e[3] = s.a[0 + (m[3] & 0x03)];
+    e[4] = s.a[4 + (m[4] & 0x03)];
+    e[5] = s.a[4 + (m[5] & 0x03)];
+    e[6] = s.a[4 + (m[6] & 0x03)];
+    e[7] = s.a[4 + (m[7] & 0x03)];
+
+    if (check_union256 (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c
new file mode 100644
index 000000000..4e1c64428
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pextrb.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c
new file mode 100644
index 000000000..bc67a2845
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pextrd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c
new file mode 100644
index 000000000..59e70b2d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pextrq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c
new file mode 100644
index 000000000..7751ded98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpextrw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pextrw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c
new file mode 100644
index 000000000..d0aee2139
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phaddd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c
new file mode 100644
index 000000000..b58978aeb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phaddsw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c
new file mode 100644
index 000000000..cdf17f694
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphaddw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phaddw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c
new file mode 100644
index 000000000..288651c95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-phminposuw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c
new file mode 100644
index 000000000..3ae122c7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -mavx -mno-avx2" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-phminposuw-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c
new file mode 100644
index 000000000..4a37ba542
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphminposuw-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx -mno-avx2" } */
+
+#include "avx-vphminposuw-2.c"
+
+/* { dg-final { scan-assembler "vphminposuw\[^\n\r\]*xmm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c
new file mode 100644
index 000000000..b1be419cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phsubd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c
new file mode 100644
index 000000000..477523e30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phsubsw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c
new file mode 100644
index 000000000..55893a672
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vphsubw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-phsubw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c
new file mode 100644
index 000000000..b3b63581d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pinsrb.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c
new file mode 100644
index 000000000..69c9bef3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pinsrd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c
new file mode 100644
index 000000000..595fc1baa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pinsrq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c
new file mode 100644
index 000000000..5e1a7cb91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpinsrw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pinsrw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c
new file mode 100644
index 000000000..adc476300
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaddubsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pmaddubsw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c
new file mode 100644
index 000000000..74b5a331f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmaxsb.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c
new file mode 100644
index 000000000..832e25e7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmaxsd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c
new file mode 100644
index 000000000..55e362e69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmaxsw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c
new file mode 100644
index 000000000..0f647cbe1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxub-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmaxub-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c
new file mode 100644
index 000000000..afd29dbb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxud-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmaxud.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c
new file mode 100644
index 000000000..74b4177ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmaxuw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmaxuw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c
new file mode 100644
index 000000000..e44ca611f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pminsb.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c
new file mode 100644
index 000000000..54e18ed53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pminsd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c
new file mode 100644
index 000000000..ce65712f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pminsw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c
new file mode 100644
index 000000000..d7b77bc62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminub-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pminub-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c
new file mode 100644
index 000000000..bbc069e78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminud-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pminud.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c
new file mode 100644
index 000000000..9b253555e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpminuw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pminuw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c
new file mode 100644
index 000000000..0b3e8aaee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovmskb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmovmskb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c
new file mode 100644
index 000000000..b3a57b044
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxbd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c
new file mode 100644
index 000000000..a9aba16bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxbq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c
new file mode 100644
index 000000000..a3f2efe36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxbw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c
new file mode 100644
index 000000000..6f2940533
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxdq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c
new file mode 100644
index 000000000..8e186e382
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxwd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxwd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c
new file mode 100644
index 000000000..90c2d1d5e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovsxwq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovsxwq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c
new file mode 100644
index 000000000..3f4556ce8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxbd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c
new file mode 100644
index 000000000..719c7271e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxbq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c
new file mode 100644
index 000000000..ad5fe4e7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxbw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c
new file mode 100644
index 000000000..7490902b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxdq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c
new file mode 100644
index 000000000..5447155d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxwd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxwd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c
new file mode 100644
index 000000000..b8239f221
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmovzxwq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmovzxwq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c
new file mode 100644
index 000000000..527d3cbdb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmuldq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmuldq.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c
new file mode 100644
index 000000000..121252ec6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhrsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pmulhrsw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c
new file mode 100644
index 000000000..f3127a9db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhuw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmulhuw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c
new file mode 100644
index 000000000..c36b489c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulhw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmulhw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c
new file mode 100644
index 000000000..63df55d79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmulld-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-pmulld.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c
new file mode 100644
index 000000000..649dcad62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmullw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmullw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c
new file mode 100644
index 000000000..e7c1cebdc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpmuludq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pmuludq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpor-1.c
new file mode 100644
index 000000000..cda694f00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpor-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-por-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c
new file mode 100644
index 000000000..6f76c9632
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsadbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psadbw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c
new file mode 100644
index 000000000..5ab106c3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-pshufb.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c
new file mode 100644
index 000000000..543bcdfcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pshufd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c
new file mode 100644
index 000000000..23b79c653
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshufhw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pshufhw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c
new file mode 100644
index 000000000..268b5d244
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpshuflw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pshuflw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c
new file mode 100644
index 000000000..9677c6834
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-psignb.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c
new file mode 100644
index 000000000..84b16b73a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-psignd.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c
new file mode 100644
index 000000000..daf47e601
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsignw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx -fno-strict-aliasing" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "ssse3-psignw.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c
new file mode 100644
index 000000000..778662dbd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslld-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pslld-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c
new file mode 100644
index 000000000..12754ed78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslld-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pslld-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c
new file mode 100644
index 000000000..aea5b7865
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpslldq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pslldq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c
new file mode 100644
index 000000000..37c152649
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psllq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c
new file mode 100644
index 000000000..0cc298df9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllq-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psllq-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c
new file mode 100644
index 000000000..ebb610c31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psllw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c
new file mode 100644
index 000000000..62a989dc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsllw-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psllw-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c
new file mode 100644
index 000000000..2293c42b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrad-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrad-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c
new file mode 100644
index 000000000..53f4f09c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrad-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrad-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c
new file mode 100644
index 000000000..525163fcc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsraw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psraw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c
new file mode 100644
index 000000000..90c8df0f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsraw-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psraw-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c
new file mode 100644
index 000000000..a143a65c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrld-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrld-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c
new file mode 100644
index 000000000..e9e1e3f2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrld-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrld-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c
new file mode 100644
index 000000000..a8cec081e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrldq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrldq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c
new file mode 100644
index 000000000..d7a57bff7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrlq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c
new file mode 100644
index 000000000..efa870818
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlq-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrlq-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c
new file mode 100644
index 000000000..e132c2da1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrlw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c
new file mode 100644
index 000000000..ec4a85dce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsrlw-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psrlw-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c
new file mode 100644
index 000000000..e66624f22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c
new file mode 100644
index 000000000..1e9214dbd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c
new file mode 100644
index 000000000..b7c22be7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c
new file mode 100644
index 000000000..fa71d6112
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubsb-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubsb-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c
new file mode 100644
index 000000000..b3fbad0ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubsw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubsw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c
new file mode 100644
index 000000000..a83140e19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpsubw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-psubw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-1.c
new file mode 100644
index 000000000..c70752d36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ptest-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-2.c
new file mode 100644
index 000000000..cb6b5520b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ptest-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c
new file mode 100644
index 000000000..ebc2673a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int s1i[8] = {0, 5463, 86456, 0, 1234, 0, 62445, 34352};
+  int s2i[8] = {0, 1223, 0,     0, 0,    1, 0,     0};
+  int d;
+  int e;
+  int i;
+  union256i_d s1, s2;
+
+  s1.x = _mm256_loadu_si256 ((__m256i*)s1i);
+  s2.x = _mm256_loadu_si256 ((__m256i*)s2i);
+  d = _mm256_testz_si256 (s1.x, s2.x);
+
+  e = 1;
+  for (i = 0; i < 8; i++)
+    if ((s1i[i] & s2i[i]) != 0)
+      e = 0;
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c
new file mode 100644
index 000000000..f85344a9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int s1i[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int s2i[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int d;
+  int e;
+  int i;
+  union256i_d s1, s2;
+
+  s1.x = _mm256_loadu_si256 ((__m256i*)s1i);
+  s2.x = _mm256_loadu_si256 ((__m256i*)s2i);
+  d = _mm256_testc_si256 (s1.x, s2.x);
+
+  e = 1;
+  for (i = 0; i < 8; i++)
+    if ((~s1i[i] & s2i[i]) != 0)
+      e = 0;
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c
new file mode 100644
index 000000000..cccbbef4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-256-3.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int s1i[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int s2i[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int d;
+  int c = 1, z = 1, e = 0xf;
+  int i;
+  union256i_d s1, s2;
+
+  s1.x = _mm256_loadu_si256 ((__m256i*)s1i);
+  s2.x = _mm256_loadu_si256 ((__m256i*)s2i);
+  d = _mm256_testnzc_si256 (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    {
+      if ((s1.a[i] & s2.a[i]))
+        z = 0;
+      if ((~s1.a[i] & s2.a[i]))
+        c = 0;
+    }
+
+   e = (z == 0 && c == 0) ? 1 : 0;
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-3.c
new file mode 100644
index 000000000..1b875a75f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vptest-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-ptest-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c
new file mode 100644
index 000000000..3c76aa3f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckhbw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c
new file mode 100644
index 000000000..a853d7014
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckhdq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c
new file mode 100644
index 000000000..8b86c7649
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhqdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckhqdq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c
new file mode 100644
index 000000000..0e4e051d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckhwd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckhwd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c
new file mode 100644
index 000000000..ad856cf6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklbw-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpcklbw-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c
new file mode 100644
index 000000000..2acd87929
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpckldq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpckldq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c
new file mode 100644
index 000000000..bd378a34f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklqdq-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpcklqdq-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c
new file mode 100644
index 000000000..07f2be177
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpunpcklwd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-punpcklwd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c
new file mode 100644
index 000000000..dfc46537b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vpxor-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-pxor-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c
new file mode 100644
index 000000000..45673de43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrcpps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-rcpps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c
new file mode 100644
index 000000000..16b3051b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrcpps-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 u, s1;
+    float e[8] = {0.0};
+
+    s1.x = _mm256_set_ps (1.0, 2.0, 13.0, 14.0, 56.89, 73.3, 4.78, 45.64);
+    u.x = _mm256_rcp_ps (s1.x);
+
+    for (i = 0; i < 8; i++) {
+      __m128 tmp = _mm_load_ss (&s1.a[i]);
+      tmp = _mm_rcp_ss (tmp);
+      _mm_store_ss (&e[i], tmp);
+    }
+
+    if (check_union256 (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c
new file mode 100644
index 000000000..c8b0ec1ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-roundpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c
new file mode 100644
index 000000000..e29ac5562
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-roundpd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c
new file mode 100644
index 000000000..71da7523a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#define iRoundMode 0x7
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double source [4] = {2134.3343,1234.635654,453.345635,54646.464356};
+  double e[4] = {0.0};
+  int i;
+
+  s1.x = _mm256_loadu_pd (source);
+  u.x = _mm256_round_pd (s1.x, iRoundMode);
+
+  for (i = 0; i < 4; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s1.a[i]);
+      tmp = _mm_round_sd (tmp, tmp, iRoundMode);
+      _mm_store_sd (&e[i], tmp);
+    }
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c
new file mode 100644
index 000000000..a61d7730c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double source [4] = {2134.3343,1234.635654,453.345635,54646.464356};
+  double e[4] = {0.0};
+  int i;
+
+  s1.x = _mm256_loadu_pd (source);
+  u.x = _mm256_floor_pd (s1.x);
+
+  for (i = 0; i < 4; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s1.a[i]);
+      tmp = _mm_floor_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c
new file mode 100644
index 000000000..f4f3e77dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-256-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double source [4] = {2134.3343,1234.635654,453.345635,54646.464356};
+  double e[4] = {0.0};
+  int i;
+
+  s1.x = _mm256_loadu_pd (source);
+  u.x = _mm256_ceil_pd (s1.x);
+
+  for (i = 0; i < 4; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s1.a[i]);
+      tmp = _mm_ceil_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c
new file mode 100644
index 000000000..6d9326f6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundpd-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse4_1-roundpd-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c
new file mode 100644
index 000000000..d33248e24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vroundps-256-1.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1;
+  float source [8] = {2134.3343,1234.635654,453.345635,54646.464356,895833.346347,56343,234234.34563,2345434.67832};
+  float e [8] = {2134.0,1234.0,453.0,54646.0,895833.0,56343,234234.0,2345434.0};
+
+  s1.x = _mm256_loadu_ps (source);
+  u.x = _mm256_round_ps (s1.x, 1);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c
new file mode 100644
index 000000000..2db1650dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-rsqrtps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c
new file mode 100644
index 000000000..19a933c5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vrsqrtps-256-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 u, s1;
+    float e[8] = {0.0};
+
+    s1.x = _mm256_set_ps (1.0, 2.0, 13.0, 14.0, 56.89, 73.3, 4.78, 45.64);
+    u.x = _mm256_rsqrt_ps (s1.x);
+
+    for (i = 0; i < 8; i++) {
+      __m128 tmp = _mm_load_ss (&s1.a[i]);
+      tmp = _mm_rsqrt_ss (tmp);
+      _mm_store_ss (&e[i], tmp);
+    }
+
+    if (check_union256 (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c
new file mode 100644
index 000000000..a6f00ea8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-shufpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c
new file mode 100644
index 000000000..828f6804f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufpd-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 10
+#endif
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_shuffle_pd (s1.x, s2.x, MASK);
+
+  e[0] = (MASK & (1 << 0)) ? s1.a[1] : s1.a[0];
+  e[1] = (MASK & (1 << 1)) ? s2.a[1] : s2.a[0];
+  e[2] = (MASK & (1 << 2)) ? s1.a[3] : s1.a[2];
+  e[3] = (MASK & (1 << 3)) ? s2.a[3] : s2.a[2];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c
new file mode 100644
index 000000000..97d85706d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-shufps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c
new file mode 100644
index 000000000..f939357d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vshufps-256-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+#ifndef MASK
+#define MASK 203
+#endif
+
+float select4(const float *src, unsigned int control)
+{
+    switch(control) {
+    case 0:
+        return src[0];
+    case 1:
+        return src[1];
+    case 2:
+        return src[2];
+    case 3:
+        return src[3];
+    }
+    return -1;
+}
+
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8);
+  s2.x = _mm256_set_ps (2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8);
+  u.x = _mm256_shuffle_ps (s1.x, s2.x, MASK);
+
+
+  e[0] = select4(s1.a,   (MASK >> 0) & 0x3);
+  e[1] = select4(s1.a,   (MASK >> 2) & 0x3);
+  e[2] = select4(s2.a,   (MASK >> 4) & 0x3);
+  e[3] = select4(s2.a,   (MASK >> 6) & 0x3);
+  e[4] = select4(s1.a+4, (MASK >> 0) & 0x3);
+  e[5] = select4(s1.a+4, (MASK >> 2) & 0x3);
+  e[6] = select4(s2.a+4, (MASK >> 4) & 0x3);
+  e[7] = select4(s2.a+4, (MASK >> 6) & 0x3);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c
new file mode 100644
index 000000000..dc098c910
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-sqrtpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c
new file mode 100644
index 000000000..d611bbd12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtpd-256-1.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1;
+  double e [4] = {0x1.d3881b2c32ed7p+7, 0x1.54abaed51711cp+4, 0x1.19195c08a8d23p+5, 0x1.719741d6c0b0bp+5};
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  u.x = _mm256_sqrt_pd (s1.x);
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c
new file mode 100644
index 000000000..deb88947f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-sqrtps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c
new file mode 100644
index 000000000..d5cd77f5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsqrtps-256-1.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1;
+  float e[8] = {0x1.7edeccp+10, 0x1.e3fa46p+8, 0x1.dabbcep+7, 0x1.d93e0cp+9,\
+                0x1.d3881cp+7, 0x1.54abbp+4, 0x1.19195cp+5, 0x1.719742p+5};
+
+  s1.x = _mm256_set_ps (2134.3343,1234.635654,453.345635,54646.464356, \
+                        895833.346347,56343,234234.34563,2345434.67832);
+  u.x = _mm256_sqrt_ps (s1.x);
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c
new file mode 100644
index 000000000..2af33fc6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-subpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c
new file mode 100644
index 000000000..ce4ddcaa1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubpd-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_sub_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c
new file mode 100644
index 000000000..59aa92847
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-subps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c
new file mode 100644
index 000000000..de4337cb6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubps-256-1.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  int i;
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_sub_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c
new file mode 100644
index 000000000..58cf4cb32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubsd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-subsd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c
new file mode 100644
index 000000000..719aa6f15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vsubss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-subss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c
new file mode 100644
index 000000000..6b52d786b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128d source1, source2;
+
+    double s1[2] = {30, -5463};
+    double s2[2] = {20, 1223};
+    int    d[1];
+    int    e[1];
+  
+    source1.x = _mm_loadu_pd(s1);
+    source2.x = _mm_loadu_pd(s2);
+
+    d[0] = _mm_testz_pd(source1.x, source2.x);
+    
+    e[0] = 1;
+    for (i = 0; i < 2; i++)
+      {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (u1.bits.sign && u2.bits.sign) {
+            e[0] = 0;
+        }
+    }
+
+    if (checkVi(d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c
new file mode 100644
index 000000000..57dfeeb7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128d source1, source2;
+
+    double s1[2] = {0, -5463};
+    double s2[2] = {0, -1223};
+    int    d[1];
+    int    e[1];
+  
+    source1.x = _mm_loadu_pd(s1);
+    source2.x = _mm_loadu_pd(s2);
+
+    d[0] = _mm_testc_pd(source1.x, source2.x);
+    
+    e[0] = 1;
+    for (i = 0; i < 2; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (!u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi(d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c
new file mode 100644
index 000000000..050f140f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256d source1, source2;
+   
+    double s1[4] = {0, -5463, 86456, 0};
+    double s2[4] = {0, -1223, 0,     1};
+    int    d[1];
+    int    e[1];
+
+    source1.x = _mm256_loadu_pd(s1);
+    source2.x = _mm256_loadu_pd(s2);
+    d[0] = _mm256_testz_pd(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (u1.bits.sign && u2.bits.sign) {
+            e[0] = 0;
+        }
+    }
+    
+   if (checkVi(d, e, 1))
+     abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c
new file mode 100644
index 000000000..0954f1dd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256d source1, source2;
+   
+    double s1[4] = {0, -5463, 86456, 0};
+    double s2[4] = {0, -1223, 0,     1};
+    int    d[1];
+    int    e[1];
+
+    source1.x = _mm256_loadu_pd(s1);
+    source2.x = _mm256_loadu_pd(s2);
+    d[0] = _mm256_testc_pd(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (!u1.bits.sign && u2.bits.sign) {
+            e[0] = 0;
+        }
+    }
+    
+  if (checkVi(d, e, 1))
+    abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c
new file mode 100644
index 000000000..8a6e32e41
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-256-3.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256d source1, source2;
+   
+    double s1[4] = {0, -5463, 86456, 0};
+    double s2[4] = {0, -1223, 0,     1};
+    int    d[1];
+    int    e[1];
+    int c=1;
+    int z=1;
+
+    source1.x = _mm256_loadu_pd(s1);
+    source2.x = _mm256_loadu_pd(s2);
+    d[0] = _mm256_testnzc_pd(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (u1.bits.sign && u2.bits.sign)
+            z = 0;
+        
+        if (!u1.bits.sign && u2.bits.sign)
+            c = 0;
+    }
+    e[0] = (c==0 && z==0) ? 1:0;
+    
+   if (checkVi(d, e, 1))
+     abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c
new file mode 100644
index 000000000..74c5dc868
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestpd-3.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_DOUBLE" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 164 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128d source1, source2;
+
+    double s1[2] = {0, -5463};
+    double s2[2] = {0, -1223};
+    int    d[1];
+    int    e[1];
+    int c = 1;
+    int z = 1;
+  
+    source1.x = _mm_loadu_pd(s1);
+    source2.x = _mm_loadu_pd(s2);
+
+    d[0] = _mm_testnzc_pd(source1.x, source2.x);
+    
+    e[0] = 1;
+    for (i = 0; i < 2; i++) {
+	union ieee754_double u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+        if (u1.bits.sign && u2.bits.sign)
+            z = 0;
+        if (!u1.bits.sign && u2.bits.sign)
+            c = 0;
+        
+    }
+
+    e[0] = (c==0 && z==0) ? 1:0;
+
+    if (checkVi(d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c
new file mode 100644
index 000000000..fb0c802fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128 source1, source2;
+    float s1[4] = {0, -5463, 86456, 0};
+    float s2[4] = {0, -1223, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm_loadu_ps(s1);
+    source2.x = _mm_loadu_ps(s2);
+    d[0] = _mm_testz_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c
new file mode 100644
index 000000000..7482dae4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128 source1, source2;
+    float s1[4] = {0, -5463, 86456, 0};
+    float s2[4] = {0, -1223, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm_loadu_ps(s1);
+    source2.x = _mm_loadu_ps(s2);
+    d[0] = _mm_testc_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (!u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c
new file mode 100644
index 000000000..6362c4183
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 source1, source2;
+
+    float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352};
+    float s2[8] = {0, -1223, 0,     0, 0,    1, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm256_loadu_ps(s1);
+    source2.x = _mm256_loadu_ps(s2);
+    d[0] = _mm256_testz_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 8; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c
new file mode 100644
index 000000000..de23ab2e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 source1, source2;
+
+    float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352};
+    float s2[8] = {0, -1223, 0,     0, 0,    1, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm256_loadu_ps(s1);
+    source2.x = _mm256_loadu_ps(s2);
+    d[0] = _mm256_testc_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 8; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (!u1.bits.sign && u2.bits.sign)
+            e[0] = 0;
+    }
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c
new file mode 100644
index 000000000..717e5bb28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-256-3.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union256 source1, source2;
+    int c = 1;
+    int z = 1;
+
+    float s1[8] = {0, -5463, 86456, 0, 1234, 0, 62445, 34352};
+    float s2[8] = {0, -1223, 0,     0, 0,    1, 0,     0};
+    int   d[1];
+    int   e[1];
+
+    source1.x = _mm256_loadu_ps(s1);
+    source2.x = _mm256_loadu_ps(s2);
+    d[0] = _mm256_testnzc_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 8; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (!u1.bits.sign && u2.bits.sign)
+            c = 0;
+	if (u1.bits.sign && u2.bits.sign)
+            z = 0;
+        }
+    e[0] = (c==0 && z==0)?1:0;
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c
new file mode 100644
index 000000000..61f58a6b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vtestps-3.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -DNEED_IEEE754_FLOAT" } */
+/* { dg-warning "attribute ignored" "" { target default_packed } 150 } */
+/* { dg-message " from " "include chain" { target default_packed } 0 } */
+
+#include "avx-check.h"
+
+static void
+avx_test ()
+{
+    int i;
+    union128 source1, source2;
+    float s1[4] = {0, -5463, 86456, 0};
+    float s2[4] = {0, -1223, 0,     0};
+    int   d[1];
+    int   e[1];
+    int c=1;
+    int z=1;
+
+    source1.x = _mm_loadu_ps(s1);
+    source2.x = _mm_loadu_ps(s2);
+    d[0] = _mm_testnzc_ps(source1.x, source2.x);
+
+    e[0] = 1;
+    for (i = 0; i < 4; i++) {
+	union ieee754_float u1, u2;
+	u1.d = s1[i];
+	u2.d = s2[i];
+	if (!u1.bits.sign && u2.bits.sign)
+            c = 0;
+	if (u1.bits.sign && u2.bits.sign)
+            z = 0;
+        
+    }
+    e[0] = (c == 0 && z == 0) ? 1:0;
+
+    if (checkVi (d, e, 1))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c
new file mode 100644
index 000000000..d4efd212d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c
new file mode 100644
index 000000000..d55f31007
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c
new file mode 100644
index 000000000..e2ba869ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c
new file mode 100644
index 000000000..961759909
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-4.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c
new file mode 100644
index 000000000..9034519af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-5.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-5.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c
new file mode 100644
index 000000000..cc9d0e925
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomisd-6.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-ucomisd-6.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c
new file mode 100644
index 000000000..c0ba7a3a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c
new file mode 100644
index 000000000..ea4b80e10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c
new file mode 100644
index 000000000..bd82bb92a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c
new file mode 100644
index 000000000..a58395a12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-4.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-4.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c
new file mode 100644
index 000000000..198933cd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-5.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-5.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c
new file mode 100644
index 000000000..db48b7a30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vucomiss-6.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-ucomiss-6.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c
new file mode 100644
index 000000000..4b7191ce0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-unpckhpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c
new file mode 100644
index 000000000..5da332d45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhpd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_unpackhi_pd (s1.x, s2.x);
+
+  e[0] = s1.a[1];
+  e[1] = s2.a[1];
+  e[2] = s1.a[3];
+  e[3] = s2.a[3];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c
new file mode 100644
index 000000000..e5a0f3e1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-unpckhps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c
new file mode 100644
index 000000000..be6fbb6f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpckhps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_unpackhi_ps (s1.x, s2.x);
+
+  e[0] = s1.a[2];
+  e[1] = s2.a[2];
+  e[2] = s1.a[3];
+  e[3] = s2.a[3];
+  e[4] = s1.a[6];
+  e[5] = s2.a[6];
+  e[6] = s1.a[7];
+  e[7] = s2.a[7];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c
new file mode 100644
index 000000000..9e0cb05ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-unpcklpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c
new file mode 100644
index 000000000..0f7e390cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklpd-256-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256d u, s1, s2;
+  double e [4];
+
+  s1.x = _mm256_set_pd (2134.3343,1234.635654,453.345635,54646.464356);
+  s2.x = _mm256_set_pd (41124.234,2344.2354,8653.65635,856.43576);
+  u.x = _mm256_unpacklo_pd (s1.x, s2.x);
+
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+  e[2] = s1.a[2];
+  e[3] = s2.a[2];
+
+  if (check_union256d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c
new file mode 100644
index 000000000..c2380a47e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mfpmath=sse -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-unpcklps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c
new file mode 100644
index 000000000..bf0e31892
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vunpcklps-256-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union256 u, s1, s2;
+  float e [8];
+
+  s1.x = _mm256_set_ps (24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4);
+  s2.x = _mm256_set_ps (1.17, 2.16, 3.15, 4.14, 5.13, 6.12, 7.11, 8.9);
+  u.x = _mm256_unpacklo_ps (s1.x, s2.x);
+
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+  e[2] = s1.a[1];
+  e[3] = s2.a[1];
+  e[4] = s1.a[4];
+  e[5] = s2.a[4];
+  e[6] = s1.a[5];
+  e[7] = s2.a[5];
+
+  if (check_union256 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c
new file mode 100644
index 000000000..435bf042a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorpd-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse2-xorpd-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c
new file mode 100644
index 000000000..4896ee01e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorpd-256-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union
+  {
+    double d[4];
+    long long l[4];
+  }source1, source2, e;
+
+  int i;
+  union256d u, s1, s2;
+
+  s1.x = _mm256_set_pd (34545.123, 95567.456, 23443.09876, 5675.543);
+  s2.x = _mm256_set_pd (674, 57897.332187, 93459, 45624.112);
+  _mm256_storeu_pd (source1.d, s1.x);
+  _mm256_storeu_pd (source2.d, s2.x);
+
+  u.x = _mm256_xor_pd (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e.l[i] = source1.l[i] ^ source2.l[i];
+
+  if (check_union256d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c
new file mode 100644
index 000000000..e203a7f57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorps-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include "sse-xorps-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c
new file mode 100644
index 000000000..007704846
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vxorps-256-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+void static
+avx_test (void)
+{
+  union {
+    float f[8];
+    int   i[8];
+  }source1, source2, e;
+  
+  int i;
+  union256 u, s1, s2;
+
+  s1.x = _mm256_set_ps (34545, 95567, 23443, 5675, 2323, 67, 2345, 45667);
+  s2.x = _mm256_set_ps (674, 57897, 93459, 45624, 54674, 1237, 67436, 79608);
+  
+  _mm256_storeu_ps (source1.f, s1.x);
+  _mm256_storeu_ps (source2.f, s2.x);
+
+  u.x = _mm256_xor_ps (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e.i[i] = source1.i[i] ^ source2.i[i];
+
+  if (check_union256 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c
new file mode 100644
index 000000000..996357a7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroall-1.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static void
+avx_test (void)
+{
+  __m256i src;
+#ifdef __x86_64__
+  char reg_save[16][32];
+  char d[16][32];
+#else
+  char reg_save[8][32];
+  char d[8][32];
+#endif  
+
+  int s[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+
+  __builtin_memset (d, 0, sizeof d);
+  __builtin_memset (reg_save, -1, sizeof reg_save);
+
+  src = _mm256_loadu_si256 ((__m256i*) s);
+
+  _mm256_zeroall (); 
+
+  __asm__ __volatile__ ("vmovdqu %%ymm0,%0":"=m"(reg_save[0]));
+  __asm__ __volatile__ ("vmovdqu %%ymm1,%0":"=m"(reg_save[1]));
+  __asm__ __volatile__ ("vmovdqu %%ymm2,%0":"=m"(reg_save[2]));
+  __asm__ __volatile__ ("vmovdqu %%ymm3,%0":"=m"(reg_save[3]));
+  __asm__ __volatile__ ("vmovdqu %%ymm4,%0":"=m"(reg_save[4]));
+  __asm__ __volatile__ ("vmovdqu %%ymm5,%0":"=m"(reg_save[5]));
+  __asm__ __volatile__ ("vmovdqu %%ymm6,%0":"=m"(reg_save[6]));
+  __asm__ __volatile__ ("vmovdqu %%ymm7,%0":"=m"(reg_save[7]));
+#ifdef __x86_64__
+  __asm__ __volatile__ ("vmovdqu %%ymm8,%0":"=m"(reg_save[8]));
+  __asm__ __volatile__ ("vmovdqu %%ymm9,%0":"=m"(reg_save[9]));
+  __asm__ __volatile__ ("vmovdqu %%ymm10,%0":"=m"(reg_save[10]));
+  __asm__ __volatile__ ("vmovdqu %%ymm11,%0":"=m"(reg_save[11]));
+  __asm__ __volatile__ ("vmovdqu %%ymm12,%0":"=m"(reg_save[12]));
+  __asm__ __volatile__ ("vmovdqu %%ymm13,%0":"=m"(reg_save[13]));
+  __asm__ __volatile__ ("vmovdqu %%ymm14,%0":"=m"(reg_save[14]));
+  __asm__ __volatile__ ("vmovdqu %%ymm15,%0":"=m"(reg_save[15]));
+#endif
+
+  if (__builtin_memcmp (reg_save, d, sizeof d))
+    abort ();
+
+  _mm256_storeu_si256 ((__m256i*) d, src);
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c
new file mode 100644
index 000000000..f49a0da42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroall-2.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx" } */
+
+#include "avx-check.h"
+
+static int s[4] = {234566, 8723467, 6576856, 19832468};
+static int d[4] = {1,1,1,1};
+
+static void
+avx_test (void)
+{
+  __m128i src;
+
+  src = _mm_loadu_si128 ((__m128i*) s);
+  _mm256_zeroall ();
+  _mm_storeu_si128 ((__m128i*) d, src);
+
+  if (__builtin_memcmp (d, s, sizeof (d)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c
new file mode 100644
index 000000000..73ce795f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-1.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mtune=generic" } */
+
+#include "avx-check.h"
+
+#ifdef __x86_64__
+#define LEN 16
+#else
+#define LEN 8
+#endif
+
+static void
+avx_test (void)
+{
+  __m256i src;
+
+  char reg_save[LEN][32];
+  int i, j;
+
+  int s[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+  int d[8] = {11, 22, 33, 44, 55, 66, 77, 88};
+
+  __builtin_memset (reg_save, -1, sizeof reg_save);
+
+  src = _mm256_loadu_si256 ((__m256i*) s);
+
+  _mm256_zeroupper (); 
+
+  __asm__ __volatile__ ("vmovdqu %%ymm0,%0":"=m"(reg_save[0]));
+  __asm__ __volatile__ ("vmovdqu %%ymm1,%0":"=m"(reg_save[1]));
+  __asm__ __volatile__ ("vmovdqu %%ymm2,%0":"=m"(reg_save[2]));
+  __asm__ __volatile__ ("vmovdqu %%ymm3,%0":"=m"(reg_save[3]));
+  __asm__ __volatile__ ("vmovdqu %%ymm4,%0":"=m"(reg_save[4]));
+  __asm__ __volatile__ ("vmovdqu %%ymm5,%0":"=m"(reg_save[5]));
+  __asm__ __volatile__ ("vmovdqu %%ymm6,%0":"=m"(reg_save[6]));
+  __asm__ __volatile__ ("vmovdqu %%ymm7,%0":"=m"(reg_save[7]));
+#ifdef __x86_64__
+  __asm__ __volatile__ ("vmovdqu %%ymm8,%0":"=m"(reg_save[8]));
+  __asm__ __volatile__ ("vmovdqu %%ymm9,%0":"=m"(reg_save[9]));
+  __asm__ __volatile__ ("vmovdqu %%ymm10,%0":"=m"(reg_save[10]));
+  __asm__ __volatile__ ("vmovdqu %%ymm11,%0":"=m"(reg_save[11]));
+  __asm__ __volatile__ ("vmovdqu %%ymm12,%0":"=m"(reg_save[12]));
+  __asm__ __volatile__ ("vmovdqu %%ymm13,%0":"=m"(reg_save[13]));
+  __asm__ __volatile__ ("vmovdqu %%ymm14,%0":"=m"(reg_save[14]));
+  __asm__ __volatile__ ("vmovdqu %%ymm15,%0":"=m"(reg_save[15]));
+#endif
+
+  for (i = 0; i < LEN; i++)
+    for (j = 16; j < 32; j++)
+      if (reg_save[i][j])
+        abort ();
+
+  _mm256_storeu_si256 ((__m256i*) d, src);
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-10.c
new file mode 100644
index 000000000..5007753a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-10.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern float x, y;
+
+void
+foo ()
+{
+  x = y;
+  _mm256_zeroupper ();
+  _mm256_zeroupper ();
+  _mm256_zeroupper ();
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-11.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-11.c
new file mode 100644
index 000000000..507f94543
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-11.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern float x, y;
+
+void
+foo ()
+{
+  x = y;
+  _mm256_zeroall ();
+  _mm256_zeroupper ();
+  _mm256_zeroupper ();
+  _mm256_zeroupper ();
+}
+
+/* { dg-final { scan-assembler-times "\\*avx_vzeroall" 1 } } */
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c
new file mode 100644
index 000000000..e694d4048
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  _mm256_zeroall ();
+  _mm256_zeroupper ();
+  x = y;
+  _mm256_zeroupper ();
+  _mm256_zeroupper ();
+  _mm256_zeroupper ();
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */
+/* { dg-final { scan-assembler-times "\\*avx_vzeroall" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-13.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-13.c
new file mode 100644
index 000000000..cff5f8878
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-13.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mno-vzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  x = y;
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-14.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-14.c
new file mode 100644
index 000000000..a31b4a2a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-14.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mtune=generic -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  x = y;
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-15.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-15.c
new file mode 100644
index 000000000..803936eef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-15.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mtune=generic -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+extern void (*bar) (void);
+
+void
+foo ()
+{
+  x = y;
+  bar ();
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c
new file mode 100644
index 000000000..66c844668
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-16.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mavx -mabi=ms -dp" } */
+
+typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));
+
+extern __m256 x;
+
+extern __m256 __attribute__ ((sysv_abi)) bar (__m256);
+
+void
+foo (void)
+{
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
+/* { dg-final { scan-assembler-times "\\*call_value_rex64_ms_sysv" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c
new file mode 100644
index 000000000..acb432945
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-17.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mavx -mabi=ms -dp" } */
+
+typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));
+
+extern __m256 x;
+
+extern __m256 __attribute__ ((sysv_abi)) (*bar) (__m256);
+
+void
+foo (void)
+{
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
+/* { dg-final { scan-assembler-times "\\*call_value_rex64_ms_sysv" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c
new file mode 100644
index 000000000..6f67f3ee3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-18.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O0 -mavx -mabi=ms -dp" } */
+
+typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));
+
+extern __m256 x;
+
+extern void __attribute__ ((sysv_abi))  bar (__m256);
+
+void
+foo (void)
+{
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
+/* { dg-final { scan-assembler-times "\\*call_rex64_ms_sysv" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c
new file mode 100644
index 000000000..ae2f8611e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx -mtune=generic -dp" } */
+
+void feat_s3_cep_dcep (int cepsize_used, float **mfc, float **feat)
+{
+  float *f;
+  float *w, *_w;
+  int i;
+  __builtin_memcpy (feat[0], mfc[0], cepsize_used * sizeof(float));
+  f = feat[0] + cepsize_used;
+  w = mfc[2];
+  _w = mfc[-2];
+  for (i = 0; i < cepsize_used; i++)
+    f[i] = w[i] - _w[i];
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c
new file mode 100644
index 000000000..66df90f14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-2.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mtune=generic" } */
+
+#include "avx-check.h"
+
+static int s[4] = {234566, 8723467, 6576856, 19832468};
+static int d[4] = {1,1,1,1};
+
+static void
+avx_test (void)
+{
+  __m128i src;
+
+  src = _mm_loadu_si128 ((__m128i*) s);
+  _mm256_zeroupper ();
+  _mm_storeu_si128 ((__m128i*) d, src);
+
+  if (__builtin_memcmp (d, s, sizeof (d)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-20.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-20.c
new file mode 100644
index 000000000..33010839e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-20.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx -mtune=generic -dp" } */
+
+extern void free (void *);
+void
+bar (void *ncstrp)
+{
+  if(ncstrp==((void *)0))
+    return;
+  free(ncstrp);
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-21.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-21.c
new file mode 100644
index 000000000..6dea0552f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-21.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mtune=generic -dp" } */
+
+extern void exit (int) __attribute__ ((__noreturn__));
+
+int
+foo (int i)
+{
+  if (i == 0)
+    exit (1);
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-22.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-22.c
new file mode 100644
index 000000000..b4e4a5806
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-22.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mtune=generic -dp" } */
+
+extern void exit (int) __attribute__ ((__noreturn__));
+extern void bar (void);
+
+int
+foo (int i)
+{
+  if (i == 0)
+    {
+      bar ();
+      exit (1);
+    }
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-23.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-23.c
new file mode 100644
index 000000000..66df800e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-23.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mtune=generic -dp" } */
+
+extern void fatal (void) __attribute__ ((__noreturn__));
+extern void exit (int) __attribute__ ((__noreturn__));
+
+void
+fatal (void)
+{
+  exit (1);
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-24.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-24.c
new file mode 100644
index 000000000..4fdd37446
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-24.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mtune=generic -dp" } */
+
+typedef struct bitmap_element_def {
+  struct bitmap_element_def *next;
+  unsigned int indx;
+} bitmap_element;
+typedef struct bitmap_head_def {
+  bitmap_element *first;
+  bitmap_element *current;
+  unsigned int indx;
+} bitmap_head;
+typedef struct bitmap_head_def *bitmap;
+typedef const struct bitmap_head_def *const_bitmap;
+extern void bar (void) __attribute__ ((__noreturn__));
+unsigned char
+bitmap_and_compl_into (bitmap a, const_bitmap b)
+{
+  bitmap_element *a_elt = a->first;
+  const bitmap_element *b_elt = b->first;
+  if (a == b)
+    {
+      if ((!(a)->first))
+	return 0;
+      else
+	return 1;
+    }
+  while (a_elt && b_elt)
+    {
+      if (a_elt->indx < b_elt->indx)
+	a_elt = a_elt->next;
+    }
+  if (a->indx == a->current->indx)
+    bar ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-25.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-25.c
new file mode 100644
index 000000000..5ef49c7d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-25.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mtune=generic -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  x = y;
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-26.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-26.c
new file mode 100644
index 000000000..96e9190fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-26.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -mavx -mtune=generic -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+extern void (*bar) (void);
+
+void
+foo ()
+{
+  x = y;
+  bar ();
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-27.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-27.c
new file mode 100644
index 000000000..7fa5de437
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-27.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mtune=generic -dp" } */
+
+typedef struct objc_class *Class;
+typedef struct objc_object
+{
+  Class class_pointer;
+} *id;
+
+typedef const struct objc_selector *SEL;
+typedef void * retval_t;
+typedef void * arglist_t;
+
+extern retval_t __objc_forward (id object, SEL sel, arglist_t args);
+
+double
+__objc_double_forward (id rcv, SEL op, ...)
+{
+  void *args, *res;
+
+  args = __builtin_apply_args ();
+  res = __objc_forward (rcv, op, args);
+  __builtin_return (res);
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-3.c
new file mode 100644
index 000000000..8053d787f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-3.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -mavx -mvzeroupper" } */
+
+#include "avx-check.h"
+
+int s[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+int d[8] = {11, 22, 33, 44, 55, 66, 77, 88};
+
+void
+__attribute__((noinline))
+foo ()
+{
+  int i;
+  for (i = 0; i < ARRAY_SIZE (d); i++)
+    d[i] = s[i] + 0x1000;
+}
+
+static void
+__attribute__((noinline))
+bar (__m256i src)
+{
+  foo ();
+  _mm256_storeu_si256 ((__m256i*) d, src);
+  if (__builtin_memcmp (d, s, sizeof (d)))
+    abort ();
+}
+
+static void
+avx_test (void)
+{
+  __m256i src = _mm256_loadu_si256 ((__m256i*) s);
+  bar (src);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c
new file mode 100644
index 000000000..467661760
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
+
+typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));
+
+extern void bar2 (__m256);
+extern __m256 y;
+
+void
+foo ()
+{
+  bar2 (y);
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c
new file mode 100644
index 000000000..ba08978ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
+
+#include <immintrin.h>
+
+extern void bar2 (__m256);
+extern __m256 y;
+
+void
+foo ()
+{
+  bar2 (y);
+  _mm256_zeroupper ();
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-6.c
new file mode 100644
index 000000000..ada87bd31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-6.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  x = y;
+  _mm256_zeroall ();
+}
+
+/* { dg-final { scan-assembler-not "avx_vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c
new file mode 100644
index 000000000..ab6d68779
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-7.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  x = y;
+  _mm256_zeroupper ();
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-8.c
new file mode 100644
index 000000000..bb370c5b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-8.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  x = y;
+  _mm256_zeroall ();
+  _mm256_zeroupper ();
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c
new file mode 100644
index 000000000..974e1626a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx-vzeroupper-9.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx -mvzeroupper -dp" } */
+
+#include <immintrin.h>
+
+extern __m256 x, y;
+
+void
+foo ()
+{
+  _mm256_zeroupper ();
+  x = y;
+  _mm256_zeroupper ();
+  _mm256_zeroupper ();
+  _mm256_zeroupper ();
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-check.h
new file mode 100644
index 000000000..424335dbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-check.h
@@ -0,0 +1,47 @@
+#include <stdlib.h>
+#include "cpuid.h"
+#include "m256-check.h"
+#include "avx-os-support.h"
+
+static void avx2_test (void);
+
+static void __attribute__ ((noinline)) do_test (void)
+{
+  avx2_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AVX2 test only if host has AVX2 support.  */
+  if ((ecx & bit_OSXSAVE) == (bit_OSXSAVE))
+    {
+      if (__get_cpuid_max (0, NULL) < 7)
+	return 0;
+
+      __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+      if ((avx_os_support ()) && ((ebx & bit_AVX2) == bit_AVX2))
+	{
+	  do_test ();
+#ifdef DEBUG
+	  printf ("PASSED\n");
+#endif
+	  return 0;
+	}
+#ifdef DEBUG
+      printf ("SKIPPED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c
new file mode 100644
index 000000000..9626a0666
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-cvt-1.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mavx2" } */
+/* { dg-require-effective-target avx2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx2_test
+#endif
+
+#include "sse2-cvt-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c
new file mode 100644
index 000000000..4826e9b6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-cvt-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx2 -mtune=generic -fdump-tree-vect-details" } */
+
+#include "avx2-cvt-1.c"
+
+/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */
+/* { dg-final { scan-assembler "vcvttpd2dq(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */
+/* { dg-final { scan-assembler "vcvtdq2ps\[^\n\r\]*ymm" } } */
+/* { dg-final { scan-assembler "vcvtps2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */
+/* { dg-final { scan-assembler "vcvttps2dq\[^\n\r\]*ymm" } } */
+/* { dg-final { scan-assembler "vcvtdq2pd\[^\n\r\]*(%xmm\[^\n\r\]*%ymm|ymm\[^\n\r\]*xmm)" } } */
+/* { dg-final { scan-assembler "vcvtpd2ps(y\[^\n\r\]*%xmm|\[^\n\r\]*xmm\[^\n\r\]*YMMWORD PTR)" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-1.c
new file mode 100644
index 000000000..7ed567dc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-1.c
@@ -0,0 +1,215 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include "avx2-check.h"
+
+#define N 1024
+float vf1[N+16], vf2[N];
+double vd1[N+16], vd2[N];
+int k[N];
+long l[N];
+short n[N];
+
+__attribute__((noinline, noclone)) void
+f1 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vf2[i] = vf1[k[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f2 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = (int) vf1[k[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f3 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vf2[i] = vf1[k[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f4 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = (int) vf1[k[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f5 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vd2[i] = vd1[k[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f6 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = (int) vd1[k[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f7 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vd2[i] = vd1[k[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f8 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = (int) vd1[k[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f9 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vf2[i] = vf1[l[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f10 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = (int) vf1[l[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f11 (long x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vf2[i] = vf1[l[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f12 (long x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = (int) vf1[l[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f13 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vd2[i] = vd1[l[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f14 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = (int) vd1[l[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f15 (long x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vd2[i] = vd1[l[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f16 (long x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = (int) vd1[l[i] + x];
+}
+
+static void
+avx2_test (void)
+{
+  int i;
+
+  for (i = 0; i < N + 16; i++)
+    {
+      asm ("");
+      vf1[i] = 17.0f + i;
+      vd1[i] = 19.0 + i;
+    }
+  for (i = 0; i < N; i++)
+    {
+      asm ("");
+      k[i] = (i * 731) & (N - 1);
+      l[i] = (i * 657) & (N - 1);
+    }
+
+  f1 ();
+  f2 ();
+  for (i = 0; i < N; i++)
+    if (vf2[i] != ((i * 731) & (N - 1)) + 17
+	|| n[i] != ((i * 731) & (N - 1)) + 17)
+      abort ();
+
+  f3 (12);
+  f4 (14);
+  for (i = 0; i < N; i++)
+    if (vf2[i] != ((i * 731) & (N - 1)) + 17 + 12
+	|| n[i] != ((i * 731) & (N - 1)) + 17 + 14)
+      abort ();
+
+  f5 ();
+  f6 ();
+  for (i = 0; i < N; i++)
+    if (vd2[i] != ((i * 731) & (N - 1)) + 19
+	|| n[i] != ((i * 731) & (N - 1)) + 19)
+      abort ();
+
+  f7 (7);
+  f8 (9);
+  for (i = 0; i < N; i++)
+    if (vd2[i] != ((i * 731) & (N - 1)) + 19 + 7
+	|| n[i] != ((i * 731) & (N - 1)) + 19 + 9)
+      abort ();
+
+  f9 ();
+  f10 ();
+  for (i = 0; i < N; i++)
+    if (vf2[i] != ((i * 657) & (N - 1)) + 17
+	|| n[i] != ((i * 657) & (N - 1)) + 17)
+      abort ();
+
+  f11 (2);
+  f12 (4);
+  for (i = 0; i < N; i++)
+    if (vf2[i] != ((i * 657) & (N - 1)) + 17 + 2
+	|| n[i] != ((i * 657) & (N - 1)) + 17 + 4)
+      abort ();
+
+  f13 ();
+  f14 ();
+  for (i = 0; i < N; i++)
+    if (vd2[i] != ((i * 657) & (N - 1)) + 19
+	|| n[i] != ((i * 657) & (N - 1)) + 19)
+      abort ();
+
+  f15 (13);
+  f16 (15);
+  for (i = 0; i < N; i++)
+    if (vd2[i] != ((i * 657) & (N - 1)) + 19 + 13
+	|| n[i] != ((i * 657) & (N - 1)) + 19 + 15)
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-2.c
new file mode 100644
index 000000000..8a7fe95a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx2 -fdump-tree-vect-details" } */
+
+#include "avx2-gather-1.c"
+
+/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 16 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-3.c
new file mode 100644
index 000000000..fb6289c0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-3.c
@@ -0,0 +1,167 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2 -ffast-math" } */
+
+#include "avx2-check.h"
+
+#define N 1024
+float f[N];
+double d[N];
+int k[N];
+float *l[N];
+double *n[N];
+int **m[N];
+long **o[N];
+long q[N];
+long *r[N];
+int *s[N];
+
+__attribute__((noinline, noclone)) float
+f1 (void)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += f[k[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) float
+f2 (float *p)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += p[k[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) float
+f3 (void)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += *l[i];
+  return g;
+}
+
+__attribute__((noinline, noclone)) int
+f4 (void)
+{
+  int i;
+  int g = 0;
+  for (i = 0; i < N / 2; i++)
+    g += **m[i];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f5 (void)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += d[k[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f6 (double *p)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += p[k[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f7 (void)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += *n[i];
+  return g;
+}
+
+__attribute__((noinline, noclone)) int
+f8 (void)
+{
+  int i;
+  int g = 0;
+  for (i = 0; i < N / 2; i++)
+    g += **o[i];
+  return g;
+}
+
+__attribute__((noinline, noclone)) float
+f9 (void)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += f[q[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) float
+f10 (float *p)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += p[q[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f11 (void)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += d[q[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f12 (double *p)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += p[q[i]];
+  return g;
+}
+
+static void
+avx2_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      asm ("");
+      f[i] = -256.0f + i;
+      d[i] = -258.0 + i;
+      k[i] = (i * 731) & (N - 1);
+      q[i] = (i * 657) & (N - 1);
+      l[i] = &f[(i * 239) & (N - 1)];
+      n[i] = &d[(i * 271) & (N - 1)];
+      r[i] = &q[(i * 323) & (N - 1)];
+      s[i] = &k[(i * 565) & (N - 1)];
+      m[i] = &s[(i * 13) & (N - 1)];
+      o[i] = &r[(i * 19) & (N - 1)];
+    }
+
+  if (f1 () != 136448.0f || f2 (f) != 136448.0f || f3 () != 130304.0)
+    abort ();
+  if (f4 () != 261376 || f5 () != 135424.0 || f6 (d) != 135424.0)
+    abort ();
+  if (f7 () != 129280.0 || f8 () != 259840L || f9 () != 130816.0f)
+    abort ();
+  if (f10 (f) != 130816.0f || f11 () != 129792.0 || f12 (d) != 129792.0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-4.c
new file mode 100644
index 000000000..440a9c9b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-4.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include "avx2-check.h"
+
+#define N 1024
+int a[N], b[N], c[N], d[N];
+
+__attribute__((noinline, noclone)) void
+foo (float *__restrict p, float *__restrict q, float *__restrict r,
+     long s1, long s2, long s3)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    p[i] = q[a[i] * s1 + b[i] * s2 + s3] * r[c[i] * s1 + d[i] * s2 + s3];
+}
+
+static void
+avx2_test (void)
+{
+  int i;
+  float e[N], f[N], g[N];
+  for (i = 0; i < N; i++)
+    {
+      a[i] = (i * 7) & (N / 8 - 1);
+      b[i] = (i * 13) & (N / 8 - 1);
+      c[i] = (i * 23) & (N / 8 - 1);
+      d[i] = (i * 5) & (N / 8 - 1);
+      e[i] = 16.5 + i;
+      f[i] = 127.5 - i;
+    }
+  foo (g, e, f, 3, 2, 4);
+  for (i = 0; i < N; i++)
+    if (g[i] != (float) ((20.5 + a[i] * 3 + b[i] * 2)
+			 * (123.5 - c[i] * 3 - d[i] * 2)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-5.c
new file mode 100644
index 000000000..892a20034
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-5.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2 -fno-common" } */
+
+#include "avx2-check.h"
+
+#define N 1024
+float vf1[N+16], vf2[N], vf3[N];
+int k[N];
+
+__attribute__((noinline, noclone)) void
+foo (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    {
+      float f;
+      if (vf3[i] < 0.0f)
+	f = vf1[k[i]];
+      else
+	f = 7.0f;
+      vf2[i] = f;
+    }
+}
+
+static void
+avx2_test (void)
+{
+  int i;
+  for (i = 0; i < N + 16; i++)
+    {
+      vf1[i] = 5.5f * i;
+      if (i >= N)
+	continue;
+      vf2[i] = 2.0f;
+      vf3[i] = (i & 1) ? i : -i - 1;
+      k[i] = (i & 1) ? ((i & 2) ? -i : N / 2 + i) : (i * 7) % N;
+      asm ("");
+    }
+  foo ();
+  for (i = 0; i < N; i++)
+    if (vf1[i] != 5.5 * i
+	|| vf2[i] != ((i & 1) ? 7.0f : 5.5f * ((i * 7) % N))
+	|| vf3[i] != ((i & 1) ? i : -i - 1)
+	|| k[i] != ((i & 1) ? ((i & 2) ? -i : N / 2 + i) : ((i * 7) % N)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-6.c
new file mode 100644
index 000000000..38e2009da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-gather-6.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx2 -fno-common -fdump-tree-vect-details" } */
+
+#include "avx2-gather-5.c"
+
+/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c
new file mode 100644
index 000000000..ae3b1d577
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_i32gather_epi32 (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c
new file mode 100644
index 000000000..7d3f3474d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherd (int *s1, int *s2, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_d idx;
+  union128i_d res;
+  int s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1973 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm_i32gather_epi32 (s1, idx.x, 2);
+
+  compute_i32gatherd (s1, idx.a, 2, res_ref);
+
+  if (check_union128i_d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c
new file mode 100644
index 000000000..fc8fedea0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_mask_i32gather_epi32 (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c
new file mode 100644
index 000000000..2cc3a792e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd-4.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherd (int *src, int *s1, int *s2, int *mask, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if ((mask[i] >> 31) & 1)
+      r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_d idx;
+  union128i_d res, src, mask;
+  int s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1973 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((int *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm_mask_i32gather_epi32 (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i32gatherd (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128i_d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c
new file mode 100644
index 000000000..afc73b9b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+int *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_i32gather_epi32 (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c
new file mode 100644
index 000000000..e5bcbee1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherd256 (int *s1, int *s2, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; ++i)
+    r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_d idx;
+  union256i_d res;
+  int s1[8], res_ref[8] = { 0 };
+
+  for (i = 0; i < 8; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1973 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm256_i32gather_epi32 (s1, idx.x, 2);
+
+  compute_i32gatherd256 (s1, idx.a, 2, res_ref);
+
+  if (check_union256i_d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c
new file mode 100644
index 000000000..d0c864294
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherdd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256i x;
+int *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mask_i32gather_epi32 (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c
new file mode 100644
index 000000000..a80530912
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherd256-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherd256 (int *src,
+		       int *s1, int *s2, int *mask, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; ++i)
+    if ((mask[i] >> 31) & 1)
+      r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_d idx;
+  union256i_d res, src, mask;
+  int s1[8], res_ref[8] = { 0 };
+
+  for (i = 0; i < 8; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1973 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      mask.a[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm256_mask_i32gather_epi32 (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i32gatherd256 (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union256i_d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c
new file mode 100644
index 000000000..860cac448
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128d x;
+double *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_i32gather_pd (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c
new file mode 100644
index 000000000..475f623ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherpd (double *s1, int *s2, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 2; ++i)
+    r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_d idx;
+  union128d res;
+  double s1[2], res_ref[2] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm_i32gather_pd (s1, idx.x, 2);
+
+  compute_i32gatherpd (s1, idx.a, 2, res_ref);
+
+  if (check_union128d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c
new file mode 100644
index 000000000..5e1d4864b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128d x;
+double *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_mask_i32gather_pd (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c
new file mode 100644
index 000000000..12c533f9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherpd (double *src,
+		     double *s1, int *s2, double *mask, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 2; ++i)
+    if ((((long long *) mask)[i] >> 63) & 1)
+      r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_d idx;
+  union128d res, src, mask;
+  double s1[2], res_ref[2] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((long long *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm_mask_i32gather_pd (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i32gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c
new file mode 100644
index 000000000..00b6a35c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256d x;
+double *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_i32gather_pd (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c
new file mode 100644
index 000000000..a45801ba9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherpd256 (double *s1, int *s2, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_d idx;
+  union256d res;
+  double s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm256_i32gather_pd (s1, idx.x, 2);
+
+  compute_i32gatherpd256 (s1, idx.a, 2, res_ref);
+
+  if (check_union256d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c
new file mode 100644
index 000000000..336fb299b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherdpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256d x;
+double *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mask_i32gather_pd (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c
new file mode 100644
index 000000000..f24acbd7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherpd256-4.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherpd256 (double *src,
+			double *s1,
+			int *s2, double *mask, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if ((((long long *) mask)[i] >> 63) & 1)
+      r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_d idx;
+  union256d res, src, mask;
+  double s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((long long *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order, divide by 2
+         to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm256_mask_i32gather_pd (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i32gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union256d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c
new file mode 100644
index 000000000..c43687c4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128 x;
+float *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_i32gather_ps (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c
new file mode 100644
index 000000000..1174ddad5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherps (float *s1, int *s2, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_d idx;
+  union128 res;
+  float s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm_i32gather_ps (s1, idx.x, 2);
+
+  compute_i32gatherps (s1, idx.a, 2, res_ref);
+
+  if (check_union128 (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c
new file mode 100644
index 000000000..76b46fb23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128 x;
+float *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_mask_i32gather_ps (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c
new file mode 100644
index 000000000..94b9213d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherps (float *src,
+		     float *s1, int *s2, float *mask, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if ((((int *) mask)[i] >> 31) & 1)
+      r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_d idx;
+  union128 res, src, mask;
+  float s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((int *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm_mask_i32gather_ps (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i32gatherps (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128 (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c
new file mode 100644
index 000000000..f09a0ff32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256 x;
+float *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_i32gather_ps (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c
new file mode 100644
index 000000000..654c6f676
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherps256 (float *s1, int *s2, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 8; ++i)
+    r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_d idx;
+  union256 res;
+  float s1[8], res_ref[8] = { 0 };
+
+  for (i = 0; i < 8; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm256_i32gather_ps (s1, idx.x, 2);
+
+  compute_i32gatherps256 (s1, idx.a, 2, res_ref);
+
+  if (check_union256 (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c
new file mode 100644
index 000000000..34b7b8d72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherdps\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256 x;
+float *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mask_i32gather_ps (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c
new file mode 100644
index 000000000..07c2abacb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherps256-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherps256 (float *src,
+			float *s1, int *s2, float *mask, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 8; ++i)
+    if ((((int *) mask)[i] >> 31) & 1)
+      r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_d idx;
+  union256 res, src, mask;
+  float s1[8], res_ref[8] = { 0 };
+
+  for (i = 0; i < 8; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((int *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm256_mask_i32gather_ps (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i32gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union256 (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c
new file mode 100644
index 000000000..0b250e5dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+long long int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_i32gather_epi64 (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c
new file mode 100644
index 000000000..54838e710
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherpd (long long *s1, int *s2, int scale, long long *r)
+{
+  long long i;
+
+  for (i = 0; i < 2; ++i)
+    r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  long long i;
+  union128i_d idx;
+  union128i_q res;
+  long long s1[2], res_ref[2] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1983 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm_i32gather_epi64 ((long long int *) s1, idx.x, 2);
+
+  compute_i32gatherpd (s1, idx.a, 2, res_ref);
+
+  if (check_union128i_q (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c
new file mode 100644
index 000000000..d87400c77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+long long int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_mask_i32gather_epi64 (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c
new file mode 100644
index 000000000..4770d0ada
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq-4.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherpd (long long *src,
+		     long long *s1,
+		     int *s2, long long *mask, int scale, long long *r)
+{
+  long long i;
+
+  for (i = 0; i < 2; ++i)
+    if ((mask[i] >> 63) & 1)
+      r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  long long i;
+  union128i_d idx;
+  union128i_q res, src, mask;
+  long long s1[2], res_ref[2] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1983 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      mask.a[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x =
+    _mm_mask_i32gather_epi64 (src.x, (long long int *) s1, idx.x, mask.x, 2);
+
+  compute_i32gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128i_q (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c
new file mode 100644
index 000000000..e8651438a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+long long int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_i32gather_epi64 (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c
new file mode 100644
index 000000000..85e576797
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherpd256 (long long *s1, int *s2, int scale, long long *r)
+{
+  long long i;
+
+  for (i = 0; i < 4; ++i)
+    r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  long long i;
+  union128i_d idx;
+  union256i_q res;
+  long long s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1983 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm256_i32gather_epi64 ((long long int *) s1, idx.x, 2);
+
+  compute_i32gatherpd256 (s1, idx.a, 2, res_ref);
+
+  if (check_union256i_q (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c
new file mode 100644
index 000000000..7b6f4491a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherdq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256i x;
+long long int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mask_i32gather_epi64 (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c
new file mode 100644
index 000000000..3eab9be5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i32gatherq256-4.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i32gatherpd256 (long long *src,
+			long long *s1,
+			int *s2, long long *mask, int scale, long long *r)
+{
+  long long i;
+
+  for (i = 0; i < 4; ++i)
+    if ((mask[i] >> 63) & 1)
+      r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  long long i;
+  union128i_d idx;
+  union256i_q res, src, mask;
+  long long s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1983 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      mask.a[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order, divide by 2
+         to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm256_mask_i32gather_epi64 (src.x,
+				       (long long int *) s1,
+				       idx.x, mask.x, 2);
+
+  compute_i32gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union256i_q (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c
new file mode 100644
index 000000000..f2ade8415
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_i64gather_epi32 (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c
new file mode 100644
index 000000000..f475a4a73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherps (int *s1, long long *s2, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; ++i)
+    r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_q idx;
+  union128i_d res;
+  int s1[2], res_ref[4] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1973 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (8 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm_i64gather_epi32 (s1, idx.x, 2);
+
+  compute_i64gatherps (s1, idx.a, 2, res_ref);
+
+  if (check_union128i_d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c
new file mode 100644
index 000000000..265713da5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_mask_i64gather_epi32 (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c
new file mode 100644
index 000000000..77c8747f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherps (int *src,
+		     int *s1, long long *s2, int *mask, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; ++i)
+    if ((mask[i] >> 31) & 1)
+      r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_q idx;
+  union128i_d res, src, mask;
+  int s1[2], res_ref[4] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1973 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      mask.a[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (8 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm_mask_i64gather_epi32 (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i64gatherps (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128i_d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c
new file mode 100644
index 000000000..ccc16e523
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+int *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_i64gather_epi32 (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c
new file mode 100644
index 000000000..0f88b20b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherps256 (int *s1, long long *s2, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q idx;
+  union128i_d res;
+  int s1[8], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1973 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm256_i64gather_epi32 (s1, idx.x, 2);
+
+  compute_i64gatherps256 (s1, idx.a, 2, res_ref);
+
+  if (check_union128i_d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c
new file mode 100644
index 000000000..815e70828
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherqd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+int *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mask_i64gather_epi32 (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c
new file mode 100644
index 000000000..6c4bdd60a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherd256-4.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherps256 (int *src,
+			int *s1, long long *s2, int *mask, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if ((mask[i] >> 31) & 1)
+      r[i] = *(int *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q idx;
+  union128i_d res, src, mask;
+  int s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1973 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      mask.a[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm256_mask_i64gather_epi32 (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i64gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128i_d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c
new file mode 100644
index 000000000..895b248c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128d x;
+double *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_i64gather_pd (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c
new file mode 100644
index 000000000..5a119712e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-2.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherpd (double *s1, long long *s2, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 2; ++i)
+    r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_q idx;
+  union128d res;
+  double s1[2], res_ref[2] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order, divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm_i64gather_pd (s1, idx.x, 2);
+
+  compute_i64gatherpd (s1, idx.a, 2, res_ref);
+
+  if (check_union128d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c
new file mode 100644
index 000000000..436ffe90a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128d x;
+double *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_mask_i64gather_pd (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c
new file mode 100644
index 000000000..61cb1f8d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd-4.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherpd (double *src,
+		     double *s1,
+		     long long int *s2, double *mask, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 2; ++i)
+    if ((((long long *) mask)[i] >> 63) & 1)
+      r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_q idx;
+  union128d res, src, mask;
+  double s1[2], res_ref[2] = { 0, 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((long long *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm_mask_i64gather_pd (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i64gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c
new file mode 100644
index 000000000..bc22f02e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256d x;
+double *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_i64gather_pd (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c
new file mode 100644
index 000000000..99e192d75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherpd256 (double *s1, long long int *s2, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q idx;
+  union256d res;
+  double s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm256_i64gather_pd (s1, idx.x, 2);
+
+  compute_i64gatherpd256 (s1, idx.a, 2, res_ref);
+
+  if (check_union256d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c
new file mode 100644
index 000000000..505722a8a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherqpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256d x;
+double *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mask_i64gather_pd (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c
new file mode 100644
index 000000000..09a5f8a14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherpd256-4.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherpd256 (double *src,
+			double *s1,
+			long long int *s2, double *mask, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if ((((long long *) mask)[i] >> 63) & 1)
+      r[i] = *(double *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q idx;
+  union256d res, src, mask;
+  double s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((long long *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm256_mask_i64gather_pd (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i64gatherpd256 (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union256d (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c
new file mode 100644
index 000000000..c7d7c0787
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128 x;
+float *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_i64gather_ps (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c
new file mode 100644
index 000000000..527e4e812
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherps (float *s1, long long *s2, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 2; ++i)
+    r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_q idx;
+  union128 res;
+  float s1[2], res_ref[4] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (8 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm_i64gather_ps (s1, idx.x, 2);
+
+  compute_i64gatherps (s1, idx.a, 2, res_ref);
+
+  if (check_union128 (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c
new file mode 100644
index 000000000..ca7162ad9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128 x;
+float *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_mask_i64gather_ps (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c
new file mode 100644
index 000000000..ada4e49ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps-4.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherps (float *src,
+		     float *s1,
+		     long long *s2, float *mask, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 2; ++i)
+    if ((((int *) mask)[i] >> 31) & 1)
+      r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union128i_q idx;
+  union128 res, src, mask;
+  float s1[2], res_ref[4] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((int *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (8 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm_mask_i64gather_ps (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i64gatherps (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128 (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c
new file mode 100644
index 000000000..6612e9940
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128 x;
+float *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_i64gather_ps (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c
new file mode 100644
index 000000000..d2fe7c1fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherps256 (float *s1, long long *s2, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q idx;
+  union128 res;
+  float s1[8], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm256_i64gather_ps (s1, idx.x, 2);
+
+  compute_i64gatherps256 (s1, idx.a, 2, res_ref);
+
+  if (check_union128 (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c
new file mode 100644
index 000000000..f05e4a208
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vgatherqps\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128 x;
+float *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mask_i64gather_ps (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c
new file mode 100644
index 000000000..8185cd839
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherps256-4.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherps256 (float *src,
+			float *s1,
+			long long *s2, float *mask, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if ((((int *) mask)[i] >> 31) & 1)
+      r[i] = *(float *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q idx;
+  union128 res, src, mask;
+  float s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((int *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm256_mask_i64gather_ps (src.x, s1, idx.x, mask.x, 2);
+
+  compute_i64gatherps256 (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128 (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c
new file mode 100644
index 000000000..8f9752d2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+long long int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_i64gather_epi64 (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c
new file mode 100644
index 000000000..a2d7a9968
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherpd (long long *s1, long long *s2, int scale, long long *r)
+{
+  long long i;
+
+  for (i = 0; i < 2; ++i)
+    r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  long long i;
+  union128i_q idx;
+  union128i_q res;
+  long long s1[2], res_ref[2] = { 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1983 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm_i64gather_epi64 ((long long int *) s1, idx.x, 2);
+
+  compute_i64gatherpd (s1, idx.a, 2, res_ref);
+
+  if (check_union128i_q (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c
new file mode 100644
index 000000000..c1c31c728
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]\[^\n\]*xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+long long int *base;
+__m128i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_mask_i64gather_epi64 (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c
new file mode 100644
index 000000000..cbc8e31f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq-4.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherpd (long long *src,
+		     long long *s1,
+		     long long *s2, long long *mask, int scale, long long *r)
+{
+  long long i;
+
+  for (i = 0; i < 2; ++i)
+    if ((mask[i] >> 63) & 1)
+      r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  long long i;
+  union128i_q idx;
+  union128i_q res, src, mask;
+  long long s1[2], res_ref[2] = { 0, 0 };
+
+  for (i = 0; i < 2; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1983 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      mask.a[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x =
+    _mm_mask_i64gather_epi64 (src.x, (long long int *) s1, idx.x, mask.x, 2);
+
+  compute_i64gatherpd (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union128i_q (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c
new file mode 100644
index 000000000..c873cb954
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+long long int *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_i64gather_epi64 (base, idx, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c
new file mode 100644
index 000000000..3ac3e2e01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherq256 (long long *s1, long long *s2, int scale, long long *r)
+{
+  long long i;
+
+  for (i = 0; i < 4; ++i)
+    r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale);
+}
+
+void static
+avx2_test (void)
+{
+  long long i;
+  union256i_q idx;
+  union256i_q res;
+  long long s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1983 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm256_i64gather_epi64 ((long long int *) s1, idx.x, 2);
+
+  compute_i64gatherq256 (s1, idx.a, 2, res_ref);
+
+  if (check_union256i_q (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c
new file mode 100644
index 000000000..f60ad2274
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpgatherqq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256i x;
+long long int *base;
+__m256i idx;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mask_i64gather_epi64 (x, base, idx, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c
new file mode 100644
index 000000000..355c8c2b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-i64gatherq256-4.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_i64gatherq256 (long long *src,
+		       long long *s1,
+		       long long *s2,
+		       long long *mask, int scale, long long *r)
+{
+  long long i;
+
+  for (i = 0; i < 4; ++i)
+    if ((mask[i] >> 63) & 1)
+      r[i] = *(long long *) (((unsigned char *) s1) + s2[i] * scale);
+    else
+      r[i] = src[i];
+}
+
+void static
+avx2_test (void)
+{
+  long long i;
+  union256i_q idx;
+  union256i_q res, src, mask;
+  long long s1[4], res_ref[4] = { 0 };
+
+  for (i = 0; i < 4; ++i)
+    {
+      /* Set some stuff */
+      s1[i] = 1983 * (i + 1) * (i + 2);
+
+      /* Set src as something different from s1 */
+      src.a[i] = -s1[i];
+
+      /* Mask out evens */
+      ((long long *) mask.a)[i] = i % 2 ? 0 : -1;
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (16 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm256_mask_i64gather_epi64 (src.x,
+				       (long long int *) s1,
+				       idx.x, mask.x, 2);
+
+  compute_i64gatherq256 (src.a, s1, idx.a, mask.a, 2, res_ref);
+
+  if (check_union256i_q (res, res_ref) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c
new file mode 100644
index 000000000..740e14163
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx2" } */
+/* { dg-final { scan-assembler "mpsadbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  /* imm = 13 is arbitrary here */
+  x = _mm256_mpsadbw_epu8 (x, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c
new file mode 100644
index 000000000..18118e442
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mpsadbw-2.c
@@ -0,0 +1,132 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define msk0 0xC0
+#define msk1 0x01
+#define msk2 0xF2
+#define msk3 0x03
+#define msk4 0x84
+#define msk5 0x05
+#define msk6 0xE6
+#define msk7 0x67
+
+
+static void
+compute_mpsadbw (int *i1, int *i2, int mask, int *r)
+{
+  unsigned char s[4];
+  int i, j;
+  int offs1, offs2;
+  unsigned char *v1 = (char *) i1;
+  unsigned char *v2 = (char *) i2;
+  unsigned short *ret = (unsigned short *) r;
+
+  memset (ret, 0, 32);
+
+  /* Lower part */
+  offs2 = 4 * (mask & 3);
+  for (i = 0; i < 4; i++)
+    s[i] = v2[offs2 + i];
+
+  offs1 = 4 * ((mask & 4) >> 2);
+  for (j = 0; j < 8; j++)
+    for (i = 0; i < 4; i++)
+      ret[j] += abs (v1[offs1 + j + i] - s[i]);
+
+  /* Higher part */
+  offs2 = 4 * ((mask >> 3) & 3) + 16;
+  for (i = 0; i < 4; i++)
+    s[i] = v2[offs2 + i];
+
+  offs1 = 4 * ((mask & 0x20) >> 5) + 16;
+  for (j = 0; j < 8; j++)
+    for (i = 0; i < 4; i++)
+      ret[j + 8] += abs (v1[offs1 + j + i] - s[i]);
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d val1, val2, val3[8], res[8];
+  int tmp[8];
+  unsigned char masks[8];
+  int i, j;
+
+  val1.a[0] = 0x35251505;
+  val1.a[1] = 0x75655545;
+  val1.a[2] = 0xB5A59585;
+  val1.a[3] = 0xF5E5D5C5;
+
+  val1.a[4] = 0x35251505;
+  val1.a[5] = 0x75655545;
+  val1.a[6] = 0xB5A59585;
+  val1.a[7] = 0xF5E5D5C5;
+
+  val2.a[0] = 0x31211101;
+  val2.a[1] = 0x71615141;
+  val2.a[2] = 0xB1A19181;
+  val2.a[3] = 0xF1E1D1C1;
+
+  val2.a[4] = 0x31211101;
+  val2.a[5] = 0x71615141;
+  val2.a[6] = 0xB1A19181;
+  val2.a[7] = 0xF1E1D1C1;
+
+  for (i = 0; i < 8; i++)
+    switch (i % 3)
+      {
+      case 1:
+	val3[i].a[0] = 0xF1E1D1C1;
+	val3[i].a[1] = 0xB1A19181;
+	val3[i].a[2] = 0x71615141;
+	val3[i].a[3] = 0x31211101;
+	break;
+      default:
+	val3[i].x = val2.x;
+	break;
+      }
+
+  /* Check mpsadbw imm8, ymm, ymm.  */
+  res[0].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk0);
+  res[1].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk1);
+  res[2].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk2);
+  res[3].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk3);
+  res[4].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk4);
+  res[5].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk5);
+  res[6].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk6);
+  res[7].x = _mm256_mpsadbw_epu8 (val1.x, val2.x, msk7);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+
+  for (i = 0; i < 8; i++)
+    {
+      compute_mpsadbw (val1.a, val2.a, masks[i], tmp);
+      if (check_union256i_d (res[i], tmp))
+	abort ();
+    }
+
+  /* Check mpsadbw imm8, m256, ymm.  */
+  for (i = 0; i < 8; i++)
+    {
+      res[i].x = _mm256_mpsadbw_epu8 (val1.x, val3[i].x, msk4);
+      masks[i] = msk4;
+    }
+
+  for (i = 0; i < 8; i++)
+    {
+      compute_mpsadbw (val1.a, val3[i].a, masks[i], tmp);
+      if (check_union256i_d (res[i], tmp))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mul-1.c
new file mode 100644
index 000000000..0351fbb7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-mul-1.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx2_test
+#endif
+
+#include "sse2-mul-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr51581-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr51581-1.c
new file mode 100644
index 000000000..74d507fd9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr51581-1.c
@@ -0,0 +1,9 @@
+/* PR tree-optimization/51581 */
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -mavx2 -fno-vect-cost-model" } */
+/* { dg-require-effective-target avx2 } */
+
+#define CHECK_H "avx2-check.h"
+#define TEST avx2_test
+
+#include "avx-pr51581-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr51581-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr51581-2.c
new file mode 100644
index 000000000..bf063c2ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-pr51581-2.c
@@ -0,0 +1,9 @@
+/* PR tree-optimization/51581 */
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -mavx2 -fno-vect-cost-model" } */
+/* { dg-require-effective-target avx2 } */
+
+#define CHECK_H "avx2-check.h"
+#define TEST avx2_test
+
+#include "avx-pr51581-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c
new file mode 100644
index 000000000..80964e39d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vbroadcastsd\[ \\t\]+\[^\n\]*" } } */
+
+#include <immintrin.h>
+
+__m128d x;
+__m256d y;
+
+void extern
+avx2_test (void)
+{
+  y = _mm256_broadcastsd_pd (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c
new file mode 100644
index 000000000..ee323f5af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsd_pd-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union128d s1;
+  union256d res;
+  double res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      s1.a[0] = i * 3.14;
+
+      res.x = _mm256_broadcastsd_pd (s1.x);
+
+      for (j = 0; j < 4; j++)
+	memcpy (res_ref + j, s1.a, 8);
+
+      fail += check_union256d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c
new file mode 100644
index 000000000..7805e3ddb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vbroadcasti128\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_broadcastsi128_si256 (y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c
new file mode 100644
index 000000000..ef1d370ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastsi128-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union128i_q s1;
+  union256i_q res;
+  long long int res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 2; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_broadcastsi128_si256 (s1.x);
+
+      memcpy (res_ref, s1.a, 16);
+      memcpy (res_ref + 2, s1.a, 16);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c
new file mode 100644
index 000000000..d9d47e2a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vbroadcastss\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128 x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_broadcastss_ps (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c
new file mode 100644
index 000000000..1637e703b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union128 s1, res;
+  float res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      s1.a[0] = i * 3.14;
+
+      res.x = _mm_broadcastss_ps (s1.x);
+
+      for (j = 0; j < 4; j++)
+	memcpy (res_ref + j, s1.a, 4);
+
+      fail += check_union128 (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c
new file mode 100644
index 000000000..dfac3916b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vbroadcastss\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128 x;
+__m256 y;
+
+void extern
+avx2_test (void)
+{
+  y = _mm256_broadcastss_ps (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c
new file mode 100644
index 000000000..9f90e2e85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vbroadcastss_ps256-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union128 s1;
+  union256 res;
+  float res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      s1.a[0] = i * 3.14;
+
+      res.x = _mm256_broadcastss_ps (s1.x);
+
+      for (j = 0; j < 8; j++)
+	memcpy (res_ref + j, s1.a, 4);
+
+      fail += check_union256 (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c
new file mode 100644
index 000000000..a032e3c9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vextracti128-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vextracti128\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  y = _mm256_extracti128_si256 (x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c
new file mode 100644
index 000000000..7d3c561a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vextracti128-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_q s1;
+  union128i_q res;
+  long long int res_ref[2];
+  int j;
+
+  for (j = 0; j < 4; j++)
+    s1.a[j] = j * j;
+
+  res.x = _mm256_extracti128_si256 (s1.x, 0);
+
+  memset (res_ref, 0, 16);
+  memcpy (res_ref, s1.a, 16);
+
+  if (check_union128i_q (res, res_ref))
+    abort ();
+
+  res.x = _mm256_extracti128_si256 (s1.x, 1);
+
+  memset (res_ref, 0, 16);
+  memcpy (res_ref, s1.a + 2, 16);
+
+  if (check_union128i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c
new file mode 100644
index 000000000..2d0f7c51a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vinserti128-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vinserti128\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_inserti128_si256 (x, y, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c
new file mode 100644
index 000000000..f6361cd47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vinserti128-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, res;
+  union128i_q s2;
+  long long int res_ref[4];
+  int j;
+
+  for (j = 0; j < 4; j++)
+    s1.a[j] = j * j;
+
+  for (j = 0; j < 2; j++)
+    s2.a[j] = j * j * j;
+
+  res.x = _mm256_inserti128_si256 (s1.x, s2.x, 0);
+
+  memcpy (res_ref, s1.a, 32);
+  memcpy (res_ref, s2.a, 16);
+
+  if (check_union256i_q (res, res_ref))
+    abort ();
+
+  res.x = _mm256_inserti128_si256 (s1.x, s2.x, 1);
+
+  memcpy (res_ref, s1.a, 32);
+  memcpy (res_ref + 2, s2.a, 16);
+
+  if (check_union256i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c
new file mode 100644
index 000000000..4c44f082d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vmovntdqa\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m256i *y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_stream_load_si256 (y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c
new file mode 100644
index 000000000..f1eda70bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vmovntdqa-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, res;
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_stream_load_si256 (&s1.x);
+
+      fail += check_union256i_q (res, s1.a);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c
new file mode 100644
index 000000000..0607a886c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpabsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_abs_epi8 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c
new file mode 100644
index 000000000..05db8a407
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsb256-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "ssse3-vals.h"
+#include "avx2-check.h"
+
+/* Routine to manually compute the results */
+static void
+compute_pabs256 (int *i1, char *r)
+{
+  char *b1 = (char *) i1;
+  int i;
+
+  for (i = 0; i < 32; i++)
+    if (b1[i] < 0)
+      r[i] = -b1[i];
+    else
+      r[i] = b1[i];
+}
+
+static void
+avx2_test (void)
+{
+  int i;
+  char ck[32];
+  int fail = 0;
+
+  union256i_b s, d;
+
+  for (i = 0; i < 256; ++i)
+    {
+      /* Recompute the results for 256-bits */
+      compute_pabs256 (&vals[i], ck);
+
+      s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+
+      /* Run the 256-bit tests */
+      d.x = _mm256_abs_epi8 (s.x);
+
+      fail += check_union256i_b (d, ck);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c
new file mode 100644
index 000000000..396077ff1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpabsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_abs_epi32 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c
new file mode 100644
index 000000000..4c88024b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsd256-2.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "ssse3-vals.h"
+#include "avx2-check.h"
+
+/* Routine to manually compute the results */
+static void
+compute_pabs256 (int *i1, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    if (i1[i] < 0)
+      r[i] = -i1[i];
+    else
+      r[i] = i1[i];
+}
+
+static void
+avx2_test (void)
+{
+  int i;
+  int ck[8];
+  int fail = 0;
+
+  union256i_d s, d;
+
+  for (i = 0; i < 256; ++i)
+    {
+      /* Recompute the results for 256-bits */
+      compute_pabs256 (&vals[i], ck);
+
+      s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+
+      /* Run the 256-bit tests */
+      d.x = _mm256_abs_epi32 (s.x);
+
+      fail += check_union256i_d (d, ck);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c
new file mode 100644
index 000000000..2dc7692ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpabsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_abs_epi16 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c
new file mode 100644
index 000000000..fa4efd298
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpabsw256-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "ssse3-vals.h"
+#include "avx2-check.h"
+
+/* Routine to manually compute the results */
+static void
+compute_pabs256 (int *i1, short *r)
+{
+  short *b1 = (short *) i1;
+  int i;
+
+  for (i = 0; i < 16; i++)
+    if (b1[i] < 0)
+      r[i] = -b1[i];
+    else
+      r[i] = b1[i];
+}
+
+static void
+avx2_test (void)
+{
+  int i;
+  short ck[16];
+  int fail = 0;
+
+  union256i_w s, d;
+
+  for (i = 0; i < 256; ++i)
+    {
+      /* Using only first 2 bytes of int */
+      /* Recompute the results for 256-bits */
+      compute_pabs256 (&vals[i], ck);
+
+      s.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+
+      /* Run the 256-bit tests */
+      d.x = _mm256_abs_epi16 (s.x);
+
+      fail += check_union256i_w (d, ck);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c
new file mode 100644
index 000000000..6d5667a64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpackssdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_packs_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c
new file mode 100644
index 000000000..16f0d23f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackssdw-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static short
+int_to_short (int iVal)
+{
+  short sVal;
+
+  if (iVal < -32768)
+    sVal = -32768;
+  else if (iVal > 32767)
+    sVal = 32767;
+  else
+    sVal = iVal;
+
+  return sVal;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, s2;
+  union256i_w u;
+  short e[16];
+  int i;
+
+  s1.x = _mm256_set_epi32 (1, 2, 3, 4, 65000, 20, 30, 90);
+
+  s2.x = _mm256_set_epi32 (88, 44, 33, 22, 11, 98, 76, -65000);
+
+  u.x = _mm256_packs_epi32 (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    {
+      e[i] = int_to_short (s1.a[i]);
+      e[i + 4] = int_to_short (s2.a[i]);
+      e[i + 8] = int_to_short (s1.a[i + 4]);
+      e[i + 12] = int_to_short (s2.a[i + 4]);
+    }
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c
new file mode 100644
index 000000000..00faf844a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpacksswb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_packs_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c
new file mode 100644
index 000000000..8b2a1c111
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpacksswb-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static char
+short_to_byte (short iVal)
+{
+  char sVal;
+
+  if (iVal < -128)
+    sVal = -128;
+  else if (iVal > 127)
+    sVal = 127;
+  else
+    sVal = iVal;
+
+  return sVal;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, s2;
+  union256i_b u;
+  char e[32];
+  int i;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 6500, 20, 30, 90,
+			   88, 44, 33, 22, 11, 98, 78, -1000);
+
+  s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -650,
+			   1, 2, 3, 4, 6500, 20, 30, 90);
+
+  u.x = _mm256_packs_epi16 (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    {
+      e[i] = short_to_byte (s1.a[i]);
+      e[i + 8] = short_to_byte (s2.a[i]);
+      e[i + 16] = short_to_byte (s1.a[i + 8]);
+      e[i + 24] = short_to_byte (s2.a[i + 8]);
+    }
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c
new file mode 100644
index 000000000..1f0a7ff9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpackusdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_packus_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c
new file mode 100644
index 000000000..afc102610
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackusdw-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static unsigned short
+int_to_ushort (int iVal)
+{
+  unsigned short sVal;
+
+  if (iVal < 0)
+    sVal = 0;
+  else if (iVal > 65536)
+    sVal = 65535;
+  else
+    sVal = iVal;
+
+  return sVal;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, s2;
+  union256i_w u;
+  unsigned short e[16];
+  int i;
+
+  s1.x = _mm256_set_epi32 (1, 2, 3, 4, -65000, 20, 30, 90);
+
+  s2.x = _mm256_set_epi32 (88, 44, 33, 22, 11, 98, 76, 120000);
+
+  u.x = _mm256_packus_epi32 (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    {
+      e[i] = int_to_ushort (s1.a[i]);
+      e[i + 4] = int_to_ushort (s2.a[i]);
+      e[i + 8] = int_to_ushort (s1.a[i + 4]);
+      e[i + 12] = int_to_ushort (s2.a[i + 4]);
+    }
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c
new file mode 100644
index 000000000..7b30a6666
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpackuswb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_packus_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c
new file mode 100644
index 000000000..abeee3e6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpackuswb-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static unsigned char
+short_to_ubyte (short iVal)
+{
+  unsigned char sVal;
+
+  if (iVal < 0)
+    sVal = 0;
+  else if (iVal > 255)
+    sVal = 255;
+  else
+    sVal = iVal;
+
+  return sVal;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, s2;
+  union256i_b u;
+  char e[32];
+  int i;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 6500, 20, 30, 90,
+			   88, 44, 33, 22, 11, 98, 78, -1000);
+
+  s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -650,
+			   1, 2, 3, 4, 6500, 20, 30, 90);
+
+  u.x = _mm256_packus_epi16 (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    {
+      e[i] = short_to_ubyte (s1.a[i]);
+      e[i + 8] = short_to_ubyte (s2.a[i]);
+      e[i + 16] = short_to_ubyte (s1.a[i + 8]);
+      e[i + 24] = short_to_ubyte (s2.a[i + 8]);
+    }
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c
new file mode 100644
index 000000000..b6ceef16f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpaddb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_add_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c
new file mode 100644
index 000000000..8abeb50c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  char e[32];
+  unsigned i;
+
+  s1.x = _mm256_set_epi8 (10, 74, 50, 4, 6, 99, 1, 4, 87, 83, 84,
+			  29, 81, 79, 1, 3, 1, 5, 2, 47, 20, 2, 72,
+			  92, 9, 4, 23, 17, 99, 43, 72, 17);
+
+  s2.x = _mm256_set_epi8 (88, 44, 33, 20, 56, 99, 2, 90, 38, 4, 200,
+			  17, 3, 39, 2, 37, 27, 95, 17, 74, 72, 43,
+			  27, 112, 71, 50, 32, 72, 84, 17, 27, 96);
+
+  u.x = _mm256_add_epi8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
new file mode 100644
index 000000000..238f02092
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE char
+#define BIN_OP(a, b) ((a) + (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpaddb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c
new file mode 100644
index 000000000..14142ec0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_add_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c
new file mode 100644
index 000000000..c3b196196
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-2.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_d u, s1, s2;
+  int e[8];
+  unsigned i;
+
+  s1.x = _mm256_set_epi32 (100, 74, 50000, 4, 6999, 39999, 1000, 4);
+  s2.x = _mm256_set_epi32 (88, 44, 33, 220, 4556, 2999, 2, 9000000);
+
+  u.x = _mm256_add_epi32 (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c
new file mode 100644
index 000000000..c57ef8fea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE int
+#define BIN_OP(a, b) ((a) + (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c
new file mode 100644
index 000000000..9fcf9aaad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpaddq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_add_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c
new file mode 100644
index 000000000..03b011f3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-2.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_q u, s1, s2;
+  long long e[4];
+  unsigned i;
+
+  s1.x = _mm256_set_epi64x (100, 74, 50000, 4);
+  s2.x = _mm256_set_epi64x (88, 44, 33, 220);
+
+  u.x = _mm256_add_epi64 (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union256i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
new file mode 100644
index 000000000..801bd39d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE long long int
+#define BIN_OP(a, b) ((a) + (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpaddq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c
new file mode 100644
index 000000000..77978d936
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpaddsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_adds_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c
new file mode 100644
index 000000000..d07a6a781
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsb-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  char e[32];
+  int i, tmp;
+
+  s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100,
+			  -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98,
+			  76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+
+  s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78,
+			  -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20,
+			  30, 90, -80, -40, -100, -15, 98, 25, 98, 7);
+
+  u.x = _mm256_adds_epi8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+
+      if (tmp > 127)
+	tmp = 127;
+      if (tmp < -128)
+	tmp = -128;
+
+      e[i] = tmp;
+    }
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c
new file mode 100644
index 000000000..128f5309f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpaddsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_adds_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c
new file mode 100644
index 000000000..19bbe0a77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddsw-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_w u, s1, s2;
+  short e[16];
+  int i, tmp;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80,
+			   -40, -100, -15, 98, 25, 98, 7);
+
+  s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -100,
+			   -34, -78, -39, 6, 3, 4, 5, 119);
+
+  u.x = _mm256_adds_epi16 (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+
+      if (tmp > 32767)
+	tmp = 32767;
+      if (tmp < -32768)
+	tmp = -32768;
+
+      e[i] = tmp;
+    }
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c
new file mode 100644
index 000000000..f6cf4019c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpaddusb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_adds_epu8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c
new file mode 100644
index 000000000..68ad4f03f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusb-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  unsigned char e[32];
+  unsigned i, tmp;
+
+  s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, 80, 40, 100, 15,
+			  98, 25, 98, 7, 88, 44, 33, 22, 11, 98, 76,
+			  200, 34, 78, 39, 6, 3, 4, 5, 119);
+
+  s2.x = _mm256_set_epi8 (88, 44, 33, 220, 11, 98, 76, 100, 34, 78, 39,
+			  6, 3, 4, 5, 219, 1, 2, 3, 4, 10, 20, 30, 90,
+			  80, 40, 100, 15, 98, 25, 98, 7);
+
+  u.x = _mm256_adds_epu8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    {
+      tmp = (unsigned char) s1.a[i] + (unsigned char) s2.a[i];
+
+      if (tmp > 255)
+	tmp = 255;
+
+      e[i] = tmp;
+    }
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c
new file mode 100644
index 000000000..a4c1dd9bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpaddusw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_adds_epu16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c
new file mode 100644
index 000000000..937b93c21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddusw-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_w u, s1, s2;
+  unsigned short e[32];
+  unsigned i, tmp;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90,
+			   65531, 40, 100, 15, 98, 25, 98, 7);
+
+  s2.x = _mm256_set_epi16 (88, 44, 33, 220, 11, 98, 76, 100,
+			   34, 78, 39, 6, 3, 4, 5, 219);
+
+  u.x = _mm256_adds_epu16 (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp = (unsigned short) s1.a[i] + (unsigned short) s2.a[i];
+
+      if (tmp > 65535)
+	tmp = 65535;
+
+      e[i] = tmp;
+    }
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c
new file mode 100644
index 000000000..052e3a352
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_add_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c
new file mode 100644
index 000000000..f7dbf2053
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_w u, s1, s2;
+  short e[16];
+  unsigned i;
+
+  s1.x = _mm256_set_epi16 (100, 74, 50000, 4, 6999, 39999, 1000, 4,
+			   874, 2783, 29884, 2904, 2889, 3279, 1, 3);
+  s2.x = _mm256_set_epi16 (88, 44, 33, 220, 4556, 2999, 2, 9000,
+			   238, 194, 274, 17, 3, 5739, 2, 379);
+
+  u.x = _mm256_add_epi16 (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
new file mode 100644
index 000000000..facee9f2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE short
+#define BIN_OP(a, b) ((a) + (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c
new file mode 100644
index 000000000..a87a207d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx2" } */
+/* { dg-final { scan-assembler "vpalignr\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  /* imm = 13 is arbitrary here */
+  x = _mm256_alignr_epi8 (x, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c
new file mode 100644
index 000000000..5be64c0cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpalignr256-2.c
@@ -0,0 +1,177 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "ssse3-vals.h"
+#include "avx2-check.h"
+
+/* Test the 256-bit form */
+static void
+avx2_test_palignr256 (__m256i t1, __m256i t2, unsigned int imm, __m256i * r)
+{
+  switch (imm)
+    {
+    case 0:
+      *r = _mm256_alignr_epi8 (t1, t2, 0);
+      break;
+    case 1:
+      *r = _mm256_alignr_epi8 (t1, t2, 1);
+      break;
+    case 2:
+      *r = _mm256_alignr_epi8 (t1, t2, 2);
+      break;
+    case 3:
+      *r = _mm256_alignr_epi8 (t1, t2, 3);
+      break;
+    case 4:
+      *r = _mm256_alignr_epi8 (t1, t2, 4);
+      break;
+    case 5:
+      *r = _mm256_alignr_epi8 (t1, t2, 5);
+      break;
+    case 6:
+      *r = _mm256_alignr_epi8 (t1, t2, 6);
+      break;
+    case 7:
+      *r = _mm256_alignr_epi8 (t1, t2, 7);
+      break;
+    case 8:
+      *r = _mm256_alignr_epi8 (t1, t2, 8);
+      break;
+    case 9:
+      *r = _mm256_alignr_epi8 (t1, t2, 9);
+      break;
+    case 10:
+      *r = _mm256_alignr_epi8 (t1, t2, 10);
+      break;
+    case 11:
+      *r = _mm256_alignr_epi8 (t1, t2, 11);
+      break;
+    case 12:
+      *r = _mm256_alignr_epi8 (t1, t2, 12);
+      break;
+    case 13:
+      *r = _mm256_alignr_epi8 (t1, t2, 13);
+      break;
+    case 14:
+      *r = _mm256_alignr_epi8 (t1, t2, 14);
+      break;
+    case 15:
+      *r = _mm256_alignr_epi8 (t1, t2, 15);
+      break;
+    case 16:
+      *r = _mm256_alignr_epi8 (t1, t2, 16);
+      break;
+    case 17:
+      *r = _mm256_alignr_epi8 (t1, t2, 17);
+      break;
+    case 18:
+      *r = _mm256_alignr_epi8 (t1, t2, 18);
+      break;
+    case 19:
+      *r = _mm256_alignr_epi8 (t1, t2, 19);
+      break;
+    case 20:
+      *r = _mm256_alignr_epi8 (t1, t2, 20);
+      break;
+    case 21:
+      *r = _mm256_alignr_epi8 (t1, t2, 21);
+      break;
+    case 22:
+      *r = _mm256_alignr_epi8 (t1, t2, 22);
+      break;
+    case 23:
+      *r = _mm256_alignr_epi8 (t1, t2, 23);
+      break;
+    case 24:
+      *r = _mm256_alignr_epi8 (t1, t2, 24);
+      break;
+    case 25:
+      *r = _mm256_alignr_epi8 (t1, t2, 25);
+      break;
+    case 26:
+      *r = _mm256_alignr_epi8 (t1, t2, 26);
+      break;
+    case 27:
+      *r = _mm256_alignr_epi8 (t1, t2, 27);
+      break;
+    case 28:
+      *r = _mm256_alignr_epi8 (t1, t2, 28);
+      break;
+    case 29:
+      *r = _mm256_alignr_epi8 (t1, t2, 29);
+      break;
+    case 30:
+      *r = _mm256_alignr_epi8 (t1, t2, 30);
+      break;
+    case 31:
+      *r = _mm256_alignr_epi8 (t1, t2, 31);
+      break;
+    default:
+      *r = _mm256_alignr_epi8 (t1, t2, 32);
+      break;
+    }
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result_256 (int *i1, int *i2, unsigned int imm, int *r)
+{
+  char buf[32];
+  char *bout = (char *) r;
+  int i;
+
+  /* Fill lowers 128 bit of ymm */
+  memcpy (&buf[0], i2, 16);
+  memcpy (&buf[16], i1, 16);
+
+  for (i = 0; i < 16; i++)
+    if (imm >= 32 || imm + i >= 32)
+      bout[i] = 0;
+    else
+      bout[i] = buf[imm + i];
+
+  /* Fill higher 128 bit of ymm */
+  bout += 16;
+  memcpy (&buf[0], i2 + 4, 16);
+  memcpy (&buf[16], i1 + 4, 16);
+
+  for (i = 0; i < 16; i++)
+    if (imm >= 32 || imm + i >= 32)
+      bout[i] = 0;
+    else
+      bout[i] = buf[imm + i];
+}
+
+static void
+avx2_test (void)
+{
+  int i;
+  int ck[8];
+  int r[8];
+  unsigned int imm;
+  int fail = 0;
+
+  union256i_q s1, s2, d;
+
+  for (i = 0; i < 256; i += 16)
+    for (imm = 0; imm < 100; imm++)
+      {
+	/* Recompute the results for 256-bits */
+	compute_correct_result_256 (&vals[i + 0], &vals[i + 8], imm, ck);
+
+	s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 0]);
+	s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]);
+
+	/* Run the 256-bit tests */
+	avx2_test_palignr256 (s1.x, s2.x, imm, &d.x);
+
+	_mm256_storeu_si256 ((__m256i *) r, d.x);
+
+	fail += checkVi (r, ck, 8);
+      }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c
new file mode 100644
index 000000000..e77e36982
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpand\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_and_si256 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c
new file mode 100644
index 000000000..ffd3404e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q u, s1, s2;
+  int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 };
+  int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 };
+  int d[8];
+  int e[8];
+
+  s1.x = _mm256_loadu_si256 ((__m256i *) source1);
+  s2.x = _mm256_loadu_si256 ((__m256i *) source2);
+  u.x = _mm256_and_si256 (s1.x, s2.x);
+
+  _mm256_storeu_si256 ((__m256i *) d, u.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = source1[i] & source2[i];
+
+  if (checkVi (d, e, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c
new file mode 100644
index 000000000..67ca4a7cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE unsigned
+#define BIN_OP(a, b) ((a) & (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpand\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c
new file mode 100644
index 000000000..b06889884
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpandn-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpandn\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_andnot_si256 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c
new file mode 100644
index 000000000..06d3cbd23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpandn-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q u, s1, s2;
+  int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 };
+  int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 };
+  int d[8];
+  int e[8];
+
+  s1.x = _mm256_loadu_si256 ((__m256i *) source1);
+  s2.x = _mm256_loadu_si256 ((__m256i *) source2);
+  u.x = _mm256_andnot_si256 (s1.x, s2.x);
+
+  _mm256_storeu_si256 ((__m256i *) d, u.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (~source1[i]) & source2[i];
+
+  if (checkVi (d, e, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c
new file mode 100644
index 000000000..a7abd6751
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpavgb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_avg_epu8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c
new file mode 100644
index 000000000..8519e9bc3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgb-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  unsigned char e[32];
+  int tmp;
+  int i;
+
+  s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100,
+			  -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98,
+			  76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+
+  s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78,
+			  -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20,
+			  30, 90, -80, -40, -100, -15, 98, 25, 98, 7);
+
+  u.x = _mm256_avg_epu8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    e[i] = ((unsigned char) s1.a[i] + (unsigned char) s2.a[i] + 1) >> 1;
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c
new file mode 100644
index 000000000..dc68b8a6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpavgw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_avg_epu16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c
new file mode 100644
index 000000000..d222a9d4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpavgw-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_w u, s1, s2;
+  unsigned short e[32];
+  int i;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, 80,
+			   40, 100, 15, 98, 25, 98, 7);
+  s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, 100,
+			   34, 78, 39, 6, 3, 4, 5, 119);
+
+  u.x = _mm256_avg_epu16 (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    e[i] = (s1.a[i] + s2.a[i] + 1) >> 1;
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c
new file mode 100644
index 000000000..a3fea9554
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpblendd\[ \\t\]+\[^\n\]*" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_blend_epi32 (x, y, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c
new file mode 100644
index 000000000..44732cc6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd128-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 20
+
+#undef MASK
+#define MASK 0xf1
+
+static void
+init_pblendd128 (int *src1, int *src2, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 4; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      src2[i] = (i + seed + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pblendd128 (int *src1, int *src2, unsigned int mask, int *dst)
+{
+  int i;
+
+  memcpy (dst, src1, 16);
+  for (i = 0; i < 4; i++)
+    if (mask & (1 << i))
+      dst[i] = src2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_d src1, src2, dst;
+  int dst_ref[4];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pblendd128 (src1.a, src2.a, i);
+
+      dst.x = _mm_blend_epi32 (src1.x, src2.x, MASK);
+      calc_pblendd128 (src1.a, src2.a, MASK, dst_ref);
+
+      if (check_union128i_d (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c
new file mode 100644
index 000000000..ab7498854
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpblendd\[ \\t\]+\[^\n\]*" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_blend_epi32 (x, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c
new file mode 100644
index 000000000..fc5e3f7be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendd256-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 20
+
+#undef MASK
+#define MASK 0xf1
+
+static void
+init_pblendd256 (int *src1, int *src2, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 8; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      src2[i] = (i + seed + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pblendd256 (int *src1, int *src2, unsigned int mask, int *dst)
+{
+  int i;
+
+  memcpy (dst, src1, 32);
+  for (i = 0; i < 8; i++)
+    if (mask & (1 << i))
+      dst[i] = src2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d src1, src2, dst;
+  int dst_ref[8];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pblendd256 (src1.a, src2.a, i);
+
+      dst.x = _mm256_blend_epi32 (src1.x, src2.x, MASK);
+      calc_pblendd256 (src1.a, src2.a, MASK, dst_ref);
+
+      if (check_union256i_d (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c
new file mode 100644
index 000000000..09ff4bcca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpblendvb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_blendv_epi8 (x, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c
new file mode 100644
index 000000000..c0e1d71ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendvb-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_pblendb (char *src1, char *src2, char *mask, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 32; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      src2[i] = (i + seed + 20) * sign;
+      sign = -sign;
+
+      if (sign > 0)
+	mask[i] = 1 << 7;
+      else
+	mask[i] = 0;
+    }
+}
+
+static void
+calc_pblendb (char *src1, char *src2, char *mask, char *dst)
+{
+  int i;
+
+  memcpy (dst, src1, 32);
+  for (i = 0; i < 32; i++)
+    if (mask[i] & (1 << 7))
+      dst[i] = src2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_b src1, src2, mask, dst;
+  char dst_ref[32];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pblendb (src1.a, src2.a, mask.a, i);
+
+      dst.x = _mm256_blendv_epi8 (src1.x, src2.x, mask.x);
+      calc_pblendb (src1.a, src2.a, mask.a, dst_ref);
+
+      if (check_union256i_b (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c
new file mode 100644
index 000000000..7bbb93e4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpblendw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_blend_epi16 (x, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c
new file mode 100644
index 000000000..0500d351e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpblendw-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 20
+
+#undef MASK
+#define MASK 0xfe
+
+static void
+init_pblendw (short *src1, short *src2, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 16; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      src2[i] = (i + seed + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pblendw (short *src1, short *src2, unsigned int mask, short *dst)
+{
+  int i;
+
+  memcpy (dst, src1, 32);
+  for (i = 0; i < 16; i++)
+    if (mask & (1 << (i % 8)))
+      dst[i] = src2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w src1, src2, dst;
+  short dst_ref[16];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pblendw (src1.a, src2.a, i);
+
+      dst.x = _mm256_blend_epi16 (src1.x, src2.x, MASK);
+      calc_pblendw (src1.a, src2.a, MASK, dst_ref);
+
+      if (check_union256i_w (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c
new file mode 100644
index 000000000..14b9a7c09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastb\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_broadcastb_epi8 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c
new file mode 100644
index 000000000..927755b2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb128-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_pbroadcastb128 (char *src, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 16; i++)
+    {
+      src[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pbroadcastb128 (char *src, char *dst)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    dst[i] = src[0];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_b src, dst;
+  char dst_ref[16];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pbroadcastb128 (src.a, i);
+
+      dst.x = _mm_broadcastb_epi8 (src.x);
+      calc_pbroadcastb128 (src.a, dst_ref);
+
+      if (check_union128i_b (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c
new file mode 100644
index 000000000..8e1247aac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i y;
+
+void extern
+avx2_test (void)
+{
+  y = _mm256_broadcastb_epi8 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c
new file mode 100644
index 000000000..9b0e56469
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastb256-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_pbroadcastb256 (char *src, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 16; i++)
+    {
+      src[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pbroadcastb256 (char *src, char *dst)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    dst[i] = src[0];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_b src;
+  union256i_b dst;
+  char dst_ref[32];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pbroadcastb256 (src.a, i);
+
+      dst.x = _mm256_broadcastb_epi8 (src.x);
+      calc_pbroadcastb256 (src.a, dst_ref);
+
+      if (check_union256i_b (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c
new file mode 100644
index 000000000..8a396678e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_broadcastd_epi32 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c
new file mode 100644
index 000000000..c9d2b46d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd128-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_pbroadcastd128 (int *src, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 4; i++)
+    {
+      src[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pbroadcastd128 (int *src, int *dst)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    dst[i] = src[0];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_d src, dst;
+  int dst_ref[4];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pbroadcastd128 (src.a, i);
+
+      dst.x = _mm_broadcastd_epi32 (src.x);
+      calc_pbroadcastd128 (src.a, dst_ref);
+
+      if (check_union128i_d (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c
new file mode 100644
index 000000000..57f1bc78e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i y;
+
+void extern
+avx2_test (void)
+{
+  y = _mm256_broadcastd_epi32 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c
new file mode 100644
index 000000000..fe009da1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastd256-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_pbroadcastd256 (int *src, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 4; i++)
+    {
+      src[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pbroadcastd256 (int *src, int *dst)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    dst[i] = src[0];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_d src;
+  union256i_d dst;
+  int dst_ref[8];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pbroadcastd256 (src.a, i);
+
+      dst.x = _mm256_broadcastd_epi32 (src.x);
+      calc_pbroadcastd256 (src.a, dst_ref);
+
+      if (check_union256i_d (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c
new file mode 100644
index 000000000..6714ae7ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_broadcastq_epi64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c
new file mode 100644
index 000000000..e6446de7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq128-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_pbroadcastq128 (long long int *src, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 2; i++)
+    {
+      src[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pbroadcastq128 (long long int *src, long long int *dst)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    dst[i] = src[0];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_q src, dst;
+  long long int dst_ref[2];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pbroadcastq128 (src.a, i);
+
+      dst.x = _mm_broadcastq_epi64 (src.x);
+      calc_pbroadcastq128 (src.a, dst_ref);
+
+      if (check_union128i_q (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c
new file mode 100644
index 000000000..bf1532b1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i y;
+
+void extern
+avx2_test (void)
+{
+  y = _mm256_broadcastq_epi64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c
new file mode 100644
index 000000000..470263156
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastq256-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_pbroadcastq256 (long long int *src, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 2; i++)
+    {
+      src[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pbroadcastq256 (long long int *src, long long int *dst)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    dst[i] = src[0];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_q src;
+  union256i_q dst;
+  long long int dst_ref[4];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pbroadcastq256 (src.a, i);
+
+      dst.x = _mm256_broadcastq_epi64 (src.x);
+      calc_pbroadcastq256 (src.a, dst_ref);
+
+      if (check_union256i_q (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c
new file mode 100644
index 000000000..ff5ee8741
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_broadcastw_epi16 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c
new file mode 100644
index 000000000..e8673a9dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw128-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_pbroadcastw128 (short *src, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 8; i++)
+    {
+      src[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pbroadcastw128 (short *src, short *dst)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    dst[i] = src[0];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_w src, dst;
+  short dst_ref[8];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pbroadcastw128 (src.a, i);
+
+      dst.x = _mm_broadcastw_epi16 (src.x);
+      calc_pbroadcastw128 (src.a, dst_ref);
+
+      if (check_union128i_w (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c
new file mode 100644
index 000000000..14462a19b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i y;
+
+void extern
+avx2_test (void)
+{
+  y = _mm256_broadcastw_epi16 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c
new file mode 100644
index 000000000..bac748fef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpbroadcastw256-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_pbroadcastw256 (short *src, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 8; i++)
+    {
+      src[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_pbroadcastw256 (short *src, short *dst)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    dst[i] = src[0];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_w src;
+  union256i_w dst;
+  short dst_ref[16];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_pbroadcastw256 (src.a, i);
+
+      dst.x = _mm256_broadcastw_epi16 (src.x);
+      calc_pbroadcastw256 (src.a, dst_ref);
+
+      if (check_union256i_w (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c
new file mode 100644
index 000000000..063cb5750
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpcmpeqb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_cmpeq_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c
new file mode 100644
index 000000000..87a8fa42c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqb-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  char e[32];
+  int i;
+
+  s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100,
+			  -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98,
+			  76, -100, -34, -78, -39, 6, 3, 25, 5, 119);
+
+  s2.x = _mm256_set_epi8 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78,
+			  -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20,
+			  30, 90, -80, -40, -100, -15, 98, 25, 98, 7);
+
+  u.x = _mm256_cmpeq_epi8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0;
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c
new file mode 100644
index 000000000..002b69686
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpcmpeqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_cmpeq_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c
new file mode 100644
index 000000000..0cc10458f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqd-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_d u, s1, s2;
+  int e[8];
+  int i;
+
+  s1.x = _mm256_set_epi32 (1, 2, 3, 4, 10, 20, 30, 90000);
+
+  s2.x = _mm256_set_epi32 (88, 44, 3, 22, 11, 98, 76, -100);
+
+  u.x = _mm256_cmpeq_epi32 (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0;
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c
new file mode 100644
index 000000000..196e3c311
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpcmpeqq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_cmpeq_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c
new file mode 100644
index 000000000..4abe78198
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqq-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_q u, s1, s2;
+  long long int e[4];
+  int i;
+
+  s1.x = _mm256_set_epi64x (1, 2, 3, 4);
+
+  s2.x = _mm256_set_epi64x (88, 44, 3, 220000);
+
+  u.x = _mm256_cmpeq_epi64 (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0;
+
+  if (check_union256i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c
new file mode 100644
index 000000000..1efa29143
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpcmpeqw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_cmpeq_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c
new file mode 100644
index 000000000..9fb38de2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpeqw-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_w u, s1, s2;
+  short e[16];
+  int i;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100,
+			   76, -100, -34, -78, -31000);
+
+  s2.x = _mm256_set_epi16 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78,
+			   30, 90, -80, -40, -100, -15);
+
+  u.x = _mm256_cmpeq_epi16 (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    e[i] = (s1.a[i] == s2.a[i]) ? -1 : 0;
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c
new file mode 100644
index 000000000..d8b35bba7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpcmpgtb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_cmpgt_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c
new file mode 100644
index 000000000..b76077c20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtb-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  char e[32];
+  int i;
+
+  s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100,
+			  -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98,
+			  76, -100, -34, -78, -39, 6, 3, 25, 5, 119);
+
+  s2.x = _mm256_set_epi8 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78,
+			  -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20,
+			  30, 90, -80, -40, -100, -15, 98, 25, 98, 7);
+
+  u.x = _mm256_cmpgt_epi8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0;
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c
new file mode 100644
index 000000000..75e4b24e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpcmpgtd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_cmpgt_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c
new file mode 100644
index 000000000..371bd79fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtd-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_d u, s1, s2;
+  int e[8];
+  int i;
+
+  s1.x = _mm256_set_epi32 (1, 2, 3, 4, 10, 20, 30, 90000);
+
+  s2.x = _mm256_set_epi32 (88, 44, 3, 22, 11, 98, 76, -100);
+
+  u.x = _mm256_cmpgt_epi32 (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0;
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c
new file mode 100644
index 000000000..7a983808b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpcmpgtq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_cmpgt_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c
new file mode 100644
index 000000000..8d5cf3ee8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtq-2.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_q u, s1, s2;
+  long long int e[4];
+  int i;
+
+  s1.x = _mm256_set_epi64x (1, 2, 3, 4);
+
+  s2.x = _mm256_set_epi64x (88, 44, 3, 220000);
+
+  u.x = _mm256_cmpgt_epi64 (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0;
+
+  if (check_union256i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c
new file mode 100644
index 000000000..f2ed47298
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpcmpgtw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_cmpgt_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c
new file mode 100644
index 000000000..490878f8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpcmpgtw-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_w u, s1, s2;
+  short e[16];
+  int i;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100,
+			   76, -100, -34, -78, -31000);
+
+  s2.x = _mm256_set_epi16 (88, 44, 3, 22, 11, 98, 76, -100, -34, -78,
+			   30, 90, -80, -40, -100, -15);
+
+  u.x = _mm256_cmpgt_epi16 (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    e[i] = (s1.a[i] > s2.a[i]) ? -1 : 0;
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c
new file mode 100644
index 000000000..518ff333b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vperm2i128\[ \\t\]+\[^\n\]*" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_permute2x128_si256 (x, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c
new file mode 100644
index 000000000..96f32b8f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vperm2i128-2.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+#define MASK 0xf1
+
+static void
+init_perm2i128 (unsigned long long *src1, unsigned long long *src2, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 4; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      src2[i] = (i + seed) * seed * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_perm2i128 (unsigned long long *src1,
+		unsigned long long *src2,
+		unsigned int mask, unsigned long long *dst)
+{
+  int i, temp;
+
+  temp = mask & 3;
+
+  switch (temp)
+    {
+    case 0:
+      memcpy (dst, src1, 16);
+    case 1:
+      memcpy (dst, src1 + 2, 16);
+    case 2:
+      memcpy (dst, src2, 16);
+    case 3:
+      memcpy (dst, src1 + 2, 16);
+    }
+
+  temp = (mask >> 4) & 3;
+
+  switch (temp)
+    {
+    case 0:
+      memcpy (dst + 2, src1, 16);
+    case 1:
+      memcpy (dst + 2, src1 + 2, 16);
+    case 2:
+      memcpy (dst + 2, src2, 16);
+    case 3:
+      memcpy (dst + 2, src1 + 2, 16);
+    }
+
+  if ((mask >> 3) & 1)
+    memset (dst, 0, 16);
+
+  if ((mask >> 7) & 1)
+    memset (dst + 2, 0, 16);
+}
+
+static void
+avx2_test (void)
+{
+  union256i_q src1, src2, dst;
+  unsigned long long dst_ref[4];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_perm2i128 (src1.a, src2.a, i);
+
+      dst.x = _mm256_permute2x128_si256 (src1.x, src2.x, MASK);
+      calc_perm2i128 (src1.a, src2.a, MASK, dst_ref);
+
+      if (check_union256i_q (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c
new file mode 100644
index 000000000..939f33895
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpermd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_permutevar8x32_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c
new file mode 100644
index 000000000..a663337e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_permd (int *src1, int *src2, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 8; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      src2[i] = (i + seed + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_permd (int *src1, int *src2, int *dst)
+{
+  int i;
+  unsigned temp;
+
+  memcpy (dst, src1, 32);
+  for (i = 0; i < 8; i++)
+    {
+      temp = src2[i];
+      dst[i] = src1[temp & 7];
+    }
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d src1, src2, dst;
+  int dst_ref[8];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_permd (src1.a, src2.a, i);
+
+      dst.x = _mm256_permutevar8x32_epi32 (src1.x, src2.x);
+      calc_permd (src1.a, src2.a, dst_ref);
+
+      if (check_union256i_d (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c
new file mode 100644
index 000000000..62ca67cc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermpd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpermpd\[ \\t\]+\[^\n\]*" } } */
+
+#include <immintrin.h>
+
+__m256d x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_permute4x64_pd (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c
new file mode 100644
index 000000000..1097e5cd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define MASK 0x1a
+
+#define NUM 10
+
+static void
+init_permpd (double *src1, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 4; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_permpd (double *src1, int mask, double *dst)
+{
+  int i;
+  unsigned temp;
+
+  memcpy (dst, src1, 32);
+  for (i = 0; i < 4; i++)
+    {
+      temp = mask >> (i * 2);
+      dst[i] = src1[temp & 3];
+    }
+}
+
+static void
+avx2_test (void)
+{
+  union256d src1, dst;
+  double dst_ref[4];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_permpd (src1.a, i);
+
+      dst.x = _mm256_permute4x64_pd (src1.x, MASK);
+      calc_permpd (src1.a, MASK, dst_ref);
+
+      if (check_union256d (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c
new file mode 100644
index 000000000..bf436599d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermps-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpermps\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m256 x;
+__m256i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_permutevar8x32_ps (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c
new file mode 100644
index 000000000..4190189a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermps-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+static void
+init_permps (float *src1, int *src2, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 8; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      src2[i] = (i + seed + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_permps (float *src1, int *src2, float *dst)
+{
+  int i;
+  unsigned temp;
+
+  memcpy (dst, src1, 32);
+  for (i = 0; i < 8; i++)
+    {
+      temp = src2[i];
+      dst[i] = src1[temp & 7];
+    }
+}
+
+static void
+avx2_test (void)
+{
+  union256 src1, dst;
+  union256i_d src2;
+  float dst_ref[8];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_permps (src1.a, src2.a, i);
+
+      dst.x = _mm256_permutevar8x32_ps (src1.x, src2.x);
+      calc_permps (src1.a, src2.a, dst_ref);
+
+      if (check_union256 (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c
new file mode 100644
index 000000000..533af89a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpermq\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_permute4x64_epi64 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c
new file mode 100644
index 000000000..2d8c34402
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpermq-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include <string.h>
+
+#define NUM 10
+
+#define MASK 0xf1
+
+static void
+init_permq (unsigned long long *src1, int seed)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < 4; i++)
+    {
+      src1[i] = (i + seed) * (i + seed) * sign;
+      sign = -sign;
+    }
+}
+
+static void
+calc_permq (unsigned long long *src1, unsigned int mask,
+	    unsigned long long *dst)
+{
+  int i, temp;
+
+  for (i = 0; i < 4; i++)
+    {
+      temp = (mask >> (2 * i)) & 3;
+      dst[i] = src1[temp];
+    }
+}
+
+static void
+avx2_test (void)
+{
+  union256i_q src1, dst;
+  unsigned long long dst_ref[4];
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      init_permq (src1.a, i);
+
+      dst.x = _mm256_permute4x64_epi64 (src1.x, MASK);
+      calc_permq (src1.a, MASK, dst_ref);
+
+      if (check_union256i_q (dst, dst_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c
new file mode 100644
index 000000000..2fb0fd7f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vphaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_hadd_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c
new file mode 100644
index 000000000..0d686cb4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddd-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include "ssse3-vals.h"
+
+static void
+compute_phaddd256 (int *i1, int *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    r[i + 0] = i1[2 * i] + i1[2 * i + 1];
+
+  for (i = 0; i < 2; i++)
+    r[i + 2] = i2[2 * i] + i2[2 * i + 1];
+
+  for (i = 0; i < 2; i++)
+    r[i + 4] = i1[2 * i + 4] + i1[2 * i + 5];
+
+  for (i = 0; i < 2; i++)
+    r[i + 6] = i2[2 * i + 4] + i2[2 * i + 5];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+
+  for (i = 0; i < 256; i += 16)
+    {
+      s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+      s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]);
+
+      res.x = _mm256_hadd_epi32 (s1.x, s2.x);
+
+      compute_phaddd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c
new file mode 100644
index 000000000..dbedf69de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vphaddsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_hadds_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c
new file mode 100644
index 000000000..371984776
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddsw-2.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include "ssse3-vals.h"
+
+static short
+signed_saturate_to_word (int x)
+{
+  if (x > (int) 0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short) x;
+}
+
+static void
+compute_phaddsw256 (short *i1, short *i2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i + 0] = signed_saturate_to_word (i1[2 * i] + i1[2 * i + 1]);
+
+  for (i = 0; i < 4; i++)
+    r[i + 4] = signed_saturate_to_word (i2[2 * i] + i2[2 * i + 1]);
+
+  for (i = 0; i < 4; i++)
+    r[i + 8] = signed_saturate_to_word (i1[2 * i + 8] + i1[2 * i + 9]);
+
+  for (i = 0; i < 4; i++)
+    r[i + 12] = signed_saturate_to_word (i2[2 * i + 8] + i2[2 * i + 9]);
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+
+  for (i = 0; i < 256; i += 16)
+    {
+      s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+      s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]);
+
+      res.x = _mm256_hadds_epi16 (s1.x, s2.x);
+
+      compute_phaddsw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c
new file mode 100644
index 000000000..c0bdac2f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vphaddw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_hadd_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c
new file mode 100644
index 000000000..8811e99d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphaddw-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include "ssse3-vals.h"
+
+static void
+compute_phaddw256 (short *i1, short *i2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i + 0] = i1[2 * i] + i1[2 * i + 1];
+
+  for (i = 0; i < 4; i++)
+    r[i + 4] = i2[2 * i] + i2[2 * i + 1];
+
+  for (i = 0; i < 4; i++)
+    r[i + 8] = i1[2 * i + 8] + i1[2 * i + 9];
+
+  for (i = 0; i < 4; i++)
+    r[i + 12] = i2[2 * i + 8] + i2[2 * i + 9];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 16)
+    {
+      s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+      s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]);
+
+      res.x = _mm256_hadd_epi16 (s1.x, s2.x);
+
+      compute_phaddw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c
new file mode 100644
index 000000000..d4ede9db0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vphsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_hsub_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c
new file mode 100644
index 000000000..ba4936792
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubd-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include "ssse3-vals.h"
+
+static void
+compute_phsubd256 (int *i1, int *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    r[i + 0] = i1[2 * i] - i1[2 * i + 1];
+
+  for (i = 0; i < 2; i++)
+    r[i + 2] = i2[2 * i] - i2[2 * i + 1];
+
+  for (i = 0; i < 2; i++)
+    r[i + 4] = i1[2 * i + 4] - i1[2 * i + 5];
+
+  for (i = 0; i < 2; i++)
+    r[i + 6] = i2[2 * i + 4] - i2[2 * i + 5];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+
+  for (i = 0; i < 256; i += 16)
+    {
+      s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+      s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]);
+
+      res.x = _mm256_hsub_epi32 (s1.x, s2.x);
+
+      compute_phsubd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c
new file mode 100644
index 000000000..d941f44b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vphsubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_hsubs_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c
new file mode 100644
index 000000000..1ed099090
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubsw-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include "ssse3-vals.h"
+
+static short
+signed_saturate_to_word (int x)
+{
+  if (x > (int) 0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short) x;
+}
+
+static void
+compute_phsubsw256 (short *i1, short *i2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i + 0] = signed_saturate_to_word (i1[2 * i] - i1[2 * i + 1]);
+
+  for (i = 0; i < 4; i++)
+    r[i + 4] = signed_saturate_to_word (i2[2 * i] - i2[2 * i + 1]);
+
+  for (i = 0; i < 4; i++)
+    r[i + 8] = signed_saturate_to_word (i1[2 * i + 8] - i1[2 * i + 9]);
+
+  for (i = 0; i < 4; i++)
+    r[i + 12] = signed_saturate_to_word (i2[2 * i + 8] - i2[2 * i + 9]);
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 16)
+    {
+      s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+      s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]);
+
+      res.x = _mm256_hsubs_epi16 (s1.x, s2.x);
+
+      compute_phsubsw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c
new file mode 100644
index 000000000..f336fad48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vphsubw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vphsubw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_hsub_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c
new file mode 100644
index 000000000..6ab19103d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaddubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_maddubs_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c
new file mode 100644
index 000000000..5761d8f44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddubsw-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include "ssse3-vals.h"
+
+static short
+signed_saturate_to_word (int x)
+{
+  if (x > (int) 0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short) x;
+}
+
+static void
+compute_pmaddubsw256 (short *i1, short *i2, short *r)
+{
+  unsigned char *ub1 = (unsigned char *) i1;
+  char *sb2 = (char *) i2;
+  short *sout = (short *) r;
+  int t0;
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      t0 = ((int) ub1[2 * i] * (int) sb2[2 * i] +
+	    (int) ub1[2 * i + 1] * (int) sb2[2 * i + 1]);
+      sout[i] = signed_saturate_to_word (t0);
+    }
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 16)
+    {
+      s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+      s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]);
+
+      res.x = _mm256_maddubs_epi16 (s1.x, s2.x);
+
+      compute_pmaddubsw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c
new file mode 100644
index 000000000..97de707ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaddwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_madd_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c
new file mode 100644
index 000000000..d539d3943
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaddwd-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+#include "ssse3-vals.h"
+
+static void
+compute_pmaddwd256 (short *i1, short *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = ((int) i1[2 * i] * (int) i2[2 * i] +
+	    (int) i1[2 * i + 1] * (int) i2[2 * i + 1]);
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2;
+  union256i_d res;
+  int res_ref[8];
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 16)
+    {
+      s1.x = _mm256_loadu_si256 ((__m256i *) & vals[i]);
+      s2.x = _mm256_loadu_si256 ((__m256i *) & vals[i + 8]);
+
+      res.x = _mm256_madd_epi16 (s1.x, s2.x);
+
+      compute_pmaddwd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c
new file mode 100644
index 000000000..917de5136
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+int *y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_maskload_epi32 (y, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c
new file mode 100644
index 000000000..9bc3f31be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+#ifndef MASK
+#define MASK 134
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx2_test (void)
+{
+  int i;
+  int m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) };
+  int s[4] = { 1, 2, 3, 4 };
+  union128i_d u, mask;
+  int e[4] = { 0 };
+
+  mask.x = _mm_loadu_si128 ((__m128i *) m);
+  u.x = _mm_maskload_epi32 (s, mask.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = m[i] ? s[i] : 0;
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c
new file mode 100644
index 000000000..aa9438c93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+int *y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_maskload_epi32 (y, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c
new file mode 100644
index 000000000..b5a82bddd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadd256-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+#ifndef MASK
+#define MASK 134
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx2_test (void)
+{
+  int i;
+  int m[8] =
+    { mask_v (0), mask_v (1), mask_v (2), mask_v (3), mask_v (4), mask_v (5),
+mask_v (6), mask_v (7) };
+  int s[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+  union256i_d u, mask;
+  int e[8] = { 0 };
+
+  mask.x = _mm256_loadu_si256 ((__m256i *) m);
+  u.x = _mm256_maskload_epi32 (s, mask.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = m[i] ? s[i] : 0;
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c
new file mode 100644
index 000000000..24768b8f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+long long int *y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_maskload_epi64 (y, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c
new file mode 100644
index 000000000..ca7abadca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+#ifndef MASK
+#define MASK 7
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx2_test (void)
+{
+  int i;
+  long long m[2] = { mask_v (0), mask_v (1) };
+  long long s[2] = { 1, 2 };
+  union128i_q u, mask;
+  long long e[2] = { 0 };
+
+  mask.x = _mm_loadu_si128 ((__m128i *) m);
+  u.x = _mm_maskload_epi64 (s, mask.x);
+
+  for (i = 0; i < 2; i++)
+    e[i] = m[i] ? s[i] : 0;
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c
new file mode 100644
index 000000000..9b824eb57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+long long int *y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_maskload_epi64 (y, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c
new file mode 100644
index 000000000..c74d15304
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskloadq256-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+#ifndef MASK
+#define MASK 7
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx2_test (void)
+{
+  int i;
+  long long m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) };
+  long long s[4] = { 1, 2, 3, 4 };
+  union256i_q u, mask;
+  long long e[4] = { 0 };
+
+  mask.x = _mm256_loadu_si256 ((__m256i *) m);
+  u.x = _mm256_maskload_epi64 (s, mask.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = m[i] ? s[i] : 0;
+
+  if (check_union256i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c
new file mode 100644
index 000000000..0731d1ae1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+int *y;
+
+void extern
+avx2_test (void)
+{
+  _mm_maskstore_epi32 (y, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c
new file mode 100644
index 000000000..89b54f594
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+#ifndef MASK
+#define MASK 214
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx2_test (void)
+{
+  int i;
+  int m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) };
+  int s[4] = { 1, 2, 3, 4 };
+  union128i_d src, mask;
+  int e[4] = { 0 };
+  int d[4] = { 0 };
+
+  src.x = _mm_loadu_si128 ((__m128i *) s);
+  mask.x = _mm_loadu_si128 ((__m128i *) m);
+  _mm_maskstore_epi32 (d, mask.x, src.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = m[i] ? s[i] : 0;
+
+  if (checkVi (d, e, 4))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c
new file mode 100644
index 000000000..4e2944de0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaskmovd\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+int *y;
+
+void extern
+avx2_test (void)
+{
+  _mm256_maskstore_epi32 (y, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c
new file mode 100644
index 000000000..7b66a0897
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstored256-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+#ifndef MASK
+#define MASK 214
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
+
+void static
+avx2_test (void)
+{
+  int i;
+  int m[8] =
+    { mask_v (0), mask_v (1), mask_v (2), mask_v (3), mask_v (4), mask_v (5),
+mask_v (6), mask_v (7) };
+  int s[8] = { 1, 2, 3, 4, 5, 6, 7, 8 };
+  union256i_d src, mask;
+  int e[8] = { 0 };
+  int d[8] = { 0 };
+
+  src.x = _mm256_loadu_si256 ((__m256i *) s);
+  mask.x = _mm256_loadu_si256 ((__m256i *) m);
+  _mm256_maskstore_epi32 (d, mask.x, src.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = m[i] ? s[i] : 0;
+
+  if (checkVi (d, e, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c
new file mode 100644
index 000000000..f1075bf25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+long long int *y;
+
+void extern
+avx2_test (void)
+{
+  _mm_maskstore_epi64 (y, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c
new file mode 100644
index 000000000..bd9e39470
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+#ifndef MASK
+#define MASK 6
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx2_test (void)
+{
+  int i;
+  long long m[2] = { mask_v (0), mask_v (1) };
+  long long s[2] = { 1, 2 };
+  long long e[2] = { 0 };
+  long long d[2] = { 0 };
+  union128i_q src, mask;
+
+  src.x = _mm_loadu_si128 ((__m128i *) s);
+  mask.x = _mm_loadu_si128 ((__m128i *) m);
+  _mm_maskstore_epi64 (d, mask.x, src.x);
+
+  for (i = 0; i < 2; i++)
+    e[i] = m[i] ? s[i] : 0;
+
+  if (checkVl (d, e, 2))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c
new file mode 100644
index 000000000..0d0520b81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaskmovq\[ \\t\]+\[^\n\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+long long int *y;
+
+void extern
+avx2_test (void)
+{
+  _mm256_maskstore_epi64 (y, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c
new file mode 100644
index 000000000..091791ac6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaskstoreq256-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+#ifndef MASK
+#define MASK 6
+#endif
+
+#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
+
+void static
+avx2_test (void)
+{
+  int i;
+  long long m[4] = { mask_v (0), mask_v (1), mask_v (2), mask_v (3) };
+  long long s[4] = { 1, 2, 3, 4 };
+  long long e[4] = { 0 };
+  long long d[4] = { 0 };
+  union256i_q src, mask;
+
+  src.x = _mm256_loadu_si256 ((__m256i *) s);
+  mask.x = _mm256_loadu_si256 ((__m256i *) m);
+  _mm256_maskstore_epi64 (d, mask.x, src.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = m[i] ? s[i] : 0;
+
+  if (checkVl (d, e, 4))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c
new file mode 100644
index 000000000..2cbbcff9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaxsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_max_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c
new file mode 100644
index 000000000..4b1b1dd2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsb-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmaxsb256 (char *s1, char *s2, char *r)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    r[i] = s1[i] > s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_b s1, s2, res;
+  char res_ref[32];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (i + 20) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_max_epi8 (s1.x, s2.x);
+
+      compute_pmaxsb256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c
new file mode 100644
index 000000000..1b227e614
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaxsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_max_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c
new file mode 100644
index 000000000..e488a6ea1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsd-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmaxsd256 (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = s1[i] > s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (i + 2000) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_max_epi32 (s1.x, s2.x);
+
+      compute_pmaxsd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c
new file mode 100644
index 000000000..8fb2d29cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaxsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_max_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c
new file mode 100644
index 000000000..6ada1cd23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxsw-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmaxsw256 (short *s1, short *s2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = s1[i] > s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (i + 2000) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_max_epi16 (s1.x, s2.x);
+
+      compute_pmaxsw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c
new file mode 100644
index 000000000..6d0fe9828
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaxub\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_max_epu8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c
new file mode 100644
index 000000000..f0654e032
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxub-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmaxub256 (unsigned char *s1, unsigned char *s2, unsigned char *r)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    r[i] = s1[i] > s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_b s1, s2, res;
+  unsigned char res_ref[32];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = i + 200;
+	}
+
+      res.x = _mm256_max_epu8 (s1.x, s2.x);
+
+      compute_pmaxub256 ((unsigned char *) s1.a,
+			 (unsigned char *) s2.a, (unsigned char *) res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c
new file mode 100644
index 000000000..5784148c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaxud\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_max_epu32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c
new file mode 100644
index 000000000..a61314d19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxud-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmaxud256 (unsigned int *s1, unsigned int *s2, unsigned int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = s1[i] > s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  unsigned int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = i + 2000;
+	}
+
+      res.x = _mm256_max_epu32 (s1.x, s2.x);
+
+      compute_pmaxud256 ((unsigned *) s1.a, (unsigned *) s2.a,
+			 (unsigned *) res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c
new file mode 100644
index 000000000..dbadc254c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmaxuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_max_epu16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c
new file mode 100644
index 000000000..2631f0cf0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmaxuw-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmaxuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = s1[i] > s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  unsigned short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = i + 2000;
+	}
+
+      res.x = _mm256_max_epu16 (s1.x, s2.x);
+
+      compute_pmaxuw256 ((unsigned short *) s1.a,
+			 (unsigned short *) s2.a, (unsigned short *) res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c
new file mode 100644
index 000000000..35cbdb312
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpminsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_min_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c
new file mode 100644
index 000000000..2dc5b109f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsb-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pminsb256 (char *s1, char *s2, char *r)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    r[i] = s1[i] < s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_b s1, s2, res;
+  char res_ref[32];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (i + 20) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_min_epi8 (s1.x, s2.x);
+
+      compute_pminsb256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c
new file mode 100644
index 000000000..97c99f24c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpminsd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_min_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c
new file mode 100644
index 000000000..e2c69e7e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsd-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pminsd256 (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = s1[i] < s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (i + 2000) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_min_epi32 (s1.x, s2.x);
+
+      compute_pminsd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c
new file mode 100644
index 000000000..43f5c72ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpminsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_min_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c
new file mode 100644
index 000000000..05be8ce90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminsw-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pminsw256 (short *s1, short *s2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = s1[i] < s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (i + 2000) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_min_epi16 (s1.x, s2.x);
+
+      compute_pminsw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c
new file mode 100644
index 000000000..44663e8ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminub-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpminub\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_min_epu8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c
new file mode 100644
index 000000000..16c5f7628
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminub-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pminub256 (unsigned char *s1, unsigned char *s2, unsigned char *r)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    r[i] = s1[i] < s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_b s1, s2, res;
+  unsigned char res_ref[32];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = i + 200;
+	}
+
+      res.x = _mm256_min_epu8 (s1.x, s2.x);
+
+      compute_pminub256 ((unsigned char *) s1.a,
+			 (unsigned char *) s2.a, (unsigned char *) res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c
new file mode 100644
index 000000000..d6acb8b47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminud-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpminud\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_min_epu32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c
new file mode 100644
index 000000000..97ff74226
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminud-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pminud256 (unsigned int *s1, unsigned int *s2, unsigned int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = s1[i] < s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  unsigned int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = i + 2000;
+	}
+
+      res.x = _mm256_min_epu32 (s1.x, s2.x);
+
+      compute_pminud256 ((unsigned *) s1.a, (unsigned *) s2.a,
+			 (unsigned *) res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c
new file mode 100644
index 000000000..c018a49c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminuw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpminuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_min_epu16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c
new file mode 100644
index 000000000..7de87d00d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpminuw-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pminuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = s1[i] < s2[i] ? s1[i] : s2[i];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  unsigned short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = i + 2000;
+	}
+
+      res.x = _mm256_min_epu16 (s1.x, s2.x);
+
+      compute_pminuw256 ((unsigned short *) s1.a,
+			 (unsigned short *) s2.a, (unsigned short *) res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c
new file mode 100644
index 000000000..1a37b1bef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovmskb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+int res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_movemask_epi8 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c
new file mode 100644
index 000000000..e5a9c10e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovmskb-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovmskb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include "avx2-check.h"
+
+static void
+avx2_test (void)
+{
+  union256i_b s;
+  int res, res_ref;
+  int i, e = 0;
+
+  s.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100,
+			 15, 98, 25, 98, 7, 1, 2, 3, 4, 10, 20, 30, 90,
+			 -80, -40, -100, -15, 98, 25, 98, 7);
+
+  res = _mm256_movemask_epi8 (s.x);
+
+  for (i = 0; i < 32; i++)
+    if (s.a[i] & (1 << 7))
+      res_ref = res_ref | (1 << i);
+
+  if (res != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c
new file mode 100644
index 000000000..d438248b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovsxbd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepi8_epi32 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c
new file mode 100644
index 000000000..3b641b0ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbd-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movsxbd (char *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_b s;
+  union256i_d res;
+  int res_ref[8];
+
+  s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8);
+
+  res.x = _mm256_cvtepi8_epi32 (s.x);
+
+  compute_movsxbd (s.a, res_ref);
+
+  if (check_union256i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c
new file mode 100644
index 000000000..12c817ffb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovsxbq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepi8_epi64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c
new file mode 100644
index 000000000..23aae5bdb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbq-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movsxbq (char *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_b s;
+  union256i_q res;
+  long long int res_ref[4];
+
+  s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8);
+
+  res.x = _mm256_cvtepi8_epi64 (s.x);
+
+  compute_movsxbq (s.a, res_ref);
+
+  if (check_union256i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c
new file mode 100644
index 000000000..bf98e3154
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovsxbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepi8_epi16 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c
new file mode 100644
index 000000000..d1c02ea86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxbw-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movsxbw (char *s, short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_b s;
+  union256i_w res;
+  short res_ref[16];
+
+  s.x = _mm_set_epi8 (1, 2, 3, 4, 20, -50, 6, 8, 1, 2, 3, 4, -20, 5, 6, 8);
+
+  res.x = _mm256_cvtepi8_epi16 (s.x);
+
+  compute_movsxbw (s.a, res_ref);
+
+  if (check_union256i_w (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c
new file mode 100644
index 000000000..9c72c41e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovsxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepi32_epi64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c
new file mode 100644
index 000000000..7e87f316f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxdq-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movsxdq (int *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_d s;
+  union256i_q res;
+  long long int res_ref[4];
+
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+
+  res.x = _mm256_cvtepi32_epi64 (s.x);
+
+  compute_movsxdq (s.a, res_ref);
+
+  if (check_union256i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c
new file mode 100644
index 000000000..39627ced8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovsxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepi16_epi32 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c
new file mode 100644
index 000000000..5a95e376e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwd-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movsxwd (short *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_w s;
+  union256i_d res;
+  int res_ref[8];
+
+  s.x = _mm_set_epi16 (1, -2, 3, 4, 200, 5000, -6, 8);
+
+  res.x = _mm256_cvtepi16_epi32 (s.x);
+
+  compute_movsxwd (s.a, res_ref);
+
+  if (check_union256i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c
new file mode 100644
index 000000000..9fa613b34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovsxwq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepi16_epi64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c
new file mode 100644
index 000000000..f096de577
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovsxwq-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movsxwq (short *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_w s;
+  union256i_q res;
+  long long int res_ref[4];
+
+  s.x = _mm_set_epi16 (1, 2, 3, 4, -200, 50, 6, 8);
+
+  res.x = _mm256_cvtepi16_epi64 (s.x);
+
+  compute_movsxwq (s.a, res_ref);
+
+  if (check_union256i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c
new file mode 100644
index 000000000..bde8c134d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovzxbd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepu8_epi32 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c
new file mode 100644
index 000000000..7a212c89d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbd-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movzxbd (unsigned char *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_b s;
+  union256i_d res;
+  int res_ref[8];
+
+  s.x = _mm_set_epi8 (1, 2, 3, 4, 20, 50, 6, 8, 1, 2, 3, 4, 200, 5, 6, 8);
+
+  res.x = _mm256_cvtepu8_epi32 (s.x);
+
+  compute_movzxbd (s.a, res_ref);
+
+  if (check_union256i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c
new file mode 100644
index 000000000..da8e0584a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovzxbq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepu8_epi64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c
new file mode 100644
index 000000000..c09c21d67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbq-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movzxbq (unsigned char *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_b s;
+  union256i_q res;
+  long long int res_ref[4];
+
+  s.x = _mm_set_epi8 (1, 2, 3, 4, 20, 150, 6, 8, 1, 2, 3, 4, 20, 5, 6, 8);
+
+  res.x = _mm256_cvtepu8_epi64 (s.x);
+
+  compute_movzxbq (s.a, res_ref);
+
+  if (check_union256i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c
new file mode 100644
index 000000000..f7a926de1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovzxbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepu8_epi16 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c
new file mode 100644
index 000000000..5ef4b1535
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxbw-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movzxbw (unsigned char *s, short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_b s;
+  union256i_w res;
+  short res_ref[16];
+
+  s.x = _mm_set_epi8 (1, 2, 3, 4, 200, 50, 6, 8, 1, 2, 3, 4, 200, 5, 6, 8);
+
+  res.x = _mm256_cvtepu8_epi16 (s.x);
+
+  compute_movzxbw (s.a, res_ref);
+
+  if (check_union256i_w (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c
new file mode 100644
index 000000000..3f0c400c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovzxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepu32_epi64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c
new file mode 100644
index 000000000..20986b644
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxdq-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movzxdq (unsigned *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_d s;
+  union256i_q res;
+  long long int res_ref[4];
+
+  s.x = _mm_set_epi32 (1, 2, 3, 4);
+
+  res.x = _mm256_cvtepu32_epi64 (s.x);
+
+  compute_movzxdq (s.a, res_ref);
+
+  if (check_union256i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c
new file mode 100644
index 000000000..902cd6df8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovzxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepu16_epi32 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c
new file mode 100644
index 000000000..b4d2b2da6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwd-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movzxwd (unsigned short *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_w s;
+  union256i_d res;
+  int res_ref[8];
+
+  s.x = _mm_set_epi16 (1, 2, 3, 4, 200, 5000, 6, 8);
+
+  res.x = _mm256_cvtepu16_epi32 (s.x);
+
+  compute_movzxwd (s.a, res_ref);
+
+  if (check_union256i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c
new file mode 100644
index 000000000..4eaa65aeb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmovzxwq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+__m256i res;
+
+void extern
+avx2_test (void)
+{
+  res = _mm256_cvtepu16_epi64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c
new file mode 100644
index 000000000..8a9250aec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmovzxwq-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_movzxwq (unsigned short *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s[i];
+}
+
+static void
+avx2_test (void)
+{
+  union128i_w s;
+  union256i_q res;
+  long long int res_ref[4];
+
+  s.x = _mm_set_epi16 (1, 2, 3, 4, 200, 5000, 6, 8);
+
+  res.x = _mm256_cvtepu16_epi64 (s.x);
+
+  compute_movzxwq (s.a, res_ref);
+
+  if (check_union256i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c
new file mode 100644
index 000000000..e1c232da3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmuldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mul_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c
new file mode 100644
index 000000000..b67f25fc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuldq-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmuldq256 (int *s1, int *s2, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s1[i * 2] * s2[i * 2];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2;
+  union256i_q res;
+  long long int res_ref[4];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = i * j * sign;
+	  s2.a[j] = (j + 20) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_mul_epi32 (s1.x, s2.x);
+      compute_pmuldq256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c
new file mode 100644
index 000000000..7c6692b81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmulhrsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mulhrs_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c
new file mode 100644
index 000000000..c6d874222
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhrsw-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmulhrsw256 (short *s1, short *s2, short *r)
+{
+  int i;
+  int t0;
+
+  for (i = 0; i < 16; i++)
+    {
+      t0 = (((int) s1[i] * (int) s2[i]) >> 14) + 1;
+      r[i] = (short) (t0 >> 1);
+    }
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = i * j * sign;
+	  s2.a[j] = (j + 20) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_mulhrs_epi16 (s1.x, s2.x);
+
+      compute_pmulhrsw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c
new file mode 100644
index 000000000..d9a2fa7ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmulhuw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mulhi_epu16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c
new file mode 100644
index 000000000..734b20cfb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhuw-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmulhuw256 (unsigned short *s1, unsigned short *s2, unsigned short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = (s1[i] * s2[i]) >> 16;
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  unsigned short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = i * j;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_mulhi_epu16 (s1.x, s2.x);
+
+      compute_pmulhuw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c
new file mode 100644
index 000000000..a626f1919
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmulhw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mulhi_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c
new file mode 100644
index 000000000..ea0bde2be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulhw-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmulhw256 (short *s1, short *s2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = (s1[i] * s2[i]) >> 16;
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = i * j * sign;
+	  s2.a[j] = (j + 20) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_mulhi_epi16 (s1.x, s2.x);
+
+      compute_pmulhw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c
new file mode 100644
index 000000000..4e2e5250f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmulld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mullo_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c
new file mode 100644
index 000000000..74443a24d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmulld256 (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    r[i] = (int) ((long long int) s1[i] * (long long int) s2[i]);
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = i * j * sign;
+	  s2.a[j] = (j + 20) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_mullo_epi32 (s1.x, s2.x);
+
+      compute_pmulld256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c
new file mode 100644
index 000000000..b2d539ba4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE int
+#define BIN_OP(a, b) ((a) * (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpmulld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c
new file mode 100644
index 000000000..61cc75884
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmullw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mullo_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c
new file mode 100644
index 000000000..81d05ccab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmullw256 (short *s1, short *s2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    r[i] = (short) ((int) s1[i] * (int) s2[i]);
+}
+
+static void
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = i * j * sign;
+	  s2.a[j] = (j + 20) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_mullo_epi16 (s1.x, s2.x);
+
+      compute_pmullw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
new file mode 100644
index 000000000..46d173fc3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE short
+#define BIN_OP(a, b) ((a) * (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpmullw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c
new file mode 100644
index 000000000..4fa1bf155
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpmuludq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_mul_epu32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c
new file mode 100644
index 000000000..619b7358e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpmuludq-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+static void
+compute_pmuludq256 (unsigned int *s1, unsigned int *s2, unsigned long long *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s1[i * 2] * s2[i * 2];
+}
+
+static void
+avx2_test (void)
+{
+  union256i_d s1, s2;
+  union256i_q res;
+  unsigned long long res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = i * j;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_mul_epu32 (s1.x, s2.x);
+
+      compute_pmuludq256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h
new file mode 100644
index 000000000..204b11cb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpop-check.h
@@ -0,0 +1,55 @@
+#include "avx2-check.h"
+
+#define SIZE 256
+
+TYPE a[SIZE];
+TYPE b[SIZE];
+TYPE c[SIZE];
+volatile TYPE c_ref[SIZE];
+
+__attribute__ ((__noinline__))
+void
+gen_pop ()
+{
+  int i;
+  for (i = 0; i < SIZE; ++i)
+#ifdef BIN_OP
+    c[i] = BIN_OP (a[i], b[i]);
+#else /*  Must be UN_OP */
+    c[i] = UN_OP (a[i]);
+#endif /*  BIN_OP */
+}
+
+void
+check_pop ()
+{
+  int i;
+  for (i = 0; i < SIZE; ++i)
+#ifdef BIN_OP
+    c_ref[i] = BIN_OP (a[i], b[i]);
+#else /*  Must be UN_OP */
+    c_ref[i] = UN_OP (a[i]);
+#endif /*  BIN_OP */
+}
+
+void static
+avx2_test (void)
+{
+  int i, j;
+  for (i = 0; i < 4; ++i )
+    {
+      for ( j = 0; j < SIZE; ++j )
+	{
+	  a[i] = i * i + i;
+	  b[i] = i * i * i;
+	}
+
+      gen_pop ();
+      check_pop ();
+
+      /* We need to cast away volatility from c_ref here in order to eliminate
+	 warning if libc version of memcpy is used here.  */
+      if (memcmp (c, (void *) c_ref, SIZE * sizeof (TYPE)))
+	abort();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c
new file mode 100644
index 000000000..2e0f46d21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpor-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpor\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_or_si256 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c
new file mode 100644
index 000000000..fd5da8335
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpor-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include "avx2-check.h"
+
+static void
+compute_por256 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s1[i] | s2[i];
+}
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, s2, res;
+  long long int res_ref[4];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  s1.a[j] = i * j * sign;
+	  s2.a[j] = (j + 20) * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_or_si256 (s1.x, s2.x);
+      compute_por256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c
new file mode 100644
index 000000000..1cd56661c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsadbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sad_epu8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c
new file mode 100644
index 000000000..392613659
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsadbw-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_sadbw256 (unsigned char *s1, unsigned char *s2, unsigned short *r)
+{
+  int i;
+  unsigned char tmp[32];
+
+  for (i = 0; i < 32; i++)
+    tmp[i] = s1[i] > s2[i] ? s1[i] - s2[i] : s2[i] - s1[i];
+
+  memset (r, 0, 32);
+
+  for (i = 0; i < 8; i++)
+    r[0] += tmp[i];
+
+  for (i = 8; i < 16; i++)
+    r[4] += tmp[i];
+
+  for (i = 16; i < 24; i++)
+    r[8] += tmp[i];
+
+  for (i = 24; i < 32; i++)
+    r[12] += tmp[i];
+}
+
+void static
+avx2_test (void)
+{
+  union256i_b s1, s2;
+  union256i_w res;
+  unsigned short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_sad_epu8 (s1.x, s2.x);;
+      compute_sadbw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c
new file mode 100644
index 000000000..b94563d0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpshufb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_shuffle_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c
new file mode 100644
index 000000000..ee9149395
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufb-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_pshufb256 (char *s1, char *s2, char *r)
+{
+  int i;
+  char select;
+
+  for (i = 0; i < 16; i++)
+    {
+      select = s2[i];
+      if (select & 0x80)
+	r[i] = 0;
+      else
+	r[i] = s1[select & 0xf];
+
+      select = s2[i + 16];
+      if (select & 0x80)
+	r[i + 16] = 0;
+      else
+	r[i + 16] = s1[16 + (select & 0xf)];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_b s1, s2, res;
+  char res_ref[32];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_shuffle_epi8 (s1.x, s2.x);
+      compute_pshufb256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c
new file mode 100644
index 000000000..cdfde4654
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpshufd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_shuffle_epi32 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c
new file mode 100644
index 000000000..e799ed789
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufd-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0xec
+
+static void
+compute_pshufd256 (int *s1, unsigned char imm, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    r[i] = s1[((N & (0x3 << (2 * i))) >> (2 * i))];
+
+  for (i = 0; i < 4; i++)
+    r[i + 4] = s1[((N & (0x3 << (2 * i))) >> (2 * i)) + 4];
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, res;
+  int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_shuffle_epi32 (s1.x, N);
+      compute_pshufd256 (s1.a, N, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c
new file mode 100644
index 000000000..fa3f809da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpshufhw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_shufflehi_epi16 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c
new file mode 100644
index 000000000..a27ed03b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshufhw-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0xec
+
+static void
+compute_pshuflw256 (short *s1, unsigned char imm, short *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    {
+      r[i] = s1[(imm >> (2 * i)) & 3];
+      r[i + 8] = s1[((imm >> (2 * i)) & 3) + 8];
+    }
+
+  for (i = 4; i < 8; i++)
+    {
+      r[i] = s1[i];
+      r[i + 8] = s1[i + 8];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, res;
+  short res_ref[16];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 1; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_shufflelo_epi16 (s1.x, N);
+      compute_pshuflw256 (s1.a, N, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c
new file mode 100644
index 000000000..24e75625f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpshuflw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_shufflelo_epi16 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c
new file mode 100644
index 000000000..144197348
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpshuflw-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0xec
+
+static void
+compute_pshufhw256 (short *s1, unsigned char imm, short *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    {
+      r[i] = s1[i];
+      r[i + 8] = s1[i + 8];
+    }
+
+  for (i = 4; i < 8; i++)
+    {
+      r[i] = s1[((imm >> (2 * (i - 4))) & 3) + 4];
+      r[i + 8] = s1[((imm >> (2 * (i - 4))) & 3) + 12];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, res;
+  short res_ref[16];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 1; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_shufflehi_epi16 (s1.x, N);
+      compute_pshufhw256 (s1.a, N, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c
new file mode 100644
index 000000000..6cd7ca6e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsignb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sign_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c
new file mode 100644
index 000000000..5e3d819fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignb-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psignb256 (char *s1, char *s2, char *r)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    if (s2[i] < 0)
+      r[i] = -s1[i];
+    else if (s2[i] == 0)
+      r[i] = 0;
+    else
+      r[i] = s1[i];
+}
+
+void static
+avx2_test (void)
+{
+  union256i_b s1, s2, res;
+  char res_ref[32];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_sign_epi8 (s1.x, s2.x);
+      compute_psignb256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c
new file mode 100644
index 000000000..dab81a3b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsignd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sign_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c
new file mode 100644
index 000000000..14e61b014
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignd-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psignd256 (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    if (s2[i] < 0)
+      r[i] = -s1[i];
+    else if (s2[i] == 0)
+      r[i] = 0;
+    else
+      r[i] = s1[i];
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_sign_epi32 (s1.x, s2.x);
+      compute_psignd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c
new file mode 100644
index 000000000..cae04c081
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsignw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sign_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c
new file mode 100644
index 000000000..bb96a1d53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsignw-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psignw256 (short int *s1, short int *s2, short int *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    if (s2[i] < 0)
+      r[i] = -s1[i];
+    else if (s2[i] == 0)
+      r[i] = 0;
+    else
+      r[i] = s1[i];
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short int res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_sign_epi16 (s1.x, s2.x);
+      compute_psignw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c
new file mode 100644
index 000000000..5140d7ae0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslld-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpslld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sll_epi32 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c
new file mode 100644
index 000000000..84c68feb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslld-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_pslld256 (int *s1, long long int *s2, int *r)
+{
+  int i;
+  long long int count = s2[0];
+
+  memset (r, 0, 32);
+
+  if (count < 32)
+    for (i = 0; i < 8; ++i)
+      r[i] = s1[i] << count;
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, res;
+  union128i_q s2;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	s1.a[j] = j * i;
+
+      s2.a[0] = i;
+
+      res.x = _mm256_sll_epi32 (s1.x, s2.x);
+
+      compute_pslld256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c
new file mode 100644
index 000000000..9cea0f675
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldi-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpslld\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_slli_epi32 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c
new file mode 100644
index 000000000..dfd7d9a03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldi-2.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_pslldi256 (int *s1, int *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  if (N < 64)
+    for (i = 0; i < 8; ++i)
+      r[i] = s1[i] << N;
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, res;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_slli_epi32 (s1.x, N);
+
+      compute_pslldi256 (s1.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c
new file mode 100644
index 000000000..5a85a7982
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpslldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+extern volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_slli_si256 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c
new file mode 100644
index 000000000..7bfb5b185
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpslldq-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_pslldq256 (char *s1, char *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  for (i = 0; i < 16 - N; i++)
+    r[i + N] = s1[i];
+
+  for (i = 0; i < 16 - N; i++)
+    r[i + 16 + N] = s1[i + 16];
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_b s1, res;
+  char res_ref[32];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_slli_si256 (s1.x, N);
+
+      compute_pslldq256 (s1.a, res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c
new file mode 100644
index 000000000..53417a1ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsllq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sll_epi64 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c
new file mode 100644
index 000000000..c0ac89bfe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psllq256 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count = s2[0];
+
+  memset (r, 0, 32);
+
+  if (count < 64)
+    for (i = 0; i < 4; ++i)
+      r[i] = s1[i] << count;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, res;
+  union128i_q s2;
+  long long int res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	s1.a[j] = j * i;
+
+      s2.a[0] = i;
+
+      res.x = _mm256_sll_epi64 (s1.x, s2.x);
+
+      compute_psllq256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c
new file mode 100644
index 000000000..2851be5e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpsllq\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_slli_epi64 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c
new file mode 100644
index 000000000..9ef49bdb9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllqi-2.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_psllqi256 (long long int *s1, long long int *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  if (N < 64)
+    for (i = 0; i < 4; ++i)
+      r[i] = s1[i] << N;
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, res;
+  long long int res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_slli_epi64 (s1.x, N);
+
+      compute_psllqi256 (s1.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c
new file mode 100644
index 000000000..b57afc4af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsllvd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_sllv_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c
new file mode 100644
index 000000000..5ab83ae20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd128-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psllvd128 (int *s1, int *s2, int *r)
+{
+  int i, count;
+
+  for (i = 0; i < 4; ++i)
+    {
+      count = s2[i];
+      r[i] = s1[i] << count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union128i_d s1, s2, res;
+  int res_ref[4];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm_sllv_epi32 (s1.x, s2.x);
+
+      compute_psllvd128 (s1.a, s2.a, res_ref);
+
+      fail += check_union128i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c
new file mode 100644
index 000000000..59063d5c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsllvd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sllv_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c
new file mode 100644
index 000000000..407a8f3c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvd256-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psllvd256 (int *s1, int *s2, int *r)
+{
+  int i, count;
+
+  for (i = 0; i < 8; ++i)
+    {
+      count = s2[i];
+      r[i] = s1[i] << count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j, sign = 1;;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_sllv_epi32 (s1.x, s2.x);
+
+      compute_psllvd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c
new file mode 100644
index 000000000..245aa5508
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsllvq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_sllv_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c
new file mode 100644
index 000000000..422ddf5bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq128-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psllvq128 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count;
+
+  for (i = 0; i < 2; ++i)
+    {
+      count = s2[i];
+      r[i] = s1[i] << count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union128i_q s1, s2, res;
+  long long int res_ref[2];
+  int i, j, sign = 2;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm_sllv_epi64 (s1.x, s2.x);
+
+      compute_psllvq128 (s1.a, s2.a, res_ref);
+
+      fail += check_union128i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c
new file mode 100644
index 000000000..caae3f2fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsllvq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sllv_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c
new file mode 100644
index 000000000..c41597b16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllvq256-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psllvq256 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count;
+
+  for (i = 0; i < 4; ++i)
+    {
+      count = s2[i];
+      r[i] = s1[i] << count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, s2, res;
+  long long int res_ref[4];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_sllv_epi64 (s1.x, s2.x);
+
+      compute_psllvq256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c
new file mode 100644
index 000000000..2fbc43f48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllw-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsllw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sll_epi16 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c
new file mode 100644
index 000000000..1b26330dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllw-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psllw256 (short *s1, long long int *s2, short *r)
+{
+  int i;
+  int count = s2[0];
+
+  memset (r, 0, 32);
+
+  if (count < 16)
+    for (i = 0; i < 16; ++i)
+      r[i] = s1[i] << count;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, res;
+  union128i_q s2;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	s1.a[j] = j * i;
+
+      s2.a[0] = i;
+
+      res.x = _mm256_sll_epi16 (s1.x, s2.x);
+
+      compute_psllw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+
+      if (fail)
+	{
+	  for (j = 0; j < 16; ++j)
+	    printf ("%d <->%d\n", res.a[j], res_ref[j]);
+	  abort ();
+	}
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c
new file mode 100644
index 000000000..10bd08c34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpsllw\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_slli_epi16 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c
new file mode 100644
index 000000000..f1d3e1109
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsllwi-2.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_psllwi256 (short *s1, short *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  if (N < 16)
+    for (i = 0; i < 16; ++i)
+      r[i] = s1[i] << N;
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, res;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_slli_epi16 (s1.x, N);
+
+      compute_psllwi256 (s1.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c
new file mode 100644
index 000000000..673398e3d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrad\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sra_epi32 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c
new file mode 100644
index 000000000..39a579e4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psrad256 (int *s1, long long int *s2, int *r)
+{
+  int i;
+  long long int count = s2[0];
+
+  memset (r, 0, 32);
+
+  if (count < 32)
+    for (i = 0; i < 8; ++i)
+      r[i] = s1[i] >> count;
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, res;
+  union128i_q s2;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	s1.a[j] = j * i;
+
+      s2.a[0] = i;
+
+      res.x = _mm256_sra_epi32 (s1.x, s2.x);
+
+      compute_psrad256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c
new file mode 100644
index 000000000..97affb4bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE unsigned
+#define UN_OP(a) ((a) >> (5))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c
new file mode 100644
index 000000000..f6bb71a57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsradi-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpsrad\[ \\t\]+\[^\n\]*" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srai_epi32 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c
new file mode 100644
index 000000000..b9cfc7afa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsradi-2.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_psradi256 (int *s1, int *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  if (N < 32)
+    for (i = 0; i < 8; ++i)
+      r[i] = s1[i] >> N;
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, res;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_srai_epi16 (s1.x, N);
+
+      compute_psradi256 (s1.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c
new file mode 100644
index 000000000..a20a8868a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsravd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_srav_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c
new file mode 100644
index 000000000..8438d9a44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd128-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psravd128 (int *s1, int *s2, int *r)
+{
+  int i, count;
+
+  for (i = 0; i < 4; ++i)
+    {
+      count = s2[i];
+      r[i] = s1[i] >> count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union128i_d s1, s2, res;
+  int res_ref[4];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm_srav_epi32 (s1.x, s2.x);
+
+      compute_psravd128 (s1.a, s2.a, res_ref);
+
+      fail += check_union128i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c
new file mode 100644
index 000000000..6adf3049b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsravd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srav_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c
new file mode 100644
index 000000000..0be75205b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsravd256-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psravd256 (int *s1, int *s2, int *r)
+{
+  int i, count;
+
+  for (i = 0; i < 8; ++i)
+    {
+      count = s2[i];
+      r[i] = s1[i] >> count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_srav_epi32 (s1.x, s2.x);
+
+      compute_psravd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c
new file mode 100644
index 000000000..2b1c3584b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpsraw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sra_epi16 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c
new file mode 100644
index 000000000..66fe8a95c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psraw256 (short *s1, long long int *s2, short *r)
+{
+  int i;
+  long long int count = s2[0];
+
+  memset (r, 0, 32);
+
+  if (count < 16)
+    for (i = 0; i < 16; ++i)
+      r[i] = s1[i] >> count;
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, res;
+  union128i_q s2;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	s1.a[j] = j * i;
+
+      s2.a[0] = i;
+
+      res.x = _mm256_sra_epi16 (s1.x, s2.x);
+
+      compute_psraw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
new file mode 100644
index 000000000..e7112565b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE short
+#define UN_OP(a) ((a) >> (5))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpsraw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c
new file mode 100644
index 000000000..e8558c35d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpsraw\[ \\t\]+\[^\n\]*" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srai_epi16 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c
new file mode 100644
index 000000000..c135833a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrawi-2.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_psrawi256 (short *s1, short *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  if (N < 16)
+    for (i = 0; i < 16; ++i)
+      r[i] = s1[i] >> N;
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, res;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_srai_epi16 (s1.x, N);
+
+      compute_psrawi256 (s1.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c
new file mode 100644
index 000000000..5c0605cdd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srl_epi32 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c
new file mode 100644
index 000000000..1fab08cd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psrld256 (int *s1, long long int *s2, int *r)
+{
+  int i;
+  long long int count = s2[0];
+
+  memset (r, 0, 32);
+
+  if (count < 32)
+    for (i = 0; i < 8; ++i)
+      r[i] = s1[i] >> count;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, res;
+  union128i_q s2;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	s1.a[j] = j * i;
+
+      s2.a[0] = i;
+
+      res.x = _mm256_srl_epi32 (s1.x, s2.x);
+
+      compute_psrld256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c
new file mode 100644
index 000000000..97affb4bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE unsigned
+#define UN_OP(a) ((a) >> (5))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c
new file mode 100644
index 000000000..feac4c920
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpsrld\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srli_epi32 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c
new file mode 100644
index 000000000..0f109feb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldi-2.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_psrldi256 (int *s1, int *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  if (N < 64)
+    for (i = 0; i < 8; ++i)
+      r[i] = s1[i] >> N;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, res;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_srli_epi32 (s1.x, N);
+
+      compute_psrldi256 (s1.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c
new file mode 100644
index 000000000..dd804e04f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+extern volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srli_si256 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c
new file mode 100644
index 000000000..4c2850903
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrldq-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_psrldq256 (char *s1, char *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  for (i = 0; i < 16 - N; i++)
+    r[i] = s1[i + N];
+
+  for (i = 0; i < 16 - N; i++)
+    r[i + 16] = s1[i + N + 16];
+}
+
+
+void static
+avx2_test (void)
+{
+  union256i_b s1, res;
+  char res_ref[32];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_srli_si256 (s1.x, N);
+
+      compute_psrldq256 (s1.a, res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c
new file mode 100644
index 000000000..c19d067a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrlq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srl_epi64 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c
new file mode 100644
index 000000000..e02da78f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psrlq256 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count = s2[0];
+
+  memset (r, 0, 32);
+
+  if (count < 64)
+    for (i = 0; i < 4; ++i)
+      r[i] = s1[i] >> count;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, res;
+  union128i_q s2;
+  long long int res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	s1.a[j] = j * i;
+
+      s2.a[0] = i;
+
+      res.x = _mm256_srl_epi64 (s1.x, s2.x);
+
+      compute_psrlq256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c
new file mode 100644
index 000000000..3cab1dc0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpsrlq\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srli_epi64 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c
new file mode 100644
index 000000000..1aa23fedc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlqi-2.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_psrlqi256 (long long int *s1, long long int *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  if (N < 64)
+    for (i = 0; i < 4; ++i)
+      r[i] = s1[i] >> N;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, res;
+  long long int res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_srli_epi64 (s1.x, N);
+
+      compute_psrlqi256 (s1.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c
new file mode 100644
index 000000000..d4d035842
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrlvd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_srlv_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c
new file mode 100644
index 000000000..c7674c02c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd128-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psrlvd128 (int *s1, int *s2, int *r)
+{
+  int i, count;
+
+  for (i = 0; i < 4; ++i)
+    {
+      count = s2[i];
+      r[i] = ((unsigned) s1[i]) >> count;
+    }
+}
+
+
+void static
+avx2_test (void)
+{
+  union128i_d s1, s2, res;
+  int res_ref[4];
+  int i, j, sign;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm_srlv_epi32 (s1.x, s2.x);
+
+      compute_psrlvd128 (s1.a, s2.a, res_ref);
+
+      fail += check_union128i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c
new file mode 100644
index 000000000..ce76c8f80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrlvd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srlv_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c
new file mode 100644
index 000000000..e3c3c4841
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvd256-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psrlvd256 (int *s1, int *s2, int *r)
+{
+  int i, count;
+
+  for (i = 0; i < 8; ++i)
+    {
+      count = s2[i];
+      r[i] = ((unsigned) s1[i]) >> count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_srlv_epi32 (s1.x, s2.x);
+
+      compute_psrlvd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c
new file mode 100644
index 000000000..64d7c28ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrlvq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m128i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm_srlv_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c
new file mode 100644
index 000000000..842559ff2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq128-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psrlvq128 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count;
+
+  for (i = 0; i < 2; ++i)
+    {
+      count = s2[i];
+      r[i] = ((unsigned long long int) s1[i]) >> count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union128i_q s1, s2, res;
+  long long int res_ref[2];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm_srlv_epi64 (s1.x, s2.x);
+
+      compute_psrlvq128 (s1.a, s2.a, res_ref);
+
+      fail += check_union128i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c
new file mode 100644
index 000000000..4e00736e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrlvq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srlv_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c
new file mode 100644
index 000000000..e006d7c27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlvq256-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psrlvq256 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count;
+
+  for (i = 0; i < 4; ++i)
+    {
+      count = s2[i];
+      r[i] = ((unsigned long long) s1[i]) >> count;
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, s2, res;
+  long long int res_ref[4];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm256_srlv_epi64 (s1.x, s2.x);
+
+      compute_psrlvq256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c
new file mode 100644
index 000000000..f69edbc69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsrlw\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+__m128i y;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srl_epi16 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c
new file mode 100644
index 000000000..fb7526c0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+static void
+compute_psrlw256 (short *s1, long long int *s2, short *r)
+{
+  int i;
+  int count = s2[0];
+
+  memset (r, 0, 32);
+
+  if (count < 16)
+    for (i = 0; i < 16; ++i)
+      r[i] = s1[i] >> count;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, res;
+  union128i_q s2;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	s1.a[j] = j * i;
+
+      s2.a[0] = i;
+
+      res.x = _mm256_srl_epi16 (s1.x, s2.x);
+
+      compute_psrlw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+
+      if (fail)
+	{
+	  for (j = 0; j < 16; ++j)
+	    printf ("%d <->%d\n", res.a[j], res_ref[j]);
+	  abort ();
+	}
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
new file mode 100644
index 000000000..67f3afc41
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE unsigned short
+#define UN_OP(a) ((a) >> (5))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpsrlw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c
new file mode 100644
index 000000000..823d81eb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O3" } */
+/* { dg-final { scan-assembler "vpsrlw\[ \\t\]+\[^\n\]*\\$\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_srli_epi16 (x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c
new file mode 100644
index 000000000..9baf2dadc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsrlwi-2.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_psrlwi256 (short *s1, short *r)
+{
+  int i;
+
+  memset (r, 0, 32);
+
+  if (N < 16)
+    for (i = 0; i < 16; ++i)
+      r[i] = s1[i] >> N;
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, res;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	s1.a[j] = j * i;
+
+      res.x = _mm256_srli_epi16 (s1.x, N);
+
+      compute_psrlwi256 (s1.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c
new file mode 100644
index 000000000..e5ccd6be8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsubb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sub_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c
new file mode 100644
index 000000000..14da9e02c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  char e[32];
+  unsigned i;
+
+  s1.x = _mm256_set_epi8 (10, 74, 50, 4, 6, 99, 1, 4, 87, 83, 84,
+			  29, 81, 79, 1, 3, 1, 5, 2, 47, 20, 2, 72,
+			  92, 9, 4, 23, 17, 99, 43, 72, 17);
+
+  s2.x = _mm256_set_epi8 (88, 44, 33, 20, 56, 99, 2, 90, 38, 4, 200,
+			  17, 3, 39, 2, 37, 27, 95, 17, 74, 72, 43,
+			  27, 112, 71, 50, 32, 72, 84, 17, 27, 96);
+
+  u.x = _mm256_sub_epi8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
new file mode 100644
index 000000000..843128b4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE char
+#define BIN_OP(a, b) ((a) - (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpsubb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c
new file mode 100644
index 000000000..150f4cbcf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sub_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c
new file mode 100644
index 000000000..74a6fec01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-2.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_d u, s1, s2;
+  int e[8];
+  unsigned i;
+
+  s1.x = _mm256_set_epi32 (100, 74, 50000, 4, 6999, 39999, 1000, 4);
+  s2.x = _mm256_set_epi32 (88, 44, 33, 220, 4556, 2999, 2, 9000000);
+
+  u.x = _mm256_sub_epi32 (s1.x, s2.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c
new file mode 100644
index 000000000..f8f399f6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE int
+#define BIN_OP(a, b) ((a) - (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c
new file mode 100644
index 000000000..9460b0d84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsubq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_sub_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c
new file mode 100644
index 000000000..aa869252a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-2.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_q u, s1, s2;
+  long long e[4];
+  unsigned i;
+
+  s1.x = _mm256_set_epi64x (100, 74, 50000, 4);
+  s2.x = _mm256_set_epi64x (88, 44, 33, 220);
+
+  u.x = _mm256_sub_epi64 (s1.x, s2.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union256i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
new file mode 100644
index 000000000..0a23a280e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE long long int
+#define BIN_OP(a, b) ((a) - (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpsubq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c
new file mode 100644
index 000000000..ad1b986f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsubsb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_subs_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c
new file mode 100644
index 000000000..5f33f6b89
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsb-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  char e[32];
+  int i, tmp;
+
+  s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, -80, -40, -100,
+			  -15, 98, 25, 98, 7, 88, 44, 33, 22, 11, 98,
+			  76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+
+  s2.x = _mm256_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78,
+			  -39, 6, 3, 4, 5, 119, 1, 2, 3, 4, 10, 20,
+			  30, 90, -80, -40, -100, -15, 98, 25, 98, 7);
+
+  u.x = _mm256_subs_epi8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    {
+      tmp = s1.a[i] - s2.a[i];
+
+      if (tmp > 127)
+	tmp = 127;
+      if (tmp < -128)
+	tmp = -128;
+
+      e[i] = tmp;
+    }
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c
new file mode 100644
index 000000000..c02d27551
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsubsw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_subs_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c
new file mode 100644
index 000000000..2f2fc7d60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubsw-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_w u, s1, s2;
+  short e[16];
+  int i, tmp;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90, -80,
+			   -40, -100, -15, 98, 25, 98, 7);
+
+  s2.x = _mm256_set_epi16 (88, 44, 33, 22, 11, 98, 76, -100,
+			   -34, -78, -39, 6, 3, 4, 5, 119);
+
+  u.x = _mm256_subs_epi16 (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp = s1.a[i] - s2.a[i];
+
+      if (tmp > 32767)
+	tmp = 32767;
+      if (tmp < -32768)
+	tmp = -32768;
+
+      e[i] = tmp;
+    }
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c
new file mode 100644
index 000000000..917ffa9a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsubusb\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_subs_epu8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c
new file mode 100644
index 000000000..bffb5b6f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusb-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_b u, s1, s2;
+  unsigned char e[32];
+  int i, tmp;
+
+  s1.x = _mm256_set_epi8 (1, 2, 3, 4, 10, 20, 30, 90, 80, 40, 100, 15,
+			  98, 25, 98, 7, 88, 44, 33, 22, 11, 98, 76,
+			  200, 34, 78, 39, 6, 3, 4, 5, 119);
+
+  s2.x = _mm256_set_epi8 (88, 44, 33, 220, 11, 98, 76, 100, 34, 78, 39,
+			  6, 3, 4, 5, 219, 1, 2, 3, 4, 10, 20, 30, 90,
+			  80, 40, 100, 15, 98, 25, 98, 7);
+
+  u.x = _mm256_subs_epu8 (s1.x, s2.x);
+
+  for (i = 0; i < 32; i++)
+    {
+      tmp = (unsigned char) s1.a[i] - (unsigned char) s2.a[i];
+
+      if (tmp < 0)
+	tmp = 0;
+
+      e[i] = tmp;
+    }
+
+  if (check_union256i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c
new file mode 100644
index 000000000..bc0e3df63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpsubusw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_subs_epu16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c
new file mode 100644
index 000000000..7fd16400a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubusw-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  union256i_w u, s1, s2;
+  unsigned short e[16];
+  int i, tmp;
+
+  s1.x = _mm256_set_epi16 (1, 2, 3, 4, 10, 20, 30, 90,
+			   65531, 40, 100, 15, 98, 25, 98, 7);
+
+  s2.x = _mm256_set_epi16 (88, 44, 33, 220, 11, 98, 76, 100,
+			   34, 78, 39, 6, 3, 4, 5, 219);
+
+  u.x = _mm256_subs_epu16 (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp = (unsigned short) s1.a[i] - (unsigned short) s2.a[i];
+
+      if (tmp < 0)
+	tmp = 0;
+
+      e[i] = tmp;
+    }
+
+  if (check_union256i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
new file mode 100644
index 000000000..1cb90b5a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-mavx2 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-require-effective-target avx2 } */
+
+
+#define TYPE short
+#define BIN_OP(a, b) ((a) - (b))
+
+#include "avx2-vpop-check.h"
+
+/* { dg-final { scan-assembler-times "vpsubw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c
new file mode 100644
index 000000000..2c7c9bd11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpunpckhbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_unpackhi_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c
new file mode 100644
index 000000000..3d3f84934
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhbw-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_punpckhbw256 (char *s1, char *s2, char *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      r[2 * i] = s1[i + 8];
+      r[2 * i + 1] = s2[i + 8];
+
+      r[2 * i + 16] = s1[i + 24];
+      r[2 * i + 16 + 1] = s2[i + 24];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_b s1, s2, res;
+  char res_ref[32];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_unpackhi_epi8 (s1.x, s2.x);
+
+      compute_punpckhbw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c
new file mode 100644
index 000000000..e1e65eae3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpunpckhdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_unpackhi_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c
new file mode 100644
index 000000000..34499f01a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhdq-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_punpckhwd256 (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    {
+      r[2 * i] = s1[i + 2];
+      r[2 * i + 1] = s2[i + 2];
+
+      r[2 * i + 4] = s1[i + 2 + 4];
+      r[2 * i + 4 + 1] = s2[i + 2 + 4];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_unpackhi_epi32 (s1.x, s2.x);
+
+      compute_punpckhwd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c
new file mode 100644
index 000000000..a8a5f37ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpunpckhqdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_unpackhi_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c
new file mode 100644
index 000000000..4668571c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhqdq-2.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_punpckhqdq256 (long long int *s1, long long int *s2, long long int *r)
+{
+  r[0] = s1[1];
+  r[1] = s2[1];
+  r[2] = s1[3];
+  r[3] = s2[3];
+}
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, s2, res;
+  long long int res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_unpackhi_epi64 (s1.x, s2.x);
+
+      compute_punpckhqdq256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c
new file mode 100644
index 000000000..1ab034407
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpunpckhwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_unpackhi_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c
new file mode 100644
index 000000000..59c4ed89c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckhwd-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_punpckhwd256 (short *s1, short *s2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    {
+      r[2 * i] = s1[i + 4];
+      r[2 * i + 1] = s2[i + 4];
+
+      r[2 * i + 8] = s1[i + 4 + 8];
+      r[2 * i + 8 + 1] = s2[i + 4 + 8];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_unpackhi_epi16 (s1.x, s2.x);
+
+      compute_punpckhwd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c
new file mode 100644
index 000000000..45db9a41e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpunpcklbw\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_unpacklo_epi8 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c
new file mode 100644
index 000000000..49e41212f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklbw-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_punpcklbw256 (char *s1, char *s2, char *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      r[2 * i] = s1[i];
+      r[2 * i + 1] = s2[i];
+
+      r[2 * i + 16] = s1[i + 16];
+      r[2 * i + 16 + 1] = s2[i + 16];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_b s1, s2, res;
+  char res_ref[32];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 32; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_unpacklo_epi8 (s1.x, s2.x);
+
+      compute_punpcklbw256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_b (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c
new file mode 100644
index 000000000..aff815b29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpunpckldq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_unpacklo_epi32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c
new file mode 100644
index 000000000..aba5e8092
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpckldq-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_punpcklwd256 (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    {
+      r[2 * i] = s1[i];
+      r[2 * i + 1] = s2[i];
+
+      r[2 * i + 4] = s1[i + 4];
+      r[2 * i + 4 + 1] = s2[i + 4];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_d s1, s2, res;
+  int res_ref[8];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_unpacklo_epi32 (s1.x, s2.x);
+
+      compute_punpcklwd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_d (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c
new file mode 100644
index 000000000..e8dd06da8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpunpcklqdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_unpacklo_epi64 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c
new file mode 100644
index 000000000..1c6db718a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklqdq-2.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_punpcklqdq256 (long long int *s1, long long int *s2, long long int *r)
+{
+  r[0] = s1[0];
+  r[1] = s2[0];
+  r[2] = s1[2];
+  r[3] = s2[2];
+}
+
+void static
+avx2_test (void)
+{
+  union256i_q s1, s2, res;
+  long long int res_ref[4];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_unpacklo_epi64 (s1.x, s2.x);
+
+      compute_punpcklqdq256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c
new file mode 100644
index 000000000..6bcdf9bf9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpunpcklwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_unpacklo_epi16 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c
new file mode 100644
index 000000000..9f6f9c0d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpunpcklwd-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <string.h>
+#include "avx2-check.h"
+
+#define N 0x5
+
+static void
+compute_punpcklwd256 (short *s1, short *s2, short *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    {
+      r[2 * i] = s1[i];
+      r[2 * i + 1] = s2[i];
+
+      r[2 * i + 8] = s1[i + 8];
+      r[2 * i + 8 + 1] = s2[i + 8];
+    }
+}
+
+void static
+avx2_test (void)
+{
+  union256i_w s1, s2, res;
+  short res_ref[16];
+  int i, j;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 16; j++)
+	{
+	  s1.a[j] = j * i;
+	  s2.a[j] = j + 20;
+	}
+
+      res.x = _mm256_unpacklo_epi16 (s1.x, s2.x);
+
+      compute_punpcklwd256 (s1.a, s2.a, res_ref);
+
+      fail += check_union256i_w (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c
new file mode 100644
index 000000000..cfd43b0fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpxor-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+/* { dg-final { scan-assembler "vpxor\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+
+void extern
+avx2_test (void)
+{
+  x = _mm256_xor_si256 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c
new file mode 100644
index 000000000..be3264498
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vpxor-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx2" } */
+/* { dg-require-effective-target avx2 } */
+
+#include "avx2-check.h"
+
+void static
+avx2_test (void)
+{
+  int i;
+  union256i_q u, s1, s2;
+  int source1[8] = { 34545, 95567, 23443, 5675, 2323, 67, 2345, 45667 };
+  int source2[8] = { 674, 57897, 93459, 45624, 54674, 1237, 67436, 79608 };
+  int d[8];
+  int e[8];
+
+  s1.x = _mm256_loadu_si256 ((__m256i *) source1);
+  s2.x = _mm256_loadu_si256 ((__m256i *) source2);
+  u.x = _mm256_xor_si256 (s1.x, s2.x);
+
+  _mm256_storeu_si256 ((__m256i *) d, u.x);
+
+  for (i = 0; i < 8; i++)
+    e[i] = source1[i] ^ source2[i];
+
+  if (checkVi (d, e, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c
new file mode 100644
index 000000000..15f20c836
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx2-vshift-1.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mavx2" } */
+/* { dg-require-effective-target avx2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "avx2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST avx2_test
+#endif
+
+#include "xop-vshift-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
new file mode 100644
index 000000000..1fe52bbb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */
+
+#define N 1024
+
+float a[N], b[N+3], c[N];
+
+void
+avx_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    c[i] = a[i] * b[i+3];
+}
+
+/* { dg-final { scan-assembler-not "(avx_loadups256|vmovups\[^\n\r]*movv8sf_internal)" } } */
+/* { dg-final { scan-assembler "(sse_loadups|movv4sf_internal)" } } */
+/* { dg-final { scan-assembler "vinsertf128" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
new file mode 100644
index 000000000..933f265ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */
+
+void
+avx_test (char **cp, char **ep)
+{
+  int i;
+  char **ap = __builtin_assume_aligned (ep, 32);
+  for (i = 128; i > 0; i--)
+    *ap++ = *cp++;
+}
+
+/* { dg-final { scan-assembler-not "(avx_loaddqu256|vmovdqu\[^\n\r]*movv32qi_internal)" } } */
+/* { dg-final { scan-assembler "(sse2_loaddqu|vmovdqu\[^\n\r]*movv16qi_internal)" } } */
+/* { dg-final { scan-assembler "vinsert.128" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c
new file mode 100644
index 000000000..fe66e0b17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mtune=generic" } */
+
+#define N 1024
+
+double a[N], b[N+3], c[N];
+
+void
+avx_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    c[i] = a[i] * b[i+3];
+}
+
+/* { dg-final { scan-assembler-not "(avx_loadupd256|vmovupd\[^\n\r]*movv4df_internal)" } } */
+/* { dg-final { scan-assembler "(sse2_loadupd|vmovupd\[^\n\r]*movv2df_internal)" } } */
+/* { dg-final { scan-assembler "vinsertf128" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
new file mode 100644
index 000000000..1d35ef57b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -fno-common" } */
+
+#define N 1024
+
+float a[N+3], b[N];
+
+void
+avx_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i] = a[i+3] * 2;
+}
+
+/* { dg-final { scan-assembler "(avx_loadups256|vmovups\[^\n\r]*movv8sf_internal)" } } */
+/* { dg-final { scan-assembler-not "(sse_loadups|vmovups\[^\n\r]*movv4sf_internal)" } } */
+/* { dg-final { scan-assembler-not "vinsertf128" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-5.c
new file mode 100644
index 000000000..153b66f82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-5.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */
+
+#include "avx-check.h"
+
+#define N 8
+
+float a[N+3] = { -1, -1, -1, 24.43, 68.346, 43.35,
+		 546.46, 46.79, 82.78, 82.7, 9.4 };
+float b[N];
+float c[N];
+
+void
+foo (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i] = a[i+3] * 2;
+}
+
+__attribute__ ((noinline))
+float
+bar (float x)
+{
+  return x * 2;
+}
+
+void
+avx_test (void)
+{
+  int i;
+
+  foo ();
+
+  for (i = 0; i < N; i++)
+    c[i] = bar (a[i+3]);
+
+  for (i = 0; i < N; i++)
+    if (b[i] != c[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-6.c
new file mode 100644
index 000000000..2fa984cc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-6.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */
+
+#include "avx-check.h"
+
+#define N 4
+
+double a[N+3] = { -1, -1, -1, 24.43, 68.346, 43.35, 546.46 };
+double b[N];
+double c[N];
+
+void
+foo (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i] = a[i+3] * 2;
+}
+
+__attribute__ ((noinline))
+double
+bar (double x)
+{
+  return x * 2;
+}
+
+void
+avx_test (void)
+{
+  int i;
+
+  foo ();
+
+  for (i = 0; i < N; i++)
+    c[i] = bar (a[i+3]);
+
+  for (i = 0; i < N; i++)
+    if (b[i] != c[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c
new file mode 100644
index 000000000..ad16a5329
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load" } */
+
+#include "avx-check.h"
+
+#define N 128
+
+char **ep;
+char **fp;
+char **mp;
+char **lp;
+
+__attribute__ ((noinline))
+void
+foo (void)
+{
+  mp = (char **) malloc (N);
+  lp = (char **) malloc (N);
+  ep = (char **) malloc (N);
+  fp = (char **) malloc (N);
+}
+
+void
+avx_test (void)
+{
+  int i;
+  char **ap, **bp, **cp, **dp;
+  char *str = "STR";
+
+  foo ();
+
+  cp = mp;
+  dp = lp;
+
+  for (i = N; i >= 0; i--)
+    {
+      *cp++ = str;
+      *dp++ = str;
+    }
+
+  ap = ep;
+  bp = fp;
+  cp = mp;
+  dp = lp;
+
+  for (i = N; i >= 0; i--)
+    {
+      *ap++ = *cp++;
+      *bp++ = *dp++;
+    }
+
+  for (i = N; i >= 0; i--)
+    {
+      if (strcmp (*--ap, "STR") != 0)
+	abort ();
+      if (strcmp (*--bp, "STR") != 0)
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
new file mode 100644
index 000000000..77eaa422e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -fno-common" } */
+
+#define N 1024
+
+float a[N], b[N+3], c[N], d[N];
+
+void
+avx_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i+3] = a[i] * 10.0;
+
+  for (i = 0; i < N; i++)
+    d[i] = c[i] * 20.0;
+}
+
+/* { dg-final { scan-assembler-not "avx_storeups256" } } */
+/* { dg-final { scan-assembler "vmovups.*\\*movv4sf_internal/3" } } */
+/* { dg-final { scan-assembler "vextractf128" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
new file mode 100644
index 000000000..48e2efa13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
@@ -0,0 +1,28 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */
+
+#define N 1024
+
+char **ep;
+char **fp;
+
+void
+avx_test (void)
+{
+  int i;
+  char **ap;
+  char **bp;
+  char **cp;
+
+  ap = ep;
+  bp = fp;
+  for (i = 128; i >= 0; i--)
+    {
+      *ap++ = *cp++;
+      *bp++ = 0;
+    }
+}
+
+/* { dg-final { scan-assembler-not "avx_storedqu256" } } */
+/* { dg-final { scan-assembler "vmovups.*\\*movv16qi_internal/3" } } */
+/* { dg-final { scan-assembler "vextract.128" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c
new file mode 100644
index 000000000..6175d5217
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mtune=generic -fno-common" } */
+
+#define N 1024
+
+double a[N], b[N+3], c[N], d[N];
+
+void
+avx_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i+3] = a[i] * 10.0;
+
+  for (i = 0; i < N; i++)
+    d[i] = c[i] * 20.0;
+}
+
+/* { dg-final { scan-assembler-not "avx_storeupd256" } } */
+/* { dg-final { scan-assembler "vmovups.*\\*movv2df_internal/3" } } */
+/* { dg-final { scan-assembler "vextractf128" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
new file mode 100644
index 000000000..85682452f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -fno-common" } */
+
+#define N 1024
+
+float a[N], b[N+3], c[N];
+
+void
+avx_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i+3] = a[i] * c[i];
+}
+
+/* { dg-final { scan-assembler "avx_storeups256" } } */
+/* { dg-final { scan-assembler-not "sse_storeups" } } */
+/* { dg-final { scan-assembler-not "\\*avx_movv4sf_internal/3" } } */
+/* { dg-final { scan-assembler-not "vextractf128" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-5.c
new file mode 100644
index 000000000..642da3cf0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-5.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */
+
+#include "avx-check.h"
+
+#define N 8
+
+float a[N] = { 24.43, 68.346, 43.35, 546.46, 46.79, 82.78, 82.7, 9.4 };
+float b[N+3];
+float c[N+3];
+
+void
+foo (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i+3] = a[i] * 2;
+}
+
+__attribute__ ((noinline))
+float
+bar (float x)
+{
+  return x * 2;
+}
+
+void
+avx_test (void)
+{
+  int i;
+
+  foo ();
+
+  for (i = 0; i < N; i++)
+    c[i+3] = bar (a[i]);
+
+  for (i = 0; i < N; i++)
+    if (b[i+3] != c[i+3])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-6.c
new file mode 100644
index 000000000..a0de7a56f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-6.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */
+
+#include "avx-check.h"
+
+#define N 4
+
+double a[N] = { 24.43, 68.346, 43.35, 546.46 };
+double b[N+3];
+double c[N+3];
+
+void
+foo (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i+3] = a[i] * 2;
+}
+
+__attribute__ ((noinline))
+double
+bar (double x)
+{
+  return x * 2;
+}
+
+void
+avx_test (void)
+{
+  int i;
+
+  foo ();
+
+  for (i = 0; i < N; i++)
+    c[i+3] = bar (a[i]);
+
+  for (i = 0; i < N; i++)
+    if (b[i+3] != c[i+3])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c
new file mode 100644
index 000000000..4272dc3cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store" } */
+
+#include "avx-check.h"
+
+#define N 128
+
+char **ep;
+char **fp;
+
+__attribute__ ((noinline))
+void
+foo (void)
+{
+  ep = (char **) malloc (N);
+  fp = (char **) malloc (N);
+}
+
+void
+avx_test (void)
+{
+  int i;
+  char **ap, **bp;
+  char *str = "STR";
+
+  foo ();
+
+  ap = ep;
+  bp = fp;
+
+  for (i = N; i >= 0; i--)
+    {
+      *ap++ = str;
+      *bp++ = str;
+    }
+
+  for (i = N; i >= 0; i--)
+    {
+      if (strcmp (*--ap, "STR") != 0)
+	abort ();
+      if (strcmp (*--bp, "STR") != 0)
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-check.h
new file mode 100644
index 000000000..bccf8b48e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-check.h
@@ -0,0 +1,46 @@
+#include <stdlib.h>
+#include "cpuid.h"
+#include "m512-check.h"
+#include "avx512f-os-support.h"
+
+static void avx512cd_test (void);
+
+static void __attribute__ ((noinline)) do_test (void)
+{
+  avx512cd_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  if ((ecx & bit_OSXSAVE) == (bit_OSXSAVE))
+    {
+      if (__get_cpuid_max (0, NULL) < 7)
+	return 0;
+
+      __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+      if ((avx512f_os_support ()) && ((ebx & (bit_AVX512CD)) == (bit_AVX512CD)))
+	{
+	  do_test ();
+#ifdef DEBUG
+	  printf ("PASSED\n");
+#endif
+	  return 0;
+	}
+#ifdef DEBUG
+      printf ("SKIPPED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmb2q-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmb2q-1.c
new file mode 100644
index 000000000..036031b76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmb2q-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512cd -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastmb2q\[ \\t\]+\[^\n\]*k\[1-7\]\[^\n\]*%zmm\[0-7\]" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcastmb_epi64 (m8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmb2q-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmb2q-2.c
new file mode 100644
index 000000000..05f4bfc42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmb2q-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512cd" } */
+/* { dg-require-effective-target avx512cd } */
+
+#define HAVE_512
+#define AVX512CD
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+
+CALC (long long *res, __mmask8 src)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    res[i] = src;
+}
+
+static void
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) res;
+  long long res_ref[SIZE];
+  __mmask8 src;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res.a[i] = -1;
+    }
+
+  res.x = INTRINSIC (_broadcastmb_epi64) (src);
+
+  CALC (res_ref, src);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmw2d-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmw2d-1.c
new file mode 100644
index 000000000..36abb5e7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmw2d-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512cd -O2" } */
+/* { dg-final { scan-assembler "vpbroadcastmw2d\[ \\t\]+\[^\n\]*k\[1-7\]\[^\n\]*%zmm\[0-7\]" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m16;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcastmw_epi32 (m16);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmw2d-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmw2d-2.c
new file mode 100644
index 000000000..7282110ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpbroadcastmw2d-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512cd" } */
+/* { dg-require-effective-target avx512cd } */
+
+#define HAVE_512
+#define AVX512CD
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+
+CALC (int *res, __mmask16 src)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    res[i] = src;
+}
+
+static void
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) res;
+  int res_ref[SIZE];
+  __mmask16 src;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res.a[i] = -1;
+    }
+
+  res.x = INTRINSIC (_broadcastmw_epi32) (src);
+
+  CALC (res_ref, src);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictd-1.c
new file mode 100644
index 000000000..d3f2a258d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512cd -O2" } */
+/* { dg-final { scan-assembler-times "vpconflictd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpconflictd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpconflictd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m512i res;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_conflict_epi32 (s);
+  res = _mm512_mask_conflict_epi32 (res, 2, s);
+  res = _mm512_maskz_conflict_epi32 (2, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictd-2.c
new file mode 100644
index 000000000..16597fbaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictd-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512cd" } */
+/* { dg-require-effective-target avx512cd } */
+
+#define HAVE_512
+#define AVX512CD
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s, int *r)
+{
+  int i, j;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = 0;
+      for (j = 0; j < i; j++)
+	{
+	  r[i] |= s[j] == s[i] ? 1 << j : 0;
+	}
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s, res1, res2, res3;
+  int res_ref[SIZE];
+  MASK_TYPE mask = MASK_VALUE;
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 1234 * (i % 5);
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_conflict_epi32) (s.x);
+  res2.x = INTRINSIC (_mask_conflict_epi32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_conflict_epi32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictq-1.c
new file mode 100644
index 000000000..795fa6add
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512cd -O2" } */
+/* { dg-final { scan-assembler-times "vpconflictq\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpconflictq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vpconflictq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m512i res;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_conflict_epi64 (s);
+  res = _mm512_mask_conflict_epi64 (res, 2, s);
+  res = _mm512_maskz_conflict_epi64 (2, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictq-2.c
new file mode 100644
index 000000000..a2695195c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vpconflictq-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512cd" } */
+/* { dg-require-effective-target avx512cd } */
+
+#define HAVE_512
+#define AVX512CD
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *s, long long *r)
+{
+  int i, j;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = 0;
+      for (j = 0; j < i; j++)
+	{
+	  r[i] |= s[i] == s[j] ? 1 << j : 0;
+	}
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s, res1, res2, res3;
+  long long res_ref[SIZE];
+  MASK_TYPE mask = MASK_VALUE;
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 12345678 * (i % 5);
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_conflict_epi64) (s.x);
+  res2.x = INTRINSIC (_mask_conflict_epi64) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_conflict_epi64) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntd-1.c
new file mode 100644
index 000000000..65a2a3275
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512cd -O2" } */
+/* { dg-final { scan-assembler-times "vplzcntd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vplzcntd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1} } */
+/* { dg-final { scan-assembler-times "vplzcntd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m512i res;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_lzcnt_epi32 (s);
+  res = _mm512_mask_lzcnt_epi32 (res, 2, s);
+  res = _mm512_maskz_lzcnt_epi32 (2, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntd-2.c
new file mode 100644
index 000000000..0a357b69f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntd-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512cd" } */
+/* { dg-require-effective-target avx512cd } */
+
+#define HAVE_512
+#define AVX512CD
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include <strings.h>
+
+static void
+CALC (int *s, int *r)
+{
+  int i, res;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res = 0;
+      while ((res < 32) && (((s[i] >> (31 - res)) & 1) == 0))
+	++res;
+      r[i] = res;
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s, res1, res2, res3;
+  int res_ref[SIZE];
+  MASK_TYPE mask = MASK_VALUE;
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 12345678 * (i % 5);
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_lzcnt_epi32) (s.x);
+  res2.x = INTRINSIC (_mask_lzcnt_epi32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_lzcnt_epi32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntq-1.c
new file mode 100644
index 000000000..0324cd0c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512cd -O2" } */
+/* { dg-final { scan-assembler-times "vplzcntq\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vplzcntq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vplzcntq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m512i res;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_lzcnt_epi64 (s);
+  res = _mm512_maskz_lzcnt_epi64 (2, s);
+  res = _mm512_mask_lzcnt_epi64 (res, 2, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntq-2.c
new file mode 100644
index 000000000..f0cc40304
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512cd-vplzcntq-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512cd" } */
+/* { dg-require-effective-target avx512cd } */
+
+#define HAVE_512
+#define AVX512CD
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include <strings.h>
+
+static void
+CALC (long long *s, long long *r)
+{
+  int i, res;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res = 0;
+      while ((res < 64) && (((s[i] >> (63 - res)) & 1) == 0))
+	++res;
+      r[i] = res;
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s, res1, res2, res3;
+  long long res_ref[SIZE];
+  MASK_TYPE mask = MASK_VALUE;
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 12345678 * (i % 5);
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_lzcnt_epi64) (s.x);
+  res2.x = INTRINSIC (_mask_lzcnt_epi64) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_lzcnt_epi64) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-check.h
new file mode 100644
index 000000000..34440d346
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-check.h
@@ -0,0 +1,46 @@
+#include <stdlib.h>
+#include "cpuid.h"
+#include "m512-check.h"
+#include "avx512f-os-support.h"
+
+static void avx512er_test (void);
+
+static void __attribute__ ((noinline)) do_test (void)
+{
+  avx512er_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  if ((ecx & bit_OSXSAVE) == (bit_OSXSAVE))
+    {
+      if (__get_cpuid_max (0, NULL) < 7)
+	return 0;
+
+      __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+      if ((avx512f_os_support ()) && ((ebx & bit_AVX512ER) == bit_AVX512ER))
+	{
+	  do_test ();
+#ifdef DEBUG
+	  printf ("PASSED\n");
+#endif
+	  return 0;
+	}
+#ifdef DEBUG
+      printf ("SKIPPED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2pd-1.c
new file mode 100644
index 000000000..22c086d5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2pd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vexp2pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vexp2pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vexp2pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vexp2pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]*\n" 1 } } */
+/* { dg-final { scan-assembler-times "vexp2pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vexp2pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm512_exp2a23_pd (x);
+  x = _mm512_mask_exp2a23_pd (x, m, x);
+  x = _mm512_maskz_exp2a23_pd (m, x);
+  x = _mm512_exp2a23_round_pd (x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_exp2a23_round_pd (x, m, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_exp2a23_round_pd (m, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2pd-2.c
new file mode 100644
index 000000000..ce4e86c1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2pd-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+void static
+compute_vexp2pd (double *s, double *r)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    r[i] = pow (2.0, s[i]);
+}
+
+void static
+avx512er_test (void)
+{
+  union512d src, res1, res2, res3;
+  __mmask8 mask = MASK_VALUE;
+  double res_ref[8];
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 179.345 - 6.5645 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = _mm512_exp2a23_pd (src.x);
+  res2.x = _mm512_mask_exp2a23_pd (res2.x, mask, src.x);
+  res3.x = _mm512_maskz_exp2a23_pd (mask, src.x);
+
+  compute_vexp2pd (src.a, res_ref);
+
+  if (check_rough_union512d (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, 8);
+  if (check_rough_union512d (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, 8);
+  if (check_rough_union512d (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2ps-1.c
new file mode 100644
index 000000000..9d1178e55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2ps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vexp2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vexp2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vexp2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vexp2ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]*\n" 1 } } */
+/* { dg-final { scan-assembler-times "vexp2ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vexp2ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm512_exp2a23_ps (x);
+  x = _mm512_mask_exp2a23_ps (x, m, x);
+  x = _mm512_maskz_exp2a23_ps (m, x);
+  x = _mm512_exp2a23_round_ps (x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_exp2a23_round_ps (x, m, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_exp2a23_round_ps (m, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2ps-2.c
new file mode 100644
index 000000000..ab911c017
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vexp2ps-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+void static
+compute_vexp2ps (float *s, float *r)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    r[i] = pow (2.0, s[i]);
+}
+
+void static
+avx512er_test (void)
+{
+  union512 src, res1, res2, res3;
+  __mmask16 mask = MASK_VALUE;
+  float res_ref[16];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      src.a[i] = 79.345 - 6.5645 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = _mm512_exp2a23_ps (src.x);
+  res2.x = _mm512_mask_exp2a23_ps (res2.x, mask, src.x);
+  res3.x = _mm512_maskz_exp2a23_ps (mask, src.x);
+
+  compute_vexp2ps (src.a, res_ref);
+
+  if (check_rough_union512 (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, 16);
+  if (check_rough_union512 (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, 16);
+  if (check_rough_union512 (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28pd-1.c
new file mode 100644
index 000000000..505c0eb9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28pd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vrcp28pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrcp28pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrcp28pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vrcp28pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]*\n" 1 } } */
+/* { dg-final { scan-assembler-times "vrcp28pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrcp28pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm512_rcp28_pd (x);
+  x = _mm512_mask_rcp28_pd (x, m, x);
+  x = _mm512_maskz_rcp28_pd (m, x);
+  x = _mm512_rcp28_round_pd (x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_rcp28_round_pd (x, m, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_rcp28_round_pd (m, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28pd-2.c
new file mode 100644
index 000000000..609aeaa31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28pd-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+
+void static
+compute_vrcp28pd (double *s, double *r)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    r[i] = 1.0 / s[i];
+}
+
+void static
+avx512er_test (void)
+{
+  union512d src, res1, res2, res3;
+  __mmask8 mask = MASK_VALUE;
+  double res_ref[8];
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 179.345 - 6.5645 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = _mm512_rcp28_pd (src.x);
+  res2.x = _mm512_mask_rcp28_pd (res2.x, mask, src.x);
+  res3.x = _mm512_maskz_rcp28_pd (mask, src.x);
+
+  compute_vrcp28pd (src.a, res_ref);
+
+  if (check_rough_union512d (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, 8);
+  if (check_rough_union512d (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, 8);
+  if (check_rough_union512d (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ps-1.c
new file mode 100644
index 000000000..e9245bad4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vrcp28ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrcp28ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrcp28ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vrcp28ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]*\n" 1 } } */
+/* { dg-final { scan-assembler-times "vrcp28ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrcp28ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm512_rcp28_ps (x);
+  x = _mm512_mask_rcp28_ps (x, m, x);
+  x = _mm512_maskz_rcp28_ps (m, x);
+  x = _mm512_rcp28_round_ps (x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_rcp28_round_ps (x, m, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_rcp28_round_ps (m, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ps-2.c
new file mode 100644
index 000000000..4059e0e7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ps-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+
+void static
+compute_vrcp28ps (float *s, float *r)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    r[i] = 1.0 / s[i];
+}
+
+void static
+avx512er_test (void)
+{
+  union512 src, res1, res2, res3;
+  __mmask16 mask = MASK_VALUE;
+  float res_ref[16];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      src.a[i] = 179.345 - 6.5645 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = _mm512_rcp28_ps (src.x);
+  res2.x = _mm512_mask_rcp28_ps (res2.x, mask, src.x);
+  res3.x = _mm512_maskz_rcp28_ps (mask, src.x);
+
+  compute_vrcp28ps (src.a, res_ref);
+
+  if (check_rough_union512 (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, 16);
+  if (check_rough_union512 (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, 16);
+  if (check_rough_union512 (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28sd-1.c
new file mode 100644
index 000000000..d09ba5711
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28sd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vrcp28sd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrcp28sd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]*\n" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x, y;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm_rcp28_sd (x, y);
+  x = _mm_rcp28_round_sd (x, y, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28sd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28sd-2.c
new file mode 100644
index 000000000..889f990ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28sd-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+void static
+avx512er_test (void)
+{
+  union128d src1, src2, res;
+  double res_ref[2];
+  int i;
+  
+  for (i = 0; i < 2; i++)
+    {
+      src1.a[i] = 179.345 - 6.5645 * i;
+      src2.a[i] = 204179.345 + 6.5645 * i;
+      res_ref[i] = src1.a[i];
+    }
+
+  res_ref[0] = 1.0 / src2.a[0];
+
+  res.x = _mm_rcp28_round_sd (src1.x, src2.x, _MM_FROUND_NO_EXC);
+
+  if (checkVd (res.a, res_ref, 2))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ss-1.c
new file mode 100644
index 000000000..3f5ccea15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ss-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vrcp28ss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrcp28ss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]*\n" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x, y;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm_rcp28_ss (x, y);
+  x = _mm_rcp28_round_ss (x, y, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ss-2.c
new file mode 100644
index 000000000..328087910
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrcp28ss-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+void static
+avx512er_test (void)
+{
+  union128 src1, src2, res;
+  float res_ref[4];
+  int i;
+  
+  for (i = 0; i < 4; i++)
+    {
+      src1.a[i] = 179.345 - 6.5645 * i;
+      src2.a[i] = 179345.006 + 6.5645 * i;
+      res_ref[i] = src1.a[i];
+    }
+
+  res_ref[0] = 1.0 / src2.a[0];
+
+  res.x = _mm_rcp28_round_ss (src1.x, src2.x, _MM_FROUND_NO_EXC);
+
+  if (checkVf (res.a, res_ref, 4))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28pd-1.c
new file mode 100644
index 000000000..5d264ac73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28pd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vrsqrt28pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]*\n" 1 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm512_rsqrt28_pd (x);
+  x = _mm512_mask_rsqrt28_pd (x, m, x);
+  x = _mm512_maskz_rsqrt28_pd (m, x);
+  x = _mm512_rsqrt28_round_pd (x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_rsqrt28_round_pd (x, m, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_rsqrt28_round_pd (m, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28pd-2.c
new file mode 100644
index 000000000..84a66addd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28pd-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+void static
+compute_vrsqrt28pd (double *s, double *r)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    r[i] = 1.0 / sqrt (s[i]);
+}
+
+void static
+avx512er_test (void)
+{
+  union512d src, res1, res2, res3;
+  __mmask8 mask = MASK_VALUE;
+  double res_ref[8];
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 179.345 - 6.5645 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = _mm512_rsqrt28_pd (src.x);
+  res2.x = _mm512_mask_rsqrt28_pd (res2.x, mask, src.x);
+  res3.x = _mm512_maskz_rsqrt28_pd (mask, src.x);
+
+  compute_vrsqrt28pd (src.a, res_ref);
+
+  if (check_rough_union512d (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, 8);
+  if (check_rough_union512d (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, 8);
+  if (check_rough_union512d (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ps-1.c
new file mode 100644
index 000000000..bfdb9ac6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vrsqrt28ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]*\n" 1 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm512_rsqrt28_ps (x);
+  x = _mm512_mask_rsqrt28_ps (x, m, x);
+  x = _mm512_maskz_rsqrt28_ps (m, x);
+  x = _mm512_rsqrt28_round_ps (x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_rsqrt28_round_ps (x, m, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_rsqrt28_round_ps (m, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ps-2.c
new file mode 100644
index 000000000..a92472e61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ps-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+void static
+compute_vrsqrt28ps (float *s, float *r)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    r[i] = 1.0 / sqrt (s[i]);
+}
+
+void static
+avx512er_test (void)
+{
+  union512 src, res1, res2, res3;
+  __mmask16 mask = MASK_VALUE;
+  float res_ref[16];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      src.a[i] = 179.345 - 6.5645 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = _mm512_rsqrt28_ps (src.x);
+  res2.x = _mm512_mask_rsqrt28_ps (res2.x, mask, src.x);
+  res3.x = _mm512_maskz_rsqrt28_ps (mask, src.x);
+
+  compute_vrsqrt28ps (src.a, res_ref);
+
+  if (check_rough_union512 (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, 16);
+  if (check_rough_union512 (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, 16);
+  if (check_rough_union512 (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28sd-1.c
new file mode 100644
index 000000000..59dff784e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28sd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vrsqrt28sd\[ \\t\]+\[^\{^\n\]*%xmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28sd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x, y;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm_rsqrt28_sd (x, y);
+  x = _mm_rsqrt28_round_sd (x, y, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28sd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28sd-2.c
new file mode 100644
index 000000000..bd217e822
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28sd-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+void static
+avx512er_test (void)
+{
+  union128d src1, src2, res;
+  double res_ref[2];
+  int i;
+  
+  for (i = 0; i < 2; i++)
+    {
+      src1.a[i] = 179.345 - 6.5645 * i;
+      src2.a[i] = 45 - 6.5645 * i;
+      res_ref[i] = src1.a[i];
+    }
+
+  res_ref[0] = 1.0 / sqrt (src2.a[0]);
+
+  res.x = _mm_rsqrt28_round_sd (src1.x, src2.x, _MM_FROUND_NO_EXC);
+
+  if (checkVd (res.a, res_ref, 2))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ss-1.c
new file mode 100644
index 000000000..a33437581
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ss-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512er -O2" } */
+/* { dg-final { scan-assembler-times "vrsqrt28ss\[ \\t\]+\[^\{^\n\]*%xmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrsqrt28ss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x, y;
+
+void extern
+avx512er_test (void)
+{
+  x = _mm_rsqrt28_ss (x, y);
+  x = _mm_rsqrt28_round_ss (x, y, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ss-2.c
new file mode 100644
index 000000000..f7bfff5a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512er-vrsqrt28ss-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512er } */
+/* { dg-options "-O2 -mavx512er" } */
+
+#include "avx512er-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+void static
+avx512er_test (void)
+{
+  union128 src1, src2, res;
+  float res_ref[4];
+  int i;
+  
+  for (i = 0; i < 4; i++)
+    {
+      src1.a[i] = 179.345 - 6.5645 * i;
+      src2.a[i] = 179221345 + 6.5645 * i;
+      res_ref[i] = src1.a[i];
+    }
+
+  res_ref[0] = 1.0 / sqrt (src2.a[0]);
+
+  res.x = _mm_rsqrt28_round_ss (src1.x, src2.x, _MM_FROUND_NO_EXC);
+
+  if (checkVf (res.a, res_ref, 4))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
new file mode 100644
index 000000000..1bd428aed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f" } */
+
+void foo ()
+{
+  register int zmm_var asm ("zmm9");
+
+  __asm__ __volatile__("vxorpd %%zmm0, %%zmm0, %%zmm7\n" : : : "zmm7" );
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-broadcast-gpr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-broadcast-gpr-1.c
new file mode 100644
index 000000000..f550e2247
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-broadcast-gpr-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastq\[ \\t\]+%r\[^\n\]+%zmm\[0-9\]\[^\{\]" 1 { target { ! { ia32 } } } } } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[ \\t\]+%e\[^\n\]+%zmm\[0-9\]\[^\{\]" 1 { target { ! { ia32 } } } } } */
+/* { dg-final { scan-assembler-times "vpbroadcastq\[ \\t\]+\[^\n\]+%zmm\[0-9\]\[^\{\]" 1 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[ \\t\]+\[^\n\]+%zmm\[0-9\]\[^\{\]" 1 { target ia32 } } } */
+
+#include <x86intrin.h>
+
+__m512i
+foo_1 (long long y)
+{
+  return __extension__ (__m512i)(__v8di){ y, y, y, y, y, y, y, y };
+}
+
+__m512i
+foo_2 (int y)
+{
+  return __extension__ (__m512i)(__v16si){ y, y, y, y, y, y, y, y, y,
+				      y, y, y, y, y, y, y };
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-broadcast-gpr-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-broadcast-gpr-2.c
new file mode 100644
index 000000000..91665b299
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-broadcast-gpr-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+#include "avx512f-broadcast-gpr-1.c"
+
+void
+avx512f_test (void)
+{
+  union512i_q q;
+  union512i_d d;
+  int i;
+
+  q.x = foo_1 (3);
+  d.x = foo_2 (5);
+
+  for (i = 0; i < 8; i++)
+  {
+    if (q.a[i] != 3)
+      abort ();
+  }
+
+  for (i = 0; i < 16; i++)
+  {
+    if (d.a[i] != 5)
+      abort ();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-ceil-sfix-vec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-ceil-sfix-vec-1.c
new file mode 100644
index 000000000..038d25e35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-ceil-sfix-vec-1.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include <math.h>
+#include "avx512f-check.h"
+
+extern double ceil (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+avx512f_test (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) ceil (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) ceil (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-ceil-sfix-vec-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-ceil-sfix-vec-2.c
new file mode 100644
index 000000000..8dafb1bf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-ceil-sfix-vec-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */
+
+#include "avx512f-ceil-sfix-vec-1.c"
+
+/* { dg-final { scan-assembler "vrndscalepd\[^\n\]*zmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "vcvttpd2dq\[^\n\]*zmm\[0-9\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-check.h
new file mode 100644
index 000000000..9e0136720
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-check.h
@@ -0,0 +1,47 @@
+#include <stdlib.h>
+#include "cpuid.h"
+#include "m512-check.h"
+#include "avx512f-os-support.h"
+
+static void avx512f_test (void);
+
+static void __attribute__ ((noinline)) do_test (void)
+{
+  avx512f_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AVX512F test only if host has AVX512F support.  */
+  if ((ecx & bit_OSXSAVE) == (bit_OSXSAVE))
+    {
+      if (__get_cpuid_max (0, NULL) < 7)
+	return 0;
+
+      __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+      if ((avx512f_os_support ()) && ((ebx & bit_AVX512F) == bit_AVX512F))
+	{
+	  do_test ();
+#ifdef DEBUG
+	  printf ("PASSED\n");
+#endif
+	  return 0;
+	}
+#ifdef DEBUG
+      printf ("SKIPPED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-dummy.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-dummy.c
new file mode 100644
index 000000000..84b062789
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-dummy.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union512i_q u, s1, s2;
+  long long e[8];
+  volatile int tst = check_union512i_q (u, e);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-floor-sfix-vec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-floor-sfix-vec-1.c
new file mode 100644
index 000000000..fab7e6528
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-floor-sfix-vec-1.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include <math.h>
+#include "avx512f-check.h"
+
+extern double floor (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+avx512f_test (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) floor (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) floor (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-floor-sfix-vec-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-floor-sfix-vec-2.c
new file mode 100644
index 000000000..90e625abc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-floor-sfix-vec-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx512f" } */
+
+#include "avx512f-floor-sfix-vec-1.c"
+
+/* { dg-final { scan-assembler "vrndscalepd\[^\n\]*zmm\[0-9\]" } } */
+/* { dg-final { scan-assembler "vcvttpd2dq\[^\n\]*zmm\[0-9\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-1.c
new file mode 100644
index 000000000..5ccb03a1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-1.c
@@ -0,0 +1,217 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-options "-O3 -mavx512f" } */
+
+#include "avx512f-check.h"
+
+#define N 1024
+float vf1[N+16], vf2[N];
+double vd1[N+16], vd2[N];
+int vi1[N+16], vi2[N], k[N];
+long long vl1[N+16], vl2[N];
+long l[N];
+
+__attribute__((noinline, noclone)) void
+f1 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vf2[i] = vf1[k[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f2 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vi2[i] = vi1[k[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f3 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vf2[i] = vf1[k[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f4 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vi2[i] = vi1[k[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f5 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vd2[i] = vd1[k[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f6 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vl2[i] = vl1[k[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f7 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vd2[i] = vd1[k[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f8 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vl2[i] = vl1[k[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f9 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vf2[i] = vf1[l[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f10 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vi2[i] = vi1[l[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f11 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vf2[i] = vf1[l[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f12 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vi2[i] = vi1[l[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f13 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vd2[i] = vd1[l[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f14 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vl2[i] = vl1[l[i]];
+}
+
+__attribute__((noinline, noclone)) void
+f15 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vd2[i] = vd1[l[i] + x];
+}
+
+__attribute__((noinline, noclone)) void
+f16 (int x)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    vl2[i] = vl1[l[i] + x];
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+
+  for (i = 0; i < N + 16; i++)
+    {
+      asm ("");
+      vf1[i] = 17.0f + i;
+      vd1[i] = 19.0 + i;
+      vi1[i] = 21 + i;
+      vl1[i] = 23L + i;
+    }
+  for (i = 0; i < N; i++)
+    {
+      asm ("");
+      k[i] = (i * 731) & (N - 1);
+      l[i] = (i * 657) & (N - 1);
+    }
+
+  f1 ();
+  f2 ();
+  for (i = 0; i < N; i++)
+    if (vf2[i] != ((i * 731) & (N - 1)) + 17
+	|| vi2[i] != ((i * 731) & (N - 1)) + 21)
+      abort ();
+
+  f3 (12);
+  f4 (14);
+  for (i = 0; i < N; i++)
+    if (vf2[i] != ((i * 731) & (N - 1)) + 17 + 12
+	|| vi2[i] != ((i * 731) & (N - 1)) + 21 + 14)
+      abort ();
+
+  f5 ();
+  f6 ();
+  for (i = 0; i < N; i++)
+    if (vd2[i] != ((i * 731) & (N - 1)) + 19
+	|| vl2[i] != ((i * 731) & (N - 1)) + 23)
+      abort ();
+
+  f7 (6);
+  f8 (3);
+  for (i = 0; i < N; i++)
+    if (vd2[i] != ((i * 731) & (N - 1)) + 19 + 6
+	|| vl2[i] != ((i * 731) & (N - 1)) + 23 + 3)
+      abort ();
+
+  f9 ();
+  f10 ();
+  for (i = 0; i < N; i++)
+    if (vf2[i] != ((i * 657) & (N - 1)) + 17
+	|| vi2[i] != ((i * 657) & (N - 1)) + 21)
+      abort ();
+
+  f11 (7);
+  f12 (9);
+  for (i = 0; i < N; i++)
+    if (vf2[i] != ((i * 657) & (N - 1)) + 17 + 7
+	|| vi2[i] != ((i * 657) & (N - 1)) + 21 + 9)
+      abort ();
+
+  f13 ();
+  f14 ();
+  for (i = 0; i < N; i++)
+    if (vd2[i] != ((i * 657) & (N - 1)) + 19
+	|| vl2[i] != ((i * 657) & (N - 1)) + 23)
+      abort ();
+
+  f15 (2);
+  f16 (12);
+  for (i = 0; i < N; i++)
+    if (vd2[i] != ((i * 657) & (N - 1)) + 19 + 2
+	|| vl2[i] != ((i * 657) & (N - 1)) + 23 + 12)
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-2.c
new file mode 100644
index 000000000..f20d3db22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */ /* PR59617 */
+/* { dg-options "-O3 -mavx512f -fdump-tree-vect-details" } */
+
+#include "avx512f-gather-1.c"
+
+/* { dg-final { scan-assembler-not "gather\[^\n\]*ymm\[^\n\]*ymm" } } */
+/* { dg-final { scan-assembler-not "gather\[^\n\]*xmm\[^\n\]*ymm" } } */
+/* { dg-final { scan-assembler-not "gather\[^\n\]*ymm\[^\n\]*xmm" } } */
+/* { dg-final { scan-assembler-not "gather\[^\n\]*xmm\[^\n\]*xmm" } } */
+/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 16 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-3.c
new file mode 100644
index 000000000..5e20dd889
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-3.c
@@ -0,0 +1,169 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-options "-O3 -mavx512f -ffast-math" } */
+
+#include "avx512f-check.h"
+
+#define N 1024
+float f[N];
+double d[N];
+int k[N];
+float *l[N];
+double *n[N];
+int **m[N];
+long q[N];
+long long **o[N];
+long long t[N];
+long long *r[N];
+int *s[N];
+
+__attribute__((noinline, noclone)) float
+f1 (void)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += f[k[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) float
+f2 (float *p)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += p[k[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) float
+f3 (void)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += *l[i];
+  return g;
+}
+
+__attribute__((noinline, noclone)) int
+f4 (void)
+{
+  int i;
+  int g = 0;
+  for (i = 0; i < N / 2; i++)
+    g += **m[i];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f5 (void)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += d[k[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f6 (double *p)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += p[k[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f7 (void)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += *n[i];
+  return g;
+}
+
+__attribute__((noinline, noclone)) int
+f8 (void)
+{
+  int i;
+  int g = 0;
+  for (i = 0; i < N / 2; i++)
+    g += **o[i];
+  return g;
+}
+
+__attribute__((noinline, noclone)) float
+f9 (void)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += f[q[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) float
+f10 (float *p)
+{
+  int i;
+  float g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += p[q[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f11 (void)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += d[q[i]];
+  return g;
+}
+
+__attribute__((noinline, noclone)) double
+f12 (double *p)
+{
+  int i;
+  double g = 0.0;
+  for (i = 0; i < N / 2; i++)
+    g += p[q[i]];
+  return g;
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      asm ("");
+      f[i] = -256.0f + i;
+      d[i] = -258.0 + i;
+      k[i] = (i * 731) & (N - 1);
+      q[i] = (i * 657) & (N - 1);
+      t[i] = (i * 657) & (N - 1);
+      l[i] = &f[(i * 239) & (N - 1)];
+      n[i] = &d[(i * 271) & (N - 1)];
+      r[i] = &t[(i * 323) & (N - 1)];
+      s[i] = &k[(i * 565) & (N - 1)];
+      m[i] = &s[(i * 13) & (N - 1)];
+      o[i] = &r[(i * 19) & (N - 1)];
+    }
+
+  if (f1 () != 136448.0f || f2 (f) != 136448.0f || f3 () != 130304.0)
+    abort ();
+  if (f4 () != 261376 || f5 () != 135424.0 || f6 (d) != 135424.0)
+    abort ();
+  if (f7 () != 129280.0 || f8 () != 259840L || f9 () != 130816.0f)
+    abort ();
+  if (f10 (f) != 130816.0f || f11 () != 129792.0 || f12 (d) != 129792.0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-4.c
new file mode 100644
index 000000000..bea8c24b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-4.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-options "-O3 -mavx512f" } */
+
+#include "avx512f-check.h"
+
+#define N 1024
+int a[N], b[N], c[N], d[N];
+
+__attribute__((noinline, noclone)) void
+foo (float *__restrict p, float *__restrict q, float *__restrict r,
+     int s1, int s2, int s3)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    p[i] = q[a[i] * s1 + b[i] * s2 + s3] * r[c[i] * s1 + d[i] * s2 + s3];
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  float e[N], f[N], g[N];
+  for (i = 0; i < N; i++)
+    {
+      a[i] = (i * 7) & (N / 8 - 1);
+      b[i] = (i * 13) & (N / 8 - 1);
+      c[i] = (i * 23) & (N / 8 - 1);
+      d[i] = (i * 5) & (N / 8 - 1);
+      e[i] = 16.5 + i;
+      f[i] = 127.5 - i;
+    }
+  foo (g, e, f, 3, 2, 4);
+  for (i = 0; i < N; i++)
+    if (g[i] != (float) ((20.5 + a[i] * 3 + b[i] * 2)
+			 * (123.5 - c[i] * 3 - d[i] * 2)))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-5.c
new file mode 100644
index 000000000..d2237da15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-gather-5.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx512f" } */
+
+#include "avx512f-gather-4.c"
+
+/* { dg-final { scan-assembler "gather\[^\n\]*zmm" } } */
+/* { dg-final { scan-assembler-not "gather\[^\n\]*ymm\[^\n\]*ymm" } } */
+/* { dg-final { scan-assembler-not "gather\[^\n\]*xmm\[^\n\]*ymm" } } */
+/* { dg-final { scan-assembler-not "gather\[^\n\]*ymm\[^\n\]*xmm" } } */
+/* { dg-final { scan-assembler-not "gather\[^\n\]*xmm\[^\n\]*xmm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-helper.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-helper.h
new file mode 100644
index 000000000..61b2e90d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-helper.h
@@ -0,0 +1,96 @@
+/* This file is used to reduce a number of runtime tests for AVX512F
+   instructions.  Idea is to create one file per instruction -
+   avx512f-insn-2.c - using defines from this file instead of intrinsic
+   name, vector length etc.  Then dg-options are set with appropriate
+   -Dwhatever options in that .c file producing tests for specific
+   length.  */
+
+#if defined (AVX512F)
+#include "avx512f-check.h"
+#elif defined (AVX512ER)
+#include "avx512er-check.h"
+#elif defined (AVX512CD)
+#include "avx512cd-check.h"
+#endif
+
+/* Macros expansion.  */
+#define CONCAT(a,b,c) a ## b ## c
+#define EVAL(a,b,c) CONCAT(a,b,c)
+
+/* Value to be written into destination.
+   We have one value for all types so it must be small enough
+   to fit into signed char.  */
+#define DEFAULT_VALUE 117
+
+#define MAKE_MASK_MERGE(NAME, TYPE)				      \
+static void							      \
+__attribute__((noinline, unused))				      \
+merge_masking_##NAME (TYPE *arr, unsigned long long mask, int size)   \
+{								      \
+  int i;							      \
+  for (i = 0; i < size; i++)					      \
+    {								      \
+      arr[i] = (mask & (1LL << i)) ? arr[i] : DEFAULT_VALUE;	      \
+    }								      \
+}
+
+MAKE_MASK_MERGE(i_b, char)
+MAKE_MASK_MERGE(i_w, short)
+MAKE_MASK_MERGE(i_d, int)
+MAKE_MASK_MERGE(i_q, long long)
+MAKE_MASK_MERGE(, float)
+MAKE_MASK_MERGE(d, double)
+
+#define MASK_MERGE(TYPE) merge_masking_##TYPE
+
+#define MAKE_MASK_ZERO(NAME, TYPE)				      \
+static void							      \
+__attribute__((noinline, unused))				      \
+zero_masking_##NAME (TYPE *arr, unsigned long long mask, int size)    \
+{								      \
+  int i;							      \
+  for (i = 0; i < size; i++)					      \
+    {								      \
+      arr[i] = (mask & (1LL << i)) ? arr[i] : 0;		      \
+    }								      \
+}
+
+MAKE_MASK_ZERO(i_b, char)
+MAKE_MASK_ZERO(i_w, short)
+MAKE_MASK_ZERO(i_d, int)
+MAKE_MASK_ZERO(i_q, long long)
+MAKE_MASK_ZERO(, float)
+MAKE_MASK_ZERO(d, double)
+
+#define MASK_ZERO(TYPE) zero_masking_##TYPE
+
+/* Intrinsic being tested.  */
+#define INTRINSIC(NAME) EVAL(_mm, AVX512F_LEN, NAME)
+/* Unions used for testing (for example union512d, union256d etc.).  */
+#define UNION_TYPE(SIZE, NAME) EVAL(union, SIZE, NAME)
+/* Corresponding union check.  */
+#define UNION_CHECK(SIZE, NAME) EVAL(check_union, SIZE, NAME)
+/* Corresponding fp union check.  */
+#define UNION_FP_CHECK(SIZE, NAME) EVAL(check_fp_union, SIZE, NAME)
+/* Corresponding rough union check.  */
+#define UNION_ROUGH_CHECK(SIZE, NAME) \
+  EVAL(check_rough_union, SIZE, NAME)
+/* Function which tests intrinsic for given length.  */
+#define TEST EVAL(test_, AVX512F_LEN,)
+/* Function which calculates result.  */
+#define CALC EVAL(calc_, AVX512F_LEN,)
+
+#define AVX512F_LEN 512
+#define AVX512F_LEN_HALF 256
+static void test_512 ();
+
+#if defined (AVX512F)
+void
+avx512f_test (void) { test_512 (); }
+#elif defined (AVX512CD)
+void
+avx512cd_test (void) { test_512 (); }
+#elif defined (AVX512ER)
+void
+avx512er_test (void) { test_512 (); }
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherd512-1.c
new file mode 100644
index 000000000..7a0ee9978
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherd512-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpgatherdd\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*zmm\[0-9\]{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, idx;
+volatile __mmask16 m16;
+int *base;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_i32gather_epi32 (idx, base, 8);
+  x = _mm512_mask_i32gather_epi32 (x, m16, idx, base, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherd512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherd512-2.c
new file mode 100644
index 000000000..d89ef048d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherd512-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_gatherdd (int *res, __mmask16 m16, int *idx,
+		  int *src, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      if (m16 & (1 << i))
+	r[i] = *(int *) (((unsigned char *) src) + idx[i] * scale);
+      else
+	r[i] = res[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512i_d idx, res;
+  int src[16];
+  int res_ref[16];
+  __mmask16 m16 = 0xBC5D;
+
+  for (i = 0; i < 16; i++)
+    {
+      src[i] = 1973 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm512_mask_i32gather_epi32 (res.x, m16, idx.x, src, SCALE);
+  compute_gatherdd (res.a, m16, idx.a, src, SCALE, res_ref);
+
+  if (check_union512i_d (res, res_ref))
+    abort ();
+
+  res.x = _mm512_i32gather_epi32 (idx.x, src, SCALE);
+  compute_gatherdd (res.a, 0xFFFF, idx.a, src, SCALE, res_ref);
+
+  if (check_union512i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherpd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherpd512-1.c
new file mode 100644
index 000000000..88b9ae624
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherpd512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vgatherdpd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*zmm\[0-9\]{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m256i idx;
+volatile __mmask8 m8;
+double *base;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_i32gather_pd (idx, base, 8);
+  x = _mm512_mask_i32gather_pd (x, m8, idx, base, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherpd512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherpd512-2.c
new file mode 100644
index 000000000..3af491548
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherpd512-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_gatherdpd (double *res, __mmask8 m8, int *idx,
+		   double *src, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	r[i] = *(double *) (((unsigned char *) src) + idx[i] * scale);
+      else
+	r[i] = res[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512d res;
+  union256i_d idx;
+  double src[8];
+  double res_ref[8];
+  __mmask8 m8 = 0xC5;
+
+  res.x = _mm512_setzero_pd();
+
+  for (i = 0; i < 8; i++)
+    {
+      src[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm512_mask_i32gather_pd (res.x, m8, idx.x, src, SCALE);
+  compute_gatherdpd (res.a, m8, idx.a, src, SCALE, res_ref);
+
+  if (check_union512d (res, res_ref))
+    abort ();
+
+  res.x = _mm512_i32gather_pd (idx.x, src, SCALE);
+  compute_gatherdpd (res.a, 0xFF, idx.a, src, SCALE, res_ref);
+
+  if (check_union512d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherps512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherps512-1.c
new file mode 100644
index 000000000..6abc2301d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherps512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vgatherdps\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*zmm\[0-9\]{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m512i idx;
+volatile __mmask16 m16;
+float *base;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_i32gather_ps (idx, base, 8);
+  x = _mm512_mask_i32gather_ps (x, m16, idx, base, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherps512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherps512-2.c
new file mode 100644
index 000000000..691413ab2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherps512-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_gatherdps (float *res, __mmask16 m16, int *idx,
+		   float *src, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      if (m16 & (1 << i))
+	r[i] = *(float *) (((unsigned char *) src) + idx[i] * scale);
+      else
+	r[i] = res[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512 res;
+  union512i_d idx;
+  float src[16];
+  float res_ref[16];
+  __mmask16 m16 = 0xBC5D;
+
+  res.x = _mm512_setzero_ps();
+
+  for (i = 0; i < 16; i++)
+    {
+      src[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm512_mask_i32gather_ps (res.x, m16, idx.x, src, SCALE);
+  compute_gatherdps (res.a, m16, idx.a, src, SCALE, res_ref);
+
+  if (check_union512 (res, res_ref))
+    abort ();
+
+  res.x = _mm512_i32gather_ps (idx.x, src, SCALE);
+  compute_gatherdps (res.a, 0xFFFF, idx.a, src, SCALE, res_ref);
+
+  if (check_union512 (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherq512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherq512-1.c
new file mode 100644
index 000000000..ee4491eb1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherq512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpgatherdq\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*zmm\[0-9\]{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m256i idx;
+volatile __mmask8 m8;
+long long *base;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_i32gather_epi64 (idx, base, 8);
+  x = _mm512_mask_i32gather_epi64 (x, m8, idx, base, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherq512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherq512-2.c
new file mode 100644
index 000000000..4d472faa2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32gatherq512-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_gatherdq (long long *res, __mmask8 m8, int *idx,
+		  long long *src, int scale, long long *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	r[i] = *(long long *)
+	  (((unsigned char *) src) + idx[i] * scale);
+      else
+	r[i] = res[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union256i_d idx;
+  union512i_q res;
+  long long src[8];
+  long long res_ref[8];
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src[i] = 1983 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm512_mask_i32gather_epi64 (res.x, m8, idx.x, src, SCALE);
+  compute_gatherdq (res.a, m8, idx.a, src, SCALE, res_ref);
+
+  if (check_union512i_q (res, res_ref))
+    abort ();
+
+  res.x = _mm512_i32gather_epi64 (idx.x, src, SCALE);
+  compute_gatherdq (res.a, 0xFF, idx.a, src, SCALE, res_ref);
+
+  if (check_union512i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterd512-1.c
new file mode 100644
index 000000000..7a5c31166
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterd512-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpscatterdd\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*zmm\[0-9\]\[^\n\]*{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512i src, idx;
+volatile __mmask16 m16;
+int *addr;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_i32scatter_epi32 (addr, idx, src, 8);
+  _mm512_mask_i32scatter_epi32 (addr, m16, idx, src, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterd512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterd512-2.c
new file mode 100644
index 000000000..569690021
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterd512-2.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_scatterdd (__mmask16 m16, int *idx,
+		   int *src, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      if (m16 & (1 << i))
+	*(int *) (((unsigned char *) r) + idx[i] * scale) = src[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512i_d src, idx;
+  int res[16] = { 0 };
+  int res_ref[16] = { 0 };
+  __mmask16 m16 = 0xBC5D;
+
+  for (i = 0; i < 16; i++)
+    {
+      src.a[i] = 1973 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 4) >> 1;
+    }
+
+  _mm512_mask_i32scatter_epi32 (res, m16, idx.x, src.x, SCALE);
+  compute_scatterdd (m16, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVi (res, res_ref, 16))
+    abort ();
+
+  _mm512_i32scatter_epi32 (res, idx.x, src.x, SCALE);
+  compute_scatterdd (0xFFFF, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVi (res, res_ref, 16))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterpd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterpd512-1.c
new file mode 100644
index 000000000..6c5ddc0a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterpd512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vscatterdpd\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512d src;
+volatile __m256i idx;
+volatile __mmask8 m8;
+double *addr;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_i32scatter_pd (addr, idx, src, 8);
+  _mm512_mask_i32scatter_pd (addr, m8, idx, src, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterpd512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterpd512-2.c
new file mode 100644
index 000000000..987b3f437
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterpd512-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_scatterdpd (__mmask8 m8, int *idx, double *src,
+		    int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	*(double *) (((unsigned char *) r) + idx[i] * scale) = src[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512d src;
+  union256i_d idx;
+  double res[8] = { 0.0 };
+  double res_ref[8] = { 0.0 };
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 8) >> 1;
+    }
+
+  _mm512_mask_i32scatter_pd (res, m8, idx.x, src.x, SCALE);
+  compute_scatterdpd (m8, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVd (res, res_ref, 8))
+    abort ();
+
+  _mm512_i32scatter_pd (res, idx.x, src.x, SCALE);
+  compute_scatterdpd (0xFF, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVd (res, res_ref, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterps512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterps512-1.c
new file mode 100644
index 000000000..c24344a28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterps512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vscatterdps\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*zmm\[0-9\]\[^\n\]*{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512 src;
+volatile __m512i idx;
+volatile __mmask16 m16;
+float *addr;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_i32scatter_ps (addr, idx, src, 8);
+  _mm512_mask_i32scatter_ps (addr, m16, idx, src, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterps512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterps512-2.c
new file mode 100644
index 000000000..8604c8d5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterps512-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_scatterdps (__mmask16 m16, int *idx,
+		    float *src, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      if (m16 & (1 << i))
+	*(float *) (((unsigned char *) r) + idx[i] * scale) = src[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512 src;
+  union512i_d idx;
+  float res[16] = { 0.0 };
+  float res_ref[16] = { 0.0 };
+  __mmask16 m16 = 0xBC5D;
+
+  for (i = 0; i < 16; i++)
+    {
+      src.a[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 4) >> 1;
+    }
+
+  _mm512_mask_i32scatter_ps (res, m16, idx.x, src.x, SCALE);
+  compute_scatterdps (m16, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVf (res, res_ref, 16))
+    abort ();
+
+  _mm512_i32scatter_ps (res, idx.x, src.x, SCALE);
+  compute_scatterdps (0xFFFF, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVf (res, res_ref, 16))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterq512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterq512-1.c
new file mode 100644
index 000000000..5b2817546
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterq512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpscatterdq\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*ymm\[0-9\]\[^\n\]*{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512i src;
+volatile __m256i idx;
+volatile __mmask8 m8;
+long long *addr;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_i32scatter_epi64 (addr, idx, src, 8);
+  _mm512_mask_i32scatter_epi64 (addr, m8, idx, src, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterq512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterq512-2.c
new file mode 100644
index 000000000..fe5c3ade1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i32scatterq512-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_scatterdq (__mmask8 m8, int *idx, long long *src,
+		   int scale, long long *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	*(long long *) (((unsigned char *) r) + idx[i] * scale) =
+	  src[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union256i_d idx;
+  union512i_q src;
+  long long res[8] = { 0 };
+  long long res_ref[8] = { 0 };
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 1983 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 8) >> 1;
+    }
+
+  _mm512_mask_i32scatter_epi64 (res, m8, idx.x, src.x, SCALE);
+  compute_scatterdq (m8, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVl (res, res_ref, 8))
+    abort ();
+
+  _mm512_i32scatter_epi64 (res, idx.x, src.x, SCALE);
+  compute_scatterdq (0xFF, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVl (res, res_ref, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherd512-1.c
new file mode 100644
index 000000000..66dcf6f60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherd512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpgatherqd\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*ymm\[0-9\]{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_i64gather_epi32 (idx, base, 8);
+  x = _mm512_mask_i64gather_epi32 (x, m8, idx, base, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherd512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherd512-2.c
new file mode 100644
index 000000000..dff818db4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherd512-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_gatherqd (int *res, __mmask8 m8, long long *idx,
+		  int *src, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	r[i] = *(int *) (((unsigned char *) src) + idx[i] * scale);
+      else
+	r[i] = res[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union256i_d res;
+  union512i_q idx;
+  int src[8];
+  int res_ref[8];
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src[i] = 1973 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm512_mask_i64gather_epi32 (res.x, m8, idx.x, src, SCALE);
+  compute_gatherqd (res.a, m8, idx.a, src, SCALE, res_ref);
+
+  if (check_union256i_d (res, res_ref))
+    abort ();
+
+  res.x = _mm512_i64gather_epi32 (idx.x, src, SCALE);
+  compute_gatherqd (res.a, 0xFF, idx.a, src, SCALE, res_ref);
+
+  if (check_union256i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherpd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherpd512-1.c
new file mode 100644
index 000000000..4a3df8904
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherpd512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vgatherqpd\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*zmm\[0-9\]{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m512i idx;
+volatile __mmask8 m8;
+double *base;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_i64gather_pd (idx, base, 8);
+  x = _mm512_mask_i64gather_pd (x, m8, idx, base, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherpd512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherpd512-2.c
new file mode 100644
index 000000000..7cb6d82eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherpd512-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_gatherqpd (double *res, __mmask8 m8, long long *idx,
+		   double *src, int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	r[i] = *(double *) (((unsigned char *) src) + idx[i] * scale);
+      else
+	r[i] = res[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512d res;
+  union512i_q idx;
+  double src[8];
+  double res_ref[8];
+  __mmask8 m8 = 0xC5;
+
+  res.x = _mm512_setzero_pd();
+
+  for (i = 0; i < 8; i++)
+    {
+      src[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm512_mask_i64gather_pd (res.x, m8, idx.x, src, SCALE);
+  compute_gatherqpd (res.a, m8, idx.a, src, SCALE, res_ref);
+
+  if (check_union512d (res, res_ref))
+    abort ();
+
+  res.x = _mm512_i64gather_pd (idx.x, src, SCALE);
+  compute_gatherqpd (res.a, 0xFF, idx.a, src, SCALE, res_ref);
+
+  if (check_union512d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherps512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherps512-1.c
new file mode 100644
index 000000000..4caee0569
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherps512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vgatherqps\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*ymm\[0-9\]{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m256 x;
+volatile __m512i idx;
+volatile __mmask8 m8;
+float *base;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_i64gather_ps (idx, base, 8);
+  x = _mm512_mask_i64gather_ps (x, m8, idx, base, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherps512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherps512-2.c
new file mode 100644
index 000000000..8ed0fcef4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherps512-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_gatherqps (float *res, __mmask8 m8, long long *idx,
+		   float *src, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	r[i] = *(float *) (((unsigned char *) src) + idx[i] * scale);
+      else
+	r[i] = res[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union256 res;
+  union512i_q idx;
+  float src[8];
+  float res_ref[8];
+  __mmask8 m8 = 0xC5;
+
+  res.x = _mm256_setzero_ps();
+
+  for (i = 0; i < 8; i++)
+    {
+      src[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 4) >> 1;
+    }
+
+  res.x = _mm512_mask_i64gather_ps (res.x, m8, idx.x, src, SCALE);
+  compute_gatherqps (res.a, m8, idx.a, src, SCALE, res_ref);
+
+  if (check_union256 (res, res_ref))
+    abort ();
+
+  res.x = _mm512_i64gather_ps (idx.x, src, SCALE);
+  compute_gatherqps (res.a, 0xFF, idx.a, src, SCALE, res_ref);
+
+  if (check_union256 (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherq512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherq512-1.c
new file mode 100644
index 000000000..20d39e748
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherq512-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpgatherqq\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*zmm\[0-9\]{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, idx;
+volatile __mmask8 m8;
+long long *base;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_i64gather_epi64 (idx, base, 8);
+  x = _mm512_mask_i64gather_epi64 (x, m8, idx, base, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherq512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherq512-2.c
new file mode 100644
index 000000000..134fd18b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64gatherq512-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_gatherqq (long long *res, __mmask8 m8, long long *idx,
+		  long long *src, int scale, long long *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	r[i] = *(long long *)
+	  (((unsigned char *) src) + idx[i] * scale);
+      else
+	r[i] = res[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512i_q idx, res;
+  long long src[8];
+  long long res_ref[8];
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src[i] = 1983 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 8) >> 1;
+    }
+
+  res.x = _mm512_mask_i64gather_epi64 (res.x, m8, idx.x, src, SCALE);
+  compute_gatherqq (res.a, m8, idx.a, src, SCALE, res_ref);
+
+  if (check_union512i_q (res, res_ref))
+    abort ();
+
+  res.x = _mm512_i64gather_epi64 (idx.x, src, SCALE);
+  compute_gatherqq (res.a, 0xFF, idx.a, src, SCALE, res_ref);
+
+  if (check_union512i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterd512-1.c
new file mode 100644
index 000000000..a2f5275d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterd512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpscatterqd\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*zmm\[0-9\]\[^\n\]*{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m256i src;
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *addr;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_i64scatter_epi32 (addr, idx, src, 8);
+  _mm512_mask_i64scatter_epi32 (addr, m8, idx, src, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterd512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterd512-2.c
new file mode 100644
index 000000000..877ef9062
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterd512-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_scatterqd (__mmask8 m8, long long *idx,
+		   int *src, int scale, int *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	*(int *) (((unsigned char *) r) + idx[i] * scale) = src[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union256i_d src;
+  union512i_q idx;
+  int res[8] = { 0 };
+  int res_ref[8] = { 0 };
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 1973 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 4) >> 1;
+    }
+
+  _mm512_mask_i64scatter_epi32 (res, m8, idx.x, src.x, SCALE);
+  compute_scatterqd (m8, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVi (res, res_ref, 8))
+    abort ();
+
+  _mm512_i64scatter_epi32 (res, idx.x, src.x, SCALE);
+  compute_scatterqd (0xFF, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVi (res, res_ref, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterpd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterpd512-1.c
new file mode 100644
index 000000000..288a2183b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterpd512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vscatterqpd\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*zmm\[0-9\]\[^\n\]*{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512d src;
+volatile __m512i idx;
+volatile __mmask8 m8;
+double *addr;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_i64scatter_pd (addr, idx, src, 8);
+  _mm512_mask_i64scatter_pd (addr, m8, idx, src, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterpd512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterpd512-2.c
new file mode 100644
index 000000000..2ded7bc76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterpd512-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_scatterqpd (__mmask8 m8, long long *idx, double *src,
+		    int scale, double *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	*(double *) (((unsigned char *) r) + idx[i] * scale) = src[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512d src;
+  union512i_q idx;
+  double res[8] = { 0.0 };
+  double res_ref[8] = { 0.0 };
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 8) >> 1;
+    }
+
+  _mm512_mask_i64scatter_pd (res, m8, idx.x, src.x, SCALE);
+  compute_scatterqpd (m8, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVd (res, res_ref, 8))
+    abort ();
+
+  _mm512_i64scatter_pd (res, idx.x, src.x, SCALE);
+  compute_scatterqpd (0xFF, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVd (res, res_ref, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterps512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterps512-1.c
new file mode 100644
index 000000000..6a0b05d79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterps512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vscatterqps\[ \\t\]+\[^\n\]*ymm\[0-9\]\[^\n\]*zmm\[0-9\]\[^\n\]*{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m256 src;
+volatile __m512i idx;
+volatile __mmask8 m8;
+float *addr;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_i64scatter_ps (addr, idx, src, 8);
+  _mm512_mask_i64scatter_ps (addr, m8, idx, src, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterps512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterps512-2.c
new file mode 100644
index 000000000..4a74d4667
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterps512-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_scatterqps (__mmask8 m8, long long *idx,
+		    float *src, int scale, float *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	*(float *) (((unsigned char *) r) + idx[i] * scale) = src[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union256 src;
+  union512i_q idx;
+  float res[8] = { 0.0 };
+  float res_ref[8] = { 0.0 };
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 2.718281828459045 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+	 divide by 2 to demonstrate scale */
+      idx.a[i] = (32 - (i + 1) * 4) >> 1;
+    }
+
+  _mm512_mask_i64scatter_ps (res, m8, idx.x, src.x, SCALE);
+  compute_scatterqps (m8, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVf (res, res_ref, 8))
+    abort ();
+
+  _mm512_i64scatter_ps (res, idx.x, src.x, SCALE);
+  compute_scatterqps (0xFF, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVf (res, res_ref, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterq512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterq512-1.c
new file mode 100644
index 000000000..10a7a4be6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterq512-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpscatterqq\[ \\t\]+\[^\n\]*zmm\[0-9\]\[^\n\]*zmm\[0-9\]\[^\n\]*{%k\[1-7\]}" 2 } } */
+
+#include <immintrin.h>
+
+volatile __m512i src, idx;
+volatile __mmask8 m8;
+long long *addr;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_i64scatter_epi64 (addr, idx, src, 8);
+  _mm512_mask_i64scatter_epi64 (addr, m8, idx, src, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterq512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterq512-2.c
new file mode 100644
index 000000000..975973f34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-i64scatterq512-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+#define SCALE 2
+
+static void
+compute_scatterqq (__mmask8 m8, long long *idx, long long *src,
+		   int scale, long long *r)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      if (m8 & (1 << i))
+	*(long long *) (((unsigned char *) r) + idx[i] * scale) =
+	  src[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  union512i_q src, idx;
+  long long res[8] = { 0 };
+  long long res_ref[8] = { 0 };
+  __mmask8 m8 = 0xC5;
+
+  for (i = 0; i < 8; i++)
+    {
+      src.a[i] = 1983 * (i + 1) * (i + 2);
+
+      /* About to gather in reverse order,
+         divide by 2 to demonstrate scale */
+      idx.a[i] = (64 - (i + 1) * 8) >> 1;
+    }
+
+  _mm512_mask_i64scatter_epi64 (res, m8, idx.x, src.x, SCALE);
+  compute_scatterqq (m8, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVl (res, res_ref, 8))
+    abort ();
+
+  _mm512_i64scatter_epi64 (res, idx.x, src.x, SCALE);
+  compute_scatterqq (0xFF, idx.a, src.a, SCALE, res_ref);
+
+  if (checkVl (res, res_ref, 8))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-inline-asm.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-inline-asm.c
new file mode 100644
index 000000000..2557eab64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-inline-asm.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static void
+init_vpadd_mask (int* dst, int *src1, int *src2, int seed)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      dst[i] = -1;
+      src1[i] = seed * 2 * i + 1;
+      src2[i] = seed * 2 * i;
+    }
+}
+
+static inline void
+calc_vpadd_mask_zeroed (int *dst, __mmask16 m, int *src1, int *src2)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      if (m & (1 << i))
+	dst[i] = src1[i] + src2[i];
+      else
+	dst[i] = 0;
+    }
+}
+
+void static
+avx512f_test (void)
+{
+  /* Checking mask arithmetic instruction */
+
+  __mmask16 msk_dst, msk_src1, msk_src2, msk_dst_ref;
+
+  msk_src1 = 0x0FFB;
+  msk_src2 = 0x0F0F;
+
+  asm ("kandw\t%2, %1, %0"
+       : "=k" (msk_dst)
+       : "k" (msk_src1), "k" (msk_src2));
+
+  msk_dst_ref =  _mm512_kand (msk_src1, msk_src2);
+  if (msk_dst != msk_dst_ref)
+    abort ();
+
+
+  /* Checking zero-masked vector instruction */
+  union512i_d dst, src1, src2;
+  int dst_ref[16];
+
+  init_vpadd_mask (dst.a,   src1.a, src2.a, 1);
+  init_vpadd_mask (dst_ref, src1.a, src2.a, 1);
+
+  asm ("vpaddd\t%2, %1, %0 %{%3%}%{z%}"
+       : "=x" (dst.x)
+       : "x" (src1.x), "x" (src2.x), "Yk" (msk_dst));
+
+  calc_vpadd_mask_zeroed (dst_ref, msk_dst, src1.a, src2.a);
+
+  if (check_union512i_d (dst, dst_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kandnw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kandnw-1.c
new file mode 100644
index 000000000..3d777c830
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kandnw-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "kandnw\[ \\t\]+\[^\n\]*%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test ()
+{
+  __mmask16 k1, k2, k3;
+  volatile __m512 x;
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (1) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (2) );
+
+  k3 = _mm512_kandn (k1, k2);
+  x = _mm512_mask_add_ps (x, k3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kandw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kandw-1.c
new file mode 100644
index 000000000..19a3cf4db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kandw-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "kandw\[ \\t\]+\[^\n\]*%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test ()
+{
+  __mmask16 k1, k2, k3;
+  volatile __m512 x;
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (1) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (2) );
+
+  k3 = _mm512_kand (k1, k2);
+  x = _mm512_mask_add_ps (x, k3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c
new file mode 100644
index 000000000..df7fc9b7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-klogic-2.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void
+avx512f_test (void)
+{
+  __mmask16 dst, src1, src2, dst_ref;
+  volatile __m512 x;
+
+  __asm__( "kmovw %1, %0" : "=k" (src1) : "r" (0x0FFF) );
+  __asm__( "kmovw %1, %0" : "=k" (src2) : "r" (0x0F0F) );
+
+  dst = _mm512_kand (src1, src2);
+  x = _mm512_mask_add_ps (x, dst, x, x);
+  dst_ref = src1 & src2;
+  if (dst != dst_ref)
+    abort ();
+
+  dst = _mm512_kandn (src1, src2);
+  x = _mm512_mask_add_ps (x, dst, x, x);
+  dst_ref = ~src1 & src2;
+  if (dst != dst_ref)
+    abort ();
+
+  dst = _mm512_kor (src1, src2);
+  x = _mm512_mask_add_ps (x, dst, x, x);
+  dst_ref = src1 | src2;
+  if (dst != dst_ref)
+    abort ();
+
+  dst = _mm512_kxnor (src1, src2);
+  x = _mm512_mask_add_ps (x, dst, x, x);
+  dst_ref = ~(src1 ^ src2);
+  if (dst != dst_ref)
+    abort ();
+
+  dst = _mm512_kxor (src1, src2);
+  x = _mm512_mask_add_ps (x, dst, x, x);
+  dst_ref = src1 ^ src2;
+  if (dst != dst_ref)
+    abort ();
+
+  dst = _mm512_knot (src1);
+  x = _mm512_mask_add_ps (x, dst, x, x);
+  dst_ref = ~src1;
+  if (dst != dst_ref)
+    abort ();
+
+  dst = _mm512_kunpackb (src1, src2);
+  x = _mm512_mask_add_ps (x, dst, x, x);
+  dst_ref = 0xFF0F;
+
+  if (dst != dst_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kmovw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kmovw-1.c
new file mode 100644
index 000000000..9c20472af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kmovw-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "kmovw\[ \\t\]+\[^\n\]*%k\[0-7\]" } } */
+
+#include <immintrin.h>
+volatile __mmask16 k1;
+
+void
+avx512f_test ()
+{
+  k1 = _mm512_kmov (11);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-knotw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-knotw-1.c
new file mode 100644
index 000000000..a8f8f10b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-knotw-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "knotw\[ \\t\]+\[^\n\]*%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test ()
+{
+  __mmask16 k1, k2;
+  volatile __m512 x;
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (45) );
+
+  k2 = _mm512_knot (k1);
+
+  x = _mm512_mask_add_ps (x, k1, x, x);
+  x = _mm512_mask_add_ps (x, k2, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kortestw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kortestw-1.c
new file mode 100644
index 000000000..a3cdd4a1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kortestw-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx512f" } */
+/* { dg-final { scan-assembler-times "kortestw\[ \\t\]+\[^\n\]*%k\[0-7\]" 4 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test () {
+  volatile __mmask16 k1;
+  __mmask16 k2;
+  volatile __mmask8 k3;
+  __mmask8 k4;
+
+  volatile short r;
+
+  /* Check that appropriate insn sequence is generated at -O0.  */
+  r = _mm512_kortestc (k1, k2);
+  r = _mm512_kortestz (k1, k2);
+
+  r = _mm512_kortestc (k3, k4);
+  r = _mm512_kortestz (k3, k4);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kortestw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kortestw-2.c
new file mode 100644
index 000000000..4b9cadcc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kortestw-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void
+avx512f_test () {
+  volatile __mmask16 k1;
+  __mmask16 k2;
+  volatile short r = 0;
+
+  /* Test kortestc.  */
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (0) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (45) );
+
+  r += _mm512_kortestc (k1, k2);
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (0) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (0) );
+
+  r += _mm512_kortestc (k1, k2);
+  if (r)
+    abort ();
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (-1) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (0) );
+
+  r += _mm512_kortestc (k1, k2);
+  if (!r)
+    abort ();
+
+  r = 0;
+  /* Test kortestz.  */
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (0) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (45) );
+
+  r += _mm512_kortestz (k1, k2);
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (-1) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (0) );
+
+  r += _mm512_kortestz (k1, k2);
+  if (r)
+    abort ();
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (0) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (0) );
+
+  r += _mm512_kortestz (k1, k2);
+  if (!r)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-korw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-korw-1.c
new file mode 100644
index 000000000..96f837b96
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-korw-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "korw\[ \\t\]+\[^\n\]*%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test ()
+{
+  __mmask16 k1, k2, k3;
+  volatile __m512 x;
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (1) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (2) );
+
+  k3 = _mm512_kor (k1, k2);
+  x = _mm512_mask_add_ps (x, k3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kunpckbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kunpckbw-1.c
new file mode 100644
index 000000000..bc55f8b30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kunpckbw-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "kunpckbw\[ \\t\]+\[^\n\]*%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test () {
+  __mmask16 k1, k2, k3;
+  volatile __m512 x;
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (1) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (2) );
+
+  k3 = _mm512_kunpackb (k1, k2);
+  x = _mm512_mask_add_ps (x, k3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kxnorw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kxnorw-1.c
new file mode 100644
index 000000000..8b12b2ac8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kxnorw-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "kxnorw\[ \\t\]+\[^\n\]*%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test ()
+{
+  __mmask16 k1, k2, k3;
+  volatile __m512 x;
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (1) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (2) );
+
+  k3 = _mm512_kxnor (k1, k2);
+  x = _mm512_mask_add_ps (x, k3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kxorw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kxorw-1.c
new file mode 100644
index 000000000..7ae1bc462
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-kxorw-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "kxorw\[ \\t\]+\[^\n\]*%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test ()
+{
+  __mmask16 k1, k2, k3;
+  volatile __m512 x;
+
+  __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (1) );
+  __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (2) );
+
+  k3 = _mm512_kxor (k1, k2);
+  x = _mm512_mask_add_ps (x, k3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-mask-type.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-mask-type.h
new file mode 100644
index 000000000..2dacdd67a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-mask-type.h
@@ -0,0 +1,10 @@
+/* Type of mask.  */
+#if SIZE <= 8
+#define MASK_TYPE __mmask8
+#define MASK_VALUE 0xB9
+#define MASK_ALL_ONES 0xFF
+#elif SIZE <= 16
+#define MASK_TYPE __mmask16
+#define MASK_VALUE 0xA6BA
+#define MASK_ALL_ONES 0xFFFF
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-os-support.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-os-support.h
new file mode 100644
index 000000000..deefa5e11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-os-support.h
@@ -0,0 +1,10 @@
+/* Check if the OS supports executing AVX512F instructions.  */
+
+static int
+avx512f_os_support (void)
+{
+  unsigned int eax, edx;
+
+  __asm__ ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (0));
+  return (eax & 230) == 230;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-rounding.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-rounding.c
new file mode 100644
index 000000000..254e3a418
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-rounding.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx512f" } */
+
+#include <x86intrin.h>
+
+int
+test_rounding (__m128d x, int r)
+{
+  return _mm_cvt_roundsd_i32 (x, r); /* { dg-error "incorrect rounding operand." } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-1.c
new file mode 100644
index 000000000..0ae82bc41
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-1.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512
+__attribute__ ((noinline))
+foo (float *v)
+{
+  return _mm512_set_ps (v[15], v[14], v[13], v[12],
+			v[11], v[10], v[9], v[8],
+			v[7], v[6], v[5], v[4],
+			v[3], v[2], v[1], v[0]);
+}
+
+static __m512
+__attribute__ ((noinline))
+foo_r (float *v)
+{
+  return _mm512_setr_ps (v[0], v[1], v[2], v[3],
+			 v[4], v[5], v[6], v[7],
+			 v[8], v[9], v[10], v[11],
+			 v[12], v[13], v[14], v[15]);
+}
+
+static void
+avx512f_test (void)
+{
+  float v[16] = { -3.3, 2.6, 1.48, 9.104, -23.9, 17, -13.48, 4,
+		  69.78, 0.33, 81, 0.4, -8.9, -173.37, 0.8, 68 };
+  union512 res;
+
+  res.x = foo (v);
+
+  if (check_union512 (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_ps ();
+
+  res.x = foo_r (v);
+
+  if (check_union512 (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-2.c
new file mode 100644
index 000000000..1884c2f33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512
+__attribute__ ((noinline))
+foo (float x1, float x2, float x3, float x4,
+     float x5, float x6, float x7, float x8,
+     float x9, float x10, float x11, float x12,
+     float x13, float x14, float x15, float x16)
+{
+  return _mm512_set_ps (x1, x2, x3, x4, x5, x6, x7, x8,
+			x9, x10, x11, x12, x13, x14, x15, x16);
+}
+
+static __m512
+__attribute__ ((noinline))
+foo_r (float x1, float x2, float x3, float x4,
+       float x5, float x6, float x7, float x8,
+       float x9, float x10, float x11, float x12,
+       float x13, float x14, float x15, float x16)
+{
+  return _mm512_setr_ps (x16, x15, x14, x13, x12, x11, x10, x9,
+			 x8, x7, x6, x5, x4, x3, x2, x1);
+}
+
+static void
+avx512f_test (void)
+{
+  float v[16] = { -3.3, 2.6, 1.48, 9.104, -23.9, 17, -13.48, 4,
+		  69.78, 0.33, 81, 0.4, -8.9, -173.37, 0.8, 68 };
+  union512 res;
+
+  res.x = foo (v[15], v[14], v[13], v[12], v[11], v[10], v[9], v[8],
+	       v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union512 (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_ps ();
+
+  res.x = foo_r (v[15], v[14], v[13], v[12], v[11], v[10], v[9], v[8],
+		 v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union512 (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-3.c
new file mode 100644
index 000000000..7ec166a58
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-3.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512
+__attribute__ ((noinline))
+foo (float x)
+{
+  return _mm512_set_ps (x, x, x, x, x, x, x, x,
+			x, x, x, x, x, x, x, x);
+}
+
+static __m512
+__attribute__ ((noinline))
+foo_r (float x)
+{
+  return _mm512_setr_ps (x, x, x, x, x, x, x, x,
+			 x, x, x, x, x, x, x, x);
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  float e = 34.5;
+  float v[16];
+  union512 res;
+
+  for (i = 0; i < 16; i++)
+    v[i] = e;
+
+  res.x = foo (e);
+
+  if (check_union512 (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_ps ();
+
+  res.x = foo_r (e);
+
+  if (check_union512 (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-4.c
new file mode 100644
index 000000000..cd37e0064
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-4.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512
+__attribute__ ((noinline))
+foo (float x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm512_set_ps (x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 14:
+      return _mm512_set_ps (0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 13:
+      return _mm512_set_ps (0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 12:
+      return _mm512_set_ps (0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 11:
+      return _mm512_set_ps (0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 10:
+      return _mm512_set_ps (0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 9:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 8:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 7:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm512_set_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static __m512
+__attribute__ ((noinline))
+foo_r (float x, int i)
+{
+  switch (i)
+    {
+    case 0:
+      return _mm512_setr_ps (x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 1:
+      return _mm512_setr_ps (0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 2:
+      return _mm512_setr_ps (0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 3:
+      return _mm512_setr_ps (0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm512_setr_ps (0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 7:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 8:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0);
+    case 9:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0);
+    case 10:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0);
+    case 11:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0);
+    case 12:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0);
+    case 13:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0);
+    case 14:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0);
+    case 15:
+      return _mm512_setr_ps (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  float e = -3.234;
+  float v[16];
+  union512 res;
+  int i, j;
+
+  for (i = 0; i < 16; i++)
+    {
+      for (j = 0; j < 16; j++)
+	v[j] = 0;
+      v[i] = e;
+
+      res.x = foo (e, i);
+
+      if (check_union512 (res, v))
+	abort ();
+
+      res.x = _mm512_setzero_ps ();
+
+      res.x = foo_r (e, i);
+
+      if (check_union512 (res, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-5.c
new file mode 100644
index 000000000..dec7fd40a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16sf-5.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512
+__attribute__ ((noinline))
+foo (float x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm512_set_ps (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 14:
+      return _mm512_set_ps (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 13:
+      return _mm512_set_ps (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 12:
+      return _mm512_set_ps (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm512_set_ps (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm512_set_ps (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm512_set_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static __m512
+__attribute__ ((noinline))
+foo_r (float x, int i)
+{
+  switch (i)
+    {
+    case 0:
+      return _mm512_setr_ps (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 1:
+      return _mm512_setr_ps (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 2:
+      return _mm512_setr_ps (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 3:
+      return _mm512_setr_ps (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm512_setr_ps (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1);
+    case 12:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1);
+    case 13:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1);
+    case 14:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1);
+    case 15:
+      return _mm512_setr_ps (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  float e = -3.234;
+  float v[16];
+  union512 res;
+  int i, j;
+
+  for (i = 0; i < 16; i++)
+    {
+      for (j = 0; j < 16; j++)
+	v[j] = 1;
+      v[i] = e;
+
+      res.x = foo (e, i);
+
+      if (check_union512 (res, v))
+	abort ();
+
+      res.x = _mm512_setzero_ps ();
+
+      res.x = foo_r (e, i);
+
+      if (check_union512 (res, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-1.c
new file mode 100644
index 000000000..ebd048699
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (int *v)
+{
+  return _mm512_set_epi32 (v[15], v[14], v[13], v[12],
+			   v[11], v[10], v[9], v[8],
+			   v[7], v[6], v[5], v[4],
+			   v[3], v[2], v[1], v[0]);
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (int *v)
+{
+  return _mm512_setr_epi32 (v[0], v[1], v[2], v[3],
+			    v[4], v[5], v[6], v[7],
+			    v[8], v[9], v[10], v[11],
+			    v[12], v[13], v[14], v[15]);
+}
+
+static void
+avx512f_test (void)
+{
+  int v[16] = { 19832468, 2134, 6576856, 6678,
+		8723467, 54646, 234566, 12314,
+		786784, 77575, 645245, 234555,
+		9487733, 411244, 12344, 86533 };
+  union512i_d res;
+
+  res.x = foo (v);
+
+  if (check_union512i_d (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_si512 ();
+
+  res.x = foo_r (v);
+
+  if (check_union512i_d (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-2.c
new file mode 100644
index 000000000..3090a2de6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (int x1, int x2, int x3, int x4,
+     int x5, int x6, int x7, int x8,
+     int x9, int x10, int x11, int x12,
+     int x13, int x14, int x15, int x16)
+{
+  return _mm512_set_epi32 (x1, x2, x3, x4, x5, x6, x7, x8,
+			   x9, x10, x11, x12, x13, x14, x15, x16);
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (int x1, int x2, int x3, int x4,
+       int x5, int x6, int x7, int x8,
+       int x9, int x10, int x11, int x12,
+       int x13, int x14, int x15, int x16)
+{
+  return _mm512_setr_epi32 (x16, x15, x14, x13, x12, x11, x10, x9,
+			    x8, x7, x6, x5, x4, x3, x2, x1);
+}
+
+static void
+avx512f_test (void)
+{
+  int v[16] = { -3, -453, 2, -231, 1, -111, 9, -145,
+		23, 671, -173, 166, -13, 714, 69, 123 };
+  union512i_d res;
+
+  res.x = foo (v[15], v[14], v[13], v[12], v[11], v[10], v[9], v[8],
+	       v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union512i_d (res, v))
+     abort ();
+
+  res.x = _mm512_setzero_si512 ();
+
+  res.x = foo_r (v[15], v[14], v[13], v[12], v[11], v[10], v[9], v[8],
+		 v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union512i_d (res, v))
+     abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-3.c
new file mode 100644
index 000000000..c02838ec3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-3.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (int x)
+{
+  return _mm512_set_epi32 (x, x, x, x, x, x, x, x,
+			   x, x, x, x, x, x, x, x);
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (int x)
+{
+  return _mm512_setr_epi32 (x, x, x, x, x, x, x, x,
+			    x, x, x, x, x, x, x, x);
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  int e = 0xabadbeef;
+  int v[16];
+  union512i_d res;
+
+  for (i = 0; i < 16; i++)
+    v[i] = e;
+
+  res.x = foo (e);
+
+  if (check_union512i_d (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_si512 ();
+
+  res.x = foo_r (e);
+
+  if (check_union512i_d (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-4.c
new file mode 100644
index 000000000..a16f6f068
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-4.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (int x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm512_set_epi32 (x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 14:
+      return _mm512_set_epi32 (0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 13:
+      return _mm512_set_epi32 (0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 12:
+      return _mm512_set_epi32 (0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 11:
+      return _mm512_set_epi32 (0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 10:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 9:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 8:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 7:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm512_set_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (int x, int i)
+{
+  switch (i)
+    {
+    case 0:
+      return _mm512_setr_epi32 (x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 1:
+      return _mm512_setr_epi32 (0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 2:
+      return _mm512_setr_epi32 (0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 3:
+      return _mm512_setr_epi32 (0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm512_setr_epi32 (0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 7:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0, 0);
+    case 8:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0, 0);
+    case 9:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0, 0);
+    case 10:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0, 0);
+    case 11:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0, 0);
+    case 12:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0, 0);
+    case 13:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0, 0);
+    case 14:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x, 0);
+    case 15:
+      return _mm512_setr_epi32 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int e = 0xabadbeef;
+  int v[16];
+  union512i_d res;
+  int i, j;
+
+  for (i = 0; i < 16; i++)
+    {
+      for (j = 0; j < 16; j++)
+	v[j] = 0;
+      v[i] = e;
+
+      res.x = foo (e, i);
+
+      if (check_union512i_d (res, v))
+	abort ();
+
+      res.x = _mm512_setzero_si512 ();
+
+      res.x = foo_r (e, i);
+
+      if (check_union512i_d (res, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-5.c
new file mode 100644
index 000000000..948d4ed42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v16si-5.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (int x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm512_set_epi32 (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 14:
+      return _mm512_set_epi32 (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 13:
+      return _mm512_set_epi32 (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 12:
+      return _mm512_set_epi32 (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm512_set_epi32 (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm512_set_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (int x, int i)
+{
+  switch (i)
+    {
+    case 0:
+      return _mm512_setr_epi32 (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 1:
+      return _mm512_setr_epi32 (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 2:
+      return _mm512_setr_epi32 (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 3:
+      return _mm512_setr_epi32 (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm512_setr_epi32 (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1);
+    case 12:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1);
+    case 13:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1);
+    case 14:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1);
+    case 15:
+      return _mm512_setr_epi32 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int e = 0xabadbeef;
+  int v[16];
+  union512i_d res;
+  int i, j;
+
+  for (i = 0; i < 16; i++)
+    {
+      for (j = 0; j < 16; j++)
+	v[j] = 1;
+      v[i] = e;
+
+      res.x = foo (e, i);
+
+      if (check_union512i_d (res, v))
+	abort ();
+
+      res.x = _mm512_setzero_si512 ();
+
+      res.x = foo_r (e, i);
+
+      if (check_union512i_d (res, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-1.c
new file mode 100644
index 000000000..a3514ef72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512d
+__attribute__ ((noinline))
+foo (double *v)
+{
+  return _mm512_set_pd (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+}
+
+static __m512d
+__attribute__ ((noinline))
+foo_r (double *v)
+{
+  return _mm512_setr_pd (v[0], v[1], v[2], v[3], v[4], v[5], v[6], v[7]);
+}
+
+static void
+avx512f_test (void)
+{
+  double v[8] = { -3.3, 2.6, 1.48, 9.104, -23.9, -173.37, -13.48, 69.78 };
+  union512d res;
+
+  res.x = foo (v);
+
+  if (check_union512d (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_pd ();
+
+  res.x = foo_r (v);
+
+  if (check_union512d (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-2.c
new file mode 100644
index 000000000..a412de582
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-2.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512d
+__attribute__ ((noinline))
+foo (double x1, double x2, double x3, double x4,
+     double x5, double x6, double x7, double x8)
+{
+  return _mm512_set_pd (x1, x2, x3, x4, x5, x6, x7, x8);
+}
+
+static __m512d
+__attribute__ ((noinline))
+foo_r (double x1, double x2, double x3, double x4,
+       double x5, double x6, double x7, double x8)
+{
+  return _mm512_setr_pd (x8, x7, x6, x5, x4, x3, x2, x1);
+}
+
+static void
+avx512f_test (void)
+{
+  double v[8] = { -3.3, 2.6, 1.48, 9.104, -23.9, -173.37, -13.48, 69.78 };
+  union512d res;
+
+  res.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union512d (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_pd ();
+
+  res.x = foo_r (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union512d (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-3.c
new file mode 100644
index 000000000..751af6703
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-3.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512d
+__attribute__ ((noinline))
+foo (double x)
+{
+  return _mm512_set_pd (x, x, x, x, x, x, x, x);
+}
+
+static __m512d
+__attribute__ ((noinline))
+foo_r (double x)
+{
+  return _mm512_setr_pd (x, x, x, x, x, x, x, x);
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  double e = 34.5;
+  double v[8];
+  union512d res;
+
+  for (i = 0; i < 8; i++)
+    v[i] = e;
+
+  res.x = foo (e);
+
+  if (check_union512d (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_pd ();
+
+  res.x = foo_r (e);
+
+  if (check_union512d (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-4.c
new file mode 100644
index 000000000..f62bb5fa0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-4.c
@@ -0,0 +1,87 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512d
+__attribute__ ((noinline))
+foo (double x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm512_set_pd (x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm512_set_pd (0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm512_set_pd (0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm512_set_pd (0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm512_set_pd (0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm512_set_pd (0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm512_set_pd (0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm512_set_pd (0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static __m512d
+__attribute__ ((noinline))
+foo_r (double x, int i)
+{
+  switch (i)
+    {
+    case 0:
+      return _mm512_setr_pd (x, 0, 0, 0, 0, 0, 0, 0);
+    case 1:
+      return _mm512_setr_pd (0, x, 0, 0, 0, 0, 0, 0);
+    case 2:
+      return _mm512_setr_pd (0, 0, x, 0, 0, 0, 0, 0);
+    case 3:
+      return _mm512_setr_pd (0, 0, 0, x, 0, 0, 0, 0);
+    case 4:
+      return _mm512_setr_pd (0, 0, 0, 0, x, 0, 0, 0);
+    case 5:
+      return _mm512_setr_pd (0, 0, 0, 0, 0, x, 0, 0);
+    case 6:
+      return _mm512_setr_pd (0, 0, 0, 0, 0, 0, x, 0);
+    case 7:
+      return _mm512_setr_pd (0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  double e = -3.234;
+  double v[8];
+  union512d res;
+  int i, j;
+
+  for (i = 0; i < 8; i++)
+    {
+      for (j = 0; j < 8; j++)
+	v[j] = 0;
+      v[i] = e;
+
+      res.x = foo (e, i);
+
+      if (check_union512d (res, v))
+	abort ();
+
+      res.x = _mm512_setzero_pd ();
+
+      res.x = foo_r (e, i);
+
+      if (check_union512d (res, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-5.c
new file mode 100644
index 000000000..c6abd82da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8df-5.c
@@ -0,0 +1,87 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512d
+__attribute__ ((noinline))
+foo (double x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm512_set_pd (x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm512_set_pd (1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm512_set_pd (1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm512_set_pd (1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm512_set_pd (1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm512_set_pd (1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm512_set_pd (1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm512_set_pd (1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static __m512d
+__attribute__ ((noinline))
+foo_r (double x, int i)
+{
+  switch (i)
+    {
+    case 0:
+      return _mm512_setr_pd (x, 1, 1, 1, 1, 1, 1, 1);
+    case 1:
+      return _mm512_setr_pd (1, x, 1, 1, 1, 1, 1, 1);
+    case 2:
+      return _mm512_setr_pd (1, 1, x, 1, 1, 1, 1, 1);
+    case 3:
+      return _mm512_setr_pd (1, 1, 1, x, 1, 1, 1, 1);
+    case 4:
+      return _mm512_setr_pd (1, 1, 1, 1, x, 1, 1, 1);
+    case 5:
+      return _mm512_setr_pd (1, 1, 1, 1, 1, x, 1, 1);
+    case 6:
+      return _mm512_setr_pd (1, 1, 1, 1, 1, 1, x, 1);
+    case 7:
+      return _mm512_setr_pd (1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  double e = -3.234;
+  double v[8];
+  union512d res;
+  int i, j;
+
+  for (i = 0; i < 8; i++)
+    {
+      for (j = 0; j < 8; j++)
+	v[j] = 1;
+      v[i] = e;
+
+      res.x = foo (e, i);
+
+      if (check_union512d (res, v))
+	abort ();
+
+      res.x = _mm512_setzero_pd ();
+
+      res.x = foo_r (e, i);
+
+      if (check_union512d (res, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-1.c
new file mode 100644
index 000000000..8cb1f8f61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (long long *v)
+{
+  return _mm512_set_epi64 (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (long long *v)
+{
+  return _mm512_setr_epi64 (v[0], v[1], v[2], v[3], v[4], v[5], v[6], v[7]);
+}
+
+static void
+avx512f_test (void)
+{
+  long long v[8] = { 0x12e9e94645ad8LL, 0x851c0b39446LL, 2134, 6678,
+		     0x786784645245LL, 0x9487731234LL, 41124, 86530 };
+  union512i_q res;
+
+  res.x = foo (v);
+
+  if (check_union512i_q (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_si512 ();
+
+  res.x = foo_r (v);
+
+  if (check_union512i_q (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-2.c
new file mode 100644
index 000000000..fd033ce24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-2.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (long long x1, long long x2, long long x3, long long x4,
+     long long x5, long long x6, long long x7, long long x8)
+{
+  return _mm512_set_epi64 (x1, x2, x3, x4, x5, x6, x7, x8);
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (long long x1, long long x2, long long x3, long long x4,
+       long long x5, long long x6, long long x7, long long x8)
+{
+  return _mm512_setr_epi64 (x8, x7, x6, x5, x4, x3, x2, x1);
+}
+
+static void
+avx512f_test (void)
+{
+  long long v[8] = { 0x12e9e94645ad8LL, 0x851c0b39446LL, 2134, 6678,
+		     0x786784645245LL, 0x9487731234LL, 41124, 86530 };
+  union512i_q res;
+
+  res.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union512i_q (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_si512 ();
+
+  res.x = foo_r (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union512i_q (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-3.c
new file mode 100644
index 000000000..16e12c7f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-3.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (long long x)
+{
+  return _mm512_set_epi64 (x, x, x, x, x, x, x, x);
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (long long x)
+{
+  return _mm512_setr_epi64 (x, x, x, x, x, x, x, x);
+}
+
+static void
+avx512f_test (void)
+{
+  int i;
+  long long e = 0xfed178ab134badf1LL;
+  long long v[8];
+  union512i_q res;
+
+  for (i = 0; i < 8; i++)
+    v[i] = e;
+
+  res.x = foo (e);
+
+  if (check_union512i_q (res, v))
+    abort ();
+
+  res.x = _mm512_setzero_si512 ();
+
+  res.x = foo_r (e);
+
+  if (check_union512i_q (res, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-4.c
new file mode 100644
index 000000000..ea6421fcc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-4.c
@@ -0,0 +1,87 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (long long x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm512_set_epi64 (x, 0, 0, 0, 0, 0, 0, 0);
+    case 6:
+      return _mm512_set_epi64 (0, x, 0, 0, 0, 0, 0, 0);
+    case 5:
+      return _mm512_set_epi64 (0, 0, x, 0, 0, 0, 0, 0);
+    case 4:
+      return _mm512_set_epi64 (0, 0, 0, x, 0, 0, 0, 0);
+    case 3:
+      return _mm512_set_epi64 (0, 0, 0, 0, x, 0, 0, 0);
+    case 2:
+      return _mm512_set_epi64 (0, 0, 0, 0, 0, x, 0, 0);
+    case 1:
+      return _mm512_set_epi64 (0, 0, 0, 0, 0, 0, x, 0);
+    case 0:
+      return _mm512_set_epi64 (0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (long long x, int i)
+{
+  switch (i)
+    {
+    case 0:
+      return _mm512_setr_epi64 (x, 0, 0, 0, 0, 0, 0, 0);
+    case 1:
+      return _mm512_setr_epi64 (0, x, 0, 0, 0, 0, 0, 0);
+    case 2:
+      return _mm512_setr_epi64 (0, 0, x, 0, 0, 0, 0, 0);
+    case 3:
+      return _mm512_setr_epi64 (0, 0, 0, x, 0, 0, 0, 0);
+    case 4:
+      return _mm512_setr_epi64 (0, 0, 0, 0, x, 0, 0, 0);
+    case 5:
+      return _mm512_setr_epi64 (0, 0, 0, 0, 0, x, 0, 0);
+    case 6:
+      return _mm512_setr_epi64 (0, 0, 0, 0, 0, 0, x, 0);
+    case 7:
+      return _mm512_setr_epi64 (0, 0, 0, 0, 0, 0, 0, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  long long e = 0xabadbeef01234567LL;
+  long long v[8];
+  union512i_q res;
+  int i, j;
+
+  for (i = 0; i < 8; i++)
+    {
+      for (j = 0; j < 8; j++)
+	v[j] = 0;
+      v[i] = e;
+
+      res.x = foo (e, i);
+
+      if (check_union512i_q (res, v))
+	abort ();
+
+      res.x = _mm512_setzero_si512 ();
+
+      res.x = foo_r (e, i);
+
+      if (check_union512i_q (res, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-5.c
new file mode 100644
index 000000000..76ec44388
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-set-v8di-5.c
@@ -0,0 +1,87 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static __m512i
+__attribute__ ((noinline))
+foo (long long x, int i)
+{
+  switch (i)
+    {
+    case 7:
+      return _mm512_set_epi64 (x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm512_set_epi64 (1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm512_set_epi64 (1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm512_set_epi64 (1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm512_set_epi64 (1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm512_set_epi64 (1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm512_set_epi64 (1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm512_set_epi64 (1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static __m512i
+__attribute__ ((noinline))
+foo_r (long long x, int i)
+{
+  switch (i)
+    {
+    case 0:
+      return _mm512_setr_epi64 (x, 1, 1, 1, 1, 1, 1, 1);
+    case 1:
+      return _mm512_setr_epi64 (1, x, 1, 1, 1, 1, 1, 1);
+    case 2:
+      return _mm512_setr_epi64 (1, 1, x, 1, 1, 1, 1, 1);
+    case 3:
+      return _mm512_setr_epi64 (1, 1, 1, x, 1, 1, 1, 1);
+    case 4:
+      return _mm512_setr_epi64 (1, 1, 1, 1, x, 1, 1, 1);
+    case 5:
+      return _mm512_setr_epi64 (1, 1, 1, 1, 1, x, 1, 1);
+    case 6:
+      return _mm512_setr_epi64 (1, 1, 1, 1, 1, 1, x, 1);
+    case 7:
+      return _mm512_setr_epi64 (1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  long long e = 0xabadbeef01234567LL;
+  long long v[8];
+  union512i_q res;
+  int i, j;
+
+  for (i = 0; i < 8; i++)
+    {
+      for (j = 0; j < 8; j++)
+	v[j] = 1;
+      v[i] = e;
+
+      res.x = foo (e, i);
+
+      if (check_union512i_q (res, v))
+	abort ();
+
+      res.x = _mm512_setzero_si512 ();
+
+      res.x = foo_r (e, i);
+
+      if (check_union512i_q (res, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-pd-1.c
new file mode 100644
index 000000000..f0589bd18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-pd-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  int i;
+  union512d res;
+  double res_ref[8];
+
+  res.x = _mm512_setzero_pd ();
+
+  for (i = 0; i < 8; i++)
+    res_ref[i] = 0.0;
+
+  if (check_union512d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-ps-1.c
new file mode 100644
index 000000000..5b1ee29e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-ps-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  int i;
+  union512 res;
+  float res_ref[16];
+
+  res.x = _mm512_setzero_ps ();
+
+  for (i = 0; i < 16; i++)
+    res_ref[i] = 0.0;
+
+  if (check_union512 (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-si512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-si512-1.c
new file mode 100644
index 000000000..1c60489b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-setzero-si512-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  int i;
+  union512i_q res;
+  long long res_ref[8];
+
+  res.x = _mm512_setzero_si512 ();
+
+  for (i = 0; i < 8; i++)
+    res_ref[i] = 0;
+
+  if (check_union512i_q (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddpd-1.c
new file mode 100644
index 000000000..567fecffb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddpd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vaddpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vaddpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vaddpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vaddpd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vaddpd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vaddpd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_add_pd (x, x);
+  x = _mm512_mask_add_pd (x, m, x, x);
+  x = _mm512_maskz_add_pd (m, x, x);
+  x = _mm512_add_round_pd (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_add_round_pd (x, m, x, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_add_round_pd (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddpd-2.c
new file mode 100644
index 000000000..ce6918ed6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s1, double *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] + s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_add_pd) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_add_pd) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_add_pd) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddps-1.c
new file mode 100644
index 000000000..66618b9ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vaddps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_add_ps (x, x);
+  x = _mm512_mask_add_ps (x, m, x, x);
+  x = _mm512_maskz_add_ps (m, x, x);
+  x = _mm512_add_round_ps (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_add_round_ps (x, m, x, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_add_round_ps (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddps-2.c
new file mode 100644
index 000000000..6c982bcaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddps-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s1, float *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] + s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_add_ps) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_add_ps) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_add_ps) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddsd-1.c
new file mode 100644
index 000000000..5cdb76501
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vaddsd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_add_round_sd (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddss-1.c
new file mode 100644
index 000000000..0003c44bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vaddss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vaddss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_add_round_ss (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignd-1.c
new file mode 100644
index 000000000..693adb057
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "valignd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "valignd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "valignd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i z;
+volatile __mmask16 m1;
+
+void extern
+avx512f_test (void)
+{
+  z = _mm512_alignr_epi32 (z, z, 3);
+  z = _mm512_mask_alignr_epi32 (z, m1, z, z, 3);
+  z = _mm512_maskz_alignr_epi32 (m1, z, z, 3);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignd-2.c
new file mode 100644
index 000000000..3d2a71ca1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignd-2.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+#define N (SIZE / 2)
+
+static void
+CALC (int *s1, int *s2, int *r)
+{
+  int i;
+  int s[2 * SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s[i] = s2[i];
+      s[i + SIZE] = s1[i];
+    }
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s[i + N];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, s1, s2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 2 * i;
+      s2.a[i] = i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_alignr_epi32) (s1.x, s2.x, N);
+  res2.x = INTRINSIC (_mask_alignr_epi32) (res2.x, mask, s1.x, s2.x, N);
+  res3.x = INTRINSIC (_maskz_alignr_epi32) (mask, s1.x, s2.x, N);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+      abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+      abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignq-1.c
new file mode 100644
index 000000000..a72946837
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "valignq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "valignq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "valignq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i z;
+volatile __mmask8 m1;
+
+void extern
+avx512f_test (void)
+{
+  z = _mm512_alignr_epi64 (z, z, 3);
+  z = _mm512_mask_alignr_epi64 (z, m1, z, z, 3);
+  z = _mm512_maskz_alignr_epi64 (m1, z, z, 3);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignq-2.c
new file mode 100644
index 000000000..b3c09c7b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-valignq-2.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#define N (SIZE / 2)
+
+static void
+CALC (long long *s1, long long *s2, long long *r)
+{
+  int i;
+  long long s[2 * SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s[i] = s2[i];
+      s[i + SIZE] = s1[i];
+    }
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s[i + N];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, s1, s2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 2 * i;
+      s2.a[i] = i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_alignr_epi64) (s1.x, s2.x, N);
+  res2.x = INTRINSIC (_mask_alignr_epi64) (res2.x, mask, s1.x, s2.x, N);
+  res3.x = INTRINSIC (_maskz_alignr_epi64) (mask, s1.x, s2.x, N);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+      abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+      abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmpd-1.c
new file mode 100644
index 000000000..cb0e4c250
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmpd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "(vblendmpd|vmovapd)\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}" } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_blend_pd (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmpd-2.c
new file mode 100644
index 000000000..1fe4cb616
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmpd-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s1, double *s2, MASK_TYPE mask)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (mask & (1LL << i)) ? s2[i] : s1[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+
+  res1.x = INTRINSIC (_mask_blend_pd) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a, mask);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmps-1.c
new file mode 100644
index 000000000..faee9955b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmps-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "(vblendmps|vmovaps)\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}" } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_blend_ps (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmps-2.c
new file mode 100644
index 000000000..e92c70c37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vblendmps-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s1, float *s2, MASK_TYPE mask)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (mask & (1 << i)) ? s2[i] : s1[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN,) res1, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+
+  res1.x = INTRINSIC (_mask_blend_ps) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a, mask);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf32x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf32x4-1.c
new file mode 100644
index 000000000..2af23f11d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf32x4-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastf32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]|vshuff32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastf32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]|vshuff32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastf32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}|vshuff32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m128 y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcast_f32x4 (y);
+  x = _mm512_mask_broadcast_f32x4 (x, m, y);
+  x = _mm512_maskz_broadcast_f32x4 (m, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf32x4-2.c
new file mode 100644
index 000000000..79abcdc0d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf32x4-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[i % 4];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3;
+  UNION_TYPE (128,) src;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < 4; i++)
+    {
+      src.a[i] = 34.67 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_broadcast_f32x4) (src.x);
+  res2.x = INTRINSIC (_mask_broadcast_f32x4) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_broadcast_f32x4) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf64x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf64x4-1.c
new file mode 100644
index 000000000..dbc3967cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf64x4-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastf64x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]|vshuff64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastf64x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]|vshuff64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastf64x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}|vshuff64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m256d y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcast_f64x4 (y);
+  x = _mm512_mask_broadcast_f64x4 (x, m, y);
+  x = _mm512_maskz_broadcast_f64x4 (m, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf64x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf64x4-2.c
new file mode 100644
index 000000000..bc5f6a1cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastf64x4-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[i % 4];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3;
+  UNION_TYPE (256, d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < 2; i++)
+    {
+      src.a[i] = 34.67 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_broadcast_f64x4) (src.x);
+  res2.x = INTRINSIC (_mask_broadcast_f64x4) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_broadcast_f64x4) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti32x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti32x4-1.c
new file mode 100644
index 000000000..743e1cbcc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti32x4-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcasti32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]|vshufi32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcasti32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]|vshufi32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcasti32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}|vshufi32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcast_i32x4 (y);
+  x = _mm512_mask_broadcast_i32x4 (x, m, y);
+  x = _mm512_maskz_broadcast_i32x4 (m, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti32x4-2.c
new file mode 100644
index 000000000..61dccc227
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti32x4-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[i % 4];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  UNION_TYPE (128, i_d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < 4; i++)
+    {
+      src.a[i] = 34 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_broadcast_i32x4) (src.x);
+  res2.x = INTRINSIC (_mask_broadcast_i32x4) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_broadcast_i32x4) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti64x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti64x4-1.c
new file mode 100644
index 000000000..28a50ed8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti64x4-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcasti64x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]|vshufi64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcasti64x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]|vshufi64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcasti64x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}|vshufi64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m256i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcast_i64x4 (y);
+  x = _mm512_mask_broadcast_i64x4 (x, m, y);
+  x = _mm512_maskz_broadcast_i64x4 (m, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti64x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti64x4-2.c
new file mode 100644
index 000000000..6286fca81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcasti64x4-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[i % 4];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  UNION_TYPE (256, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < 2; i++)
+    {
+      src.a[i] = 34 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_broadcast_i64x4) (src.x);
+  res2.x = INTRINSIC (_mask_broadcast_i64x4) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_broadcast_i64x4) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastsd-1.c
new file mode 100644
index 000000000..3d261afea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastsd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m128d y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcastsd_pd (y);
+  x = _mm512_mask_broadcastsd_pd (x, m, y);
+  x = _mm512_maskz_broadcastsd_pd (m, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastsd-2.c
new file mode 100644
index 000000000..3ecc1a7c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastsd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[0];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3;
+  UNION_TYPE (128, d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < 2; i++)
+    {
+      src.a[i] = 1.5 + 34.67 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_broadcastsd_pd) (src.x);
+  res2.x = INTRINSIC (_mask_broadcastsd_pd) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_broadcastsd_pd) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastss-1.c
new file mode 100644
index 000000000..4cc8cb787
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastss-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m128 y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcastss_ps (y);
+  x = _mm512_mask_broadcastss_ps (x, m, y);
+  x = _mm512_maskz_broadcastss_ps (m, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastss-2.c
new file mode 100644
index 000000000..f3f339825
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vbroadcastss-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[0];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3;
+  UNION_TYPE (128,) src;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < 4; i++)
+    {
+      src.a[i] = 1.5 + 34.67 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_broadcastss_ps) (src.x);
+  res2.x = INTRINSIC (_mask_broadcastss_ps) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_broadcastss_ps) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-1.c
new file mode 100644
index 000000000..fa3655610
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler "vcmppd\[ \\t\]+\[^\n\]*\[^\}\]%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vcmppd\[ \\t\]+\[^\n\]*\[^\}\]%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+/* { dg-final { scan-assembler "vcmppd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vcmppd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmp_pd_mask (x, x, _CMP_FALSE_OQ);
+  m = _mm512_mask_cmp_pd_mask (m, x, x, _CMP_FALSE_OQ);
+  m = _mm512_cmp_round_pd_mask (x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
+  m = _mm512_mask_cmp_round_pd_mask (m, x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-2.c
new file mode 100644
index 000000000..add23d07a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmppd-2.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -std=c99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#if AVX512F_LEN == 512
+#define CMP(imm, rel)					\
+    dst_ref = 0;					\
+    for (i = 0; i < 8; i++)				\
+    {							\
+      dst_ref = (((int) rel) << i) | dst_ref;		\
+    }							\
+    source1.x = _mm512_loadu_pd(s1);			\
+    source2.x = _mm512_loadu_pd(s2);			\
+    dst1 = _mm512_cmp_pd_mask(source1.x, source2.x, imm);\
+    dst2 = _mm512_mask_cmp_pd_mask(mask, source1.x, source2.x, imm);\
+    if (dst_ref != dst1) abort();			\
+    if ((dst_ref & mask) != dst2) abort();
+#endif
+
+static void
+TEST ()
+{
+    UNION_TYPE (AVX512F_LEN, d) source1, source2;
+    MASK_TYPE dst1, dst2, dst_ref;
+    MASK_TYPE mask = MASK_VALUE;
+    int i;
+    double s1[8]={2134.3343, 6678.346, 453.345635, 54646.464,
+		  231.23311, 5674.455, 111.111111, 23241.152};
+    double s2[8]={41124.234, 6678.346, 8653.65635, 856.43576,
+		  231.23311, 4646.123, 111.111111, 124.12455};
+
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1)
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-1.c
new file mode 100644
index 000000000..b90be8c72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler "vcmpps\[ \\t\]+\[^\n\]*\[^\}\]%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vcmpps\[ \\t\]+\[^\n\]*\[^\}\]%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+/* { dg-final { scan-assembler "vcmpps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vcmpps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmp_ps_mask (x, x, _CMP_FALSE_OQ);
+  m = _mm512_mask_cmp_ps_mask (m, x, x, _CMP_FALSE_OQ);
+  m = _mm512_cmp_round_ps_mask (x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
+  m = _mm512_mask_cmp_round_ps_mask (m, x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-2.c
new file mode 100644
index 000000000..15c314e2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpps-2.c
@@ -0,0 +1,80 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -std=c99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+#if AVX512F_LEN == 512
+#define CMP(imm, rel)					\
+    dst_ref = 0;					\
+    for (i = 0; i < 16; i++)				\
+    {							\
+      dst_ref = (((int) rel) << i) | dst_ref;		\
+    }							\
+    source1.x = _mm512_loadu_ps(s1);			\
+    source2.x = _mm512_loadu_ps(s2);			\
+    dst1 = _mm512_cmp_ps_mask(source1.x, source2.x, imm);\
+    dst2 = _mm512_mask_cmp_ps_mask(mask, source1.x, source2.x, imm);\
+    if (dst_ref != dst1) abort();			\
+    if ((dst_ref & mask) != dst2) abort();
+#endif
+
+static void
+TEST ()
+{
+    UNION_TYPE (AVX512F_LEN,) source1, source2;
+    MASK_TYPE dst1, dst2, dst_ref;
+    MASK_TYPE mask = MASK_VALUE;
+    int i;
+    float s1[16] = {2134.3343, 6678.346, 453.345635, 54646.464,
+		    231.23311, 5674.455, 111.111111, 23241.152,
+		    123.14811, 1245.124, 244.151353, 53454.141,
+		    926.16717, 3733.261, 643.161644, 23514.633};
+    float s2[16] = {41124.234, 6678.346, 8653.65635, 856.43576,
+		    231.23311, 4646.123, 111.111111, 124.12455,
+		    123.14811, 1245.124, 244.151353, 53454.141,
+		    2134.3343, 6678.346, 453.345635, 54646.464};
+
+    CMP(_CMP_EQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OS, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OS, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_US, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_US, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[i], s2[i]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_US, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_US, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OS, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OS, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[i], s2[i]) && s1[i] == s2[i]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[i], s2[i]) && s1[i] < s2[i]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[i], s2[i]) && s1[i] <= s2[i]);
+    CMP(_CMP_UNORD_S, isunordered(s1[i], s2[i]));
+    CMP(_CMP_NEQ_US, isunordered(s1[i], s2[i]) || s1[i] != s2[i]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[i], s2[i]) || s1[i] >= s2[i]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[i], s2[i]) || s1[i] > s2[i]);
+    CMP(_CMP_ORD_S, !isunordered(s1[i], s2[i]));
+    CMP(_CMP_EQ_US, isunordered(s1[i], s2[i]) || s1[i] == s2[i]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[i], s2[i]) || s1[i] < s2[i]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[i], s2[i]) || s1[i] <= s2[i]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[i], s2[i]) && s1[i] != s2[i]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[i], s2[i]) && s1[i] >= s2[i]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[i], s2[i]) && s1[i] > s2[i]);
+    CMP(_CMP_TRUE_US, 1)
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpsd-1.c
new file mode 100644
index 000000000..7f92fbea3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpsd-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler "vcmpsd\[ \\t\]+\[^\n\]*\[^\}\]%xmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vcmpsd\[ \\t\]+\[^\n\]*\[^\}\]%xmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+/* { dg-final { scan-assembler "vcmpsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vcmpsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm_cmp_sd_mask (x, x, _CMP_FALSE_OQ);
+  m = _mm_mask_cmp_sd_mask (m, x, x, _CMP_FALSE_OQ);
+  m = _mm_cmp_round_sd_mask (x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
+  m = _mm_mask_cmp_round_sd_mask (m, x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpsd-2.c
new file mode 100644
index 000000000..3e4729e4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpsd-2.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx512f -std=c99" } */
+
+#include "avx512f-check.h"
+#include <math.h>
+
+double s1[2] = {2134.3343, 6678.346};
+double s2[2] = {1485.1288, 6678.346};
+
+__mmask8 dst_ref;
+
+#define CMP(imm, rel)					\
+    dst_ref = 0;					\
+    dst_ref = ((int) rel) | dst_ref;			\
+    source1 = _mm_loadu_pd(s1);				\
+    source2 = _mm_loadu_pd(s2);				\
+    dst = _mm_cmp_sd_mask(source1, source2, imm);	\
+    dst2 = _mm_mask_cmp_sd_mask(mask, source1, source2, imm);\
+    if (dst_ref != dst) abort();			\
+    if ((dst_ref & mask) != dst2) abort();
+
+static void
+avx512f_test ()
+{
+    __m128d source1, source2;
+    __mmask8 dst, dst2, mask;
+    mask = 1;
+    int i;
+
+    CMP(_CMP_EQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OS, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OS, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_US, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_US, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[0], s2[0]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_US, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_US, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OS, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OS, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_S, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_US, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_S, !isunordered(s1[0], s2[0]));
+    CMP(_CMP_EQ_US, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_US, 1)
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpss-1.c
new file mode 100644
index 000000000..9f370cb0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpss-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler "vcmpss\[ \\t\]+\[^\n\]*\[^\}\]%xmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vcmpss\[ \\t\]+\[^\n\]*\[^\}\]%xmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+/* { dg-final { scan-assembler "vcmpss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vcmpss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm_cmp_ss_mask (x, x, _CMP_FALSE_OQ);
+  m = _mm_mask_cmp_ss_mask (m, x, x, _CMP_FALSE_OQ);
+  m = _mm_cmp_round_ss_mask (x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
+  m = _mm_mask_cmp_round_ss_mask (m, x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpss-2.c
new file mode 100644
index 000000000..7343cb05c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcmpss-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O2 -mavx512f -std=c99" } */
+
+#include "avx512f-check.h"
+#include <math.h>
+
+float s1[4] = {2134.3343, 6678.346, 453.345635, 54646.464};
+float s2[4] = {1485.1288, 6678.346, 8653.65635, 856.43576};
+
+__mmask8 dst_ref;
+
+#define CMP(imm, rel)					\
+    dst_ref = 0;					\
+    dst_ref = ((int) rel) | dst_ref;			\
+    source1 = _mm_loadu_ps(s1);				\
+    source2 = _mm_loadu_ps(s2);				\
+    dst = _mm_cmp_ss_mask(source1, source2, imm);	\
+    dst2 = _mm_mask_cmp_ss_mask(mask, source1, source2, imm);\
+    if (dst_ref != dst) abort();			\
+    if ((dst_ref & mask)!= dst2) abort();
+
+static void
+avx512f_test ()
+{
+    __m128 source1, source2;
+    __mmask8 dst, dst2, mask;
+    int i;
+
+    mask = 1;
+
+    CMP(_CMP_EQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OS, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OS, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_Q, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_UQ, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_US, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_US, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_Q, !isunordered(s1[0], s2[0]));
+
+    CMP(_CMP_EQ_UQ, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_US, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_US, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+
+    CMP(_CMP_FALSE_OQ, 0);
+    CMP(_CMP_NEQ_OQ, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OS, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OS, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_UQ, 1);
+
+    CMP(_CMP_EQ_OS, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(_CMP_LT_OQ, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(_CMP_LE_OQ, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(_CMP_UNORD_S, isunordered(s1[0], s2[0]));
+    CMP(_CMP_NEQ_US, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(_CMP_NLT_UQ, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(_CMP_NLE_UQ, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(_CMP_ORD_S, !isunordered(s1[0], s2[0]));
+    CMP(_CMP_EQ_US, isunordered(s1[0], s2[0]) || s1[0] == s2[0]);
+    CMP(_CMP_NGE_UQ, isunordered(s1[0], s2[0]) || s1[0] < s2[0]);
+    CMP(_CMP_NGT_UQ, isunordered(s1[0], s2[0]) || s1[0] <= s2[0]);
+    CMP(_CMP_FALSE_OS, 0);
+    CMP(_CMP_NEQ_OS, !isunordered(s1[0], s2[0]) && s1[0] != s2[0]);
+    CMP(_CMP_GE_OQ, !isunordered(s1[0], s2[0]) && s1[0] >= s2[0]);
+    CMP(_CMP_GT_OQ, !isunordered(s1[0], s2[0]) && s1[0] > s2[0]);
+    CMP(_CMP_TRUE_US, 1)
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcomisd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcomisd-1.c
new file mode 100644
index 000000000..7b5aff4e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcomisd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vcomisd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm"  } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile int res;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm_comi_round_sd (x, x, _CMP_LT_OS, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcomiss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcomiss-1.c
new file mode 100644
index 000000000..bc5041904
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcomiss-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcomiss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm" 1 } } */
+/* { dg-final { scan-assembler-times "vcomiss\[ \\t\]+\[^{}\n\]*%xmm" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile int res;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm_comi_round_ss (x, x, _CMP_LT_OS, _MM_FROUND_NO_EXC);
+}
+
+void extern
+avx512f_test_2 (void)
+{
+  res = _mm_comi_round_ss (x, x, _CMP_LT_OS, _MM_FROUND_CUR_DIRECTION);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompresspd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompresspd-1.c
new file mode 100644
index 000000000..3f2cdff9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompresspd-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcompresspd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcompresspd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vcompresspd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+double *p;
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_compress_pd (x, m, x);
+  x = _mm512_maskz_compress_pd (m, x);
+
+  _mm512_mask_compressstoreu_pd (p, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompresspd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompresspd-2.c
new file mode 100644
index 000000000..4acbadbe7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompresspd-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#define MASK ((1 << SIZE) - 1)
+#include <x86intrin.h>
+
+static void
+CALC (double *s, double *r, MASK_TYPE mask)
+{
+  int i, k;
+
+  for (i = 0, k = 0; i < SIZE; i++)
+    {
+      if (mask & (1 << i))
+	r[k++] = s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s, res1, res2;
+  double res3[SIZE];
+  MASK_TYPE compressed_mask, mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i, mask_bit_count, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 12345 * (i + 200) * sign;
+      res1.a[i] = DEFAULT_VALUE;
+      res3[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_mask_compress_pd) (res1.x, mask, s.x);
+  res2.x = INTRINSIC (_maskz_compress_pd) (mask, s.x);
+  INTRINSIC (_mask_compressstoreu_pd) (res3, mask, s.x);
+
+  mask_bit_count = __popcntd (mask & MASK);
+  compressed_mask = (1 << mask_bit_count) - 1;
+  CALC (s.a, res_ref, mask);
+
+  MASK_MERGE (d) (res_ref, compressed_mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, compressed_mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, compressed_mask, SIZE);
+  if (checkVd (res3, res_ref, SIZE))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompressps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompressps-1.c
new file mode 100644
index 000000000..ab715c6fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompressps-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcompressps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcompressps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vcompressps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+float *p;
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_compress_ps (x, m, x);
+  x = _mm512_maskz_compress_ps (m, x);
+
+  _mm512_mask_compressstoreu_ps (p, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompressps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompressps-2.c
new file mode 100644
index 000000000..f996452b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcompressps-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#define MASK ((1 << SIZE) - 1)
+#include <x86intrin.h>
+
+static void
+CALC (float *s, float *r, MASK_TYPE mask)
+{
+  int i, k;
+
+  for (i = 0, k = 0; i < SIZE; i++)
+    {
+      if (mask & (1 << i))
+	r[k++] = s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s, res1, res2;
+  float res3[SIZE];
+  MASK_TYPE compressed_mask, mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i, mask_bit_count, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 12345 * (i + 200) * sign;
+      res1.a[i] = DEFAULT_VALUE;
+      res3[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_mask_compress_ps) (res1.x, mask, s.x);
+  res2.x = INTRINSIC (_maskz_compress_ps) (mask, s.x);
+  INTRINSIC (_mask_compressstoreu_ps) (res3, mask, s.x);
+
+  mask_bit_count = __popcntd (mask & MASK);
+  compressed_mask = (1 << mask_bit_count) - 1;
+  CALC (s.a, res_ref, mask);
+
+  MASK_MERGE () (res_ref, compressed_mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, compressed_mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, compressed_mask, SIZE);
+  if (checkVf (res3, res_ref, SIZE))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2pd-1.c
new file mode 100644
index 000000000..d2c616b08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2pd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtdq2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtdq2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtdq2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i s;
+volatile __m512d res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi32_pd (s);
+  res = _mm512_mask_cvtepi32_pd (res, m, s);
+  res = _mm512_maskz_cvtepi32_pd (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2pd-2.c
new file mode 100644
index 000000000..77cdbab0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2pd-2.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE ((AVX512F_LEN_HALF) / 32)
+#include "avx512f-mask-type.h"
+#define DST_SIZE ((AVX512F_LEN) / 64)
+
+static void
+CALC (int *s, double *r)
+{
+  int i;
+
+  for (i = 0; i < DST_SIZE; i++)
+    {
+      r[i] = (double) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) s;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[DST_SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s.a[i] = 123456 * (i + 2000) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_cvtepi32_pd) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepi32_pd) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepi32_pd) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2ps-1.c
new file mode 100644
index 000000000..7c326f0bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2ps-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m512 res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi32_ps (s);
+  res = _mm512_mask_cvtepi32_ps (res, m, s);
+  res = _mm512_maskz_cvtepi32_ps (m, s);
+  res = _mm512_cvt_roundepi32_ps (s, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvt_roundepi32_ps (res, m, s, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvt_roundepi32_ps (m, s, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2ps-2.c
new file mode 100644
index 000000000..4a3e3aa4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtdq2ps-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (float) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s;
+  UNION_TYPE (AVX512F_LEN, ) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 123456 * (i + 2000) * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_cvtepi32_ps) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepi32_ps) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepi32_ps) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2dq-1.c
new file mode 100644
index 000000000..2a6d38c46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2dq-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d s;
+volatile __m256i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtpd_epi32 (s);
+  res = _mm512_mask_cvtpd_epi32 (res, m, s);
+  res = _mm512_maskz_cvtpd_epi32 (m, s);
+  res = _mm512_cvt_roundpd_epi32 (s, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvt_roundpd_epi32 (res, m, s, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvt_roundpd_epi32 (m, s, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2dq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2dq-2.c
new file mode 100644
index 000000000..5ecb640ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2dq-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE ((AVX512F_LEN) / 64)
+#include "avx512f-mask-type.h"
+#define DST_SIZE ((AVX512F_LEN_HALF) / 32)
+
+static void
+CALC (double *s, unsigned *r)
+{
+  int i;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      r[i] = (s[i] >= 0) ? (int) (s[i] + 0.5)
+			 : (int) (s[i] - 0.5);
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s;
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[DST_SIZE] = { 0 };
+  int i, sign = 1;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_cvtpd_epi32) (s.x);
+  res2.x = INTRINSIC (_mask_cvtpd_epi32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtpd_epi32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SRC_SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SRC_SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2ps-1.c
new file mode 100644
index 000000000..baa8b0848
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2ps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 6 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m256 y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_cvtpd_ps (x);
+  y = _mm512_mask_cvtpd_ps (y, 4, x);
+  y = _mm512_maskz_cvtpd_ps (6, x);
+  y = _mm512_cvt_roundpd_ps (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  y = _mm512_mask_cvt_roundpd_ps (y, 4, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  y = _mm512_maskz_cvt_roundpd_ps (6, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2ps-2.c
new file mode 100644
index 000000000..fa17ef9aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2ps-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+void static
+CALC (float *e, UNION_TYPE (AVX512F_LEN, d) s1)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    e[i] = (float) s1.a[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1;
+  UNION_TYPE (AVX512F_LEN_HALF,) u1, u2, u3;
+  MASK_TYPE mask = MASK_VALUE;
+  float e[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 0.12 * (i + 37.09);
+      u1.a[i] = DEFAULT_VALUE;
+      u2.a[i] = DEFAULT_VALUE;
+      u3.a[i] = DEFAULT_VALUE;
+    }
+
+  u1.x = INTRINSIC (_cvtpd_ps) (s1.x);
+  u2.x = INTRINSIC (_mask_cvtpd_ps) (u2.x, mask, s1.x);
+  u3.x = INTRINSIC (_maskz_cvtpd_ps) (mask, s1.x);
+
+  CALC (e, s1);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF,) (u1, e))
+    abort ();
+
+  MASK_MERGE ()(e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF,) (u2, e))
+    abort ();
+
+  MASK_ZERO ()(e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF,) (u3, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2udq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2udq-1.c
new file mode 100644
index 000000000..33651e3f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2udq-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d s;
+volatile __m256i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtpd_epu32 (s);
+  res = _mm512_mask_cvtpd_epu32 (res, m, s);
+  res = _mm512_maskz_cvtpd_epu32 (m, s);
+  res = _mm512_cvt_roundpd_epu32 (s, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvt_roundpd_epu32 (res, m, s, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvt_roundpd_epu32 (m, s, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2udq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2udq-2.c
new file mode 100644
index 000000000..24788d97a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtpd2udq-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE ((AVX512F_LEN) / 64)
+#include "avx512f-mask-type.h"
+#define DST_SIZE ((AVX512F_LEN_HALF) / 32)
+
+static void
+CALC (double *s, unsigned *r)
+{
+  int i;
+
+  for (i = 0; i < DST_SIZE; i++)
+    {
+      r[i] = (unsigned) (s[i] + 0.5);
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s;
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned res_ref[DST_SIZE] = { 0 };
+  int i;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000);
+    }
+
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_cvtpd_epu32) (s.x);
+  res2.x = INTRINSIC (_mask_cvtpd_epu32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtpd_epu32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SRC_SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SRC_SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtph2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtph2ps-1.c
new file mode 100644
index 000000000..b22a950dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtph2ps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtph2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 6 } } */
+/* { dg-final { scan-assembler-times "vcvtph2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtph2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtph2ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vcvtph2ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2ps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i x;
+volatile __m512 y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_cvtph_ps (x);
+  y = _mm512_mask_cvtph_ps (y, 4, x);
+  y = _mm512_maskz_cvtph_ps (6, x);
+  y = _mm512_cvt_roundph_ps (x, _MM_FROUND_NO_EXC);
+  y = _mm512_mask_cvt_roundph_ps (y, 4, x, _MM_FROUND_NO_EXC);
+  y = _mm512_maskz_cvt_roundph_ps (6, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtph2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtph2ps-2.c
new file mode 100644
index 000000000..725e1e87b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtph2ps-2.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN_HALF, i_w) val;
+  UNION_TYPE (AVX512F_LEN,) res1,res2,res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float exp[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  exp[0] = 1;
+  exp[1] = 2;
+  exp[2] = 4;
+  exp[3] = 8;
+#if AVX512F_LEN > 128
+  exp[4] = -1;
+  exp[5] = -2;
+  exp[6] = -4;
+  exp[7] = -8;
+#endif
+#if AVX512F_LEN > 256
+  exp[8] = 1;
+  exp[9] = 2;
+  exp[10] = 4;
+  exp[11] = 8;
+  exp[12] = -1;
+  exp[13] = -2;
+  exp[14] = -4;
+  exp[15] = -8;
+#endif
+
+  val.a[0] = 0x3c00;
+  val.a[1] = 0x4000;
+  val.a[2] = 0x4400;
+  val.a[3] = 0x4800;
+#if AVX512F_LEN > 128
+  val.a[4] = 0xbc00;
+  val.a[5] = 0xc000;
+  val.a[6] = 0xc400;
+  val.a[7] = 0xc800;
+#endif
+#if AVX512F_LEN > 256
+  val.a[8] = 0x3c00;
+  val.a[9] = 0x4000;
+  val.a[10] = 0x4400;
+  val.a[11] = 0x4800;
+  val.a[12] = 0xbc00;
+  val.a[13] = 0xc000;
+  val.a[14] = 0xc400;
+  val.a[15] = 0xc800;
+#endif
+
+  res1.x = _mm512_cvtph_ps (val.x);
+  res2.x = _mm512_mask_cvtph_ps (res2.x, mask, val.x);
+  res3.x = _mm512_maskz_cvtph_ps (mask, val.x);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, exp))
+    abort ();
+
+  MASK_MERGE () (exp, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, exp))
+    abort ();
+
+  MASK_ZERO () (exp, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, exp))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2dq-1.c
new file mode 100644
index 000000000..7879e170e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2dq-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2dq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 s;
+volatile __m512i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtps_epi32 (s);
+  res = _mm512_mask_cvtps_epi32 (res, m, s);
+  res = _mm512_maskz_cvtps_epi32 (m, s);
+  res = _mm512_cvt_roundps_epi32 (s, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvt_roundps_epi32 (res, m, s, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvt_roundps_epi32 (m, s, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2dq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2dq-2.c
new file mode 100644
index 000000000..a35c2ad02
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2dq-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, float *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s[i] >= 0) ? (int) (s[i] + 0.5) : (int) (s[i] - 0.5);
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN,) src;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      res2.a[i] = DEFAULT_VALUE;
+      src.a[i] = 1.5 + 34.67 * i * sign;
+      sign = sign * -1;
+    }
+
+  res1.x = INTRINSIC (_cvtps_epi32) (src.x);
+  res2.x = INTRINSIC (_mask_cvtps_epi32) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtps_epi32) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2pd-1.c
new file mode 100644
index 000000000..c6fc47337
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2pd-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2pd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256 s;
+volatile __m512d res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtps_pd (s);
+  res = _mm512_mask_cvtps_pd (res, m, s);
+  res = _mm512_maskz_cvtps_pd (m, s);
+  res = _mm512_cvt_roundps_pd (s, _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvt_roundps_pd (res, m, s, _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvt_roundps_pd (m, s, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2pd-2.c
new file mode 100644
index 000000000..5bed4f33f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2pd-2.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE ((AVX512F_LEN_HALF) / 32)
+#include "avx512f-mask-type.h"
+#define DST_SIZE ((AVX512F_LEN) / 64)
+
+static void
+CALC (float *s, double *r)
+{
+  int i;
+
+  for (i = 0; i < DST_SIZE; i++)
+    {
+      r[i] = (double) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN_HALF, ) s;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[DST_SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_cvtps_pd) (s.x);
+  res2.x = INTRINSIC (_mask_cvtps_pd) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtps_pd) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-1.c
new file mode 100644
index 000000000..daf701484
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2ph\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m256i y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_cvtps_ph (x, 0);
+  y = _mm512_maskz_cvtps_ph (4, x, 0);
+  y = _mm512_mask_cvtps_ph (y, 2, x, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-2.c
new file mode 100644
index 000000000..6fe9effd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2ph-2.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) val;
+  UNION_TYPE (AVX512F_LEN_HALF, i_w) res1,res2,res3;
+  MASK_TYPE mask = MASK_VALUE;
+  short exp[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  val.a[0] = 1;
+  val.a[1] = 2;
+  val.a[2] = 4;
+  val.a[3] = 8;
+#if AVX512F_LEN > 128
+  val.a[4] = -1;
+  val.a[5] = -2;
+  val.a[6] = -4;
+  val.a[7] = -8;
+#endif
+#if AVX512F_LEN > 256
+  val.a[8] = 1;
+  val.a[9] = 2;
+  val.a[10] = 4;
+  val.a[11] = 8;
+  val.a[12] = -1;
+  val.a[13] = -2;
+  val.a[14] = -4;
+  val.a[15] = -8;
+#endif
+
+  exp[0] = 0x3c00;
+  exp[1] = 0x4000;
+  exp[2] = 0x4400;
+  exp[3] = 0x4800;
+#if AVX512F_LEN > 128
+  exp[4] = 0xbc00;
+  exp[5] = 0xc000;
+  exp[6] = 0xc400;
+  exp[7] = 0xc800;
+#endif
+#if AVX512F_LEN > 256
+  exp[8] = 0x3c00;
+  exp[9] = 0x4000;
+  exp[10] = 0x4400;
+  exp[11] = 0x4800;
+  exp[12] = 0xbc00;
+  exp[13] = 0xc000;
+  exp[14] = 0xc400;
+  exp[15] = 0xc800;
+#endif
+
+  res1.x = _mm512_cvtps_ph (val.x, 0);
+  res2.x = _mm512_mask_cvtps_ph (res2.x, mask, val.x, 0);
+  res3.x = _mm512_maskz_cvtps_ph (mask, val.x, 0);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res1, exp))
+    abort ();
+
+  MASK_MERGE (i_w) (exp, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res2, exp))
+    abort ();
+
+  MASK_ZERO (i_w) (exp, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res3, exp))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2udq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2udq-1.c
new file mode 100644
index 000000000..b1d9b9143
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2udq-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtps2udq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 s;
+volatile __m512i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtps_epu32 (s);
+  res = _mm512_mask_cvtps_epu32 (res, m, s);
+  res = _mm512_maskz_cvtps_epu32 (m, s);
+  res = _mm512_cvt_roundps_epu32 (s, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvt_roundps_epu32 (res, m, s, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvt_roundps_epu32 (m, s, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2udq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2udq-2.c
new file mode 100644
index 000000000..7826e2d79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtps2udq-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned *r, float *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    r[i] = (unsigned) (s[i] + 0.5);
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN,) src;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1.5 + 34.67 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtps_epu32) (src.x);
+  res2.x = INTRINSIC (_mask_cvtps_epu32) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtps_epu32) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c
new file mode 100644
index 000000000..219fc7147
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtsd2si\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile unsigned y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvt_roundsd_i32 (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c
new file mode 100644
index 000000000..7a9f1d893
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtsd2siq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile unsigned long long y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvt_roundsd_i64 (x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2ss-1.c
new file mode 100644
index 000000000..8aadb9ae0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2ss-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtsd2ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 s1, r;
+volatile __m128d s2;
+
+void extern
+avx512f_test (void)
+{
+  r = _mm_cvt_roundsd_ss (s1, s2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi-1.c
new file mode 100644
index 000000000..ec28c865a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtsd2usi\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2usi\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile unsigned y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvtsd_u32 (x);
+  y = _mm_cvt_roundsd_u32 (x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi-2.c
new file mode 100644
index 000000000..e53012446
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union128d s1;
+  unsigned int d;
+  unsigned int e;
+
+  s1.x = _mm_set_pd (24.43, 68.346);
+  d =  _mm_cvtsd_u32 (s1.x);
+  e = (unsigned int)(s1.a[0] + 0.5);
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi64-1.c
new file mode 100644
index 000000000..f76e752b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtsd2usi\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtsd2usi\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile unsigned long long y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvtsd_u64 (x);
+  y = _mm_cvt_roundsd_u64 (x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi64-2.c
new file mode 100644
index 000000000..92843d9e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2usi64-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union128d s1;
+  unsigned long long d;
+  unsigned long long e;
+
+  s1.x = _mm_set_pd (24.43, 68.346);
+  d =  _mm_cvtsd_u64 (s1.x);
+  e = (unsigned long long)(s1.a[0] + 0.5);
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2sd64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2sd64-1.c
new file mode 100644
index 000000000..d5e18fbf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2sd64-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtsi2sdq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile long long n;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_cvt_roundi64_sd (x, n, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss-1.c
new file mode 100644
index 000000000..1adca43f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtsi2ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile int n;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_cvt_roundi32_ss (x, n, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss64-1.c
new file mode 100644
index 000000000..098092666
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss64-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtsi2ssq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile long long n;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_cvt_roundi64_ss (x, n, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2sd-1.c
new file mode 100644
index 000000000..5b6a43f54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2sd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtss2sd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d s1, r;
+volatile __m128 s2;
+
+void extern
+avx512f_test (void)
+{
+  r = _mm_cvt_roundss_sd (s1, s2, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c
new file mode 100644
index 000000000..a0998a9ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtss2si\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile unsigned y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvt_roundss_i32 (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c
new file mode 100644
index 000000000..e429ead95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtss2siq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile unsigned long long y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvt_roundss_i64 (x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi-1.c
new file mode 100644
index 000000000..cc3bfcebe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtss2usi\[ \\t\]+\[^\n\]*%xmm\[0-9\]"  2 } } */
+/* { dg-final { scan-assembler-times "vcvtss2usi\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile unsigned y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvtss_u32 (x);
+  y = _mm_cvt_roundss_u32 (x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi-2.c
new file mode 100644
index 000000000..bdfab8309
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union128 s1;
+  unsigned int d;
+  unsigned int e;
+
+  s1.x = _mm_set_ps (24.43, 68.346, 35.7765, 34508.51);
+  d =  _mm_cvtss_u32 (s1.x);
+  e = (unsigned int)(s1.a[0] + 0.5);
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi64-1.c
new file mode 100644
index 000000000..6c5b01870
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvtss2usi\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2  } } */
+/* { dg-final { scan-assembler-times "vcvtss2usi\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile unsigned long long y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvtss_u64 (x);
+  y = _mm_cvt_roundss_u64 (x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi64-2.c
new file mode 100644
index 000000000..d19da3171
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2usi64-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union128 s1;
+  unsigned long long d;
+  unsigned long long e;
+
+  s1.x = _mm_set_ps (24.43, 68.346, 12.34, 80.67);
+  d =  _mm_cvtss_u64 (s1.x);
+  e = (unsigned long long)(s1.a[0] + 0.5);
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2dq-1.c
new file mode 100644
index 000000000..5fad1e354
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2dq-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2dq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d s;
+volatile __m256i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttpd_epi32 (s);
+  res = _mm512_mask_cvttpd_epi32 (res, m, s);
+  res = _mm512_maskz_cvttpd_epi32 (m, s);
+  res = _mm512_cvtt_roundpd_epi32 (s, _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvtt_roundpd_epi32 (res, m, s, _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvtt_roundpd_epi32 (m, s, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2dq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2dq-2.c
new file mode 100644
index 000000000..f73c5c3c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2dq-2.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE ((AVX512F_LEN) / 64)
+#include "avx512f-mask-type.h"
+#define DST_SIZE ((AVX512F_LEN_HALF) / 32)
+
+static void
+CALC (double *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      r[i] = (int) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s;
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[DST_SIZE] = { 0 };
+  int i, sign = 1;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_cvttpd_epi32) (s.x);
+  res2.x = INTRINSIC (_mask_cvttpd_epi32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvttpd_epi32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SRC_SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SRC_SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2udq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2udq-1.c
new file mode 100644
index 000000000..36f2e40c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2udq-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttpd2udq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d s;
+volatile __m256i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttpd_epu32 (s);
+  res = _mm512_mask_cvttpd_epu32 (res, m, s);
+  res = _mm512_maskz_cvttpd_epu32 (m, s);
+  res = _mm512_cvtt_roundpd_epu32 (s, _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvtt_roundpd_epu32 (res, m, s, _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvtt_roundpd_epu32 (m, s, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2udq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2udq-2.c
new file mode 100644
index 000000000..a8d3adc8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttpd2udq-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE ((AVX512F_LEN) / 64)
+#include "avx512f-mask-type.h"
+#define DST_SIZE ((AVX512F_LEN_HALF) / 32)
+
+static void
+CALC (double *s, unsigned *r)
+{
+  int i;
+
+  for (i = 0; i < DST_SIZE; i++)
+    {
+      r[i] = (unsigned) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s;
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned res_ref[DST_SIZE] = { 0 };
+  int i;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000);
+    }
+
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_cvttpd_epu32) (s.x);
+  res2.x = INTRINSIC (_mask_cvttpd_epu32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvttpd_epu32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SRC_SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SRC_SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2dq-1.c
new file mode 100644
index 000000000..a156dbee9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2dq-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvttps2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttps2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttps2dq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttps2dq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[\\n\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttps2dq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttps2dq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 s;
+volatile __m512i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttps_epi32 (s);
+  res = _mm512_mask_cvttps_epi32 (res, m, s);
+  res = _mm512_maskz_cvttps_epi32 (m, s);
+  res = _mm512_cvtt_roundps_epi32 (s, _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvtt_roundps_epi32 (res, m, s, _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvtt_roundps_epi32 (m, s, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2dq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2dq-2.c
new file mode 100644
index 000000000..f2cb5c708
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2dq-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, float *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    r[i] = (int) s[i];
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN,) src;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      res2.a[i] = DEFAULT_VALUE;
+      src.a[i] = 1.5 + 34.67 * i * sign;
+      sign = sign * -1;
+    }
+
+  res1.x = INTRINSIC (_cvttps_epi32) (src.x);
+  res2.x = INTRINSIC (_mask_cvttps_epi32) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvttps_epi32) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2udq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2udq-1.c
new file mode 100644
index 000000000..ffbfdfca3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2udq-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvttps2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttps2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttps2udq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttps2udq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[\\n\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttps2udq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvttps2udq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 s;
+volatile __m512i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvttps_epu32 (s);
+  res = _mm512_mask_cvttps_epu32 (res, m, s);
+  res = _mm512_maskz_cvttps_epu32 (m, s);
+  res = _mm512_cvtt_roundps_epu32 (s, _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvtt_roundps_epu32 (res, m, s, _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvtt_roundps_epu32 (m, s, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2udq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2udq-2.c
new file mode 100644
index 000000000..2b0212e1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttps2udq-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned *r, float *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    r[i] = (unsigned) s[i];
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN,) src;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1.5 + 34.67 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvttps_epu32) (src.x);
+  res2.x = INTRINSIC (_mask_cvttps_epu32) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvttps_epu32) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c
new file mode 100644
index 000000000..e813a24a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvttsd2si\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttsd2si\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvttsd_i32 (x);
+  y = _mm_cvtt_roundsd_i32 (x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-2.c
new file mode 100644
index 000000000..a447a8734
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+
+static int
+__attribute__ ((noinline, unused))
+test (__m128d x)
+{
+  return _mm_cvttsd_i32 (x);
+}
+
+static void
+avx512f_test (void)
+{
+  union128d s1;
+  int res, res_ref;
+
+  s1.x = _mm_set_pd (123.321, 456.987);
+  res = test (s1.x);
+  res_ref = (int) s1.a[0];
+
+  if (res != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c
new file mode 100644
index 000000000..a3b870c10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvttsd2siq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttsd2siq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile long long y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvttsd_i64 (x);
+  y = _mm_cvtt_roundsd_i64 (x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-2.c
new file mode 100644
index 000000000..7b759c1fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+
+static int
+__attribute__ ((noinline, unused))
+test (__m128d x)
+{
+  return _mm_cvttsd_i64 (x);
+}
+
+static void
+avx512f_test (void)
+{
+  union128d s1;
+  long long res, res_ref;
+
+  s1.x = _mm_set_pd (123.321, 456.987);
+  res = test (s1.x);
+  res_ref = (long long) s1.a[0];
+
+  if (res != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi-1.c
new file mode 100644
index 000000000..3a88517a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvttsd2usi\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttsd2usi\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile unsigned y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvttsd_u32 (x);
+  y = _mm_cvtt_roundsd_u32 (x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi-2.c
new file mode 100644
index 000000000..00f7eb6e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static unsigned int
+__attribute__((noinline, unused))
+test (union128d s1)
+{
+  return _mm_cvttsd_u32 (s1.x);
+}
+
+void static
+avx512f_test (void)
+{
+  union128d s1;
+  unsigned int d;
+  unsigned int e;
+
+  s1.x = _mm_set_pd (24.43, 68.346);
+  d =  test (s1);
+  e = (unsigned int)s1.a[0];
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi64-1.c
new file mode 100644
index 000000000..87bbcb7be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvttsd2usi\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvttsd2usi\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile unsigned long long y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvttsd_u64 (x);
+  y = _mm_cvtt_roundsd_u64 (x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi64-2.c
new file mode 100644
index 000000000..4aa45ef82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2usi64-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static unsigned long long
+__attribute__((noinline, unused))
+test (union128d s1)
+{
+  return _mm_cvttsd_u64 (s1.x);
+}
+
+void static
+avx512f_test (void)
+{
+  union128d s1;
+  unsigned long long d;
+  unsigned long long e;
+
+  s1.x = _mm_set_pd (24.43, 68.346);
+  d =  test (s1);
+  e = (unsigned long long)s1.a[0];
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c
new file mode 100644
index 000000000..7669a1729
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvttss2si\[ \\t\]+\[^\n\]*%xmm\[0-9\]"  2 } } */
+/* { dg-final { scan-assembler-times "vcvttss2si\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvttss_i32 (x);
+  y = _mm_cvtt_roundss_i32 (x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-2.c
new file mode 100644
index 000000000..2aa62c071
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+
+static int
+__attribute__ ((noinline, unused))
+test (__m128 x)
+{
+  return _mm_cvttss_i32 (x);
+}
+
+static void
+avx512f_test (void)
+{
+  union128 s1;
+  int res, res_ref;
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  res = test (s1.x);
+  res_ref = (int) s1.a[0];
+
+  if (res != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c
new file mode 100644
index 000000000..4888d6d1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvttss2siq\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2  } } */
+/* { dg-final { scan-assembler-times "vcvttss2siq\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile long long y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvttss_i64 (x);
+  y = _mm_cvtt_roundss_i64 (x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-2.c
new file mode 100644
index 000000000..cf33b997a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+
+static int
+__attribute__ ((noinline, unused))
+test (__m128 x)
+{
+  return _mm_cvttss_i64 (x);
+}
+
+static void
+avx512f_test (void)
+{
+  union128 s1;
+  long long res, res_ref;
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  res = test (s1.x);
+  res_ref = (long long) s1.a[0];
+
+  if (res != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi-1.c
new file mode 100644
index 000000000..b27027635
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvttss2usi\[ \\t\]+\[^\n\]*%xmm\[0-9\]"  2 } } */
+/* { dg-final { scan-assembler-times "vcvttss2usi\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile unsigned y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvttss_u32 (x);
+  y = _mm_cvtt_roundss_u32 (x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi-2.c
new file mode 100644
index 000000000..4d1910477
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static unsigned int
+__attribute__((noinline, unused))
+test (union128 s1)
+{
+  return _mm_cvttss_u32 (s1.x);
+}
+
+void static
+avx512f_test (void)
+{
+  union128 s1;
+  unsigned int d;
+  unsigned int e;
+
+  s1.x = _mm_set_ps (24.43, 68.346, 45.12, 90.97);
+  d =  test (s1);
+  e = (unsigned int)s1.a[0];
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi64-1.c
new file mode 100644
index 000000000..7c3b473c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vcvttss2usi\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2  } } */
+/* { dg-final { scan-assembler-times "vcvttss2usi\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile unsigned long long y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm_cvttss_u64 (x);
+  y = _mm_cvtt_roundss_u64 (x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi64-2.c
new file mode 100644
index 000000000..85f55d6cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2usi64-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static unsigned long long
+__attribute__((noinline, unused))
+test (union128 s1)
+{
+  return _mm_cvttss_u64 (s1.x);
+}
+
+void static
+avx512f_test (void)
+{
+  union128 s1;
+  unsigned long long d;
+  unsigned long long e;
+
+  s1.x = _mm_set_ps (24.43, 68.346, 10.756, 89.145);
+  d =  test (s1);
+  e = (unsigned long long)s1.a[0];
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2pd-1.c
new file mode 100644
index 000000000..933e785e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2pd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtudq2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtudq2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtudq2pd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i s;
+volatile __m512d res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepu32_pd (s);
+  res = _mm512_mask_cvtepu32_pd (res, m, s);
+  res = _mm512_maskz_cvtepu32_pd (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2pd-2.c
new file mode 100644
index 000000000..814a7b769
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2pd-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE ((AVX512F_LEN_HALF) / 32)
+#include "avx512f-mask-type.h"
+#define DST_SIZE ((AVX512F_LEN) / 64)
+
+static void
+CALC (unsigned *s, double *r)
+{
+  int i;
+
+  for (i = 0; i < DST_SIZE; i++)
+    {
+      r[i] = (double) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) s;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[DST_SIZE];
+  int i;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s.a[i] = 123456 * (i + 2000);
+    }
+
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_cvtepu32_pd) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepu32_pd) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepu32_pd) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2ps-1.c
new file mode 100644
index 000000000..cb904b95d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2ps-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtudq2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vcvtudq2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtudq2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtudq2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtudq2ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtudq2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m512 res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepu32_ps (s);
+  res = _mm512_mask_cvtepu32_ps (res, m, s);
+  res = _mm512_maskz_cvtepu32_ps (m, s);
+  res = _mm512_cvt_roundepu32_ps (s, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  res = _mm512_mask_cvt_roundepu32_ps (res, m, s, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  res = _mm512_maskz_cvt_roundepu32_ps (m, s, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2ps-2.c
new file mode 100644
index 000000000..c43df063a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtudq2ps-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned *s, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (float) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s;
+  UNION_TYPE (AVX512F_LEN, ) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 123456 * (i + 2000);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepu32_ps) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepu32_ps) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepu32_ps) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-1.c
new file mode 100644
index 000000000..b00c321c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vcvtusi2sd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile unsigned n;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_cvtu32_sd (x, n);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-2.c
new file mode 100644
index 000000000..2100cbeb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static void
+  __attribute__ ((noinline, unused))
+compute_vcvtusi2sd (double *s1, unsigned s2, double *r)
+{
+  r[0] = (double) s2;
+  r[1] = s1[1];
+}
+
+static void
+avx512f_test (void)
+{
+  union128d s1, res;
+  unsigned s2;
+  double res_ref[2];
+
+  s1.x = _mm_set_pd (-24.43, -43.35);
+  s2 = 0xFEDCA987;
+
+  res.x = _mm_cvtu32_sd (s1.x, s2);
+
+  compute_vcvtusi2sd (s1.a, s2, res_ref);
+
+  if (check_union128d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-1.c
new file mode 100644
index 000000000..9bfafce46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtusi2sd\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtusi2sd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile unsigned long long n;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_cvtu64_sd (x, n);
+  x = _mm_cvt_roundu64_sd (x, n, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-2.c
new file mode 100644
index 000000000..997e21bb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static void
+  __attribute__ ((noinline, unused))
+compute_vcvtusi2sd (double *s1, unsigned long long s2, double *r)
+{
+  r[0] = (double) s2;
+  r[1] = s1[1];
+}
+
+static void
+avx512f_test (void)
+{
+  union128d s1, res;
+  unsigned long long s2;
+  double res_ref[4];
+
+  s1.x = _mm_set_pd (-24.43, -43.35);
+  s2 = 0xFEDCBA9876543210;
+
+  res.x = _mm_cvtu64_sd (s1.x, s2);
+
+  compute_vcvtusi2sd (s1.a, s2, res_ref);
+
+  if (check_union128d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-1.c
new file mode 100644
index 000000000..5214af6ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile unsigned n;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_cvtu32_ss (x, n);
+  x = _mm_cvt_roundu32_ss (x, n, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-2.c
new file mode 100644
index 000000000..b5f67dd0b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static void
+  __attribute__ ((noinline, unused))
+compute_vcvtusi2ss (float *s1, unsigned s2, float *r)
+{
+  r[0] = (float) s2;
+  r[1] = s1[1];
+  r[2] = s1[2];
+  r[3] = s1[3];
+}
+
+static void
+avx512f_test (void)
+{
+  union128 s1, res;
+  unsigned s2;
+  float res_ref[4];
+
+  s1.x = _mm_set_ps (-24.43, 68.346, -43.35, 546.46);
+  s2 = 0xFEDCA987;
+
+  res.x = _mm_cvtu32_ss (s1.x, s2);
+
+  compute_vcvtusi2ss (s1.a, s2, res_ref);
+
+  if (check_union128 (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-1.c
new file mode 100644
index 000000000..70ed64a2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\n\]*%xmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile unsigned long long n;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_cvtu64_ss (x, n);
+  x = _mm_cvt_roundu64_ss (x, n, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-2.c
new file mode 100644
index 000000000..eeb499aac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+static void
+  __attribute__ ((noinline, unused))
+compute_vcvtusi2ss (float *s1, unsigned long long s2, float *r)
+{
+  r[0] = (float) s2;
+  r[1] = s1[1];
+  r[2] = s1[2];
+  r[3] = s1[3];
+}
+
+static void
+avx512f_test (void)
+{
+  union128 s1, res;
+  unsigned long long s2;
+  float res_ref[4];
+
+  s1.x = _mm_set_ps (-24.43, 68.346, -43.35, 546.46);
+  s2 = 0xFEDCBA9876543210;
+
+  res.x = _mm_cvtu64_ss (s1.x, s2);
+
+  compute_vcvtusi2ss (s1.a, s2, res_ref);
+
+  if (check_union128 (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivpd-1.c
new file mode 100644
index 000000000..2695ecb1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivpd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vdivpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vdivpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vdivpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vdivpd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vdivpd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vdivpd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_div_pd (x, x);
+  x = _mm512_mask_div_pd (x, m, x, x);
+  x = _mm512_maskz_div_pd (m, x, x);
+  x = _mm512_div_round_pd (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_div_round_pd (x, m, x, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_div_round_pd (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivpd-2.c
new file mode 100644
index 000000000..761ee20f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s1, double *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] / s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign + 1.0;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_div_pd) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_div_pd) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_div_pd) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivps-1.c
new file mode 100644
index 000000000..367b1af46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_div_ps (x, x);
+  x = _mm512_mask_div_ps (x, m, x, x);
+  x = _mm512_maskz_div_ps (m, x, x);
+  x = _mm512_div_round_ps (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_div_round_ps (x, m, x, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_div_round_ps (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivps-2.c
new file mode 100644
index 000000000..f5a7b78f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivps-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s1, float *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] / s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign + 1.0;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_div_ps) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_div_ps) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_div_ps) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_FP_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_FP_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivsd-1.c
new file mode 100644
index 000000000..605304b31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivsd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vdivsd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_div_round_sd (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivss-1.c
new file mode 100644
index 000000000..27303ba3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vdivss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vdivss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_div_round_ss (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vec-init.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vec-init.c
new file mode 100644
index 000000000..acbd34f3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vec-init.c
@@ -0,0 +1,121 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vmovdqa64\[ \\t\]+%zmm" 2 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastd" 1 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastq" 1 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastb" 2 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastw" 2 } } */
+/* { dg-final { scan-assembler-times "vbroadcastss" 1 } } */
+/* { dg-final { scan-assembler-times "vbroadcastsd" 1 } } */
+
+#include <x86intrin.h>
+
+typedef char __v64qi __attribute__ ((vector_size (64)));
+typedef short __v32hi __attribute__ ((vector_size (64)));
+
+__v64qi foo_1 (char c)
+{
+  __v64qi v1 = {
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
+
+__v32hi foo_2 (short c)
+{
+  __v32hi v1 = {
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
+
+__v16si foo_3 (int c)
+{
+  __v16si v1 = {
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
+
+__v8di foo_4 (long long c)
+{
+  __v8di v1 = {
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
+
+__v32qi foo_5 (char c)
+{
+  __v32qi v1 = {
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
+
+__v16hi foo_6 (short c)
+{
+  __v16hi v1 = {
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
+
+__v8si foo_7 (int c)
+{
+  __v8si v1 = {
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
+
+__v4di foo_8 (long long c)
+{
+  __v4di v1 = {
+      c, c, c, c
+  };
+
+  return v1;
+}
+
+
+__v16qi foo_9 (char c)
+{
+  __v16qi v1 = {
+      c, c, c, c, c, c, c, c,
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
+
+__v8hi foo_10(short c)
+{
+  __v8hi v1 = {
+      c, c, c, c, c, c, c, c
+  };
+
+  return v1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vec-unpack.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vec-unpack.c
new file mode 100644
index 000000000..8dcdac7b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vec-unpack.c
@@ -0,0 +1,127 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx512f" } */
+
+long long *D;
+int *S;
+short *H;
+char *Q;
+
+long long foo_unpack_1 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    D[i] *= S[i];
+
+  return D[ind];
+}
+
+long long foo_unpack_2 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    D[i] *= H[i];
+
+  return D[ind];
+}
+
+long long foo_unpack_3 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    D[i] *= Q[i];
+
+  return D[ind];
+}
+
+int foo_unpack_4 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    S[i] *= H[i];
+
+  return S[ind];
+}
+
+int foo_unpack_5 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    S[i] *= Q[i];
+
+  return S[ind];
+}
+
+short foo_unpack_6 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    H[i] *= Q[i];
+
+  return H[ind];
+}
+
+int foo_expand_1 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    S[i] *= D[i];
+
+  return S[ind];
+}
+
+short foo_expand_2 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    H[i] *= D[i];
+
+  return H[ind];
+}
+
+char foo_expand_3 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    Q[i] *= D[i];
+
+  return Q[ind];
+}
+
+short foo_expand_4 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    H[i] *= S[i];
+
+  return H[ind];
+}
+
+char foo_expand_5 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    Q[i] *= S[i];
+
+  return Q[ind];
+}
+
+char foo_expand_6 (int low, int high, int ind)
+{
+  int i;
+
+  for (i = low; i <= high; i++)
+    Q[i] *= H[i];
+
+  return Q[ind];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandpd-1.c
new file mode 100644
index 000000000..b7648c6d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandpd-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vexpandpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 4 } } */
+/* { dg-final { scan-assembler-times "vexpandpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vexpandpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+
+#include <immintrin.h>
+
+double *p;
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_expand_pd (x, m, x);
+  x = _mm512_maskz_expand_pd (m, x);
+
+  x = _mm512_mask_expandloadu_pd (x, m, p);
+  x = _mm512_maskz_expandloadu_pd (m, p);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandpd-2.c
new file mode 100644
index 000000000..373c17df1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandpd-2.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s, double *r, MASK_TYPE mask)
+{
+  int i, k;
+
+  for (i = 0, k = 0; i < SIZE; i++)
+    {
+      if (mask & (1 << i))
+	r[i] = s[k++];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, res2, res3, res4, res5;
+  MASK_TYPE mask = MASK_VALUE;
+  double s2[SIZE];
+  double res_ref1[SIZE];
+  double res_ref2[SIZE];
+  double res_ref3[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 123.456 * (i + 200) * sign;
+      s2[i] = 789.012 * (i + 300) * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      res4.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res2.x = INTRINSIC (_mask_expand_pd) (res2.x, mask, s1.x);
+  res3.x = INTRINSIC (_maskz_expand_pd) (mask, s1.x);
+  res4.x = INTRINSIC (_mask_expandloadu_pd) (res4.x, mask, s2);
+  res5.x = INTRINSIC (_maskz_expandloadu_pd) (mask, s2);
+
+  /* no mask is the same as all ones mask.  */
+  CALC (s1.a, res_ref1, MASK_ALL_ONES);
+  CALC (s1.a, res_ref2, mask);
+  CALC (s2, res_ref3, mask);
+
+  MASK_MERGE (d) (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref2))
+    abort ();
+
+  MASK_ZERO (d) (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref2))
+    abort ();
+
+  MASK_MERGE (d) (res_ref3, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res4, res_ref3))
+    abort ();
+
+  MASK_ZERO (d) (res_ref3, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res5, res_ref3))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandps-1.c
new file mode 100644
index 000000000..b0a36c300
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandps-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vexpandps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 4 } } */
+/* { dg-final { scan-assembler-times "vexpandps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vexpandps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+
+#include <immintrin.h>
+
+float *p;
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_expand_ps (x, m, x);
+  x = _mm512_maskz_expand_ps (m, x);
+
+  x = _mm512_mask_expandloadu_ps (x, m, p);
+  x = _mm512_maskz_expandloadu_ps (m, p);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandps-2.c
new file mode 100644
index 000000000..7143c8ae2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vexpandps-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s, float *r, MASK_TYPE mask)
+{
+  int i, k;
+
+  for (i = 0, k = 0; i < SIZE; i++)
+    {
+      if (mask & (1 << i))
+	r[i] = s[k++];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s1, res2, res3, res4, res5;
+  MASK_TYPE mask = MASK_VALUE;
+  float s2[SIZE];
+  float res_ref1[SIZE];
+  float res_ref2[SIZE];
+  float res_ref3[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 123.456 * (i + 200) * sign;
+      s2[i] = 789.012 * (i + 300) * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      res4.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res2.x = INTRINSIC (_mask_expand_ps) (res2.x, mask, s1.x);
+  res3.x = INTRINSIC (_maskz_expand_ps) (mask, s1.x);
+  res4.x = INTRINSIC (_mask_expandloadu_ps) (res4.x, mask, s2);
+  res5.x = INTRINSIC (_maskz_expandloadu_ps) (mask, s2);
+
+  CALC (s1.a, res_ref1, MASK_ALL_ONES);
+  CALC (s1.a, res_ref2, mask);
+  CALC (s2, res_ref3, mask);
+
+  MASK_MERGE () (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref2))
+    abort ();
+
+  MASK_ZERO () (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref2))
+    abort ();
+
+  MASK_MERGE () (res_ref3, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res4, res_ref3))
+    abort ();
+
+  MASK_ZERO () (res_ref3, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res5, res_ref3))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf32x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf32x4-1.c
new file mode 100644
index 000000000..b32d161ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf32x4-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vextractf32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vextractf32x4\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vextractf32x4\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m128 y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_extractf32x4_ps (x, 1);
+  y = _mm512_mask_extractf32x4_ps (y, 2, x, 1);
+  y = _mm512_maskz_extractf32x4_ps (2, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf32x4-2.c
new file mode 100644
index 000000000..35377b430
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf32x4-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "string.h"
+
+void
+CALC (UNION_TYPE (AVX512F_LEN,) s1, float *res_ref, int mask)
+{
+  memset (res_ref, 0, 16);
+  memcpy (res_ref, s1.a + mask * 4, 16);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) s1;
+  union128 res1, res2, res3;
+  float res_ref[4];
+  MASK_TYPE mask = MASK_VALUE;
+  int j;
+
+  for (j = 0; j < SIZE; j++)
+    {
+      s1.a[j] = j * j / 4.56;
+    }
+
+  for (j = 0; j < 4; j++)
+    {
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_extractf32x4_ps) (s1.x, 1);
+  res2.x = INTRINSIC (_mask_extractf32x4_ps) (res2.x, mask, s1.x, 1);
+  res3.x = INTRINSIC (_maskz_extractf32x4_ps) (mask, s1.x, 1);
+  CALC (s1, res_ref, 1);
+
+  if (check_union128 (res1, res_ref))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, 4);
+  if (check_union128 (res2, res_ref))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, 4);
+  if (check_union128 (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf64x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf64x4-1.c
new file mode 100644
index 000000000..6259ac806
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf64x4-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vextractf64x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vextractf64x4\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vextractf64x4\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m256d y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_extractf64x4_pd (x, 1);
+  y = _mm512_maskz_extractf64x4_pd (2, x, 1);
+  y = _mm512_mask_extractf64x4_pd (y, 2, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf64x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf64x4-2.c
new file mode 100644
index 000000000..b73044917
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextractf64x4-2.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-options "-O2 -mavx512f" } */
+
+#include <string.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+void static
+avx512f_test (void)
+{
+  union512d s1;
+  union256d res1, res2, res3;
+  __mmask8 mask = 0xBA;
+  double res_ref[4];
+  int j;
+
+  for (j = 0; j < 8; j++)
+    {
+      s1.a[j] = j * j / 4.56;
+    }
+
+  for (j = 0; j < 4; j++)
+    {
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+    }
+
+  res1.x = _mm512_extractf64x4_pd (s1.x, 0);
+  res2.x = _mm512_mask_extractf64x4_pd (res2.x, mask, s1.x, 0);
+  res3.x = _mm512_maskz_extractf64x4_pd (mask, s1.x, 0);
+
+  memset (res_ref, 0, 32);
+  memcpy (res_ref, s1.a, 32);
+
+  if (check_union256d (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, 4);
+  if (check_union256d (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, 4);
+  if (check_union256d (res3, res_ref))
+    abort ();
+
+  res1.x = _mm512_extractf64x4_pd (s1.x, 1);
+  res2.x = _mm512_mask_extractf64x4_pd (res2.x, mask, s1.x, 1);
+  res3.x = _mm512_maskz_extractf64x4_pd (mask, s1.x, 1);
+
+  memset (res_ref, 0, 32);
+  memcpy (res_ref, s1.a + 4, 32);
+
+  if (check_union256d (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, 4);
+  if (check_union256d (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, 4);
+  if (check_union256d (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti32x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti32x4-1.c
new file mode 100644
index 000000000..87c92f7b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti32x4-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vextracti32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vextracti32x4\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vextracti32x4\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_extracti32x4_epi32 (x, 1);
+  y = _mm512_mask_extracti32x4_epi32 (y, 2, x, 1);
+  y = _mm512_maskz_extracti32x4_epi32 (2, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti32x4-2.c
new file mode 100644
index 000000000..1ea77b034
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti32x4-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "string.h"
+
+void
+CALC (UNION_TYPE (AVX512F_LEN, i_d) s1, int *res_ref, int mask)
+{
+  memset (res_ref, 0, 16);
+  memcpy (res_ref, s1.a + mask * 4, 16);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1;
+  union128i_d res1, res2, res3;
+  int res_ref[4];
+  MASK_TYPE mask = MASK_VALUE;
+  int j;
+
+  for (j = 0; j < SIZE; j++)
+    {
+      s1.a[j] = j * j / 4.56;
+    }
+
+  for (j = 0; j < 4; j++)
+    {
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_extracti32x4_epi32) (s1.x, 1);
+  res2.x =
+    INTRINSIC (_mask_extracti32x4_epi32) (res2.x, mask, s1.x, 1);
+  res3.x = INTRINSIC (_maskz_extracti32x4_epi32) (mask, s1.x, 1);
+  CALC (s1, res_ref, 1);
+
+  if (check_union128i_d (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, 4);
+  if (check_union128i_d (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, 4);
+  if (check_union128i_d (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti64x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti64x4-1.c
new file mode 100644
index 000000000..71268bcbe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti64x4-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vextracti64x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vextracti64x4\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vextracti64x4\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m256i y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_extracti64x4_epi64 (x, 1);
+  y = _mm512_mask_extracti64x4_epi64 (y, 2, x, 1);
+  y = _mm512_maskz_extracti64x4_epi64 (2, x, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti64x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti64x4-2.c
new file mode 100644
index 000000000..9753d2461
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vextracti64x4-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-options "-O2 -mavx512f" } */
+
+#include <string.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+void static
+avx512f_test (void)
+{
+  union512i_q s1;
+  union256i_q res1, res2, res3;
+  __mmask8 mask = 0xBA;
+  long long int res_ref[4];
+  int j;
+
+  for (j = 0; j < 8; j++)
+    s1.a[j] = j * j;
+
+  for (j = 0; j < 4; j++)
+    {
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+    }
+  res1.x = _mm512_extracti64x4_epi64 (s1.x, 0);
+  res2.x = _mm512_mask_extracti64x4_epi64 (res2.x, mask, s1.x, 0);
+  res3.x = _mm512_maskz_extracti64x4_epi64 (mask, s1.x, 0);
+
+  memset (res_ref, 0, 32);
+  memcpy (res_ref, s1.a, 32);
+
+  if (check_union256i_q (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, 4);
+  if (check_union256i_q (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, 4);
+  if (check_union256i_q (res3, res_ref))
+    abort ();
+
+  res1.x = _mm512_extracti64x4_epi64 (s1.x, 1);
+  res2.x = _mm512_mask_extracti64x4_epi64 (res2.x, mask, s1.x, 1);
+  res3.x = _mm512_maskz_extracti64x4_epi64 (mask, s1.x, 1);
+
+  memset (res_ref, 0, 32);
+  memcpy (res_ref, s1.a + 4, 32);
+
+  if (check_union256i_q (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, 4);
+  if (check_union256i_q (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, 4);
+  if (check_union256i_q (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-1.c
new file mode 100644
index 000000000..e452ebcff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vfixupimmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vfixupimmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfixupimmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfixupimmpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vfixupimmpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfixupimmpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x1, x2;
+volatile __m512i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fixupimm_pd (x1, x2, y, 3);
+  x1 = _mm512_mask_fixupimm_pd (x1, m, x2, y, 3);
+  x1 = _mm512_maskz_fixupimm_pd (m, x1, x2, y, 3);
+  x1 = _mm512_fixupimm_round_pd (x1, x2, y, 3, _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fixupimm_round_pd (x1, m, x2, y, 3, _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fixupimm_round_pd (m, x1, x2, y, 3, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-2.c
new file mode 100644
index 000000000..d4ddd3214
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmpd-2.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -std=gnu99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (double *r, double src, long long tbl)
+{
+  switch (tbl & 0xf)
+    {
+    case 0:
+      *r = src;
+      break;
+    case 1:
+      *r = src;
+      break;
+    case 2:
+      *r = signbit (src) ? -NAN : NAN;
+      break;
+    case 3:
+      *r = -NAN;
+      break;
+    case 4:
+      *r = -INFINITY;
+      break;
+    case 5:
+      *r = INFINITY;
+      break;
+    case 6:
+      *r = signbit (src) ? -INFINITY : INFINITY;
+      break;
+    case 7:
+      *r = 1.0 / -INFINITY;
+      break;
+    case 8:
+      *r = 0.0;
+      break;
+    case 9:
+      *r = -1.0;
+      break;
+    case 10:
+      *r = 1.0;
+      break;
+    case 11:
+      *r = 1.0 / 2.0;
+      break;
+    case 12:
+      *r = 90.0;
+      break;
+    case 13:
+      *r = M_PI_2;
+      break;
+    case 14:
+      *r = MAXDOUBLE;
+      break;
+    case 15:
+      *r = -MAXDOUBLE;
+      break;
+    default:
+      abort ();
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, j, k;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, s1;
+  UNION_TYPE (AVX512F_LEN, i_q) s2;
+  double res_ref[SIZE];
+
+
+  float vals[2] = { -10, 10 };
+  int controls[8] = {0x11111111, 0x77777777, 0x77777777, 0x88888888,
+    0x99999999, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc};
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < 2; i++)
+    {
+      for (j = 0; j < SIZE; j++)
+	{
+	  s1.a[j] = vals[i];
+	  s2.a[j] = controls[j];
+	  res1.a[j] = DEFAULT_VALUE;
+	  res2.a[j] = DEFAULT_VALUE;
+	  res3.a[j] = DEFAULT_VALUE;
+
+	  CALC (&res_ref[j], s1.a[j], s2.a[j]);
+	}
+
+      res1.x = INTRINSIC (_fixupimm_pd) (res1.x, s1.x, s2.x, 0);
+      res2.x = INTRINSIC (_mask_fixupimm_pd) (res2.x, mask, s1.x, s2.x, 0);
+      res3.x = INTRINSIC (_maskz_fixupimm_pd) (mask, res3.x, s1.x, s2.x, 0);
+
+      if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE(d) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+	abort ();
+      MASK_ZERO(d) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+	abort ();
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-1.c
new file mode 100644
index 000000000..5cf045df3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfixupimmps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x1, x2;
+volatile __m512i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fixupimm_ps (x1, x2, y, 3);
+  x1 = _mm512_mask_fixupimm_ps (x1, m, x2, y, 3);
+  x1 = _mm512_maskz_fixupimm_ps (m, x1, x2, y, 3);
+  x1 = _mm512_fixupimm_round_ps (x1, x2, y, 3, _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fixupimm_round_ps (x1, m, x2, y, 3, _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fixupimm_round_ps (m, x1, x2, y, 3, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-2.c
new file mode 100644
index 000000000..6c2539d0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmps-2.c
@@ -0,0 +1,122 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -std=gnu99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (float *r, float src, int tbl)
+{
+  switch (tbl & 0xf)
+    {
+    case 0:
+      *r = src;
+      break;
+    case 1:
+      *r = src;
+      break;
+    case 2:
+      *r = signbit (src) ? -NAN : NAN;
+      break;
+    case 3:
+      *r = -NAN;
+      break;
+    case 4:
+      *r = -INFINITY;
+      break;
+    case 5:
+      *r = INFINITY;
+      break;
+    case 6:
+      *r = signbit (src) ? -INFINITY : INFINITY;
+      break;
+    case 7:
+      *r = 1.0 / -INFINITY;
+      break;
+    case 8:
+      *r = 0.0;
+      break;
+    case 9:
+      *r = -1.0;
+      break;
+    case 10:
+      *r = 1.0;
+      break;
+    case 11:
+      *r = 1.0 / 2.0;
+      break;
+    case 12:
+      *r = 90.0;
+      break;
+    case 13:
+      *r = M_PI_2;
+      break;
+    case 14:
+      *r = MAXFLOAT;
+      break;
+    case 15:
+      *r = -MAXFLOAT;
+      break;
+    default:
+      abort ();
+    }
+}
+
+
+void static
+TEST (void)
+{
+  int i, j, k;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3, s1;
+  UNION_TYPE (AVX512F_LEN, i_d) s2;
+  float res_ref[SIZE];
+
+
+  float vals[2] = { -10, 10 };
+  int controls[16] = { 0x11111111,
+    0x77777777, 0x88888888, 0x99999999,
+    0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc,
+    0x77777777, 0x88888888, 0x99999999,
+    0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc,
+    0xdddddddd, 0xeeeeeeee, 0xffffffff
+  };
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < 2; i++)
+    {
+      for (j = 0; j < SIZE; j++)
+	{
+	  s1.a[j] = vals[i];
+	  s2.a[j] = controls[j];
+	  res1.a[j] = DEFAULT_VALUE;
+	  res2.a[j] = DEFAULT_VALUE;
+	  res3.a[j] = DEFAULT_VALUE;
+
+	  CALC (&res_ref[j], s1.a[j], s2.a[j]);
+	}
+
+      res1.x = INTRINSIC (_fixupimm_ps) (res1.x, s1.x, s2.x, 0);
+      res2.x = INTRINSIC (_mask_fixupimm_ps) (res2.x, mask, s1.x, s2.x, 0);
+      res3.x = INTRINSIC (_maskz_fixupimm_ps) (mask, res3.x, s1.x, s2.x, 0);
+
+      if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE() (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+	abort ();
+      MASK_ZERO() (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+	abort ();
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-1.c
new file mode 100644
index 000000000..76676afef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vfixupimmsd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vfixupimmsd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfixupimmsd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfixupimmsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vfixupimmsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfixupimmsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile __m128i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_fixupimm_sd (x, x, y, 3);
+  x = _mm_mask_fixupimm_sd (x, m, x, y, 3);
+  x = _mm_maskz_fixupimm_sd (m, x, x, y, 3);
+  x = _mm_fixupimm_round_sd (x, x, y, 3, _MM_FROUND_NO_EXC);
+  x = _mm_mask_fixupimm_round_sd (x, m, x, y, 3, _MM_FROUND_NO_EXC);
+  x = _mm_maskz_fixupimm_round_sd (m, x, x, y, 3, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-2.c
new file mode 100644
index 000000000..1344c7fd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmsd-2.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2 -std=gnu99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+#include <math.h>
+#include <values.h>
+#include "avx512f-mask-type.h"
+
+void
+compute_fixupimmpd (double *r, double src, long long tbl)
+{
+  switch (tbl & 0xf)
+    {
+    case 0:
+      *r = src;
+      break;
+    case 1:
+      *r = src;
+      break;
+    case 2:
+      *r = signbit (src) ? -NAN : NAN;
+      break;
+    case 3:
+      *r = -NAN;
+      break;
+    case 4:
+      *r = -INFINITY;
+      break;
+    case 5:
+      *r = INFINITY;
+      break;
+    case 6:
+      *r = signbit (src) ? -INFINITY : INFINITY;
+      break;
+    case 7:
+      *r = 1.0 / -INFINITY;
+      break;
+    case 8:
+      *r = 0.0;
+      break;
+    case 9:
+      *r = -1.0;
+      break;
+    case 10:
+      *r = 1.0;
+      break;
+    case 11:
+      *r = 1.0 / 2.0;
+      break;
+    case 12:
+      *r = 90.0;
+      break;
+    case 13:
+      *r = M_PI_2;
+      break;
+    case 14:
+      *r = MAXDOUBLE;
+      break;
+    case 15:
+      *r = -MAXDOUBLE;
+      break;
+    default:
+      abort ();
+    }
+}
+
+void static
+avx512f_test (void)
+{
+  union128d s1, res1, res2, res3;
+  union128i_q s2;
+  double res_ref[2];
+  int i, j, k;
+
+  float vals[2] = { -10, 10 };
+  int controls[10] = { 0x11111111,
+    0x77777777, 0x88888888, 0x99999999,
+    0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc,
+    0xdddddddd, 0xeeeeeeee, 0xffffffff
+  };
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < 2; i++)
+    {
+      s1.a[0] = vals[i];
+      s1.a[1] = 1.0;
+      s2.a[1] = 1.0;
+
+      res_ref[0] = 1.0;
+      res_ref[1] = 1.0;
+      res1.a[0] = res2.a[0] = res3.a[0] = DEFAULT_VALUE;
+      res1.a[1] = res2.a[1] = res3.a[1] = DEFAULT_VALUE;
+
+      for (j = 0; j < 10; j++)
+	{
+	  s2.a[0] = controls[j];
+	  compute_fixupimmpd (&res_ref[0], s1.a[0], s2.a[0]);
+
+	  res1.x = _mm_fixupimm_sd (res1.x, s1.x, s2.x, 0);
+	  res2.x = _mm_mask_fixupimm_sd (res2.x, mask, s1.x, s2.x, 0);
+	  res3.x = _mm_maskz_fixupimm_sd (mask, res3.x, s1.x, s2.x, 0);
+
+	  if (check_union128d (res1, res_ref))
+	    abort ();
+
+	  MASK_MERGE (d) (res_ref, mask, 1);
+	  if (check_union128d (res2, res_ref))
+	    abort ();
+
+	  MASK_ZERO (d) (res_ref, mask, 1);
+	  if (check_union128d (res3, res_ref))
+	    abort ();
+	}
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-1.c
new file mode 100644
index 000000000..435befbfa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vfixupimmss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vfixupimmss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfixupimmss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfixupimmss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vfixupimmss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfixupimmss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile __m128i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_fixupimm_ss (x, x, y, 3);
+  x = _mm_mask_fixupimm_ss (x, m, x, y, 3);
+  x = _mm_maskz_fixupimm_ss (m, x, x, y, 3);
+  x = _mm_fixupimm_round_ss (x, x, y, 3, _MM_FROUND_NO_EXC);
+  x = _mm_mask_fixupimm_round_ss (x, m, x, y, 3, _MM_FROUND_NO_EXC);
+  x = _mm_maskz_fixupimm_round_ss (m, x, x, y, 3, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-2.c
new file mode 100644
index 000000000..25e165ff5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfixupimmss-2.c
@@ -0,0 +1,120 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2 -std=gnu99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+#include <math.h>
+#include <values.h>
+#include "avx512f-mask-type.h"
+
+void
+compute_fixupimmps (float *r, float src, int tbl)
+{
+  switch (tbl & 0xf)
+    {
+    case 0:
+      *r = src;
+      break;
+    case 1:
+      *r = src;
+      break;
+    case 2:
+      *r = signbit (src) ? -NAN : NAN;
+      break;
+    case 3:
+      *r = -NAN;
+      break;
+    case 4:
+      *r = -INFINITY;
+      break;
+    case 5:
+      *r = INFINITY;
+      break;
+    case 6:
+      *r = signbit (src) ? -INFINITY : INFINITY;
+      break;
+    case 7:
+      *r = 1.0 / -INFINITY;
+      break;
+    case 8:
+      *r = 0.0;
+      break;
+    case 9:
+      *r = -1.0;
+      break;
+    case 10:
+      *r = 1.0;
+      break;
+    case 11:
+      *r = 1.0 / 2.0;
+      break;
+    case 12:
+      *r = 90.0;
+      break;
+    case 13:
+      *r = M_PI_2;
+      break;
+    case 14:
+      *r = MAXFLOAT;
+      break;
+    case 15:
+      *r = -MAXFLOAT;
+      break;
+    default:
+      abort ();
+    }
+}
+
+void static
+avx512f_test (void)
+{
+  union128 s1, res1, res2, res3;
+  union128i_d s2;
+  float res_ref[4];
+  int i, j, k;
+
+  float vals[2] = { -10, 10 };
+  int controls[10] = { 0x11111111,
+    0x77777777, 0x88888888, 0x99999999,
+    0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc,
+    0xdddddddd, 0xeeeeeeee, 0xffffffff
+  };
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < 2; i++)
+    {
+      s1.a[0] = vals[i];
+      res1.a[0] = res2.a[0] = res3.a[0] = DEFAULT_VALUE;
+      for (k = 1; k < 4; k++)
+	{
+	  s1.a[k] = k;
+	  s2.a[k] = k;
+	  res_ref[k] = k;
+	  res1.a[k] = res2.a[k] = res3.a[k] = DEFAULT_VALUE;
+	}
+
+      for (j = 0; j < 10; j++)
+	{
+	  s2.a[0] = controls[j];
+	  compute_fixupimmps (&res_ref[0], s1.a[0], s2.a[0]);
+
+	  res1.x = _mm_fixupimm_ss (res1.x, s1.x, s2.x, 0);
+	  res2.x = _mm_mask_fixupimm_ss (res2.x, mask, s1.x, s2.x, 0);
+	  res3.x = _mm_maskz_fixupimm_ss (mask, res3.x, s1.x, s2.x, 0);
+
+	  if (check_union128 (res1, res_ref))
+	    abort ();
+
+	  MASK_MERGE () (res_ref, mask, 1);
+	  if (check_union128 (res2, res_ref))
+	    abort ();
+
+	  MASK_ZERO () (res_ref, mask, 1);
+	  if (check_union128 (res3, res_ref))
+	    abort ();
+	}
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXpd-1.c
new file mode 100644
index 000000000..929afe3e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXpd-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfmadd231pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd231pd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x1, x2, x3;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fmadd_pd (x1, x2, x3);
+  x1 = _mm512_mask_fmadd_pd (x1, m, x2, x3);
+  x3 = _mm512_mask3_fmadd_pd (x1, x2, x3, m);
+  x1 = _mm512_maskz_fmadd_pd (m, x1, x2, x3);
+  x1 = _mm512_fmadd_round_pd (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fmadd_round_pd (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fmadd_round_pd (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fmadd_round_pd (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXpd-2.c
new file mode 100644
index 000000000..797363008
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXpd-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s1, double *s2, double *s3, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] * s2[i] + s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref1[SIZE];
+  double res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fmadd_pd) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fmadd_pd) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fmadd_pd) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fmadd_pd) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXps-1.c
new file mode 100644
index 000000000..95b886162
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXps-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfmadd231ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x1, x2, x3;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fmadd_ps (x1, x2, x3);
+  x1 = _mm512_mask_fmadd_ps (x1, m, x2, x3);
+  x3 = _mm512_mask3_fmadd_ps (x1, x2, x3, m);
+  x1 = _mm512_maskz_fmadd_ps (m, x1, x2, x3);
+  x1 = _mm512_fmadd_round_ps (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fmadd_round_ps (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fmadd_round_ps (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fmadd_round_ps (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXps-2.c
new file mode 100644
index 000000000..6883b77d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXps-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s1, float *s2, float *s3, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] * s2[i] + s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref1[SIZE];
+  float res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fmadd_ps) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fmadd_ps) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fmadd_ps) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fmadd_ps) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE () (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXsd-1.c
new file mode 100644
index 000000000..eb012d206
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmadd...sd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d a, b, c;
+
+void extern
+avx512f_test (void)
+{
+  a = _mm_fmadd_round_sd (a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXss-1.c
new file mode 100644
index 000000000..1c04965b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddXXXss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmadd...ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 a, b, c;
+
+void extern
+avx512f_test (void)
+{
+  a = _mm_fmadd_round_ss (a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXpd-1.c
new file mode 100644
index 000000000..6445cbaed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXpd-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmaddsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub231pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub231pd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x1, x2, x3;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fmaddsub_pd (x1, x2, x3);
+  x1 = _mm512_mask_fmaddsub_pd (x1, m, x2, x3);
+  x3 = _mm512_mask3_fmaddsub_pd (x1, x2, x3, m);
+  x1 = _mm512_maskz_fmaddsub_pd (m, x1, x2, x3);
+  x1 = _mm512_fmaddsub_round_pd (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fmaddsub_round_pd (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fmaddsub_round_pd (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fmaddsub_round_pd (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXpd-2.c
new file mode 100644
index 000000000..c54652033
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXpd-2.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s1, double *s2, double *s3, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      if (i % 2)
+	r[i] = s1[i] * s2[i] + s3[i];
+      else
+	r[i] = s1[i] * s2[i] - s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref1[SIZE];
+  double res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fmaddsub_pd) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fmaddsub_pd) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fmaddsub_pd) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fmaddsub_pd) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXps-1.c
new file mode 100644
index 000000000..9cff06c5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXps-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmaddsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub231ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x1, x2, x3;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fmaddsub_ps (x1, x2, x3);
+  x1 = _mm512_mask_fmaddsub_ps (x1, m, x2, x3);
+  x3 = _mm512_mask3_fmaddsub_ps (x1, x2, x3, m);
+  x1 = _mm512_maskz_fmaddsub_ps (m, x1, x2, x3);
+  x1 = _mm512_fmaddsub_round_ps (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fmaddsub_round_ps (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fmaddsub_round_ps (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fmaddsub_round_ps (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXps-2.c
new file mode 100644
index 000000000..2e27ffb46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmaddsubXXXps-2.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s1, float *s2, float *s3, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      if (i % 2)
+	r[i] = s1[i] * s2[i] + s3[i];
+      else
+	r[i] = s1[i] * s2[i] - s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref1[SIZE];
+  float res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fmaddsub_ps) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fmaddsub_ps) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fmaddsub_ps) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fmaddsub_ps) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE () (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXpd-1.c
new file mode 100644
index 000000000..ef4565b36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXpd-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfmsub231pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub...pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub231pd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x1, x2, x3;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fmsub_pd (x1, x2, x3);
+  x1 = _mm512_mask_fmsub_pd (x1, m, x2, x3);
+  x3 = _mm512_mask3_fmsub_pd (x1, x2, x3, m);
+  x1 = _mm512_maskz_fmsub_pd (m, x1, x2, x3);
+  x1 = _mm512_fmsub_round_pd (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fmsub_round_pd (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fmsub_round_pd (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fmsub_round_pd (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXpd-2.c
new file mode 100644
index 000000000..caebada6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXpd-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s1, double *s2, double *s3, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] * s2[i] - s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref1[SIZE];
+  double res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fmsub_pd) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fmsub_pd) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fmsub_pd) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fmsub_pd) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXps-1.c
new file mode 100644
index 000000000..1ff925666
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXps-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfmsub231ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x1, x2, x3;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fmsub_ps (x1, x2, x3);
+  x1 = _mm512_mask_fmsub_ps (x1, m, x2, x3);
+  x3 = _mm512_mask3_fmsub_ps (x1, x2, x3, m);
+  x1 = _mm512_maskz_fmsub_ps (m, x1, x2, x3);
+  x1 = _mm512_fmsub_round_ps (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fmsub_round_ps (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fmsub_round_ps (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fmsub_round_ps (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXps-2.c
new file mode 100644
index 000000000..da8908f33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXps-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s1, float *s2, float *s3, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] * s2[i] - s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref1[SIZE];
+  float res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fmsub_ps) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fmsub_ps) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fmsub_ps) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fmsub_ps) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE () (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXsd-1.c
new file mode 100644
index 000000000..b8aecf77e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmsub...sd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d a, b, c;
+
+void extern
+avx512f_test (void)
+{
+  a = _mm_fmsub_round_sd (a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXss-1.c
new file mode 100644
index 000000000..8912eb8a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubXXXss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmsub...ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 a, b, c;
+
+void extern
+avx512f_test (void)
+{
+  a = _mm_fmsub_round_ss (a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXpd-1.c
new file mode 100644
index 000000000..dd5db25f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXpd-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmsubadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd231pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd231pd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x1, x2, x3;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fmsubadd_pd (x1, x2, x3);
+  x1 = _mm512_mask_fmsubadd_pd (x1, m, x2, x3);
+  x3 = _mm512_mask3_fmsubadd_pd (x1, x2, x3, m);
+  x1 = _mm512_maskz_fmsubadd_pd (m, x1, x2, x3);
+  x1 = _mm512_fmsubadd_round_pd (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fmsubadd_round_pd (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fmsubadd_round_pd (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fmsubadd_round_pd (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXpd-2.c
new file mode 100644
index 000000000..537948b1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXpd-2.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s1, double *s2, double *s3, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      if (i % 2)
+	r[i] = s1[i] * s2[i] - s3[i];
+      else
+	r[i] = s1[i] * s2[i] + s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref1[SIZE];
+  double res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fmsubadd_pd) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fmsubadd_pd) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fmsubadd_pd) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fmsubadd_pd) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXps-1.c
new file mode 100644
index 000000000..7cf3b0cf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXps-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfmsubadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd231ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x1, x2, x3;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fmsubadd_ps (x1, x2, x3);
+  x1 = _mm512_mask_fmsubadd_ps (x1, m, x2, x3);
+  x3 = _mm512_mask3_fmsubadd_ps (x1, x2, x3, m);
+  x1 = _mm512_maskz_fmsubadd_ps (m, x1, x2, x3);
+  x1 = _mm512_fmsubadd_round_ps (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fmsubadd_round_ps (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fmsubadd_round_ps (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fmsubadd_round_ps (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXps-2.c
new file mode 100644
index 000000000..85be77ccb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfmsubaddXXXps-2.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s1, float *s2, float *s3, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      if (i % 2)
+	r[i] = s1[i] * s2[i] - s3[i];
+      else
+	r[i] = s1[i] * s2[i] + s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref1[SIZE];
+  float res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fmsubadd_ps) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fmsubadd_ps) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fmsubadd_ps) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fmsubadd_ps) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE () (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXpd-1.c
new file mode 100644
index 000000000..78c3c6b1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXpd-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfnmadd231pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd231pd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x1, x2, x3;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fnmadd_pd (x1, x2, x3);
+  x1 = _mm512_mask_fnmadd_pd (x1, m, x2, x3);
+  x3 = _mm512_mask3_fnmadd_pd (x1, x2, x3, m);
+  x1 = _mm512_maskz_fnmadd_pd (m, x1, x2, x3);
+  x1 = _mm512_fnmadd_round_pd (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fnmadd_round_pd (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fnmadd_round_pd (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fnmadd_round_pd (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXpd-2.c
new file mode 100644
index 000000000..71939a562
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXpd-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s1, double *s2, double *s3, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = -s1[i] * s2[i] + s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref1[SIZE];
+  double res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fnmadd_pd) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fnmadd_pd) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fnmadd_pd) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fnmadd_pd) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXps-1.c
new file mode 100644
index 000000000..c8211ab90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXps-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfnmadd231ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x1, x2, x3;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fnmadd_ps (x1, x2, x3);
+  x1 = _mm512_mask_fnmadd_ps (x1, m, x2, x3);
+  x3 = _mm512_mask3_fnmadd_ps (x1, x2, x3, m);
+  x1 = _mm512_maskz_fnmadd_ps (m, x1, x2, x3);
+  x1 = _mm512_fnmadd_round_ps (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fnmadd_round_ps (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fnmadd_round_ps (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fnmadd_round_ps (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXps-2.c
new file mode 100644
index 000000000..b591d23aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXps-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s1, float *s2, float *s3, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = -s1[i] * s2[i] + s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref1[SIZE];
+  float res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fnmadd_ps) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fnmadd_ps) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fnmadd_ps) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fnmadd_ps) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE () (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXsd-1.c
new file mode 100644
index 000000000..2e2ac1639
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfnmadd...sd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d a, b, c;
+
+void extern
+avx512f_test (void)
+{
+  a = _mm_fnmadd_round_sd (a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXss-1.c
new file mode 100644
index 000000000..b28ed0a56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmaddXXXss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfnmadd...ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 a, b, c;
+
+void extern
+avx512f_test (void)
+{
+  a = _mm_fnmadd_round_ss (a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXpd-1.c
new file mode 100644
index 000000000..664902aac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXpd-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfnmsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfnmsub231pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...pd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...pd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub231pd\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...pd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x1, x2, x3;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fnmsub_pd (x1, x2, x3);
+  x1 = _mm512_mask_fnmsub_pd (x1, m, x2, x3);
+  x3 = _mm512_mask3_fnmsub_pd (x1, x2, x3, m);
+  x1 = _mm512_maskz_fnmsub_pd (m, x1, x2, x3);
+  x1 = _mm512_fnmsub_round_pd (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fnmsub_round_pd (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fnmsub_round_pd (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fnmsub_round_pd (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXpd-2.c
new file mode 100644
index 000000000..177ea7306
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXpd-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s1, double *s2, double *s3, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = -s1[i] * s2[i] - s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref1[SIZE];
+  double res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fnmsub_pd) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fnmsub_pd) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fnmsub_pd) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fnmsub_pd) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-1.c
new file mode 100644
index 000000000..c0751e9a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-1.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfnmsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vfnmsub231ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub231ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x1, x2, x3;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_fnmsub_ps (x1, x2, x3);
+  x1 = _mm512_mask_fnmsub_ps (x1, m, x2, x3);
+  x3 = _mm512_mask3_fnmsub_ps (x1, x2, x3, m);
+  x1 = _mm512_maskz_fnmsub_ps (m, x1, x2, x3);
+  x1 = _mm512_fnmsub_round_ps (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x1 = _mm512_mask_fnmsub_round_ps (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x3 = _mm512_mask3_fnmsub_round_ps (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x1 = _mm512_maskz_fnmsub_round_ps (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-2.c
new file mode 100644
index 000000000..379708b46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXps-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s1, float *s2, float *s3, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = -s1[i] * s2[i] - s3[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s1, s2, s3, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref1[SIZE];
+  float res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 56.78 * (i + 1) * sign;
+      s3.a[i] = 90.12 * (i + 2) * sign;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_fnmsub_ps) (s1.x, s2.x, s3.x);
+#endif
+  res2.x = INTRINSIC (_mask_fnmsub_ps) (s1.x, mask, s2.x, s3.x);
+  res3.x = INTRINSIC (_mask3_fnmsub_ps) (s2.x, s3.x, s1.x, mask);
+  res4.x = INTRINSIC (_maskz_fnmsub_ps) (mask, s1.x, s2.x, s3.x);
+
+  CALC (s1.a, s2.a, s3.a, res_ref1);
+  CALC (s2.a, s3.a, s1.a, res_ref2);
+
+#if AVX512F_LEN == 512
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res1, res_ref1, 0.0001))
+    abort ();
+#endif
+
+  MASK_MERGE () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res2, res_ref1, 0.0001))
+    abort ();
+
+  MASK_MERGE () (res_ref2, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res3, res_ref2, 0.0001))
+    abort ();
+
+  MASK_ZERO () (res_ref1, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, ) (res4, res_ref1, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXsd-1.c
new file mode 100644
index 000000000..2c7b0453a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfnmsub...sd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d a, b, c;
+
+void extern
+avx512f_test (void)
+{
+  a = _mm_fnmsub_round_sd (a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXss-1.c
new file mode 100644
index 000000000..ad25c62f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vfnmsubXXXss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vfnmsub...ss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 a, b, c;
+
+void extern
+avx512f_test (void)
+{
+  a = _mm_fnmsub_round_ss (a, b, c, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexppd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexppd-1.c
new file mode 100644
index 000000000..3d899ea2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexppd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vgetexppd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6} } */
+/* { dg-final { scan-assembler-times "vgetexppd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2} } */
+/* { dg-final { scan-assembler-times "vgetexppd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2} } */
+/* { dg-final { scan-assembler-times "vgetexppd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 3} } */
+/* { dg-final { scan-assembler-times "vgetexppd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1} } */
+/* { dg-final { scan-assembler-times "vgetexppd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1} } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_getexp_pd (x);
+  x = _mm512_mask_getexp_pd (x, m, x);
+  x = _mm512_maskz_getexp_pd (m, x);
+  x = _mm512_getexp_round_pd (x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_getexp_round_pd (x, m, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_getexp_round_pd (m, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexppd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexppd-2.c
new file mode 100644
index 000000000..ec9321aa8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexppd-2.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "math.h"
+
+static void
+CALC (double *s, double *r)
+{
+  int i = 0;
+  for (i = 0; i < SIZE; i++)
+    r[i] = floor (log (s[i]) / log (2));
+}
+
+void static
+TEST (void)
+{
+  int j;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, s;
+  double res_ref[SIZE];
+  double res_ref_mask[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (j = 0; j < SIZE; j++)
+    {
+      s.a[j] = j * (j + 12.0231);
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_getexp_pd) (s.x);
+  res2.x = INTRINSIC (_mask_getexp_pd) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_getexp_pd) (mask, s.x);
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE(d) (res_ref, mask, SIZE);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO(d) (res_ref, mask, SIZE);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpps-1.c
new file mode 100644
index 000000000..fb5674d70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vgetexpps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6} } */
+/* { dg-final { scan-assembler-times "vgetexpps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2} } */
+/* { dg-final { scan-assembler-times "vgetexpps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2} } */
+/* { dg-final { scan-assembler-times "vgetexpps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 3} } */
+/* { dg-final { scan-assembler-times "vgetexpps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1} } */
+/* { dg-final { scan-assembler-times "vgetexpps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1} } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_getexp_ps (x);
+  x = _mm512_mask_getexp_ps (x, m, x);
+  x = _mm512_maskz_getexp_ps (m, x);
+  x = _mm512_getexp_round_ps (x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_getexp_round_ps (x, m, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_getexp_round_ps (m, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpps-2.c
new file mode 100644
index 000000000..56f4eaa15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpps-2.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "math.h"
+
+static void
+CALC (float *s, float *r)
+{
+  int i = 0;
+  for (i = 0; i < SIZE; i++)
+    r[i] = floor (log (s[i]) / log (2));
+}
+
+void static
+TEST (void)
+{
+  int j;
+  UNION_TYPE (AVX512F_LEN, ) res1,res2,res3,s;
+  float res_ref[SIZE];
+  float res_ref_mask[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (j = 0; j < SIZE; j++)
+    {
+      s.a[j] = j * (j + 12.0231);
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_getexp_ps) (s.x);
+  res2.x = INTRINSIC (_mask_getexp_ps) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_getexp_ps) (mask, s.x);
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE() (res_ref,mask,SIZE );
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO() (res_ref,mask,SIZE );
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-1.c
new file mode 100644
index 000000000..952ed5460
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vgetexpsd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\, %xmm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vgetexpsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\, %xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_getexp_sd (x, x);
+  x = _mm_getexp_round_sd (x, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-2.c
new file mode 100644
index 000000000..c1e5e5f22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpsd-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#define SIZE (128 / 64)
+
+#include <math.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+static void
+compute_vgetexpsd (double *s, double *r)
+{
+  r[0] = floor (log (s[0]) / log (2));
+}
+
+void static
+avx512f_test (void)
+{
+  int i;
+  union128d res1, s1;
+  double res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 5.0 - i;
+      res_ref[i] = s1.a[i];
+    }
+
+  res1.x = _mm_getexp_sd (s1.x, s1.x);
+
+  compute_vgetexpsd (s1.a, res_ref);
+
+  if (check_fp_union128d (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-1.c
new file mode 100644
index 000000000..d946a4788
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vgetexpss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\, %xmm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vgetexpss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\, %xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_getexp_ss (x, x);
+  x = _mm_getexp_round_ss (x, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-2.c
new file mode 100644
index 000000000..39d77c7a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetexpss-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#define SIZE (128 / 32)
+
+#include <math.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+static void
+compute_vgetexpss (float *s, float *r)
+{
+  r[0] = floor (log (s[0]) / log (2));
+}
+
+void static
+avx512f_test (void)
+{
+  int i;
+  union128 res1, s1;
+  float res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 5.0 - i;
+      res_ref[i] = s1.a[i];
+    }
+
+  res1.x = _mm_getexp_ss (s1.x, s1.x);
+
+  compute_vgetexpss (s1.a, res_ref);
+
+  if (check_fp_union128 (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantpd-1.c
new file mode 100644
index 000000000..b19846d17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantpd-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vgetmantpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vgetmantpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vgetmantpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vgetmantpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[\\n\]" 1 } } */
+/* { dg-final { scan-assembler-times "vgetmantpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vgetmantpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x, y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_getmant_pd (y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src);
+  x =
+    _mm512_mask_getmant_pd (x, m, y, _MM_MANT_NORM_p75_1p5,
+			    _MM_MANT_SIGN_src);
+  x =
+    _mm512_maskz_getmant_pd (m, y, _MM_MANT_NORM_p75_1p5,
+			     _MM_MANT_SIGN_src);
+  x = _mm512_getmant_round_pd (y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src,
+			       _MM_FROUND_NO_EXC);
+  x =
+    _mm512_mask_getmant_round_pd (x, m, y, _MM_MANT_NORM_p75_1p5,
+			    _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC);
+  x =
+    _mm512_maskz_getmant_round_pd (m, y, _MM_MANT_NORM_p75_1p5,
+			     _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantpd-2.c
new file mode 100644
index 000000000..0209021b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantpd-2.c
@@ -0,0 +1,124 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -std=c99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include <math.h>
+
+#ifndef GET_NORM_MANT
+#define GET_NORM_MANT
+
+union fp_int_t
+{
+  long long int int_val;
+  double fp_val;
+};
+
+double
+get_norm_mant (double source, int signctrl, int interv)
+{
+  long long src, sign, exp, fraction;
+  union fp_int_t bin_conv;
+
+  bin_conv.fp_val = source;
+  src = bin_conv.int_val;
+  sign = (signctrl & 0x1) ? 0 : (src >> 63);
+  exp = (src & 0x7ff0000000000000) >> 52;
+  fraction = (src & 0xfffffffffffff);
+
+  if (isnan (source))
+    return signbit (source) ? -NAN : NAN;
+  if (source == 0.0 || source == -0.0 || isinf (source))
+    return sign ? -1.0 : 1.0;
+  if (signbit (source) && (signctrl & 0x2))
+    return -NAN;
+  if (!isnormal (source))
+    {
+      src = (src & 0xfff7ffffffffffff);
+      exp = 0x3ff;
+      while (!(src & 0x8000000000000))
+	{
+	  src += fraction & 0x8000000000000;
+	  fraction = fraction << 1;
+	  exp--;
+	}
+    }
+
+  switch (interv)
+    {
+    case 0:
+      exp = 0x3ff;
+      break;
+    case 1:
+      exp = ((exp - 0x3ff) & 0x1) ? 0x3fe : 0x3ff;
+      break;
+    case 2:
+      exp = 0x3fe;
+      break;
+    case 3:
+      exp = (fraction & 0x8000000000000) ? 0x3fe : 0x3ff;
+      break;
+    default:
+      abort ();
+    }
+
+  bin_conv.int_val = (sign << 63) | (exp << 52) | fraction;
+  return bin_conv.fp_val;
+}
+#endif
+
+void static
+CALC (double *r, double *s, int interv, int signctrl)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = get_norm_mant (s[i], signctrl, interv);
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, src;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int interv = _MM_MANT_NORM_p5_1;
+  int signctrl = _MM_MANT_SIGN_src;
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 34.67 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_getmant_pd) (src.x, interv, signctrl);
+  res2.x =
+    INTRINSIC (_mask_getmant_pd) (res2.x, mask, src.x, interv,
+				  signctrl);
+  res3.x =
+    INTRINSIC (_maskz_getmant_pd) (mask, src.x, interv, signctrl);
+
+  CALC (res_ref, src.a, interv, signctrl);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantps-1.c
new file mode 100644
index 000000000..a3ce09e97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantps-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vgetmantps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vgetmantps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vgetmantps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vgetmantps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[\\n\]" 1 } } */
+/* { dg-final { scan-assembler-times "vgetmantps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vgetmantps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x, y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_getmant_ps (y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src);
+  x =
+    _mm512_mask_getmant_ps (x, m, y, _MM_MANT_NORM_p75_1p5,
+			    _MM_MANT_SIGN_src);
+  x =
+    _mm512_maskz_getmant_ps (m, y, _MM_MANT_NORM_p75_1p5,
+			     _MM_MANT_SIGN_src);
+  x = _mm512_getmant_round_ps (y, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src,
+			 _MM_FROUND_NO_EXC);
+  x =
+    _mm512_mask_getmant_round_ps (x, m, y, _MM_MANT_NORM_p75_1p5,
+			    _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC);
+  x =
+    _mm512_maskz_getmant_round_ps (m, y, _MM_MANT_NORM_p75_1p5,
+			     _MM_MANT_SIGN_src, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantps-2.c
new file mode 100644
index 000000000..25e41d182
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantps-2.c
@@ -0,0 +1,125 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -std=c99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include <math.h>
+
+#ifndef GET_NORM_MANT
+#define GET_NORM_MANT
+
+union fp_int_t
+{
+  int int_val;
+  float fp_val;
+};
+
+float
+get_norm_mant (float source, int signctrl, int interv)
+{
+  int src, sign, exp, fraction;
+  union fp_int_t bin_conv;
+
+  bin_conv.fp_val = source;
+  src = bin_conv.int_val;
+  sign = (signctrl & 0x1) ? 0 : (src >> 31);
+  exp = (src & 0x7f800000) >> 23;
+  fraction = (src & 0x7fffff);
+
+  if (isnan (source))
+    return signbit (source) ? -NAN : NAN;
+  if (source == 0.0 || source == -0.0 || isinf (source))
+    return sign ? -1.0 : 1.0;
+  if (signbit (source) && (signctrl & 0x2))
+    return -NAN;
+  if (!isnormal (source))
+    {
+      src = (src & 0xffbfffff);
+      exp = 0x7f;
+      while (!(src & 0x400000))
+	{
+	  src += fraction & 0x400000;
+	  fraction = fraction << 1;
+	  exp--;
+	}
+    }
+
+  switch (interv)
+    {
+    case 0:
+      exp = 0x7f;
+      break;
+    case 1:
+      exp = ((exp - 0x7f) & 0x1) ? 0x7e : 0x7f;
+      break;
+    case 2:
+      exp = 0x7e;
+      break;
+    case 3:
+      exp = (fraction & 0x400000) ? 0x7e : 0x7f;
+      break;
+    default:
+      abort ();
+    }
+
+  bin_conv.int_val = (sign << 31) | (exp << 23) | fraction;
+  
+  return bin_conv.fp_val;
+}
+#endif
+
+void static
+CALC (float *r, float *s, int interv, int signctrl)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = get_norm_mant (s[i], signctrl, interv);
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3, src;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int interv = _MM_MANT_NORM_p5_1;
+  int signctrl = _MM_MANT_SIGN_src;
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 34.67 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_getmant_ps) (src.x, interv, signctrl);
+  res2.x =
+    INTRINSIC (_mask_getmant_ps) (res2.x, mask, src.x, interv,
+				  signctrl);
+  res3.x =
+    INTRINSIC (_maskz_getmant_ps) (mask, src.x, interv, signctrl);
+
+  CALC (res_ref, src.a, interv, signctrl);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-1.c
new file mode 100644
index 000000000..4b252a416
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vgetmantsd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vgetmantsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[\\n\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x, y, z;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_getmant_sd (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src);
+  x = _mm_getmant_round_sd (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src,
+			    _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-2.c
new file mode 100644
index 000000000..563d3cc22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantsd-2.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2 -std=c99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+union fp_int_t
+{
+  long long int int_val;
+  double fp_val;
+};
+
+double
+get_norm_mant (double source, int signctrl, int interv)
+{
+  long long src, sign, exp, fraction;
+
+  union fp_int_t bin_conv;
+
+  bin_conv.fp_val = source;
+  src = bin_conv.int_val;
+  sign = (signctrl & 0x1) ? 0 : (src >> 63);
+  exp = (src & 0x7ff0000000000000) >> 52;
+  fraction = (src & 0xfffffffffffff);
+
+  if (isnan (source))
+    return signbit (source) ? -NAN : NAN;
+  if (source == 0.0 || source == -0.0 || isinf (source))
+    return sign ? -1.0 : 1.0;
+  if (signbit (source) && (signctrl & 0x2))
+    return -NAN;
+  if (!isnormal (source))
+    {
+      src = (src & 0xfff7ffffffffffff);
+      exp = 0x3ff;
+      while (!(src & 0x8000000000000))
+	{
+	  src += fraction & 0x8000000000000;
+	  fraction = fraction << 1;
+	  exp--;
+	}
+    }
+
+  switch (interv)
+    {
+    case 0:
+      exp = 0x3ff;
+      break;
+    case 1:
+      exp = ((exp - 0x3ff) & 0x1) ? 0x3fe : 0x3ff;
+      break;
+    case 2:
+      exp = 0x3fe;
+      break;
+    case 3:
+      exp = (fraction & 0x8000000000000) ? 0x3fe : 0x3ff;
+      break;
+    default:
+      abort ();
+    }
+
+  bin_conv.int_val = (sign << 63) | (exp << 52) | fraction;
+  return bin_conv.fp_val;
+}
+
+static void
+compute_vgetmantsd (double *r, double *s1, double *s2, int interv,
+		    int signctrl)
+{
+  r[0] = get_norm_mant (s2[0], signctrl, interv);
+  r[1] = s1[1];
+}
+
+static void
+avx512f_test (void)
+{
+  int i, sign;
+  union128d res1, src1, src2;
+  double res_ref[2];
+  int interv = _MM_MANT_NORM_p5_1;
+  int signctrl = _MM_MANT_SIGN_src;
+
+  src1.x = _mm_set_pd (-3.0, 111.111);
+  src2.x = _mm_set_pd (222.222, -2.0);
+
+  res1.x = _mm_getmant_sd (src1.x, src2.x, interv, signctrl);
+
+  compute_vgetmantsd (res_ref, src1.a, src2.a, interv, signctrl);
+
+  if (check_union128d (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-1.c
new file mode 100644
index 000000000..30c837b6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vgetmantss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[\\n\]" 2 } } */
+/* { dg-final { scan-assembler-times "vgetmantss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[\\n\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x, y, z;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_getmant_ss (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src);
+  x = _mm_getmant_round_ss (y, z, _MM_MANT_NORM_p75_1p5, _MM_MANT_SIGN_src,
+		      _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-2.c
new file mode 100644
index 000000000..3ffab4ee1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vgetmantss-2.c
@@ -0,0 +1,100 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2 -std=c99" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target c99_runtime } */
+
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+#include <math.h>
+
+union fp_int_t
+{
+  int int_val;
+  float fp_val;
+};
+
+float
+get_norm_mant (float source, int signctrl, int interv)
+{
+  int src, sign, exp, fraction;
+  union fp_int_t bin_conv;
+
+  bin_conv.fp_val = source;
+  src = bin_conv.int_val;
+  sign = (signctrl & 0x1) ? 0 : (src >> 31);
+  exp = (src & 0x7f800000) >> 23;
+  fraction = (src & 0x7fffff);
+
+  if (isnan (source))
+    return signbit (source) ? -NAN : NAN;
+  if (source == 0.0 || source == -0.0 || isinf (source))
+    return sign ? -1.0 : 1.0;
+  if (signbit (source) && (signctrl & 0x2))
+    return -NAN;
+  if (!isnormal (source))
+    {
+      src = (src & 0xffbfffff);
+      exp = 0x7f;
+      while (!(src & 0x400000))
+	{
+	  src += fraction & 0x400000;
+	  fraction = fraction << 1;
+	  exp--;
+	}
+    }
+
+  switch (interv)
+    {
+    case 0:
+      exp = 0x7f;
+      break;
+    case 1:
+      exp = ((exp - 0x7f) & 0x1) ? 0x7e : 0x7f;
+      break;
+    case 2:
+      exp = 0x7e;
+      break;
+    case 3:
+      exp = (fraction & 0x400000) ? 0x7e : 0x7f;
+      break;
+    default:
+      abort ();
+    }
+
+  bin_conv.int_val = (sign << 31) | (exp << 23) | fraction;
+
+  return bin_conv.fp_val;
+
+}
+
+static void
+compute_vgetmantss (float *r, float *s1, float *s2, int interv,
+		    int signctrl)
+{
+  int i;
+  r[0] = get_norm_mant (s2[0], signctrl, interv);
+  for (i = 1; i < 4; i++)
+    {
+      r[i] = s1[i];
+    }
+}
+
+static void
+avx512f_test (void)
+{
+  int i, sign;
+  union128 res1, src1, src2;
+  float res_ref[4];
+  int interv = _MM_MANT_NORM_p5_1;
+  int signctrl = _MM_MANT_SIGN_src;
+
+  src1.x = _mm_set_ps (-24.043, 68.346, -43.35, 546.46);
+  src2.x = _mm_set_ps (222.222, 333.333, 444.444, -2.0);
+
+  res1.x = _mm_getmant_ss (src1.x, src2.x, interv, signctrl);
+
+  compute_vgetmantss (res_ref, src1.a, src2.a, interv, signctrl);
+
+  if (check_union128 (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf32x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf32x4-1.c
new file mode 100644
index 000000000..b2caa5324
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf32x4-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\]*zmm" 3 } } */
+/* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\]*\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\]*\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+__m128 y;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_insertf32x4 (x, y, 1);
+  x = _mm512_maskz_insertf32x4 (6, x, y, 1);
+  x = _mm512_mask_insertf32x4 (x, 2, x, y, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf32x4-2.c
new file mode 100644
index 000000000..9231163c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf32x4-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "string.h"
+
+void static
+CALC (UNION_TYPE (AVX512F_LEN,) s1, union128 s2, float *res_ref, int imm)
+{
+  memcpy (res_ref, s1.a, SIZE * sizeof (float));
+  memcpy (res_ref + imm * 4, s2.a, 16);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) s1, res1, res2, res3;
+  union128 s2;
+  float res_ref[SIZE];
+  int j;
+
+  MASK_TYPE mask = 6 ^ (0xffd >> SIZE);
+
+  for (j = 0; j < SIZE; j++)
+    {
+      s1.a[j] = j * j / 10.2;
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+    }
+
+  for (j = 0; j < 4; j++)
+    s2.a[j] = j * j * j / 2.03;
+
+  res1.x = INTRINSIC (_insertf32x4) (s1.x, s2.x, 1);
+  res2.x = INTRINSIC (_mask_insertf32x4) (res2.x, mask, s1.x, s2.x, 1);
+  res3.x = INTRINSIC (_maskz_insertf32x4) (mask, s1.x, s2.x, 1);
+
+  CALC (s1, s2, res_ref, 1);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf64x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf64x4-1.c
new file mode 100644
index 000000000..a4c74fd48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf64x4-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vinsertf64x4\[ \\t\]+\[^\n\]+" 3 } } */
+/* { dg-final { scan-assembler-times "vinsertf64x4\[ \\t\]+\[^\n\]+\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vinsertf64x4\[ \\t\]+\[^\n\]+\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m256d y;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_insertf64x4 (x, y, 1);
+  x = _mm512_mask_insertf64x4 (x, 2, x, y, 1);
+  x = _mm512_maskz_insertf64x4 (2, x, y, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf64x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf64x4-2.c
new file mode 100644
index 000000000..17871b854
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinsertf64x4-2.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-options "-O2 -mavx512f" } */
+
+#define SIZE (512 / 64)
+#include "avx512f-mask-type.h"
+#include <string.h>
+#include "avx512f-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+
+void static
+avx512f_test (void)
+{
+  union512d s1, res, res2, res3;
+  union256d s2;
+  double res_ref[8];
+  MASK_TYPE mask = MASK_VALUE;
+  int j;
+
+  for (j = 0; j < 8; j++)
+    {
+      s1.a[j] = j * j + 1.6;
+      res2.a[j] = DEFAULT_VALUE;
+    }
+
+  for (j = 0; j < 4; j++)
+    s2.a[j] = j * j * j / 2.7;
+
+  res.x = _mm512_insertf64x4 (s1.x, s2.x, 0);
+  res2.x = _mm512_mask_insertf64x4 (res2.x, mask, s1.x, s2.x, 0);
+  res3.x = _mm512_maskz_insertf64x4 (mask, s1.x, s2.x, 0);
+
+  memcpy (res_ref, s1.a, 64);
+  memcpy (res_ref, s2.a, 32);
+
+  if (check_union512d (res, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (check_union512d (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (check_union512d (res3, res_ref))
+    abort ();
+
+  res.x = _mm512_insertf64x4 (s1.x, s2.x, 1);
+  res2.x = _mm512_mask_insertf64x4 (res2.x, mask, s1.x, s2.x, 1);
+  res3.x = _mm512_maskz_insertf64x4 (mask, s1.x, s2.x, 1);
+
+  memcpy (res_ref, s1.a, 64);
+  memcpy (res_ref + 4, s2.a, 32);
+
+  if (check_union512d (res, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (check_union512d (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (check_union512d (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti32x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti32x4-1.c
new file mode 100644
index 000000000..44c083137
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti32x4-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\]*xmm\[^\n\]*zmm\[^\n\]*zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\]*\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vinserti32x4\[^\n\]*\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x,a;
+volatile __m128i y;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_maskz_inserti32x4 (6, x, y, 1);
+  x = _mm512_mask_inserti32x4 (a, 6, x, y, 1);
+  x = _mm512_inserti32x4 (x, y, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti32x4-2.c
new file mode 100644
index 000000000..c0cce565b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti32x4-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "string.h"
+
+void static
+CALC (UNION_TYPE (AVX512F_LEN, i_d) s1, union128i_d s2, int *res_ref, int imm)
+{
+  memcpy (res_ref, s1.a, SIZE * sizeof (int));
+  memcpy (res_ref + imm * 4, s2.a, 16);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, res1, res2, res3;
+  union128i_d s2;
+  int res_ref[SIZE];
+  int j;
+
+  MASK_TYPE mask = 6 ^ (0xffd >> SIZE);
+
+  for (j = 0; j < SIZE; j++)
+    {
+      s1.a[j] = j * j;
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+    }
+
+  for (j = 0; j < 4; j++)
+    s2.a[j] = j * j * j;
+
+  res1.x = INTRINSIC (_inserti32x4) (s1.x, s2.x, 1);
+  res2.x = INTRINSIC (_mask_inserti32x4) (res2.x, mask, s1.x, s2.x, 1);
+  res3.x = INTRINSIC (_maskz_inserti32x4) (mask, s1.x, s2.x, 1);
+
+  CALC (s1, s2, res_ref, 1);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti64x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti64x4-1.c
new file mode 100644
index 000000000..f5b7eff09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti64x4-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vinserti64x4\[ \\t\]+\[^\n\]+\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vinserti64x4\[ \\t\]+\[^\n\]+\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vinserti64x4\[ \\t\]+\[^\n\]+\[^\n\]" 3 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m256i y;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_inserti64x4 (x, y, 1);
+  x = _mm512_mask_inserti64x4 (x, 2, x, y, 1);
+  x = _mm512_maskz_inserti64x4 (2, x, y, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti64x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti64x4-2.c
new file mode 100644
index 000000000..58993ad5e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vinserti64x4-2.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-options "-O2 -mavx512f" } */
+
+#define SIZE (512 / 64)
+#include "avx512f-mask-type.h"
+#include <string.h>
+#include "avx512f-check.h"
+#include "avx512f-mask-type.h"
+#include "avx512f-helper.h"
+
+void static
+avx512f_test (void)
+{
+  union512i_q s1, res, res2, res3;
+  union256i_q s2;
+  long long int res_ref[8];
+  MASK_TYPE mask = MASK_VALUE;
+  int j;
+
+  for (j = 0; j < 8; j++)
+    {
+      s1.a[j] = j * j;
+      res2.a[j] = DEFAULT_VALUE;
+    }
+
+  for (j = 0; j < 4; j++)
+    s2.a[j] = j * j * j;
+
+  res.x = _mm512_inserti64x4 (s1.x, s2.x, 0);
+  res2.x = _mm512_mask_inserti64x4 (res2.x, mask, s1.x, s2.x, 0);
+  res3.x = _mm512_maskz_inserti64x4 (mask, s1.x, s2.x, 0);
+
+  memcpy (res_ref, s1.a, 64);
+  memcpy (res_ref, s2.a, 32);
+
+  if (check_union512i_q (res, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (check_union512i_q (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (check_union512i_q (res3, res_ref))
+    abort ();
+
+  res.x = _mm512_inserti64x4 (s1.x, s2.x, 1);
+  res2.x = _mm512_mask_inserti64x4 (res2.x, mask, s1.x, s2.x, 1);
+  res3.x = _mm512_maskz_inserti64x4 (mask, s1.x, s2.x, 1);
+
+  memcpy (res_ref, s1.a, 64);
+  memcpy (res_ref + 4, s2.a, 32);
+
+  if (check_union512i_q (res, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (check_union512i_q (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (check_union512i_q (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxpd-1.c
new file mode 100644
index 000000000..085a7e5e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxpd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vmaxpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vmaxpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vmaxpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vmaxpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vmaxpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_max_pd (x, x);
+  x = _mm512_mask_max_pd (x, m, x, x);
+  x = _mm512_maskz_max_pd (m, x, x);
+  x = _mm512_max_round_pd (x, x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_max_round_pd (x, m, x, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_max_round_pd (m, x, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxpd-2.c
new file mode 100644
index 000000000..70f60a968
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s1, double *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] > s2[i] ? s1[i] : s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_max_pd) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_max_pd) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_max_pd) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxps-1.c
new file mode 100644
index 000000000..564eeb516
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vmaxps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vmaxps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vmaxps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vmaxps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vmaxps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmaxps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_max_ps (x, x);
+  x = _mm512_mask_max_ps (x, m, x, x);
+  x = _mm512_maskz_max_ps (m, x, x);
+  x = _mm512_max_round_ps (x, x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_max_round_ps (x, m, x, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_max_round_ps (m, x, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxps-2.c
new file mode 100644
index 000000000..fc92eaa3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxps-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s1, float *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] > s2[i] ? s1[i] : s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, ) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_max_ps) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_max_ps) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_max_ps) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxsd-1.c
new file mode 100644
index 000000000..8c2470442
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmaxsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_max_round_sd (x1, x2, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxss-1.c
new file mode 100644
index 000000000..027445db3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmaxss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmaxss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_max_round_ss (x1, x2, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminpd-1.c
new file mode 100644
index 000000000..a4c993e64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminpd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vminpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vminpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vminpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vminpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vminpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vminpd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_min_pd (x, x);
+  x = _mm512_mask_min_pd (x, m, x, x);
+  x = _mm512_maskz_min_pd (m, x, x);
+  x = _mm512_min_round_pd (x, x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_min_round_pd (x, m, x, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_min_round_pd (m, x, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminpd-2.c
new file mode 100644
index 000000000..cfb355539
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s1, double *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] < s2[i] ? s1[i] : s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_min_pd) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_min_pd) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_min_pd) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminps-1.c
new file mode 100644
index 000000000..3cd5904bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vminps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vminps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vminps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vminps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vminps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vminps\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_min_ps (x, x);
+  x = _mm512_mask_min_ps (x, m, x, x);
+  x = _mm512_maskz_min_ps (m, x, x);
+  x = _mm512_min_round_ps (x, x, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_min_round_ps (x, m, x, x, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_min_round_ps (m, x, x, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminps-2.c
new file mode 100644
index 000000000..f619b12fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminps-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s1, float *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] < s2[i] ? s1[i] : s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, ) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_min_ps) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_min_ps) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_min_ps) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminsd-1.c
new file mode 100644
index 000000000..8f8488f8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vminsd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_min_round_sd (x1, x2, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminss-1.c
new file mode 100644
index 000000000..0774b7577
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vminss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vminss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_min_round_ss (x1, x2, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovapd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovapd-1.c
new file mode 100644
index 000000000..9cae38ff3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovapd-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovapd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovapd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovapd\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovapd\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovapd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+double *p;
+volatile __m512d x1, x2;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_mask_mov_pd (x1, m, x2);
+  x1 = _mm512_maskz_mov_pd (m, x2);
+
+  x1 = _mm512_load_pd (p);
+  x1 = _mm512_mask_load_pd (x1, m, p);
+  x1 = _mm512_maskz_load_pd (m, p);
+
+  _mm512_store_pd (p, x1);
+  _mm512_mask_store_pd (p, m, x1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovapd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovapd-2.c
new file mode 100644
index 000000000..5e720ae82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovapd-2.c
@@ -0,0 +1,71 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE ((AVX512F_LEN) / 64)
+#include "avx512f-mask-type.h"
+#define ALIGN ((AVX512F_LEN) / 8)
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s2, s3, res1, res3, res4, res5, res6;
+  MASK_TYPE mask = MASK_VALUE;
+  double s1[SIZE] __attribute__ ((aligned (ALIGN)));
+  double res2[SIZE] __attribute__ ((aligned (ALIGN)));
+  double res7[SIZE] __attribute__ ((aligned (ALIGN)));
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1[i] = 12.34 * (i + 2000) * sign;
+      s2.a[i] = 56.78 * (i - 30) * sign;
+      s3.a[i] = 90.12 * (i + 40) * sign;
+      res3.a[i] = DEFAULT_VALUE;
+      res5.a[i] = DEFAULT_VALUE;
+      res7[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_load_pd) (s1);
+  INTRINSIC (_store_pd) (res2, s2.x);
+#endif
+  res3.x = INTRINSIC (_mask_mov_pd) (res3.x, mask, s3.x);
+  res4.x = INTRINSIC (_maskz_mov_pd) (mask, s3.x);
+  res5.x = INTRINSIC (_mask_load_pd) (res5.x, mask, s1);
+  res6.x = INTRINSIC (_maskz_load_pd) (mask, s1);
+  INTRINSIC (_mask_store_pd) (res7, mask, s2.x);
+
+#if AVX512F_LEN == 512
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, s1))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, d) (s2, res2))
+    abort ();
+#endif
+
+  MASK_MERGE (d) (s3.a, mask, SIZE);
+  if (checkVd (res3.a, s3.a, SIZE))
+    abort ();
+
+  MASK_ZERO (d) (s3.a, mask, SIZE);
+  if (checkVd (res4.a, s3.a, SIZE))
+    abort ();
+
+  MASK_MERGE (d) (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res5, s1))
+    abort ();
+
+  MASK_ZERO (d) (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res6, s1))
+    abort ();
+
+  MASK_MERGE (d) (s2.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (s2, res7))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovaps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovaps-1.c
new file mode 100644
index 000000000..217e29ccb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovaps-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovaps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovaps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovaps\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovaps\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovaps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+float *p;
+volatile __m512 x1, x2;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_mask_mov_ps (x1, m, x2);
+  x1 = _mm512_maskz_mov_ps (m, x2);
+
+  x1 = _mm512_load_ps (p);
+  x1 = _mm512_mask_load_ps (x1, m, p);
+  x1 = _mm512_maskz_load_ps (m, p);
+
+  _mm512_store_ps (p, x1);
+  _mm512_mask_store_ps (p, m, x1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovaps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovaps-2.c
new file mode 100644
index 000000000..d92ec968b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovaps-2.c
@@ -0,0 +1,71 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE ((AVX512F_LEN) / 32)
+#include "avx512f-mask-type.h"
+#define ALIGN ((AVX512F_LEN) / 8)
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s2, s3, res1, res3, res4, res5, res6;
+  MASK_TYPE mask = MASK_VALUE;
+  float s1[SIZE] __attribute__ ((aligned (ALIGN)));
+  float res2[SIZE] __attribute__ ((aligned (ALIGN)));
+  float res7[SIZE] __attribute__ ((aligned (ALIGN)));
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1[i] = 12.34 * (i + 2000) * sign;
+      s2.a[i] = 56.78 * (i - 30) * sign;
+      s3.a[i] = 90.12 * (i + 40) * sign;
+      res3.a[i] = DEFAULT_VALUE;
+      res5.a[i] = DEFAULT_VALUE;
+      res7[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_load_ps) (s1);
+  INTRINSIC (_store_ps) (res2, s2.x);
+#endif
+  res3.x = INTRINSIC (_mask_mov_ps) (res3.x, mask, s3.x);
+  res4.x = INTRINSIC (_maskz_mov_ps) (mask, s3.x);
+  res5.x = INTRINSIC (_mask_load_ps) (res5.x, mask, s1);
+  res6.x = INTRINSIC (_maskz_load_ps) (mask, s1);
+  INTRINSIC (_mask_store_ps) (res7, mask, s2.x);
+
+#if AVX512F_LEN == 512
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, s1))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, ) (s2, res2))
+    abort ();
+#endif
+
+  MASK_MERGE () (s3.a, mask, SIZE);
+  if (checkVf (res3.a, s3.a, SIZE))
+    abort ();
+
+  MASK_ZERO () (s3.a, mask, SIZE);
+  if (checkVf (res4.a, s3.a, SIZE))
+    abort ();
+
+  MASK_MERGE () (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res5, s1))
+    abort ();
+
+  MASK_ZERO () (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res6, s1))
+    abort ();
+
+  MASK_MERGE () (s2.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (s2, res7))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovddup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovddup-1.c
new file mode 100644
index 000000000..ccaa078ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovddup-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovddup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]|vunpcklpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vmovddup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]|vunpcklpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovddup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}|vunpcklpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x1, x2;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+    x1 = _mm512_movedup_pd (x2);
+    x1 = _mm512_mask_movedup_pd (x1, m8, x2);
+    x1 = _mm512_maskz_movedup_pd (m8, x2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovddup-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovddup-2.c
new file mode 100644
index 000000000..57619c142
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovddup-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+void static
+CALC (double *s, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE/2; i++)
+    {
+      r[2 * i] = s[2 * i];
+      r[2 * i + 1] = s[2 * i];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = i * 123.2 + 32.6;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_movedup_pd) (s.x);
+  res2.x = INTRINSIC (_mask_movedup_pd) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_movedup_pd) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa32-1.c
new file mode 100644
index 000000000..1bfd2a591
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa32-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovdqa32\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqa32\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqa32\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqa32\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqa32\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+int *p;
+volatile __m512i x1, x2;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_mask_mov_epi32 (x1, m, x2);
+  x1 = _mm512_maskz_mov_epi32 (m, x2);
+
+  x1 = _mm512_load_si512 (p);
+  x1 = _mm512_load_epi32 (p);
+  x1 = _mm512_mask_load_epi32 (x1, m, p);
+  x1 = _mm512_maskz_load_epi32 (m, p);
+
+  _mm512_store_si512 (p, x1);
+  _mm512_store_epi32 (p, x1);
+  _mm512_mask_store_epi32 (p, m, x1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa32-2.c
new file mode 100644
index 000000000..685b58b60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa32-2.c
@@ -0,0 +1,80 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE ((AVX512F_LEN) / 32)
+#include "avx512f-mask-type.h"
+#define ALIGN ((AVX512F_LEN) / 8)
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s2, s3, res1, res2, res5, res6, res7, res8;
+  MASK_TYPE mask = MASK_VALUE;
+  int s1[SIZE] __attribute__ ((aligned (ALIGN)));
+  int res3[SIZE] __attribute__ ((aligned (ALIGN)));
+  int res4[SIZE] __attribute__ ((aligned (ALIGN)));
+  int res9[SIZE] __attribute__ ((aligned (ALIGN)));
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1[i] = 1234 * (i + 2000) * sign;
+      s2.a[i] = 5678 * (i - 30) * sign;
+      s3.a[i] = 9012 * (i + 40) * sign;
+      res5.a[i] = DEFAULT_VALUE;
+      res7.a[i] = DEFAULT_VALUE;
+      res9[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_load_si512) (s1);
+  res2.x = INTRINSIC (_load_epi32) (s1);
+  INTRINSIC (_store_si512) (res3, s2.x);
+  INTRINSIC (_store_epi32) (res4, s2.x);
+#endif
+  res5.x = INTRINSIC (_mask_mov_epi32) (res5.x, mask, s3.x);
+  res6.x = INTRINSIC (_maskz_mov_epi32) (mask, s3.x);
+  res7.x = INTRINSIC (_mask_load_epi32) (res7.x, mask, s1);
+  res8.x = INTRINSIC (_maskz_load_epi32) (mask, s1);
+  INTRINSIC (_mask_store_epi32) (res9, mask, s2.x);
+
+#if AVX512F_LEN == 512
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, s1))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, s1))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (s2, res3))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (s2, res4))
+    abort ();
+#endif
+
+  MASK_MERGE (i_d) (s3.a, mask, SIZE);
+  if (checkVi (res5.a, s3.a, SIZE))
+    abort ();
+
+  MASK_ZERO (i_d) (s3.a, mask, SIZE);
+  if (checkVi (res6.a, s3.a, SIZE))
+    abort ();
+
+  MASK_MERGE (i_d) (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res7, s1))
+    abort ();
+
+  MASK_ZERO (i_d) (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res8, s1))
+    abort ();
+
+  MASK_MERGE (i_d) (s2.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (s2, res9))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa64-1.c
new file mode 100644
index 000000000..81f958adb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa64-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovdqa64\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqa64\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqa64\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqa64\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqa64\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+long long *p;
+volatile __m512i x1, x2;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm512_mask_mov_epi64 (x1, m, x2);
+  x1 = _mm512_maskz_mov_epi64 (m, x2);
+
+  x1 = _mm512_load_epi64 (p);
+  x1 = _mm512_mask_load_epi64 (x1, m, p);
+  x1 = _mm512_maskz_load_epi64 (m, p);
+
+  _mm512_store_epi64 (p, x1);
+  _mm512_mask_store_epi64 (p, m, x1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa64-2.c
new file mode 100644
index 000000000..d5f51f2d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqa64-2.c
@@ -0,0 +1,71 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE ((AVX512F_LEN) / 64)
+#include "avx512f-mask-type.h"
+#define ALIGN ((AVX512F_LEN) / 8)
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s2, s3, res1, res3, res4, res5, res6;
+  MASK_TYPE mask = MASK_VALUE;
+  long long s1[SIZE] __attribute__ ((aligned (ALIGN)));
+  long long res2[SIZE] __attribute__ ((aligned (ALIGN)));
+  long long res7[SIZE] __attribute__ ((aligned (ALIGN)));
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1[i] = 1234 * (i + 2000) * sign;
+      s2.a[i] = 5678 * (i - 30) * sign;
+      s3.a[i] = 9012 * (i + 40) * sign;
+      res3.a[i] = DEFAULT_VALUE;
+      res5.a[i] = DEFAULT_VALUE;
+      res7[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = INTRINSIC (_load_epi64) (s1);
+  INTRINSIC (_store_epi64) (res2, s2.x);
+#endif
+  res3.x = INTRINSIC (_mask_mov_epi64) (res3.x, mask, s3.x);
+  res4.x = INTRINSIC (_maskz_mov_epi64) (mask, s3.x);
+  res5.x = INTRINSIC (_mask_load_epi64) (res5.x, mask, s1);
+  res6.x = INTRINSIC (_maskz_load_epi64) (mask, s1);
+  INTRINSIC (_mask_store_epi64) (res7, mask, s2.x);
+
+#if AVX512F_LEN == 512
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, s1))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (s2, res2))
+    abort ();
+#endif
+
+  MASK_MERGE (i_q) (s3.a, mask, SIZE);
+  if (checkVl (res3.a, s3.a, SIZE))
+    abort ();
+
+  MASK_ZERO (i_q) (s3.a, mask, SIZE);
+  if (checkVl (res4.a, s3.a, SIZE))
+    abort ();
+
+  MASK_MERGE (i_q) (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res5, s1))
+    abort ();
+
+  MASK_ZERO (i_q) (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res6, s1))
+    abort ();
+
+  MASK_MERGE (i_q) (s2.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (s2, res7))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu32-1.c
new file mode 100644
index 000000000..79dbf9dd3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu32-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovdqu\[36\]\[24\]\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu32\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu32\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu32\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu32\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+int *p;
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_loadu_si512 (p);
+  x = _mm512_mask_loadu_epi32 (x, m, p);
+  x = _mm512_maskz_loadu_epi32 (m, p);
+
+  _mm512_storeu_si512 (p, x);
+  _mm512_mask_storeu_epi32 (p, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu32-2.c
new file mode 100644
index 000000000..f1ae73c1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu32-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE ((AVX512F_LEN) / 32)
+#include "avx512f-mask-type.h"
+
+typedef struct
+{
+  char c;
+  int a[SIZE];
+} __attribute__ ((packed)) EVAL(unaligned_array, AVX512F_LEN,);
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s2, res1, res3, res4;
+  EVAL(unaligned_array, AVX512F_LEN,) s1, res2, res5;
+  MASK_TYPE mask = MASK_VALUE;
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 12345 * (i + 2000) * sign;
+      s2.a[i] = 67890 * (i + 2000) * sign;
+      res3.a[i] = DEFAULT_VALUE;
+      res5.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+#if AVX512F_LEN == 512
+  res1.x = _mm512_loadu_si512 (s1.a);
+  _mm512_storeu_si512 (res2.a, s2.x);
+#endif
+  res3.x = INTRINSIC (_mask_loadu_epi32) (res3.x, mask, s1.a);
+  res4.x = INTRINSIC (_maskz_loadu_epi32) (mask, s1.a);
+  INTRINSIC (_mask_storeu_epi32) (res5.a, mask, s2.x);
+
+#if AVX512F_LEN == 512
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, s1.a))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (s2, res2.a))
+    abort ();
+#endif
+
+  MASK_MERGE (i_d) (s1.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, s1.a))
+    abort ();
+
+  MASK_ZERO (i_d) (s1.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res4, s1.a))
+    abort ();
+
+  MASK_MERGE (i_d) (s2.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (s2, res5.a))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu64-1.c
new file mode 100644
index 000000000..87565489e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu64-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovdqu64\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+
+#include <immintrin.h>
+
+long long *p;
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_loadu_epi64 (x, m, p);
+  x = _mm512_maskz_loadu_epi64 (m, p);
+
+  _mm512_mask_storeu_epi64 (p, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu64-2.c
new file mode 100644
index 000000000..867a2517d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovdqu64-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE ((AVX512F_LEN) / 64)
+#include "avx512f-mask-type.h"
+
+typedef struct
+{
+  char c;
+  long long a[SIZE];
+} __attribute__ ((packed)) EVAL(unaligned_array, AVX512F_LEN,);
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s2, res1, res2;
+  EVAL(unaligned_array, AVX512F_LEN,) s1, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 12345 * (i + 2000) * sign;
+      s2.a[i] = 67890 * (i + 2000) * sign;
+      res1.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_mask_loadu_epi64) (res1.x, mask, s1.a);
+  res2.x = INTRINSIC (_maskz_loadu_epi64) (mask, s1.a);
+  INTRINSIC (_mask_storeu_epi64) (res3.a, mask, s2.x);
+
+  MASK_MERGE (i_q) (s1.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, s1.a))
+    abort ();
+
+  MASK_ZERO (i_q) (s1.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, s1.a))
+    abort ();
+
+  MASK_MERGE (i_q) (s2.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (s2, res3.a))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdq-1.c
new file mode 100644
index 000000000..7a3ba47b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vmovntdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m512i *x;
+volatile __m512i y;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_stream_si512 (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdq-2.c
new file mode 100644
index 000000000..7b200e37d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdq-2.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union512i_q s, res;
+
+  s.x = _mm512_set_epi64 (39578, -429496, 7856, 0, 85632, -1234, 47563, -1);
+  _mm512_stream_si512 (&res.x, s.x);
+
+  if (check_union512i_q (s, res.a))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdqa-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdqa-1.c
new file mode 100644
index 000000000..d5be976e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdqa-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vmovntdqa\[ \\t\]+\[^\n\]*%zmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+__m512i *x;
+volatile __m512i y;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_stream_load_si512 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdqa-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdqa-2.c
new file mode 100644
index 000000000..0825781c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntdqa-2.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union512i_q s, res;
+
+  s.x = _mm512_set_epi64 (39578, -429496, 7856, 0, 85632, -1234, 47563, -1);
+  res.x = _mm512_stream_load_si512 (&s.x);
+
+  if (check_union512i_q (s, res.a))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntpd-1.c
new file mode 100644
index 000000000..a02162124
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntpd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vmovntpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+double *x;
+volatile __m512d y;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_stream_pd (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntpd-2.c
new file mode 100644
index 000000000..96c26c21e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntpd-2.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union512d s;
+  double res[8];
+
+  s.x = _mm512_set_pd (-39578.467285, 4294967295.1, -7856.342941, 0,
+		       85632.783567, 1234.9999, 47563.234215, -1.07);
+  _mm512_stream_pd (res, s.x);
+
+  if (check_union512d (s, res))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntps-1.c
new file mode 100644
index 000000000..933f01518
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntps-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vmovntps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+float *x;
+volatile __m512 y;
+
+void extern
+avx512f_test (void)
+{
+  _mm512_stream_ps (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntps-2.c
new file mode 100644
index 000000000..9f4c7cb5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovntps-2.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+
+void static
+avx512f_test (void)
+{
+  union512 s;
+  float res[16];
+
+  s.x = _mm512_set_ps (-39578.467285, 4294967295.1, -7856.342941, 0,
+		       85632.783567, 1234.9999, 47563.234215, -1.07,
+		       3453.65743, -1234.9999, 67.234, -1,
+		       0.336624, 34534543, 4345.234234, -1.07234234);
+
+  _mm512_stream_ps (res, s.x);
+
+  if (check_union512 (s, res))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovshdup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovshdup-1.c
new file mode 100644
index 000000000..b23df0a00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovshdup-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovshdup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vmovshdup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovshdup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_movehdup_ps (x);
+  x = _mm512_mask_movehdup_ps (x, m, x);
+  x = _mm512_maskz_movehdup_ps (m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovshdup-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovshdup-2.c
new file mode 100644
index 000000000..1cd8a6b9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovshdup-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+void static
+CALC (float *s, float *r)
+{
+  int i;
+
+  for (i = 1; i < SIZE; i += 2)
+    {
+      r[i - 1] = r[i] = s[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = i * 123.2 + 32.6;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_movehdup_ps) (s.x);
+  res2.x = INTRINSIC (_mask_movehdup_ps) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_movehdup_ps) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovsldup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovsldup-1.c
new file mode 100644
index 000000000..f2fd4e07d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovsldup-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovsldup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vmovsldup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovsldup\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_moveldup_ps (x);
+  x = _mm512_mask_moveldup_ps (x, m, x);
+  x = _mm512_maskz_moveldup_ps (m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovsldup-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovsldup-2.c
new file mode 100644
index 000000000..032fec82e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovsldup-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+void static
+CALC (float *s, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i += 2)
+    {
+      r[i] = r[i + 1] = s[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = i * 123.2 + 32.6;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_moveldup_ps) (s.x);
+  res2.x = INTRINSIC (_mask_moveldup_ps) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_moveldup_ps) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovupd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovupd-1.c
new file mode 100644
index 000000000..f505819e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovupd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovupd\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovupd\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovupd\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovupd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovupd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+double *p;
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_loadu_pd (p);
+  x = _mm512_mask_loadu_pd (x, m, p);
+  x = _mm512_maskz_loadu_pd (m, p);
+
+  _mm512_storeu_pd (p, x);
+  _mm512_mask_storeu_pd (p, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovupd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovupd-2.c
new file mode 100644
index 000000000..7e76e29b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovupd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, s2;
+  MASK_TYPE mask = MASK_VALUE;
+  double s1[SIZE];
+  double res4[SIZE];
+  double res5[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1[i] = 123.456 * (i + 2000) * sign;
+      s2.a[i] = 789.012 * (i + 3000) * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      res5[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_loadu_pd) (s1);
+  res2.x = INTRINSIC (_mask_loadu_pd) (res2.x, mask, s1);
+  res3.x = INTRINSIC (_maskz_loadu_pd) (mask, s1);
+  INTRINSIC (_storeu_pd) (res4, s2.x);
+  INTRINSIC (_mask_storeu_pd) (res5, mask, s2.x);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, s1))
+    abort ();
+
+  MASK_MERGE (d) (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, s1))
+    abort ();
+
+  MASK_ZERO (d) (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, s1))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, d) (s2, res4))
+    abort ();
+
+  MASK_MERGE (d) (s2.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (s2, res5))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovups-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovups-1.c
new file mode 100644
index 000000000..93b76876c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovups-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmovups\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovups\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovups\[ \\t\]+\[^\n\]*\\)\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vmovups\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmovups\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+float *p;
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_loadu_ps (p);
+  x = _mm512_mask_loadu_ps (x, m, p);
+  x = _mm512_maskz_loadu_ps (m, p);
+
+  _mm512_storeu_ps (p, x);
+  _mm512_mask_storeu_ps (p, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovups-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovups-2.c
new file mode 100644
index 000000000..7225bda54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmovups-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) res1, res2, res3, s2;
+  MASK_TYPE mask = MASK_VALUE;
+  float s1[SIZE];
+  float res4[SIZE];
+  float res5[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1[i] = 123.456 * (i + 2000) * sign;
+      s2.a[i] = 789.012 * (i + 3000) * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      res5[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_loadu_ps) (s1);
+  res2.x = INTRINSIC (_mask_loadu_ps) (res2.x, mask, s1);
+  res3.x = INTRINSIC (_maskz_loadu_ps) (mask, s1);
+  INTRINSIC (_storeu_ps) (res4, s2.x);
+  INTRINSIC (_mask_storeu_ps) (res5, mask, s2.x);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, s1))
+    abort ();
+
+  MASK_MERGE () (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, s1))
+    abort ();
+
+  MASK_ZERO () (s1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, s1))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, ) (s2, res4))
+    abort ();
+
+  MASK_MERGE () (s2.a, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (s2, res5))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulpd-1.c
new file mode 100644
index 000000000..944e54fb8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulpd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vmulpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vmulpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vmulpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vmulpd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmulpd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmulpd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mul_pd (x, x);
+  x = _mm512_mask_mul_pd (x, m, x, x);
+  x = _mm512_maskz_mul_pd (m, x, x);
+  x = _mm512_mul_round_pd (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_mul_round_pd (x, m, x, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_mul_round_pd (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulpd-2.c
new file mode 100644
index 000000000..bfd2a5155
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s1, double *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] * s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_mul_pd) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_mul_pd) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_mul_pd) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulps-1.c
new file mode 100644
index 000000000..273b82d67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vmulps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mul_ps (x, x);
+  x = _mm512_mask_mul_ps (x, m, x, x);
+  x = _mm512_maskz_mul_ps (m, x, x);
+  x = _mm512_mul_round_ps (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_mul_round_ps (x, m, x, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_mul_round_ps (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulps-2.c
new file mode 100644
index 000000000..09bb29967
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulps-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s1, float *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] * s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_mul_ps) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_mul_ps) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_mul_ps) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulsd-1.c
new file mode 100644
index 000000000..1726f7aa4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmulsd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_mul_round_sd (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulss-1.c
new file mode 100644
index 000000000..a3435f800
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vmulss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vmulss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_mul_round_ss (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsd-2.c
new file mode 100644
index 000000000..124e2e1a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsd-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *i1, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    if (i1[i] < 0)
+      r[i] = -i1[i];
+    else
+      r[i] = i1[i];
+}
+
+static void
+TEST (void)
+{
+  int ck[SIZE];
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) s, d, dm, dz;
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = i * 7 + (i << 15) + 356;
+      d.a[i] = DEFAULT_VALUE;
+      dm.a[i] = DEFAULT_VALUE;
+      dz.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (s.a, ck);
+
+  d.x = INTRINSIC (_abs_epi32) (s.x);
+  dz.x = INTRINSIC (_maskz_abs_epi32) (mask, s.x);
+  dm.x = INTRINSIC (_mask_abs_epi32) (dm.x, mask, s.x);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (d, ck))
+    abort ();
+
+  MASK_MERGE (i_d) (ck, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (dm, ck))
+    abort ();
+
+  MASK_ZERO (i_d) (ck, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (dz, ck))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsd512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsd512-1.c
new file mode 100644
index 000000000..67b1def17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsd512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpabsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpabsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpabsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_abs_epi32 (x);
+  x = _mm512_maskz_abs_epi32 (7, x);
+  x = _mm512_mask_abs_epi32 (x, 6, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsq-2.c
new file mode 100644
index 000000000..ff906f6d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsq-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *i1, long long *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    if (i1[i] < 0)
+      r[i] = -i1[i];
+    else
+      r[i] = i1[i];
+}
+
+static void
+TEST (void)
+{
+  long long ck[SIZE];
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) s, d, dm, dz;
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = i * 7 + (i << 15) + 356;
+      d.a[i] = DEFAULT_VALUE;
+      dm.a[i] = DEFAULT_VALUE;
+      dz.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (s.a, ck);
+
+  d.x = INTRINSIC (_abs_epi64) (s.x);
+  dz.x = INTRINSIC (_maskz_abs_epi64) (mask, s.x);
+  dm.x = INTRINSIC (_mask_abs_epi64) (dm.x, mask, s.x);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (d, ck))
+    abort ();
+
+  MASK_MERGE (i_q) (ck, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (dm, ck))
+    abort ();
+
+  MASK_ZERO (i_q) (ck, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (dz, ck))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsq512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsq512-1.c
new file mode 100644
index 000000000..fee48b1b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpabsq512-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpabsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpabsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpabsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_abs_epi64 (x);
+  x = _mm512_maskz_abs_epi64 (2, x);
+  x = _mm512_mask_abs_epi64 (x, 3, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddd-1.c
new file mode 100644
index 000000000..f4bf7eb3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_add_epi32 (x, x);
+  x = _mm512_mask_add_epi32 (x, m, x, x);
+  x = _mm512_maskz_add_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddd-2.c
new file mode 100644
index 000000000..8aff11eb9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, int *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] + s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_add_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_add_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_add_epi32) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddq-1.c
new file mode 100644
index 000000000..6f8223e11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpaddq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpaddq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpaddq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_add_epi64 (x, x);
+  x = _mm512_mask_add_epi64 (x, m, x, x);
+  x = _mm512_maskz_add_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddq-2.c
new file mode 100644
index 000000000..a9d317152
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpaddq-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] + s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_add_epi64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_add_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_add_epi64) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandd-1.c
new file mode 100644
index 000000000..fbf8a49a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_and_si512 (x, x);
+  x = _mm512_and_epi32 (x, x);
+  x = _mm512_mask_and_epi32 (x, m, x, x);
+  x = _mm512_maskz_and_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandd-2.c
new file mode 100644
index 000000000..b422c9d5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandd-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s1[i] & s2[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * sign;
+      s2.a[i] = (i + 20) * sign;
+      sign = -sign;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_and_si512) (s1.x, s2.x);
+  res2.x = INTRINSIC (_and_epi32) (s1.x, s2.x);
+  res3.x = INTRINSIC (_mask_and_epi32) (res3.x, mask, s1.x, s2.x);
+  res4.x = INTRINSIC (_maskz_and_epi32) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res4, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnd-1.c
new file mode 100644
index 000000000..8f48d601c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_andnot_si512 (x, x);
+  x = _mm512_andnot_epi32 (x, x);
+  x = _mm512_mask_andnot_epi32 (x, m, x, x);
+  x = _mm512_maskz_andnot_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnd-2.c
new file mode 100644
index 000000000..f1b12b6e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnd-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (~s1[i]) & s2[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * sign;
+      s2.a[i] = (i + 20) * sign;
+      sign = -sign;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_andnot_si512) (s1.x, s2.x);
+  res2.x = INTRINSIC (_andnot_epi32) (s1.x, s2.x);
+  res3.x = INTRINSIC (_mask_andnot_epi32) (res3.x, mask, s1.x, s2.x);
+  res4.x = INTRINSIC (_maskz_andnot_epi32) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+      abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+      abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res4, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnq-1.c
new file mode 100644
index 000000000..348fb1596
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpandnq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpandnq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_andnot_epi64 (x, x);
+  x = _mm512_mask_andnot_epi64 (x,m, x, x);
+  x = _mm512_maskz_andnot_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnq-2.c
new file mode 100644
index 000000000..d03bd0692
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandnq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *s1, long long *s2, long long *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (~s1[i]) & s2[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * sign;
+      s2.a[i] = (i + 20) * sign;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_andnot_epi64) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_andnot_epi64) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_andnot_epi64) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+      abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandq-1.c
new file mode 100644
index 000000000..343ff59f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpandq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpandq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_and_epi64 (x, x);
+  x = _mm512_mask_and_epi64 (x,m, x, x);
+  x = _mm512_maskz_and_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandq-2.c
new file mode 100644
index 000000000..86ab76ba8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpandq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *s1, long long *s2, long long *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s1[i] & s2[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * sign;
+      s2.a[i] = (i + 20) * sign;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_and_epi64) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_and_epi64) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_and_epi64) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+      abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmd-1.c
new file mode 100644
index 000000000..3a0aa2429
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "(vpblendmd|vmovdqa32)\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_blend_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmd-2.c
new file mode 100644
index 000000000..c2670fbf9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmd-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, int *s2, MASK_TYPE mask)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (mask & (1LL << i)) ? s2[i] : s1[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 15 + 3467 * i * sign;
+      src2.a[i] = -2217 * i * sign;
+      sign = sign * -1;
+    }
+
+  res1.x = INTRINSIC (_mask_blend_epi32) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a, mask);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmq-1.c
new file mode 100644
index 000000000..38581beaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "(vpblendmq|vmovdqa64)\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_blend_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmq-2.c
new file mode 100644
index 000000000..1fc8a5b57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpblendmq-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long *s2, MASK_TYPE mask)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (mask & (1LL << i)) ? s2[i] : s1[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 15 + 3467 * i * sign;
+      src2.a[i] = -2217 * i * sign;
+      sign = sign * -1;
+    }
+
+  res1.x = INTRINSIC (_mask_blend_epi64) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a, mask);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastd-1.c
new file mode 100644
index 000000000..668db6b81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastd-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[ \\t\]+%e\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[ \\t\]+%e\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[ \\t\]+%e\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile int z;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcastd_epi32 (y);
+  x = _mm512_mask_broadcastd_epi32 (x, m, y);
+  x = _mm512_maskz_broadcastd_epi32 (m, y);
+
+  x = _mm512_set1_epi32 (z);
+  x = _mm512_mask_set1_epi32 (x, m, z);
+  x = _mm512_maskz_set1_epi32 (m, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastd-2.c
new file mode 100644
index 000000000..67bd3ac2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastd-2.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[0];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  UNION_TYPE (128, i_d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < 4; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_broadcastd_epi32) (src.x);
+  res2.x = INTRINSIC (_mask_broadcastd_epi32) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_broadcastd_epi32) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+
+  res1.x = INTRINSIC (_set1_epi32) (src.a[0]);
+  res2.x = INTRINSIC (_mask_set1_epi32) (res2.x, mask, src.a[0]);
+  res3.x = INTRINSIC (_maskz_set1_epi32) (mask, src.a[0]);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastq-1.c
new file mode 100644
index 000000000..7c4698a34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastq-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 2  } } */
+/* { dg-final { scan-assembler-times "vpbroadcastq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vpbroadcastq\[ \\t\]+%r\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 { target { ! { ia32 } } } } } */
+/* { dg-final { scan-assembler-times "vpbroadcastq\[ \\t\]+%r\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 { target { ! { ia32 } } } } } */
+/* { dg-final { scan-assembler-times "vpbroadcastq\[ \\t\]+%r\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 { target { ! { ia32 } } } } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile long long z;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_broadcastq_epi64 (y);
+  x = _mm512_mask_broadcastq_epi64 (x, m, y);
+  x = _mm512_maskz_broadcastq_epi64 (m, y);
+
+  x = _mm512_set1_epi64 (z);
+  x = _mm512_mask_set1_epi64 (x, m, z);
+  x = _mm512_maskz_set1_epi64 (m, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastq-2.c
new file mode 100644
index 000000000..4518f6ef4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpbroadcastq-2.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[0];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  UNION_TYPE (128, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < 2; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_broadcastq_epi64) (src.x);
+  res2.x = INTRINSIC (_mask_broadcastq_epi64) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_broadcastq_epi64) (mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+
+  res1.x = INTRINSIC (_set1_epi64) (src.a[0]);
+  res2.x = INTRINSIC (_mask_set1_epi64) (res2.x, mask, src.a[0]);
+  res3.x = INTRINSIC (_maskz_set1_epi64) (mask, src.a[0]);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpd-1.c
new file mode 100644
index 000000000..7e835db1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpd-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler "vpcmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vpcmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmp_epi32_mask (x, x, _MM_CMPINT_GE);
+  m = _mm512_mask_cmp_epi32_mask (m, x, x, _MM_CMPINT_NLE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpd-2.c
new file mode 100644
index 000000000..600dfd2c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpd-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+#if AVX512F_LEN == 512
+#define CMP(imm, rel)					\
+    dst_ref = 0;					\
+    for (i = 0; i < 16; i++)				\
+    {							\
+      dst_ref = ((rel) << i) | dst_ref;			\
+    }							\
+    source1.x = _mm512_loadu_si512 (s1);		\
+    source2.x = _mm512_loadu_si512 (s2);		\
+    dst1 = _mm512_cmp_epi32_mask (source1.x, source2.x, imm);\
+    dst2 = _mm512_mask_cmp_epi32_mask (mask, source1.x, source2.x, imm);\
+    if (dst_ref != dst1) abort();			\
+    if ((mask & dst_ref) != dst2) abort();
+#endif
+
+static void
+TEST ()
+{
+    UNION_TYPE (AVX512F_LEN, i_d) source1, source2;
+    MASK_TYPE dst1, dst2, dst_ref;
+    MASK_TYPE mask = MASK_VALUE;
+    int i;
+    int s1[16] = {2134,  6678,  453, 54646,
+		  231, 5674,  111, 23241,
+		  12314,  145,  671, 77575,
+		  23455,  166, 5321, 5673};
+    int s2[16] = {41124, 6678, 8653,   856,
+		  231, 4646,  111,   124,
+		  2745, 4567, 3676,   123,
+		  714, 3589, 5683,  5673};
+
+    CMP(0x00, s1[i] == s2[i]);
+    CMP(0x01, s1[i] < s2[i]);
+    CMP(0x02, s1[i] <= s2[i]);
+    CMP(0x03, 0);
+    CMP(0x04, s1[i] != s2[i]);
+    CMP(0x05, s1[i] >= s2[i]);
+    CMP(0x06, s1[i] > s2[i]);
+    CMP(0x07, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqd-1.c
new file mode 100644
index 000000000..834fae79a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqd-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpeqd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpcmpeqd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]\{" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpeq_epi32_mask (x, x);
+  m = _mm512_mask_cmpeq_epi32_mask (3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqd-2.c
new file mode 100644
index 000000000..9a4c493aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqd-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] == s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1, res2;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+  res2 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpeq_epi32_mask) (src1.x, src2.x);
+  res2 = INTRINSIC (_mask_cmpeq_epi32_mask) (mask, src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+
+  res_ref &= mask;
+
+  if (res_ref != res2)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqq-1.c
new file mode 100644
index 000000000..8689fe3a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqq-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpeqq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpcmpeqq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]\{" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpeq_epi64_mask (x, x);
+  m = _mm512_mask_cmpeq_epi64_mask (3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqq-2.c
new file mode 100644
index 000000000..8c269eeb1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpeqq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] == s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res2, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+  res2 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpeq_epi64_mask) (src1.x, src2.x);
+  res2 = INTRINSIC (_mask_cmpeq_epi64_mask) (mask, src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+
+  res_ref &= mask;
+
+  if (res2 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpged-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpged-1.c
new file mode 100644
index 000000000..83c259eee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpged-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpge_epi32_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpged-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpged-2.c
new file mode 100644
index 000000000..988587810
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpged-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] >= s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpge_epi32_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeq-1.c
new file mode 100644
index 000000000..ec7a17510
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpge_epi64_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeq-2.c
new file mode 100644
index 000000000..dfff1dc34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] >= s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpge_epi64_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeud-1.c
new file mode 100644
index 000000000..3db73a9fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeud-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpge_epu32_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeud-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeud-2.c
new file mode 100644
index 000000000..7bb366783
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeud-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] >= s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpge_epu32_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeuq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeuq-1.c
new file mode 100644
index 000000000..4d9c3f4ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeuq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpge_epu64_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeuq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeuq-2.c
new file mode 100644
index 000000000..78cae6941
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgeuq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] >= s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpge_epu64_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtd-1.c
new file mode 100644
index 000000000..1be0f8d26
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtd-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpgtd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpcmpgtd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]\{" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpgt_epi32_mask (x, x);
+  m = _mm512_mask_cmpgt_epi32_mask (3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtd-2.c
new file mode 100644
index 000000000..6c8243605
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtd-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] > s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1, res2;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+  res2 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpgt_epi32_mask) (src1.x, src2.x);
+  res2 = INTRINSIC (_mask_cmpgt_epi32_mask) (mask, src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+
+  res_ref &= mask;
+
+  if (res_ref != res2)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtq-1.c
new file mode 100644
index 000000000..b94be287e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtq-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpgtq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpcmpgtq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]\{" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpgt_epi64_mask (x, x);
+  m = _mm512_mask_cmpgt_epi64_mask (3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtq-2.c
new file mode 100644
index 000000000..c1eb5801b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpgtq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] > s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res2, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+  res2 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpgt_epi64_mask) (src1.x, src2.x);
+  res2 = INTRINSIC (_mask_cmpgt_epi64_mask) (mask, src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+
+  res_ref &= mask;
+
+  if (res2 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpled-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpled-1.c
new file mode 100644
index 000000000..68f085ace
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpled-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmple_epi32_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpled-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpled-2.c
new file mode 100644
index 000000000..15573766c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpled-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] <= s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmple_epi32_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleq-1.c
new file mode 100644
index 000000000..0d5b6fab6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmple_epi64_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleq-2.c
new file mode 100644
index 000000000..5fdf9d752
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] <= s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmple_epi64_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleud-1.c
new file mode 100644
index 000000000..902f4ab05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleud-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmple_epu32_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleud-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleud-2.c
new file mode 100644
index 000000000..22c825a09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleud-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] <= s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmple_epu32_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleuq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleuq-1.c
new file mode 100644
index 000000000..5c5f0e5cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleuq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmple_epu64_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleuq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleuq-2.c
new file mode 100644
index 000000000..e7843d1e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpleuq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] <= s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmple_epu64_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltd-1.c
new file mode 100644
index 000000000..16bb1bf1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmplt_epi32_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltd-2.c
new file mode 100644
index 000000000..f8728cd0d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltd-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] < s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmplt_epi32_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltq-1.c
new file mode 100644
index 000000000..0e87ad14e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmplt_epi64_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltq-2.c
new file mode 100644
index 000000000..204b69e57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] < s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmplt_epi64_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltud-1.c
new file mode 100644
index 000000000..0ad8fd195
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltud-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmplt_epu32_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltud-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltud-2.c
new file mode 100644
index 000000000..aea70ec84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltud-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] < s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmplt_epu32_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltuq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltuq-1.c
new file mode 100644
index 000000000..d428b0064
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltuq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmplt_epu64_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltuq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltuq-2.c
new file mode 100644
index 000000000..83becbd6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpltuq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] < s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmplt_epu64_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqd-1.c
new file mode 100644
index 000000000..2cffad594
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpneq_epi32_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqd-2.c
new file mode 100644
index 000000000..fd9bfc5aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqd-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] != s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpneq_epi32_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqq-1.c
new file mode 100644
index 000000000..4a2928acb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpneq_epi64_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqq-2.c
new file mode 100644
index 000000000..1beacd449
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpneqq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] != s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpneq_epi64_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequd-1.c
new file mode 100644
index 000000000..2c204790d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpneq_epu32_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequd-2.c
new file mode 100644
index 000000000..09d11f52c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequd-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, int *s1, int *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] != s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpneq_epu32_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res_ref != res1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequq-1.c
new file mode 100644
index 000000000..770149399
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequq-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcmpuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmpneq_epu64_mask (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequq-2.c
new file mode 100644
index 000000000..41e1f5b63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpnequq-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *r, long long *s1, long long *s2)
+{
+  int i;
+  *r = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (s1[i] != s2[i])
+      *r = *r | (one << i);
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res1, res_ref;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      src1.a[i * 2] = i;
+      src1.a[i * 2 + 1] = i * i;
+      src2.a[i * 2] = 2 * i;
+      src2.a[i * 2 + 1] = i * i;
+    }
+
+  res1 = INTRINSIC (_cmpneq_epu64_mask) (src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpq-1.c
new file mode 100644
index 000000000..800140d03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpq-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler "vpcmpq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+/* { dg-final { scan-assembler "vpcmpq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmp_epi64_mask (x, x, _MM_CMPINT_NE);
+  m = _mm512_mask_cmp_epi64_mask (m, x, x, _MM_CMPINT_NLT);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpq-2.c
new file mode 100644
index 000000000..2a9ceb6a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpq-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+__mmask8 dst_ref;
+
+#define CMP(imm, rel)					\
+    dst_ref = 0;					\
+    for (i = 0; i < 8; i++)				\
+    {							\
+      dst_ref = ((rel) << i) | dst_ref;			\
+    }							\
+    source1.x = _mm512_loadu_si512 (s1);		\
+    source2.x = _mm512_loadu_si512 (s2);		\
+    dst1 = _mm512_cmp_epi64_mask (source1.x, source2.x, imm);\
+    dst2 = _mm512_mask_cmp_epi64_mask (mask, source1.x, source2.x, imm);\
+    if (dst_ref != dst1) abort();			\
+    if ((mask & dst_ref) != dst2) abort();
+
+static void
+TEST ()
+{
+    UNION_TYPE (AVX512F_LEN, i_d) source1, source2;
+    MASK_TYPE dst1, dst2, dst_ref;
+    MASK_TYPE mask = MASK_VALUE;
+    long long s1[8] = {2134,  6678,  453, 54646,
+		       231,  5674,  111, 23241};
+    long long s2[8] = {41124, 6678, 8653,   856,
+		       231,  4646,  111,   124};
+    int i;
+
+    CMP(0x00, s1[i] == s2[i]);
+    CMP(0x01, s1[i] < s2[i]);
+    CMP(0x02, s1[i] <= s2[i]);
+    CMP(0x03, 0);
+    CMP(0x04, s1[i] != s2[i]);
+    CMP(0x05, s1[i] >= s2[i]);
+    CMP(0x06, s1[i] > s2[i]);
+    CMP(0x07, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpud-1.c
new file mode 100644
index 000000000..110c09047
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpud-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler "vpcmpud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vpcmpud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmp_epu32_mask (x, x, _MM_CMPINT_EQ);
+  m = _mm512_mask_cmp_epu32_mask (m, x, x, _MM_CMPINT_LT);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpud-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpud-2.c
new file mode 100644
index 000000000..c0bb97839
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpud-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+#if AVX512F_LEN == 512
+#define CMP(imm, rel)					\
+    dst_ref = 0;					\
+    for (i = 0; i < 16; i++)				\
+    {							\
+      dst_ref = ((rel) << i) | dst_ref;			\
+    }							\
+    source1.x = _mm512_loadu_si512 (s1);		\
+    source2.x = _mm512_loadu_si512 (s2);		\
+    dst1 = _mm512_cmp_epu32_mask (source1.x, source2.x, imm);\
+    dst2 = _mm512_mask_cmp_epu32_mask (mask, source1.x, source2.x, imm);\
+    if (dst_ref != dst1) abort();			\
+    if ((mask & dst_ref) != dst2) abort();
+#endif
+
+static void
+TEST ()
+{
+    unsigned int s1[16] = {2134,  6678,  453, 54646,
+			  231, 5674,  111, 23241,
+			  12314,  145,  671, 77575,
+			  23455,  166, 5321, 5673};
+    unsigned int s2[16] = {41124, 6678, 8653,   856,
+			  231, 4646,  111,   124,
+			  2745, 4567, 3676,   123,
+			  714, 3589, 5683,  5673};
+    UNION_TYPE (AVX512F_LEN, i_d) source1, source2;
+    MASK_TYPE dst1, dst2, dst_ref;
+    MASK_TYPE mask = MASK_VALUE;
+    int i;
+
+    CMP(0x00, s1[i] == s2[i]);
+    CMP(0x01, s1[i] < s2[i]);
+    CMP(0x02, s1[i] <= s2[i]);
+    CMP(0x03, 0);
+    CMP(0x04, s1[i] != s2[i]);
+    CMP(0x05, s1[i] >= s2[i]);
+    CMP(0x06, s1[i] > s2[i]);
+    CMP(0x07, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpuq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpuq-1.c
new file mode 100644
index 000000000..2f79f4dcc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpuq-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler "vpcmpuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\[^\{\]" } } */
+/* { dg-final { scan-assembler "vpcmpuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n^k\]*%k\[1-7\]\{" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  m = _mm512_cmp_epu64_mask (x, x, _MM_CMPINT_LE);
+  m = _mm512_mask_cmp_epu64_mask (m, x, x, _MM_CMPINT_UNUSED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpuq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpuq-2.c
new file mode 100644
index 000000000..3bd1b8656
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcmpuq-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#if AVX512F_LEN == 512
+#define CMP(imm, rel)					\
+    dst_ref = 0;					\
+    for (i = 0; i < 8; i++)				\
+    {							\
+      dst_ref = ((rel) << i) | dst_ref;			\
+    }							\
+    source1.x = _mm512_loadu_si512 (s1);		\
+    source2.x = _mm512_loadu_si512 (s2);		\
+    dst1 = _mm512_cmp_epu64_mask (source1.x, source2.x, imm);\
+    dst2 = _mm512_mask_cmp_epu64_mask (mask, source1.x, source2.x, imm);\
+    if (dst_ref != dst1) abort();			\
+    if ((mask & dst_ref) != dst2) abort();
+#endif
+
+static void
+TEST ()
+{
+    UNION_TYPE (AVX512F_LEN, i_q) source1, source2;
+    MASK_TYPE dst1, dst2, dst_ref;
+    MASK_TYPE mask = MASK_VALUE;
+    int i;
+    unsigned long long s1[8] = {2134,  6678,  453, 54646,
+				231,  5674,  111, 23241};
+    unsigned long long s2[8] = {41124, 6678, 8653,   856,
+				231,  4646,  111,   124};
+
+    CMP(0x00, s1[i] == s2[i]);
+    CMP(0x01, s1[i] < s2[i]);
+    CMP(0x02, s1[i] <= s2[i]);
+    CMP(0x03, 0);
+    CMP(0x04, s1[i] != s2[i]);
+    CMP(0x05, s1[i] >= s2[i]);
+    CMP(0x06, s1[i] > s2[i]);
+    CMP(0x07, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressd-1.c
new file mode 100644
index 000000000..162fa7aef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressd-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcompressd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+int *p;
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_compress_epi32 (x, m, x);
+  x = _mm512_maskz_compress_epi32 (m, x);
+
+  _mm512_mask_compressstoreu_epi32 (p, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressd-2.c
new file mode 100644
index 000000000..2c1e3f586
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressd-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#define MASK ((1 << SIZE) - 1)
+#include <x86intrin.h>
+
+static void
+CALC (int *s, int *r, MASK_TYPE mask)
+{
+  int i, k;
+
+  for (i = 0, k = 0; i < SIZE; i++)
+    {
+      if (mask & (1 << i))
+	r[k++] = s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s, res1, res2;
+  int res3[SIZE];
+  MASK_TYPE compressed_mask, mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, mask_bit_count, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 12345 * (i + 200) * sign;
+      res1.a[i] = DEFAULT_VALUE;
+      res3[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_mask_compress_epi32) (res1.x, mask, s.x);
+  res2.x = INTRINSIC (_maskz_compress_epi32) (mask, s.x);
+  INTRINSIC (_mask_compressstoreu_epi32) (res3, mask, s.x);
+
+  mask_bit_count = __popcntd (mask & MASK);
+  compressed_mask = (1 << mask_bit_count) - 1;
+  CALC (s.a, res_ref, mask);
+
+  MASK_MERGE (i_d) (res_ref, compressed_mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, compressed_mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, compressed_mask, SIZE);
+  if (checkVi (res3, res_ref, SIZE))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressq-1.c
new file mode 100644
index 000000000..3a07ee89b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressq-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpcompressq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*\\)\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+long long *p;
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_compress_epi64 (x, m, x);
+  x = _mm512_maskz_compress_epi64 (m, x);
+
+  _mm512_mask_compressstoreu_epi64 (p, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressq-2.c
new file mode 100644
index 000000000..0ea69f0ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpcompressq-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#define MASK ((1 << SIZE) - 1)
+#include <x86intrin.h>
+
+static void
+CALC (long long *s, long long *r, MASK_TYPE mask)
+{
+  int i, k;
+
+  for (i = 0, k = 0; i < SIZE; i++)
+    {
+      if (mask & (1 << i))
+	r[k++] = s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s, res1, res2;
+  long long res3[SIZE];
+  MASK_TYPE compressed_mask, mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i, mask_bit_count, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 12345 * (i + 200) * sign;
+      res1.a[i] = DEFAULT_VALUE;
+      res3[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_mask_compress_epi64) (res1.x, mask, s.x);
+  res2.x = INTRINSIC (_maskz_compress_epi64) (mask, s.x);
+  INTRINSIC (_mask_compressstoreu_epi64) (res3, mask, s.x);
+
+  mask_bit_count = __popcntd (mask & MASK);
+  compressed_mask = (1 << mask_bit_count) - 1;
+  CALC (s.a, res_ref, mask);
+
+  MASK_MERGE (i_q) (res_ref, compressed_mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, compressed_mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, compressed_mask, SIZE);
+  if (checkVl (res3, res_ref, SIZE))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermd-1.c
new file mode 100644
index 000000000..4b5f8d91a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vpermd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutexvar_epi32 (x, x);
+  x = _mm512_maskz_permutexvar_epi32 (m, x, x);
+  x = _mm512_mask_permutexvar_epi32 (x, m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermd-2.c
new file mode 100644
index 000000000..1c494e3d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermd-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *mask, int *src1, int *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      dst[i] = src1[mask[i] & 15];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = (i + 10) * (i + 10) * sign;
+      src2.a[i] = (i + 30);
+      sign = -sign;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permutexvar_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_maskz_permutexvar_epi32) (mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_mask_permutexvar_epi32) (res3.x, mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-1.c
new file mode 100644
index 000000000..0436dfd70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermi2d\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask2_permutex2var_epi32 (x, x, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-2.c
new file mode 100644
index 000000000..9aa104bbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2d-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (int *dst, int *src1, int *ind, int *src2)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      unsigned long long offset = ind[i] & (SIZE - 1);
+      unsigned long long cond = ind[i] & SIZE;
+
+      dst[i] = cond ? src2[offset] : src1[offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2, res, ind;
+  int res_ref[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      ind.a[i] = DEFAULT_VALUE;
+      s1.a[i] = 34 * i + 1;
+      s2.a[i] = 34 * i;
+
+      res.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (res_ref, s1.a, ind.a, s2.a);
+
+  res.x =
+    INTRINSIC (_mask2_permutex2var_epi32) (s1.x, ind.x, mask, s2.x);
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-1.c
new file mode 100644
index 000000000..e2b74cc99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermi2pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m512i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask2_permutex2var_pd (x, y, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-2.c
new file mode 100644
index 000000000..a2daca0bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2pd-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (double *dst, double *src1, long long *ind, double *src2)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      unsigned long long offset = ind[i] & (SIZE - 1);
+      unsigned long long cond = ind[i] & SIZE;
+
+      dst[i] = cond ? src2[offset] : src1[offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, k;
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, res;
+  UNION_TYPE (AVX512F_LEN, i_q) ind;
+  double res_ref[SIZE];
+
+  union
+  {
+    double f;
+    long long i;
+  } ind_copy[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      /* Some of the integer indexes may be interpreted as floating point
+         values in mask-merge mode, that's why we use IND_COPY.  */
+      ind.a[i] = ind_copy[i].i = 17 * (i << 1);
+      s1.a[i] = 42.5 * i + 1;
+      s2.a[i] = 22.5 * i;
+
+      res.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (res_ref, s1.a, ind.a, s2.a);
+
+  res.x = INTRINSIC (_mask2_permutex2var_pd) (s1.x, ind.x, mask, s2.x);
+
+  /* Standard MASK_MERGE cannot be used since VPERMI2PD in mask-merge mode
+     merges vectors of two different types (_m512d and __m512i).  */
+  for (k = 0; k < SIZE; k++)
+    res_ref[k] = (mask & (1LL << k)) ? res_ref[k] : ind_copy[k].f;
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-1.c
new file mode 100644
index 000000000..fc103a90e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermi2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m512i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask2_permutex2var_ps (x, y, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-2.c
new file mode 100644
index 000000000..56215cfca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2ps-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (float *dst, float *src1, int *ind, float *src2)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      unsigned long long offset = ind[i] & (SIZE - 1);
+      unsigned long long cond = ind[i] & SIZE;
+
+      dst[i] = cond ? src2[offset] : src1[offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, k;
+  UNION_TYPE (AVX512F_LEN,) s1, s2, res;
+  UNION_TYPE (AVX512F_LEN, i_d) ind;
+  float res_ref[SIZE];
+
+  union
+  {
+    float f;
+    int i;
+  } ind_copy[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      /* Some of the integer indexes may be interpreted as floating point
+         values in mask-merge mode, that's why we use IND_COPY.  */
+      ind.a[i] = ind_copy[i].i = 17 * (i << 1);
+      s1.a[i] = 42.5 * i + 1;
+      s2.a[i] = 22.5 * i;
+
+      res.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (res_ref, s1.a, ind.a, s2.a);
+
+  res.x = INTRINSIC (_mask2_permutex2var_ps) (s1.x, ind.x, mask, s2.x);
+
+  /* Standard MASK_MERGE cannot be used since VPERMI2PS in mask-merge mode
+     merges vectors of two different types (_m512 and __m512i).  */
+  for (k = 0; k < SIZE; k++)
+    res_ref[k] = (mask & (1LL << k)) ? res_ref[k] : ind_copy[k].f;
+
+  if (UNION_CHECK (AVX512F_LEN,) (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-1.c
new file mode 100644
index 000000000..7d780b2a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermi2q\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask2_permutex2var_epi64 (x, x, m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-2.c
new file mode 100644
index 000000000..9d7b9bec3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermi2q-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (long long *dst, long long *src1, long long *ind, long long *src2)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      unsigned long long offset = ind[i] & (SIZE - 1);
+      unsigned long long cond = ind[i] & SIZE;
+
+      dst[i] = cond ? src2[offset] : src1[offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) s1, s2, res, ind;
+  long long res_ref[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      ind.a[i] = DEFAULT_VALUE;
+      s1.a[i] = 34 * i + 1;
+      s2.a[i] = 34 * i;
+
+      res.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (res_ref, s1.a, ind.a, s2.a);
+
+  res.x =
+    INTRINSIC (_mask2_permutex2var_epi64) (s1.x, ind.x, mask, s2.x);
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpd-1.c
new file mode 100644
index 000000000..061a62535
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermilpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermilpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermilpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m512i c;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutevar_pd (x, c);
+  x = _mm512_mask_permutevar_pd (x, m, x, c);
+  x = _mm512_maskz_permutevar_pd (m, x, c);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpd-2.c
new file mode 100644
index 000000000..27d697bd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpd-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#ifndef CTRL
+#define CTRL 6
+#endif
+
+#undef mask_v
+#define mask_v(pos) (((CTRL & (1ULL << (pos))) >> (pos)) << 1)
+
+static void
+CALC (double *s1, long long *s2, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s1[(2 * (i / 2)) + ((s2[i] & 0x02) >> 1)];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN, i_q) s2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i + 10.;
+      s2.a[i] = mask_v (i);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permutevar_pd) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_permutevar_pd) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_permutevar_pd) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpdi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpdi-1.c
new file mode 100644
index 000000000..8b5ffd023
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpdi-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermilpd\[ \\t\]+\[^\n\]*13\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermilpd\[ \\t\]+\[^\n\]*13\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermilpd\[ \\t\]+\[^\n\]*13\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permute_pd (x, 13);
+  x = _mm512_mask_permute_pd (x, m, x, 13);
+  x = _mm512_maskz_permute_pd (m, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpdi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpdi-2.c
new file mode 100644
index 000000000..9b5ecd4c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpdi-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#ifndef CTRL
+#define CTRL 129
+#endif
+
+static void
+CALC (double *s1, int s2, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (s2 & (1 << i)) ? s1[1 + 2 * (i / 2)] : s1[2 * (i / 2)];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i + 10.;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permute_pd) (s1.x, CTRL);
+  res2.x = INTRINSIC (_mask_permute_pd) (res2.x, mask, s1.x, CTRL);
+  res3.x = INTRINSIC (_maskz_permute_pd) (mask, s1.x, CTRL);
+
+  CALC (s1.a, CTRL, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilps-1.c
new file mode 100644
index 000000000..b46182b24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilps-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermilps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermilps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermilps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m512i c;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutevar_ps (x, c);
+  x = _mm512_mask_permutevar_ps (x, m, x, c);
+  x = _mm512_maskz_permutevar_ps (m, x, c);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilps-2.c
new file mode 100644
index 000000000..92c65538d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilps-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+#ifndef CTRL
+#define CTRL 233
+#endif
+
+#undef mask_v
+#define mask_v(pos) ((CTRL & (0x3 << (pos))) >> (pos))
+
+static void
+CALC (float *s1, int *s2, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s1[(4 * (i / 4)) + (s2[i] & 0x03)];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) s1, res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN, i_d) s2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i + 10.;
+      s2.a[i] = mask_v (i);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permutevar_ps) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_permutevar_ps) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_permutevar_ps) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpsi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpsi-1.c
new file mode 100644
index 000000000..f09213e03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpsi-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermilps\[ \\t\]+\[^\n\]*13\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermilps\[ \\t\]+\[^\n\]*13\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermilps\[ \\t\]+\[^\n\]*13\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permute_ps (x, 13);
+  x = _mm512_mask_permute_ps (x, m, x, 13);
+  x = _mm512_maskz_permute_ps (m, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpsi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpsi-2.c
new file mode 100644
index 000000000..381a794b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermilpsi-2.c
@@ -0,0 +1,82 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+#ifndef CTRL
+#define CTRL 129
+#endif
+
+#ifndef SELECT4_DEFINED
+#define SELECT4_DEFINED
+static int
+select4 (int i, unsigned ctrl)
+{
+  int res;
+  switch (i % 4)
+    {
+    case 0:
+      res = (CTRL & 0x03);
+      break;
+    case 1:
+      res = ((CTRL & 0x0c) >> 2);
+      break;
+    case 2:
+      res = ((CTRL & 0x30) >> 4);
+      break;
+    case 3:
+      res = ((CTRL & 0xc0) >> 6);
+      break;
+    }
+  return res;
+}
+#endif
+
+static void
+CALC (float *s, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[(4 * (i / 4)) + select4 (i, CTRL)];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) s1, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i + 10.;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permute_ps) (s1.x, CTRL);
+  res2.x = INTRINSIC (_mask_permute_ps) (res2.x, mask, s1.x, CTRL);
+  res3.x = INTRINSIC (_maskz_permute_ps) (mask, s1.x, CTRL);
+
+  CALC (s1.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpd-1.c
new file mode 100644
index 000000000..d2e8b9c97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m512d y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_permutexvar_pd (x, y);
+  y = _mm512_mask_permutexvar_pd (y, m, x, y);
+  y = _mm512_maskz_permutexvar_pd (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpd-2.c
new file mode 100644
index 000000000..00d171b79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpd-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *mask, double *s1, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[mask[i] & 7 % SIZE];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) src1, res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN, i_q) src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i * sign;
+      src2.a[i] = i + 20;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permutexvar_pd) (src2.x, src1.x);
+  res2.x = INTRINSIC (_mask_permutexvar_pd) (res2.x, mask, src2.x, src1.x);
+  res3.x = INTRINSIC (_maskz_permutexvar_pd) (mask, src2.x, src1.x);
+
+  CALC (src2.a, src1.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpdi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpdi-1.c
new file mode 100644
index 000000000..97fd92c84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpdi-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutex_pd (x, 13);
+  x = _mm512_mask_permutex_pd (x, m, x, 13);
+  x = _mm512_maskz_permutex_pd (m, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpdi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpdi-2.c
new file mode 100644
index 000000000..eb8e58381
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermpdi-2.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#define N 0x7c
+
+static void
+CALC (double *s1, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      int index = (N >> ((i % 4) * 2)) & 3;
+      int base = i / 4;
+      r[i] = s1[4 * base + index];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) src1, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i * i * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_permutex_pd) (src1.x, N);
+  res2.x = INTRINSIC (_mask_permutex_pd) (res2.x, mask, src1.x, N);
+  res3.x = INTRINSIC (_maskz_permutex_pd) (mask, src1.x, N);
+
+  CALC (src1.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermps-1.c
new file mode 100644
index 000000000..7b7367afa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermps-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m512 y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  y = _mm512_permutexvar_ps (x, y);
+  y = _mm512_mask_permutexvar_ps (y, m, x, y);
+  y = _mm512_maskz_permutexvar_ps (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermps-2.c
new file mode 100644
index 000000000..53081c48e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermps-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *mask, float *s1, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[mask[i] & 15 % SIZE];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) src1, res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN, i_d) src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i * sign;
+      src2.a[i] = i + 20;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permutexvar_ps) (src2.x, src1.x);
+  res2.x = INTRINSIC (_mask_permutexvar_ps) (res2.x, mask, src2.x, src1.x);
+  res3.x = INTRINSIC (_maskz_permutexvar_ps) (mask, src2.x, src1.x);
+
+  CALC (src2.a, src1.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-1.c
new file mode 100644
index 000000000..ef0271b61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutex_epi64 (x, 13);
+  x = _mm512_mask_permutex_epi64 (x, m, x, 13);
+  x = _mm512_maskz_permutex_epi64 (m, x, 13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-2.c
new file mode 100644
index 000000000..6b1d778c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-imm-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#define IMM_MASK 0x7c
+
+static void
+CALC (long long *src1, int mask, long long *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      int index = ((mask >> (2 * (i % 4))) & 3);
+      int base = i / 4;
+      dst[i] = src1[4 * base + index];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = (i + 10) * (i + 10) * sign;
+      sign = -sign;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permutex_epi64) (src1.x, IMM_MASK);
+  res2.x = INTRINSIC (_maskz_permutex_epi64) (mask, src1.x, IMM_MASK);
+  res3.x = INTRINSIC (_mask_permutex_epi64) (res3.x, mask, src1.x, IMM_MASK);
+
+  CALC (src1.a, IMM_MASK, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-1.c
new file mode 100644
index 000000000..62b28c33d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vpermq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutexvar_epi64 (x, x);
+  x = _mm512_maskz_permutexvar_epi64 (m, x, x);
+  x = _mm512_mask_permutexvar_epi64 (x, m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-2.c
new file mode 100644
index 000000000..ff330a571
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermq-var-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *mask, long long *src1, long long *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      dst[i] = src1[mask[i] & 7];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = (i + 10) * (i + 10) * sign;
+      src2.a[i] = 2 * i + 10;
+      sign = -sign;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_permutexvar_epi64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_maskz_permutexvar_epi64) (mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_mask_permutexvar_epi64) (res3.x, mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-1.c
new file mode 100644
index 000000000..892b5710d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermt2d\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermt2d\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermt2d\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutex2var_epi32 (x, x, x);
+  x = _mm512_mask_permutex2var_epi32 (x, m, x, x);
+  x = _mm512_maskz_permutex2var_epi32 (m, x, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-2.c
new file mode 100644
index 000000000..ef8d1951b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2d-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (int *dst, int *src1, int *ind, int *src2)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      unsigned long long offset = ind[i] & (SIZE - 1);
+      unsigned long long cond = ind[i] & SIZE;
+
+      dst[i] = cond ? src2[offset] : src1[offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2, res1, res2, res3, ind;
+  int res_ref[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      ind.a[i] = 17 * (i << 1);
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 34 * i;
+
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (res_ref, s1.a, ind.a, s2.a);
+
+  res1.x = INTRINSIC (_permutex2var_epi32) (s1.x, ind.x, s2.x);
+  res2.x =
+    INTRINSIC (_mask_permutex2var_epi32) (s1.x, mask, ind.x, s2.x);
+  res3.x =
+    INTRINSIC (_maskz_permutex2var_epi32) (mask, s1.x, ind.x, s2.x);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-1.c
new file mode 100644
index 000000000..01595233f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermt2pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermt2pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermt2pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __m512i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutex2var_pd (x, y, x);
+  x = _mm512_mask_permutex2var_pd (x, m, y, x);
+  x = _mm512_maskz_permutex2var_pd (m, x, y, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-2.c
new file mode 100644
index 000000000..511a47015
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2pd-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (double *dst, double *src1, long long *ind, double *src2)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      unsigned long long offset = ind[i] & (SIZE - 1);
+      unsigned long long cond = ind[i] & SIZE;
+
+      dst[i] = cond ? src2[offset] : src1[offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN, i_q) ind;
+  double res_ref[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      ind.a[i] = 17 * (i << 1);
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 22.5 * i;
+
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (res_ref, s1.a, ind.a, s2.a);
+
+  res1.x = INTRINSIC (_permutex2var_pd) (s1.x, ind.x, s2.x);
+  res2.x = INTRINSIC (_mask_permutex2var_pd) (s1.x, mask, ind.x, s2.x);
+  res3.x =
+    INTRINSIC (_maskz_permutex2var_pd) (mask, s1.x, ind.x, s2.x);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-1.c
new file mode 100644
index 000000000..f315055da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermt2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermt2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermt2ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __m512i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutex2var_ps (x, y, x);
+  x = _mm512_mask_permutex2var_ps (x, m, y, x);
+  x = _mm512_maskz_permutex2var_ps (m, x, y, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-2.c
new file mode 100644
index 000000000..cd35d1237
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2ps-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (float *dst, float *src1, int *ind, float *src2)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      unsigned long long offset = ind[i] & (SIZE - 1);
+      unsigned long long cond = ind[i] & SIZE;
+
+      dst[i] = cond ? src2[offset] : src1[offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN,) s1, s2, res1, res2, res3;
+  UNION_TYPE (AVX512F_LEN, i_d) ind;
+  float res_ref[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      ind.a[i] = 17 * (i << 1);
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 22.5 * i;
+
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (res_ref, s1.a, ind.a, s2.a);
+
+  res1.x = INTRINSIC (_permutex2var_ps) (s1.x, ind.x, s2.x);
+  res2.x = INTRINSIC (_mask_permutex2var_ps) (s1.x, mask, ind.x, s2.x);
+  res3.x =
+    INTRINSIC (_maskz_permutex2var_ps) (mask, s1.x, ind.x, s2.x);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO ()(res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-1.c
new file mode 100644
index 000000000..65f4afb04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpermt2q\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpermt2q\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpermt2q\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_permutex2var_epi64 (x, x, x);
+  x = _mm512_mask_permutex2var_epi64 (x, m, x, x);
+  x = _mm512_maskz_permutex2var_epi64 (m, x, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-2.c
new file mode 100644
index 000000000..5f449adec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpermt2q-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "math.h"
+#include "values.h"
+
+static void
+CALC (long long *dst, long long *src1, long long *ind, long long *src2)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      unsigned long long offset = ind[i] & (SIZE - 1);
+      unsigned long long cond = ind[i] & SIZE;
+
+      dst[i] = cond ? src2[offset] : src1[offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) s1, s2, res1, res2, res3, ind;
+  long long res_ref[SIZE];
+
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      ind.a[i] = 17 * (i << 1);
+      s1.a[i] = DEFAULT_VALUE;
+      s2.a[i] = 34 * i;
+
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  CALC (res_ref, s1.a, ind.a, s2.a);
+
+  res1.x = INTRINSIC (_permutex2var_epi64) (s1.x, ind.x, s2.x);
+  res2.x =
+    INTRINSIC (_mask_permutex2var_epi64) (s1.x, mask, ind.x, s2.x);
+  res3.x =
+    INTRINSIC (_maskz_permutex2var_epi64) (mask, s1.x, ind.x, s2.x);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandd-1.c
new file mode 100644
index 000000000..c70a2abc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandd-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpexpandd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vpexpandd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+
+#include <immintrin.h>
+
+int *p;
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_expand_epi32 (x, m, x);
+  x = _mm512_maskz_expand_epi32 (m, x);
+
+  x = _mm512_mask_expandloadu_epi32 (x, m, p);
+  x = _mm512_maskz_expandloadu_epi32 (m, p);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandd-2.c
new file mode 100644
index 000000000..31b3b5a05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandd-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s, int *r, MASK_TYPE mask)
+{
+  int i, k;
+
+  for (i = 0, k = 0; i < SIZE; i++)
+    {
+      if (mask & (1 << i))
+	r[i] = s[k++];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  int s2[SIZE];
+  int res_ref1[SIZE];
+  int res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 12345 * (i + 200) * sign;
+      s2[i] = 67890 * (i + 300) * sign;
+      res1.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_mask_expand_epi32) (res1.x, mask, s1.x);
+  res2.x = INTRINSIC (_maskz_expand_epi32) (mask, s1.x);
+  res3.x = INTRINSIC (_mask_expandloadu_epi32) (res3.x, mask, s2);
+  res4.x = INTRINSIC (_maskz_expandloadu_epi32) (mask, s2);
+
+  CALC (s1.a, res_ref1, mask);
+  CALC (s2, res_ref2, mask);
+
+  MASK_MERGE (i_d) (res_ref1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref1))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref1))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref2))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res4, res_ref2))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandq-1.c
new file mode 100644
index 000000000..fc477f209
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandq-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpexpandq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vpexpandq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+
+#include <immintrin.h>
+
+long long *p;
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mask_expand_epi64 (x, m, x);
+  x = _mm512_maskz_expand_epi64 (m, x);
+
+  x = _mm512_mask_expandloadu_epi64 (x, m, p);
+  x = _mm512_maskz_expandloadu_epi64 (m, p);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandq-2.c
new file mode 100644
index 000000000..f72799c57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpexpandq-2.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *s, long long *r, MASK_TYPE mask)
+{
+  int i, k;
+
+  for (i = 0, k = 0; i < SIZE; i++)
+    {
+      if (mask & (1 << i))
+	r[i] = s[k++];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  long long s2[SIZE];
+  long long res_ref1[SIZE];
+  long long res_ref2[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 12345 * (i + 200) * sign;
+      s2[i] = 67890 * (i + 300) * sign;
+      res1.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_mask_expand_epi64) (res1.x, mask, s1.x);
+  res2.x = INTRINSIC (_maskz_expand_epi64) (mask, s1.x);
+  res3.x = INTRINSIC (_mask_expandloadu_epi64) (res3.x, mask, s2);
+  res4.x = INTRINSIC (_maskz_expandloadu_epi64) (mask, s2);
+
+  CALC (s1.a, res_ref1, mask);
+  CALC (s2, res_ref2, mask);
+
+  MASK_MERGE (i_q) (res_ref1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref1))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref1, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref1))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref2))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref2, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res4, res_ref2))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsd-1.c
new file mode 100644
index 000000000..2c88e92bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmaxsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpmaxsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmaxsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_max_epi32 (x, x);
+  x = _mm512_mask_max_epi32 (x, m, x, x);
+  x = _mm512_maskz_max_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsd-2.c
new file mode 100644
index 000000000..78c5511a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsd-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+
+CALC (int *src1, int *src2, int *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] > src2[i] ? src1[i] : src2[i];
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] =  i * sign;
+      src2.a[i] = (i + 2000) * sign;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_max_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_max_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_max_epi32) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsq-1.c
new file mode 100644
index 000000000..e15fa2ab3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmaxsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpmaxsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmaxsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_max_epi64 (x, x);
+  x = _mm512_mask_max_epi64 (x, m, x, x);
+  x = _mm512_maskz_max_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsq-2.c
new file mode 100644
index 000000000..10bcd8230
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxsq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+
+CALC (long long *src1, long long *src2, long long *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] > src2[i] ? src1[i] : src2[i];
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] =  i * sign;
+      src2.a[i] = (i + 2000) * sign;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_max_epi64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_max_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_max_epi64) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxud-1.c
new file mode 100644
index 000000000..321992ac1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxud-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmaxud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpmaxud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmaxud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_max_epu32 (x, x);
+  x = _mm512_mask_max_epu32 (x, m, x, x);
+  x = _mm512_maskz_max_epu32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxud-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxud-2.c
new file mode 100644
index 000000000..b014be862
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxud-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+
+CALC (unsigned *src1, unsigned *src2,
+      unsigned *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] > src2[i] ? src1[i] : src2[i];
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] =  i;
+      src2.a[i] = (i + 2000);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_max_epu32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_max_epu32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_max_epu32) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxuq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxuq-1.c
new file mode 100644
index 000000000..2cf8b4cc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxuq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmaxuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpmaxuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmaxuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_max_epu64 (x, x);
+  x = _mm512_mask_max_epu64 (x, m, x, x);
+  x = _mm512_maskz_max_epu64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxuq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxuq-2.c
new file mode 100644
index 000000000..e2daacd39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmaxuq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+
+CALC (unsigned long long *src1, unsigned long long *src2,
+    unsigned long long *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] > src2[i] ? src1[i] : src2[i];
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned long long res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] =  i;
+      src2.a[i] = (i + 2000);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_max_epu64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_max_epu64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_max_epu64) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsd-1.c
new file mode 100644
index 000000000..2beffc6e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpminsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpminsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpminsd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_min_epi32 (x, x);
+  x = _mm512_mask_min_epi32 (x, m, x, x);
+  x = _mm512_maskz_min_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsd-2.c
new file mode 100644
index 000000000..1a6b82bfd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsd-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+
+CALC (int *src1, int *src2, int *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] < src2[i] ? src1[i] : src2[i];
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] =  i * sign;
+      src2.a[i] = (i + 2000) * sign;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_min_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_min_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_min_epi32) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsq-1.c
new file mode 100644
index 000000000..8270307fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpminsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpminsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpminsq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_min_epi64 (x, x);
+  x = _mm512_mask_min_epi64 (x, m, x, x);
+  x = _mm512_maskz_min_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsq-2.c
new file mode 100644
index 000000000..f646489ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminsq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+
+CALC (long long *src1, long long *src2, long long *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] < src2[i] ? src1[i] : src2[i];
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] =  i * sign;
+      src2.a[i] = (i + 2000) * sign;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_min_epi64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_min_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_min_epi64) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminud-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminud-1.c
new file mode 100644
index 000000000..6cbb9d631
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminud-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpminud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpminud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpminud\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_min_epu32 (x, x);
+  x = _mm512_mask_min_epu32 (x, m, x, x);
+  x = _mm512_maskz_min_epu32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminud-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminud-2.c
new file mode 100644
index 000000000..17aac43a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminud-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+
+CALC (unsigned *src1, unsigned *src2,
+      unsigned *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] < src2[i] ? src1[i] : src2[i];
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i * i;
+      src2.a[i] = i + 20;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_min_epu32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_min_epu32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_min_epu32) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminuq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminuq-1.c
new file mode 100644
index 000000000..816c11bcc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminuq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpminuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpminuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpminuq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_min_epu64 (x, x);
+  x = _mm512_mask_min_epu64 (x, m, x, x);
+  x = _mm512_maskz_min_epu64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminuq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminuq-2.c
new file mode 100644
index 000000000..4c27977ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpminuq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+
+CALC (unsigned long long *src1, unsigned long long *src2,
+    unsigned long long *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] < src2[i] ? src1[i] : src2[i];
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned long long res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] =  i;
+      src2.a[i] = (i + 2000);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_min_epu64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_min_epu64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_min_epu64) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdb-1.c
new file mode 100644
index 000000000..5f1190399
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdb-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovdb\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi32_epi8 (s);
+  res = _mm512_mask_cvtepi32_epi8 (res, m, s);
+  res = _mm512_maskz_cvtepi32_epi8 (m, s);
+  _mm512_mask_cvtepi32_storeu_epi8 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdb-2.c
new file mode 100644
index 000000000..cc63f4816
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdb-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (char *r, int *s)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    {
+      r[i] = (i < SIZE) ? (char) s[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_b) res1, res2, res3;
+  char res4[16];
+  UNION_TYPE (AVX512F_LEN, i_d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  char res_ref[16];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepi32_epi8) (src.x);
+  res2.x = INTRINSIC (_mask_cvtepi32_epi8) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtepi32_epi8) (mask, src.x);
+  INTRINSIC (_mask_cvtepi32_storeu_epi8) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (128, i_b) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res2, res_ref))
+    abort ();
+
+  if (checkVc (res4, res_ref, 16))
+    abort ();
+
+  MASK_ZERO (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdw-1.c
new file mode 100644
index 000000000..a4652a675
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdw-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovdw\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m256i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi32_epi16 (s);
+  res = _mm512_mask_cvtepi32_epi16 (res, m, s);
+  res = _mm512_maskz_cvtepi32_epi16 (m, s);
+  _mm512_mask_cvtepi32_storeu_epi16 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdw-2.c
new file mode 100644
index 000000000..43fe8cb16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovdw-2.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#define SIZE_HALF (AVX512F_LEN_HALF / 16)
+
+CALC (short *r, int *s)
+{
+  int i;
+  for (i = 0; i < SIZE_HALF; i++)
+    {
+      r[i] = (i < SIZE) ? (short) s[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN_HALF, i_w) res1, res2, res3;
+  short res4[SIZE_HALF];
+  UNION_TYPE (AVX512F_LEN, i_d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  short res_ref[SIZE_HALF];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepi32_epi16) (src.x);
+  res2.x = INTRINSIC (_mask_cvtepi32_epi16) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtepi32_epi16) (mask, src.x);
+  INTRINSIC (_mask_cvtepi32_storeu_epi16) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res2, res_ref))
+    abort ();
+
+  if (checkVs (res4, res_ref, SIZE_HALF))
+    abort ();
+
+  MASK_ZERO (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqb-1.c
new file mode 100644
index 000000000..76b6ca507
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqb-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovqb\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi64_epi8 (s);
+  res = _mm512_mask_cvtepi64_epi8 (res, m, s);
+  res = _mm512_maskz_cvtepi64_epi8 (m, s);
+  _mm512_mask_cvtepi64_storeu_epi8 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqb-2.c
new file mode 100644
index 000000000..1b0fbbb3d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqb-2.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (char *r, long long *s, int mem)
+{
+  int i;
+  /* Don't zero out upper half if destination is memory.  */
+  int len = mem ? 8 : 16;
+  for (i = 0; i < len; i++)
+    {
+      r[i] = (i < SIZE) ? (char) s[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_b) res1, res2, res3;
+  char res4[16];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  char res_ref[16];
+  char res_ref2[16];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  for (i = SIZE; i < 16; i++)
+    {
+      /* To check that memory is not touched.  */
+      res4[i] = DEFAULT_VALUE * 2;
+      res_ref2[i] = DEFAULT_VALUE * 2;
+    }
+
+  res1.x = INTRINSIC (_cvtepi64_epi8) (src.x);
+  res2.x = INTRINSIC (_mask_cvtepi64_epi8) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtepi64_epi8) (mask, src.x);
+
+  CALC (res_ref, src.a, 0);
+
+  if (UNION_CHECK (128, i_b) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res3, res_ref))
+    abort ();
+
+
+  INTRINSIC (_mask_cvtepi64_storeu_epi8) (res4, mask, src.x);
+
+  CALC (res_ref2, src.a, 1);
+  MASK_MERGE (i_b) (res_ref2, mask, SIZE);
+
+  if (checkVc (res4, res_ref2, 16))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqd-1.c
new file mode 100644
index 000000000..4055bf8ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqd-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovqd\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m256i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi64_epi32 (s);
+  res = _mm512_mask_cvtepi64_epi32 (res, m, s);
+  res = _mm512_maskz_cvtepi64_epi32 (m, s);
+  _mm512_mask_cvtepi64_storeu_epi32 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqd-2.c
new file mode 100644
index 000000000..db5054b93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqd-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#define SIZE_HALF (AVX512F_LEN_HALF / 32)
+
+CALC (int *r, long long *s)
+{
+  int i;
+  for (i = 0; i < SIZE_HALF; i++)
+    {
+      r[i] = (i < SIZE) ? (int) s[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) res1, res2, res3, res5;
+  int res4[SIZE_HALF];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE_HALF];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepi64_epi32) (src.x);
+  res2.x = INTRINSIC (_mask_cvtepi64_epi32) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtepi64_epi32) (mask, src.x);
+  INTRINSIC (_mask_cvtepi64_storeu_epi32) (res4, mask, src.x);
+
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res2, res_ref))
+    abort ();
+
+  if (checkVi (res4, res_ref, SIZE_HALF))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqw-1.c
new file mode 100644
index 000000000..e63136364
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqw-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovqw\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi64_epi16 (s);
+  res = _mm512_mask_cvtepi64_epi16 (res, m, s);
+  res = _mm512_maskz_cvtepi64_epi16 (m, s);
+  _mm512_mask_cvtepi64_storeu_epi16 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqw-2.c
new file mode 100644
index 000000000..9bdd6e10d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovqw-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (short *r, long long *s)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    {
+      r[i] = (i < SIZE) ? (short) s[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_w) res1, res2, res3;
+  short res4[8];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  short res_ref[8];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepi64_epi16) (src.x);
+  res2.x = INTRINSIC (_mask_cvtepi64_epi16) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtepi64_epi16) (mask, src.x);
+  INTRINSIC (_mask_cvtepi64_storeu_epi16) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (128, i_w) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_w) (res2, res_ref))
+    abort ();
+
+  if (checkVs (res4, res_ref, 8))
+    abort ();
+
+  MASK_ZERO (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_w) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdb-1.c
new file mode 100644
index 000000000..1b68d9ca7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdb-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsdb\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovsdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtsepi32_epi8 (s);
+  res = _mm512_mask_cvtsepi32_epi8 (res, m, s);
+  res = _mm512_maskz_cvtsepi32_epi8 (m, s);
+  _mm512_mask_cvtsepi32_storeu_epi8 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdb-2.c
new file mode 100644
index 000000000..4ac69b517
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdb-2.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include <limits.h>
+
+CALC (char *r, int *s)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    {
+      if (s[i] < CHAR_MIN)
+	r[i] = CHAR_MIN;
+      else if (s[i] > CHAR_MAX)
+	r[i] = CHAR_MAX;
+      else
+	r[i] = s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_b) res1, res2, res3;
+  char res4[16];
+  UNION_TYPE (AVX512F_LEN, i_d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  char res_ref[16];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtsepi32_epi8) (src.x);
+  res2.x = INTRINSIC (_mask_cvtsepi32_epi8) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtsepi32_epi8) (mask, src.x);
+  INTRINSIC (_mask_cvtsepi32_storeu_epi8) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (128, i_b) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res2, res_ref))
+    abort ();
+
+  if (checkVc (res4, res_ref, 16))
+    abort ();
+
+  MASK_ZERO (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdw-1.c
new file mode 100644
index 000000000..ee10c12f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdw-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsdw\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovsdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m256i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtsepi32_epi16 (s);
+  res = _mm512_mask_cvtsepi32_epi16 (res, m, s);
+  res = _mm512_maskz_cvtsepi32_epi16 (m, s);
+  _mm512_mask_cvtsepi32_storeu_epi16 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdw-2.c
new file mode 100644
index 000000000..98d8745d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsdw-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#define SIZE_HALF (AVX512F_LEN_HALF / 16)
+#include <limits.h>
+
+CALC (short *r, int *s)
+{
+  int i;
+  for (i = 0; i < SIZE_HALF; i++)
+    {
+      if (s[i] < SHRT_MIN)
+	r[i] = SHRT_MIN;
+      else if (s[i] > SHRT_MAX)
+	r[i] = SHRT_MAX;
+      else
+	r[i] = s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN_HALF, i_w) res1, res2, res3;
+  short res4[SIZE_HALF];
+  UNION_TYPE (AVX512F_LEN, i_d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  short res_ref[SIZE_HALF];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtsepi32_epi16) (src.x);
+  res2.x = INTRINSIC (_mask_cvtsepi32_epi16) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtsepi32_epi16) (mask, src.x);
+  INTRINSIC (_mask_cvtsepi32_storeu_epi16) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res2, res_ref))
+    abort ();
+
+  if (checkVs (res4, res_ref, SIZE_HALF))
+    abort ();
+
+  MASK_ZERO (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqb-1.c
new file mode 100644
index 000000000..9b2e00449
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqb-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsqb\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovsqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtsepi64_epi8 (s);
+  res = _mm512_mask_cvtsepi64_epi8 (res, m, s);
+  res = _mm512_maskz_cvtsepi64_epi8 (m, s);
+  _mm512_mask_cvtsepi64_storeu_epi8 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqb-2.c
new file mode 100644
index 000000000..0fb7883de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqb-2.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include <limits.h>
+
+CALC (char *r, long long *s, int mem)
+{
+  int i;
+  int len = mem ? 8 : 16;
+  for (i = 0; i < len; i++)
+    {
+      if (s[i] < CHAR_MIN)
+	r[i] = CHAR_MIN;
+      else if (s[i] > CHAR_MAX)
+	r[i] = CHAR_MAX;
+      else
+	r[i] = s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_b) res1, res2, res3;
+  char res4[16];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  char res_ref[16];
+  char res_ref2[16];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  for (i = SIZE; i < 16; i++)
+    {
+      res_ref2[i] = DEFAULT_VALUE * 2;
+      res4[i] = DEFAULT_VALUE * 2;
+    }
+
+  res1.x = INTRINSIC (_cvtsepi64_epi8) (src.x);
+  res2.x = INTRINSIC (_mask_cvtsepi64_epi8) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtsepi64_epi8) (mask, src.x);
+
+  CALC (res_ref, src.a, 0);
+
+  if (UNION_CHECK (128, i_b) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res3, res_ref))
+    abort ();
+
+  INTRINSIC (_mask_cvtsepi64_storeu_epi8) (res4, mask, src.x);
+
+  CALC (res_ref2, src.a, 1);
+  MASK_MERGE (i_b) (res_ref2, mask, SIZE);
+
+  if (checkVc (res4, res_ref2, 16))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqd-1.c
new file mode 100644
index 000000000..ba6198935
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqd-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsqd\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovsqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m256i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtsepi64_epi32 (s);
+  res = _mm512_mask_cvtsepi64_epi32 (res, m, s);
+  res = _mm512_maskz_cvtsepi64_epi32 (m, s);
+  _mm512_mask_cvtsepi64_storeu_epi32 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqd-2.c
new file mode 100644
index 000000000..3230528a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqd-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#define SIZE_HALF (AVX512F_LEN_HALF / 32)
+#include <limits.h>
+
+CALC (int *r, long long *s)
+{
+  int i;
+  for (i = 0; i < SIZE_HALF; i++)
+    {
+      if (s[i] < INT_MIN)
+	r[i] = INT_MIN;
+      else if (s[i] > INT_MAX)
+	r[i] = INT_MAX;
+      else
+	r[i] = s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) res1, res2, res3;
+  int res4[SIZE_HALF];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE_HALF];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtsepi64_epi32) (src.x);
+  res2.x = INTRINSIC (_mask_cvtsepi64_epi32) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtsepi64_epi32) (mask, src.x);
+  INTRINSIC (_mask_cvtsepi64_storeu_epi32) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res2, res_ref))
+    abort ();
+
+  if (checkVi (res4, res_ref, SIZE_HALF))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqw-1.c
new file mode 100644
index 000000000..a47e76741
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqw-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsqw\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovsqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtsepi64_epi16 (s);
+  res = _mm512_mask_cvtsepi64_epi16 (res, m, s);
+  res = _mm512_maskz_cvtsepi64_epi16 (m, s);
+  _mm512_mask_cvtsepi64_storeu_epi16 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqw-2.c
new file mode 100644
index 000000000..25e54a73d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsqw-2.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include <limits.h>
+
+CALC (short *r, long long *s)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    {
+      if (s[i] < SHRT_MIN)
+	r[i] = SHRT_MIN;
+      else if (s[i] > SHRT_MAX)
+	r[i] = SHRT_MAX;
+      else
+	r[i] = s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_w) res1, res2, res3;
+  short res4[8];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  short res_ref[8];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i * sign;
+      sign = sign * -1;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtsepi64_epi16) (src.x);
+  res2.x = INTRINSIC (_mask_cvtsepi64_epi16) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtsepi64_epi16) (mask, src.x);
+  INTRINSIC (_mask_cvtsepi64_storeu_epi16) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (128, i_w) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_w) (res2, res_ref))
+    abort ();
+
+  if (checkVs (res4, res_ref, 8))
+    abort ();
+
+  MASK_ZERO (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_w) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbd-1.c
new file mode 100644
index 000000000..18a34ae01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsxbd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxbd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxbd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128i s;
+volatile __m512i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi8_epi32 (s);
+  res = _mm512_mask_cvtepi8_epi32 (res, m, s);
+  res = _mm512_maskz_cvtepi8_epi32 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbd-2.c
new file mode 100644
index 000000000..3bfb6ab75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (char *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (int) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  union128i_b s;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 8 * i * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_cvtepi8_epi32) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepi8_epi32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepi8_epi32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbq-1.c
new file mode 100644
index 000000000..e902b6e76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsxbq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxbq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxbq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128i s;
+volatile __m512i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi8_epi64 (s);
+  res = _mm512_mask_cvtepi8_epi64 (res, m, s);
+  res = _mm512_maskz_cvtepi8_epi64 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbq-2.c
new file mode 100644
index 000000000..540d21819
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxbq-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (char *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (long long int) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  union128i_b s;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 8 * i * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_cvtepi8_epi64) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepi8_epi64) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepi8_epi64) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxdq-1.c
new file mode 100644
index 000000000..265c9fe32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxdq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i s;
+volatile __m512i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi32_epi64 (s);
+  res = _mm512_mask_cvtepi32_epi64 (res, m, s);
+  res = _mm512_maskz_cvtepi32_epi64 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxdq-2.c
new file mode 100644
index 000000000..f1e131e00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxdq-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (long long int) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) s;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 2000 * i * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_cvtepi32_epi64) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepi32_epi64) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepi32_epi64) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwd-1.c
new file mode 100644
index 000000000..cdcba564e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i s;
+volatile __m512i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi16_epi32 (s);
+  res = _mm512_mask_cvtepi16_epi32 (res, m, s);
+  res = _mm512_maskz_cvtepi16_epi32 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwd-2.c
new file mode 100644
index 000000000..04b43a6e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (short *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (int) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN_HALF, i_w) s;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 2000 * i * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_cvtepi16_epi32) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepi16_epi32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepi16_epi32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwq-1.c
new file mode 100644
index 000000000..28d6b17ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovsxwq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxwq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovsxwq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128i s;
+volatile __m512i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepi16_epi64 (s);
+  res = _mm512_mask_cvtepi16_epi64 (res, m, s);
+  res = _mm512_maskz_cvtepi16_epi64 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwq-2.c
new file mode 100644
index 000000000..9e6832d86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovsxwq-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (short *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (long long int) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  union128i_w s;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 2000 * i * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_cvtepi16_epi64) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepi16_epi64) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepi16_epi64) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdb-1.c
new file mode 100644
index 000000000..bc0d3d504
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdb-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovusdb\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovusdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusdb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtusepi32_epi8 (s);
+  res = _mm512_mask_cvtusepi32_epi8 (res, m, s);
+  res = _mm512_maskz_cvtusepi32_epi8 (m, s);
+  _mm512_mask_cvtusepi32_storeu_epi8 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdb-2.c
new file mode 100644
index 000000000..f13bb95b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdb-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include <limits.h>
+
+CALC (unsigned char *r, unsigned int *s)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    {
+      r[i] = (s[i] > UCHAR_MAX) ? UCHAR_MAX : s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_b) res1, res2, res3;
+  unsigned char res4[16];
+  UNION_TYPE (AVX512F_LEN, i_d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned char res_ref[16];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtusepi32_epi8) (src.x);
+  res2.x = INTRINSIC (_mask_cvtusepi32_epi8) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtusepi32_epi8) (mask, src.x);
+  INTRINSIC (_mask_cvtusepi32_storeu_epi8) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (128, i_b) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res2, res_ref))
+    abort ();
+
+  if (checkVc (res4, res_ref, 16))
+    abort ();
+
+  MASK_ZERO (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdw-1.c
new file mode 100644
index 000000000..ea987eb2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdw-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovusdw\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovusdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusdw\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m256i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtusepi32_epi16 (s);
+  res = _mm512_mask_cvtusepi32_epi16 (res, m, s);
+  res = _mm512_maskz_cvtusepi32_epi16 (m, s);
+  _mm512_mask_cvtusepi32_storeu_epi16 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdw-2.c
new file mode 100644
index 000000000..c33a10b71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusdw-2.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#define SIZE_HALF (AVX512F_LEN_HALF / 16)
+#include <limits.h>
+
+CALC (unsigned short *r, unsigned int *s)
+{
+  int i;
+  for (i = 0; i < SIZE_HALF; i++)
+    {
+      r[i] = (s[i] > USHRT_MAX) ? USHRT_MAX : s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN_HALF, i_w) res1, res2, res3;
+  unsigned short res4[SIZE_HALF];
+  UNION_TYPE (AVX512F_LEN, i_d) src;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned short res_ref[SIZE_HALF];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtusepi32_epi16) (src.x);
+  res2.x = INTRINSIC (_mask_cvtusepi32_epi16) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtusepi32_epi16) (mask, src.x);
+  INTRINSIC (_mask_cvtusepi32_storeu_epi16) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res2, res_ref))
+    abort ();
+
+  if (checkVs (res4, res_ref, SIZE_HALF))
+    abort ();
+
+  MASK_ZERO (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_w) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqb-1.c
new file mode 100644
index 000000000..805b72403
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqb-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovusqb\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovusqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusqb\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtusepi64_epi8 (s);
+  res = _mm512_mask_cvtusepi64_epi8 (res, m, s);
+  res = _mm512_maskz_cvtusepi64_epi8 (m, s);
+  _mm512_mask_cvtusepi64_storeu_epi8 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqb-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqb-2.c
new file mode 100644
index 000000000..43fb9d275
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqb-2.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include <limits.h>
+
+CALC (unsigned char *r, unsigned long long *s, int mem)
+{
+  int i;
+  int len = mem ? 8 : 16;
+  for (i = 0; i < len; i++)
+    {
+      r[i] = (s[i] > UCHAR_MAX) ? UCHAR_MAX : s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_b) res1, res2, res3;
+  unsigned char res4[16];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned char res_ref[16];
+  unsigned char res_ref2[16];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  for (i = SIZE; i < 16; i++)
+    {
+      res4[i] = DEFAULT_VALUE * 2;
+      res_ref2[i] = DEFAULT_VALUE * 2;
+    }
+
+  res1.x = INTRINSIC (_cvtusepi64_epi8) (src.x);
+  res2.x = INTRINSIC (_mask_cvtusepi64_epi8) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtusepi64_epi8) (mask, src.x);
+
+  CALC (res_ref, src.a, 0);
+
+  if (UNION_CHECK (128, i_b) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_b) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_b) (res3, res_ref))
+    abort ();
+
+  INTRINSIC (_mask_cvtusepi64_storeu_epi8) (res4, mask, src.x);
+
+  CALC (res_ref2, src.a, 1);
+  MASK_MERGE (i_b) (res_ref2, mask, SIZE);
+
+  if (checkVc (res4, res_ref2, 16))
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqd-1.c
new file mode 100644
index 000000000..11d7ccbcf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqd-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovusqd\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovusqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusqd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m256i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtusepi64_epi32 (s);
+  res = _mm512_mask_cvtusepi64_epi32 (res, m, s);
+  res = _mm512_maskz_cvtusepi64_epi32 (m, s);
+  _mm512_mask_cvtusepi64_storeu_epi32 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqd-2.c
new file mode 100644
index 000000000..79613b36a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqd-2.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#define SIZE_HALF (AVX512F_LEN_HALF / 32)
+#include <limits.h>
+
+CALC (unsigned int *r, unsigned long long *s)
+{
+  int i;
+  for (i = 0; i < SIZE_HALF; i++)
+    {
+      r[i] = (s[i] > UINT_MAX) ? UINT_MAX : s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) res1, res2, res3;
+  unsigned int res4[SIZE_HALF];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned int res_ref[SIZE_HALF];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtusepi64_epi32) (src.x);
+  res2.x = INTRINSIC (_mask_cvtusepi64_epi32) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtusepi64_epi32) (mask, src.x);
+  INTRINSIC (_mask_cvtusepi64_storeu_epi32) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res2, res_ref))
+    abort ();
+
+  if (checkVi (res4, res_ref, SIZE_HALF))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN_HALF, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqw-1.c
new file mode 100644
index 000000000..1f6eb2411
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqw-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovusqw\[ \\t\]+\[^\n\]*" 4 } } */
+/* { dg-final { scan-assembler-times "vpmovusqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovusqw\[ \\t\]+\[^\n\]*%xmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i s;
+volatile __m128i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtusepi64_epi16 (s);
+  res = _mm512_mask_cvtusepi64_epi16 (res, m, s);
+  res = _mm512_maskz_cvtusepi64_epi16 (m, s);
+  _mm512_mask_cvtusepi64_storeu_epi16 ((void *) &res, m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqw-2.c
new file mode 100644
index 000000000..f905eed83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovusqw-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include <limits.h>
+
+CALC (unsigned short *r, unsigned long long *s)
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    {
+      r[i] = (s[i] > USHRT_MAX) ? USHRT_MAX : s[i];
+      r[i] = (i < SIZE) ? r[i] : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (128, i_w) res1, res2, res3;
+  unsigned short res4[8];
+  UNION_TYPE (AVX512F_LEN, i_q) src;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned short res_ref[8];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src.a[i] = 1 + 34 * i;
+      res2.a[i] = DEFAULT_VALUE;
+      res4[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtusepi64_epi16) (src.x);
+  res2.x = INTRINSIC (_mask_cvtusepi64_epi16) (res2.x, mask, src.x);
+  res3.x = INTRINSIC (_maskz_cvtusepi64_epi16) (mask, src.x);
+  INTRINSIC (_mask_cvtusepi64_storeu_epi16) (res4, mask, src.x);
+
+  CALC (res_ref, src.a);
+
+  if (UNION_CHECK (128, i_w) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_w) (res2, res_ref))
+    abort ();
+
+  if (checkVs (res4, res_ref, 8))
+    abort ();
+
+  MASK_ZERO (i_w) (res_ref, mask, SIZE);
+  if (UNION_CHECK (128, i_w) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbd-1.c
new file mode 100644
index 000000000..6b4976dca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovzxbd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxbd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxbd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128i s;
+volatile __m512i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepu8_epi32 (s);
+  res = _mm512_mask_cvtepu8_epi32 (res, m, s);
+  res = _mm512_maskz_cvtepu8_epi32 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbd-2.c
new file mode 100644
index 000000000..eb2b9509f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned char *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  union128i_b s;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 16 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepu8_epi32) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepu8_epi32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepu8_epi32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbq-1.c
new file mode 100644
index 000000000..758e06654
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovzxbq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxbq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxbq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128i s;
+volatile __m512i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepu8_epi64 (s);
+  res = _mm512_mask_cvtepu8_epi64 (res, m, s);
+  res = _mm512_maskz_cvtepu8_epi64 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbq-2.c
new file mode 100644
index 000000000..e1629951a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxbq-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned char *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  union128i_b s;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long int res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 16 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepu8_epi64) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepu8_epi64) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepu8_epi64) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxdq-1.c
new file mode 100644
index 000000000..1a8c37a13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxdq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovzxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxdq\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i s;
+volatile __m512i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepu32_epi64 (s);
+  res = _mm512_mask_cvtepu32_epi64 (res, m, s);
+  res = _mm512_maskz_cvtepu32_epi64 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxdq-2.c
new file mode 100644
index 000000000..69c352279
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxdq-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN_HALF, i_d) s;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long int res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 2000 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepu32_epi64) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepu32_epi64) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepu32_epi64) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwd-1.c
new file mode 100644
index 000000000..6f9555854
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovzxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxwd\[ \\t\]+\[^\n\]*%ymm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i s;
+volatile __m512i res;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepu16_epi32 (s);
+  res = _mm512_mask_cvtepu16_epi32 (res, m, s);
+  res = _mm512_maskz_cvtepu16_epi32 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwd-2.c
new file mode 100644
index 000000000..ea5331433
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned short *s, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN_HALF, i_w) s;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 2000 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepu16_epi32) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepu16_epi32) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepu16_epi32) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwq-1.c
new file mode 100644
index 000000000..13f893e63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmovzxwq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxwq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmovzxwq\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128i s;
+volatile __m512i res;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm512_cvtepu16_epi64 (s);
+  res = _mm512_mask_cvtepu16_epi64 (res, m, s);
+  res = _mm512_maskz_cvtepu16_epi64 (m, s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwq-2.c
new file mode 100644
index 000000000..9e0fc7668
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmovzxwq-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned short *s, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = (long long int) s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  union128i_w s;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long int res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 2000 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_cvtepu16_epi64) (s.x);
+  res2.x = INTRINSIC (_mask_cvtepu16_epi64) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_cvtepu16_epi64) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuldq-1.c
new file mode 100644
index 000000000..091de8c39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuldq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmuldq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpmuldq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmuldq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}{z}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mul_epi32 (x, x);
+  x = _mm512_mask_mul_epi32 (x, m, x, x);
+  x = _mm512_maskz_mul_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuldq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuldq-2.c
new file mode 100644
index 000000000..83058dcf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuldq-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#define DST_SIZE (AVX512F_LEN / 64)
+
+static void
+CALC (int *s1, int *s2, long long int *r)
+{
+  int i;
+
+  for (i = 0; i < DST_SIZE; i++)
+    r[i] = s1[i * 2] * s2[i * 2];
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[DST_SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s1.a[i] = i * 20;
+      s2.a[i] = i + 20;
+    }
+
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  CALC (s1.a, s2.a, res_ref);
+
+  res1.x = INTRINSIC (_mul_epi32) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_mul_epi32) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_mul_epi32) (mask, s1.x, s2.x);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmulld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmulld-1.c
new file mode 100644
index 000000000..d1d77d2e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmulld-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmulld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpmulld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmulld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}{z}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 mx;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mullo_epi32 (x, x);
+  x = _mm512_mask_mullo_epi32 (x, mx, x, x);
+  x = _mm512_maskz_mullo_epi32 (mx, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmulld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmulld-2.c
new file mode 100644
index 000000000..a08120c43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmulld-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+
+static void
+CALC (int *src1, int *src2, int *dst)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    dst[i] = src1[i] * src2[i];
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int dst_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i + 50;
+      src2.a[i] = i + 100;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_mullo_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_mullo_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_mullo_epi32) (mask, src1.x, src2.x);
+
+  CALC (src1.a, src2.a, dst_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, dst_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (dst_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, dst_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (dst_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, dst_ref))
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuludq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuludq-1.c
new file mode 100644
index 000000000..b6fd4daf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuludq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpmuludq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpmuludq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpmuludq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}{z}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_mul_epu32 (x, x);
+  x = _mm512_mask_mul_epu32 (x, m, x, x);
+  x = _mm512_maskz_mul_epu32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuludq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuludq-2.c
new file mode 100644
index 000000000..fc0416b6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpmuludq-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SRC_SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#define DST_SIZE (AVX512F_LEN / 64)
+
+static void
+CALC (unsigned int *s1, unsigned int *s2, unsigned long long *r)
+{
+  int i;
+
+  for (i = 0; i < DST_SIZE; i++)
+    r[i] = s1[i * 2] * s2[i * 2];
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned long long res_ref[DST_SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SRC_SIZE; i++)
+    {
+      s1.a[i] = i * 20;
+      s2.a[i] = i + 20;
+    }
+  for (i = 0; i < DST_SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  CALC (s1.a, s2.a, res_ref);
+
+  res1.x = INTRINSIC (_mul_epu32) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_mul_epu32) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_mul_epu32) (mask, s1.x, s2.x);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, DST_SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpord-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpord-1.c
new file mode 100644
index 000000000..78650751c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpord-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_or_si512 (x, x);
+  x = _mm512_or_epi32 (x, x);
+  x = _mm512_mask_or_epi32 (x, m, x, x);
+  x = _mm512_maskz_or_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpord-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpord-2.c
new file mode 100644
index 000000000..9493aa01f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpord-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s1[i] | s2[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * sign;
+      s2.a[i] = (i + 20) * sign;
+      sign = -sign;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_or_si512) (s1.x, s2.x);
+  res2.x = INTRINSIC (_or_epi32) (s1.x, s2.x);
+  res3.x = INTRINSIC (_mask_or_epi32) (res3.x, mask, s1.x, s2.x);
+  res4.x = INTRINSIC (_maskz_or_epi32) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res4, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vporq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vporq-1.c
new file mode 100644
index 000000000..c6f8bb576
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vporq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vporq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vporq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vporq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_or_epi64 (x, x);
+  x = _mm512_mask_or_epi64 (x, m, x, x);
+  x = _mm512_maskz_or_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vporq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vporq-2.c
new file mode 100644
index 000000000..843ecbd37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vporq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *s1, long long *s2, long long *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s1[i] | s2[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * sign;
+      s2.a[i] = (i + 20) * sign;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_or_epi64) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_or_epi64) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_or_epi64) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+      abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprold-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprold-1.c
new file mode 100644
index 000000000..4a98e1992
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprold-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vprold\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vprold\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vprold\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rol_epi32 (x, 12);
+  x = _mm512_mask_rol_epi32 (x, m, x, 12);
+  x = _mm512_maskz_rol_epi32 (m, x, 12);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprold-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprold-2.c
new file mode 100644
index 000000000..e56115d19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprold-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+#define N 0x5
+
+static void
+CALC (int *s1, int count, int *r)
+{
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s1[i] << count) | (s1[i] >> sizeof (s1[i]) * 8 - count);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 137 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_rol_epi32) (s1.x, N);
+  res2.x = INTRINSIC (_mask_rol_epi32) (res2.x, mask, s1.x, N);
+  res3.x = INTRINSIC (_maskz_rol_epi32) (mask, s1.x, N);
+
+  CALC (s1.a, N, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolq-1.c
new file mode 100644
index 000000000..91b2462ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vprolq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vprolq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vprolq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rol_epi64 (x, 12);
+  x = _mm512_mask_rol_epi64 (x, m, x, 12);
+  x = _mm512_maskz_rol_epi64 (m, x, 12);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolq-2.c
new file mode 100644
index 000000000..116a6aa6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#define N 0x5
+
+static void
+CALC (long long *s1, int count, long long *r)
+{
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s1[i] << count) | (s1[i] >> sizeof (s1[i]) * 8 - count);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 137 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_rol_epi64) (s1.x, N);
+  res2.x = INTRINSIC (_mask_rol_epi64) (res2.x, mask, s1.x, N);
+  res3.x = INTRINSIC (_maskz_rol_epi64) (mask, s1.x, N);
+
+  CALC (s1.a, N, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvd-1.c
new file mode 100644
index 000000000..10331a61d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vprolvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vprolvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vprolvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rolv_epi32 (x, x);
+  x = _mm512_mask_rolv_epi32 (x, m, x, x);
+  x = _mm512_maskz_rolv_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvd-2.c
new file mode 100644
index 000000000..e537ae8f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvd-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s1, int *s2, int *r)
+{
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s1[i] << s2[i]) | (s1[i] >> sizeof (s1[i]) * 8 - s2[i]);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 137 * i;
+      s2.a[i] = (i + 7);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_rolv_epi32) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_rolv_epi32) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_rolv_epi32) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvq-1.c
new file mode 100644
index 000000000..a182a6203
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vprolvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vprolvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vprolvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rolv_epi64 (x, x);
+  x = _mm512_mask_rolv_epi64 (x, m, x, x);
+  x = _mm512_maskz_rolv_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvq-2.c
new file mode 100644
index 000000000..a1c748d50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprolvq-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *s1, long long *s2, long long *r)
+{
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s1[i] << s2[i]) | (s1[i] >> sizeof (s1[i]) * 8 - s2[i]);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 137 * i;
+      s2.a[i] = (i + 7);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_rolv_epi64) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_rolv_epi64) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_rolv_epi64) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprord-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprord-1.c
new file mode 100644
index 000000000..c1cf8a5f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprord-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vprord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vprord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vprord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_ror_epi32 (x, 12);
+  x = _mm512_mask_ror_epi32 (x, m, x, 12);
+  x = _mm512_maskz_ror_epi32 (m, x, 12);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprord-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprord-2.c
new file mode 100644
index 000000000..5223fe0a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprord-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+#define N 0x5
+
+static void
+CALC (int *s1, int count, int *r)
+{
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s1[i] >> count) | (s1[i] << sizeof (s1[i]) * 8 - count);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 137 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_ror_epi32) (s1.x, N);
+  res2.x = INTRINSIC (_mask_ror_epi32) (res2.x, mask, s1.x, N);
+  res3.x = INTRINSIC (_maskz_ror_epi32) (mask, s1.x, N);
+
+  CALC (s1.a, N, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorq-1.c
new file mode 100644
index 000000000..66b9e0391
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vprorq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vprorq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vprorq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_ror_epi64 (x, 12);
+  x = _mm512_mask_ror_epi64 (x, m, x, 12);
+  x = _mm512_maskz_ror_epi64 (m, x, 12);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorq-2.c
new file mode 100644
index 000000000..704b0a50a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+#define N 0x5
+
+static void
+CALC (long long *s1, int count, long long *r)
+{
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s1[i] >> count) | (s1[i] << sizeof (s1[i]) * 8 - count);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 137 * i;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_ror_epi64) (s1.x, N);
+  res2.x = INTRINSIC (_mask_ror_epi64) (res2.x, mask, s1.x, N);
+  res3.x = INTRINSIC (_maskz_ror_epi64) (mask, s1.x, N);
+
+  CALC (s1.a, N, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvd-1.c
new file mode 100644
index 000000000..59f0c95e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvd-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vprorvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rorv_epi32 (x, x);
+  x = _mm512_mask_rorv_epi32 (x, m, x, x);
+  x = _mm512_maskz_rorv_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvd-2.c
new file mode 100644
index 000000000..eaf8df92e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvd-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s1, int *s2, int *r)
+{
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s1[i] >> s2[i]) | (s1[i] << sizeof (s1[i]) * 8 - s2[i]);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 137 * i;
+      s2.a[i] = (i + 7);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_rorv_epi32) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_rorv_epi32) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_rorv_epi32) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvq-1.c
new file mode 100644
index 000000000..31b59b188
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vprorvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vprorvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vprorvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rorv_epi64 (x, x);
+  x = _mm512_mask_rorv_epi64 (x, m, x, x);
+  x = _mm512_maskz_rorv_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvq-2.c
new file mode 100644
index 000000000..035ce9677
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vprorvq-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *s1, long long *s2, long long *r)
+{
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = (s1[i] >> s2[i]) | (s1[i] << sizeof (s1[i]) * 8 - s2[i]);
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  unsigned int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 137 * i;
+      s2.a[i] = (i + 7);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_rorv_epi64) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_rorv_epi64) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_rorv_epi64) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpshufd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpshufd-1.c
new file mode 100644
index 000000000..9b7afc54e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpshufd-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpshufd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpshufd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vpshufd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_shuffle_epi32 (x, _MM_PERM_AADB);
+  x = _mm512_mask_shuffle_epi32 (x, 2, x, _MM_PERM_AADB);
+  x = _mm512_maskz_shuffle_epi32 (2, x, _MM_PERM_AADB);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpshufd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpshufd-2.c
new file mode 100644
index 000000000..a6379c372
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpshufd-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s1, unsigned char imm, int *r)
+{
+  int i, j, offset;
+
+  for (j = 0; j < SIZE / 4; j++)
+    {
+      offset = j * 4;
+      for (i = 0; i < 4; i++)
+	r[i + offset] =
+	  s1[((imm & (0x3 << (2 * i))) >> (2 * i)) + offset];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, res1, res2, res3;
+  int res_ref[SIZE];
+  int i, j, sign = 1;
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (j = 0; j < SIZE; j++)
+    {
+      s1.a[j] = j * i * sign;
+      res1.a[j] = DEFAULT_VALUE;
+      res2.a[j] = DEFAULT_VALUE;
+      res3.a[j] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_shuffle_epi32) (s1.x, 0xec);
+  res2.x = INTRINSIC (_mask_shuffle_epi32) (res2.x, mask, s1.x, 0xec);
+  res3.x = INTRINSIC (_maskz_shuffle_epi32) (mask, s1.x, 0xec);
+
+  CALC (s1.a, 0xec, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslld-1.c
new file mode 100644
index 000000000..a2c3711df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslld-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpslld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpslld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpslld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sll_epi32 (x, y);
+  x = _mm512_mask_sll_epi32 (x, m, x, y);
+  x = _mm512_maskz_sll_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslld-2.c
new file mode 100644
index 000000000..c6c8a9c1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslld-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, long long* s2)
+{
+  int i;
+  int count = s2[0];
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = count < 32 ? (s1[i] << count) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1;
+  UNION_TYPE (128, i_q) src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  long long imm;
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      sign = sign * -1;
+    }
+
+  for (imm = 1; imm <= 33; imm++)
+    {
+      src2.a[0] = imm;
+      for (i = 0; i < SIZE; i++)
+	res2.a[i] = DEFAULT_VALUE;
+
+      res1.x = INTRINSIC (_sll_epi32) (src1.x, src2.x);
+      res2.x = INTRINSIC (_mask_sll_epi32) (res2.x, mask, src1.x, src2.x);
+      res3.x = INTRINSIC (_maskz_sll_epi32) (mask, src1.x, src2.x);
+
+      CALC (res_ref, src1.a, src2.a);
+
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE (i_d) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+	abort ();
+
+      MASK_ZERO (i_d) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslldi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslldi-1.c
new file mode 100644
index 000000000..c81ac9200
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslldi-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpslld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpslld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpslld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+#define y 7
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_slli_epi32 (x, y);
+  x = _mm512_mask_slli_epi32 (x, m, x, y);
+  x = _mm512_maskz_slli_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslldi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslldi-2.c
new file mode 100644
index 000000000..c3bfdd28a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpslldi-2.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, int count)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = count < 32 ? (s1[i] << count) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      sign = sign * -1;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_slli_epi32) (src1.x, 2);
+  res2.x = INTRINSIC (_mask_slli_epi32) (res2.x, mask, src1.x, 2);
+  res3.x = INTRINSIC (_maskz_slli_epi32) (mask, src1.x, 2);
+
+  CALC (res_ref, src1.a, 2);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_slli_epi32) (src1.x, 33);
+  res2.x = INTRINSIC (_mask_slli_epi32) (res2.x, mask, src1.x, 33);
+  res3.x = INTRINSIC (_maskz_slli_epi32) (mask, src1.x, 33);
+
+  CALC (res_ref, src1.a, 33);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllq-1.c
new file mode 100644
index 000000000..491234e88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsllq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsllq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsllq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sll_epi64 (x, y);
+  x = _mm512_mask_sll_epi64 (x, m, x, y);
+  x = _mm512_maskz_sll_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllq-2.c
new file mode 100644
index 000000000..5addaa517
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllq-2.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1,  long long* s2)
+{
+  int i;
+  long long count = s2[0];
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = count < 64 ? (s1[i] << count) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1;
+  UNION_TYPE (128, i_q) src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  long long imm;
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      sign = sign * -1;
+    }
+
+  for (imm = 1; imm <= 65; imm++)
+    {
+      src2.a[0] = imm;
+      for (i = 0; i < SIZE; i++)
+	res2.a[i] = DEFAULT_VALUE;
+
+      res1.x = INTRINSIC (_sll_epi64) (src1.x, src2.x);
+      res2.x = INTRINSIC (_mask_sll_epi64) (res2.x, mask, src1.x, src2.x);
+      res3.x = INTRINSIC (_maskz_sll_epi64) (mask, src1.x, src2.x);
+
+      CALC (res_ref, src1.a, src2.a);
+
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE (i_q) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+	abort ();
+
+      MASK_ZERO (i_q) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllqi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllqi-1.c
new file mode 100644
index 000000000..7e077e41b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllqi-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsllq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsllq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsllq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+#define y 7
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_slli_epi64 (x, y);
+  x = _mm512_mask_slli_epi64 (x, m, x, y);
+  x = _mm512_maskz_slli_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllqi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllqi-2.c
new file mode 100644
index 000000000..e15b324d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllqi-2.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long count)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = count < 64 ? (s1[i] << count) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      sign = sign * -1;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_slli_epi64) (src1.x, 3);
+  res2.x = INTRINSIC (_mask_slli_epi64) (res2.x, mask, src1.x, 3);
+  res3.x = INTRINSIC (_maskz_slli_epi64) (mask, src1.x, 3);
+
+  CALC (res_ref, src1.a, 3);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_slli_epi64) (src1.x, 65);
+  res2.x = INTRINSIC (_mask_slli_epi64) (res2.x, mask, src1.x, 65);
+  res3.x = INTRINSIC (_maskz_slli_epi64) (mask, src1.x, 65);
+
+  CALC (res_ref, src1.a, 65);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvd-1.c
new file mode 100644
index 000000000..0a966af38
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsllvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsllvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsllvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m512i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sllv_epi32 (x, y);
+  x = _mm512_mask_sllv_epi32 (x, m, x, y);
+  x = _mm512_maskz_sllv_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvd-2.c
new file mode 100644
index 000000000..82ff3a652
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned int *r, unsigned int *s1, unsigned int *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s2[i] < 32 ? (s1[i] << s2[i]) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned int res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + 7 * i % 291;
+      src2.a[i] = 1 + 17 * i % 71;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_sllv_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_sllv_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_sllv_epi32) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq-1.c
new file mode 100644
index 000000000..8faeef02a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsllvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsllvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsllvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m512i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sllv_epi64 (x, y);
+  x = _mm512_mask_sllv_epi64 (x, m, x, y);
+  x = _mm512_maskz_sllv_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq-2.c
new file mode 100644
index 000000000..e2b48d7fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned long long *r, unsigned long long *s1,
+      unsigned long long *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s2[i] < 64 ? (s1[i] << s2[i]) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned long long res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + 7 * i % 291;
+      src2.a[i] = 1 + 17 * i % 71;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_sllv_epi64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_sllv_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_sllv_epi64) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq512-1.c
new file mode 100644
index 000000000..e93b8c529
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq512-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vpsllvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sllv_epi64 (x, x);
+}
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq512-2.c
new file mode 100644
index 000000000..0c970dbb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsllvq512-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include <string.h>
+#include "avx512f-check.h"
+
+static void
+compute_psllvq512 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count;
+
+  for (i = 0; i < 8; ++i)
+    {
+      count = s2[i];
+      r[i] = s1[i] << count;
+    }
+}
+
+void static
+avx512f_test (void)
+{
+  union512i_q s1, s2, res;
+  long long int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm512_sllv_epi64 (s1.x, s2.x);
+
+      compute_psllvq512 (s1.a, s2.a, res_ref);
+
+      fail += check_union512i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrad-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrad-1.c
new file mode 100644
index 000000000..3d6c5fc13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrad-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsrad\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsrad\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsrad\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sra_epi32 (x, y);
+  x = _mm512_mask_sra_epi32 (x, m, x, y);
+  x = _mm512_maskz_sra_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrad-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrad-2.c
new file mode 100644
index 000000000..596f98b43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrad-2.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, long long *s2)
+{
+  int i;
+  int count = s2[0];
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] =
+	count < 32 ? (s1[i] >> count) : (s1[i] > 0 ? 0 : 0xFFFFFFFF);
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1;
+  UNION_TYPE (128, i_q) src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  long long imm;
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      sign = sign * -1;
+    }
+
+  for (imm = 1; imm <= 33; imm++)
+    {
+      src2.a[0] = imm;
+      for (i = 0; i < SIZE; i++)
+	res2.a[i] = DEFAULT_VALUE;
+
+      res1.x = INTRINSIC (_sra_epi32) (src1.x, src2.x);
+      res2.x =
+	INTRINSIC (_mask_sra_epi32) (res2.x, mask, src1.x, src2.x);
+      res3.x = INTRINSIC (_maskz_sra_epi32) (mask, src1.x, src2.x);
+
+      CALC (res_ref, src1.a, src2.a);
+
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE (i_d) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+	abort ();
+
+      MASK_ZERO (i_d) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsradi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsradi-1.c
new file mode 100644
index 000000000..c7bf9385d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsradi-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsrad\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsrad\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsrad\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+#define y 7
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srai_epi32 (x, y);
+  x = _mm512_mask_srai_epi32 (x, m, x, y);
+  x = _mm512_maskz_srai_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsradi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsradi-2.c
new file mode 100644
index 000000000..3ba3ff131
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsradi-2.c
@@ -0,0 +1,78 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, int count)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] =
+	count < 32 ? (s1[i] >> count) : (s1[i] > 0 ? 0 : 0xFFFFFFFF);
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      sign = sign * -1;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srai_epi32) (src1.x, 3);
+  res2.x =
+    INTRINSIC (_mask_srai_epi32) (res2.x, mask, src1.x, 3);
+  res3.x = INTRINSIC (_maskz_srai_epi32) (mask, src1.x, 3);
+
+  CALC (res_ref, src1.a, 3);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srai_epi32) (src1.x, 33);
+  res2.x =
+    INTRINSIC (_mask_srai_epi32) (res2.x, mask, src1.x, 33);
+  res3.x = INTRINSIC (_maskz_srai_epi32) (mask, src1.x, 33);
+
+  CALC (res_ref, src1.a, 33);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraq-1.c
new file mode 100644
index 000000000..1c7a43db4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsraq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsraq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsraq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sra_epi64 (x, y);
+  x = _mm512_mask_sra_epi64 (x, m, x, y);
+  x = _mm512_maskz_sra_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraq-2.c
new file mode 100644
index 000000000..c5ae9c67d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraq-2.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long *s2)
+{
+  int i;
+  long long count = s2[0];
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] =
+	count < 64 ? (s1[i] >> count) : (s1[i] >
+					 0 ? 0 : 0xFFFFFFFFFFFFFFFFLL);
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1;
+  UNION_TYPE (128, i_q) src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  long long imm;
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      sign = sign * -1;
+    }
+
+  for (imm = 1; imm <= 65; imm++)
+    {
+      src2.a[0] = imm;
+      for (i = 0; i < SIZE; i++)
+	res2.a[i] = DEFAULT_VALUE;
+
+      res1.x = INTRINSIC (_sra_epi64) (src1.x, src2.x);
+      res2.x =
+	INTRINSIC (_mask_sra_epi64) (res2.x, mask, src1.x, src2.x);
+      res3.x = INTRINSIC (_maskz_sra_epi64) (mask, src1.x, src2.x);
+
+      CALC (res_ref, src1.a, src2.a);
+
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE (i_q) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+	abort ();
+
+      MASK_ZERO (i_q) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraqi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraqi-1.c
new file mode 100644
index 000000000..6400ef4c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraqi-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsraq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsraq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsraq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+#define y 7
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srai_epi64 (x, y);
+  x = _mm512_mask_srai_epi64 (x, m, x, y);
+  x = _mm512_maskz_srai_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraqi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraqi-2.c
new file mode 100644
index 000000000..47c273297
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsraqi-2.c
@@ -0,0 +1,80 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long count)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] =
+	count < 64 ? (s1[i] >> count) : (s1[i] >
+					 0 ? 0 : 0xFFFFFFFFFFFFFFFFLL);
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      sign = sign * -1;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srai_epi64) (src1.x, 3);
+  res2.x =
+    INTRINSIC (_mask_srai_epi64) (res2.x, mask, src1.x, 3);
+  res3.x = INTRINSIC (_maskz_srai_epi64) (mask, src1.x, 3);
+
+  CALC (res_ref, src1.a, 3);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srai_epi64) (src1.x, 65);
+  res2.x =
+    INTRINSIC (_mask_srai_epi64) (res2.x, mask, src1.x, 65);
+  res3.x = INTRINSIC (_maskz_srai_epi64) (mask, src1.x, 65);
+
+  CALC (res_ref, src1.a, 65);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravd-1.c
new file mode 100644
index 000000000..80414c109
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsravd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsravd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsravd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srav_epi32 (x, y);
+  x = _mm512_mask_srav_epi32 (x, m, x, y);
+  x = _mm512_maskz_srav_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravd-2.c
new file mode 100644
index 000000000..0651c24cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravd-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, int *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] =
+	s2[i] < 32 ? (s1[i] >> s2[i]) : (s1[i] > 0 ? 0 : 0xFFFFFFFF);
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      src2.a[i] = 1 + 17 * i % 71;
+      sign = sign * -1;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srav_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_srav_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_srav_epi32) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq-1.c
new file mode 100644
index 000000000..db6b8dd37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsravq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsravq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsravq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srav_epi64 (x, y);
+  x = _mm512_mask_srav_epi64 (x, m, x, y);
+  x = _mm512_maskz_srav_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq-2.c
new file mode 100644
index 000000000..3b7063f57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq-2.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] =
+	s2[i] < 64 ? (s1[i] >> s2[i]) : (s1[i] >
+					 0 ? 0 : 0xFFFFFFFFFFFFFFFFLL);
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + sign * 7 * i % 291;
+      src2.a[i] = 1 + 17 * i % 71;
+      sign = sign * -1;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srav_epi64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_srav_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_srav_epi64) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq512-1.c
new file mode 100644
index 000000000..318769b16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq512-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vpsravq\[ \\t\]+\[^\n\]*%zmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srav_epi64 (x, x);
+}
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq512-2.c
new file mode 100644
index 000000000..c2511e9f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsravq512-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include <string.h>
+#include "avx512f-check.h"
+
+static void
+compute_psravq512 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count;
+
+  for (i = 0; i < 8; ++i)
+    {
+      count = s2[i];
+      r[i] = s1[i] >> count;
+    }
+}
+
+void static
+avx512f_test (void)
+{
+  union512i_q s1, s2, res;
+  long long int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm512_srav_epi64 (s1.x, s2.x);
+
+      compute_psravq512 (s1.a, s2.a, res_ref);
+
+      fail += check_union512i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrld-1.c
new file mode 100644
index 000000000..7c9ea1610
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrld-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srl_epi32 (x, y);
+  x = _mm512_mask_srl_epi32 (x, m, x, y);
+  x = _mm512_maskz_srl_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrld-2.c
new file mode 100644
index 000000000..653a8f8f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrld-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned int *r, unsigned int *s1,  unsigned long long* s2)
+{
+  int i;
+  unsigned int count = s2[0];
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = count < 32 ? (s1[i] >> count) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1;
+  UNION_TYPE (128, i_q) src2;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned int res_ref[SIZE];
+
+  unsigned long long imm;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + 7 * i % 291;
+    }
+
+  for (imm = 1; imm <= 33; imm++)
+    {
+      src2.a[0] = imm;
+      for (i = 0; i < SIZE; i++)
+	res2.a[i] = DEFAULT_VALUE;
+
+      res1.x = INTRINSIC (_srl_epi32) (src1.x, src2.x);
+      res2.x = INTRINSIC (_mask_srl_epi32) (res2.x, mask, src1.x, src2.x);
+      res3.x = INTRINSIC (_maskz_srl_epi32) (mask, src1.x, src2.x);
+
+      CALC (res_ref, src1.a, src2.a);
+
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE (i_d) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+	abort ();
+
+      MASK_ZERO (i_d) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrldi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrldi-1.c
new file mode 100644
index 000000000..c21566d1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrldi-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsrld\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+#define y 7
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srli_epi32 (x, y);
+  x = _mm512_mask_srli_epi32 (x, m, x, y);
+  x = _mm512_maskz_srli_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrldi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrldi-2.c
new file mode 100644
index 000000000..e178445fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrldi-2.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned int *r, unsigned int *s1, unsigned int count)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = count < 32 ? (s1[i] >> count) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned int res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + 7 * i % 291;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srli_epi32) (src1.x, 3);
+  res2.x =
+    INTRINSIC (_mask_srli_epi32) (res2.x, mask, src1.x, 3);
+  res3.x = INTRINSIC (_maskz_srli_epi32) (mask, src1.x, 3);
+
+  CALC (res_ref, src1.a, 3);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srli_epi32) (src1.x, 33);
+  res2.x =
+    INTRINSIC (_mask_srli_epi32) (res2.x, mask, src1.x, 33);
+  res3.x = INTRINSIC (_maskz_srli_epi32) (mask, src1.x, 33);
+
+  CALC (res_ref, src1.a, 33);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlq-1.c
new file mode 100644
index 000000000..d3af6091f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsrlq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsrlq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsrlq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m128i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srl_epi64 (x, y);
+  x = _mm512_mask_srl_epi64 (x, m, x, y);
+  x = _mm512_maskz_srl_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlq-2.c
new file mode 100644
index 000000000..403052873
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlq-2.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned long long *r, unsigned long long *s1,  unsigned long long* s2)
+{
+  int i;
+  unsigned long long count = s2[0];
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = count < 64 ? (s1[i] >> count) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1;
+  UNION_TYPE (128, i_q) src2;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned long long res_ref[SIZE];
+
+  unsigned long long imm;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + 7 * i % 291;
+    }
+
+  for (imm = 1; imm <= 65; imm++)
+    {
+      src2.a[0] = imm;
+      for (i = 0; i < SIZE; i++)
+	res2.a[i] = DEFAULT_VALUE;
+
+      res1.x = INTRINSIC (_srl_epi64) (src1.x, src2.x);
+      res2.x = INTRINSIC (_mask_srl_epi64) (res2.x, mask, src1.x, src2.x);
+      res3.x = INTRINSIC (_maskz_srl_epi64) (mask, src1.x, src2.x);
+
+      CALC (res_ref, src1.a, src2.a);
+
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE (i_q) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+	abort ();
+
+      MASK_ZERO (i_q) (res_ref, mask, SIZE);
+      if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlqi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlqi-1.c
new file mode 100644
index 000000000..b1f6d2766
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlqi-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsrlq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsrlq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsrlq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+#define y 7
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srli_epi64 (x, y);
+  x = _mm512_mask_srli_epi64 (x, m, x, y);
+  x = _mm512_maskz_srli_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlqi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlqi-2.c
new file mode 100644
index 000000000..3fedac4c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlqi-2.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned long long *r, unsigned long long *s1,
+      unsigned long long count)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = count < 64 ? (s1[i] >> count) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned long long res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + 7 * i % 291;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srli_epi64) (src1.x, 3);
+  res2.x =
+    INTRINSIC (_mask_srli_epi64) (res2.x, mask, src1.x, 3);
+  res3.x = INTRINSIC (_maskz_srli_epi64) (mask, src1.x, 3);
+
+  CALC (res_ref, src1.a, 3);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srli_epi64) (src1.x, 65);
+  res2.x =
+    INTRINSIC (_mask_srli_epi64) (res2.x, mask, src1.x, 65);
+  res3.x = INTRINSIC (_maskz_srli_epi64) (mask, src1.x, 65);
+
+  CALC (res_ref, src1.a, 65);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvd-1.c
new file mode 100644
index 000000000..c8fe74d73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsrlvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsrlvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsrlvd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m512i y;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srlv_epi32 (x, y);
+  x = _mm512_mask_srlv_epi32 (x, m, x, y);
+  x = _mm512_maskz_srlv_epi32 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvd-2.c
new file mode 100644
index 000000000..514d36a37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned int *r, unsigned int *s1, unsigned int *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s2[i] < 32 ? (s1[i] >> s2[i]) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned int res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + 7 * i % 291;
+      src2.a[i] = 1 + 17 * i % 71;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srlv_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_srlv_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_srlv_epi32) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq-1.c
new file mode 100644
index 000000000..b316f68f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsrlvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsrlvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsrlvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __m512i y;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srlv_epi64 (x, y);
+  x = _mm512_mask_srlv_epi64 (x, m, x, y);
+  x = _mm512_maskz_srlv_epi64 (m, x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq-2.c
new file mode 100644
index 000000000..586b8c2f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (unsigned long long *r, unsigned long long *s1,
+      unsigned long long *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s2[i] < 64 ? (s1[i] >> s2[i]) : 0;
+    }
+}
+
+void static
+TEST (void)
+{
+  int i;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  unsigned long long res_ref[SIZE];
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 2 + 7 * i % 291;
+      src2.a[i] = 1 + 17 * i % 71;
+    }
+
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_srlv_epi64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_srlv_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_srlv_epi64) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq512-1.c
new file mode 100644
index 000000000..99b12d200
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq512-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vpsrlvq\[ \\t\]+\[^\n\]*%zmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_srlv_epi64 (x, x);
+}
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq512-2.c
new file mode 100644
index 000000000..d262a8352
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsrlvq512-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#include <string.h>
+#include "avx512f-check.h"
+
+static void
+compute_psrlvq512 (long long int *s1, long long int *s2, long long int *r)
+{
+  int i;
+  long long int count;
+
+  for (i = 0; i < 8; ++i)
+    {
+      count = s2[i];
+      r[i] = ((unsigned long long) s1[i]) >> count;
+    }
+}
+
+void static
+avx512f_test (void)
+{
+  union512i_q s1, s2, res;
+  long long int res_ref[8];
+  int i, j, sign = 1;
+  int fail = 0;
+
+  for (i = 0; i < 10; i++)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  s1.a[j] = j * i * sign;
+	  s2.a[j] = (j + i) >> 2;
+	  sign = -sign;
+	}
+
+      res.x = _mm512_srlv_epi64 (s1.x, s2.x);
+
+      compute_psrlvq512 (s1.a, s2.a, res_ref);
+
+      fail += check_union512i_q (res, res_ref);
+    }
+
+  if (fail != 0)
+    abort ();
+}
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubd-1.c
new file mode 100644
index 000000000..28c3584e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sub_epi32 (x, x);
+  x = _mm512_mask_sub_epi32 (x, m, x, x);
+  x = _mm512_maskz_sub_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubd-2.c
new file mode 100644
index 000000000..acc26ce83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, int *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] - s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_sub_epi32) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_sub_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_sub_epi32) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubq-1.c
new file mode 100644
index 000000000..c51b291da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vpsubq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpsubq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpsubq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sub_epi64 (x, x);
+  x = _mm512_mask_sub_epi64 (x, m, x, x);
+  x = _mm512_maskz_sub_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubq-2.c
new file mode 100644
index 000000000..ba16ee184
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpsubq-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] - s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_sub_epi64) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_sub_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_sub_epi64) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogd-1.c
new file mode 100644
index 000000000..e4708bf51
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpternlogd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpternlogd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpternlogd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, y, z;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_ternarylogic_epi32 (x, y, z, 0xF0);
+  x = _mm512_mask_ternarylogic_epi32 (x, m, y, z, 0xF0);
+  x = _mm512_maskz_ternarylogic_epi32 (m, x, y, z, 0xF0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogd-2.c
new file mode 100644
index 000000000..c9813ed24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogd-2.c
@@ -0,0 +1,71 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *src1, int *src2, int *src3, int imm, int *r)
+{
+  int i, j, index, res, mask, one_mask = 1;
+  int src1_bit, src2_bit, src3_bit, imm_bit;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res = 0;
+      for (j = 0; j < 32; j++)
+	{
+	  mask = one_mask << j;
+	  src1_bit = ((src1[i] & mask) >> j) << 2;
+	  src2_bit = ((src2[i] & mask) >> j) << 1;
+	  src3_bit = ((src3[i] & mask) >> j);
+	  index = src1_bit | src2_bit | src3_bit;
+	  imm_bit = (imm & (one_mask << index)) >> index;
+	  res = res | (imm_bit << j);
+	}
+      r[i] = res;
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) src2, src3, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, imm = 0x7D;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+      src2.a[i] = 145132 * i + 123123;
+      src3.a[i] = 1223 * i + 895;
+    }
+
+  CALC (res1.a, src2.a, src3.a, imm, res_ref);
+
+  res1.x = INTRINSIC (_ternarylogic_epi32) (res1.x, src2.x, src3.x,
+    imm);
+  res2.x = INTRINSIC (_mask_ternarylogic_epi32) (res2.x, mask, src2.x,
+    src3.x, imm);
+  res3.x = INTRINSIC (_maskz_ternarylogic_epi32) (mask, res3.x, src2.x,
+    src3.x, imm);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogq-1.c
new file mode 100644
index 000000000..7d074668d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpternlogq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpternlogq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpternlogq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, y, z;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_ternarylogic_epi64 (x, y, z, 0xF0);
+  x = _mm512_mask_ternarylogic_epi64 (x, m, y, z, 0xF0);
+  x = _mm512_maskz_ternarylogic_epi64 (m, x, y, z, 0xF0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogq-2.c
new file mode 100644
index 000000000..a8065541e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpternlogq-2.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *src1, long long *src2, long long *src3,
+      long long imm, long long *r)
+{
+  int i, j;
+  long long res, index, mask, one_mask = 1;
+  long long src1_bit, src2_bit, src3_bit, imm_bit;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res = 0;
+      for (j = 0; j < 64; j++)
+	{
+	  mask = one_mask << j;
+	  src1_bit = ((src1[i] & mask) >> j) << 2;
+	  src2_bit = ((src2[i] & mask) >> j) << 1;
+	  src3_bit = ((src3[i] & mask) >> j);
+	  index = src1_bit | src2_bit | src3_bit;
+	  imm_bit = (imm & (one_mask << index)) >> index;
+	  res = res | (imm_bit << j);
+	}
+      r[i] = res;
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) src2, src3, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i, imm = 0x7D;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      res1.a[i] = DEFAULT_VALUE;
+      res2.a[i] = DEFAULT_VALUE;
+      res3.a[i] = DEFAULT_VALUE;
+      src2.a[i] = 145132 * i + 123123;
+      src3.a[i] = 1223 * i + 895;
+    }
+
+  CALC (res1.a, src2.a, src3.a, imm, res_ref);
+
+  res1.x = INTRINSIC (_ternarylogic_epi64) (res1.x, src2.x, src3.x,
+    imm);
+  res2.x = INTRINSIC (_mask_ternarylogic_epi64) (res2.x, mask, src2.x,
+    src3.x, imm);
+  res3.x = INTRINSIC (_maskz_ternarylogic_epi64) (mask, res3.x, src2.x,
+    src3.x, imm);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmd-1.c
new file mode 100644
index 000000000..2242314ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmd-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vptestmd\[ \\t\]+\[^\n\]*%zmm\[0-7\]\[^\n^k\]*k\[1-7\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vptestmd\[ \\t\]+\[^\n\]*%zmm\[0-7\]\[^\n^k\]*k\[1-7\]\{" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m16;
+
+void extern
+avx512f_test (void)
+{
+  m16 = _mm512_test_epi32_mask (x, x);
+  m16 = _mm512_mask_test_epi32_mask (3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmd-2.c
new file mode 100644
index 000000000..5025fab30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmd-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *res, int *src1, int *src2)
+{
+  int i;
+  *res = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (src1[i] & src2[i])
+      *res = *res | one << i;
+}
+
+static void
+TEST (void)
+{
+  int i, sign = 1;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1, res2;
+  MASK_TYPE mask = MASK_VALUE;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i * i * sign;
+      src2.a[i] = i + 20;
+      sign = -sign;
+    }
+
+  res1 = INTRINSIC (_test_epi32_mask) (src1.x, src2.x);
+  res2 = INTRINSIC (_mask_test_epi32_mask) (mask, src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+
+  res_ref &= mask;
+
+  if (res2 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmq-1.c
new file mode 100644
index 000000000..9a92903a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmq-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vptestmq\[ \\t\]+\[^\n\]*%zmm\[0-7\]\[^\n^k\]*k\[1-7\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vptestmq\[ \\t\]+\[^\n\]*%zmm\[0-7\]\[^\n^k\]*k\[1-7\]\{" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  m8 = _mm512_test_epi64_mask (x, x);
+  m8 = _mm512_mask_test_epi64_mask (3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmq-2.c
new file mode 100644
index 000000000..9ec9e48b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestmq-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *res, long long *src1, long long *src2)
+{
+  int i;
+  *res = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (src1[i] & src2[i])
+      *res = *res | one << i;
+}
+
+static void
+TEST (void)
+{
+  int i, sign = 1;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res_ref, res1, res2;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+  res2 = 0;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i * i * sign;
+      src2.a[i] = i + 20;
+      sign = -sign;
+    }
+
+  res1 = INTRINSIC (_test_epi64_mask) (src1.x, src2.x);
+  res2 = INTRINSIC (_mask_test_epi64_mask) (mask, src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+
+  res_ref &= mask;
+
+  if (res2 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmd-1.c
new file mode 100644
index 000000000..1094ee5b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmd-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vptestnmd\[ \\t\]+\[^\n\]*%zmm\[0-7\]\[^\n^k\]*k\[1-7\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vptestnmd\[ \\t\]+\[^\n\]*%zmm\[0-7\]\[^\n^k\]*k\[1-7\]\{" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m16;
+
+void extern
+avx512f_test (void)
+{
+  m16 = _mm512_testn_epi32_mask (x, x);
+  m16 = _mm512_mask_testn_epi32_mask (3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmd-2.c
new file mode 100644
index 000000000..b2b4d0e1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmd-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *res, int *src1, int *src2)
+{
+  int i;
+  *res = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (!(src1[i] & src2[i]))
+      *res = *res | one << i;
+}
+
+static void
+TEST (void)
+{
+  int i, sign = 1;
+  UNION_TYPE (AVX512F_LEN, i_d) src1, src2;
+  MASK_TYPE res_ref, res1, res2;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+  res2 = 0;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i * i * sign;
+      src2.a[i] = i + 20;
+      sign = -sign;
+    }
+
+  res1 = INTRINSIC (_testn_epi32_mask) (src1.x, src2.x);
+  res2 = INTRINSIC (_mask_testn_epi32_mask) (mask, src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+
+  res_ref &= mask;
+
+  if (res2 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmq-1.c
new file mode 100644
index 000000000..081a25e17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmq-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vptestnmq\[ \\t\]+\[^\n\]*%zmm\[0-7\]\[^\n^k\]*k\[1-7\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vptestnmq\[ \\t\]+\[^\n\]*%zmm\[0-7\]\[^\n^k\]*k\[1-7\]\{" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m8;
+
+void extern
+avx512f_test (void)
+{
+  m8 = _mm512_testn_epi64_mask (x, x);
+  m8 = _mm512_mask_testn_epi64_mask (3, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmq-2.c
new file mode 100644
index 000000000..b6330d213
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vptestnmq-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (MASK_TYPE *res, long long *src1, long long *src2)
+{
+  int i;
+  *res = 0;
+  MASK_TYPE one = 1;
+
+  for (i = 0; i < SIZE; i++)
+    if (!(src1[i] & src2[i]))
+      *res = *res | one << i;
+}
+
+static void
+TEST (void)
+{
+  int i, sign = 1;
+  UNION_TYPE (AVX512F_LEN, i_q) src1, src2;
+  MASK_TYPE res_ref, res1, res2;
+  MASK_TYPE mask = MASK_VALUE;
+  res1 = 0;
+  res2 = 0;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = i * i * sign;
+      src2.a[i] = i + 20;
+      sign = -sign;
+    }
+
+  res1 = INTRINSIC (_testn_epi64_mask) (src1.x, src2.x);
+  res2 = INTRINSIC (_mask_testn_epi64_mask) (mask, src1.x, src2.x);
+
+  CALC (&res_ref, src1.a, src2.a);
+
+  if (res1 != res_ref)
+    abort ();
+
+  res_ref &= mask;
+
+  if (res2 != res_ref)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhdq-1.c
new file mode 100644
index 000000000..800e1e0ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhdq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpunpckhdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, y, z;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_unpackhi_epi32 (y, z);
+  x = _mm512_mask_unpackhi_epi32 (x, m, y, z);
+  x = _mm512_maskz_unpackhi_epi32 (m, y, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhdq-2.c
new file mode 100644
index 000000000..adb9b7a53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhdq-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, int *s2)
+{
+  int i;
+  for (i = 0; i < SIZE / 4; i++)
+    {
+      r[4 * i] = s1[4 * i + 2];
+      r[4 * i + 1] = s2[4 * i + 2];
+      r[4 * i + 2] = s1[4 * i + 3];
+      r[4 * i + 3] = s2[4 * i + 3];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 34 * i * sign;
+      src1.a[i] = 179 * i;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_unpackhi_epi32) (src1.x, src2.x);
+  res2.x =
+    INTRINSIC (_mask_unpackhi_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_unpackhi_epi32) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhqdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhqdq-1.c
new file mode 100644
index 000000000..05b22297f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhqdq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpunpckhqdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhqdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhqdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, y, z;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_unpackhi_epi64 (y, z);
+  x = _mm512_mask_unpackhi_epi64 (x, m, y, z);
+  x = _mm512_maskz_unpackhi_epi64 (m, y, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhqdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhqdq-2.c
new file mode 100644
index 000000000..b226274df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckhqdq-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long *s2)
+{
+  int i;
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      r[2 * i] = s1[2 * i + 1];
+      r[2 * i + 1] = s2[2 * i + 1];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 34 * i * sign;
+      src1.a[i] = 179 * i;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_unpackhi_epi64) (src1.x, src2.x);
+  res2.x =
+    INTRINSIC (_mask_unpackhi_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_unpackhi_epi64) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckldq-1.c
new file mode 100644
index 000000000..29a2c8dc6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckldq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpunpckldq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckldq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckldq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, y, z;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_unpacklo_epi32 (y, z);
+  x = _mm512_mask_unpacklo_epi32 (x, m, y, z);
+  x = _mm512_maskz_unpacklo_epi32 (m, y, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckldq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckldq-2.c
new file mode 100644
index 000000000..b715fde17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpckldq-2.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (int *r, int *s1, int *s2)
+{
+  int i;
+  for (i = 0; i < SIZE / 4; i++)
+    {
+      r[4 * i] = s1[4 * i];
+      r[4 * i + 1] = s2[4 * i];
+      r[4 * i + 2] = s1[4 * i + 1];
+      r[4 * i + 3] = s2[4 * i + 1];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 34 * i * sign;
+      src1.a[i] = 179 * i;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_unpacklo_epi32) (src1.x, src2.x);
+  res2.x =
+    INTRINSIC (_mask_unpacklo_epi32) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_unpacklo_epi32) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpcklqdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpcklqdq-1.c
new file mode 100644
index 000000000..ac6f2976a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpcklqdq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpunpcklqdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[\\n\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpcklqdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpcklqdq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x, y, z;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_unpacklo_epi64 (y, z);
+  x = _mm512_mask_unpacklo_epi64 (x, m, y, z);
+  x = _mm512_maskz_unpacklo_epi64 (m, y, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpcklqdq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpcklqdq-2.c
new file mode 100644
index 000000000..2892f1c32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpunpcklqdq-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (long long *r, long long *s1, long long *s2)
+{
+  int i;
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      r[2 * i] = s1[2 * i];
+      r[2 * i + 1] = s2[2 * i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, i_q) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 34 * i * sign;
+      src1.a[i] = 179 * i;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_unpacklo_epi64) (src1.x, src2.x);
+  res2.x =
+    INTRINSIC (_mask_unpacklo_epi64) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_unpacklo_epi64) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxord-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxord-1.c
new file mode 100644
index 000000000..99e82bef4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxord-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_xor_si512 (x, x);
+  x = _mm512_xor_epi32 (x, x);
+  x = _mm512_mask_xor_epi32 (x, m, x, x);
+  x = _mm512_maskz_xor_epi32 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxord-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxord-2.c
new file mode 100644
index 000000000..7a9666ce7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxord-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (int *s1, int *s2, int *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s1[i] ^ s2[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) s1, s2, res1, res2, res3, res4;
+  MASK_TYPE mask = MASK_VALUE;
+  int res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * sign;
+      s2.a[i] = (i + 20) * sign;
+      sign = -sign;
+      res3.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_xor_si512) (s1.x, s2.x);
+  res2.x = INTRINSIC (_xor_epi32) (s1.x, s2.x);
+  res3.x = INTRINSIC (_mask_xor_epi32) (res3.x, mask, s1.x, s2.x);
+  res4.x = INTRINSIC (_maskz_xor_epi32) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res1, res_ref))
+    abort ();
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res2, res_ref))
+    abort ();
+
+  MASK_MERGE (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res3, res_ref))
+    abort ();
+
+  MASK_ZERO (i_d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (res4, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxorq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxorq-1.c
new file mode 100644
index 000000000..cd2853409
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxorq-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpxorq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vpxorq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vpxorq\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_xor_epi64 (x, x);
+  x = _mm512_mask_xor_epi64 (x, m, x, x);
+  x = _mm512_maskz_xor_epi64 (m, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxorq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxorq-2.c
new file mode 100644
index 000000000..288b0085f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vpxorq-2.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (long long *s1, long long *s2, long long *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    r[i] = s1[i] ^ s2[i];
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  long long res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * sign;
+      s2.a[i] = (i + 20) * sign;
+      sign = -sign;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_xor_epi64) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_xor_epi64) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_xor_epi64) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res1, res_ref))
+      abort ();
+
+  MASK_MERGE (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (i_q) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14pd-1.c
new file mode 100644
index 000000000..734242048
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14pd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrcp14pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vrcp14pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrcp14pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rcp14_pd (x);
+  x = _mm512_mask_rcp14_pd (x, m, x);
+  x = _mm512_maskz_rcp14_pd (m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14pd-2.c
new file mode 100644
index 000000000..4653d7730
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14pd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = 1.0 / s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000) * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_rcp14_pd) (s.x);
+  res2.x = INTRINSIC (_mask_rcp14_pd) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_rcp14_pd) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ps-1.c
new file mode 100644
index 000000000..ea6c68de7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ps-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrcp14ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vrcp14ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrcp14ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rcp14_ps (x);
+  x = _mm512_mask_rcp14_ps (x, m, x);
+  x = _mm512_maskz_rcp14_ps (m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ps-2.c
new file mode 100644
index 000000000..6e0e57791
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ps-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = 1.0 / s[i];
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i, sign = 1;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000) * sign;
+      res2.a[i] = DEFAULT_VALUE;
+      sign = -sign;
+    }
+
+  res1.x = INTRINSIC (_rcp14_ps) (s.x);
+  res2.x = INTRINSIC (_mask_rcp14_ps) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_rcp14_ps) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_ROUGH_CHECK (AVX512F_LEN,) (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN,) (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN,) (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14sd-1.c
new file mode 100644
index 000000000..c0c8d038c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14sd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrcp14sd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_rcp14_sd (x1, x2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14sd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14sd-2.c
new file mode 100644
index 000000000..f94460036
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14sd-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+static void
+compute_vrcp14sd (double *s1, double *s2, double *r)
+{
+  r[0] = 1.0 / s2[0];
+  r[1] = s1[1];
+}
+
+static void
+avx512f_test (void)
+{
+  union128d s1, s2, res1, res2, res3;
+  double res_ref[2];
+
+  s1.x = _mm_set_pd (-3.0, 111.111);
+  s2.x = _mm_set_pd (222.222, -2.0);
+  res2.a[0] = DEFAULT_VALUE;
+
+  res1.x = _mm_rcp14_sd (s1.x, s2.x);
+
+  compute_vrcp14sd (s1.a, s2.a, res_ref);
+
+  if (checkVd (res1.a, res_ref, 2))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ss-1.c
new file mode 100644
index 000000000..580dfd6a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrcp14ss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_rcp14_ss (x1, x2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ss-2.c
new file mode 100644
index 000000000..7aca591bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrcp14ss-2.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+static void
+compute_vrcp14ss (float *s1, float *s2, float *r)
+{
+  r[0] = 1.0 / s2[0];
+  r[1] = s1[1];
+  r[2] = s1[2];
+  r[3] = s1[3];
+}
+
+static void
+avx512f_test (void)
+{
+  union128 s1, s2, res1, res2, res3;
+  float res_ref[4];
+
+  s1.x = _mm_set_ps (-24.043, 68.346, -43.35, 546.46);
+  s2.x = _mm_set_ps (222.222, 333.333, 444.444, -2.0);
+  res2.a[0] = DEFAULT_VALUE;
+
+  res1.x = _mm_rcp14_ss (s1.x, s2.x);
+
+  compute_vrcp14ss (s1.a, s2.a, res_ref);
+
+  if (checkVf (res1.a, res_ref, 4))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalepd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalepd-1.c
new file mode 100644
index 000000000..baf505c80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalepd-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrndscalepd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vrndscalepd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vrndscalepd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vrndscalepd\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%zmm\[0-9\]\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscalepd\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_roundscale_pd (x, 0x42);
+  x = _mm512_ceil_pd (x);
+  x = _mm512_floor_pd (x);
+  x = _mm512_mask_roundscale_pd (x, 2, x, 0x42);
+  x = _mm512_mask_ceil_pd (x, 2, x);
+  x = _mm512_mask_floor_pd (x, 2, x);
+  x = _mm512_maskz_roundscale_pd (2, x, 0x42);
+
+  x = _mm512_roundscale_round_pd (x, 0x42, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_roundscale_round_pd (x, 2, x, 0x42, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_roundscale_round_pd (2, x, 0x42, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalepd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalepd-2.c
new file mode 100644
index 000000000..f18cdcbca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalepd-2.c
@@ -0,0 +1,94 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "math.h"
+
+static void
+CALC (double *s, double *r, int imm)
+{
+  int i = 0, rc, m;
+  rc = imm & 0xf;
+  m = imm >> 4;
+  for (i = 0; i < SIZE; i++)
+    switch (rc)
+      {
+      case _MM_FROUND_FLOOR:
+	r[i] = floor (s[i] * pow (2, m)) / pow (2, m);
+	break;
+      case _MM_FROUND_CEIL:
+	r[i] = ceil (s[i] * pow (2, m)) / pow (2, m);
+	break;
+      default:
+	abort ();
+	break;
+      }
+}
+
+void static
+TEST (void)
+{
+  int imm, i, j;
+  UNION_TYPE (AVX512F_LEN, d) res1,res2,res3,s;
+  double res_ref[SIZE];
+  double res_ref_mask[SIZE];
+
+  MASK_TYPE mask = 6 ^ (0xff >> SIZE);
+
+  imm = _MM_FROUND_FLOOR | (7 << 4);
+
+  for (i = 0; i < 3; i++)
+    {
+
+      for (j = 0; j < SIZE; j++)
+	{
+	  s.a[j] = j * (j + 12.0231);
+	  res1.a[j] = DEFAULT_VALUE;
+	  res2.a[j] = DEFAULT_VALUE;
+	  res3.a[j] = DEFAULT_VALUE;
+	}
+
+      switch (i)
+	{
+	case 0:
+	  imm = _MM_FROUND_FLOOR | (7 << 4);
+	  res1.x = INTRINSIC (_roundscale_pd) (s.x, imm);
+	  res2.x = INTRINSIC (_mask_roundscale_pd) (res2.x, mask, s.x, imm);
+	  res3.x = INTRINSIC (_maskz_roundscale_pd) (mask, s.x, imm);
+	  break;
+	case 1:
+	  imm = _MM_FROUND_FLOOR;
+	  res1.x = INTRINSIC (_floor_pd) (s.x);
+	  res2.x = INTRINSIC (_mask_floor_pd) (res2.x, mask, s.x);
+	  break;
+	case 2:
+	  imm = _MM_FROUND_CEIL;
+	  res1.x = INTRINSIC (_ceil_pd) (s.x);
+	  res2.x = INTRINSIC (_mask_ceil_pd) (res2.x, mask, s.x);
+	  break;
+	}
+
+      CALC (s.a, res_ref, imm);
+
+      if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE(d) (res_ref,mask,SIZE );
+
+      if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+	abort ();
+
+      MASK_ZERO(d) (res_ref,mask,SIZE );
+
+      if (!i && UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+	abort ();
+
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaleps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaleps-1.c
new file mode 100644
index 000000000..d7a6f9f90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaleps-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrndscaleps\[ \\t\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vrndscaleps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 4 } } */
+/* { dg-final { scan-assembler-times "vrndscaleps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vrndscaleps\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrndscaleps\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_roundscale_ps (x, 0x42);
+  x = _mm512_ceil_ps (x);
+  x = _mm512_floor_ps (x);
+  x = _mm512_mask_roundscale_ps (x, 2, x, 0x42);
+  x = _mm512_mask_ceil_ps (x, 2, x);
+  x = _mm512_mask_floor_ps (x, 2, x);
+  x = _mm512_maskz_roundscale_ps (2, x, 0x42);
+
+  x = _mm512_roundscale_round_ps (x, 0x42, _MM_FROUND_NO_EXC);
+  x = _mm512_mask_roundscale_round_ps (x, 2, x, 0x42, _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_roundscale_round_ps (2, x, 0x42, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaleps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaleps-2.c
new file mode 100644
index 000000000..097253d75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaleps-2.c
@@ -0,0 +1,92 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "math.h"
+
+static void
+CALC (float *s, float *r, int imm)
+{
+  int i = 0, rc, m;
+  rc = imm & 0xf;
+  m = imm >> 4;
+  for (i = 0; i < SIZE; i++)
+    switch (rc)
+      {
+      case _MM_FROUND_FLOOR:
+	r[i] = floor (s[i] * pow (2, m)) / pow (2, m);
+	break;
+      case _MM_FROUND_CEIL:
+	r[i] = ceil (s[i] * pow (2, m)) / pow (2, m);
+	break;
+      default:
+	abort ();
+	break;
+      }
+}
+
+void static
+TEST (void)
+{
+  int imm, i, j;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3, s;
+  float res_ref[SIZE];
+
+  MASK_TYPE mask = 6 ^ (0xffff >> SIZE);
+
+  imm = _MM_FROUND_FLOOR | (7 << 4);
+
+  for (i = 0; i < 3; i++)
+    {
+
+      for (j = 0; j < SIZE; j++)
+	{
+	  s.a[j] = j * (j + 12.0231);
+	  res1.a[j] = DEFAULT_VALUE;
+	  res2.a[j] = DEFAULT_VALUE;
+	  res3.a[j] = DEFAULT_VALUE;
+	}
+
+      switch (i)
+	{
+	case 0:
+	  imm = _MM_FROUND_FLOOR | (7 << 4);
+	  res1.x = INTRINSIC (_roundscale_ps) (s.x, imm);
+	  res2.x = INTRINSIC (_mask_roundscale_ps) (res2.x, mask, s.x, imm);
+	  res3.x = INTRINSIC (_maskz_roundscale_ps) (mask, s.x, imm);
+	  break;
+	case 1:
+	  imm = _MM_FROUND_FLOOR;
+	  res1.x = INTRINSIC (_floor_ps) (s.x);
+	  res2.x = INTRINSIC (_mask_floor_ps) (res2.x, mask, s.x);
+	  break;
+	case 2:
+	  imm = _MM_FROUND_CEIL;
+	  res1.x = INTRINSIC (_ceil_ps) (s.x);
+	  res2.x = INTRINSIC (_mask_ceil_ps) (res2.x, mask, s.x);
+	  break;
+	}
+
+      CALC (s.a, res_ref, imm);
+
+      if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+	abort ();
+
+      MASK_MERGE ()(res_ref, mask, SIZE);
+
+      if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+	abort ();
+
+      MASK_ZERO ()(res_ref, mask, SIZE);
+
+      if (!i && UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+	abort ();
+
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalesd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalesd-1.c
new file mode 100644
index 000000000..2f370a927
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalesd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrndscalesd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrndscalesd\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_roundscale_sd (x1, x2, 0x42);
+  x1 = _mm_roundscale_round_sd (x1, x2, 0x42, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalesd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalesd-2.c
new file mode 100644
index 000000000..5b4e8423c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscalesd-2.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#define SIZE (128 / 64)
+
+#include <math.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+static void
+compute_rndscalesd (double *s1, double *s2, double *r, int imm)
+{
+  int rc, m;
+  rc = imm & 0xf;
+  m = imm >> 4;
+
+  switch (rc)
+    {
+    case _MM_FROUND_FLOOR:
+      r[0] = floor (s2[0] * pow (2, m)) / pow (2, m);
+      break;
+    case _MM_FROUND_CEIL:
+      r[0] = ceil (s2[0] * pow (2, m)) / pow (2, m);
+      break;
+    default:
+      abort ();
+      break;
+    }
+
+  r[1] = s1[1];
+}
+
+static void
+avx512f_test (void)
+{
+  int imm = _MM_FROUND_FLOOR | (7 << 4);
+  union128d s1, s2, res1;
+  double res_ref[SIZE];
+
+  s1.x = _mm_set_pd (4.05084, -1.23162);
+  s2.x = _mm_set_pd (-3.53222, 7.33527);
+
+  res1.x = _mm_roundscale_sd (s1.x, s2.x, imm);
+
+  compute_rndscalesd (s1.a, s2.a, res_ref, imm);
+
+  if (check_union128d (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaless-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaless-1.c
new file mode 100644
index 000000000..c9f5a753d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaless-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrndscaless\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vrndscaless\[ \\t\]+\\S*,\[ \\t\]+\{sae\}\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_roundscale_ss (x1, x2, 0x42);
+  x1 = _mm_roundscale_round_ss (x1, x2, 0x42, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaless-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaless-2.c
new file mode 100644
index 000000000..45052bc61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrndscaless-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#define SIZE (128 / 32)
+
+#include <math.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+static void
+compute_rndscaless (float *s1, float *s2, float *r, int imm)
+{
+  int rc, m;
+  rc = imm & 0xf;
+  m = imm >> 4;
+
+  switch (rc)
+    {
+    case _MM_FROUND_FLOOR:
+      r[0] = __builtin_floorf (s2[0] * pow (2, m)) / pow (2, m);
+      break;
+    case _MM_FROUND_CEIL:
+      r[0] = __builtin_ceilf (s2[0] * pow (2, m)) / pow (2, m);
+      break;
+    default:
+      abort ();
+      break;
+    }
+
+  r[1] = s1[1];
+  r[2] = s1[2];
+  r[3] = s1[3];
+}
+
+static void
+avx512f_test (void)
+{
+  int imm = _MM_FROUND_FLOOR | (7 << 4);
+  union128 s1, s2, res1;
+  float res_ref[SIZE];
+
+  s1.x = _mm_set_ps (4.05084, -1.23162, 2.00231, -6.22103);
+  s2.x = _mm_set_ps (-4.19319, -3.53222, 7.33527, 5.57655);
+
+  res1.x = _mm_roundscale_ss (s1.x, s2.x, imm);
+
+  compute_rndscaless (s1.a, s2.a, res_ref, imm);
+
+  if (check_union128 (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14pd-1.c
new file mode 100644
index 000000000..e8818a6b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14pd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrsqrt14pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vrsqrt14pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrsqrt14pd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rsqrt14_pd (x);
+  x = _mm512_mask_rsqrt14_pd (x, m, x);
+  x = _mm512_maskz_rsqrt14_pd (m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14pd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14pd-2.c
new file mode 100644
index 000000000..76e39cf80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14pd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = 1.0 / sqrt(s[i]);
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_rsqrt14_pd) (s.x);
+  res2.x = INTRINSIC (_mask_rsqrt14_pd) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_rsqrt14_pd) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN, d) (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ps-1.c
new file mode 100644
index 000000000..b766d8541
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ps-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrsqrt14ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 3 } } */
+/* { dg-final { scan-assembler-times "vrsqrt14ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vrsqrt14ps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_rsqrt14_ps (x);
+  x = _mm512_mask_rsqrt14_ps (x, m, x);
+  x = _mm512_maskz_rsqrt14_ps (m, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ps-2.c
new file mode 100644
index 000000000..4e6f77dd4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ps-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = 1.0 / sqrt(s[i]);
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_rsqrt14_ps) (s.x);
+  res2.x = INTRINSIC (_mask_rsqrt14_ps) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_rsqrt14_ps) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_ROUGH_CHECK (AVX512F_LEN,) (res1, res_ref, 0.0001))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN,) (res2, res_ref, 0.0001))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_ROUGH_CHECK (AVX512F_LEN,) (res3, res_ref, 0.0001))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14sd-1.c
new file mode 100644
index 000000000..bd8b7a84f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14sd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrsqrt14sd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_rsqrt14_sd (x1, x2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14sd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14sd-2.c
new file mode 100644
index 000000000..ef4e407f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14sd-2.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include <math.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+static void
+compute_vrsqrt14sd (double *s1, double *s2, double *r)
+{
+  r[0] = 1.0 / sqrt (s2[0]);
+  r[1] = s1[1];
+}
+
+static void
+avx512f_test (void)
+{
+  union128d s1, s2, res1, res2, res3;
+  double res_ref[2];
+
+  s1.x = _mm_set_pd (-3.0, 111.111);
+  s2.x = _mm_set_pd (222.222, 4.0);
+  res2.a[0] = DEFAULT_VALUE;
+
+  res1.x = _mm_rsqrt14_sd (s1.x, s2.x);
+
+  compute_vrsqrt14sd (s1.a, s2.a, res_ref);
+
+  if (check_fp_union128d (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ss-1.c
new file mode 100644
index 000000000..d4d4eeadc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vrsqrt14ss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_rsqrt14_ss (x1, x2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ss-2.c
new file mode 100644
index 000000000..b01420f7a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vrsqrt14ss-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include <math.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+static void
+compute_vrsqrt14ss (float *s1, float *s2, float *r)
+{
+  r[0] = 1.0 / sqrt (s2[0]);
+  r[1] = s1[1];
+  r[2] = s1[2];
+  r[3] = s1[3];
+}
+
+static void
+avx512f_test (void)
+{
+  union128 s1, s2, res1, res2, res3;
+  float res_ref[4];
+
+  s1.x = _mm_set_ps (-24.43, 68.346, -43.35, 546.46);
+  s2.x = _mm_set_ps (222.222, 333.333, 444.444, 4.0);
+  res2.a[0] = DEFAULT_VALUE;
+
+  res1.x = _mm_rsqrt14_ss (s1.x, s2.x);
+
+  compute_vrsqrt14ss (s1.a, s2.a, res_ref);
+
+  if (check_fp_union128 (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefpd-1.c
new file mode 100644
index 000000000..884a3d4af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefpd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vscalefpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vscalefpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscalefpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vscalefpd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vscalefpd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vscalefpd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_scalef_pd (x, x);
+  x = _mm512_mask_scalef_pd (x, m, x, x);
+  x = _mm512_maskz_scalef_pd (m, x, x);
+  x = _mm512_scalef_round_pd (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_scalef_round_pd (x, m, x, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_scalef_round_pd (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefpd-2.c
new file mode 100644
index 000000000..829f7418f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefpd-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include <math.h>
+
+CALC (double *r, double *s1, double *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = ldexp (s1[i], floor (s2[i]));
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_scalef_pd) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_scalef_pd) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_scalef_pd) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefps-1.c
new file mode 100644
index 000000000..8299f60ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vscalefps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vscalefps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscalefps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vscalefps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vscalefps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vscalefps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_scalef_ps (x, x);
+  x = _mm512_mask_scalef_ps (x, m, x, x);
+  x = _mm512_maskz_scalef_ps (m, x, x);
+  x = _mm512_scalef_round_ps (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_scalef_round_ps (x, m, x, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_scalef_round_ps (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefps-2.c
new file mode 100644
index 000000000..59c32369f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefps-2.c
@@ -0,0 +1,56 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include <math.h>
+
+CALC (float *r, float *s1, float *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = ldexp (s1[i], floor (s2[i]));
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, ) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_scalef_ps) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_scalef_ps) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_scalef_ps) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefsd-1.c
new file mode 100644
index 000000000..ab3a791a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefsd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vscalefsd\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscalefsd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_scalef_sd (x, x);
+  x = _mm_scalef_round_sd (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefsd-2.c
new file mode 100644
index 000000000..131fc67c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefsd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include <math.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+#define SIZE (128 / 64)
+
+static void
+compute_scalefsd (double *s1, double *s2, double *r)
+{
+  r[0] = s1[0] * pow (2, floor (s2[0]));
+  r[1] = s1[1];
+}
+
+void static
+avx512f_test (void)
+{
+  union128d res1, s1, s2;
+  double res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 11.5 * (i + 1);
+      s2.a[i] = 10.5 * (i + 1);
+    }
+
+  res1.x = _mm_scalef_sd (s1.x, s2.x);
+
+  compute_scalefsd (s1.a, s2.a, res_ref);
+
+  if (check_union128d (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefss-1.c
new file mode 100644
index 000000000..93ea8a107
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefss-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vscalefss\[ \\t\]+\[^\n\]*%xmm\[0-9\]\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscalefss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm_scalef_ss (x, x);
+  x = _mm_scalef_round_ss (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefss-2.c
new file mode 100644
index 000000000..3e8f6d193
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vscalefss-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-require-effective-target avx512f } */
+
+#include <math.h>
+#include "avx512f-check.h"
+#include "avx512f-helper.h"
+
+#define SIZE (128 / 32)
+
+static void
+compute_scalefss (float *s1, float *s2, float *r)
+{
+  r[0] = s1[0] * (float) pow (2, floor (s2[0]));
+  r[1] = s1[1];
+  r[2] = s1[2];
+  r[3] = s1[3];
+}
+
+static void
+avx512f_test (void)
+{
+  union128 res1, s1, s2;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 11.5 * (i + 1);
+      s2.a[i] = 10.5 * (i + 1);
+    }
+
+  res1.x = _mm_scalef_ss (s1.x, s2.x);
+
+  compute_scalefss (s1.a, s2.a, res_ref);
+
+  if (check_union128 (res1, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-1.c
new file mode 100644
index 000000000..712b31482
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vshuff32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vshuff32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vshuff32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+__m512 x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_shuffle_f32x4 (x, x, 56);
+  x = _mm512_mask_shuffle_f32x4 (x, 4, x, x, 56);
+  x = _mm512_maskz_shuffle_f32x4 (6, x, x, 56);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c
new file mode 100644
index 000000000..271c8624b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff32x4-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "string.h"
+
+void
+CALC (float *e, UNION_TYPE (AVX512F_LEN,) s1, UNION_TYPE (AVX512F_LEN,) s2,
+      int imm)
+{
+  int i, offset, selector;
+  float *source;
+  for (i = 0; i < SIZE / 4; i++)
+    {
+
+#if AVX512F_LEN == 512
+      selector = (imm >> i * 2) & 0x3;
+#else
+      selector = (imm >> i) & 0x1;
+#endif
+
+      offset = i * 4;
+      source = i * 4 * 32 < AVX512F_LEN / 2 ? s1.a : s2.a;
+      memcpy (e + offset, source + selector * 4, 16);
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) u1, u2, u3, s1, s2;
+  MASK_TYPE mask = MASK_VALUE;
+  float e[SIZE];
+  int i;
+  int imm = 203;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 1.2 / (i + 0.378);
+      s1.a[i] = 91.02 / (i + 4.3578);
+      u1.a[i] = DEFAULT_VALUE;
+      u2.a[i] = DEFAULT_VALUE;
+      u3.a[i] = DEFAULT_VALUE;
+    }
+
+  u1.x = INTRINSIC (_shuffle_f32x4) (s1.x, s2.x, imm);
+  u2.x = INTRINSIC (_mask_shuffle_f32x4) (u2.x, mask, s1.x, s2.x, imm);
+  u3.x = INTRINSIC (_maskz_shuffle_f32x4) (mask, s1.x, s2.x, imm);
+
+  CALC (e, s1, s2, imm);
+
+  if (UNION_CHECK (AVX512F_LEN,) (u1, e))
+    abort ();
+
+  MASK_MERGE ()(e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (u2, e))
+    abort ();
+
+  MASK_ZERO ()(e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (u3, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-1.c
new file mode 100644
index 000000000..c5ac373cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vshuff64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vshuff64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vshuff64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+__m512d x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_shuffle_f64x2 (x, x, 56);
+  x = _mm512_maskz_shuffle_f64x2 (3, x, x, 56);
+  x = _mm512_mask_shuffle_f64x2 (x, 3, x, x, 56);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c
new file mode 100644
index 000000000..4842942ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshuff64x2-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "string.h"
+
+void
+CALC (double *e, UNION_TYPE (AVX512F_LEN, d) s1,
+      UNION_TYPE (AVX512F_LEN, d) s2, int imm)
+{
+  int i, offset, selector;
+  double *source;
+  for (i = 0; i < SIZE / 2; i++)
+    {
+
+#if AVX512F_LEN == 512
+      selector = (imm >> i * 2) & 0x3;
+#else
+      selector = (imm >> i) & 0x1;
+#endif
+
+      offset = i * 2;
+      source = i * 2 * 64 < AVX512F_LEN / 2 ? s1.a : s2.a;
+      memcpy (e + offset, source + selector * 2, 16);
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) u1, u2, u3, s1, s2;
+  MASK_TYPE mask = MASK_VALUE;
+  double e[SIZE];
+  int i;
+  int imm = 203;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 1.2 / (i + 0.378);
+      s1.a[i] = 91.02 / (i + 4.3578);
+      u1.a[i] = DEFAULT_VALUE;
+      u2.a[i] = DEFAULT_VALUE;
+      u3.a[i] = DEFAULT_VALUE;
+    }
+
+  u1.x = INTRINSIC (_shuffle_f64x2) (s1.x, s2.x, imm);
+  u2.x = INTRINSIC (_mask_shuffle_f64x2) (u2.x, mask, s1.x, s2.x, imm);
+  u3.x = INTRINSIC (_maskz_shuffle_f64x2) (mask, s1.x, s2.x, imm);
+
+  CALC (e, s1, s2, imm);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (u1, e))
+    abort ();
+
+  MASK_MERGE (d) (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (u2, e))
+    abort ();
+
+  MASK_ZERO (d) (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (u3, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-1.c
new file mode 100644
index 000000000..8e48fdf7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vshufi32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vshufi32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vshufi32x4\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+__m512i x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_shuffle_i32x4 (x, x, 56);
+  x = _mm512_mask_shuffle_i32x4 (x, 8, x, x, 56);
+  x = _mm512_maskz_shuffle_i32x4 (8, x, x, 56);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-2.c
new file mode 100644
index 000000000..105c71568
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi32x4-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+#include "string.h"
+
+void
+CALC (int *e, UNION_TYPE (AVX512F_LEN, i_d) s1,
+      UNION_TYPE (AVX512F_LEN, i_d) s2, int imm)
+{
+  int i, offset, selector;
+  int *source;
+  for (i = 0; i < SIZE / 4; i++)
+    {
+
+#if AVX512F_LEN == 512
+      selector = (imm >> i * 2) & 0x3;
+#else
+      selector = (imm >> i) & 0x1;
+#endif
+
+      offset = i * 4;
+      source = i * 4 * 32 < AVX512F_LEN / 2 ? s1.a : s2.a;
+      memcpy (e + offset, source + selector * 4, 16);
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_d) u1, u2, u3, s1, s2;
+  MASK_TYPE mask = MASK_VALUE;
+  int e[SIZE];
+  int i;
+  int imm = 203;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 1.2 / (i + 0.378);
+      s1.a[i] = 91.02 / (i + 4.3578);
+      u1.a[i] = DEFAULT_VALUE;
+      u2.a[i] = DEFAULT_VALUE;
+      u3.a[i] = DEFAULT_VALUE;
+    }
+
+  u1.x = INTRINSIC (_shuffle_i32x4) (s1.x, s2.x, imm);
+  u2.x = INTRINSIC (_mask_shuffle_i32x4) (u2.x, mask, s1.x, s2.x, imm);
+  u3.x = INTRINSIC (_maskz_shuffle_i32x4) (mask, s1.x, s2.x, imm);
+
+  CALC (e, s1, s2, imm);
+
+  if (UNION_CHECK (AVX512F_LEN, i_d) (u1, e))
+    abort ();
+
+  MASK_MERGE (i_d) (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (u2, e))
+    abort ();
+
+  MASK_ZERO (i_d) (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_d) (u3, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-1.c
new file mode 100644
index 000000000..5bb5c8f63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vshufi64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vshufi64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vshufi64x2\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+__m512i x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_shuffle_i64x2 (x, x, 56);
+  x = _mm512_mask_shuffle_i64x2 (x, 3, x, x, 56);
+  x = _mm512_maskz_shuffle_i64x2 (2, x, x, 56);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-2.c
new file mode 100644
index 000000000..d79d8f6bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufi64x2-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+#include "string.h"
+
+void
+CALC (long long *e, UNION_TYPE (AVX512F_LEN, i_q) s1,
+      UNION_TYPE (AVX512F_LEN, i_q) s2, int imm)
+{
+  int i, offset, selector;
+  long long *source;
+  for (i = 0; i < SIZE / 2; i++)
+    {
+
+#if AVX512F_LEN == 512
+      selector = (imm >> i * 2) & 0x3;
+#else
+      selector = (imm >> i) & 0x1;
+#endif
+
+      offset = i * 2;
+      source = i * 2 * 64 < AVX512F_LEN / 2 ? s1.a : s2.a;
+      memcpy (e + offset, source + selector * 2, 16);
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, i_q) u1, u2, u3, s1, s2;
+  MASK_TYPE mask = MASK_VALUE;
+  long long e[SIZE];
+  int i;
+  int imm = 203;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 1.2 / (i + 0.378);
+      s1.a[i] = 91.02 / (i + 4.3578);
+      u1.a[i] = DEFAULT_VALUE;
+      u2.a[i] = DEFAULT_VALUE;
+      u3.a[i] = DEFAULT_VALUE;
+    }
+
+  u1.x = INTRINSIC (_shuffle_i64x2) (s1.x, s2.x, imm);
+  u2.x = INTRINSIC (_mask_shuffle_i64x2) (u2.x, mask, s1.x, s2.x, imm);
+  u3.x = INTRINSIC (_maskz_shuffle_i64x2) (mask, s1.x, s2.x, imm);
+
+  CALC (e, s1, s2, imm);
+
+  if (UNION_CHECK (AVX512F_LEN, i_q) (u1, e))
+    abort ();
+
+  MASK_MERGE (i_q) (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (u2, e))
+    abort ();
+
+  MASK_ZERO (i_q) (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, i_q) (u3, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufpd-1.c
new file mode 100644
index 000000000..420a6cfd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufpd-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vshufpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vshufpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vshufpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+__m512d x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_shuffle_pd (x, x, 56);
+  x = _mm512_mask_shuffle_pd (x, 2, x, x, 56);
+  x = _mm512_maskz_shuffle_pd (2, x, x, 56);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufpd-2.c
new file mode 100644
index 000000000..d70228af1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufpd-2.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+void static
+CALC (double *e, UNION_TYPE (AVX512F_LEN, d) s1,
+      UNION_TYPE (AVX512F_LEN, d) s2, int imm)
+{
+  e[0] = (imm & (1 << 0)) ? s1.a[1] : s1.a[0];
+  e[1] = (imm & (1 << 1)) ? s2.a[1] : s2.a[0];
+#if AVX512F_LEN > 128
+  e[2] = (imm & (1 << 2)) ? s1.a[3] : s1.a[2];
+  e[3] = (imm & (1 << 3)) ? s2.a[3] : s2.a[2];
+#if AVX512F_LEN > 256
+  e[4] = (imm & (1 << 4)) ? s1.a[5] : s1.a[4];
+  e[5] = (imm & (1 << 5)) ? s2.a[5] : s2.a[4];
+  e[6] = (imm & (1 << 6)) ? s1.a[7] : s1.a[6];
+  e[7] = (imm & (1 << 7)) ? s2.a[7] : s2.a[6];
+#endif
+#endif
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) u1, u2, u3, s1, s2;
+  double e[SIZE];
+  MASK_TYPE mask = MASK_VALUE;
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 2134.3343 * i + 54846.4641;
+      s2.a[i] = 856.43576 * i + 1124.209;
+      u1.a[i] = DEFAULT_VALUE;
+      u2.a[i] = DEFAULT_VALUE;
+      u3.a[i] = DEFAULT_VALUE;
+    }
+
+  u1.x = INTRINSIC (_shuffle_pd) (s1.x, s2.x, 120);
+  u2.x = INTRINSIC (_mask_shuffle_pd) (u2.x, mask, s1.x, s2.x, 120);
+  u3.x = INTRINSIC (_maskz_shuffle_pd) (mask, s1.x, s2.x, 120);
+  CALC (e, s1, s2, 120);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (u1, e))
+    abort ();
+
+  MASK_MERGE (d) (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (u2, e))
+    abort ();
+
+  MASK_ZERO (d) (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (u3, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufps-1.c
new file mode 100644
index 000000000..e3dbf0751
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufps-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vshufps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vshufps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vshufps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+__m512 x;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_shuffle_ps (x, x, 56);
+  x = _mm512_mask_shuffle_ps (x, 2, x, x, 56);
+  x = _mm512_maskz_shuffle_ps (2, x, x, 56);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufps-2.c
new file mode 100644
index 000000000..ed378d1c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vshufps-2.c
@@ -0,0 +1,74 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+void
+CALC (float *e, UNION_TYPE (AVX512F_LEN,) s1, UNION_TYPE (AVX512F_LEN,) s2,
+      int imm)
+{
+  e[0] = s1.a[(imm >> 0) & 0x3];
+  e[1] = s1.a[(imm >> 2) & 0x3];
+  e[2] = s2.a[(imm >> 4) & 0x3];
+  e[3] = s2.a[(imm >> 6) & 0x3];
+#if AVX512F_LEN > 128
+  e[4] = s1.a[4 + ((imm >> 0) & 0x3)];
+  e[5] = s1.a[4 + ((imm >> 2) & 0x3)];
+  e[6] = s2.a[4 + ((imm >> 4) & 0x3)];
+  e[7] = s2.a[4 + ((imm >> 6) & 0x3)];
+#if AVX512F_LEN > 256
+  e[8] = s1.a[8 + ((imm >> 0) & 0x3)];
+  e[9] = s1.a[8 + ((imm >> 2) & 0x3)];
+  e[10] = s2.a[8 + ((imm >> 4) & 0x3)];
+  e[11] = s2.a[8 + ((imm >> 6) & 0x3)];
+  e[12] = s1.a[12 + ((imm >> 0) & 0x3)];
+  e[13] = s1.a[12 + ((imm >> 2) & 0x3)];
+  e[14] = s2.a[12 + ((imm >> 4) & 0x3)];
+  e[15] = s2.a[12 + ((imm >> 6) & 0x3)];
+#endif
+#endif
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) u1, u2, u3, s1, s2;
+  float e[SIZE];
+  int i, sign;
+  MASK_TYPE mask = MASK_VALUE;
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = 1.5 + 34.67 * i * sign;
+      s2.a[i] = -22.17 * i * sign;
+      u1.a[i] = DEFAULT_VALUE;
+      u2.a[i] = DEFAULT_VALUE;
+      u3.a[i] = DEFAULT_VALUE;
+      sign = sign * -1;
+    }
+
+
+  u1.x = INTRINSIC (_shuffle_ps) (s1.x, s2.x, 203);
+  u2.x = INTRINSIC (_mask_shuffle_ps) (u2.x, mask, s1.x, s2.x, 203);
+  u3.x = INTRINSIC (_maskz_shuffle_ps) (mask, s1.x, s2.x, 203);
+
+  CALC (e, s1, s2, 203);
+
+  if (UNION_CHECK (AVX512F_LEN,) (u1, e))
+    abort ();
+
+  MASK_MERGE ()(e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (u2, e))
+    abort ();
+
+  MASK_ZERO ()(e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (u3, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtpd-1.c
new file mode 100644
index 000000000..cd85b291c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtpd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vsqrtpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vsqrtpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vsqrtpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vsqrtpd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vsqrtpd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vsqrtpd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sqrt_pd (x);
+  x = _mm512_mask_sqrt_pd (x, m, x);
+  x = _mm512_maskz_sqrt_pd (m, x);
+  x = _mm512_sqrt_round_pd (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_sqrt_round_pd (x, m, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_sqrt_round_pd (m, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtpd-2.c
new file mode 100644
index 000000000..27b649157
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtpd-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (double *s, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = sqrt(s[i]);
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_sqrt_pd) (s.x);
+  res2.x = INTRINSIC (_mask_sqrt_pd) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_sqrt_pd) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_FP_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_FP_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_FP_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtps-1.c
new file mode 100644
index 000000000..0e7fcb5e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vsqrtps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vsqrtps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vsqrtps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vsqrtps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vsqrtps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vsqrtps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sqrt_ps (x);
+  x = _mm512_mask_sqrt_ps (x, m, x);
+  x = _mm512_maskz_sqrt_ps (m, x);
+  x = _mm512_sqrt_round_ps (x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_sqrt_round_ps (x, m, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_sqrt_round_ps (m, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtps-2.c
new file mode 100644
index 000000000..4fc45e395
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtps-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#include <math.h>
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (float *s, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = sqrt(s[i]);
+    }
+}
+
+static void
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) s, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s.a[i] = 123.456 * (i + 2000);
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_sqrt_ps) (s.x);
+  res2.x = INTRINSIC (_mask_sqrt_ps) (res2.x, mask, s.x);
+  res3.x = INTRINSIC (_maskz_sqrt_ps) (mask, s.x);
+
+  CALC (s.a, res_ref);
+
+  if (UNION_FP_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_FP_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_FP_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtsd-1.c
new file mode 100644
index 000000000..80ad41403
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vsqrtsd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_sqrt_round_sd (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtss-1.c
new file mode 100644
index 000000000..a3bb68f79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsqrtss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vsqrtss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_sqrt_round_ss (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubpd-1.c
new file mode 100644
index 000000000..5a9cc9fb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubpd-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vsubpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vsubpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vsubpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vsubpd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vsubpd\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vsubpd\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sub_pd (x, x);
+  x = _mm512_mask_sub_pd (x, m, x, x);
+  x = _mm512_maskz_sub_pd (m, x, x);
+  x = _mm512_sub_round_pd (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_sub_round_pd (x, m, x, x, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_sub_round_pd (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubpd-2.c
new file mode 100644
index 000000000..a462631b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+CALC (double *r, double *s1, double *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] - s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN, d) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_sub_pd) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_sub_pd) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_sub_pd) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubps-1.c
new file mode 100644
index 000000000..7f711f316
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubps-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\[^\{\]" 6 } } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 2 } } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 2 } } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%zmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+/* { dg-final { scan-assembler-times "vsubps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x;
+volatile __mmask16 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_sub_ps (x, x);
+  x = _mm512_mask_sub_ps (x, m, x, x);
+  x = _mm512_maskz_sub_ps (m, x, x);
+  x = _mm512_sub_round_ps (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+  x = _mm512_mask_sub_round_ps (x, m, x, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+  x = _mm512_maskz_sub_round_ps (m, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubps-2.c
new file mode 100644
index 000000000..366b7e744
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubps-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+CALC (float *r, float *s1, float *s2)
+{
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      r[i] = s1[i] - s2[i];
+    }
+}
+
+void static
+TEST (void)
+{
+  int i, sign;
+  UNION_TYPE (AVX512F_LEN,) res1, res2, res3, src1, src2;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+
+  sign = -1;
+  for (i = 0; i < SIZE; i++)
+    {
+      src1.a[i] = 1.5 + 34.67 * i * sign;
+      src2.a[i] = -22.17 * i * sign;
+      sign = sign * -1;
+    }
+  for (i = 0; i < SIZE; i++)
+    res2.a[i] = DEFAULT_VALUE;
+
+  res1.x = INTRINSIC (_sub_ps) (src1.x, src2.x);
+  res2.x = INTRINSIC (_mask_sub_ps) (res2.x, mask, src1.x, src2.x);
+  res3.x = INTRINSIC (_maskz_sub_ps) (mask, src1.x, src2.x);
+
+  CALC (res_ref, src1.a, src2.a);
+
+  if (UNION_CHECK (AVX512F_LEN,) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN,) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubsd-1.c
new file mode 100644
index 000000000..ad552f765
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubsd-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vsubsd\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128d x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_sub_round_sd (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubss-1.c
new file mode 100644
index 000000000..809c51597
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vsubss-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vsubss\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%xmm\[0-9\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128 x1, x2;
+
+void extern
+avx512f_test (void)
+{
+  x1 = _mm_sub_round_ss (x1, x2, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vucomisd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vucomisd-1.c
new file mode 100644
index 000000000..da0df7620
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vucomisd-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vucomisd\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm"  } } */
+
+#include <immintrin.h>
+
+volatile __m128d x;
+volatile int res;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm_comi_round_sd (x, x, _CMP_NLE_UQ, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vucomiss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vucomiss-1.c
new file mode 100644
index 000000000..d4355de0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vucomiss-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler "vucomiss\[ \\t\]+\[^\n\]*\{sae\}\[^\n\]*%xmm"  } } */
+
+#include <immintrin.h>
+
+volatile __m128 x;
+volatile int res;
+
+void extern
+avx512f_test (void)
+{
+  res = _mm_comi_round_ss (x, x, _CMP_EQ_OQ, _MM_FROUND_NO_EXC);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhpd-1.c
new file mode 100644
index 000000000..2ce55e446
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhpd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vunpckhpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vunpckhpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vunpckhpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x, y, z;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_unpackhi_pd (y, z);
+  x = _mm512_mask_unpackhi_pd (x, m, y, z);
+  x = _mm512_maskz_unpackhi_pd (m, y, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhpd-2.c
new file mode 100644
index 000000000..60898bbf2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+void static
+CALC (double *s1, double *s2, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      r[2 * i] = s1[2 * i + 1];
+      r[2 * i + 1] = s2[2 * i + 1];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * 123.2 + 32.6;
+      s2.a[i] = i + 2.5;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_unpackhi_pd) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_unpackhi_pd) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_unpackhi_pd) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhps-1.c
new file mode 100644
index 000000000..9567272c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhps-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vunpckhps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vunpckhps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vunpckhps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x, y, z;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_unpackhi_ps (y, z);
+  x = _mm512_mask_unpackhi_ps (x, m, y, z);
+  x = _mm512_maskz_unpackhi_ps (m, y, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhps-2.c
new file mode 100644
index 000000000..6047985bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpckhps-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+void static
+CALC (float *s1, float *s2, float *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE / 4; i++)
+    {
+      r[4 * i] = s1[4 * i + 2];
+      r[4 * i + 1] = s2[4 * i + 2];
+      r[4 * i + 2] = s1[4 * i + 3];
+      r[4 * i + 3] = s2[4 * i + 3];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, ) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  float res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * 123.2 + 32.6;
+      s2.a[i] = i + 2.5;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_unpackhi_ps) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_unpackhi_ps) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_unpackhi_ps) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, ) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO () (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklpd-1.c
new file mode 100644
index 000000000..5a7303784
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklpd-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vunpcklpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vunpcklpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vunpcklpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512d x, y, z;
+volatile __mmask8 m;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_unpacklo_pd (y, z);
+  x = _mm512_mask_unpacklo_pd (x, m, y, z);
+  x = _mm512_maskz_unpacklo_pd (m, y, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklpd-2.c
new file mode 100644
index 000000000..3317e4acf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklpd-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 64)
+#include "avx512f-mask-type.h"
+
+void static
+CALC (double *s1, double *s2, double *r)
+{
+  int i;
+
+  for (i = 0; i < SIZE / 2; i++)
+    {
+      r[2 * i] = s1[2 * i];
+      r[2 * i + 1] = s2[2 * i];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN, d) s1, s2, res1, res2, res3;
+  MASK_TYPE mask = MASK_VALUE;
+  double res_ref[SIZE];
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * 123.2 + 32.6;
+      s2.a[i] = i + 2.5;
+      res2.a[i] = DEFAULT_VALUE;
+    }
+
+  res1.x = INTRINSIC (_unpacklo_pd) (s1.x, s2.x);
+  res2.x = INTRINSIC (_mask_unpacklo_pd) (res2.x, mask, s1.x, s2.x);
+  res3.x = INTRINSIC (_maskz_unpacklo_pd) (mask, s1.x, s2.x);
+
+  CALC (s1.a, s2.a, res_ref);
+
+  if (UNION_CHECK (AVX512F_LEN, d) (res1, res_ref))
+    abort ();
+
+  MASK_MERGE (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res2, res_ref))
+    abort ();
+
+  MASK_ZERO (d) (res_ref, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, d) (res3, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklps-1.c
new file mode 100644
index 000000000..a007a050b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklps-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vunpcklps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 3 } } */
+/* { dg-final { scan-assembler-times "vunpcklps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\{z\}" 1 } } */
+/* { dg-final { scan-assembler-times "vunpcklps\[ \\t\]+\[^\n\]*%zmm\[0-9\]\{%k\[1-7\]\}\[^\{\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512 x, y, z;
+
+void extern
+avx512f_test (void)
+{
+  x = _mm512_unpacklo_ps (y, z);
+  x = _mm512_mask_unpacklo_ps (x, 2, y, z);
+  x = _mm512_maskz_unpacklo_ps (2, y, z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklps-2.c
new file mode 100644
index 000000000..538a9fa80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f-vunpcklps-2.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f" } */
+/* { dg-require-effective-target avx512f } */
+
+#define AVX512F
+
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+#include "avx512f-mask-type.h"
+
+void static
+CALC (float *e, float *s1, float *s2)
+{
+  int i;
+  for (i = 0; i < SIZE / 4; i++)
+    {
+      e[4 * i] = s1[4 * i];
+      e[4 * i + 1] = s2[4 * i];
+      e[4 * i + 2] = s1[4 * i + 1];
+      e[4 * i + 3] = s2[4 * i + 1];
+    }
+}
+
+void static
+TEST (void)
+{
+  UNION_TYPE (AVX512F_LEN,) s1, s2, u1, u2, u3;
+  MASK_TYPE mask = MASK_VALUE;
+  float e[SIZE];
+  int i;
+  for (i = 0; i < SIZE; i++)
+    {
+      s1.a[i] = i * 123.2 + 32.6;
+      s2.a[i] = i + 2.5;
+      u1.a[i]= DEFAULT_VALUE;
+      u2.a[i]= DEFAULT_VALUE;
+      u3.a[i]= DEFAULT_VALUE;
+    }
+
+  u1.x = INTRINSIC (_unpacklo_ps) (s1.x, s2.x);
+  u2.x = INTRINSIC (_mask_unpacklo_ps) (u2.x, mask, s1.x, s2.x);
+  u3.x = INTRINSIC (_maskz_unpacklo_ps) (mask, s1.x, s2.x);
+
+  CALC (e, s1.a, s2.a);
+
+  if (UNION_CHECK (AVX512F_LEN,) (u1, e))
+    abort ();
+
+  MASK_MERGE () (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (u2, e))
+    abort ();
+
+  MASK_ZERO () (e, mask, SIZE);
+  if (UNION_CHECK (AVX512F_LEN, ) (u3, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_cond_move.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_cond_move.c
new file mode 100644
index 000000000..c06ee2631
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_cond_move.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx512f" } */
+/* { dg-final { scan-assembler "(vpblendmd|vmovdqa32)" } } */
+
+unsigned int x[128];
+unsigned int y[128];
+
+void
+foo () 
+{
+  int i;
+  for (i = 0; i < 128; i++)
+    x[i] = y[i] > 3 ? 2 : 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_evex_reg_asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_evex_reg_asm-1.c
new file mode 100644
index 000000000..34a435378
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_evex_reg_asm-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f -ffixed-xmm0 -ffixed-xmm1 -ffixed-xmm2 -ffixed-xmm3 -ffixed-xmm4 -ffixed-xmm5 -ffixed-xmm6 -ffixed-xmm7 -ffixed-xmm8 -ffixed-xmm9 -ffixed-xmm10 -ffixed-xmm11 -ffixed-xmm12 -ffixed-xmm13 -ffixed-xmm14 -ffixed-xmm15" } */
+
+volatile float a,b,c,d;
+
+void foo()
+{
+     __asm__ __volatile__( "vcmpss $1,%1, %2,%3;" : "=x"(c) : "x"(a),"x"(b),"x"(d) );/* { dg-error "inconsistent operand constraints" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_evex_reg_asm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_evex_reg_asm-2.c
new file mode 100644
index 000000000..a0a268559
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512f_evex_reg_asm-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mavx512f -ffixed-xmm0 -ffixed-xmm1 -ffixed-xmm2 -ffixed-xmm3 -ffixed-xmm4 -ffixed-xmm5 -ffixed-xmm6 -ffixed-xmm7 -ffixed-xmm8 -ffixed-xmm9 -ffixed-xmm10 -ffixed-xmm11 -ffixed-xmm12 -ffixed-xmm13 -ffixed-xmm14 -ffixed-xmm15" } */
+/* { dg-final { scan-assembler "vaddss\[ \\t\]+\[^\n\]*%xmm(1\[6-9\]|2\[0-9\]|3\[0-1\])\[^\{\]" } } */
+
+volatile float a, b, c, d;
+
+void foo()
+{
+  __asm__ __volatile__( "vaddss %1, %2, %3;" : "=v"(c) : "v"(a),"v"(b),"v"(d) );
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0dpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0dpd-1.c
new file mode 100644
index 000000000..9051a1620
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0dpd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vgatherpf0dpd\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i idx;
+volatile __mmask8 m8;
+void *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_mask_prefetch_i32gather_pd (idx, m8, base, 8, _MM_HINT_T0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0dps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0dps-1.c
new file mode 100644
index 000000000..bda31d77b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0dps-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vgatherpf0dps\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask16 m16;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_mask_prefetch_i32gather_ps (idx, m16, base, 8, _MM_HINT_T0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0qpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0qpd-1.c
new file mode 100644
index 000000000..34bcecfe2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0qpd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vgatherpf0qpd\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_mask_prefetch_i64gather_pd (idx, m8, base, 8, _MM_HINT_T0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0qps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0qps-1.c
new file mode 100644
index 000000000..a9011b081
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf0qps-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vgatherpf0qps\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_mask_prefetch_i64gather_ps (idx, m8, base, 8, _MM_HINT_T0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1dpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1dpd-1.c
new file mode 100644
index 000000000..a16f4d395
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1dpd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vgatherpf1dpd\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_mask_prefetch_i32gather_pd (idx, m8, base, 8, _MM_HINT_T1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1dps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1dps-1.c
new file mode 100644
index 000000000..c43152b01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1dps-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vgatherpf1dps\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask16 m16;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_mask_prefetch_i32gather_ps (idx, m16, base, 8, _MM_HINT_T1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1qpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1qpd-1.c
new file mode 100644
index 000000000..ab9e35166
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1qpd-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vgatherpf1qpd\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_mask_prefetch_i64gather_pd (idx, m8, base, 8, _MM_HINT_T1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1qps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1qps-1.c
new file mode 100644
index 000000000..28d7cd666
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vgatherpf1qps-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vgatherpf1qps\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_mask_prefetch_i64gather_ps (idx, m8, base, 8, _MM_HINT_T1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0dpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0dpd-1.c
new file mode 100644
index 000000000..14d5c9744
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0dpd-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vscatterpf0dpd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscatterpf0dpd\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i idx;
+volatile __mmask8 m8;
+void *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_prefetch_i32scatter_pd (base, idx, 8, _MM_HINT_T0);
+  _mm512_mask_prefetch_i32scatter_pd (base, m8, idx, 8, _MM_HINT_ET0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0dps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0dps-1.c
new file mode 100644
index 000000000..05f51f2bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0dps-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vscatterpf0dps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscatterpf0dps\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask16 m16;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_prefetch_i32scatter_ps (base, idx, 8, _MM_HINT_T0);
+  _mm512_mask_prefetch_i32scatter_ps (base, m16, idx, 8, _MM_HINT_ET0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0qpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0qpd-1.c
new file mode 100644
index 000000000..93a65a8c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0qpd-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vscatterpf0qpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscatterpf0qpd\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask8 m8;
+void *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_prefetch_i64scatter_pd (base, idx, 8, _MM_HINT_T0);
+  _mm512_mask_prefetch_i64scatter_pd (base, m8, idx, 8, _MM_HINT_ET0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0qps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0qps-1.c
new file mode 100644
index 000000000..1f9b97363
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf0qps-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vscatterpf0qps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscatterpf0qps\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_prefetch_i64scatter_ps (base, idx, 8, _MM_HINT_T0);
+  _mm512_mask_prefetch_i64scatter_ps (base, m8, idx, 8, _MM_HINT_ET0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1dpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1dpd-1.c
new file mode 100644
index 000000000..04c367ca3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1dpd-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vscatterpf1dpd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscatterpf1dpd\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256i idx;
+volatile __mmask8 m8;
+void *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_prefetch_i32scatter_pd (base, idx, 8, _MM_HINT_T1);
+  _mm512_mask_prefetch_i32scatter_pd (base, m8, idx, 8, _MM_HINT_ET1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1dps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1dps-1.c
new file mode 100644
index 000000000..a76b77c63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1dps-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vscatterpf1dps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscatterpf1dps\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask16 m16;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_prefetch_i32scatter_ps (base, idx, 8, _MM_HINT_T1);
+  _mm512_mask_prefetch_i32scatter_ps (base, m16, idx, 8, _MM_HINT_ET1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1qpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1qpd-1.c
new file mode 100644
index 000000000..7a5747cfe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1qpd-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vscatterpf1qpd\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscatterpf1qpd\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_prefetch_i64scatter_pd (base, idx, 8, _MM_HINT_T1);
+  _mm512_mask_prefetch_i64scatter_pd (base, m8, idx, 8, _MM_HINT_ET1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1qps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1qps-1.c
new file mode 100644
index 000000000..d0372b7b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avx512pf-vscatterpf1qps-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512pf -O2" } */
+/* { dg-final { scan-assembler-times "vscatterpf1qps\[ \\t\]+\[^\n\]*%zmm\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "vscatterpf1qps\[ \\t\]+\[^\n\]*\{%k\[1-7\]" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i idx;
+volatile __mmask8 m8;
+int *base;
+
+void extern
+avx512pf_test (void)
+{
+  _mm512_prefetch_i64scatter_ps (base, idx, 8, _MM_HINT_T1);
+  _mm512_mask_prefetch_i64scatter_ps (base, m8, idx, 8, _MM_HINT_ET1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avxfp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avxfp-1.c
new file mode 100644
index 000000000..70bc8f1ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avxfp-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+/* { dg-final { scan-assembler "vmaxsd" } } */
+/* { dg-final { scan-assembler "vminsd" } } */
+double x;
+t()
+{
+  x=x>5?x:5;
+}
+
+double x;
+q()
+{
+  x=x<5?x:5;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/avxfp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/avxfp-2.c
new file mode 100644
index 000000000..c34a1bd7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/avxfp-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mfpmath=sse" } */
+/* { dg-final { scan-assembler "vmaxsd" } } */
+/* { dg-final { scan-assembler "vminsd" } } */
+double x;
+q()
+{
+  x=x<5?5:x;
+}
+
+double x;
+q1()
+{
+  x=x>5?5:x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield1.c
new file mode 100644
index 000000000..00b7bfd71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield1.c
@@ -0,0 +1,55 @@
+// Test for bitfield alignment in structs on IA-32
+// { dg-do run }
+// { dg-require-effective-target ia32 }
+// { dg-options "-O2" }
+// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-interix* i?86-*-cygwin* i?86-*-mingw*} }
+
+extern void abort (void);
+extern void exit (int);
+
+struct A
+{
+  char a;
+  long long b : 61;
+  char c;
+} a, a4[4];
+
+struct B
+{
+  char d;
+  struct A e;
+  char f;
+} b;
+
+struct C
+{
+  char g;
+  union U
+  {
+    char u1;
+    long long u2;
+    long long u3 : 64;
+  } h;
+  char i;
+} c;
+
+int main (void)
+{
+  if (&a.c - &a.a != 12)
+    abort ();
+  if (sizeof (a) != 16)
+    abort ();
+  if (sizeof (a4) != 4 * 16)
+    abort ();
+  if (sizeof (b) != 2 * 4 + 16)
+    abort ();
+  if (__alignof__ (b.e) != 4)
+    abort ();
+  if (&c.i - &c.g != 12)
+    abort ();
+  if (sizeof (c) != 16)
+    abort ();
+  if (__alignof__ (c.h) != 4)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield2.c
new file mode 100644
index 000000000..e40059892
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield2.c
@@ -0,0 +1,23 @@
+// Test for bitfield alignment in structs on IA-32
+// { dg-do run }
+// { dg-require-effective-target ia32 }
+// { dg-options "-O2" }
+// { dg-options "-mno-align-double -mno-ms-bitfields" { target i?86-*-interix* i?86-*-cygwin* i?86-*-mingw* } }
+
+extern void abort (void);
+extern void exit (int);
+
+struct X {
+  char a;
+  long long : 0;
+  char b;
+} x;
+
+int main () {
+  if (&x.b - &x.a != 4)
+    abort ();
+  if (sizeof (x) != 5)
+    abort ();
+  
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield3.c
new file mode 100644
index 000000000..1a161597c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bitfield3.c
@@ -0,0 +1,25 @@
+// Test for bitfield alignment in structs on IA-32
+// { dg-do run }
+// { dg-options "-O2" }
+// { dg-additional-options "-mno-align-double -mno-ms-bitfields" { target *-*-interix* } }
+// { dg-additional-options "-mno-ms-bitfields" { target *-*-mingw* } }
+
+extern void abort (void);
+extern void exit (int);
+
+struct X {
+  int : 32;
+};
+
+struct Y {
+  int i : 32;
+};
+
+int main () {
+  if (__alignof__(struct X) != 1)
+    abort ();
+  if (__alignof__(struct Y) != 4)
+    abort ();
+  
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-1.c
new file mode 100644
index 000000000..a05cb275a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-1.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi " } */
+/* { dg-final { scan-assembler "andn\[^\\n]*eax" } } */
+/* { dg-final { scan-assembler-times "bextr\[ \\t]+\[^\\n]*eax" 2 } } */
+/* { dg-final { scan-assembler "blsi\[^\\n]*eax" } } */
+/* { dg-final { scan-assembler "blsmsk\[^\\n]*eax" } } */
+/* { dg-final { scan-assembler "blsr\[^\\n]*eax" } } */
+/* { dg-final { scan-assembler "tzcntl\[^\\n]*eax" } } */
+
+#include <x86intrin.h>
+
+unsigned int
+func_andn32 (unsigned int X, unsigned int Y)
+{
+  return __andn_u32(X, Y);
+}
+
+unsigned int
+func_bextr32 (unsigned int X, unsigned int Y)
+{
+  return __bextr_u32(X, Y);
+}
+
+unsigned int
+func_bextr32_3args (unsigned int X,
+		    unsigned int Y,
+		    unsigned int Z)
+{
+  return _bextr_u32(X, Y, Z);
+}
+
+unsigned int
+func_blsi32 (unsigned int X)
+{
+  return __blsi_u32(X);
+}
+
+unsigned int
+func_blsmsk32 (unsigned int X)
+{
+  return __blsmsk_u32(X);
+}
+
+unsigned int
+func_blsr32 (unsigned int X)
+{
+  return __blsr_u32(X);
+}
+
+unsigned int
+func_tzcnt32 (unsigned int X)
+{
+  return __tzcnt_u32(X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-2.c
new file mode 100644
index 000000000..68d06a205
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-2.c
@@ -0,0 +1,54 @@
+/* { dg-do compile { target { ! { ia32 }  } } } */
+/* { dg-options "-O2 -mbmi " } */
+/* { dg-final { scan-assembler "andn\[^\\n]*rax" } } */
+/* { dg-final { scan-assembler-times "bextr\[ \\t]+\[^\\n]*rax" 2 } } */
+/* { dg-final { scan-assembler "blsi\[^\\n]*rax" } } */
+/* { dg-final { scan-assembler "blsmsk\[^\\n]*rax" } } */
+/* { dg-final { scan-assembler "blsr\[^\\n]*rax" } } */
+/* { dg-final { scan-assembler "tzcntq\[^\\n]*rax" } } */
+
+#include <x86intrin.h>
+
+unsigned long long
+func_andn64 (unsigned long long X, unsigned long long Y)
+{
+  return __andn_u64 (X, Y);
+}
+
+unsigned long long
+func_bextr64 (unsigned long long X, unsigned long long Y)
+{
+  return __bextr_u64 (X, Y);
+}
+
+unsigned long long
+func_bextr64_3args (unsigned long long X,
+		    unsigned long long Y,
+		    unsigned long long Z)
+{
+  return _bextr_u64 (X, Y, Z);
+}
+
+unsigned long long
+func_blsi64 (unsigned long long X)
+{
+  return __blsi_u64 (X);
+}
+
+unsigned long long
+func_blsmsk64 (unsigned long long X)
+{
+  return __blsmsk_u64 (X);
+}
+
+unsigned long long
+func_blsr64 (unsigned long long X)
+{
+  return __blsr_u64 (X);
+}
+
+unsigned long long
+func_tzcnt64 (unsigned long long X)
+{
+  return __tzcnt_u64 (X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-3.c
new file mode 100644
index 000000000..ddc5e0f66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi " } */
+/* { dg-final { scan-assembler "tzcntw\[^\\n]*(%|)ax" } } */
+
+#include <x86intrin.h>
+
+unsigned short
+func_tzcnt16 (unsigned short X)
+{
+  return __tzcnt_u16(X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-4.c
new file mode 100644
index 000000000..e0a116162
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-4.c
@@ -0,0 +1,13 @@
+/* { dg-do link } */
+/* { dg-options "-O2 -mbmi" } */
+
+#include <x86intrin.h>
+
+/* Test that a constant operand 0 to tzcnt gets folded.  */
+extern void link_error(void);
+int main()
+{
+  if (__tzcnt_u32(0) != 32)
+    link_error();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-5.c
new file mode 100644
index 000000000..546a593c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-5.c
@@ -0,0 +1,13 @@
+/* { dg-do link { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mbmi" } */
+
+#include <x86intrin.h>
+
+/* Test that a constant operand 0 to tzcnt gets folded.  */
+extern void link_error(void);
+int main()
+{
+  if (__tzcnt_u64(0) != 64)
+    link_error();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-6.c
new file mode 100644
index 000000000..a4489e0b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-6.c
@@ -0,0 +1,13 @@
+/* { dg-do link } */
+/* { dg-options "-O2 -mbmi" } */
+
+#include <x86intrin.h>
+
+/* Test that a constant operand 0 to tzcnt gets folded.  */
+extern void link_error(void);
+int main()
+{
+  if (__tzcnt_u16(0) != 16)
+    link_error();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1.c
new file mode 100644
index 000000000..bf0685ad3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { bmi && { ! ia32 } } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+long long calc_andn_u64 (long long src1,
+			 long long src2,
+			 long long dummy)
+{
+  return (~src1 + dummy) & (src2);
+}
+
+static void
+bmi_test()
+{
+  unsigned i;
+
+  long long src = 0xfacec0ffeefacec0;
+  long long res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_andn_u64 (src, src+i, 0);
+    res = __andn_u64 (src, src+i);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c
new file mode 100644
index 000000000..a7ee07653
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-andn-1.c"
+
+/* { dg-final { scan-assembler-times "bmi_andn_di" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2.c
new file mode 100644
index 000000000..bb998f3af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { bmi } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+long long calc_andn_u32 (int src1, int src2, int dummy)
+{
+  return (~src1+dummy) & (src2);
+}
+
+static void
+bmi_test()
+{
+  unsigned i;
+
+  int src = 0xfacec0ff;
+  int res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_andn_u32 (src, src+i, 0);
+    res = __andn_u32 (src, src+i);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c
new file mode 100644
index 000000000..72fe02639
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-andn-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-andn-2.c"
+
+/* { dg-final { scan-assembler-times "bmi_andn_si" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c
new file mode 100644
index 000000000..4abe63e54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run { target { bmi && { ! ia32 } } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+long long calc_bextr_u64 (unsigned long long src1,
+			  unsigned long long src2)
+{
+  long long res = 0;
+  unsigned char start = (src2 & 0xff);
+  unsigned char len = (int) ((src2 >> 8) & 0xff);
+  if (start < 64) {
+    unsigned i;
+    unsigned last = (start+len) < 64 ? start+len : 64;
+
+    src1 >>= start;
+    for (i=start; i<last; ++i) {
+      res |= (src1 & 1) << (i-start);
+      src1 >>= 1;
+    }
+  }
+
+  return res;
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  unsigned char start, len;
+  unsigned long long src1 = 0xfacec0ffeefacec0;
+  unsigned long long res, res_ref, src2;
+
+  for (i=0; i<5; ++i) {
+    start = (i * 1983) % 64;
+    len = i + (i * 1983) % 64;
+
+    src1 = src1 * 3;
+    src2 = start | (((long long)len) << 8);
+
+    res_ref = calc_bextr_u64 (src1, src2);
+    res = __bextr_u64 (src1, src2);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c
new file mode 100644
index 000000000..4ccfbdc98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-bextr-1.c"
+
+/* { dg-final { scan-assembler-times "bmi_bextr_di" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c
new file mode 100644
index 000000000..2ce625966
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run { target { bmi } } } */
+/* { dg-require-effective-target bmi  } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+unsigned calc_bextr_u32 (unsigned src1, unsigned src2)
+{
+  unsigned res = 0;
+  unsigned char start = (src2 & 0xff);
+  unsigned char len = (int) ((src2 >> 8) & 0xff);
+  if (start < 32) {
+    unsigned i;
+    unsigned last = (start+len) < 32 ? start+len : 32;
+
+    src1 >>= start;
+    for (i=start; i<last; ++i) {
+      res |= (src1 & 1) << (i-start);
+      src1 >>= 1;
+    }
+  }
+
+  return res;
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  unsigned char start, len;
+  unsigned src1 = 0xfacec0ff;
+  unsigned res, res_ref, src2;
+
+  for (i=0; i<5; ++i) {
+    start = (i * 1983) % 32;
+    len = i + (i * 1983) % 32;
+
+    src1 = src1 * 3;
+    src2 = start | (((unsigned)len) << 8);
+
+    res_ref = calc_bextr_u32 (src1, src2);
+    res = __bextr_u32 (src1, src2);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c
new file mode 100644
index 000000000..282a3e400
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-bextr-2.c"
+
+/* { dg-final { scan-assembler-times "bmi_bextr_si" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-3.c
new file mode 100644
index 000000000..fe342b9e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-3.c
@@ -0,0 +1,31 @@
+/* PR target/57623 */
+/* { dg-do assemble { target bmi } } */
+/* { dg-options "-O2 -mbmi" } */
+
+#include <x86intrin.h>
+
+unsigned int
+f1 (unsigned int x, unsigned int *y)
+{
+  return __bextr_u32 (x, *y);
+}
+
+unsigned int
+f2 (unsigned int *x, unsigned int y)
+{
+  return __bextr_u32 (*x, y);
+}
+
+#ifdef  __x86_64__
+unsigned long long
+f3 (unsigned long long x, unsigned long long *y)
+{
+  return __bextr_u64 (x, *y);
+}
+
+unsigned long long
+f4 (unsigned long long *x, unsigned long long y)
+{
+  return __bextr_u64 (*x, y);
+}
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-4.c
new file mode 100644
index 000000000..2318847ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-4.c
@@ -0,0 +1,49 @@
+/* { dg-do run { target { bmi } } } */
+/* { dg-require-effective-target bmi  } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+unsigned calc_bextr_u32 (unsigned src1, unsigned src2)
+{
+  unsigned res = 0;
+  unsigned char start = (src2 & 0xff);
+  unsigned char len = (int) ((src2 >> 8) & 0xff);
+  if (start < 32) {
+    unsigned i;
+    unsigned last = (start+len) < 32 ? start+len : 32;
+
+    src1 >>= start;
+    for (i=start; i<last; ++i) {
+      res |= (src1 & 1) << (i-start);
+      src1 >>= 1;
+    }
+  }
+
+  return res;
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  unsigned char start, len;
+  unsigned src1 = 0xfacec0ff;
+  unsigned res, res_ref, src2;
+
+  for (i=0; i<5; ++i) {
+    start = i * 4;
+    len = i * 4;
+
+    src1 = src1 * 3;
+    src2 = (start & 0xff) | ((len & 0xff) << 8);
+
+    res_ref = calc_bextr_u32 (src1, src2);
+    res = _bextr_u32 (src1, start, len);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-5.c
new file mode 100644
index 000000000..fd6e3620f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-bextr-5.c
@@ -0,0 +1,48 @@
+/* { dg-do run { target { bmi && { ! ia32 } } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+long long calc_bextr_u64 (unsigned long long src1,
+			  unsigned long long src2)
+{
+  long long res = 0;
+  unsigned char start = (src2 & 0xff);
+  unsigned char len = (int) ((src2 >> 8) & 0xff);
+  if (start < 64) {
+    unsigned i;
+    unsigned last = (start+len) < 64 ? start+len : 64;
+
+    src1 >>= start;
+    for (i=start; i<last; ++i) {
+      res |= (src1 & 1) << (i-start);
+      src1 >>= 1;
+    }
+  }
+
+  return res;
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  unsigned char start, len;
+  unsigned long long src1 = 0xfacec0ffeefacec0;
+  unsigned long long res, res_ref, src2;
+
+  for (i=0; i<5; ++i) {
+    start = i * 4;
+    len = i * 3;
+    src1 = src1 * 3;
+    src2 = (start & 0xff) | ((len & 0xff) << 8);
+
+    res_ref = calc_bextr_u64 (src1, src2);
+    res = _bextr_u64 (src1, start, len);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c
new file mode 100644
index 000000000..e7f2c896d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { bmi && { ! ia32 } } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+/* To fool compiler, so it not generate blsi here. */
+long long calc_blsi_u64 (long long src1, long long src2)
+{
+  return (-src1) & (src2);
+}
+
+static void
+bmi_test()
+{
+  unsigned i;
+
+  long long src = 0xfacec0ffeefacec0;
+  long long res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_blsi_u64 (src, src);
+    res = __blsi_u64 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c
new file mode 100644
index 000000000..e9e0ecb67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-blsi-1.c"
+
+/* { dg-final { scan-assembler-times "bmi_blsi_di" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c
new file mode 100644
index 000000000..b6633a980
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { bmi } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+/* To fool compiler, so it not generate blsi here. */
+int calc_blsi_u32 (int src1, int src2)
+{
+  return (-src1) & (src2);
+}
+
+static void
+bmi_test()
+{
+  unsigned i;
+  int src = 0xfacec0ff;
+  int res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_blsi_u32 (src, src);
+    res = __blsi_u32 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c
new file mode 100644
index 000000000..be9ca3f63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsi-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-blsi-2.c"
+
+/* { dg-final { scan-assembler-times "bmi_blsi_si" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c
new file mode 100644
index 000000000..5498007c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { bmi && { ! ia32 } } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+/*  Trick compiler in order not to generate target insn here. */
+long long calc_blsmsk_u64 (long long src1, long long src2)
+{
+  return (src1-1) ^ (src2);
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  long long src = 0xfacec0ffeefacec0;
+  long long res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_blsmsk_u64 (src, src);
+    res = __blsmsk_u64 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c
new file mode 100644
index 000000000..4e6cb7b36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-blsmsk-1.c"
+
+/* { dg-final { scan-assembler-times "bmi_blsmsk_di" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c
new file mode 100644
index 000000000..be0ebf900
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { bmi } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+/*  Trick compiler in order not to generate target insn here. */
+int calc_blsmsk_u32 (int src1, int src2)
+{
+  return (src1-1) ^ (src2);
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  int src = 0xfacec0ff;
+  int res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_blsmsk_u32 (src, src);
+    res = __blsmsk_u32 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c
new file mode 100644
index 000000000..f6f6babff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsmsk-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-blsmsk-2.c"
+
+/* { dg-final { scan-assembler-times "bmi_blsmsk_si" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c
new file mode 100644
index 000000000..68e01f39f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run { target { bmi && { ! ia32 } } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+long long calc_blsr_u64 (long long src1, long long src2)
+{
+  return (src1-1) & (src2);
+}
+
+static void
+bmi_test()
+{
+  unsigned i;
+  long long src = 0xfacec0ffeefacec0;
+  long long res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_blsr_u64 (src, src);
+    res = __blsr_u64 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c
new file mode 100644
index 000000000..79241ca8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-blsr-1.c"
+
+/* { dg-final { scan-assembler-times "bmi_blsr_di" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c
new file mode 100644
index 000000000..b3fc4e5e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2.c
@@ -0,0 +1,29 @@
+/* { dg-do run { target { bmi } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+int calc_blsr_u32 (int src1, int src2)
+{
+  return (src1-1) & (src2);
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  int src = 0xfacec0ff;
+  int res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_blsr_u32 (src, src);
+    res = __blsr_u32 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c
new file mode 100644
index 000000000..d88c16e4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-blsr-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi -fno-inline -dp" } */
+
+#include "bmi-blsr-2.c"
+
+/* { dg-final { scan-assembler-times "bmi_blsr_si" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-check.h
new file mode 100644
index 000000000..8fad38ad0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-check.h
@@ -0,0 +1,39 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void bmi_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  bmi_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (__get_cpuid_max (0, NULL) < 7)
+    return 0;
+
+  __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+  /* Run BMI test only if host has BMI support.  */
+  if (ebx & bit_BMI)
+    {
+      do_test ();
+#ifdef DEBUG
+    printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c
new file mode 100644
index 000000000..a9fce15ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { bmi && { ! ia32 } } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+long long calc_tzcnt_u64 (long long src)
+{
+  int i;
+  int res = 0;
+
+  while ( (res<64) && ((src&1) == 0)) {
+    ++res;
+    src >>= 1;
+  }
+
+  return res;
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  long long src = 0xfacec0ffeefacec0;
+  long long res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_tzcnt_u64 (src);
+    res = __tzcnt_u64 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c
new file mode 100644
index 000000000..e283c3154
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include "bmi-tzcnt-1.c"
+
+/* { dg-final { scan-assembler-times "tzcntq" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c
new file mode 100644
index 000000000..1a9235b59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run { target { bmi } } } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "bmi-check.h"
+
+int calc_tzcnt_u32 (int src)
+{
+  int i;
+  int res = 0;
+
+  while ( (res<32) && ((src&1) == 0)) {
+    ++res;
+    src >>= 1;
+  }
+  return res;
+}
+
+static void
+bmi_test ()
+{
+  unsigned i;
+  int src = 0xfacec0ff;
+  int res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = i + src << i;
+
+    res_ref = calc_tzcnt_u32 (src);
+    res = __tzcnt_u32 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c
new file mode 100644
index 000000000..2cdb3f443
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi-tzcnt-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi -fno-inline" } */
+
+#include "bmi-tzcnt-2.c"
+
+/* { dg-final { scan-assembler-times "tzcntl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi-1.c
new file mode 100644
index 000000000..42e002d06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi-1.c
@@ -0,0 +1,31 @@
+/* PR target/57623 */
+/* { dg-do assemble { target bmi2 } } */
+/* { dg-options "-O2 -mbmi2" } */
+
+#include <x86intrin.h>
+
+unsigned int
+f1 (unsigned int x, unsigned int *y)
+{
+  return _bzhi_u32 (x, *y);
+}
+
+unsigned int
+f2 (unsigned int *x, unsigned int y)
+{
+  return _bzhi_u32 (*x, y);
+}
+
+#ifdef  __x86_64__
+unsigned long long
+f3 (unsigned long long x, unsigned long long *y)
+{
+  return _bzhi_u64 (x, *y);
+}
+
+unsigned long long
+f4 (unsigned long long *x, unsigned long long y)
+{
+  return _bzhi_u64 (*x, y);
+}
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c
new file mode 100644
index 000000000..68df8b71d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { bmi2 } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include <x86intrin.h>
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned
+calc_bzhi_u32 (unsigned a, int l)
+{
+  unsigned res = a;
+  int i;
+  for (i = 0; i < 32 - l; ++i)
+    res &= ~(1 << (31 - i));
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned src = 0xce7ace0f;
+  unsigned res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_bzhi_u32 (src, i * 2);
+    res = _bzhi_u32 (src, i * 2);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c
new file mode 100644
index 000000000..05be7a837
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi32-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-bzhi32-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_bzhi_si3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c
new file mode 100644
index 000000000..1ffe135b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { bmi2 && { ! ia32 } } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include <x86intrin.h>
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned long long
+calc_bzhi_u64 (unsigned long long a, int l)
+{
+  unsigned long long res = a;
+  int i;
+  for (i = 0; i < 64 - l; ++i)
+    res &= ~(1LL << (63 - i));
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned long long src = 0xce7ace0ce7ace0ff;
+  unsigned long long res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_bzhi_u64 (src, i * 2);
+    res = _bzhi_u64 (src, i * 2);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c
new file mode 100644
index 000000000..dc4a94cc3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-bzhi64-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-bzhi64-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_bzhi_di3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-check.h
new file mode 100644
index 000000000..c933a49f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-check.h
@@ -0,0 +1,39 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void bmi2_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  bmi2_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (__get_cpuid_max (0, NULL) < 7)
+    return 0;
+
+  __cpuid_count (7, 0,  eax, ebx, ecx, edx);
+
+  /* Run BMI2 test only if host has BMI2 support.  */
+  if (ebx & bit_BMI2)
+    {
+      do_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c
new file mode 100644
index 000000000..5e6028781
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { bmi2 && { ia32 } } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned long long
+calc_mul_u32 (unsigned volatile a, unsigned b)
+{
+  unsigned long long res = 0;
+  int i;
+  for (i = 0; i < b; ++i)
+    res += a;
+
+  return res;
+}
+
+__attribute__((noinline, regparm (2)))
+unsigned long long
+gen_mulx (unsigned a, unsigned b)
+{
+  unsigned long long res;
+
+  res = (unsigned long long)a * b;
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned a = 0xce7ace0;
+  unsigned b = 0xfacefff;
+  unsigned long long res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    a = a * (i + 1);
+    b = b / (i + 1);
+
+    res_ref = calc_mul_u32 (a, b);
+    res = gen_mulx (a, b);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c
new file mode 100644
index 000000000..cf3bb085c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-mulx32-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_umulsidi3_1" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c
new file mode 100644
index 000000000..7c99b2dae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run { target { bmi2 && { ia32 } } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include <x86intrin.h>
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned long long
+calc_mul_u32 (unsigned volatile a, unsigned b)
+{
+  unsigned long long res = 0;
+  int i;
+  for (i = 0; i < b; ++i)
+    res += a;
+
+  return res;
+}
+
+__attribute__((noinline, regparm (2)))
+unsigned calc_mulx_u32 (unsigned x, unsigned y, unsigned *res_h)
+{
+  return (unsigned) _mulx_u32 (x, y, res_h);
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned a = 0xce7ace0;
+  unsigned b = 0xfacefff;
+  unsigned res_l, res_h;
+  unsigned long long res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    a = a * (i + 1);
+    b = b / (i + 1);
+
+    res_ref = calc_mul_u32 (a, b);
+    res_l = calc_mulx_u32 (a, b, &res_h);
+
+    res = ((unsigned long long) res_h << 32) | res_l;
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c
new file mode 100644
index 000000000..356d593c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx32-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O2 -mbmi2" } */
+
+#include "bmi2-mulx32-2.c"
+
+/* { dg-final { scan-assembler-times "mulx\[ \\t\]+\[^\n\]*" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c
new file mode 100644
index 000000000..68449466c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run { target { bmi2 && { ! ia32 } } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned __int128
+calc_mul_u64 (unsigned long long volatile a, unsigned long long b)
+{
+  unsigned __int128 res = 0;
+  int i;
+  for (i = 0; i < b; ++i)
+    res += (unsigned __int128) a;
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned long long a = 0xce7ace0ce7ace0;
+  unsigned long long b = 0xface;
+  unsigned __int128 res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    a = a * (i + 1);
+    b = b / (i + 1);
+
+    res_ref = calc_mul_u64 (a, b);
+    res = (unsigned __int128) a * b;
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c
new file mode 100644
index 000000000..592d713e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-mulx64-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_umulditi3_1" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c
new file mode 100644
index 000000000..55b355462
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2.c
@@ -0,0 +1,51 @@
+/* { dg-do run { target { bmi2 && { ! ia32 } } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include <x86intrin.h>
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned __int128
+calc_mul_u64 (unsigned long long volatile a, unsigned long long b)
+{
+  unsigned __int128 res = 0;
+  int i;
+  for (i = 0; i < b; ++i)
+    res += (unsigned __int128) a;
+
+  return res;
+}
+
+__attribute__((noinline))
+unsigned long long
+calc_mulx_u64 (unsigned long long x,
+	       unsigned long long y,
+	       unsigned long long *res_h)
+{
+  return _mulx_u64 (x, y, res_h);
+}
+
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned long long a = 0xce7ace0ce7ace0;
+  unsigned long long b = 0xface;
+  unsigned long long res_l, res_h;
+  unsigned __int128 res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    a = a * (i + 1);
+    b = b / (i + 1);
+
+    res_ref = calc_mul_u64 (a, b);
+
+    res_l = calc_mulx_u64 (a, b, &res_h);
+
+    res = ((unsigned __int128) res_h << 64) | res_l;
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c
new file mode 100644
index 000000000..d8b3e0ecc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-mulx64-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi2" } */
+
+#include "bmi2-mulx64-2.c"
+
+/* { dg-final { scan-assembler-times "mulx\[ \\t\]+\[^\n\]*" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c
new file mode 100644
index 000000000..5aecf5717
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run { target { bmi2 } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include <x86intrin.h>
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned
+calc_pdep_u32 (unsigned a, int mask)
+{
+  unsigned res = 0;
+  int i, k = 0;
+
+  for (i = 0; i < 32; ++i)
+    if (mask & (1 << i)) {
+      res |= ((a & (1 << k)) >> k) << i;
+      ++k;
+    }
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned src = 0xce7acc;
+  unsigned res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_pdep_u32 (src, i * 3);
+    res = _pdep_u32 (src, i * 3);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c
new file mode 100644
index 000000000..87888fcff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep32-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-pdep32-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_pdep_si3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c
new file mode 100644
index 000000000..f718b2f35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run { target { bmi2 && { ! ia32 } } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include <x86intrin.h>
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned long long
+calc_pdep_u64 (unsigned long long a, unsigned long long mask)
+{
+  unsigned long long res = 0;
+  unsigned long long i, k = 0;
+
+  for (i = 0; i < 64; ++i)
+    if (mask & (1LL << i)) {
+      res |= ((a & (1LL << k)) >> k) << i;
+      ++k;
+    }
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned long long i;
+  unsigned long long src = 0xce7acce7acce7ac;
+  unsigned long long res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_pdep_u64 (src, ~(i * 3));
+    res = _pdep_u64 (src, ~(i * 3));
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c
new file mode 100644
index 000000000..8163c4062
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pdep64-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-pdep64-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_pdep_di3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c
new file mode 100644
index 000000000..7fe78378e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run { target { bmi2 } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include <x86intrin.h>
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned
+calc_pext_u32 (unsigned a, unsigned mask)
+{
+  unsigned res = 0;
+  int i, k = 0;
+
+  for (i = 0; i < 32; ++i)
+    if (mask & (1 << i)) {
+      res |= ((a & (1 << i)) >> i) << k;
+      ++k;
+    }
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned src = 0xce7acc;
+  unsigned res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_pext_u32 (src, ~(i * 3));
+    res = _pext_u32 (src, ~(i * 3));
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c
new file mode 100644
index 000000000..c4a6deeca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext32-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-pext32-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_pext_si3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c
new file mode 100644
index 000000000..685074966
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run { target { bmi2 && { ! ia32 } } } } */
+/* { dg-options "-mbmi2 -O2" } */
+
+#include <x86intrin.h>
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned long long
+calc_pext_u64 (unsigned long long a, unsigned long long mask)
+{
+  unsigned long long res = 0;
+  int i, k = 0;
+
+  for (i = 0; i < 64; ++i)
+    if (mask & (1LL << i)) {
+      res |= ((a & (1LL << i)) >> i) << k;
+      ++k;
+    }
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned long long i;
+  unsigned long long src = 0xce7acce7acce7ac;
+  unsigned long long res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_pext_u64 (src, ~(i * 3));
+    res = _pext_u64 (src, ~(i * 3));
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c
new file mode 100644
index 000000000..aaf06c1f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-pext64-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-pext64-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_pext_di3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c
new file mode 100644
index 000000000..d7f6f3b62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run { target { bmi2 } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned
+calc_rorx_u32 (unsigned a, int l)
+{
+  unsigned volatile res = a;
+  int i;
+  for (i = 0; i < l; ++i)
+    res = (res >> 1) | ((res & 1) << 31);
+
+  return res;
+}
+
+#define SHIFT_VAL 0x0e
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned src = 0xce7ace0;
+  unsigned res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_rorx_u32 (src, SHIFT_VAL);
+    res = (src >> SHIFT_VAL) | (src << (32 - SHIFT_VAL));
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c
new file mode 100644
index 000000000..bb3b28d6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx32-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-rorx32-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_rorxsi3_1" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c
new file mode 100644
index 000000000..ccd60c28a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run { target { bmi2 && { ! ia32 } } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned long long
+calc_rorx_u64 (unsigned long long a, int l)
+{
+  unsigned long long volatile res = a;
+  int i;
+  for (i = 0; i < l; ++i)
+    res = (res >> 1) | ((res&1)<< 63);
+
+  return res;
+}
+
+#define SHIFT_VAL 0x1e
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned long long src = 0xce7ace0ce7ace0;
+  unsigned long long res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_rorx_u64 (src, SHIFT_VAL);
+    res = (src >> SHIFT_VAL) | (src << (64 - SHIFT_VAL));
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c
new file mode 100644
index 000000000..2a7a7a08c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-rorx64-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-rorx64-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_rorxdi3_1" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c
new file mode 100644
index 000000000..8224b6f60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { bmi2 } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+int
+calc_sarx_u32 (int a, int l)
+{
+  int volatile res = a;
+  int i;
+  for (i = 0; i < l; ++i)
+    res >>= 1;
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  int src = 0xfce7ace0;
+  int res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_sarx_u32 (src, i + 1);
+    res = src >> (i + 1);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c
new file mode 100644
index 000000000..f10d60b3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx32-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-sarx32-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_ashrsi3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c
new file mode 100644
index 000000000..a43b2025d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { bmi2 && { ! ia32 } } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+long long
+calc_sarx_u64 (long long a, int l)
+{
+  long long volatile res = a;
+  int i;
+  for (i = 0; i < l; ++i)
+    res >>= 1;
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  long long src = 0xfce7ace0ce7ace0;
+  long long res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_sarx_u64 (src, i + 1);
+    res = src >> (i + 1);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c
new file mode 100644
index 000000000..bcf0fd44c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-sarx64-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-sarx64-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_ashrdi3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c
new file mode 100644
index 000000000..0bf970282
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { bmi2 } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+int
+calc_shlx_u32 (int a, int l)
+{
+  int volatile res = a;
+  int i;
+  for (i = 0; i < l; ++i)
+    res <<= 1;
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  int src = 0xfce7ace0;
+  int res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_shlx_u32 (src, i + 1);
+    res = src << (i + 1);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c
new file mode 100644
index 000000000..215e5d3d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shlx32-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-shlx32-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_ashlsi3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c
new file mode 100644
index 000000000..2d2ec155e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { bmi2 } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned
+calc_shrx_u32 (unsigned a, int l)
+{
+  unsigned volatile res = a;
+  int i;
+  for (i = 0; i < l; ++i)
+    res >>= 1;
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned src = 0xce7ace0;
+  unsigned res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_shrx_u32 (src, i + 1);
+    res = src >> (i + 1);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c
new file mode 100644
index 000000000..24c53d458
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx32-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-shrx32-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_lshrsi3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c
new file mode 100644
index 000000000..81d232e76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { bmi2 && { ! ia32 } } } } */
+/* { dg-options "-mbmi2 -O2 -dp" } */
+
+#include "bmi2-check.h"
+
+__attribute__((noinline))
+unsigned long long
+calc_shrx_u64 (unsigned long long a, int l)
+{
+  unsigned long long volatile res = a;
+  int i;
+  for (i = 0; i < l; ++i)
+    res >>= 1;
+
+  return res;
+}
+
+static void
+bmi2_test ()
+{
+  unsigned i;
+  unsigned long long src = 0xce7ace0ce7ace0;
+  unsigned long long res, res_ref;
+
+  for (i = 0; i < 5; ++i) {
+    src = src * (i + 1);
+
+    res_ref = calc_shrx_u64 (src, i + 1);
+    res = src >> (i + 1);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c
new file mode 100644
index 000000000..783043935
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bmi2-shrx64-1a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mbmi2 -dp" } */
+
+#include "bmi2-shrx64-1.c"
+
+/* { dg-final { scan-assembler-times "bmi2_lshrdi3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost1.c
new file mode 100644
index 000000000..ed873fa71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=0" } */
+
+extern int doo (void);
+
+int
+foo (int a, int b)
+{
+  if (a && b)
+   return doo ();
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "if " 2 "gimple" } } */
+/* { dg-final { scan-tree-dump-not " & " "gimple" } } */
+/* { dg-final { cleanup-tree-dump "gimple" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost2.c
new file mode 100644
index 000000000..4d754d57b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=2" } */
+
+extern int doo (void);
+
+int
+foo (int a, int b)
+{
+  if (a && b)
+   return doo ();
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "if " 1 "gimple" } } */
+/* { dg-final { scan-tree-dump-times " & " 1 "gimple" } } */
+/* { dg-final { cleanup-tree-dump "gimple" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost3.c
new file mode 100644
index 000000000..3b69f503f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost3.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=2" } */
+
+extern int doo (void);
+
+int
+foo (_Bool a, _Bool b)
+{
+  if (a && b)
+   return doo ();
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "if " 1 "gimple" } } */
+/* { dg-final { scan-tree-dump-times " & " 1 "gimple" } } */
+/* { dg-final { cleanup-tree-dump "gimple" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost4.c
new file mode 100644
index 000000000..5904b0da2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/branch-cost4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-gimple -mbranch-cost=0" } */
+
+extern int doo (void);
+
+int
+foo (_Bool a, _Bool b)
+{
+  if (a && b)
+   return doo ();
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "if " 2 "gimple" } } */
+/* { dg-final { scan-tree-dump-not " & " "gimple" } } */
+/* { dg-final { cleanup-tree-dump "gimple" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/brokensqrt.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/brokensqrt.c
new file mode 100644
index 000000000..836d3b37d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/brokensqrt.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */
+/* { dg-require-effective-target sse } */
+#include "sse-check.h"
+
+extern float sqrtf (float);
+float __attribute__((noinline)) broken (float a, float b)
+{
+  return sqrtf (a / b);
+}
+
+extern void abort (void);
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+static void
+sse_test (void)
+{
+  int i;
+  float x;
+  char buf[sizeof (float)];
+  x = broken (0.0f, 10000.0f);
+  /* A convoluted way to check for the correct result (zero) for all
+     floating point formats.
+     We can't use ==, !=, or range checks, or isinf/isnan/isunordered,
+     because all of these will not do the right thing under -ffast-math,
+     as they can assume that neither nan nor inf are returned.  */
+  memcpy (&buf, &x, sizeof (float));
+  for (i = 0; i < sizeof (float); i++)
+    if (buf[i] != 0)
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-1.c
new file mode 100644
index 000000000..3727155d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-1.c
@@ -0,0 +1,15 @@
+/* PR target/36473 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+extern void foo (void);
+
+int test(int x, int n)
+{
+  if (x & ( 0x01 << n ))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "btl\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-2.c
new file mode 100644
index 000000000..34fa829e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-2.c
@@ -0,0 +1,16 @@
+/* PR target/36473 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+extern void foo (void);
+
+int test(long x, long n)
+{
+  if (x & ( (long)0x01 << n ))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler "btl\[ \t\]" { target { ! lp64 } } } } */
+/* { dg-final { scan-assembler "btq\[ \t\]" { target lp64 } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-mask-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-mask-1.c
new file mode 100644
index 000000000..bdcfd558a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-mask-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+void foo (void);
+
+int test (int x, int n)
+{
+  n &= 0x1f;
+
+  if (x & (0x01 << n))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-mask-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-mask-2.c
new file mode 100644
index 000000000..babfc2bcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/bt-mask-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+void foo (void);
+
+int test (long x, long n)
+{
+  n &= 0x3f;
+
+  if (x & ((long)0x01 << n))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c
new file mode 100644
index 000000000..badfe03a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-apply-mmx.c
@@ -0,0 +1,42 @@
+/* __builtin_apply_args () and __builtin_return () built-in functions does
+   not function properly when -mmmx is used in compile flags.
+   __builtin_apply_args () saves all registers that pass arguments to a
+   function, including %mm0-%mm3, to a memory block, and __builtin_return ()
+   restores %mm0, from a return memory block, as it can be used as a
+   function return register.  Unfortunatelly, when MMX registers are touched,
+   i387 FPU switches to MMX mode, and no FP operation is possible until emms
+   instruction is issued.  */
+
+/* This test case is adapted from gcc.dg/builtin-apply4.c.  */
+ 
+/* { dg-do run { xfail { ! *-*-darwin* } } } */
+/* { dg-options "-O2 -mmmx" } */
+/* { dg-require-effective-target ia32 } */
+
+#include "mmx-check.h"
+
+extern void abort (void);
+
+double
+foo (double arg)
+{
+  if (arg != 116.0)
+    abort ();
+
+  return arg + 1.0;
+}
+
+inline double
+bar (double arg)
+{
+  foo (arg);
+  __builtin_return (__builtin_apply ((void (*)()) foo,
+				     __builtin_apply_args (), 16));
+}
+
+static void
+mmx_test (void)
+{
+  if (bar (116.0) != 117.0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c
new file mode 100644
index 000000000..4acf48bdc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-assume-aligned-1.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse2 -mno-avx" } */
+
+void
+test1 (double *out1, double *out2, double *out3, double *in1,
+       double *in2, int len)
+{
+  int i;
+  double *__restrict o1 = __builtin_assume_aligned (out1, 16);
+  double *__restrict o2 = __builtin_assume_aligned (out2, 16);
+  double *__restrict o3 = __builtin_assume_aligned (out3, 16);
+  double *__restrict i1 = __builtin_assume_aligned (in1, 16);
+  double *__restrict i2 = __builtin_assume_aligned (in2, 16);
+  for (i = 0; i < len; ++i)
+    {
+      o1[i] = i1[i] * i2[i];
+      o2[i] = i1[i] + i2[i];
+      o3[i] = i1[i] - i2[i];
+    }
+}
+
+void
+test2 (double *out1, double *out2, double *out3, double *in1,
+       double *in2, int len)
+{
+  int i, align = 32, misalign = 16;
+  out1 = __builtin_assume_aligned (out1, align, misalign);
+  out2 = __builtin_assume_aligned (out2, align, 16);
+  out3 = __builtin_assume_aligned (out3, 32, misalign);
+  in1 = __builtin_assume_aligned (in1, 32, 16);
+  in2 = __builtin_assume_aligned (in2, 32, 0);
+  for (i = 0; i < len; ++i)
+    {
+      out1[i] = in1[i] * in2[i];
+      out2[i] = in1[i] + in2[i];
+      out3[i] = in1[i] - in2[i];
+    }
+}
+
+/* { dg-final { scan-assembler-not "movhpd" } } */
+/* { dg-final { scan-assembler-not "movlpd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c
new file mode 100644
index 000000000..0f94025c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "builtin_bswap" } } */
+
+long foo (long a)
+{
+  long b;
+
+#if __LP64__
+  b = __builtin_bswap64 (a);
+#else
+  b = __builtin_bswap32 (a);
+#endif
+
+  return b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c
new file mode 100644
index 000000000..818aa76b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=nocona" } */
+/* { dg-final { scan-assembler-not "bswap\[ \t\]" } } */
+
+int foo(int x)
+{
+  int t = __builtin_bswap32 (x);
+  return __builtin_bswap32 (t);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c
new file mode 100644
index 000000000..d5d612f60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "bswapdi2" } } */
+
+long long foo (long long x)
+{
+  return __builtin_bswap64 (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-4.c
new file mode 100644
index 000000000..65198aee8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-bswap-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "bswap\[ \t\]" } } */
+
+short foo (short x)
+{
+  return __builtin_bswap16 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-copysign.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-copysign.c
new file mode 100644
index 000000000..175b931c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-copysign.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#define TEST_SET(MODE, CEXT)						\
+MODE test1##CEXT(MODE a) { return -a; }					\
+MODE test2##CEXT(MODE a) { return __builtin_fabs##CEXT(a); }		\
+MODE test3##CEXT(MODE a) { return __builtin_copysign##CEXT(a, 0.0); }	\
+MODE test4##CEXT(MODE a) { return __builtin_copysign##CEXT(a, -1.0); }	\
+MODE test5##CEXT(MODE a, MODE b) { return __builtin_copysign##CEXT(a, b); }
+
+TEST_SET (float, f)
+TEST_SET (double, )
+TEST_SET (long double, l)
+TEST_SET (__float128, q)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-ucmp.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-ucmp.c
new file mode 100644
index 000000000..709804c35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-ucmp.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -mfpmath=sse -msse2" } */
+
+double foo(double a)
+{
+  return __builtin_round(a);
+}
+
+/* { dg-final { scan-assembler-not "ucom" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-unreachable.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-unreachable.c
new file mode 100644
index 000000000..91923a2df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin-unreachable.c
@@ -0,0 +1,13 @@
+/* This should return 1 without setting up a stack frame or
+   jumping.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+int h (char *p)
+{
+  if (*p)
+    __builtin_unreachable ();
+  return p ? 1 : 0;
+}
+/* { dg-final { scan-assembler-not "%e\[bs\]p" } } */
+/* { dg-final { scan-assembler-not "\[\\t \]+j" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin_target.c
new file mode 100644
index 000000000..c40983e6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/builtin_target.c
@@ -0,0 +1,284 @@
+/* This test checks if the __builtin_cpu_is and __builtin_cpu_supports calls
+   are recognized.  It also independently uses CPUID to get cpu type and
+   features supported and checks if the builtins correctly identify the
+   platform.  The code to do the identification is adapted from
+   libgcc/config/i386/cpuinfo.c.  */
+
+/* { dg-do run } */
+
+#include <assert.h>
+#include "cpuid.h"
+
+/* Check if the Intel CPU model and sub-model are identified.  */
+static void
+check_intel_cpu_model (unsigned int family, unsigned int model,
+		       unsigned int brand_id)
+{
+  /* Parse family and model only if brand ID is 0. */
+  if (brand_id == 0)
+    {
+      switch (family)
+	{
+	case 0x5:
+	  /* Pentium.  */
+	  break;
+	case 0x6:
+	  switch (model)
+	    {
+	    case 0x1c:
+	    case 0x26:
+	      /* Atom.  */
+	      assert (__builtin_cpu_is ("atom"));
+	      break;
+	    case 0x1a:
+	    case 0x1e:
+	    case 0x1f:
+	    case 0x2e:
+	      /* Nehalem.  */
+	      assert (__builtin_cpu_is ("corei7"));
+	      assert (__builtin_cpu_is ("nehalem"));
+	      break;
+	    case 0x25:
+	    case 0x2c:
+	    case 0x2f:
+	      /* Westmere.  */
+	      assert (__builtin_cpu_is ("corei7"));
+	      assert (__builtin_cpu_is ("westmere"));
+	      break;
+	    case 0x2a:
+	      /* Sandy Bridge.  */
+	      assert (__builtin_cpu_is ("corei7"));
+	      assert (__builtin_cpu_is ("sandybridge"));
+	      break;
+	    case 0x17:
+	    case 0x1d:
+	      /* Penryn.  */
+	    case 0x0f:
+	      /* Merom.  */
+	      assert (__builtin_cpu_is ("core2"));
+	      break;
+	    default:
+	      break;
+	    }
+	  break;
+	default:
+	  /* We have no idea.  */
+	  break;
+	}
+    }
+}
+
+/* Check if the AMD CPU model and sub-model are identified.  */
+static void
+check_amd_cpu_model (unsigned int family, unsigned int model)
+{
+  switch (family)
+    {
+    /* AMD Family 10h.  */
+    case 0x10:
+      switch (model)
+	{
+	case 0x2:
+	  /* Barcelona.  */
+	  assert (__builtin_cpu_is ("amdfam10h"));
+	  assert (__builtin_cpu_is ("barcelona"));
+	  break;
+	case 0x4:
+	  /* Shanghai.  */
+	  assert (__builtin_cpu_is ("amdfam10h"));
+	  assert (__builtin_cpu_is ("shanghai"));
+	  break;
+	case 0x8:
+	  /* Istanbul.  */
+	  assert (__builtin_cpu_is ("amdfam10h"));
+	  assert (__builtin_cpu_is ("istanbul"));
+	  break;
+	default:
+	  break;
+	}
+      break;
+    /* AMD Family 15h.  */
+    case 0x15:
+      assert (__builtin_cpu_is ("amdfam15h"));
+      /* Bulldozer version 1.  */
+      if ( model <= 0xf)
+	assert (__builtin_cpu_is ("bdver1"));
+      /* Bulldozer version 2.  */
+      if (model >= 0x10 && model <= 0x1f)
+	assert (__builtin_cpu_is ("bdver2"));
+      break;
+    default:
+      break;
+    }
+}
+
+/* Check if the ISA features are identified.  */
+static void
+check_features (unsigned int ecx, unsigned int edx,
+		int max_cpuid_level)
+{
+  if (edx & bit_CMOV)
+    assert (__builtin_cpu_supports ("cmov"));
+  if (edx & bit_MMX)
+    assert (__builtin_cpu_supports ("mmx"));
+  if (edx & bit_SSE)
+    assert (__builtin_cpu_supports ("sse"));
+  if (edx & bit_SSE2)
+    assert (__builtin_cpu_supports ("sse2"));
+  if (ecx & bit_POPCNT)
+    assert (__builtin_cpu_supports ("popcnt"));
+  if (ecx & bit_SSE3)
+    assert (__builtin_cpu_supports ("sse3"));
+  if (ecx & bit_SSSE3)
+    assert (__builtin_cpu_supports ("ssse3"));
+  if (ecx & bit_SSE4_1)
+    assert (__builtin_cpu_supports ("sse4.1"));
+  if (ecx & bit_SSE4_2)
+    assert (__builtin_cpu_supports ("sse4.2"));
+  if (ecx & bit_AVX)
+    assert (__builtin_cpu_supports ("avx"));
+
+  /* Get advanced features at level 7 (eax = 7, ecx = 0).  */
+  if (max_cpuid_level >= 7)
+    {
+      unsigned int eax, ebx, ecx, edx;
+      __cpuid_count (7, 0, eax, ebx, ecx, edx);
+      if (ebx & bit_AVX2)
+	assert (__builtin_cpu_supports ("avx2"));
+    }
+}
+
+static int __attribute__ ((noinline))
+__get_cpuid_output (unsigned int __level,
+		    unsigned int *__eax, unsigned int *__ebx,
+		    unsigned int *__ecx, unsigned int *__edx)
+{
+  return __get_cpuid (__level, __eax, __ebx, __ecx, __edx);
+}
+
+static int
+check_detailed ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  int max_level; 
+  unsigned int vendor;
+  unsigned int model, family, brand_id;
+  unsigned int extended_model, extended_family;
+
+  /* Assume cpuid insn present. Run in level 0 to get vendor id. */
+  if (!__get_cpuid_output (0, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  vendor = ebx;
+  max_level = eax;
+
+  if (max_level < 1)
+    return 0;
+
+  if (!__get_cpuid_output (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  model = (eax >> 4) & 0x0f;
+  family = (eax >> 8) & 0x0f;
+  brand_id = ebx & 0xff;
+  extended_model = (eax >> 12) & 0xf0;
+  extended_family = (eax >> 20) & 0xff;
+
+  if (vendor == signature_INTEL_ebx)
+    {
+      assert (__builtin_cpu_is ("intel"));
+      /* Adjust family and model for Intel CPUs.  */
+      if (family == 0x0f)
+	{
+	  family += extended_family;
+	  model += extended_model;
+	}
+      else if (family == 0x06)
+	model += extended_model;
+      check_intel_cpu_model (family, model, brand_id);
+      check_features (ecx, edx, max_level);
+    }
+  else if (vendor == signature_AMD_ebx)
+    {
+      assert (__builtin_cpu_is ("amd"));
+      /* Adjust model and family for AMD CPUS. */
+      if (family == 0x0f)
+	{
+	  family += extended_family;
+	  model += (extended_model << 4);
+	}
+      check_amd_cpu_model (family, model);
+      check_features (ecx, edx, max_level);
+    }
+
+  return 0;
+}
+
+static int
+quick_check ()
+{
+  /* Check CPU Features.  */
+  assert (__builtin_cpu_supports ("cmov") >= 0);
+
+  assert (__builtin_cpu_supports ("mmx") >= 0);
+
+  assert (__builtin_cpu_supports ("popcnt") >= 0);
+
+  assert (__builtin_cpu_supports ("sse") >= 0);
+
+  assert (__builtin_cpu_supports ("sse2") >= 0);
+
+  assert (__builtin_cpu_supports ("sse3") >= 0);
+
+  assert (__builtin_cpu_supports ("ssse3") >= 0);
+
+  assert (__builtin_cpu_supports ("sse4.1") >= 0);
+
+  assert (__builtin_cpu_supports ("sse4.2") >= 0);
+
+  assert (__builtin_cpu_supports ("avx") >= 0);
+
+  assert (__builtin_cpu_supports ("avx2") >= 0);
+
+  /* Check CPU type.  */
+  assert (__builtin_cpu_is ("amd") >= 0);
+
+  assert (__builtin_cpu_is ("intel") >= 0);
+
+  assert (__builtin_cpu_is ("atom") >= 0);
+
+  assert (__builtin_cpu_is ("core2") >= 0);
+
+  assert (__builtin_cpu_is ("corei7") >= 0);
+
+  assert (__builtin_cpu_is ("nehalem") >= 0);
+
+  assert (__builtin_cpu_is ("westmere") >= 0);
+
+  assert (__builtin_cpu_is ("sandybridge") >= 0);
+
+  assert (__builtin_cpu_is ("amdfam10h") >= 0);
+
+  assert (__builtin_cpu_is ("barcelona") >= 0);
+
+  assert (__builtin_cpu_is ("shanghai") >= 0);
+
+  assert (__builtin_cpu_is ("istanbul") >= 0);
+
+  assert (__builtin_cpu_is ("amdfam15h") >= 0);
+
+  assert (__builtin_cpu_is ("bdver1") >= 0);
+
+  assert (__builtin_cpu_is ("bdver2") >= 0);
+
+  return 0;
+}
+
+int main ()
+{
+  __builtin_cpu_init ();
+  quick_check ();
+  check_detailed ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cadd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cadd.c
new file mode 100644
index 000000000..7a39c67ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cadd.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "sbb" } } */
+
+extern void abort (void);
+
+/* Conditional increment is best done using sbb $-1, val.  */
+int t[]={0,0,0,0,1,1,1,1,1,1};
+q()
+{
+  int sum=0;
+  int i;
+  for (i=0;i<10;i++)
+    if (t[i])
+       sum++;
+  if (sum != 6)
+    abort ();
+}
+main()
+{
+  int i;
+  for (i=0;i<10000000;i++)
+    q();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/call-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/call-1.c
new file mode 100644
index 000000000..bd7c569c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/call-1.c
@@ -0,0 +1,39 @@
+/* PR optimization/11304 */
+/* Originator: <manuel.serrano@sophia.inria.fr> */
+/* { dg-do run } */
+/* { dg-options "-O -fomit-frame-pointer" } */
+
+/* Verify that %eax is always restored after a call.  */
+
+extern void abort(void);
+
+volatile int r;
+
+void set_eax(int val)
+{
+  __asm__ __volatile__ ("mov %0, %%eax" : : "m" (val));
+}
+
+void foo(int val)
+{
+  r = val;
+}
+
+int bar(int x)
+{
+  if (x)
+  {
+    set_eax(0);
+    return x;
+  }
+
+  foo(x);
+}
+
+int main(void)
+{
+  if (bar(1) != 1)
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cleanup-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cleanup-1.c
new file mode 100644
index 000000000..fc82f35a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cleanup-1.c
@@ -0,0 +1,240 @@
+/* { dg-do run { target *-*-linux* *-*-gnu* } } */
+/* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */
+/* Test complex CFA value expressions.  */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+		   _Unwind_Exception_Class exc_class,
+		   struct _Unwind_Exception *exc_obj,
+		   struct _Unwind_Context *context,
+		   void *stop_parameter)
+{
+  if (actions & _UA_END_OF_STACK)
+    abort ();
+  return _URC_NO_REASON;
+}
+
+static void
+force_unwind ()
+{
+  struct _Unwind_Exception *exc = malloc (sizeof (*exc));
+  memset (&exc->exception_class, 0, sizeof (exc->exception_class));
+  exc->exception_cleanup = 0;
+
+  _Unwind_ForcedUnwind (exc, force_unwind_stop, 0);
+  abort ();
+}
+
+int count;
+
+static void
+counter (void *p __attribute__((unused)))
+{
+  ++count;
+}
+
+static void
+handler (void *p __attribute__((unused)))
+{
+  if (count != 2)
+    abort ();
+  _exit (0);
+}
+
+static int __attribute__((noinline))
+fn5 (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  force_unwind ();
+  return 0;
+}
+
+void
+bar (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  fn5 ();
+}
+
+void __attribute__((noinline))
+foo (int x)
+{
+  char buf[256];
+#ifdef __i386__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leal	%1, %%ecx\n"
+"2:\t"	"call	bar\n"
+"3:\t"	"jmp	18f\n"
+"4:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\",@progbits\n"
+"5:\t"	".long	7f-6f	# Length of Common Information Entry\n"
+"6:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -4	# CIE Data Alignment Factor\n\t"
+	".byte	0x8	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0xc	# DW_CFA_def_cfa\n\t"
+	".uleb128 0x4\n\t"
+	".uleb128 0x0\n\t"
+	".align 4\n"
+"7:\t"	".long	17f-8f	# FDE Length\n"
+"8:\t"	".long	8b-5b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	4b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 10f-9f\n"
+"9:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 3b-1b\n"
+"10:\t"	".byte	0x40 + (2b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 12f-11f\n"
+"11:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 3b-2b\n"
+"12:\t"	".byte	0x40 + (3b-2b-1) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x8\n\t"
+	".uleb128 16f-13f\n"
+"13:\t"	".byte	0x78	# DW_OP_breg8\n\t"
+	".sleb128 15f-14f\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"14:\t"	".4byte	3b-.\n\t"
+	".byte	0x1c	# DW_OP_minus\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"15:\t"	".4byte	18f-.\n\t"
+	".byte	0x22	# DW_OP_plus\n"
+"16:\t"	".align 4\n"
+"17:\t"	".previous\n"
+"18:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "eax", "edx", "ecx");
+#elif defined __x86_64__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leaq	%1, %%rdi\n"
+"2:\t"	"subq	$128, %%rsp\n"
+"3:\t"	"call	bar\n"
+"4:\t"	"addq	$128, %%rsp\n"
+"5:\t"	"jmp	24f\n"
+"6:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\",@progbits\n"
+"7:\t"	".long	9f-8f	# Length of Common Information Entry\n"
+"8:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -8	# CIE Data Alignment Factor\n\t"
+	".byte	0x10	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0x12	# DW_CFA_def_cfa_sf\n\t"
+	".uleb128 0x7\n\t"
+	".sleb128 16\n\t"
+	".align 8\n"
+"9:\t"	".long	23f-10f	# FDE Length\n"
+"10:\t"	".long	10b-7b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	6b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 12f-11f\n"
+"11:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-1b\n"
+"12:\t"	".byte	0x40 + (2b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 14f-13f\n"
+"13:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-2b\n"
+"14:\t"	".byte	0x40 + (3b-2b) # DW_CFA_advance_loc\n\t"
+	".byte	0x0e	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 0\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 16f-15f\n"
+"15:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-3b\n"
+"16:\t"	".byte	0x40 + (4b-3b-1) # DW_CFA_advance_loc\n\t"
+	".byte	0x0e	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 128\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 20f-17f\n"
+"17:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 19f-18f\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"18:\t"	".4byte	4b-.\n\t"
+	".byte	0x1c	# DW_OP_minus\n\t"
+	".byte	0x0d	# DW_OP_const4s\n"
+"19:\t"	".4byte	24f-.\n\t"
+	".byte	0x22	# DW_OP_plus\n"
+"20:\t"	".byte	0x40 + (5b-4b+1) # DW_CFA_advance_loc\n\t"
+	".byte	0x13	# DW_CFA_def_cfa_offset_sf\n\t"
+	".sleb128 16\n\t"
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 22f-21f\n"
+"21:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 4b-5b\n"
+"22:\t"	".align 8\n"
+"23:\t"	".previous\n"
+"24:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "rax", "rdx", "rcx", "rsi", "rdi",
+	  "r8", "r9", "r10", "r11");
+#else
+# error Unsupported test architecture
+#endif
+}
+
+static int __attribute__((noinline))
+fn2 (void)
+{
+  foo (3);
+  return 0;
+}
+
+static int __attribute__((noinline))
+fn1 (void)
+{
+  fn2 ();
+  return 0;
+}
+
+static void *
+fn0 (void)
+{
+  char dummy __attribute__((cleanup (handler)));
+  fn1 ();
+  return 0;
+}
+
+int
+main (void)
+{
+  fn0 ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cleanup-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cleanup-2.c
new file mode 100644
index 000000000..36dd80da9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cleanup-2.c
@@ -0,0 +1,205 @@
+/* { dg-do run { target { *-*-linux* && { ! { ia32 } } } } } */
+/* { dg-options "-fexceptions -fnon-call-exceptions -fasynchronous-unwind-tables -O2" } */
+/* Test complex CFA value expressions.  */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <unistd.h>
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+		   _Unwind_Exception_Class exc_class,
+		   struct _Unwind_Exception *exc_obj,
+		   struct _Unwind_Context *context,
+		   void *stop_parameter)
+{
+  if (actions & _UA_END_OF_STACK)
+    abort ();
+  return _URC_NO_REASON;
+}
+
+static void
+force_unwind ()
+{
+  struct _Unwind_Exception *exc = malloc (sizeof (*exc));
+  memset (&exc->exception_class, 0, sizeof (exc->exception_class));
+  exc->exception_cleanup = 0;
+
+  _Unwind_ForcedUnwind (exc, force_unwind_stop, 0);
+  abort ();
+}
+
+int count;
+
+static void
+counter (void *p __attribute__((unused)))
+{
+  ++count;
+}
+
+static void
+handler (void *p __attribute__((unused)))
+{
+  if (count != 2)
+    abort ();
+  _exit (0);
+}
+
+static int __attribute__((noinline))
+fn5 (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  force_unwind ();
+  return 0;
+}
+
+void
+bar (void)
+{
+  char dummy __attribute__((cleanup (counter)));
+  fn5 ();
+}
+
+void __attribute__((noinline))
+foo (int x)
+{
+  char buf[256];
+#ifdef __x86_64__
+  __asm (
+	"testl	%0, %0\n\t"
+	"jnz	1f\n\t"
+	".subsection 1\n\t"
+	".type	_L_mutex_lock_%=, @function\n"
+"_L_mutex_lock_%=:\n"
+"1:\t"	"leaq	%1, %%rdi\n"
+"2:\t"	"subq	$128, %%rsp\n"
+"3:\t"	"call	bar\n"
+"4:\t"	"addq	$128, %%rsp\n"
+"5:\t"	"jmp	21f\n"
+"6:\t"	".size _L_mutex_lock_%=, .-_L_mutex_lock_%=\n\t"
+	".previous\n\t"
+	".section	.eh_frame,\"a\",@progbits\n"
+"7:\t"	".long	9f-8f	# Length of Common Information Entry\n"
+"8:\t"	".long	0x0	# CIE Identifier Tag\n\t"
+	".byte	0x1	# CIE Version\n\t"
+	".ascii \"zR\\0\"	# CIE Augmentation\n\t"
+	".uleb128 0x1	# CIE Code Alignment Factor\n\t"
+	".sleb128 -8	# CIE Data Alignment Factor\n\t"
+	".byte	0x10	# CIE RA Column\n\t"
+	".uleb128 0x1	# Augmentation size\n\t"
+	".byte	0x1b	# FDE Encoding (pcrel sdata4)\n\t"
+	".byte	0xc	# DW_CFA_def_cfa\n\t"
+	".uleb128 0x7\n\t"
+	".uleb128 0x0\n\t"
+	".align 8\n"
+"9:\t"	".long	20f-10f	# FDE Length\n"
+"10:\t"	".long	10b-7b	# FDE CIE offset\n\t"
+	".long	1b-.	# FDE initial location\n\t"
+	".long	6b-1b	# FDE address range\n\t"
+	".uleb128 0x0	# Augmentation size\n\t"
+	/* This CFA expression computes the address right
+	   past the jnz instruction above, from %rip somewhere
+	   within the _L_mutex_lock_%= subsection.  */
+	".byte	0x16	# DW_CFA_val_expression\n\t"
+	".uleb128 0x10\n\t"
+	".uleb128 19f-11f\n"
+"11:\t"	".byte	0x80	# DW_OP_breg16\n\t"
+	".sleb128 0\n"
+"12:\t"	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0x48\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	16f-13f\n"
+"13:\t"	".byte	0x13	# DW_OP_drop\n\t"
+	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	1\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0x81\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	15f-14f\n"
+"14:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 3b-2b-1\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-15f\n"
+"15:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 2b-1b-1\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-16f\n"
+"16:\t"	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	0xe8\n\t"
+	".byte	0x2e	# DW_OP_ne\n\t"
+	".byte	0x28	# DW_OP_bra\n\t"
+	".2byte	18f-17f\n"
+"17:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 4b-3b\n\t"
+	".byte	0x2f	# DW_OP_skip\n\t"
+	".2byte	12b-18f\n"
+"18:\t"	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 1\n\t"
+	".byte	0x12	# DW_OP_dup\n\t"
+	".byte	0x94	# DW_OP_deref_size\n\t"
+	".byte	4\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	72 - (6b-5b) * 8 # (6b-5b) == 5 ? 32 : 56\n\t"
+	".byte	0x24	# DW_OP_shl\n\t"
+	".byte	0x08	# DW_OP_const1u\n\t"
+	".byte	72 - (6b-5b) * 8 # (6b-5b) == 5 ? 32 : 56\n\t"
+	".byte	0x26	# DW_OP_shra\n\t"
+	".byte	0x22	# DW_OP_plus\n\t"
+	".byte	0x23	# DW_OP_plus_uconst\n\t"
+	".uleb128 6b-5b-1\n"
+"19:\t"	".byte	0x40 + (3b-1b) # DW_CFA_advance_loc\n\t"
+	".byte	0xe	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 128\n\t"
+	".byte	0x40 + (5b-3b) # DW_CFA_advance_loc\n\t"
+	".byte	0xe	# DW_CFA_def_cfa_offset\n\t"
+	".uleb128 0\n\t"
+	".align 8\n"
+"20:\t"	".previous\n"
+"21:"
+	: : "r" (x), "m" (x), "r" (buf)
+	: "memory", "rax", "rdx", "rcx", "rsi", "rdi",
+	  "r8", "r9", "r10", "r11");
+#else
+# error Unsupported test architecture
+#endif
+}
+
+static int __attribute__((noinline))
+fn2 (void)
+{
+  foo (3);
+  return 0;
+}
+
+static int __attribute__((noinline))
+fn1 (void)
+{
+  fn2 ();
+  return 0;
+}
+
+static void *
+fn0 (void)
+{
+  char dummy __attribute__((cleanup (handler)));
+  fn1 ();
+  return 0;
+}
+
+int
+main (void)
+{
+  fn0 ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcap.map b/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcap.map
new file mode 100644
index 000000000..147f922d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcap.map
@@ -0,0 +1,3 @@
+# clear all hardware capabilities emitted by Sun as: the tests here
+# guard against execution at runtime
+hwcap_1 = V0x0 OVERRIDE;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcapv2.map b/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcapv2.map
new file mode 100644
index 000000000..95cb14cc5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/clearcapv2.map
@@ -0,0 +1,7 @@
+# clear all hardware capabilities emitted by Sun as: the tests here
+# guard against execution at runtime
+# uses mapfile v2 syntax which is the only way to clear AT_SUN_CAP_HW2 flags
+$mapfile_version 2
+CAPABILITY {
+  HW = ;
+};
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/clobbers.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/clobbers.c
new file mode 100644
index 000000000..1a70688d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/clobbers.c
@@ -0,0 +1,38 @@
+/* Test asm clobbers on x86. */
+
+/* { dg-do run } */
+
+extern void abort (void);
+
+int main ()
+{
+        int i;
+        __asm__ ("movl $1,%0\n\txorl %%eax,%%eax" : "=r" (i) : : "eax");
+        if (i != 1)
+                abort ();
+	/* On darwin you can't call external functions from non-pic code,
+	   however, clobbering ebx isn't valid in pic code. Instead of
+	   disabling the whole test, just disable the ebx clobbering part.
+	   Ditto for any x86 system that is ilp32 && pic.
+	*/
+#if !(defined (__MACH__))
+#if ! defined (__PIC__) || defined (__x86_64__)
+        __asm__ ("movl $1,%0\n\txorl %%ebx,%%ebx" : "=r" (i) : : "ebx");
+        if (i != 1)
+                abort ();
+#endif /* ! pic || lp64 */
+#endif
+        __asm__ ("movl $1,%0\n\txorl %%ecx,%%ecx" : "=r" (i) : : "ecx");
+        if (i != 1)
+                abort ();
+        __asm__ ("movl $1,%0\n\txorl %%edx,%%edx" : "=r" (i) : : "edx");
+        if (i != 1)
+                abort ();
+        __asm__ ("movl $1,%0\n\txorl %%esi,%%esi" : "=r" (i) : : "esi");
+        if (i != 1)
+                abort ();
+        __asm__ ("movl $1,%0\n\txorl %%edi,%%edi" : "=r" (i) : : "edi");
+        if (i != 1)
+                abort ();
+        return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov1.c
new file mode 100644
index 000000000..edbbda584
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "sar\[^\\n\]*magic_namea" } } */
+/* { dg-final { scan-assembler "sar\[^\\n\]*magic_nameb" } } */
+/* { dg-final { scan-assembler "sar\[^\\n\]*magic_namec" } } */
+/* { dg-final { scan-assembler "shr\[^\\n\]*magic_named" } } */
+/* { dg-final { scan-assembler "shr\[^\\n\]*magic_namee" } } */
+/* { dg-final { scan-assembler "shr\[^\\n\]*magic_namef" } } */
+
+/* Check code generation for several conditional moves doable by single arithmetics.  */
+
+static int magic_namea;
+static char magic_nameb;
+static short magic_namec;
+static int magic_named;
+static char magic_namee;
+static short magic_namef;
+
+unsigned int gen;
+void m(void)
+{
+  magic_namec=magic_namec>=0?0:-1;
+  magic_namea=magic_namea>=0?0:-1;
+  magic_nameb=magic_nameb>=0?0:-1;
+  magic_named=magic_named>=0?0:1;
+  magic_namee=magic_namee>=0?0:1;
+  magic_namef=magic_namef>=0?0:1;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov2.c
new file mode 100644
index 000000000..2b7c696bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "sbb" } } */
+
+/* This conditional move is fastest to be done using sbb.  */
+t(unsigned int a, unsigned int b)
+{
+  return (a<=b?5:-5);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov3.c
new file mode 100644
index 000000000..34df0aab7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "cmov\[^3\]" } } */
+
+/* This conditional move is fastest to be done using cmov.  */
+t(int a, int b)
+{
+  return (a<=b?5:-5);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov4.c
new file mode 100644
index 000000000..6a955eaeb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "cmov\[^4\]" } } */
+
+/* Verify that if conversion happends for memory references.  */
+int ARCHnodes;
+int *nodekind;
+float *nodekindf;
+t()
+{
+int i;
+/* Redefine nodekind to be 1 for all surface nodes */
+
+  for (i = 0; i < ARCHnodes; i++) {
+    nodekind[i] = (int) nodekindf[i];
+    if (nodekind[i] == 3)
+      nodekind[i] = 1;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov5.c
new file mode 100644
index 000000000..898323b44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov5.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "sbb" } } */
+
+int
+t(float a, float b)
+{
+	return a<=b?0:-1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov6.c
new file mode 100644
index 000000000..535326e4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov6.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "cmov\[^6\]" } } */
+
+/* Verify that blocks are converted to conditional moves.  */
+extern int bar (int, int);
+int foo (int c, int d, int e)
+{
+  int a, b;
+
+  if (c)
+    {
+      a = 10;
+      b = d;
+    }
+  else
+    {
+      a = e;
+      b = 20;
+    }
+  return bar (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov7.c
new file mode 100644
index 000000000..433bf57f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov7.c
@@ -0,0 +1,16 @@
+/* PR middle-end/33187 */
+
+/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
+/* { dg-options "-O2 -ffast-math -march=k8 -mbranch-cost=5 -mfpmath=387" } */
+/* { dg-final { scan-assembler "fcmov" } } */
+
+/* compress_float_constant generates load + float_extend
+   sequence which combine pass failed to combine into
+   (set (reg:DF) (float_extend:DF (mem:SF (symbol_ref...)))).  */
+
+double
+sgn (double __x)
+{
+  return __x >= 0.0 ? 1.0 : -1.0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov8.c
new file mode 100644
index 000000000..2d95c25da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmov8.c
@@ -0,0 +1,13 @@
+/* PR target/36936 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=i686" } */
+/* { dg-final { scan-assembler "cmov\[^8\]" } } */
+
+int
+foo (int x)
+{
+  if (x < 0)
+    x = 1;
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c
new file mode 100644
index 000000000..e3402014e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cmpxchg16b-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mcx16" } */
+
+typedef int TItype __attribute__ ((mode (TI)));
+
+TItype m_128;
+
+void test(TItype x_128)
+{
+  m_128 = __sync_val_compare_and_swap (&m_128, x_128, m_128);
+}
+
+/* { dg-final { scan-assembler "cmpxchg16b\[ \\t]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-1.c
new file mode 100644
index 000000000..db81ee837
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+#include <string.h>
+static inline
+__attribute__ ((cold))
+my_cold_memset (void *a, int b,int c)
+{
+  memset (a,b,c);
+}
+t(void *a,int b,int c)
+{
+  if (a)
+    my_cold_memset (a,b,40);
+}
+
+/* The IF conditional should be predicted as cold and my_cold_memset inlined
+   for size expanding memset as rep; stosb.  */
+/* { dg-final { scan-assembler "stosb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-2.c
new file mode 100644
index 000000000..4b61b9d56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 --param=builtin-expect-probability=100" } */
+#include <string.h>
+t(int c)
+{
+  if (__builtin_expect (c, 0))
+    {
+      cold_hint ();
+      return c * 11;
+    }
+  return c;
+}
+
+/* { dg-final { scan-assembler "imul" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-3.c
new file mode 100644
index 000000000..5225428c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+#include <string.h>
+
+int
+__attribute__ ((cold))
+t(int c)
+{
+  return c * 11;
+}
+
+/* { dg-final { scan-assembler "imul" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-4.c
new file mode 100644
index 000000000..37a41e954
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cold-attribute-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+#include <string.h>
+
+int
+__attribute__ ((cold))
+t(int c)
+{
+  return -1;
+}
+
+/* { dg-final { scan-assembler "orl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/combine-mul.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/combine-mul.c
new file mode 100644
index 000000000..8a2e86284
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/combine-mul.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-final { scan-assembler-not "12345" } } */
+
+static inline unsigned int myrnd (void)
+{
+    static unsigned int s = 1388815473;
+    s *= 1103515245;
+    s += 12345;
+}
+
+struct __attribute__ ((packed)) A {
+    unsigned short i:1, l:1, j:3, k:11;
+};
+
+struct A sA;
+void testA (void)
+{
+    char *p = (char *) &sA;
+    *p++ = myrnd ();
+    *p++ = myrnd ();
+    sA.k = -1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c
new file mode 100644
index 000000000..e4d71c21c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-387-pic.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=387 -fpic" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "flds" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-387.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-387.c
new file mode 100644
index 000000000..03a834d2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-387.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=387" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "flds" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c
new file mode 100644
index 000000000..ef024dd0b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-sse-pic.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=sse -fpic" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "movsd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-sse.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-sse.c
new file mode 100644
index 000000000..c56be1300
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/compress-float-sse.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=pentium4 -mtune=prescott -mfpmath=sse" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "movsd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/conversion.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/conversion.c
new file mode 100644
index 000000000..c1718f027
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/conversion.c
@@ -0,0 +1,57 @@
+/* Check that conversion functions don't leak into global namespace.  */
+
+/* { dg-do link } */
+/* { dg-options "-ffast-math" }  */
+/* { dg-add-options c99_runtime } */
+
+#include "../../gcc.dg/builtins-config.h"
+
+int ifloor (double a) { return __builtin_ifloor (a); }
+#ifdef HAVE_C99_RUNTIME
+int ifloorf (float a) { return __builtin_ifloorf (a); }
+int ifloorl (long double a) { return __builtin_ifloorl (a); }
+#endif
+
+long lfloor (double a) { return __builtin_lfloor (a); }
+#ifdef HAVE_C99_RUNTIME
+long lfloorf (float a) { return __builtin_lfloorf (a); }
+long lfloorl (long double a) { return __builtin_lfloorl (a); }
+#endif
+
+long long llfloor (double a) { return __builtin_llfloor (a); }
+#ifdef HAVE_C99_RUNTIME
+long long llfloorf (float a) { return __builtin_llfloorf (a); }
+long long llfloorl (long double a) { return __builtin_llfloorl (a); }
+#endif
+
+int iceil (double a) { return __builtin_iceil (a); }
+#ifdef HAVE_C99_RUNTIME
+int iceilf (float a) { return __builtin_iceilf (a); }
+int iceill (long double a) { return __builtin_iceill (a); }
+#endif
+
+long lceil (double a) { return __builtin_lceil (a); }
+#ifdef HAVE_C99_RUNTIME
+long lceilf (float a) { return __builtin_lceilf (a); }
+long lceill (long double a) { return __builtin_lceill (a); }
+#endif
+
+long long llceil (double a) { return __builtin_llceil (a); }
+#ifdef HAVE_C99_RUNTIME
+long long llceilf (float a) { return __builtin_llceilf (a); }
+long long llceill (long double a) { return __builtin_llceill (a); }
+#endif
+
+int iround (double a) { return __builtin_iround (a); }
+#ifdef HAVE_C99_RUNTIME
+int iroundf (float a) { return __builtin_iroundf (a); }
+int iroundl (long double a) { return __builtin_iroundl (a); }
+#endif
+
+int irint (double a) { return __builtin_irint (a); }
+#ifdef HAVE_C99_RUNTIME
+int irintf (float a) { return __builtin_irintf (a); }
+int irintl (long double a) { return __builtin_irintl (a); }
+#endif
+
+int main () { return 0; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-1.c
new file mode 100644
index 000000000..b3ed5b684
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcrc32" } */
+/* { dg-final { scan-assembler "crc32b\[^\\n\]*eax" } } */
+/* { dg-final { scan-assembler "crc32w\[^\\n\]*eax" } } */
+/* { dg-final { scan-assembler "crc32l\[^\\n\]*eax" } } */
+
+unsigned int
+crc32b (unsigned int x, unsigned char y)
+{
+  return __builtin_ia32_crc32qi (x, y);
+}
+
+unsigned int
+crc32w (unsigned int x, unsigned short y)
+{
+  return __builtin_ia32_crc32hi (x, y);
+}
+
+unsigned int
+crc32d (unsigned int x, unsigned int y)
+{
+  return __builtin_ia32_crc32si (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-2.c
new file mode 100644
index 000000000..678cfd5a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcrc32" } */
+/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target { ! { ia32 } } } } } */
+
+unsigned long long
+crc32d (unsigned long long x, unsigned long long y)
+{
+  return __builtin_ia32_crc32di (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-3.c
new file mode 100644
index 000000000..7518a4526
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -mcrc32" } */
+/* { dg-final { scan-assembler "__builtin_ia32_crc32di" } } */
+
+unsigned long long
+crc32d (unsigned long long x, unsigned long long y)
+{
+  return __builtin_ia32_crc32di (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-4.c
new file mode 100644
index 000000000..65ef4aa1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/crc32-4.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-sse4.2 -mno-crc32" } */
+/* { dg-final { scan-assembler "__builtin_ia32_crc32di" } } */
+
+unsigned long long
+crc32d (unsigned long long x, unsigned long long y)
+{
+  return __builtin_ia32_crc32di (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/cvt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/cvt-1.c
new file mode 100644
index 000000000..9535725e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/cvt-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mfpmath=sse" } */
+/* { dg-final { scan-assembler "cvttsd2si" } } */
+/* { dg-final { scan-assembler "cvttss2si" } } */
+int a,a1;
+double b;
+float b1;
+t()
+{
+	a=b;
+	a1=b1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/darwin-fpmath.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/darwin-fpmath.c
new file mode 100644
index 000000000..7db694670
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/darwin-fpmath.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target i?86-*-darwin* } } */
+/* { dg-final { scan-assembler "addsd" } } */
+/* Do not add -msse or -msse2 or -mfpmath=sse to the options.  GCC is
+   supposed to use SSE math on Darwin by default, and libm won't work
+   right if it doesn't.  */
+double foo(double x, double y)
+{
+  return x + y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/defines-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/defines-1.c
new file mode 100644
index 000000000..acc39f3f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/defines-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=nocona -mno-sse" } */
+
+#if defined(__SSE__) || defined(__SSE2__) || defined(__SSE3__)
+#error
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/defines-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/defines-2.c
new file mode 100644
index 000000000..4383a059b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/defines-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=athlon64 -mno-mmx" } */
+
+#if defined(__MMX__) || defined(__3dNOW__) || defined(__3dNOW_A__)
+#error
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-1.c
new file mode 100644
index 000000000..2769a21c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+__attribute__((noinline))
+test (int x, int y, int q, int r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+int
+main ()
+{
+  test (7, 6, 1, 1);
+  test (-7, -6, 1, -1);
+  test (-7, 6, -1, -1);
+  test (7, -6, -1, 1);
+  test (255, 254, 1, 1);
+  test (256, 254, 1, 2);
+  test (256, 256, 1, 0);
+  test (254, 256, 0, 254);
+  test (254, 255, 0, 254);
+  test (254, 1, 254, 0);
+  test (255, 2, 127, 1);
+  test (1, 256, 0, 1);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-2.c
new file mode 100644
index 000000000..0e73b2736
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+int
+foo (int x, int y)
+{
+   return x / y;
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "idivl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-3.c
new file mode 100644
index 000000000..4b8443699
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+int
+foo (int x, int y)
+{
+   return x % y;
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "idivl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-4.c
new file mode 100644
index 000000000..7124d7a06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+test (int x, int y, int q, int r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "idivl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-4a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-4a.c
new file mode 100644
index 000000000..572b3df3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-4a.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+test (int x, int y, int q, int r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+/* { dg-final { scan-assembler-not "divb" } } */
+/* { dg-final { scan-assembler-times "idivl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-5.c
new file mode 100644
index 000000000..8d179be9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-5.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void foo (int, int, int, int, int, int);
+
+void
+bar (int x, int y)
+{
+  foo (0, 0, 0, 0, x / y, x % y);
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "idivl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-6.c
new file mode 100644
index 000000000..c79dba0a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-6.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+__attribute__((noinline))
+test (long long x, long long y, long long q, long long r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+int
+main ()
+{
+  test (7, 6, 1, 1);
+  test (-7, -6, 1, -1);
+  test (-7, 6, -1, -1);
+  test (7, -6, -1, 1);
+  test (255, 254, 1, 1);
+  test (256, 254, 1, 2);
+  test (256, 256, 1, 0);
+  test (254, 256, 0, 254);
+  test (254, 255, 0, 254);
+  test (254, 1, 254, 0);
+  test (255, 2, 127, 1);
+  test (1, 256, 0, 1);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-7.c
new file mode 100644
index 000000000..de4a1fb93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-7.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+test (long long x, long long y, long long q, long long r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "idivq" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-8.c
new file mode 100644
index 000000000..eb09a6d7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/divmod-8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void foo (long long, long long, long long, long long,
+		 long long, long long);
+
+void
+bar (long long x, long long y)
+{
+  foo (0, 0, 0, 0, x / y, x % y);
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "idivq" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-1.c
new file mode 100644
index 000000000..1bd3b8868
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-1.c
@@ -0,0 +1,203 @@
+/* Excess precision tests.  Test that excess precision is carried
+   through various operations.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -mfpmath=387 -fexcess-precision=standard" } */
+
+#include <float.h>
+
+extern void abort (void);
+extern void exit (int);
+
+volatile float f1 = 1.0f;
+volatile float f2 = 0x1.0p-30f;
+volatile float f3 = 0x1.0p-60f;
+volatile double d1 = 1.0;
+volatile double d2 = 0x1.0p-30;
+volatile double d3 = 0x1.0p-60;
+volatile float fadd1 = 1.0f + 0x1.0p-30f;
+volatile double dadd2 = 1.0 + 0x1.0p-30 + 0x1.0p-60;
+volatile long double ldadd1 = 1.0l + 0x1.0p-30l;
+volatile long double ldadd2 = 1.0l + 0x1.0p-30l + 0x1.0p-60l;
+
+void
+test_add (void)
+{
+  if (f1 + f2 != ldadd1)
+    abort ();
+  if (f1 + f2 + f3 != ldadd2)
+    abort ();
+  if (d1 + d2 != ldadd1)
+    abort ();
+  if (d1 + d2 + d3 != ldadd2)
+    abort ();
+  if (f1 + d2 + f3 != ldadd2)
+    abort ();
+  if (f1 + f2 == fadd1)
+    abort ();
+  if (f1 + f2 <= fadd1)
+    abort ();
+  if (f1 + f2 < fadd1)
+    abort ();
+  if (sizeof(long double) > sizeof(double)) {
+    if ( d1 + d2 + d3 == dadd2)
+      abort ();
+    if (!(d1 + d2 + d3 > dadd2))
+      abort ();
+    if (!(d1 + d2 + d3 >= dadd2))
+      abort ();
+  }
+  else {
+    if ( d1 + d2 + d3 != dadd2 )
+      abort();
+    if ( d1 + d2 + d3 < dadd2 )
+      abort();
+    if ( d1 + d2 + d3 > dadd2 )
+      abort();
+  }
+}
+
+volatile long double ldsub1 = 1.0l - 0x1.0p-30l;
+volatile long double ldsub2 = 1.0l - 0x1.0p-30l - 0x1.0p-60l;
+
+void
+test_sub (void)
+{
+  if (f1 - f2 != ldsub1)
+    abort ();
+  if (f1 - f2 - f3 != ldsub2)
+    abort ();
+  if (d1 - d2 != ldsub1)
+    abort ();
+  if (d1 - d2 - d3 != ldsub2)
+    abort ();
+  if (f1 - d2 - f3 != ldsub2)
+    abort ();
+  if (+(f1 - d2 - f3) != ldsub2)
+    abort ();
+  if (-(f1 - d2 - f3) != -ldsub2)
+    abort ();
+}
+
+volatile float flt_min = FLT_MIN;
+volatile double dbl_min = DBL_MIN;
+volatile long double flt_min2 = (long double)FLT_MIN * (long double)FLT_MIN;
+volatile long double dbl_min3 = (long double)DBL_MIN * (long double)DBL_MIN * (long double)DBL_MIN;
+
+void
+test_mul (void)
+{
+  if (flt_min * flt_min != flt_min2)
+    abort ();
+  if (flt_min * flt_min == 0)
+    abort ();
+  if (flt_min * flt_min == 0)
+    abort ();
+  if (!(flt_min * flt_min))
+    abort ();
+  if (dbl_min * dbl_min * dbl_min != dbl_min3)
+    abort ();
+  if ((long double)(dbl_min * dbl_min * dbl_min) != dbl_min3)
+    abort ();
+  if ((0, dbl_min * dbl_min * dbl_min) != dbl_min3)
+    abort ();
+  if (sizeof(long double) > sizeof(double) ) {
+    if (dbl_min * dbl_min * dbl_min == 0)
+      abort ();
+    if ((flt_min * flt_min ? dbl_min * dbl_min * dbl_min : 0) == 0)
+      abort ();
+  }
+  else {
+    if (dbl_min * dbl_min * dbl_min != 0)
+      abort ();
+    if ((flt_min * flt_min ? dbl_min * dbl_min * dbl_min : 1) != 0)
+      abort ();
+  }
+  if ((flt_min * flt_min ? : 0) == 0)
+    abort ();
+}
+
+volatile float f4 = 0x1.0p100f;
+volatile double d4 = 0x1.0p100;
+volatile long double flt_div = 0x1.0p100l / (long double) FLT_MIN;
+volatile long double dbl_div = 0x1.0p100l / (long double) DBL_MIN;
+
+void
+test_div (void)
+{
+  if (f4 / flt_min != flt_div)
+    abort ();
+  if (d4 / dbl_min != dbl_div)
+    abort ();
+}
+
+volatile float f5 = 0x1.0p30;
+
+void
+test_cast (void)
+{
+  if ((int)(f1 + f5) != 0x40000001)
+    abort ();
+}
+
+volatile float _Complex f1c = 1.0f + 1.0if;
+volatile float _Complex f2c = 0x1.0p-30f + 0x1.0p-31if;
+volatile float _Complex f3c = 0x1.0p-60f + 0x1.0p-59if;
+volatile double _Complex d1c = 1.0 + 1.0i;
+volatile double _Complex d2c = 0x1.0p-30 + 0x1.0p-31i;
+volatile double _Complex d3c = 0x1.0p-60 + 0x1.0p-59i;
+volatile long double _Complex ldadd1c = 1.0l + 0x1.0p-30l + 1.0il + 0x1.0p-31il;
+volatile long double _Complex ldadd2c = 1.0l + 0x1.0p-30l + 0x1.0p-60l + 1.0il + 0x1.0p-31il + 0x1.0p-59il;
+volatile long double _Complex ldadd2cc = 1.0l + 0x1.0p-30l + 0x1.0p-60l - 1.0il - 0x1.0p-31il - 0x1.0p-59il;
+volatile float _Complex flt_minc = FLT_MIN;
+volatile double _Complex dbl_minc = DBL_MIN;
+volatile float _Complex f4c = 0x1.0p100f;
+volatile double _Complex d4c = 0x1.0p100;
+
+void
+test_complex (void)
+{
+  if (f1c + f2c != ldadd1c)
+    abort ();
+  if (f1c + f2c + f3c != ldadd2c)
+    abort ();
+  if (d1c + d2c != ldadd1c)
+    abort ();
+  if (d1c + d2c + d3c != ldadd2c)
+    abort ();
+  if (__real__ (f1c + f2c + f3c) != ldadd2)
+    abort ();
+  if (__imag__ (d1c + d2c + d3c) != __imag__ ldadd2c)
+    abort ();
+  if (~(d1c + d2c + d3c) != ldadd2cc)
+    abort ();
+  /* The following call libgcc functions and so would fail unless they
+     call those for long double.  */
+  if (flt_minc * flt_minc != flt_min2)
+    abort ();
+  if (dbl_minc * dbl_minc * dbl_minc != dbl_min3)
+    abort ();
+  if (f4c / flt_minc != flt_div)
+    abort ();
+  if (d4c / dbl_minc != dbl_div)
+    abort ();
+  if (f4 / flt_minc != flt_div)
+    abort ();
+  if (d4 / dbl_minc != dbl_div)
+    abort ();
+  if (f4c / flt_min != flt_div)
+    abort ();
+  if (d4c / dbl_min != dbl_div)
+    abort ();
+}
+
+int
+main (void)
+{
+  test_add ();
+  test_sub ();
+  test_mul ();
+  test_div ();
+  test_cast ();
+  test_complex ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-2.c
new file mode 100644
index 000000000..b5035e5a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-2.c
@@ -0,0 +1,33 @@
+/* Excess precision tests.  Test excess precision of constants.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -mfpmath=387 -fexcess-precision=standard" } */
+
+#include <float.h>
+
+extern void abort (void);
+extern void exit (int);
+
+volatile long double ldadd1 = 1.0l + 0x1.0p-30l;
+volatile long double ld11f = 1.1f;
+volatile long double ld11d = 1.1;
+volatile long double ld11 = 1.1;
+
+void
+test_const (void)
+{
+  if (1.0f + 0x1.0p-30f != ldadd1)
+    abort ();
+  if (ld11f != ld11)
+    abort ();
+  if (ld11d != ld11)
+    abort ();
+  if (1.1f != ld11)
+    abort ();
+}
+
+int
+main (void)
+{
+  test_const ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-3.c
new file mode 100644
index 000000000..1fd038a87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-3.c
@@ -0,0 +1,237 @@
+/* Excess precision tests.  Test excess precision is removed when
+   necessary.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -mfpmath=387 -fexcess-precision=standard" } */
+
+#include <float.h>
+#include <stdarg.h>
+
+extern void abort (void);
+extern void exit (int);
+
+volatile float f1 = 1.0f;
+volatile float f2 = 0x1.0p-30f;
+volatile float f3 = 0x1.0p-60f;
+volatile double d1 = 1.0;
+volatile double d2 = 0x1.0p-30;
+volatile double d3 = 0x1.0p-60;
+volatile double d3d = 0x1.0p-52;
+volatile float fadd1 = 1.0f + 0x1.0p-30f;
+volatile double dadd2 = 1.0 + 0x1.0p-30 + 0x1.0p-60;
+volatile double dh = 0x1.0p-24;
+volatile float fha = 1.0f + 0x1.0p-23f;
+
+void
+test_assign (void)
+{
+  float f;
+  double d;
+  f = f1 + f2;
+  if (f != fadd1)
+    abort ();
+  d = f1 + f2;
+  if (d != dadd2)
+    abort ();
+  d = d1 + d2 + d3;
+  if (d != dadd2)
+    abort ();
+  /* Verify rounding direct to float without double rounding.  */
+  if (sizeof(long double) > sizeof(double)  )  {
+    f = d1 + dh + d3;
+    if (f != fha)
+      abort ();
+  } else {
+      f = d1 + dh + d3d;
+      if (f != fha)
+        abort ();
+  }
+}
+
+void
+test_init (void)
+{
+  float f = f1 + f2;
+  double d = d1 + d2 + d3;
+  if (f != fadd1)
+    abort ();
+  if (d != dadd2)
+    abort ();
+}
+
+volatile int i1 = 0x40000001;
+volatile unsigned int u1 = 0x80000001u;
+volatile long long ll1 = 0x4000000000000001ll;
+volatile unsigned long long ull1 = 0x8000000000000001ull;
+
+void
+test_cast (void)
+{
+  if ((float)(f1 + f2) != fadd1)
+    abort ();
+  if ((double)(d1 + d2 + d3) != dadd2)
+    abort ();
+  if ((double)(f1 + f2 + f3) != dadd2)
+    abort ();
+  if ((float)i1 != 0x1.0p30f)
+    abort ();
+  if ((float)u1 != 0x1.0p31f)
+    abort ();
+  if ((float)ll1 != 0x1.0p62f)
+    abort ();
+  if ((float)ull1 != 0x1.0p63f)
+    abort ();
+  if ((double)ll1 != 0x1.0p62)
+    abort ();
+  if ((double)ull1 != 0x1.0p63)
+    abort ();
+}
+
+static inline void
+check_float (float f)
+{
+  if (f != fadd1)
+    abort ();
+}
+
+static inline void
+check_double (double d)
+{
+  if (d != dadd2)
+    abort ();
+}
+
+static inline void
+check_float_nonproto (f)
+     float f;
+{
+  if (f != fadd1)
+    abort ();
+}
+
+static inline void
+check_double_nonproto (d)
+     double d;
+{
+  if (d != dadd2)
+    abort ();
+}
+
+static void
+check_double_va (int i, ...)
+{
+  va_list ap;
+  va_start (ap, i);
+  if (va_arg (ap, double) != dadd2)
+    abort ();
+  va_end (ap);
+}
+
+void
+test_call (void)
+{
+  check_float (f1 + f2);
+  check_double (d1 + d2 + d3);
+  check_double (f1 + f2 + f3);
+  check_float_nonproto (f1 + f2);
+  check_double_nonproto (d1 + d2 + d3);
+  check_double_nonproto (f1 + f2 + f3);
+  check_double_va (0, d1 + d2 + d3);
+  check_double_va (0, f1 + f2 + f3);
+}
+
+static inline float
+return_float (void)
+{
+  return f1 + f2;
+}
+
+static inline double
+return_double1 (void)
+{
+  return d1 + d2 + d3;
+}
+
+static inline double
+return_double2 (void)
+{
+  return f1 + f2 + f3;
+}
+
+void
+test_return (void)
+{
+  if (return_float () != fadd1)
+    abort ();
+  if (return_double1 () != dadd2)
+    abort ();
+  if (return_double2 () != dadd2)
+    abort ();
+}
+
+volatile float flt_min = FLT_MIN;
+volatile double dbl_min = DBL_MIN;
+volatile float flt_max = FLT_MAX;
+volatile double dbl_max = DBL_MAX;
+
+void
+test_builtin (void)
+{
+  /* Classification macros convert to the semantic type.  signbit and
+     comparison macros do not.  */
+  if (!__builtin_isinf (flt_max * flt_max))
+    abort ();
+  if (!__builtin_isinf (dbl_max * dbl_max))
+    abort ();
+  if (__builtin_isnormal (flt_max * flt_max))
+    abort ();
+  if (__builtin_isnormal (dbl_max * dbl_max))
+    abort ();
+  if (__builtin_isfinite (flt_max * flt_max))
+    abort ();
+  if (__builtin_isfinite (dbl_max * dbl_max))
+    abort ();
+  if (!__builtin_isgreater (flt_min * flt_min, 0.0f))
+    abort ();
+  if (!__builtin_isgreaterequal (flt_min * flt_min, 0.0f))
+    abort ();
+  if (!__builtin_isless (0.0f, flt_min * flt_min))
+    abort ();
+  if (__builtin_islessequal (flt_min * flt_min, 0.0f))
+    abort ();
+  if (!__builtin_islessgreater (flt_min * flt_min, 0.0f))
+    abort ();
+  if (!__builtin_isgreaterequal (dbl_min * dbl_min, 0.0))
+    abort ();
+  if (sizeof(long double) > sizeof(double)  ) {
+    if (!__builtin_isgreater (dbl_min * dbl_min, 0.0))
+      abort ();
+    if (!__builtin_isless (0.0, dbl_min * dbl_min))
+      abort ();
+    if (__builtin_islessequal (dbl_min * dbl_min, 0.0))
+      abort ();
+    if (!__builtin_islessgreater (dbl_min * dbl_min, 0.0))
+      abort ();
+  }
+  else {
+    if (__builtin_isgreater (dbl_min * dbl_min, 0.0))
+      abort ();
+    if (__builtin_isless (0.0, dbl_min * dbl_min))
+      abort ();
+    if (!__builtin_islessequal (dbl_min * dbl_min, 0.0))
+      abort ();
+    if (__builtin_islessgreater (dbl_min * dbl_min, 0.0))
+      abort ();
+  }
+}
+
+int
+main (void)
+{
+  test_assign ();
+  test_init ();
+  test_cast ();
+  test_call ();
+  test_return ();
+  test_builtin ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-4.c
new file mode 100644
index 000000000..04e88a375
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-4.c
@@ -0,0 +1,7 @@
+/* Excess precision tests.  Test diagnostics for excess precision of
+   constants.  */
+/* { dg-do compile } */
+/* { dg-options "-mfpmath=387 -fexcess-precision=standard" } */
+
+float f = 0.0f * 1e50f; /* { dg-warning "floating constant exceeds range of 'float'" } */
+double d = 0.0 * 1e400; /* { dg-warning "floating constant exceeds range of 'double'" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-5.c
new file mode 100644
index 000000000..1cc7e589c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-5.c
@@ -0,0 +1,22 @@
+/* Excess precision tests.  Verify excess precision doesn't affect
+   actual types.  */
+/* { dg-do compile } */
+/* { dg-options "-mfpmath=387 -fexcess-precision=standard" } */
+
+float f;
+double d;
+
+void
+test_types (void)
+{
+  float *fp;
+  double *dp;
+#define CHECK_FLOAT(E) fp = &(typeof(E)){0}
+#define CHECK_DOUBLE(E) dp = &(typeof(E)){0}
+  CHECK_FLOAT (f + f);
+  CHECK_DOUBLE (d + d);
+  CHECK_FLOAT (f * f / f);
+  CHECK_DOUBLE (d * d / d);
+  CHECK_FLOAT (f ? f - f : f);
+  CHECK_DOUBLE (d ? d - d : d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-6.c
new file mode 100644
index 000000000..fb8d57232
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/excess-precision-6.c
@@ -0,0 +1,19 @@
+/* Excess precision tests.  Make sure sqrt is not inlined for float or
+   double.  */
+/* { dg-do compile } */
+/* { dg-options "-mfpmath=387 -O2 -fno-math-errno -fexcess-precision=standard" } */
+
+float f;
+double d;
+
+float fr;
+double dr;
+
+void
+test_builtins (void)
+{
+  fr = __builtin_sqrtf (f);
+  dr = __builtin_sqrt (d);
+}
+
+/* { dg-final { scan-assembler-not "fsqrt" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-1.c
new file mode 100644
index 000000000..102beb230
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic" } */
+
+int
+foo (unsigned char x, unsigned char y)
+{
+   return (x % y) != 0;
+}
+
+/* { dg-final { scan-assembler-not "test\[b\]?\[^\\n\]*%\[a-d\]l" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-2.c
new file mode 100644
index 000000000..3bb5f154c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic" } */
+
+int
+foo (unsigned char x, unsigned char y)
+{
+   return (x % y) > 4;
+}
+
+/* { dg-final { scan-assembler-times "cmp\[b\]?\[^\\n\]*%\[a-d\]h" 1 } } */
+/* { dg-final { scan-assembler-not "cmp\[b\]?\[^\\n\]*%\[a-d\]l" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-3.c
new file mode 100644
index 000000000..520bf3bb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic" } */
+
+typedef struct
+{
+  unsigned char c1;
+  unsigned char c2;
+  unsigned char c3;
+  unsigned char c4;
+} foo_t;
+
+int
+#ifndef __x86_64__
+__attribute__((regparm(3)))
+#endif
+foo (foo_t x)
+{
+   return x.c2 != 0;
+}
+
+/* { dg-final { scan-assembler-not "test\[b\]?\[^\\n\]*%\[a-z0-9\]+l" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-4.c
new file mode 100644
index 000000000..716ae2299
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-4.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic" } */
+
+typedef struct
+{
+  unsigned char c1;
+  unsigned char c2;
+  unsigned char c3;
+  unsigned char c4;
+} foo_t;
+
+int
+#ifndef __x86_64__
+__attribute__((regparm(3)))
+#endif
+foo (foo_t x)
+{
+   return x.c2 > 4;
+}
+
+/* { dg-final { scan-assembler-times "cmp\[b\]?\[^\\n\]*%\[a-z0-9\]+h" 1 } } */
+/* { dg-final { scan-assembler-not "cmp\[b\]?\[^\\n\]*%\[a-z0-9\]+l" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-5.c
new file mode 100644
index 000000000..a488dafa2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-5.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic" } */
+
+typedef struct
+{
+  unsigned int c1:8;
+  unsigned int c2:8;
+  unsigned int c3:8;
+  unsigned int c4:8;
+} foo_t;
+
+int
+#ifndef __x86_64__
+__attribute__((regparm(3)))
+#endif
+foo (foo_t x)
+{
+   return x.c2 != 0;
+}
+
+/* { dg-final { scan-assembler-not "test\[b\]?\[^\\n\]*%\[a-z0-9\]+l" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-6.c
new file mode 100644
index 000000000..1440ec3be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/extract-6.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic" } */
+
+typedef struct
+{
+  unsigned int c1:8;
+  unsigned int c2:8;
+  unsigned int c3:8;
+  unsigned int c4:8;
+
+} foo_t;
+
+int
+#ifndef __x86_64__
+__attribute__((regparm(3)))
+#endif
+foo (foo_t x)
+{
+   return x.c2 > 4;
+}
+
+/* { dg-final { scan-assembler-times "cmp\[b\]?\[^\\n\]*%\[a-z0-9\]+h" 1 } } */
+/* { dg-final { scan-assembler-not "cmp\[b\]?\[^\\n\]*%\[a-z0-9\]+l" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/f16c-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/f16c-check.h
new file mode 100644
index 000000000..af7f32c5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/f16c-check.h
@@ -0,0 +1,30 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include "cpuid.h"
+#include "m256-check.h"
+
+static void f16c_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run F16C test only if host has F16C support.  */
+  if (ecx & bit_F16C)
+    {
+      f16c_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fastcall-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fastcall-1.c
new file mode 100644
index 000000000..9d7012391
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fastcall-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target i?86-*-mingw32* i?86-*-cygwin* } } */
+/* { dg-options "-std=gnu89" } */
+
+void
+__attribute__ ((fastcall))
+f1() { }
+
+void
+_fastcall
+f2() { }
+
+void
+__fastcall
+f3() { }
+
+void
+__attribute__ ((fastcall))
+f4(int x, int y, int z) { }
+
+/* Scan for global label with correct prefix and suffix.  */
+/* { dg-final { scan-assembler "\.globl\[ \t\]@f4@12" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c
new file mode 100644
index 000000000..3f33f6b21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fastcall-sseregparm.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-mpreferred-stack-boundary=4 -msse" } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+extern void abort(void);
+
+void __attribute__((fastcall, sseregparm)) foo(int i, int j, float x)
+{
+  static int last_align = -1;
+  int dummy, align = (int)&dummy & 15;
+  if (last_align < 0)
+    last_align = align;
+  else if (align != last_align)
+    abort ();
+}
+
+static void
+sse_test (void)
+{
+	foo(0,0,0.0);
+	foo(0,0,0.0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/float128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/float128-1.c
new file mode 100644
index 000000000..76f5dba50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/float128-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+extern void abort (void);
+
+typedef _Complex float __attribute__((mode(TC))) _Complex128;
+
+_Complex128 __attribute__ ((noinline))
+foo (_Complex128 x, _Complex128 y)
+{
+  return x * y;
+}
+
+static void
+sse2_test (void)
+{
+  _Complex128 a = 1.3q + 3.4qi, b = 5.6q + 7.8qi, c;
+
+  c = foo (a, b);
+  if (__real__(c) == 0.0q || __imag__ (c) == 0.0q)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/float128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/float128-2.c
new file mode 100644
index 000000000..ae899ab23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/float128-2.c
@@ -0,0 +1,18 @@
+/* PR target/36710 */
+
+/* { dg-do run } */
+/* { dg-options "-Os -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+extern void abort (void);
+
+static void
+sse2_test (void)
+{
+  static volatile __float128 a = 123.0q;
+
+  if ((int) a != 123)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c
new file mode 100644
index 000000000..7e73402fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmaddXX.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm256_fmadd_pd (__m256d __A, __m256d __B, __m256d __C)
+{
+  union256d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[4];
+  int i;
+  e.x = _mm256_fmadd_pd (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + c.a[i];
+    }
+  if (check_union256d (e, d))
+    abort ();
+}
+
+void
+check_mm256_fmadd_ps (__m256 __A, __m256 __B, __m256 __C)
+{
+  union256 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[8];
+  int i;
+  e.x = _mm256_fmadd_ps (__A, __B, __C);
+  for (i = 0; i < 8; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + c.a[i];
+    }
+  if (check_union256 (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union256 c[3];
+  union256d d[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 8; j++)
+	c[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 4; j++)
+	d[i].a[j] = i * j + 3.5;
+    }
+  check_mm256_fmadd_pd (d[0].x, d[1].x, d[2].x);
+  check_mm256_fmadd_ps (c[0].x, c[1].x, c[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c
new file mode 100644
index 000000000..4b61ad5f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmaddsubXX.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm256_fmaddsub_ps (__m256 __A, __m256 __B, __m256 __C)
+{
+  union256 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[8];
+  int i;
+  e.x = _mm256_fmaddsub_ps (__A, __B, __C);
+  for (i = 0; i < 8; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]);
+    }
+  if (check_union256 (e, d))
+    abort ();
+}
+
+void
+check_mm256_fmaddsub_pd (__m256d __A, __m256d __B, __m256d __C)
+{
+  union256d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[4];
+  int i;
+  e.x = _mm256_fmaddsub_pd (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]);
+    }
+  if (check_union256d (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union256 c[3];
+  union256d d[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 8; j++)
+	c[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 4; j++)
+	d[i].a[j] = i * j + 3.5;
+    }
+  check_mm256_fmaddsub_pd (d[0].x, d[1].x, d[2].x);
+  check_mm256_fmaddsub_ps (c[0].x, c[1].x, c[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c
new file mode 100644
index 000000000..d92aec0ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmsubXX.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+
+void
+check_mm256_fmsub_pd (__m256d __A, __m256d __B, __m256d __C)
+{
+  union256d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[4];
+  int i;
+  e.x = _mm256_fmsub_pd (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = a.a[i] * b.a[i] - c.a[i];
+    }
+  if (check_union256d (e, d))
+    abort ();
+}
+
+void
+check_mm256_fmsub_ps (__m256 __A, __m256 __B, __m256 __C)
+{
+  union256 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[8];
+  int i;
+  e.x = _mm256_fmsub_ps (__A, __B, __C);
+  for (i = 0; i < 8; i++)
+    {
+      d[i] = a.a[i] * b.a[i] - c.a[i];
+    }
+  if (check_union256 (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union256 c[3];
+  union256d d[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 8; j++)
+	c[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 4; j++)
+	d[i].a[j] = i * j + 3.5;
+    }
+  check_mm256_fmsub_pd (d[0].x, d[1].x, d[2].x);
+  check_mm256_fmsub_ps (c[0].x, c[1].x, c[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c
new file mode 100644
index 000000000..84a41c4c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fmsubaddXX.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm256_fmsubadd_ps (__m256 __A, __m256 __B, __m256 __C)
+{
+  union256 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[8];
+  int i;
+  e.x = _mm256_fmsubadd_ps (__A, __B, __C);
+  for (i = 0; i < 8; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]);
+    }
+  if (check_union256 (e, d))
+    abort ();
+}
+
+void
+check_mm256_fmsubadd_pd (__m256d __A, __m256d __B, __m256d __C)
+{
+  union256d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[4];
+  int i;
+  e.x = _mm256_fmsubadd_pd (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]);
+    }
+  if (check_union256d (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union256 c[3];
+  union256d d[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 8; j++)
+	c[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 4; j++)
+	d[i].a[j] = i * j + 3.5;
+    }
+  check_mm256_fmsubadd_pd (d[0].x, d[1].x, d[2].x);
+  check_mm256_fmsubadd_ps (c[0].x, c[1].x, c[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c
new file mode 100644
index 000000000..c0dfa6900
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fnmaddXX.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm256_fnmadd_pd (__m256d __A, __m256d __B, __m256d __C)
+{
+  union256d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[4];
+  int i;
+  e.x = _mm256_fnmadd_pd (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = -a.a[i] * b.a[i] + c.a[i];
+    }
+  if (check_union256d (e, d))
+    abort ();
+}
+
+void
+check_mm256_fnmadd_ps (__m256 __A, __m256 __B, __m256 __C)
+{
+  union256 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[8];
+  int i;
+  e.x = _mm256_fnmadd_ps (__A, __B, __C);
+  for (i = 0; i < 8; i++)
+    {
+      d[i] = -a.a[i] * b.a[i] + c.a[i];
+    }
+  if (check_union256 (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union256 c[3];
+  union256d d[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 8; j++)
+	c[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 4; j++)
+	d[i].a[j] = i * j + 3.5;
+    }
+  check_mm256_fnmadd_pd (d[0].x, d[1].x, d[2].x);
+  check_mm256_fnmadd_ps (c[0].x, c[1].x, c[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c
new file mode 100644
index 000000000..ac4705e5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-256-fnmsubXX.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+
+void
+check_mm256_fnmsub_pd (__m256d __A, __m256d __B, __m256d __C)
+{
+  union256d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[4];
+  int i;
+  e.x = _mm256_fnmsub_pd (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = -a.a[i] * b.a[i] - c.a[i];
+    }
+  if (check_union256d (e, d))
+    abort ();
+}
+
+void
+check_mm256_fnmsub_ps (__m256 __A, __m256 __B, __m256 __C)
+{
+  union256 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[8];
+  int i;
+  e.x = _mm256_fnmsub_ps (__A, __B, __C);
+  for (i = 0; i < 8; i++)
+    {
+      d[i] = -a.a[i] * b.a[i] - c.a[i];
+    }
+  if (check_union256 (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union256 c[3];
+  union256d d[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 8; j++)
+	c[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 4; j++)
+	d[i].a[j] = i * j + 3.5;
+    }
+  check_mm256_fnmsub_pd (d[0].x, d[1].x, d[2].x);
+  check_mm256_fnmsub_ps (c[0].x, c[1].x, c[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-check.h
new file mode 100644
index 000000000..8390f5088
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-check.h
@@ -0,0 +1,25 @@
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void fma_test (void);
+
+static void __attribute__ ((noinline)) do_test (void)
+{
+  fma_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run FMA test only if host has FMA support.  */
+  if (ecx & bit_FMA)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-compile.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-compile.c
new file mode 100644
index 000000000..0445f7bc0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-compile.c
@@ -0,0 +1,221 @@
+/* Test that the compiler properly generates floating point multiply
+   and add instructions FMA systems.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfma" } */
+
+#include <x86intrin.h>
+
+__m128d
+check_mm_fmadd_pd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fmadd_pd (a, b, c);
+}
+
+__m256d
+check_mm256_fmadd_pd (__m256d a, __m256d b, __m256d c)
+{
+  return _mm256_fmadd_pd (a, b, c);
+}
+
+__m128
+check_mm_fmadd_ps (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fmadd_ps (a, b, c);
+}
+
+__m256
+check_mm256_fmadd_ps (__m256 a, __m256 b, __m256 c)
+{
+  return _mm256_fmadd_ps (a, b, c);
+}
+
+__m128d
+check_mm_fmadd_sd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fmadd_sd (a, b, c);
+}
+
+__m128
+check_mm_fmadd_ss (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fmadd_ss (a, b, c);
+}
+
+__m128d
+check_mm_fmsub_pd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fmsub_pd (a, b, c);
+}
+
+__m256d
+check_mm256_fmsub_pd (__m256d a, __m256d b, __m256d c)
+{
+  return _mm256_fmsub_pd (a, b, c);
+}
+
+__m128
+check_mm_fmsub_ps (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fmsub_ps (a, b, c);
+}
+
+__m256
+check_mm256_fmsub_ps (__m256 a, __m256 b, __m256 c)
+{
+  return _mm256_fmsub_ps (a, b, c);
+}
+
+__m128d
+check_mm_fmsub_sd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fmsub_sd (a, b, c);
+}
+
+__m128
+check_mm_fmsub_ss (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fmsub_ss (a, b, c);
+}
+
+__m128d
+check_mm_fnmadd_pd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fnmadd_pd (a, b, c);
+}
+
+__m256d
+check_mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c)
+{
+  return _mm256_fnmadd_pd (a, b, c);
+}
+
+__m128
+check_mm_fnmadd_ps (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fnmadd_ps (a, b, c);
+}
+
+__m256
+check_mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c)
+{
+  return _mm256_fnmadd_ps (a, b, c);
+}
+
+__m128d
+check_mm_fnmadd_sd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fnmadd_sd (a, b, c);
+}
+
+__m128
+check_mm_fnmadd_ss (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fnmadd_ss (a, b, c);
+}
+
+__m128d
+check_mm_fnmsub_pd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fnmsub_pd (a, b, c);
+}
+
+__m256d
+check_mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c)
+{
+  return _mm256_fnmsub_pd (a, b, c);
+}
+
+__m128
+check_mm_fnmsub_ps (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fnmsub_ps (a, b, c);
+}
+
+__m256
+check_mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c)
+{
+  return _mm256_fnmsub_ps (a, b, c);
+}
+
+__m128d
+check_mm_fnmsub_sd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fnmsub_sd (a, b, c);
+}
+
+__m128
+check_mm_fnmsub_ss (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fnmsub_ss (a, b, c);
+}
+
+__m128d
+check_mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fmaddsub_pd (a, b, c);
+}
+
+__m256d
+check_mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c)
+{
+  return _mm256_fmaddsub_pd (a, b, c);
+}
+
+__m128
+check_mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fmaddsub_ps (a, b, c);
+}
+
+__m256
+check_mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c)
+{
+  return _mm256_fmaddsub_ps (a, b, c);
+}
+
+__m128d
+check_mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c)
+{
+  return _mm_fmsubadd_pd (a, b, c);
+}
+
+__m256d
+check_mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c)
+{
+  return _mm256_fmsubadd_pd (a, b, c);
+}
+
+__m128
+check_mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c)
+{
+  return _mm_fmsubadd_ps (a, b, c);
+}
+
+__m256
+check_mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c)
+{
+  return _mm256_fmsubadd_ps (a, b, c);
+}
+
+
+/* { dg-final { scan-assembler-times "vfmadd\[^s\]..ps" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[^s\]..ps" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ps" 2 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...ps" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...ps" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[^s\]..pd" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[^s\]..pd" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...pd" 2 } } */
+/* { dg-final { scan-assembler-times "vfmaddsub...pd" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsubadd...pd" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[^s\]..ss" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[^s\]..ss" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ss" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ss" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[^s\]..sd" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[^s\]..sd" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...sd" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...sd" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c
new file mode 100644
index 000000000..43ef9e807
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmaddXX.c
@@ -0,0 +1,102 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm_fmadd_pd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fmadd_pd (__A, __B, __C);
+  for (i = 0; i < 2; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + c.a[i];
+    }
+
+  if (check_union128d (e, d))
+    abort ();
+}
+
+void
+check_mm_fmadd_ps (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fmadd_ps (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + c.a[i];
+    }
+  if (check_union128 (e, d))
+    abort ();
+}
+
+void
+check_mm_fmadd_sd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fmadd_sd (__A, __B, __C);
+  for (i = 1; i < 2; i++)
+    {
+      d[i] = a.a[i];
+    }
+  d[0] = a.a[0] * b.a[0] + c.a[0];
+  if (check_union128d (e, d))
+    abort ();
+}
+
+void
+check_mm_fmadd_ss (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fmadd_ss (__A, __B, __C);
+  for (i = 1; i < 4; i++)
+    {
+      d[i] = a.a[i];
+    }
+  d[0] = a.a[0] * b.a[0] + c.a[0];
+  if (check_union128 (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union128 a[3];
+  union128d b[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 4; j++)
+	a[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 2; j++)
+	b[i].a[j] = i * j + 3.5;
+    }
+  check_mm_fmadd_pd (b[0].x, b[1].x, b[2].x);
+  check_mm_fmadd_sd (b[0].x, b[1].x, b[2].x);
+  check_mm_fmadd_ps (a[0].x, a[1].x, a[2].x);
+  check_mm_fmadd_ss (a[0].x, a[1].x, a[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c
new file mode 100644
index 000000000..89c816392
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmaddsubXX.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm_fmaddsub_ps (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fmaddsub_ps (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]);
+    }
+  if (check_union128 (e, d))
+    abort ();
+}
+
+void
+check_mm_fmaddsub_pd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fmaddsub_pd (__A, __B, __C);
+  for (i = 0; i < 2; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? c.a[i] : -c.a[i]);
+    }
+  if (check_union128d (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union128 a[3];
+  union128d b[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 4; j++)
+	a[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 2; j++)
+	b[i].a[j] = i * j + 3.5;
+    }
+  check_mm_fmaddsub_pd (b[0].x, b[1].x, b[2].x);
+  check_mm_fmaddsub_ps (a[0].x, a[1].x, a[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c
new file mode 100644
index 000000000..3d92d4b25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmsubXX.c
@@ -0,0 +1,101 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm_fmsub_pd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fmsub_pd (__A, __B, __C);
+  for (i = 0; i < 2; i++)
+    {
+      d[i] = a.a[i] * b.a[i] - c.a[i];
+    }
+  if (check_union128d (e, d))
+    abort ();
+}
+
+void
+check_mm_fmsub_ps (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fmsub_ps (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = a.a[i] * b.a[i] - c.a[i];
+    }
+  if (check_union128 (e, d))
+    abort ();
+}
+
+void
+check_mm_fmsub_sd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fmsub_sd (__A, __B, __C);
+  for (i = 1; i < 2; i++)
+    {
+      d[i] = a.a[i];
+    }
+  d[0] = a.a[0] * b.a[0] - c.a[0];
+  if (check_union128d (e, d))
+    abort ();
+}
+
+void
+check_mm_fmsub_ss (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fmsub_ss (__A, __B, __C);
+  for (i = 1; i < 4; i++)
+    {
+      d[i] = a.a[i];
+    }
+  d[0] = a.a[0] * b.a[0] - c.a[0];
+  if (check_union128 (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union128 a[3];
+  union128d b[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 4; j++)
+	a[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 2; j++)
+	b[i].a[j] = i * j + 3.5;
+    }
+  check_mm_fmsub_pd (b[0].x, b[1].x, b[2].x);
+  check_mm_fmsub_sd (b[0].x, b[1].x, b[2].x);
+  check_mm_fmsub_ps (a[0].x, a[1].x, a[2].x);
+  check_mm_fmsub_ss (a[0].x, a[1].x, a[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c
new file mode 100644
index 000000000..b03f87531
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fmsubaddXX.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm_fmsubadd_ps (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fmsubadd_ps (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]);
+    }
+  if (check_union128 (e, d))
+    abort ();
+}
+
+void
+check_mm_fmsubadd_pd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fmsubadd_pd (__A, __B, __C);
+  for (i = 0; i < 2; i++)
+    {
+      d[i] = a.a[i] * b.a[i] + (i % 2 == 1 ? -c.a[i] : c.a[i]);
+    }
+  if (check_union128d (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union128 a[3];
+  union128d b[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 4; j++)
+	a[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 2; j++)
+	b[i].a[j] = i * j + 3.5;
+    }
+  check_mm_fmsubadd_pd (b[0].x, b[1].x, b[2].x);
+  check_mm_fmsubadd_ps (a[0].x, a[1].x, a[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c
new file mode 100644
index 000000000..f23a6c5e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fnmaddXX.c
@@ -0,0 +1,101 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm_fnmadd_ps (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fnmadd_ps (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = -a.a[i] * b.a[i] + c.a[i];
+    }
+  if (check_union128 (e, d))
+    abort ();
+}
+
+void
+check_mm_fnmadd_pd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fnmadd_pd (__A, __B, __C);
+  for (i = 0; i < 2; i++)
+    {
+      d[i] = -a.a[i] * b.a[i] + c.a[i];
+    }
+  if (check_union128d (e, d))
+    abort ();
+}
+
+void
+check_mm_fnmadd_sd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fnmadd_sd (__A, __B, __C);
+  for (i = 1; i < 2; i++)
+    {
+      d[i] = a.a[i];
+    }
+  d[0] = -a.a[0] * b.a[0] + c.a[0];
+  if (check_union128d (e, d))
+    abort ();
+}
+
+void
+check_mm_fnmadd_ss (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fnmadd_ss (__A, __B, __C);
+  for (i = 1; i < 4; i++)
+    {
+      d[i] = a.a[i];
+    }
+  d[0] = -a.a[0] * b.a[0] + c.a[0];
+  if (check_union128 (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union128 a[3];
+  union128d b[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 4; j++)
+	a[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 2; j++)
+	b[i].a[j] = i * j + 3.5;
+    }
+  check_mm_fnmadd_pd (b[0].x, b[1].x, b[2].x);
+  check_mm_fnmadd_sd (b[0].x, b[1].x, b[2].x);
+  check_mm_fnmadd_ps (a[0].x, a[1].x, a[2].x);
+  check_mm_fnmadd_ss (a[0].x, a[1].x, a[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c
new file mode 100644
index 000000000..d17c7f2ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma-fnmsubXX.c
@@ -0,0 +1,101 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O2 -mfma" } */
+
+#include "fma-check.h"
+
+#include <x86intrin.h>
+#include "m256-check.h"
+
+void
+check_mm_fnmsub_sd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fnmsub_sd (__A, __B, __C);
+  for (i = 1; i < 2; i++)
+    {
+      d[i] = a.a[i];
+    }
+  d[0] = -a.a[0] * b.a[0] - c.a[0];
+  if (check_union128d (e, d))
+    abort ();
+}
+
+void
+check_mm_fnmsub_ss (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fnmsub_ss (__A, __B, __C);
+  for (i = 1; i < 4; i++)
+    {
+      d[i] = a.a[i];
+    }
+  d[0] = -a.a[0] * b.a[0] - c.a[0];
+  if (check_union128 (e, d))
+    abort ();
+}
+
+void
+check_mm_fnmsub_ps (__m128 __A, __m128 __B, __m128 __C)
+{
+  union128 a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  float d[4];
+  int i;
+  e.x = _mm_fnmsub_ps (__A, __B, __C);
+  for (i = 0; i < 4; i++)
+    {
+      d[i] = -a.a[i] * b.a[i] - c.a[i];
+    }
+  if (check_union128 (e, d))
+    abort ();
+}
+
+void
+check_mm_fnmsub_pd (__m128d __A, __m128d __B, __m128d __C)
+{
+  union128d a, b, c, e;
+  a.x = __A;
+  b.x = __B;
+  c.x = __C;
+  double d[2];
+  int i;
+  e.x = _mm_fnmsub_pd (__A, __B, __C);
+  for (i = 0; i < 2; i++)
+    {
+      d[i] = -a.a[i] * b.a[i] - c.a[i];
+    }
+  if (check_union128d (e, d))
+    abort ();
+}
+
+static void
+fma_test (void)
+{
+  union128 a[3];
+  union128d b[3];
+  int i, j;
+  for (i = 0; i < 3; i++)
+    {
+      for (j = 0; j < 4; j++)
+	a[i].a[j] = i * j + 3.5;
+      for (j = 0; j < 2; j++)
+	b[i].a[j] = i * j + 3.5;
+    }
+  check_mm_fnmsub_pd (b[0].x, b[1].x, b[2].x);
+  check_mm_fnmsub_sd (b[0].x, b[1].x, b[2].x);
+  check_mm_fnmsub_ps (a[0].x, a[1].x, a[2].x);
+  check_mm_fnmsub_ss (a[0].x, a[1].x, a[2].x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-builtin-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-builtin-2.c
new file mode 100644
index 000000000..01768b963
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-builtin-2.c
@@ -0,0 +1,97 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mfma -mno-fma4 -mtune=generic" } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+double vda[SIZE] __attribute__((__aligned__(32)));
+double vdb[SIZE] __attribute__((__aligned__(32)));
+double vdc[SIZE] __attribute__((__aligned__(32)));
+double vdd[SIZE] __attribute__((__aligned__(32)));
+
+float vfa[SIZE] __attribute__((__aligned__(32)));
+float vfb[SIZE] __attribute__((__aligned__(32)));
+float vfc[SIZE] __attribute__((__aligned__(32)));
+float vfd[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_fma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]);
+}
+
+void
+vector_fms (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]);
+}
+
+void
+vector_fnma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (-vdb[i], vdc[i], vdd[i]);
+}
+
+void
+vector_fnms (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (-vdb[i], vdc[i], -vdd[i]);
+}
+
+void
+vector_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]);
+}
+
+void
+vector_fmsf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]);
+}
+
+void
+vector_fnmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (-vfb[i], vfc[i], vfd[i]);
+}
+
+void
+vector_fnmsf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (-vfb[i], vfc[i], -vfd[i]);
+}
+
+/* { dg-final { scan-assembler-times "vfmadd...ps" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...pd" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ps" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...pd" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ps" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...pd" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ps" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...pd" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-builtin.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-builtin.c
new file mode 100644
index 000000000..2d9c5c73a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-builtin.c
@@ -0,0 +1,81 @@
+/* Test that the compiler properly generates floating point multiply
+   and add instructions FMA3 systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfma -mno-fma4" } */
+
+#ifndef __FP_FAST_FMAF
+# error "__FP_FAST_FMAF should be defined"
+#endif
+#ifndef __FP_FAST_FMA
+# error "__FP_FAST_FMA should be defined"
+#endif
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return __builtin_fmaf (a, b, c);
+}
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return __builtin_fma (a, b, c);
+}
+
+float
+flt_mul_sub (float a, float b, float c)
+{
+  return __builtin_fmaf (a, b, -c);
+}
+
+double
+dbl_mul_sub (double a, double b, double c)
+{
+  return __builtin_fma (a, b, -c);
+}
+
+float
+flt_neg_mul_add_1 (float a, float b, float c)
+{
+  return __builtin_fmaf (-a, b, c);
+}
+
+double
+dbl_neg_mul_add_1 (double a, double b, double c)
+{
+  return __builtin_fma (-a, b, c);
+}
+
+float
+flt_neg_mul_add_2 (float a, float b, float c)
+{
+  return __builtin_fmaf (a, -b, c);
+}
+
+double
+dbl_neg_mul_add_2 (double a, double b, double c)
+{
+  return __builtin_fma (a, -b, c);
+}
+
+float
+flt_neg_mul_sub (float a, float b, float c)
+{
+  return __builtin_fmaf (-a, b, -c);
+}
+
+double
+dbl_neg_mul_sub (double a, double b, double c)
+{
+  return __builtin_fma (-a, b, -c);
+}
+
+/* { dg-final { scan-assembler-times "vfmadd...ss" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...sd" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ss" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...sd" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ss" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...sd" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ss" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...sd" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-fma.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-fma.c
new file mode 100644
index 000000000..f18f97bf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma3-fma.c
@@ -0,0 +1,81 @@
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions FMA3 systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfma -mno-fma4" } */
+
+extern void exit (int);
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return (a * b) + c;
+}
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return (a * b) + c;
+}
+
+float
+flt_mul_sub (float a, float b, float c)
+{
+  return (a * b) - c;
+}
+
+double
+dbl_mul_sub (double a, double b, double c)
+{
+  return (a * b) - c;
+}
+
+float
+flt_neg_mul_add (float a, float b, float c)
+{
+  return (-(a * b)) + c;
+}
+
+double
+dbl_neg_mul_add (double a, double b, double c)
+{
+  return (-(a * b)) + c;
+}
+
+float
+flt_neg_mul_sub (float a, float b, float c)
+{
+  return (-(a * b)) - c;
+}
+
+double
+dbl_neg_mul_sub (double a, double b, double c)
+{
+  return (-(a * b)) - c;
+}
+
+float  f[10] = { 2, 3, 4 };
+double d[10] = { 2, 3, 4 };
+
+int main ()
+{
+  f[3] = flt_mul_add (f[0], f[1], f[2]);
+  f[4] = flt_mul_sub (f[0], f[1], f[2]);
+  f[5] = flt_neg_mul_add (f[0], f[1], f[2]);
+  f[6] = flt_neg_mul_sub (f[0], f[1], f[2]);
+
+  d[3] = dbl_mul_add (d[0], d[1], d[2]);
+  d[4] = dbl_mul_sub (d[0], d[1], d[2]);
+  d[5] = dbl_neg_mul_add (d[0], d[1], d[2]);
+  d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vfmadd...ss" } } */
+/* { dg-final { scan-assembler "vfmadd...sd" } } */
+/* { dg-final { scan-assembler "vfmsub...ss" } } */
+/* { dg-final { scan-assembler "vfmsub...sd" } } */
+/* { dg-final { scan-assembler "vfnmadd...ss" } } */
+/* { dg-final { scan-assembler "vfnmadd...sd" } } */
+/* { dg-final { scan-assembler "vfnmsub...ss" } } */
+/* { dg-final { scan-assembler "vfnmsub...sd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-maccXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-maccXX.c
new file mode 100644
index 000000000..134200af7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-maccXX.c
@@ -0,0 +1,96 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma4 } */
+/* { dg-options "-O2 -mfma4" } */
+
+#include "fma4-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m256 x[NUM];
+  float f[NUM * 8];
+  __m256d y[NUM];
+  double d[NUM * 4];
+} dst, res, src1, src2, src3;
+
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_maccps ()
+{
+  int i;
+  for (i = 0; i < NUM * 8; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_maccpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_maccps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 8; i = i + 8)
+    for (j = 0; j < 8; j++)
+      {
+	res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_maccpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static void
+fma4_test (void)
+{
+  int i;
+
+  init_maccps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm256_macc_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_maccps ()) 
+    abort ();
+
+  init_maccpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm256_macc_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_maccpd ()) 
+    abort ();  
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-msubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-msubXX.c
new file mode 100644
index 000000000..d6cafb4d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-msubXX.c
@@ -0,0 +1,96 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma4 } */
+/* { dg-options "-O2 -mfma4" } */
+
+#include "fma4-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m256 x[NUM];
+  float f[NUM * 8];
+  __m256d y[NUM];
+  double d[NUM * 4];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_msubps ()
+{
+  int i;
+  for (i = 0; i < NUM * 8; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_msubpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_msubps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 8; i = i + 8)
+    for (j = 0; j < 8; j++)
+      {
+	res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_msubpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static void
+fma4_test (void)
+{
+  int i;
+
+  init_msubps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm256_msub_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_msubps ()) 
+    abort ();
+
+  init_msubpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm256_msub_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_msubpd ()) 
+    abort ();
+  
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-nmaccXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-nmaccXX.c
new file mode 100644
index 000000000..261f302f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-nmaccXX.c
@@ -0,0 +1,96 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma4 } */
+/* { dg-options "-O2 -mfma4" } */
+
+#include "fma4-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m256 x[NUM];
+  float f[NUM * 8];
+  __m256d y[NUM];
+  double d[NUM * 4];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_nmaccps ()
+{
+  int i;
+  for (i = 0; i < NUM * 8; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_nmaccpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_nmaccps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 8; i = i + 8)
+    for (j = 0; j < 8; j++)
+      {
+	res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_nmaccpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static void
+fma4_test (void)
+{
+  int i;
+
+  init_nmaccps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm256_nmacc_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmaccps ()) 
+    abort ();
+  
+  init_nmaccpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm256_nmacc_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmaccpd ()) 
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-nmsubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-nmsubXX.c
new file mode 100644
index 000000000..3205715ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-nmsubXX.c
@@ -0,0 +1,95 @@
+/* { dg-require-effective-target fma4 } */
+/* { dg-options "-O2 -mfma4" } */
+
+#include "fma4-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m256 x[NUM];
+  float f[NUM * 8];
+  __m256d y[NUM];
+  double d[NUM * 4];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_nmsubps ()
+{
+  int i;
+  for (i = 0; i < NUM * 8; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_nmsubpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_nmsubps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 8; i = i + 8)
+    for (j = 0; j < 8; j++)
+      {
+	res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_nmsubpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static void
+fma4_test (void)
+{
+  int i;
+
+  init_nmsubps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm256_nmsub_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmsubps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4])) 
+    abort ();
+
+  init_nmsubpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm256_nmsub_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmsubpd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2])) 
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-vector.c
new file mode 100644
index 000000000..edaa21a2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-256-vector.c
@@ -0,0 +1,92 @@
+/* Test that the compiler properly optimizes floating point multiply and add
+   instructions vector into vfmaddps on FMA4 systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */
+
+extern void exit (int);
+
+typedef float     __m256  __attribute__ ((__vector_size__ (32), __may_alias__));
+typedef double    __m256d __attribute__ ((__vector_size__ (32), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m256 f_align;
+  __m256d d_align;
+  float f[SIZE];
+  double d[SIZE];
+} a, b, c, d;
+
+void
+flt_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (b.f[i] * c.f[i]) + d.f[i];
+}
+
+void
+dbl_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (b.d[i] * c.d[i]) + d.d[i];
+}
+
+void
+flt_mul_sub (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (b.f[i] * c.f[i]) - d.f[i];
+}
+
+void
+dbl_mul_sub (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (b.d[i] * c.d[i]) - d.d[i];
+}
+
+void
+flt_neg_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (-(b.f[i] * c.f[i])) + d.f[i];
+}
+
+void
+dbl_neg_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (-(b.d[i] * c.d[i])) + d.d[i];
+}
+
+int main ()
+{
+  flt_mul_add ();
+  flt_mul_sub ();
+  flt_neg_mul_add ();
+
+  dbl_mul_add ();
+  dbl_mul_sub ();
+  dbl_neg_mul_add ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vfmaddps" } } */
+/* { dg-final { scan-assembler "vfmaddpd" } } */
+/* { dg-final { scan-assembler "vfmsubps" } } */
+/* { dg-final { scan-assembler "vfmsubpd" } } */
+/* { dg-final { scan-assembler "vfnmaddps" } } */
+/* { dg-final { scan-assembler "vfnmaddpd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin-2.c
new file mode 100644
index 000000000..18927bc09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin-2.c
@@ -0,0 +1,97 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mfma4 -mtune=generic" } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+double vda[SIZE] __attribute__((__aligned__(32)));
+double vdb[SIZE] __attribute__((__aligned__(32)));
+double vdc[SIZE] __attribute__((__aligned__(32)));
+double vdd[SIZE] __attribute__((__aligned__(32)));
+
+float vfa[SIZE] __attribute__((__aligned__(32)));
+float vfb[SIZE] __attribute__((__aligned__(32)));
+float vfc[SIZE] __attribute__((__aligned__(32)));
+float vfd[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_fma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]);
+}
+
+void
+vector_fms (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]);
+}
+
+void
+vector_fnma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (-vdb[i], vdc[i], vdd[i]);
+}
+
+void
+vector_fnms (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (-vdb[i], vdc[i], -vdd[i]);
+}
+
+void
+vector_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]);
+}
+
+void
+vector_fmsf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]);
+}
+
+void
+vector_fnmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (-vfb[i], vfc[i], vfd[i]);
+}
+
+void
+vector_fnmsf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (-vfb[i], vfc[i], -vfd[i]);
+}
+
+/* { dg-final { scan-assembler-times "vfmaddps" 1 } } */
+/* { dg-final { scan-assembler-times "vfmaddpd" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubps" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubpd" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmaddps" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmaddpd" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsubps" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsubpd" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin.c
new file mode 100644
index 000000000..7135cc933
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-builtin.c
@@ -0,0 +1,81 @@
+/* Test that the compiler properly generates floating point multiply
+   and add instructions FMA4 systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfma4" } */
+
+#ifndef __FP_FAST_FMAF
+# error "__FP_FAST_FMAF should be defined"
+#endif
+#ifndef __FP_FAST_FMA
+# error "__FP_FAST_FMA should be defined"
+#endif
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return __builtin_fmaf (a, b, c);
+}
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return __builtin_fma (a, b, c);
+}
+
+float
+flt_mul_sub (float a, float b, float c)
+{
+  return __builtin_fmaf (a, b, -c);
+}
+
+double
+dbl_mul_sub (double a, double b, double c)
+{
+  return __builtin_fma (a, b, -c);
+}
+
+float
+flt_neg_mul_add_1 (float a, float b, float c)
+{
+  return __builtin_fmaf (-a, b, c);
+}
+
+double
+dbl_neg_mul_add_1 (double a, double b, double c)
+{
+  return __builtin_fma (-a, b, c);
+}
+
+float
+flt_neg_mul_add_2 (float a, float b, float c)
+{
+  return __builtin_fmaf (a, -b, c);
+}
+
+double
+dbl_neg_mul_add_2 (double a, double b, double c)
+{
+  return __builtin_fma (a, -b, c);
+}
+
+float
+flt_neg_mul_sub (float a, float b, float c)
+{
+  return __builtin_fmaf (-a, b, -c);
+}
+
+double
+dbl_neg_mul_sub (double a, double b, double c)
+{
+  return __builtin_fma (-a, b, -c);
+}
+
+/* { dg-final { scan-assembler-times "vfmaddss" 1 } } */
+/* { dg-final { scan-assembler-times "vfmaddsd" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubss" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsubsd" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmaddss" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmaddsd" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsubss" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsubsd" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-check.h
new file mode 100644
index 000000000..33cd9628c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-check.h
@@ -0,0 +1,27 @@
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void fma4_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  fma4_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run FMA4 test only if host has FMA4 support.  */
+  if (ecx & bit_FMA4)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma-2.c
new file mode 100644
index 000000000..c15be1eda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma-2.c
@@ -0,0 +1,66 @@
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into vfmaddss, vfmsubss, vfnmaddss,
+   vfnmsubss on FMA4 systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -funsafe-math-optimizations -mfma4" } */
+
+extern void exit (int);
+
+float
+flt_mul_add (float a, float c)
+{
+  return (a * a) + c;
+}
+
+double
+dbl_mul_add (double a, double c)
+{
+  return (a * a) + c;
+}
+
+float
+flt_mul_sub (float a, float c)
+{
+  return (a * a) - c;
+}
+
+double
+dbl_mul_sub (double a, double c)
+{
+  return (a * a) - c;
+}
+
+float
+flt_neg_mul_add (float a, float c)
+{
+  return (-(a * a)) + c;
+}
+
+double
+dbl_neg_mul_add (double a, double c)
+{
+  return (-(a * a)) + c;
+}
+
+float  f[10] = { 2, 3, 4 };
+double d[10] = { 2, 3, 4 };
+
+int main ()
+{
+  f[3] = flt_mul_add (f[0], f[2]);
+  f[4] = flt_mul_sub (f[0], f[2]);
+  f[5] = flt_neg_mul_add (f[0], f[2]);
+
+  d[3] = dbl_mul_add (d[0], d[2]);
+  d[4] = dbl_mul_sub (d[0], d[2]);
+  d[5] = dbl_neg_mul_add (d[0], d[2]);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vfmaddss" } } */
+/* { dg-final { scan-assembler "vfmaddsd" } } */
+/* { dg-final { scan-assembler "vfmsubss" } } */
+/* { dg-final { scan-assembler "vfmsubsd" } } */
+/* { dg-final { scan-assembler "vfnmaddss" } } */
+/* { dg-final { scan-assembler "vfnmaddsd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma.c
new file mode 100644
index 000000000..63b35dc4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-fma.c
@@ -0,0 +1,82 @@
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into vfmaddss, vfmsubss, vfnmaddss,
+   vfnmsubss on FMA4 systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfma4" } */
+
+extern void exit (int);
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return (a * b) + c;
+}
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return (a * b) + c;
+}
+
+float
+flt_mul_sub (float a, float b, float c)
+{
+  return (a * b) - c;
+}
+
+double
+dbl_mul_sub (double a, double b, double c)
+{
+  return (a * b) - c;
+}
+
+float
+flt_neg_mul_add (float a, float b, float c)
+{
+  return (-(a * b)) + c;
+}
+
+double
+dbl_neg_mul_add (double a, double b, double c)
+{
+  return (-(a * b)) + c;
+}
+
+float
+flt_neg_mul_sub (float a, float b, float c)
+{
+  return (-(a * b)) - c;
+}
+
+double
+dbl_neg_mul_sub (double a, double b, double c)
+{
+  return (-(a * b)) - c;
+}
+
+float  f[10] = { 2, 3, 4 };
+double d[10] = { 2, 3, 4 };
+
+int main ()
+{
+  f[3] = flt_mul_add (f[0], f[1], f[2]);
+  f[4] = flt_mul_sub (f[0], f[1], f[2]);
+  f[5] = flt_neg_mul_add (f[0], f[1], f[2]);
+  f[6] = flt_neg_mul_sub (f[0], f[1], f[2]);
+
+  d[3] = dbl_mul_add (d[0], d[1], d[2]);
+  d[4] = dbl_mul_sub (d[0], d[1], d[2]);
+  d[5] = dbl_neg_mul_add (d[0], d[1], d[2]);
+  d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vfmaddss" } } */
+/* { dg-final { scan-assembler "vfmaddsd" } } */
+/* { dg-final { scan-assembler "vfmsubss" } } */
+/* { dg-final { scan-assembler "vfmsubsd" } } */
+/* { dg-final { scan-assembler "vfnmaddss" } } */
+/* { dg-final { scan-assembler "vfnmaddsd" } } */
+/* { dg-final { scan-assembler "vfnmsubss" } } */
+/* { dg-final { scan-assembler "vfnmsubsd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-maccXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-maccXX.c
new file mode 100644
index 000000000..4b4c00596
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-maccXX.c
@@ -0,0 +1,136 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma4 } */
+/* { dg-options "-O0 -mfma4" } */
+
+#include "fma4-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m128 x[NUM];
+  float f[NUM * 4];
+  __m128d y[NUM];
+  double d[NUM * 2];
+} dst, res, src1, src2, src3;
+
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_maccps ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_maccpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_maccps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_maccpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    for (j = 0; j < 2; j++)
+      {
+	res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+
+static int
+check_maccss ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i= i + 4)
+    {
+      res.f[i] = (src1.f[i] * src2.f[i]) + src3.f[i];
+      if (dst.f[i] != res.f[i]) 
+	check_fails++;
+    }	
+  return check_fails++;
+}
+
+static int
+check_maccsd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    {
+      res.d[i] = (src1.d[i] * src2.d[i]) + src3.d[i];
+      if (dst.d[i] != res.d[i]) 
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+fma4_test (void)
+{
+  int i;
+
+  init_maccps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_macc_ps (src1.x[i], src2.x[i], src3.x[i]);
+
+  if (check_maccps ()) 
+    abort ();
+
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_macc_ss (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_maccss ()) 
+    abort ();
+
+  init_maccpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_macc_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_maccpd ()) 
+    abort ();
+
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_macc_sd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_maccsd ()) 
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-msubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-msubXX.c
new file mode 100644
index 000000000..eed75580e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-msubXX.c
@@ -0,0 +1,134 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma4 } */
+/* { dg-options "-O0 -mfma4" } */
+
+#include "fma4-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m128 x[NUM];
+  float f[NUM * 4];
+  __m128d y[NUM];
+  double d[NUM * 2];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_msubps ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_msubpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_msubps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_msubpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    for (j = 0; j < 2; j++)
+      {
+	res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+
+static int
+check_msubss ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    {
+      res.f[i] = (src1.f[i] * src2.f[i]) - src3.f[i];
+      if (dst.f[i] != res.f[i]) 
+	check_fails++;
+    }	
+  return check_fails++;
+}
+
+static int
+check_msubsd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    {
+      res.d[i] = (src1.d[i] * src2.d[i]) - src3.d[i];
+      if (dst.d[i] != res.d[i]) 
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+fma4_test (void)
+{
+  int i;
+
+  init_msubps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_msub_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_msubps ()) 
+    abort ();
+
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_msub_ss (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_msubss ()) 
+    abort ();
+
+  init_msubpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_msub_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_msubpd ()) 
+    abort ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_msub_sd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_msubsd ()) 
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-nmaccXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-nmaccXX.c
new file mode 100644
index 000000000..9abf74604
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-nmaccXX.c
@@ -0,0 +1,137 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma4 } */
+/* { dg-options "-O0 -mfma4" } */
+
+#include "fma4-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m128 x[NUM];
+  float f[NUM * 4];
+  __m128d y[NUM];
+  double d[NUM * 2];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_nmaccps ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_nmaccpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_nmaccps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_nmaccpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    for (j = 0; j < 2; j++)
+      {
+	res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+
+static int
+check_nmaccss ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    {
+      res.f[i] = - (src1.f[i] * src2.f[i]) + src3.f[i];
+      if (dst.f[i] != res.f[i]) 
+	check_fails++;
+    }	
+  return check_fails++;
+}
+
+static int
+check_nmaccsd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    {
+      res.d[i] = - (src1.d[i] * src2.d[i]) + src3.d[i];
+      if (dst.d[i] != res.d[i]) 
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+fma4_test (void)
+{
+  int i;
+
+  init_nmaccps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_nmacc_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmaccps ()) 
+    abort ();
+  
+
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_nmacc_ss (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmaccss ()) 
+    abort ();
+
+  init_nmaccpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_nmacc_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmaccpd ()) 
+    abort ();
+  
+
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_nmacc_sd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmaccsd ()) 
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-nmsubXX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-nmsubXX.c
new file mode 100644
index 000000000..85fbecddb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-nmsubXX.c
@@ -0,0 +1,137 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma4 } */
+/* { dg-options "-O0 -mfma4" } */
+
+#include "fma4-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 20
+
+union
+{
+  __m128 x[NUM];
+  float f[NUM * 4];
+  __m128d y[NUM];
+  double d[NUM * 2];
+} dst, res, src1, src2, src3;
+
+/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate 
+   product is not rounded, only the addition is rounded. */
+
+static void
+init_nmsubps ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.f[i] = i;
+      src2.f[i] = i + 10;
+      src3.f[i] = i + 20;
+    }
+}
+
+static void
+init_nmsubpd ()
+{
+  int i;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1.d[i] = i;
+      src2.d[i] = i + 10;
+      src3.d[i] = i + 20;
+    }
+}
+
+static int
+check_nmsubps ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    for (j = 0; j < 4; j++)
+      {
+	res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j];
+	if (dst.f[i + j] != res.f[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+static int
+check_nmsubpd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    for (j = 0; j < 2; j++)
+      {
+	res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j];
+	if (dst.d[i + j] != res.d[i + j]) 
+	  check_fails++;
+      }
+  return check_fails++;
+}
+
+
+static int
+check_nmsubss ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 4; i = i + 4)
+    {
+      res.f[i] = - (src1.f[i] * src2.f[i]) - src3.f[i];
+      if (dst.f[i] != res.f[i]) 
+	check_fails++;
+    }	
+  return check_fails++;
+}
+
+static int
+check_nmsubsd ()
+{
+  int i, j, check_fails = 0;
+  for (i = 0; i < NUM * 2; i = i + 2)
+    {
+      res.d[i] = - (src1.d[i] * src2.d[i]) - src3.d[i];
+      if (dst.d[i] != res.d[i]) 
+	check_fails++;
+    }
+  return check_fails++;
+}
+
+static void
+fma4_test (void)
+{
+  int i;
+
+  init_nmsubps ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_nmsub_ps (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmsubps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4])) 
+    abort ();
+  
+
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_nmsub_ss (src1.x[i], src2.x[i], src3.x[i]);
+  
+  if (check_nmsubss (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4])) 
+    abort ();
+
+  init_nmsubpd ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_nmsub_pd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmsubpd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2])) 
+    abort ();
+  
+
+  for (i = 0; i < NUM; i++)
+    dst.y[i] = _mm_nmsub_sd (src1.y[i], src2.y[i], src3.y[i]);
+  
+  if (check_nmsubsd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2])) 
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector-2.c
new file mode 100644
index 000000000..d8b0d0813
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */
+
+float r[256], s[256];
+float x[256];
+float y[256];
+float z[256];
+
+void foo (void)
+{
+  int i;
+  for (i = 0; i < 256; ++i)
+    {
+      r[i] = x[i] * y[i] - z[i];
+      s[i] = x[i] * y[i] + z[i];
+    }
+}
+
+/* { dg-final { scan-assembler "vfmaddps" } } */
+/* { dg-final { scan-assembler "vfmsubps" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector.c
new file mode 100644
index 000000000..db5ffdd33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma4-vector.c
@@ -0,0 +1,92 @@
+/* Test that the compiler properly optimizes floating point multiply and add
+   instructions vector into vfmaddps on FMA4 systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfma4 -ftree-vectorize -mtune=generic" } */
+
+extern void exit (int);
+
+typedef float     __m128  __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef double    __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128 f_align;
+  __m128d d_align;
+  float f[SIZE];
+  double d[SIZE];
+} a, b, c, d;
+
+void
+flt_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (b.f[i] * c.f[i]) + d.f[i];
+}
+
+void
+dbl_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (b.d[i] * c.d[i]) + d.d[i];
+}
+
+void
+flt_mul_sub (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (b.f[i] * c.f[i]) - d.f[i];
+}
+
+void
+dbl_mul_sub (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (b.d[i] * c.d[i]) - d.d[i];
+}
+
+void
+flt_neg_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.f[i] = (-(b.f[i] * c.f[i])) + d.f[i];
+}
+
+void
+dbl_neg_mul_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.d[i] = (-(b.d[i] * c.d[i])) + d.d[i];
+}
+
+int main ()
+{
+  flt_mul_add ();
+  flt_mul_sub ();
+  flt_neg_mul_add ();
+
+  dbl_mul_add ();
+  dbl_mul_sub ();
+  dbl_neg_mul_add ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vfmaddps" } } */
+/* { dg-final { scan-assembler "vfmaddpd" } } */
+/* { dg-final { scan-assembler "vfmsubps" } } */
+/* { dg-final { scan-assembler "vfmsubpd" } } */
+/* { dg-final { scan-assembler "vfnmaddps" } } */
+/* { dg-final { scan-assembler "vfnmaddpd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_1.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_1.h
new file mode 100644
index 000000000..72d737394
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_1.h
@@ -0,0 +1,101 @@
+
+#ifndef fma_1
+#define fma_1
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * a + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * a - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * a + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * a - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * a + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * a - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * a + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * a - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * a + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * a - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * a + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * a - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * a + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * a - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * a + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * a - b;
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_2.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_2.h
new file mode 100644
index 000000000..c5d38d19a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_2.h
@@ -0,0 +1,101 @@
+
+#ifndef fma_2
+#define fma_2
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * a + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * a - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * a + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * a - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * a + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * a - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * a + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * a - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * a + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * a - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * a + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * a - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * a + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * a - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * a + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * a - c;
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_3.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_3.h
new file mode 100644
index 000000000..efa88b5d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_3.h
@@ -0,0 +1,101 @@
+
+#ifndef fma_3
+#define fma_3
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * b + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * b - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * b + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * b - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * b + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * b - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * b + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * b - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * b + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * b - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * b + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * b - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * b + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * b - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * b + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * b - a;
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_4.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_4.h
new file mode 100644
index 000000000..9fbb3efdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_4.h
@@ -0,0 +1,101 @@
+
+#ifndef fma_4
+#define fma_4
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * b + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * b - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * b + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * b - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * b + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * b - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * b + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * b - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * b + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * b - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * b + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * b - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * b + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * b - c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * b + c;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * b - c;
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_5.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_5.h
new file mode 100644
index 000000000..3409db8f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_5.h
@@ -0,0 +1,101 @@
+
+#ifndef fma_5
+#define fma_5
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * c + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * c - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * c + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * c - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * c + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * c - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * c + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * c - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * c + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * c - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * c + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * c - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * c + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * c - a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * c + a;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * c - a;
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_6.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_6.h
new file mode 100644
index 000000000..a6bb4b0cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_6.h
@@ -0,0 +1,101 @@
+
+#ifndef fma_6
+#define fma_6
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * c + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) + c) * c - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * c + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) + c) * c - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * c + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return ((a * b) - c) * c - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * c + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -((a * b) - c) * c - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * c + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) + c) * c - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * c + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) + c) * c - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * c + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return (-(a * b) - c) * c - b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * c + b;
+}
+
+TYPE __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE a, TYPE b, TYPE c)
+{
+  return -(-(a * b) - c) * c - b;
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_1.c
new file mode 100644
index 000000000..c3aa3e83c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_1.h"
+
+/* { dg-final { scan-assembler-times "vfmadd132sd" 4  } } */
+/* { dg-final { scan-assembler-times "vfmadd231sd" 4  } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 4  } } */
+/* { dg-final { scan-assembler-times "vfmsub231sd" 4  } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 4  } } */
+/* { dg-final { scan-assembler-times "vfnmadd231sd" 4  } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 4  } } */
+/* { dg-final { scan-assembler-times "vfnmsub231sd" 4  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_2.c
new file mode 100644
index 000000000..843eff0a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_2.h"
+
+/* { dg-final { scan-assembler-times "vfmadd132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_3.c
new file mode 100644
index 000000000..3a04777c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_3.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub\[132\]+sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[132\]+sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[132\]+sd" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_4.c
new file mode 100644
index 000000000..51fc111ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_4.h"
+
+/* { dg-final { scan-assembler-times "vfmadd132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_5.c
new file mode 100644
index 000000000..640b552b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_5.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[132\]+sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub\[132\]+sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[132\]+sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[132\]+sd" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_6.c
new file mode 100644
index 000000000..7b75a224f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_double_6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_6.h"
+
+/* { dg-final { scan-assembler-times "vfmadd132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_1.c
new file mode 100644
index 000000000..67b1f3fe7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_1.h"
+
+/* { dg-final { scan-assembler-times "vfmadd132ss" 4  } } */
+/* { dg-final { scan-assembler-times "vfmadd231ss" 4  } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 4  } } */
+/* { dg-final { scan-assembler-times "vfmsub231ss" 4  } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 4  } } */
+/* { dg-final { scan-assembler-times "vfnmadd231ss" 4  } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 4  } } */
+/* { dg-final { scan-assembler-times "vfnmsub231ss" 4  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_2.c
new file mode 100644
index 000000000..a54644d0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_2.h"
+
+/* { dg-final { scan-assembler-times "vfmadd132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_3.c
new file mode 100644
index 000000000..7986ce4ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_3.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[132\]+ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub\[132\]+ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[132\]+ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[132\]+ss" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_4.c
new file mode 100644
index 000000000..d9689d9a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_4.h"
+
+/* { dg-final { scan-assembler-times "vfmadd132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_5.c
new file mode 100644
index 000000000..2105ae627
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_5.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[132\]+ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub\[132\]+ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[132\]+ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[132\]+ss" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_6.c
new file mode 100644
index 000000000..c75807368
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_float_6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_6.h"
+
+/* { dg-final { scan-assembler-times "vfmadd132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 8  } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 8  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_main.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_main.h
new file mode 100644
index 000000000..24464ab50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_main.h
@@ -0,0 +1,117 @@
+
+#ifndef fma_main
+#define fma_main
+
+#if DEBUG
+#include <stdio.h>
+#endif
+
+TYPE m1[32] = {
+		1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16,
+	       17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32
+	      };
+TYPE m2[32] = {
+		2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 17,
+	       18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33
+	      };
+TYPE m3[32] = {
+		3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 
+	       19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
+	      };
+TYPE m4[32];
+int test_fails = 0;
+
+void
+compare_result(char * title, TYPE *res)
+{
+  int i;
+  int good = 1;
+  for (i =0; i < 32; i++)
+    if (m4[i] != res[i])
+      {
+        if (good)
+          {
+#if DEBUG
+             printf ("!!!! %s miscompare\n", title);
+#endif
+             good = 0;
+          }
+#if DEBUG
+        printf ("res[%d] = %d, must be %d\n", i, (int)res[i], (int) m4[i]);
+#endif
+      }
+  if (!good)
+    test_fails = 1;
+}
+
+static void fma_test ()
+{
+  int i;
+  for (i=0; i <32; i++)
+    m4[i] = test_noneg_add_noneg_add (m1[i], m2[i], m3[i]);
+  compare_result ("test0000", res_test0000);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_noneg_add_noneg_sub (m1[i], m2[i], m3[i]);
+  compare_result ("test0001", res_test0001);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_noneg_add_neg_add (m1[i], m2[i], m3[i]);
+  compare_result ("test0010", res_test0010);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_noneg_add_neg_sub (m1[i], m2[i], m3[i]);
+  compare_result ("test0011", res_test0011);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_noneg_sub_noneg_add (m1[i], m2[i], m3[i]);
+  compare_result ("test0100", res_test0100);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_noneg_sub_noneg_sub (m1[i], m2[i], m3[i]);
+  compare_result ("test0101", res_test0101);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_noneg_sub_neg_add (m1[i], m2[i], m3[i]);
+  compare_result ("test0110", res_test0110);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_noneg_sub_neg_sub (m1[i], m2[i], m3[i]);
+  compare_result ("test0111", res_test0111);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_neg_add_noneg_add (m1[i], m2[i], m3[i]);
+  compare_result ("test1000", res_test1000);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_neg_add_noneg_sub (m1[i], m2[i], m3[i]);
+  compare_result ("test1001", res_test1001);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_neg_add_neg_add (m1[i], m2[i], m3[i]);
+  compare_result ("test1010", res_test1010);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_neg_add_neg_sub (m1[i], m2[i], m3[i]);
+  compare_result ("test1011", res_test1011);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_neg_sub_noneg_add (m1[i], m2[i], m3[i]);
+  compare_result ("test1100", res_test1100);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_neg_sub_noneg_sub (m1[i], m2[i], m3[i]);
+  compare_result ("test1101", res_test1101);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_neg_sub_neg_add (m1[i], m2[i], m3[i]);
+  compare_result ("test1110", res_test1110);
+
+  for (i=0; i <32; i++)
+    m4[i] = test_neg_sub_neg_sub (m1[i], m2[i], m3[i]);
+  compare_result ("test1111", res_test1111);
+
+  if (test_fails) abort ();
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_1.c
new file mode 100644
index 000000000..a2f2aae9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_1.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_1.h"
+
+#include "fma_run_double_results_1.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_2.c
new file mode 100644
index 000000000..a389473a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_2.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_2.h"
+
+#include "fma_run_double_results_2.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_3.c
new file mode 100644
index 000000000..7b9d6273b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_3.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_3.h"
+
+#include "fma_run_double_results_3.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_4.c
new file mode 100644
index 000000000..1c0456dba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_4.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_4.h"
+
+#include "fma_run_double_results_4.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_5.c
new file mode 100644
index 000000000..6c09f0bb8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_5.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_5.h"
+
+#include "fma_run_double_results_5.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_6.c
new file mode 100644
index 000000000..32e51bf31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_6.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "fma_6.h"
+
+#include "fma_run_double_results_6.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h
new file mode 100644
index 000000000..27f325b86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_1.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_double_results_1
+#define fma_run_double_results_1
+
+TYPE res_test0000[32] = {
+  7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913
+};
+TYPE res_test0001[32] = {
+  3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847
+};
+TYPE res_test0010[32] = {
+  -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847
+};
+TYPE res_test0011[32] = {
+  -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913
+};
+TYPE res_test0100[32] = {
+  1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737
+};
+TYPE res_test0101[32] = {
+  -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671
+};
+TYPE res_test0110[32] = {
+  3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671
+};
+TYPE res_test0111[32] = {
+  -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737
+};
+TYPE res_test1000[32] = {
+  3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671
+};
+TYPE res_test1001[32] = {
+  -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737
+};
+TYPE res_test1010[32] = {
+  1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737
+};
+TYPE res_test1011[32] = {
+  -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671
+};
+TYPE res_test1100[32] = {
+  -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847
+};
+TYPE res_test1101[32] = {
+  -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913
+};
+TYPE res_test1110[32] = {
+  7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913
+};
+TYPE res_test1111[32] = {
+  3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h
new file mode 100644
index 000000000..f9327ce65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_2.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_double_results_2
+#define fma_run_double_results_2
+
+TYPE res_test0000[32] = {
+  8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914
+};
+TYPE res_test0001[32] = {
+  2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846
+};
+TYPE res_test0010[32] = {
+  -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846
+};
+TYPE res_test0011[32] = {
+  -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914
+};
+TYPE res_test0100[32] = {
+  2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738
+};
+TYPE res_test0101[32] = {
+  -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670
+};
+TYPE res_test0110[32] = {
+  4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670
+};
+TYPE res_test0111[32] = {
+  -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738
+};
+TYPE res_test1000[32] = {
+  4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670
+};
+TYPE res_test1001[32] = {
+  -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738
+};
+TYPE res_test1010[32] = {
+  2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738
+};
+TYPE res_test1011[32] = {
+  -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670
+};
+TYPE res_test1100[32] = {
+  -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846
+};
+TYPE res_test1101[32] = {
+  -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914
+};
+TYPE res_test1110[32] = {
+  8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914
+};
+TYPE res_test1111[32] = {
+  2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h
new file mode 100644
index 000000000..44cf82735
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_3.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_double_results_3
+#define fma_run_double_results_3
+
+TYPE res_test0000[32] = {
+  11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002
+};
+TYPE res_test0001[32] = {
+  9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938
+};
+TYPE res_test0010[32] = {
+  -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938
+};
+TYPE res_test0011[32] = {
+  -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002
+};
+TYPE res_test0100[32] = {
+  -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758
+};
+TYPE res_test0101[32] = {
+  -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694
+};
+TYPE res_test0110[32] = {
+  3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694
+};
+TYPE res_test0111[32] = {
+  1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758
+};
+TYPE res_test1000[32] = {
+  3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694
+};
+TYPE res_test1001[32] = {
+  1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758
+};
+TYPE res_test1010[32] = {
+  -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758
+};
+TYPE res_test1011[32] = {
+  -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694
+};
+TYPE res_test1100[32] = {
+  -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938
+};
+TYPE res_test1101[32] = {
+  -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002
+};
+TYPE res_test1110[32] = {
+  11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002
+};
+TYPE res_test1111[32] = {
+  9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h
new file mode 100644
index 000000000..0b7f85775
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_4.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_double_results_4
+#define fma_run_double_results_4
+
+TYPE res_test0000[32] = {
+  13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004
+};
+TYPE res_test0001[32] = {
+  7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936
+};
+TYPE res_test0010[32] = {
+  -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936
+};
+TYPE res_test0011[32] = {
+  -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004
+};
+TYPE res_test0100[32] = {
+  1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760
+};
+TYPE res_test0101[32] = {
+  -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692
+};
+TYPE res_test0110[32] = {
+  5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692
+};
+TYPE res_test0111[32] = {
+  -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760
+};
+TYPE res_test1000[32] = {
+  5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692
+};
+TYPE res_test1001[32] = {
+  -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760
+};
+TYPE res_test1010[32] = {
+  1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760
+};
+TYPE res_test1011[32] = {
+  -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692
+};
+TYPE res_test1100[32] = {
+  -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936
+};
+TYPE res_test1101[32] = {
+  -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004
+};
+TYPE res_test1110[32] = {
+  13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004
+};
+TYPE res_test1111[32] = {
+  7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h
new file mode 100644
index 000000000..0f96cad01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_5.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_double_results_5
+#define fma_run_double_results_5
+
+TYPE res_test0000[32] = {
+  16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092
+};
+TYPE res_test0001[32] = {
+  14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028
+};
+TYPE res_test0010[32] = {
+  -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028
+};
+TYPE res_test0011[32] = {
+  -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092
+};
+TYPE res_test0100[32] = {
+  -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780
+};
+TYPE res_test0101[32] = {
+  -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716
+};
+TYPE res_test0110[32] = {
+  4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716
+};
+TYPE res_test0111[32] = {
+  2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780
+};
+TYPE res_test1000[32] = {
+  4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716
+};
+TYPE res_test1001[32] = {
+  2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780
+};
+TYPE res_test1010[32] = {
+  -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780
+};
+TYPE res_test1011[32] = {
+  -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716
+};
+TYPE res_test1100[32] = {
+  -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028
+};
+TYPE res_test1101[32] = {
+  -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092
+};
+TYPE res_test1110[32] = {
+  16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092
+};
+TYPE res_test1111[32] = {
+  14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h
new file mode 100644
index 000000000..29ae9256c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_double_results_6.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_double_results_6
+#define fma_run_double_results_6
+
+TYPE res_test0000[32] = {
+  17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093
+};
+TYPE res_test0001[32] = {
+  13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027
+};
+TYPE res_test0010[32] = {
+  -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027
+};
+TYPE res_test0011[32] = {
+  -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093
+};
+TYPE res_test0100[32] = {
+  -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781
+};
+TYPE res_test0101[32] = {
+  -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715
+};
+TYPE res_test0110[32] = {
+  5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715
+};
+TYPE res_test0111[32] = {
+  1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781
+};
+TYPE res_test1000[32] = {
+  5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715
+};
+TYPE res_test1001[32] = {
+  1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781
+};
+TYPE res_test1010[32] = {
+  -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781
+};
+TYPE res_test1011[32] = {
+  -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715
+};
+TYPE res_test1100[32] = {
+  -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027
+};
+TYPE res_test1101[32] = {
+  -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093
+};
+TYPE res_test1110[32] = {
+  17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093
+};
+TYPE res_test1111[32] = {
+  13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_1.c
new file mode 100644
index 000000000..eccf60a88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_1.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_1.h"
+
+#include "fma_run_float_results_1.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_2.c
new file mode 100644
index 000000000..18177520a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_2.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_2.h"
+
+#include "fma_run_float_results_2.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_3.c
new file mode 100644
index 000000000..b206a0775
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_3.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_3.h"
+
+#include "fma_run_float_results_3.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_4.c
new file mode 100644
index 000000000..31c5a4dbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_4.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_4.h"
+
+#include "fma_run_float_results_4.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_5.c
new file mode 100644
index 000000000..615886ced
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_5.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_5.h"
+
+#include "fma_run_float_results_5.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_6.c
new file mode 100644
index 000000000..ca6cf5b1c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_6.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "fma_6.h"
+
+#include "fma_run_float_results_6.h"
+
+#include "fma-check.h"
+#include "fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h
new file mode 100644
index 000000000..65f52f2c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_1.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_float_results_1
+#define fma_run_float_results_1
+
+TYPE res_test0000[32] = {
+  7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913
+};
+TYPE res_test0001[32] = {
+  3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847
+};
+TYPE res_test0010[32] = {
+  -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847
+};
+TYPE res_test0011[32] = {
+  -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913
+};
+TYPE res_test0100[32] = {
+  1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737
+};
+TYPE res_test0101[32] = {
+  -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671
+};
+TYPE res_test0110[32] = {
+  3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671
+};
+TYPE res_test0111[32] = {
+  -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737
+};
+TYPE res_test1000[32] = {
+  3, -1, -17, -51, -109, -197, -321, -487, -701, -969, -1297, -1691, -2157, -2701, -3329, -4047, -4861, -5777, -6801, -7939, -9197, -10581, -12097, -13751, -15549, -17497, -19601, -21867, -24301, -26909, -29697, -32671
+};
+TYPE res_test1001[32] = {
+  -1, -7, -25, -61, -121, -211, -337, -505, -721, -991, -1321, -1717, -2185, -2731, -3361, -4081, -4897, -5815, -6841, -7981, -9241, -10627, -12145, -13801, -15601, -17551, -19657, -21925, -24361, -26971, -29761, -32737
+};
+TYPE res_test1010[32] = {
+  1, 7, 25, 61, 121, 211, 337, 505, 721, 991, 1321, 1717, 2185, 2731, 3361, 4081, 4897, 5815, 6841, 7981, 9241, 10627, 12145, 13801, 15601, 17551, 19657, 21925, 24361, 26971, 29761, 32737
+};
+TYPE res_test1011[32] = {
+  -3, 1, 17, 51, 109, 197, 321, 487, 701, 969, 1297, 1691, 2157, 2701, 3329, 4047, 4861, 5777, 6801, 7939, 9197, 10581, 12097, 13751, 15549, 17497, 19601, 21867, 24301, 26909, 29697, 32671
+};
+TYPE res_test1100[32] = {
+  -3, -17, -47, -99, -179, -293, -447, -647, -899, -1209, -1583, -2027, -2547, -3149, -3839, -4623, -5507, -6497, -7599, -8819, -10163, -11637, -13247, -14999, -16899, -18953, -21167, -23547, -26099, -28829, -31743, -34847
+};
+TYPE res_test1101[32] = {
+  -7, -23, -55, -109, -191, -307, -463, -665, -919, -1231, -1607, -2053, -2575, -3179, -3871, -4657, -5543, -6535, -7639, -8861, -10207, -11683, -13295, -15049, -16951, -19007, -21223, -23605, -26159, -28891, -31807, -34913
+};
+TYPE res_test1110[32] = {
+  7, 23, 55, 109, 191, 307, 463, 665, 919, 1231, 1607, 2053, 2575, 3179, 3871, 4657, 5543, 6535, 7639, 8861, 10207, 11683, 13295, 15049, 16951, 19007, 21223, 23605, 26159, 28891, 31807, 34913
+};
+TYPE res_test1111[32] = {
+  3, 17, 47, 99, 179, 293, 447, 647, 899, 1209, 1583, 2027, 2547, 3149, 3839, 4623, 5507, 6497, 7599, 8819, 10163, 11637, 13247, 14999, 16899, 18953, 21167, 23547, 26099, 28829, 31743, 34847
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h
new file mode 100644
index 000000000..d215efd58
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_2.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_float_results_2
+#define fma_run_float_results_2
+
+TYPE res_test0000[32] = {
+  8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914
+};
+TYPE res_test0001[32] = {
+  2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846
+};
+TYPE res_test0010[32] = {
+  -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846
+};
+TYPE res_test0011[32] = {
+  -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914
+};
+TYPE res_test0100[32] = {
+  2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738
+};
+TYPE res_test0101[32] = {
+  -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670
+};
+TYPE res_test0110[32] = {
+  4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670
+};
+TYPE res_test0111[32] = {
+  -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738
+};
+TYPE res_test1000[32] = {
+  4, 0, -16, -50, -108, -196, -320, -486, -700, -968, -1296, -1690, -2156, -2700, -3328, -4046, -4860, -5776, -6800, -7938, -9196, -10580, -12096, -13750, -15548, -17496, -19600, -21866, -24300, -26908, -29696, -32670
+};
+TYPE res_test1001[32] = {
+  -2, -8, -26, -62, -122, -212, -338, -506, -722, -992, -1322, -1718, -2186, -2732, -3362, -4082, -4898, -5816, -6842, -7982, -9242, -10628, -12146, -13802, -15602, -17552, -19658, -21926, -24362, -26972, -29762, -32738
+};
+TYPE res_test1010[32] = {
+  2, 8, 26, 62, 122, 212, 338, 506, 722, 992, 1322, 1718, 2186, 2732, 3362, 4082, 4898, 5816, 6842, 7982, 9242, 10628, 12146, 13802, 15602, 17552, 19658, 21926, 24362, 26972, 29762, 32738
+};
+TYPE res_test1011[32] = {
+  -4, 0, 16, 50, 108, 196, 320, 486, 700, 968, 1296, 1690, 2156, 2700, 3328, 4046, 4860, 5776, 6800, 7938, 9196, 10580, 12096, 13750, 15548, 17496, 19600, 21866, 24300, 26908, 29696, 32670
+};
+TYPE res_test1100[32] = {
+  -2, -16, -46, -98, -178, -292, -446, -646, -898, -1208, -1582, -2026, -2546, -3148, -3838, -4622, -5506, -6496, -7598, -8818, -10162, -11636, -13246, -14998, -16898, -18952, -21166, -23546, -26098, -28828, -31742, -34846
+};
+TYPE res_test1101[32] = {
+  -8, -24, -56, -110, -192, -308, -464, -666, -920, -1232, -1608, -2054, -2576, -3180, -3872, -4658, -5544, -6536, -7640, -8862, -10208, -11684, -13296, -15050, -16952, -19008, -21224, -23606, -26160, -28892, -31808, -34914
+};
+TYPE res_test1110[32] = {
+  8, 24, 56, 110, 192, 308, 464, 666, 920, 1232, 1608, 2054, 2576, 3180, 3872, 4658, 5544, 6536, 7640, 8862, 10208, 11684, 13296, 15050, 16952, 19008, 21224, 23606, 26160, 28892, 31808, 34914
+};
+TYPE res_test1111[32] = {
+  2, 16, 46, 98, 178, 292, 446, 646, 898, 1208, 1582, 2026, 2546, 3148, 3838, 4622, 5506, 6496, 7598, 8818, 10162, 11636, 13246, 14998, 16898, 18952, 21166, 23546, 26098, 28828, 31742, 34846
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h
new file mode 100644
index 000000000..11751f131
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_3.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_float_results_3
+#define fma_run_float_results_3
+
+TYPE res_test0000[32] = {
+  11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002
+};
+TYPE res_test0001[32] = {
+  9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938
+};
+TYPE res_test0010[32] = {
+  -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938
+};
+TYPE res_test0011[32] = {
+  -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002
+};
+TYPE res_test0100[32] = {
+  -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758
+};
+TYPE res_test0101[32] = {
+  -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694
+};
+TYPE res_test0110[32] = {
+  3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694
+};
+TYPE res_test0111[32] = {
+  1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758
+};
+TYPE res_test1000[32] = {
+  3, -4, -25, -66, -133, -232, -369, -550, -781, -1068, -1417, -1834, -2325, -2896, -3553, -4302, -5149, -6100, -7161, -8338, -9637, -11064, -12625, -14326, -16173, -18172, -20329, -22650, -25141, -27808, -30657, -33694
+};
+TYPE res_test1001[32] = {
+  1, -8, -31, -74, -143, -244, -383, -566, -799, -1088, -1439, -1858, -2351, -2924, -3583, -4334, -5183, -6136, -7199, -8378, -9679, -11108, -12671, -14374, -16223, -18224, -20383, -22706, -25199, -27868, -30719, -33758
+};
+TYPE res_test1010[32] = {
+  -1, 8, 31, 74, 143, 244, 383, 566, 799, 1088, 1439, 1858, 2351, 2924, 3583, 4334, 5183, 6136, 7199, 8378, 9679, 11108, 12671, 14374, 16223, 18224, 20383, 22706, 25199, 27868, 30719, 33758
+};
+TYPE res_test1011[32] = {
+  -3, 4, 25, 66, 133, 232, 369, 550, 781, 1068, 1417, 1834, 2325, 2896, 3553, 4302, 5149, 6100, 7161, 8338, 9637, 11064, 12625, 14326, 16173, 18172, 20329, 22650, 25141, 27808, 30657, 33694
+};
+TYPE res_test1100[32] = {
+  -9, -28, -65, -126, -217, -344, -513, -730, -1001, -1332, -1729, -2198, -2745, -3376, -4097, -4914, -5833, -6860, -8001, -9262, -10649, -12168, -13825, -15626, -17577, -19684, -21953, -24390, -27001, -29792, -32769, -35938
+};
+TYPE res_test1101[32] = {
+  -11, -32, -71, -134, -227, -356, -527, -746, -1019, -1352, -1751, -2222, -2771, -3404, -4127, -4946, -5867, -6896, -8039, -9302, -10691, -12212, -13871, -15674, -17627, -19736, -22007, -24446, -27059, -29852, -32831, -36002
+};
+TYPE res_test1110[32] = {
+  11, 32, 71, 134, 227, 356, 527, 746, 1019, 1352, 1751, 2222, 2771, 3404, 4127, 4946, 5867, 6896, 8039, 9302, 10691, 12212, 13871, 15674, 17627, 19736, 22007, 24446, 27059, 29852, 32831, 36002
+};
+TYPE res_test1111[32] = {
+  9, 28, 65, 126, 217, 344, 513, 730, 1001, 1332, 1729, 2198, 2745, 3376, 4097, 4914, 5833, 6860, 8001, 9262, 10649, 12168, 13825, 15626, 17577, 19684, 21953, 24390, 27001, 29792, 32769, 35938
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h
new file mode 100644
index 000000000..13906dbdd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_4.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_float_results_4
+#define fma_run_float_results_4
+
+TYPE res_test0000[32] = {
+  13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004
+};
+TYPE res_test0001[32] = {
+  7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936
+};
+TYPE res_test0010[32] = {
+  -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936
+};
+TYPE res_test0011[32] = {
+  -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004
+};
+TYPE res_test0100[32] = {
+  1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760
+};
+TYPE res_test0101[32] = {
+  -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692
+};
+TYPE res_test0110[32] = {
+  5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692
+};
+TYPE res_test0111[32] = {
+  -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760
+};
+TYPE res_test1000[32] = {
+  5, -2, -23, -64, -131, -230, -367, -548, -779, -1066, -1415, -1832, -2323, -2894, -3551, -4300, -5147, -6098, -7159, -8336, -9635, -11062, -12623, -14324, -16171, -18170, -20327, -22648, -25139, -27806, -30655, -33692
+};
+TYPE res_test1001[32] = {
+  -1, -10, -33, -76, -145, -246, -385, -568, -801, -1090, -1441, -1860, -2353, -2926, -3585, -4336, -5185, -6138, -7201, -8380, -9681, -11110, -12673, -14376, -16225, -18226, -20385, -22708, -25201, -27870, -30721, -33760
+};
+TYPE res_test1010[32] = {
+  1, 10, 33, 76, 145, 246, 385, 568, 801, 1090, 1441, 1860, 2353, 2926, 3585, 4336, 5185, 6138, 7201, 8380, 9681, 11110, 12673, 14376, 16225, 18226, 20385, 22708, 25201, 27870, 30721, 33760
+};
+TYPE res_test1011[32] = {
+  -5, 2, 23, 64, 131, 230, 367, 548, 779, 1066, 1415, 1832, 2323, 2894, 3551, 4300, 5147, 6098, 7159, 8336, 9635, 11062, 12623, 14324, 16171, 18170, 20327, 22648, 25139, 27806, 30655, 33692
+};
+TYPE res_test1100[32] = {
+  -7, -26, -63, -124, -215, -342, -511, -728, -999, -1330, -1727, -2196, -2743, -3374, -4095, -4912, -5831, -6858, -7999, -9260, -10647, -12166, -13823, -15624, -17575, -19682, -21951, -24388, -26999, -29790, -32767, -35936
+};
+TYPE res_test1101[32] = {
+  -13, -34, -73, -136, -229, -358, -529, -748, -1021, -1354, -1753, -2224, -2773, -3406, -4129, -4948, -5869, -6898, -8041, -9304, -10693, -12214, -13873, -15676, -17629, -19738, -22009, -24448, -27061, -29854, -32833, -36004
+};
+TYPE res_test1110[32] = {
+  13, 34, 73, 136, 229, 358, 529, 748, 1021, 1354, 1753, 2224, 2773, 3406, 4129, 4948, 5869, 6898, 8041, 9304, 10693, 12214, 13873, 15676, 17629, 19738, 22009, 24448, 27061, 29854, 32833, 36004
+};
+TYPE res_test1111[32] = {
+  7, 26, 63, 124, 215, 342, 511, 728, 999, 1330, 1727, 2196, 2743, 3374, 4095, 4912, 5831, 6858, 7999, 9260, 10647, 12166, 13823, 15624, 17575, 19682, 21951, 24388, 26999, 29790, 32767, 35936
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h
new file mode 100644
index 000000000..f156bef6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_5.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_float_results_5
+#define fma_run_float_results_5
+
+TYPE res_test0000[32] = {
+  16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092
+};
+TYPE res_test0001[32] = {
+  14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028
+};
+TYPE res_test0010[32] = {
+  -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028
+};
+TYPE res_test0011[32] = {
+  -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092
+};
+TYPE res_test0100[32] = {
+  -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780
+};
+TYPE res_test0101[32] = {
+  -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716
+};
+TYPE res_test0110[32] = {
+  4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716
+};
+TYPE res_test0111[32] = {
+  2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780
+};
+TYPE res_test1000[32] = {
+  4, -6, -32, -80, -156, -266, -416, -612, -860, -1166, -1536, -1976, -2492, -3090, -3776, -4556, -5436, -6422, -7520, -8736, -10076, -11546, -13152, -14900, -16796, -18846, -21056, -23432, -25980, -28706, -31616, -34716
+};
+TYPE res_test1001[32] = {
+  2, -10, -38, -88, -166, -278, -430, -628, -878, -1186, -1558, -2000, -2518, -3118, -3806, -4588, -5470, -6458, -7558, -8776, -10118, -11590, -13198, -14948, -16846, -18898, -21110, -23488, -26038, -28766, -31678, -34780
+};
+TYPE res_test1010[32] = {
+  -2, 10, 38, 88, 166, 278, 430, 628, 878, 1186, 1558, 2000, 2518, 3118, 3806, 4588, 5470, 6458, 7558, 8776, 10118, 11590, 13198, 14948, 16846, 18898, 21110, 23488, 26038, 28766, 31678, 34780
+};
+TYPE res_test1011[32] = {
+  -4, 6, 32, 80, 156, 266, 416, 612, 860, 1166, 1536, 1976, 2492, 3090, 3776, 4556, 5436, 6422, 7520, 8736, 10076, 11546, 13152, 14900, 16796, 18846, 21056, 23432, 25980, 28706, 31616, 34716
+};
+TYPE res_test1100[32] = {
+  -14, -38, -82, -152, -254, -394, -578, -812, -1102, -1454, -1874, -2368, -2942, -3602, -4354, -5204, -6158, -7222, -8402, -9704, -11134, -12698, -14402, -16252, -18254, -20414, -22738, -25232, -27902, -30754, -33794, -37028
+};
+TYPE res_test1101[32] = {
+  -16, -42, -88, -160, -264, -406, -592, -828, -1120, -1474, -1896, -2392, -2968, -3630, -4384, -5236, -6192, -7258, -8440, -9744, -11176, -12742, -14448, -16300, -18304, -20466, -22792, -25288, -27960, -30814, -33856, -37092
+};
+TYPE res_test1110[32] = {
+  16, 42, 88, 160, 264, 406, 592, 828, 1120, 1474, 1896, 2392, 2968, 3630, 4384, 5236, 6192, 7258, 8440, 9744, 11176, 12742, 14448, 16300, 18304, 20466, 22792, 25288, 27960, 30814, 33856, 37092
+};
+TYPE res_test1111[32] = {
+  14, 38, 82, 152, 254, 394, 578, 812, 1102, 1454, 1874, 2368, 2942, 3602, 4354, 5204, 6158, 7222, 8402, 9704, 11134, 12698, 14402, 16252, 18254, 20414, 22738, 25232, 27902, 30754, 33794, 37028
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h
new file mode 100644
index 000000000..d2c2e1f97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fma_run_float_results_6.h
@@ -0,0 +1,54 @@
+
+#ifndef fma_run_float_results_6
+#define fma_run_float_results_6
+
+TYPE res_test0000[32] = {
+  17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093
+};
+TYPE res_test0001[32] = {
+  13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027
+};
+TYPE res_test0010[32] = {
+  -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027
+};
+TYPE res_test0011[32] = {
+  -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093
+};
+TYPE res_test0100[32] = {
+  -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781
+};
+TYPE res_test0101[32] = {
+  -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715
+};
+TYPE res_test0110[32] = {
+  5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715
+};
+TYPE res_test0111[32] = {
+  1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781
+};
+TYPE res_test1000[32] = {
+  5, -5, -31, -79, -155, -265, -415, -611, -859, -1165, -1535, -1975, -2491, -3089, -3775, -4555, -5435, -6421, -7519, -8735, -10075, -11545, -13151, -14899, -16795, -18845, -21055, -23431, -25979, -28705, -31615, -34715
+};
+TYPE res_test1001[32] = {
+  1, -11, -39, -89, -167, -279, -431, -629, -879, -1187, -1559, -2001, -2519, -3119, -3807, -4589, -5471, -6459, -7559, -8777, -10119, -11591, -13199, -14949, -16847, -18899, -21111, -23489, -26039, -28767, -31679, -34781
+};
+TYPE res_test1010[32] = {
+  -1, 11, 39, 89, 167, 279, 431, 629, 879, 1187, 1559, 2001, 2519, 3119, 3807, 4589, 5471, 6459, 7559, 8777, 10119, 11591, 13199, 14949, 16847, 18899, 21111, 23489, 26039, 28767, 31679, 34781
+};
+TYPE res_test1011[32] = {
+  -5, 5, 31, 79, 155, 265, 415, 611, 859, 1165, 1535, 1975, 2491, 3089, 3775, 4555, 5435, 6421, 7519, 8735, 10075, 11545, 13151, 14899, 16795, 18845, 21055, 23431, 25979, 28705, 31615, 34715
+};
+TYPE res_test1100[32] = {
+  -13, -37, -81, -151, -253, -393, -577, -811, -1101, -1453, -1873, -2367, -2941, -3601, -4353, -5203, -6157, -7221, -8401, -9703, -11133, -12697, -14401, -16251, -18253, -20413, -22737, -25231, -27901, -30753, -33793, -37027
+};
+TYPE res_test1101[32] = {
+  -17, -43, -89, -161, -265, -407, -593, -829, -1121, -1475, -1897, -2393, -2969, -3631, -4385, -5237, -6193, -7259, -8441, -9745, -11177, -12743, -14449, -16301, -18305, -20467, -22793, -25289, -27961, -30815, -33857, -37093
+};
+TYPE res_test1110[32] = {
+  17, 43, 89, 161, 265, 407, 593, 829, 1121, 1475, 1897, 2393, 2969, 3631, 4385, 5237, 6193, 7259, 8441, 9745, 11177, 12743, 14449, 16301, 18305, 20467, 22793, 25289, 27961, 30815, 33857, 37093
+};
+TYPE res_test1111[32] = {
+  13, 37, 81, 151, 253, 393, 577, 811, 1101, 1453, 1873, 2367, 2941, 3601, 4353, 5203, 6157, 7221, 8401, 9703, 11133, 12697, 14401, 16251, 18253, 20413, 22737, 25231, 27901, 30753, 33793, 37027
+};
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-1.c
new file mode 100644
index 000000000..1c3b9b834
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler-not "cvtss2sd" } } */
+float a,b;
+main()
+{
+  a=b*3.0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-2.c
new file mode 100644
index 000000000..066d84365
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler-not "cvtss2sd" } } */
+float a,b;
+main()
+{
+	return a<0.0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-3.c
new file mode 100644
index 000000000..569d21a5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler-not "cvtss2sd" } } */
+extern double fabs (double);
+float a,b;
+main()
+{
+	a=fabs(b)+1.0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-4.c
new file mode 100644
index 000000000..8257f6520
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpcvt-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mfpmath=sse" } */
+/* { dg-final { scan-assembler "cvtsi2sd" } } */
+/* Check that conversions will get folded.  */
+double
+t(short a)
+{
+  float b=a;
+  return b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fpprec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpprec-1.c
new file mode 100644
index 000000000..1c17c1d10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fpprec-1.c
@@ -0,0 +1,80 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-math-errno -fno-trapping-math -msse2 -mfpmath=sse" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+double x[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+	-0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,  /* +-DBL_MAX */
+	-0x1p-52, 0x1p-52,				    /* +-DBL_EPSILON */
+	/* nextafter/before 0.5, 1.0 and 1.5 */
+	0x1.0000000000001p-1, 0x1.fffffffffffffp-2,
+	0x1.0000000000001p+0, 0x1.fffffffffffffp-1,
+	0x1.8000000000001p+0, 0x1.7ffffffffffffp+0,
+	-0.0, 0.0, -0.5, 0.5, -1.0, 1.0, -1.5, 1.5, -2.0, 2.0,
+	-2.5, 2.5 };
+#define NUM (sizeof(x)/sizeof(double))
+
+double expect_round[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+	-0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+	-0.0, 0.0,
+	1.0, 0.0, 1.0, 1.0, 2.0, 1.0,
+	-0.0, 0.0, -1.0, 1.0, -1.0, 1.0, -2.0, 2.0, -2.0, 2.0,
+	-3.0, 3.0 };
+
+double expect_rint[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+        -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+        -0.0, 0.0,
+        1.0, 0.0, 1.0, 1.0, 2.0, 1.0,
+        -0.0, 0.0, -0.0, 0.0, -1.0, 1.0, -2.0, 2.0, -2.0, 2.0,
+        -2.0, 2.0 };
+
+double expect_floor[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+        -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+        -1.0, 0.0,
+        0.0, 0.0, 1.0, 0.0, 1.0, 1.0,
+        -0.0, 0.0, -1.0, 0.0, -1.0, 1.0, -2.0, 1.0, -2.0, 2.0,
+        -3.0, 2.0 };
+
+double expect_ceil[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+        -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+        -0.0, 1.0,
+        1.0, 1.0, 2.0, 1.0, 2.0, 2.0,
+        -0.0, 0.0, -0.0, 1.0, -1.0, 1.0, -1.0, 2.0, -2.0, 2.0,
+        -2.0, 3.0 };
+
+double expect_trunc[] = { __builtin_nan(""), __builtin_inf(), -__builtin_inf(),
+        -0x1.fffffffffffffp+1023, 0x1.fffffffffffffp+1023,
+        -0.0, 0.0,
+        0.0, 0.0, 1.0, 0.0, 1.0, 1.0,
+        -0.0, 0.0, -0.0, 0.0, -1.0, 1.0, -1.0, 1.0, -2.0, 2.0,
+        -2.0, 2.0 };
+
+
+#define CHECK(fn) \
+void check_ ## fn (void) \
+{ \
+  int i; \
+  for (i = 0; i < NUM; ++i) \
+    { \
+      double res = __builtin_ ## fn (x[i]); \
+      if (__builtin_memcmp (&res, &expect_ ## fn [i], sizeof(double)) != 0) \
+        printf( # fn " [%i]: %.18e %.18e\n", i, expect_ ## fn [i], res), abort (); \
+    } \
+}
+
+CHECK(round)
+CHECK(rint)
+CHECK(floor)
+CHECK(ceil)
+CHECK(trunc)
+
+static void
+sse2_test (void)
+{
+  check_round ();
+  check_rint ();
+  check_floor ();
+  check_ceil ();
+  check_trunc ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-1.c
new file mode 100644
index 000000000..742e3a19e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-1.c
@@ -0,0 +1,35 @@
+/* Test whether using target specific options, we can generate SSE2 code on
+   32-bit, which does not generate SSE2 by default, but still generate 387 code
+   for a function that doesn't use attribute((option)).  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O3 -ftree-vectorize -mno-sse" } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+float a[SIZE] __attribute__((__aligned__(16)));
+float b[SIZE] __attribute__((__aligned__(16)));
+float c[SIZE] __attribute__((__aligned__(16)));
+
+void sse_addnums (void) __attribute__ ((__target__ ("sse2")));
+
+void
+sse_addnums (void)
+{
+  int i = 0;
+  for (; i < SIZE; ++i)
+    a[i] = b[i] + c[i];
+}
+
+void
+i387_subnums (void)
+{
+  int i = 0;
+  for (; i < SIZE; ++i)
+    a[i] = b[i] - c[i];
+}
+
+/* { dg-final { scan-assembler "addps\[ \t\]" } } */
+/* { dg-final { scan-assembler "fsubs\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-10.c
new file mode 100644
index 000000000..de39ff00e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-10.c
@@ -0,0 +1,15 @@
+/* PR target/36936 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=i686" } */
+/* { dg-final { scan-assembler-not "cmov" } } */
+
+extern int foo (int) __attribute__((__target__("arch=i386")));
+
+int
+foo (int x)
+{
+  if (x < 0)
+    x = 1;
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-11.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-11.c
new file mode 100644
index 000000000..7c39f4cd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-11.c
@@ -0,0 +1,15 @@
+/* PR target/36936 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=i386" } */
+/* { dg-final { scan-assembler "cmov" } } */
+
+extern int foo (int) __attribute__((__target__("arch=i686")));
+
+int
+foo (int x)
+{
+  if (x < 0)
+    x = 1;
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-2.c
new file mode 100644
index 000000000..88c14b29b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-2.c
@@ -0,0 +1,98 @@
+/* Test whether using target specific options, we can generate FMA4 code.  */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -march=k8" } */
+
+extern void exit (int);
+
+#define FMA4_ATTR __attribute__((__target__("fma4")))
+extern float  flt_mul_add     (float a, float b, float c) FMA4_ATTR;
+extern float  flt_mul_sub     (float a, float b, float c) FMA4_ATTR;
+extern float  flt_neg_mul_add (float a, float b, float c) FMA4_ATTR;
+extern float  flt_neg_mul_sub (float a, float b, float c) FMA4_ATTR;
+
+extern double dbl_mul_add     (double a, double b, double c) FMA4_ATTR;
+extern double dbl_mul_sub     (double a, double b, double c) FMA4_ATTR;
+extern double dbl_neg_mul_add (double a, double b, double c) FMA4_ATTR;
+extern double dbl_neg_mul_sub (double a, double b, double c) FMA4_ATTR;
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return (a * b) + c;
+}
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return (a * b) + c;
+}
+
+float
+flt_mul_sub (float a, float b, float c)
+{
+  return (a * b) - c;
+}
+
+double
+dbl_mul_sub (double a, double b, double c)
+{
+  return (a * b) - c;
+}
+
+float
+flt_neg_mul_add (float a, float b, float c)
+{
+  return (-(a * b)) + c;
+}
+
+double
+dbl_neg_mul_add (double a, double b, double c)
+{
+  return (-(a * b)) + c;
+}
+
+float
+flt_neg_mul_sub (float a, float b, float c)
+{
+  return (-(a * b)) - c;
+}
+
+double
+dbl_neg_mul_sub (double a, double b, double c)
+{
+  return (-(a * b)) - c;
+}
+
+float  f[10] = { 2, 3, 4 };
+double d[10] = { 2, 3, 4 };
+
+int main ()
+{
+  f[3] = flt_mul_add (f[0], f[1], f[2]);
+  f[4] = flt_mul_sub (f[0], f[1], f[2]);
+  f[5] = flt_neg_mul_add (f[0], f[1], f[2]);
+  f[6] = flt_neg_mul_sub (f[0], f[1], f[2]);
+
+  d[3] = dbl_mul_add (d[0], d[1], d[2]);
+  d[4] = dbl_mul_sub (d[0], d[1], d[2]);
+  d[5] = dbl_neg_mul_add (d[0], d[1], d[2]);
+  d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vfmaddss" } } */
+/* { dg-final { scan-assembler "vfmaddsd" } } */
+/* { dg-final { scan-assembler "vfmsubss" } } */
+/* { dg-final { scan-assembler "vfmsubsd" } } */
+/* { dg-final { scan-assembler "vfnmaddss" } } */
+/* { dg-final { scan-assembler "vfnmaddsd" } } */
+/* { dg-final { scan-assembler "vfnmsubss" } } */
+/* { dg-final { scan-assembler "vfnmsubsd" } } */
+/* { dg-final { scan-assembler "call\t(.*)flt_mul_add" } } */
+/* { dg-final { scan-assembler "call\t(.*)flt_mul_sub" } } */
+/* { dg-final { scan-assembler "call\t(.*)flt_neg_mul_add" } } */
+/* { dg-final { scan-assembler "call\t(.*)flt_neg_mul_sub" } } */
+/* { dg-final { scan-assembler "call\t(.*)dbl_mul_add" } } */
+/* { dg-final { scan-assembler "call\t(.*)dbl_mul_sub" } } */
+/* { dg-final { scan-assembler "call\t(.*)dbl_neg_mul_add" } } */
+/* { dg-final { scan-assembler "call\t(.*)dbl_neg_mul_sub" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-3.c
new file mode 100644
index 000000000..f3f4db76a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-3.c
@@ -0,0 +1,67 @@
+/* Test whether using target specific options, we can generate popcnt by
+   setting the architecture.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -march=k8 -mno-sse3" } */
+
+extern void exit (int);
+extern void abort (void);
+
+#define SSE4A_ATTR __attribute__((__target__("arch=amdfam10")))
+#define SSE42_ATTR __attribute__((__target__("sse4.2")))
+
+static int sse4a_pop_i (int a) SSE4A_ATTR;
+static long sse42_pop_l (long a) SSE42_ATTR;
+static int generic_pop_i (int a);
+static long generic_pop_l (long a);
+
+static
+int sse4a_pop_i (int a)
+{
+  return __builtin_popcount (a);
+}
+
+static
+long sse42_pop_l (long a)
+{
+  return __builtin_popcountl (a);
+}
+
+static
+int generic_pop_i (int a)
+{
+  return __builtin_popcount (a);
+}
+
+static
+long generic_pop_l (long a)
+{
+  return __builtin_popcountl (a);
+}
+
+int five = 5;
+long seven = 7;
+
+int main ()
+{
+  if (sse4a_pop_i (five) != 2)
+    abort ();
+
+  if (sse42_pop_l (seven) != 3L)
+    abort ();
+
+  if (generic_pop_i (five) != 2)
+    abort ();
+
+  if (generic_pop_l (seven) != 3L)
+    abort ();
+
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "popcntl" { target { ! *-*-darwin* } } } } */
+/* { dg-final { scan-assembler "popcntq" { target { ! *-*-darwin* } } } } */
+/* { dg-final { scan-assembler-times "popcnt" 2 { target *-*-darwin* } } } */
+/* { dg-final { scan-assembler "call\t(.*)sse4a_pop_i" } } */
+/* { dg-final { scan-assembler "call\t(.*)sse42_pop_l" } } */
+/* { dg-final { scan-assembler "call\t(.*)popcountdi2" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-4.c
new file mode 100644
index 000000000..025b97dff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-4.c
@@ -0,0 +1,14 @@
+/* Test some error conditions with function specific options.  */
+/* { dg-do compile } */
+
+/* no fma400 switch */
+extern void error1 (void) __attribute__((__target__("fma400"))); /* { dg-error "unknown" } */
+
+/* Multiple arch switches */
+extern void error2 (void) __attribute__((__target__("arch=core2,arch=k8"))); /* { dg-error "already specified" } */
+
+/* Unknown tune target */
+extern void error3 (void) __attribute__((__target__("tune=foobar"))); /* { dg-error "bad value" } */
+
+/* option on a variable */
+extern int error4 __attribute__((__target__("sse2"))); /* { dg-warning "ignored" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-5.c
new file mode 100644
index 000000000..0acfe000d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-5.c
@@ -0,0 +1,147 @@
+/* Test whether all of the 32-bit function specific options are accepted
+   without error.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+
+extern void test_abm (void)			__attribute__((__target__("abm")));
+extern void test_aes (void)			__attribute__((__target__("aes")));
+extern void test_bmi (void)			__attribute__((__target__("bmi")));
+extern void test_mmx (void)			__attribute__((__target__("mmx")));
+extern void test_pclmul (void)			__attribute__((__target__("pclmul")));
+extern void test_popcnt (void)			__attribute__((__target__("popcnt")));
+extern void test_recip (void)			__attribute__((__target__("recip")));
+extern void test_sse (void)			__attribute__((__target__("sse")));
+extern void test_sse2 (void)			__attribute__((__target__("sse2")));
+extern void test_sse3 (void)			__attribute__((__target__("sse3")));
+extern void test_sse4 (void)			__attribute__((__target__("sse4")));
+extern void test_sse4_1 (void)			__attribute__((__target__("sse4.1")));
+extern void test_sse4_2 (void)			__attribute__((__target__("sse4.2")));
+extern void test_sse4a (void)			__attribute__((__target__("sse4a")));
+extern void test_fma (void)			__attribute__((__target__("fma")));
+extern void test_fma4 (void)			__attribute__((__target__("fma4")));
+extern void test_xop (void)			__attribute__((__target__("xop")));
+extern void test_ssse3 (void)			__attribute__((__target__("ssse3")));
+extern void test_tbm (void)			__attribute__((__target__("tbm")));
+extern void test_avx (void)			__attribute__((__target__("avx")));
+extern void test_avx2 (void)			__attribute__((__target__("avx2")));
+
+extern void test_no_abm (void)			__attribute__((__target__("no-abm")));
+extern void test_no_aes (void)			__attribute__((__target__("no-aes")));
+extern void test_no_bmi (void)			__attribute__((__target__("no-bmi")));
+extern void test_no_mmx (void)			__attribute__((__target__("no-mmx")));
+extern void test_no_pclmul (void)		__attribute__((__target__("no-pclmul")));
+extern void test_no_popcnt (void)		__attribute__((__target__("no-popcnt")));
+extern void test_no_recip (void)		__attribute__((__target__("no-recip")));
+extern void test_no_sse (void)			__attribute__((__target__("no-sse")));
+extern void test_no_sse2 (void)			__attribute__((__target__("no-sse2")));
+extern void test_no_sse3 (void)			__attribute__((__target__("no-sse3")));
+extern void test_no_sse4 (void)			__attribute__((__target__("no-sse4")));
+extern void test_no_sse4_1 (void)		__attribute__((__target__("no-sse4.1")));
+extern void test_no_sse4_2 (void)		__attribute__((__target__("no-sse4.2")));
+extern void test_no_sse4a (void)		__attribute__((__target__("no-sse4a")));
+extern void test_no_fma (void)			__attribute__((__target__("no-fma")));
+extern void test_no_fma4 (void)			__attribute__((__target__("no-fma4")));
+extern void test_no_xop (void)			__attribute__((__target__("no-xop")));
+extern void test_no_ssse3 (void)		__attribute__((__target__("no-ssse3")));
+extern void test_no_tbm (void)			__attribute__((__target__("no-tbm")));
+extern void test_no_avx (void)			__attribute__((__target__("no-avx")));
+extern void test_no_avx2 (void)   		__attribute__((__target__("no-avx2")));
+
+extern void test_arch_i386 (void)		__attribute__((__target__("arch=i386")));
+extern void test_arch_i486 (void)		__attribute__((__target__("arch=i486")));
+extern void test_arch_i586 (void)		__attribute__((__target__("arch=i586")));
+extern void test_arch_pentium (void)		__attribute__((__target__("arch=pentium")));
+extern void test_arch_pentium_mmx (void)	__attribute__((__target__("arch=pentium-mmx")));
+extern void test_arch_winchip_c6 (void)		__attribute__((__target__("arch=winchip-c6")));
+extern void test_arch_winchip2 (void)		__attribute__((__target__("arch=winchip2")));
+extern void test_arch_c3 (void)			__attribute__((__target__("arch=c3")));
+extern void test_arch_c3_2 (void)		__attribute__((__target__("arch=c3-2")));
+extern void test_arch_i686 (void)		__attribute__((__target__("arch=i686")));
+extern void test_arch_pentiumpro (void)		__attribute__((__target__("arch=pentiumpro")));
+extern void test_arch_pentium2 (void)		__attribute__((__target__("arch=pentium2")));
+extern void test_arch_pentium3 (void)		__attribute__((__target__("arch=pentium3")));
+extern void test_arch_pentium3m (void)		__attribute__((__target__("arch=pentium3m")));
+extern void test_arch_pentium_m (void)		__attribute__((__target__("arch=pentium-m")));
+extern void test_arch_pentium4 (void)		__attribute__((__target__("arch=pentium4")));
+extern void test_arch_pentium4m (void)		__attribute__((__target__("arch=pentium4m")));
+extern void test_arch_prescott (void)		__attribute__((__target__("arch=prescott")));
+extern void test_arch_nocona (void)		__attribute__((__target__("arch=nocona")));
+extern void test_arch_core2 (void)		__attribute__((__target__("arch=core2")));
+extern void test_arch_corei7 (void)		__attribute__((__target__("arch=corei7")));
+extern void test_arch_corei7_avx (void)		__attribute__((__target__("arch=corei7-avx")));
+extern void test_arch_core_avx2 (void)		__attribute__((__target__("arch=core-avx2")));
+extern void test_arch_geode (void)		__attribute__((__target__("arch=geode")));
+extern void test_arch_k6 (void)			__attribute__((__target__("arch=k6")));
+extern void test_arch_k6_2 (void)		__attribute__((__target__("arch=k6-2")));
+extern void test_arch_k6_3 (void)		__attribute__((__target__("arch=k6-3")));
+extern void test_arch_athlon (void)		__attribute__((__target__("arch=athlon")));
+extern void test_arch_athlon_tbird (void)	__attribute__((__target__("arch=athlon-tbird")));
+extern void test_arch_athlon_4 (void)		__attribute__((__target__("arch=athlon-4")));
+extern void test_arch_athlon_xp (void)		__attribute__((__target__("arch=athlon-xp")));
+extern void test_arch_athlon_mp (void)		__attribute__((__target__("arch=athlon-mp")));
+extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
+extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));
+extern void test_arch_opteron (void)		__attribute__((__target__("arch=opteron")));
+extern void test_arch_opteron_sse3 (void)	__attribute__((__target__("arch=opteron-sse3")));
+extern void test_arch_athlon64 (void)		__attribute__((__target__("arch=athlon64")));
+extern void test_arch_athlon64_sse3 (void)	__attribute__((__target__("arch=athlon64-sse3")));
+extern void test_arch_athlon_fx (void)		__attribute__((__target__("arch=athlon-fx")));
+extern void test_arch_amdfam10 (void)		__attribute__((__target__("arch=amdfam10")));
+extern void test_arch_barcelona (void)		__attribute__((__target__("arch=barcelona")));
+extern void test_arch_bdver1 (void)		__attribute__((__target__("arch=bdver1")));
+extern void test_arch_bdver2 (void)		__attribute__((__target__("arch=bdver2")));
+extern void test_arch_bdver3 (void)		__attribute__((__target__("arch=bdver3")));
+extern void test_arch_foo (void)		__attribute__((__target__("arch=foo"))); /* { dg-error "bad value" } */
+
+extern void test_tune_i386 (void)		__attribute__((__target__("tune=i386")));
+extern void test_tune_i486 (void)		__attribute__((__target__("tune=i486")));
+extern void test_tune_i586 (void)		__attribute__((__target__("tune=i586")));
+extern void test_tune_pentium (void)		__attribute__((__target__("tune=pentium")));
+extern void test_tune_pentium_mmx (void)	__attribute__((__target__("tune=pentium-mmx")));
+extern void test_tune_winchip_c6 (void)		__attribute__((__target__("tune=winchip-c6")));
+extern void test_tune_winchip2 (void)		__attribute__((__target__("tune=winchip2")));
+extern void test_tune_c3 (void)			__attribute__((__target__("tune=c3")));
+extern void test_tune_c3_2 (void)		__attribute__((__target__("tune=c3-2")));
+extern void test_tune_i686 (void)		__attribute__((__target__("tune=i686")));
+extern void test_tune_pentiumpro (void)		__attribute__((__target__("tune=pentiumpro")));
+extern void test_tune_pentium2 (void)		__attribute__((__target__("tune=pentium2")));
+extern void test_tune_pentium3 (void)		__attribute__((__target__("tune=pentium3")));
+extern void test_tune_pentium3m (void)		__attribute__((__target__("tune=pentium3m")));
+extern void test_tune_pentium_m (void)		__attribute__((__target__("tune=pentium-m")));
+extern void test_tune_pentium4 (void)		__attribute__((__target__("tune=pentium4")));
+extern void test_tune_pentium4m (void)		__attribute__((__target__("tune=pentium4m")));
+extern void test_tune_prescott (void)		__attribute__((__target__("tune=prescott")));
+extern void test_tune_nocona (void)		__attribute__((__target__("tune=nocona")));
+extern void test_tune_core2 (void)		__attribute__((__target__("tune=core2")));
+extern void test_tune_corei7 (void)		__attribute__((__target__("tune=corei7")));
+extern void test_tune_corei7_avx (void)		__attribute__((__target__("tune=corei7-avx")));
+extern void test_tune_core_avx2 (void)		__attribute__((__target__("tune=core-avx2")));
+extern void test_tune_geode (void)		__attribute__((__target__("tune=geode")));
+extern void test_tune_k6 (void)			__attribute__((__target__("tune=k6")));
+extern void test_tune_k6_2 (void)		__attribute__((__target__("tune=k6-2")));
+extern void test_tune_k6_3 (void)		__attribute__((__target__("tune=k6-3")));
+extern void test_tune_athlon (void)		__attribute__((__target__("tune=athlon")));
+extern void test_tune_athlon_tbird (void)	__attribute__((__target__("tune=athlon-tbird")));
+extern void test_tune_athlon_4 (void)		__attribute__((__target__("tune=athlon-4")));
+extern void test_tune_athlon_xp (void)		__attribute__((__target__("tune=athlon-xp")));
+extern void test_tune_athlon_mp (void)		__attribute__((__target__("tune=athlon-mp")));
+extern void test_tune_k8 (void)			__attribute__((__target__("tune=k8")));
+extern void test_tune_k8_sse3 (void)		__attribute__((__target__("tune=k8-sse3")));
+extern void test_tune_opteron (void)		__attribute__((__target__("tune=opteron")));
+extern void test_tune_opteron_sse3 (void)	__attribute__((__target__("tune=opteron-sse3")));
+extern void test_tune_athlon64 (void)		__attribute__((__target__("tune=athlon64")));
+extern void test_tune_athlon64_sse3 (void)	__attribute__((__target__("tune=athlon64-sse3")));
+extern void test_tune_athlon_fx (void)		__attribute__((__target__("tune=athlon-fx")));
+extern void test_tune_amdfam10 (void)		__attribute__((__target__("tune=amdfam10")));
+extern void test_tune_barcelona (void)		__attribute__((__target__("tune=barcelona")));
+extern void test_tune_bdver1 (void)		__attribute__((__target__("tune=bdver1")));
+extern void test_tune_bdver2 (void)		__attribute__((__target__("tune=bdver2")));
+extern void test_tune_bdver3 (void)		__attribute__((__target__("tune=bdver3")));
+extern void test_tune_generic (void)		__attribute__((__target__("tune=generic")));
+extern void test_tune_foo (void)		__attribute__((__target__("tune=foo"))); /* { dg-error "bad value" } */
+
+extern void test_fpmath_sse (void)		__attribute__((__target__("sse2,fpmath=sse")));
+extern void test_fpmath_387 (void)		__attribute__((__target__("sse2,fpmath=387")));
+extern void test_fpmath_sse_387 (void)		__attribute__((__target__("sse2,fpmath=sse+387")));
+extern void test_fpmath_387_sse (void)		__attribute__((__target__("sse2,fpmath=387+sse")));
+extern void test_fpmath_both (void)		__attribute__((__target__("sse2,fpmath=both")));
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-6.c
new file mode 100644
index 000000000..e28b38c44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-6.c
@@ -0,0 +1,76 @@
+/* Test whether all of the 64-bit function specific options are accepted
+   without error.  */
+/* { dg-do compile { target { ! { ia32 } } } } */
+
+extern void test_abm (void)			__attribute__((__target__("abm")));
+extern void test_aes (void)			__attribute__((__target__("aes")));
+extern void test_bmi (void)			__attribute__((__target__("bmi")));
+extern void test_mmx (void)			__attribute__((__target__("mmx")));
+extern void test_pclmul (void)			__attribute__((__target__("pclmul")));
+extern void test_popcnt (void)			__attribute__((__target__("popcnt")));
+extern void test_recip (void)			__attribute__((__target__("recip")));
+extern void test_sse (void)			__attribute__((__target__("sse")));
+extern void test_sse2 (void)			__attribute__((__target__("sse2")));
+extern void test_sse3 (void)			__attribute__((__target__("sse3")));
+extern void test_sse4 (void)			__attribute__((__target__("sse4")));
+extern void test_sse4_1 (void)			__attribute__((__target__("sse4.1")));
+extern void test_sse4_2 (void)			__attribute__((__target__("sse4.2")));
+extern void test_sse4a (void)			__attribute__((__target__("sse4a")));
+extern void test_fma4 (void)			__attribute__((__target__("fma4")));
+extern void test_ssse3 (void)			__attribute__((__target__("ssse3")));
+extern void test_tbm (void)			__attribute__((__target__("tbm")));
+extern void test_avx (void)			__attribute__((__target__("avx")));
+extern void test_avx2 (void)			__attribute__((__target__("avx2")));
+
+extern void test_no_abm (void)			__attribute__((__target__("no-abm")));
+extern void test_no_aes (void)			__attribute__((__target__("no-aes")));
+extern void test_no_bmi (void)			__attribute__((__target__("no-bmi")));
+extern void test_no_mmx (void)			__attribute__((__target__("no-mmx")));
+extern void test_no_pclmul (void)		__attribute__((__target__("no-pclmul")));
+extern void test_no_popcnt (void)		__attribute__((__target__("no-popcnt")));
+extern void test_no_recip (void)		__attribute__((__target__("no-recip")));
+extern void test_no_sse (void)			__attribute__((__target__("no-sse")));
+extern void test_no_sse2 (void)			__attribute__((__target__("no-sse2")));
+extern void test_no_sse3 (void)			__attribute__((__target__("no-sse3")));
+extern void test_no_sse4 (void)			__attribute__((__target__("no-sse4")));
+extern void test_no_sse4_1 (void)		__attribute__((__target__("no-sse4.1")));
+extern void test_no_sse4_2 (void)		__attribute__((__target__("no-sse4.2")));
+extern void test_no_sse4a (void)		__attribute__((__target__("no-sse4a")));
+extern void test_no_fma4 (void)			__attribute__((__target__("no-fma4")));
+extern void test_no_ssse3 (void)		__attribute__((__target__("no-ssse3")));
+extern void test_no_tbm (void)			__attribute__((__target__("no-tbm")));
+extern void test_no_avx (void)			__attribute__((__target__("no-avx")));
+extern void test_no_avx2 (void) 		__attribute__((__target__("no-avx2")));
+
+extern void test_arch_nocona (void)		__attribute__((__target__("arch=nocona")));
+extern void test_arch_core2 (void)		__attribute__((__target__("arch=core2")));
+extern void test_arch_k8 (void)			__attribute__((__target__("arch=k8")));
+extern void test_arch_k8_sse3 (void)		__attribute__((__target__("arch=k8-sse3")));
+extern void test_arch_opteron (void)		__attribute__((__target__("arch=opteron")));
+extern void test_arch_opteron_sse3 (void)	__attribute__((__target__("arch=opteron-sse3")));
+extern void test_arch_athlon64 (void)		__attribute__((__target__("arch=athlon64")));
+extern void test_arch_athlon64_sse3 (void)	__attribute__((__target__("arch=athlon64-sse3")));
+extern void test_arch_athlon_fx (void)		__attribute__((__target__("arch=athlon-fx")));
+extern void test_arch_amdfam10 (void)		__attribute__((__target__("arch=amdfam10")));
+extern void test_arch_barcelona (void)		__attribute__((__target__("arch=barcelona")));
+extern void test_arch_foo (void)		__attribute__((__target__("arch=foo"))); /* { dg-error "bad value" } */
+
+extern void test_tune_nocona (void)		__attribute__((__target__("tune=nocona")));
+extern void test_tune_core2 (void)		__attribute__((__target__("tune=core2")));
+extern void test_tune_k8 (void)			__attribute__((__target__("tune=k8")));
+extern void test_tune_k8_sse3 (void)		__attribute__((__target__("tune=k8-sse3")));
+extern void test_tune_opteron (void)		__attribute__((__target__("tune=opteron")));
+extern void test_tune_opteron_sse3 (void)	__attribute__((__target__("tune=opteron-sse3")));
+extern void test_tune_athlon64 (void)		__attribute__((__target__("tune=athlon64")));
+extern void test_tune_athlon64_sse3 (void)	__attribute__((__target__("tune=athlon64-sse3")));
+extern void test_tune_athlon_fx (void)		__attribute__((__target__("tune=athlon-fx")));
+extern void test_tune_amdfam10 (void)		__attribute__((__target__("tune=amdfam10")));
+extern void test_tune_barcelona (void)		__attribute__((__target__("tune=barcelona")));
+extern void test_tune_generic (void)		__attribute__((__target__("tune=generic")));
+extern void test_tune_foo (void)		__attribute__((__target__("tune=foo"))); /* { dg-error "bad value" } */
+
+extern void test_fpmath_sse (void)		__attribute__((__target__("sse2,fpmath=sse")));
+extern void test_fpmath_387 (void)		__attribute__((__target__("sse2,fpmath=387")));
+extern void test_fpmath_sse_387 (void)		__attribute__((__target__("sse2,fpmath=sse+387")));
+extern void test_fpmath_387_sse (void)		__attribute__((__target__("sse2,fpmath=387+sse")));
+extern void test_fpmath_both (void)		__attribute__((__target__("sse2,fpmath=both")));
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-7.c
new file mode 100644
index 000000000..56b549050
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-7.c
@@ -0,0 +1,13 @@
+/* Test whether using target specific options, we can generate the reciprocal
+   square root instruction.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mno-recip -mfpmath=sse -ffast-math" } */
+
+float do_recip  (float a) __attribute__((__target__("recip")));
+float do_normal (float a);
+
+float do_recip  (float a) { return 1.0f / __builtin_sqrtf (a); }
+float do_normal (float a) { return 1.0f / __builtin_sqrtf (a); }
+
+/* { dg-final { scan-assembler "sqrtss" } } */
+/* { dg-final { scan-assembler "rsqrtss" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-8.c
new file mode 100644
index 000000000..225843493
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-8.c
@@ -0,0 +1,162 @@
+/* Test whether using target specific options, we can use the x86 builtin
+   functions in functions with the appropriate function specific options.  */
+/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
+/* { dg-options "-O2 -march=k8 -mno-sse3 -mfpmath=sse" } */
+
+typedef float     __m128  __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef double    __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef int	  __m128w __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#ifdef __SSE3__
+#error "-msse3 should not be set for this test"
+#endif
+
+__m128d sse3_hsubpd (__m128d a, __m128d b) __attribute__((__target__("sse3")));
+__m128d generic_hsubpd (__m128d a, __m128d b);
+
+__m128d
+sse3_hsubpd (__m128d a, __m128d b)
+{
+  return __builtin_ia32_hsubpd (a, b);
+}
+
+__m128d
+generic_hsubpd (__m128d a, __m128d b)
+{
+  return __builtin_ia32_hsubpd (a, b);			/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSSE3__
+#error "-mssse3 should not be set for this test"
+#endif
+
+__m128w ssse3_psignd128 (__m128w a, __m128w b) __attribute__((__target__("ssse3")));
+__m128w generic_psignd (__m128w ab, __m128w b);
+
+__m128w
+ssse3_psignd128 (__m128w a, __m128w b)
+{
+  return __builtin_ia32_psignd128 (a, b);
+}
+
+__m128w
+generic_psignd128 (__m128w a, __m128w b)
+{
+  return __builtin_ia32_psignd128 (a, b);		/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSE4_1__
+#error "-msse4.1 should not be set for this test"
+#endif
+
+__m128d sse4_1_blendvpd (__m128d a, __m128d b, __m128d c) __attribute__((__target__("sse4.1")));
+__m128d generic_blendvpd (__m128d a, __m128d b, __m128d c);
+
+__m128d
+sse4_1_blendvpd  (__m128d a, __m128d b, __m128d c)
+{
+  return __builtin_ia32_blendvpd (a, b, c);
+}
+
+__m128d
+generic_blendvpd  (__m128d a, __m128d b, __m128d c)
+{
+  return __builtin_ia32_blendvpd (a, b, c);		/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSE4_2__
+#error "-msse4.2 should not be set for this test"
+#endif
+
+__m128i sse4_2_pcmpgtq (__m128i a, __m128i b) __attribute__((__target__("sse4.2")));
+__m128i generic_pcmpgtq (__m128i ab, __m128i b);
+
+__m128i
+sse4_2_pcmpgtq (__m128i a, __m128i b)
+{
+  return __builtin_ia32_pcmpgtq (a, b);
+}
+
+__m128i
+generic_pcmpgtq (__m128i a, __m128i b)
+{
+  return __builtin_ia32_pcmpgtq (a, b);			/* { dg-error "needs isa option" } */
+}
+
+#ifdef __SSE4A__
+#error "-msse4a should not be set for this test"
+#endif
+
+__m128i sse4_2_insertq (__m128i a, __m128i b) __attribute__((__target__("sse4a")));
+__m128i generic_insertq (__m128i ab, __m128i b);
+
+__m128i
+sse4_2_insertq (__m128i a, __m128i b)
+{
+  return __builtin_ia32_insertq (a, b);
+}
+
+__m128i
+generic_insertq (__m128i a, __m128i b)
+{
+  return __builtin_ia32_insertq (a, b);			/* { dg-error "needs isa option" } */
+}
+
+#ifdef __FMA4__
+#error "-mfma4 should not be set for this test"
+#endif
+
+__m128d fma4_fmaddpd (__m128d a, __m128d b, __m128d c) __attribute__((__target__("fma4")));
+__m128d generic_fmaddpd (__m128d a, __m128d b, __m128d c);
+
+__m128d
+fma4_fmaddpd  (__m128d a, __m128d b, __m128d c)
+{
+  return __builtin_ia32_vfmaddpd (a, b, c);
+}
+
+__m128d
+generic_fmaddpd  (__m128d a, __m128d b, __m128d c)
+{
+  return __builtin_ia32_vfmaddpd (a, b, c);		/* { dg-error "needs isa option" } */
+}
+
+#ifdef __AES__
+#error "-maes should not be set for this test"
+#endif
+
+__m128i aes_aesimc128 (__m128i a) __attribute__((__target__("aes")));
+__m128i generic_aesimc128 (__m128i a);
+
+__m128i
+aes_aesimc128 (__m128i a)
+{
+  return __builtin_ia32_aesimc128 (a);
+}
+
+__m128i
+generic_aesimc128 (__m128i a)
+{
+  return __builtin_ia32_aesimc128 (a);			/* { dg-error "needs isa option" } */
+}
+
+#ifdef __PCLMUL__
+#error "-mpclmul should not be set for this test"
+#endif
+
+__m128i pclmul_pclmulqdq128 (__m128i a, __m128i b) __attribute__((__target__("pclmul")));
+__m128i generic_pclmulqdq128 (__m128i a, __m128i b);
+
+__m128i
+pclmul_pclmulqdq128 (__m128i a, __m128i b)
+{
+  return __builtin_ia32_pclmulqdq128 (a, b, 5);
+}
+
+__m128i
+generic_pclmulqdq128 (__m128i a, __m128i b)
+{
+  return __builtin_ia32_pclmulqdq128 (a, b, 5);		/* { dg-error "needs isa option" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-9.c
new file mode 100644
index 000000000..78714e124
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/funcspec-9.c
@@ -0,0 +1,36 @@
+/* Test whether using target specific options, we can generate FMA4 code.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mfpmath=sse -msse2" } */
+
+extern void exit (int);
+
+#ifdef __FMA4__
+#warning "__FMA4__ should not be defined before #pragma GCC target."
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("fma4")
+
+#ifndef __FMA4__
+#warning "__FMA4__ should have be defined after #pragma GCC target."
+#endif
+
+float
+flt_mul_add (float a, float b, float c)
+{
+  return (a * b) + c;
+}
+
+#pragma GCC pop_options
+#ifdef __FMA4__
+#warning "__FMA4__ should not be defined after #pragma GCC pop target."
+#endif
+
+double
+dbl_mul_add (double a, double b, double c)
+{
+  return (a * b) + c;
+}
+
+/* { dg-final { scan-assembler "vfmaddss" } } */
+/* { dg-final { scan-assembler "addsd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fxrstor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fxrstor-1.c
new file mode 100644
index 000000000..0e1ca191f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fxrstor-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mfxsr -O2" } */
+/* { dg-final { scan-assembler "fxrstor\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+fxsave_test (void)
+{
+  char fxsave_region [512] __attribute__((aligned(16)));
+  _fxrstor (fxsave_region);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fxrstor64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fxrstor64-1.c
new file mode 100644
index 000000000..fbdb1f6fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fxrstor64-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mfxsr -O2" } */
+/* { dg-final { scan-assembler "fxrstor64\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+fxsave_test (void)
+{
+  char fxsave_region [512] __attribute__((aligned(16)));
+  _fxrstor64 (fxsave_region);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fxsave-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fxsave-1.c
new file mode 100644
index 000000000..567af8d0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fxsave-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mfxsr -O2" } */
+/* { dg-final { scan-assembler "fxsave\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+fxsave_test (void)
+{
+  char fxsave_region [512] __attribute__((aligned(16)));
+  _fxsave (fxsave_region);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/fxsave64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/fxsave64-1.c
new file mode 100644
index 000000000..317548ad6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/fxsave64-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mfxsr -O2" } */
+/* { dg-final { scan-assembler "fxsave64\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+fxsave_test (void)
+{
+  char fxsave_region [512] __attribute__((aligned(16)));
+  _fxsave64 (fxsave_region);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c
new file mode 100644
index 000000000..6d6ce992b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c
@@ -0,0 +1,24 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
+/* { dg-options "-march=i386" } */
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c
new file mode 100644
index 000000000..08c4e0b85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c
@@ -0,0 +1,25 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i486" } } */
+/* { dg-options "-march=i486" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c
new file mode 100644
index 000000000..40dd9357f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-3.c
@@ -0,0 +1,23 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-march=i586" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c
new file mode 100644
index 000000000..ab250ddfa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-4.c
@@ -0,0 +1,22 @@
+/* { dg-do preprocess { target { ! { ia32 } } } } */
+/* { dg-options "-mcx16" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/headmerge-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/headmerge-1.c
new file mode 100644
index 000000000..0c1914340
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/headmerge-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile }  */
+/* { dg-options "-O2" }  */
+/* { dg-final { scan-assembler-times "\\\$120|, 120" 1 } } */
+
+extern void foo1 (int);
+extern void foo2 (int);
+
+void t (int x, int y)
+{
+  if (y < 5)
+    foo1 (120);
+  else
+    foo2 (120);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/headmerge-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/headmerge-2.c
new file mode 100644
index 000000000..aa2e56255
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/headmerge-2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile }  */
+/* { dg-options "-O2" }  */
+/* { dg-final { scan-assembler-times "\\\$120|, 120" 1 } } */
+
+extern void foo1 (int);
+extern void foo2 (int);
+extern void foo3 (int);
+extern void foo4 (int);
+extern void foo5 (int);
+extern void foo6 (int);
+
+void t (int x, int y)
+{
+  switch (y)
+    {
+    case 1:
+      foo1 (120);
+      break;
+    case 5:
+      foo2 (120);
+      break;
+    case 7:
+      foo3 (120);
+      break;
+    case 10:
+      foo4 (120);
+      break;
+    case 13:
+      foo5 (120);
+      break;
+    default:
+      foo6 (120);
+      break;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-add-acq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-add-acq-1.c
new file mode 100644
index 000000000..71230d52c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-add-acq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+add" } } */
+
+void
+hle_add (int *p, int v)
+{
+  __atomic_fetch_add (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-add-rel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-add-rel-1.c
new file mode 100644
index 000000000..6b7cfc403
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-add-rel-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+add" } } */
+
+void
+hle_add (int *p, int v)
+{
+  __atomic_fetch_add (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-and-acq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-and-acq-1.c
new file mode 100644
index 000000000..078f89610
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-and-acq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+and" } } */
+
+void
+hle_and (int *p, int v)
+{
+  __atomic_fetch_and (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-and-rel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-and-rel-1.c
new file mode 100644
index 000000000..c1025f36b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-and-rel-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+and" } } */
+
+void
+hle_and (int *p, int v)
+{
+  __atomic_fetch_and (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-clear-rel.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-clear-rel.c
new file mode 100644
index 000000000..137a820c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-clear-rel.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+mov" } } */
+
+void
+hle_clear (char *p, int v)
+{
+  __atomic_clear (p, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-cmpxchg-acq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-cmpxchg-acq-1.c
new file mode 100644
index 000000000..cea7c09ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-cmpxchg-acq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+cmpxchg" } } */
+
+int
+hle_cmpxchg (int *p, int oldv, int newv)
+{
+  return __atomic_compare_exchange_n (p, &oldv, newv, 0, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-cmpxchg-rel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-cmpxchg-rel-1.c
new file mode 100644
index 000000000..a2749e82f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-cmpxchg-rel-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+cmpxchg" } } */
+
+int
+hle_cmpxchg (int *p, int oldv, int newv)
+{
+  return __atomic_compare_exchange_n (p, &oldv, newv, 0, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE, __ATOMIC_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-or-acq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-or-acq-1.c
new file mode 100644
index 000000000..8b28036bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-or-acq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+or" } } */
+
+void
+hle_or (int *p, int v)
+{
+  __atomic_or_fetch (p, 1, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-or-rel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-or-rel-1.c
new file mode 100644
index 000000000..939697a85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-or-rel-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+or" } } */
+
+void
+hle_xor (int *p, int v)
+{
+  __atomic_fetch_or (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-store-rel.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-store-rel.c
new file mode 100644
index 000000000..7295d3321
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-store-rel.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+mov" } } */
+
+void
+hle_store (int *p, int v)
+{
+  __atomic_store_n (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-sub-acq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-sub-acq-1.c
new file mode 100644
index 000000000..02e94b361
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-sub-acq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+sub" } } */
+
+void
+hle_sub (int *p, int v)
+{
+  __atomic_fetch_sub (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-sub-rel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-sub-rel-1.c
new file mode 100644
index 000000000..3a8c04e5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-sub-rel-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+sub" } } */
+
+void
+hle_sub (int *p, int v)
+{
+  __atomic_fetch_sub (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xadd-acq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xadd-acq-1.c
new file mode 100644
index 000000000..4527fa957
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xadd-acq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+xadd" } } */
+
+int
+hle_xadd (int *p, int v)
+{
+  return __atomic_fetch_add (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xadd-rel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xadd-rel-1.c
new file mode 100644
index 000000000..dd514143f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xadd-rel-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+xadd" } } */
+
+int
+hle_xadd (int *p, int v)
+{
+  return __atomic_fetch_add (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xchg-acq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xchg-acq-1.c
new file mode 100644
index 000000000..441c45470
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xchg-acq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+xchg" } } */
+
+int
+hle_xchg (int *p, int v)
+{
+  return __atomic_exchange_n (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xchg-rel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xchg-rel-1.c
new file mode 100644
index 000000000..a6bad3335
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xchg-rel-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+xchg" } } */
+
+int
+hle_xchg (int *p, int v)
+{
+  return __atomic_exchange_n (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xor-acq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xor-acq-1.c
new file mode 100644
index 000000000..d381be92c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xor-acq-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xacquire\|\.byte\[ \t\]+0xf2\)\[ \t\n\]+xor" } } */
+
+void
+hle_xor (int *p, int v)
+{
+  __atomic_fetch_xor (p, v, __ATOMIC_ACQUIRE | __ATOMIC_HLE_ACQUIRE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xor-rel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xor-rel-1.c
new file mode 100644
index 000000000..777bc0ac0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/hle-xor-rel-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mhle" } */
+/* { dg-final { scan-assembler "lock;?\[ \n\t\]+\(xrelease\|\.byte\[ \t\]+0xf3\)\[ \t\n\]+xor" } } */
+
+void
+hle_xor (int *p, int v)
+{
+  __atomic_fetch_xor (p, v, __ATOMIC_RELEASE | __ATOMIC_HLE_RELEASE);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/i386.exp b/gcc-4.9/gcc/testsuite/gcc.target/i386/i386.exp
new file mode 100644
index 000000000..080e302b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/i386.exp
@@ -0,0 +1,370 @@
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a x86 target.
+if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Return 1 if attribute ms_hook_prologue is supported.
+proc check_effective_target_ms_hook_prologue { } {
+    if { [check_no_compiler_messages ms_hook_prologue object {
+	     void __attribute__ ((__ms_hook_prologue__)) foo ();
+	 } ""] } {
+	return 1
+    } else {
+	return 0
+    }
+}
+
+# Return 1 if 3dnow instructions can be compiled.
+proc check_effective_target_3dnow { } {
+    return [check_no_compiler_messages 3dnow object {
+	typedef int __m64 __attribute__ ((__vector_size__ (8)));
+	typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+	__m64 _m_pfadd (__m64 __A, __m64 __B)
+	{
+	    return (__m64) __builtin_ia32_pfadd ((__v2sf)__A, (__v2sf)__B);
+	}
+    } "-O2 -m3dnow" ]
+}
+
+# Return 1 if sse3 instructions can be compiled.
+proc check_effective_target_sse3 { } {
+    return [check_no_compiler_messages sse3 object {
+	typedef double __m128d __attribute__ ((__vector_size__ (16)));
+	typedef double __v2df __attribute__ ((__vector_size__ (16)));
+
+	__m128d _mm_addsub_pd (__m128d __X, __m128d __Y)
+	{
+	    return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y);
+	}
+    } "-O2 -msse3" ]
+}
+
+# Return 1 if ssse3 instructions can be compiled.
+proc check_effective_target_ssse3 { } {
+    return [check_no_compiler_messages ssse3 object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_abs_epi32 (__m128i __X)
+	{
+	    return (__m128i) __builtin_ia32_pabsd128 ((__v4si)__X);
+	}
+    } "-O2 -mssse3" ]
+}
+
+# Return 1 if sse4 instructions can be compiled.
+proc check_effective_target_sse4 { } {
+    return [check_no_compiler_messages sse4.1 object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_mullo_epi32 (__m128i __X, __m128i __Y)
+	{
+	    return (__m128i) __builtin_ia32_pmulld128 ((__v4si)__X,
+						       (__v4si)__Y);
+	}
+    } "-O2 -msse4.1" ]
+}
+
+# Return 1 if aes instructions can be compiled.
+proc check_effective_target_aes { } {
+    return [check_no_compiler_messages aes object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_aesimc_si128 (__m128i __X)
+	{
+	    return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
+	}
+    } "-O2 -maes" ]
+}
+
+# Return 1 if vaes instructions can be compiled.
+proc check_effective_target_vaes { } {
+    return [check_no_compiler_messages vaes object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_aesimc_si128 (__m128i __X)
+	{
+	    return (__m128i) __builtin_ia32_aesimc128 ((__v2di)__X);
+	}
+    } "-O2 -maes -mavx" ]
+}
+
+# Return 1 if pclmul instructions can be compiled.
+proc check_effective_target_pclmul { } {
+    return [check_no_compiler_messages pclmul object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i pclmulqdq_test (__m128i __X, __m128i __Y)
+	{
+	    return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
+							  (__v2di)__Y,
+							  1);
+	}
+    } "-O2 -mpclmul" ]
+}
+
+# Return 1 if vpclmul instructions can be compiled.
+proc check_effective_target_vpclmul { } {
+    return [check_no_compiler_messages vpclmul object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i pclmulqdq_test (__m128i __X, __m128i __Y)
+	{
+	    return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
+							  (__v2di)__Y,
+							  1);
+	}
+    } "-O2 -mpclmul -mavx" ]
+}
+
+# Return 1 if sse4a instructions can be compiled.
+proc check_effective_target_sse4a { } {
+    return [check_no_compiler_messages sse4a object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_insert_si64 (__m128i __X,__m128i __Y)
+	{
+	    return (__m128i) __builtin_ia32_insertq ((__v2di)__X, (__v2di)__Y);
+	}
+    } "-O2 -msse4a" ]
+}
+
+# Return 1 if fma4 instructions can be compiled.
+proc check_effective_target_fma4 { } {
+    return [check_no_compiler_messages fma4 object {
+        typedef float __m128 __attribute__ ((__vector_size__ (16)));
+	typedef float __v4sf __attribute__ ((__vector_size__ (16)));
+	__m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
+	{
+	    return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
+						     (__v4sf)__B,
+						     (__v4sf)__C);
+	}
+    } "-O2 -mfma4" ]
+}
+
+# Return 1 if fma instructions can be compiled.
+proc check_effective_target_fma { } {
+    return [check_no_compiler_messages fma object {
+        typedef float __m128 __attribute__ ((__vector_size__ (16)));
+	typedef float __v4sf __attribute__ ((__vector_size__ (16)));
+	__m128 _mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
+	{
+	    return (__m128) __builtin_ia32_vfmaddps ((__v4sf)__A,
+						     (__v4sf)__B,
+						     (__v4sf)__C);
+	}
+    } "-O2 -mfma" ]
+}
+
+# Return 1 if xop instructions can be compiled.
+proc check_effective_target_xop { } {
+    return [check_no_compiler_messages xop object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+	__m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C)
+	{
+	    return (__m128i) __builtin_ia32_vpmacssww ((__v8hi)__A,
+						       (__v8hi)__B,
+						       (__v8hi)__C);
+	}
+    } "-O2 -mxop" ]
+}
+
+# Return 1 if lzcnt instruction can be compiled.
+proc check_effective_target_lzcnt { } {
+    return [check_no_compiler_messages lzcnt object {
+	unsigned short _lzcnt (unsigned short __X)
+	{
+	   return __builtin_clzs (__X);
+	}
+    } "-mlzcnt" ]
+}
+
+# Return 1 if bmi instructions can be compiled.
+proc check_effective_target_bmi { } {
+    return [check_no_compiler_messages bmi object {
+	unsigned int __bextr_u32 (unsigned int __X, unsigned int __Y)
+	{
+	  return __builtin_ia32_bextr_u32 (__X, __Y);
+	}
+    } "-mbmi" ]
+}
+
+# Return 1 if bmi2 instructions can be compiled.
+proc check_effective_target_bmi2 { } {
+    return [check_no_compiler_messages bmi2 object {
+	unsigned int
+	_bzhi_u32 (unsigned int __X, unsigned int __Y)
+	{
+	    return __builtin_ia32_bzhi_si (__X, __Y);
+	}
+    } "-mbmi2" ]
+}
+
+# Return 1 if ADX instructions can be compiled.
+proc check_effective_target_adx { } {
+    return [check_no_compiler_messages adx object {
+	unsigned char
+	_adxcarry_u32 (unsigned char __CF, unsigned int __X,
+		   unsigned int __Y, unsigned int *__P)
+	{
+	    return __builtin_ia32_addcarryx_u32 (__CF, __X, __Y, __P);
+	}
+    } "-madx" ]
+}
+
+# Return 1 if rtm instructions can be compiled.
+proc check_effective_target_rtm { } {
+    return [check_no_compiler_messages rtm object {
+	void
+	_rtm_xend (void)
+	{
+	    return __builtin_ia32_xend ();
+	}
+    } "-mrtm" ]
+}
+
+# Return 1 if avx512f instructions can be compiled.
+proc check_effective_target_avx512f { } {
+    return [check_no_compiler_messages avx512f object {
+	typedef long long __v8di __attribute__ ((__vector_size__ (64)));
+	__v8di
+	mm512_and_epi64  (__v8di __X, __v8di __Y)
+	{
+            __v8di __W;
+            return __builtin_ia32_pandq512_mask (__X, __Y, __W, -1);
+	}
+    } "-mavx512f" ]
+}
+
+# Return 1 if avx512cd instructions can be compiled.
+proc check_effective_target_avx512cd { } {
+    return [check_no_compiler_messages avx512cd_trans object {
+	typedef long long __v8di __attribute__ ((__vector_size__ (64)));
+	__v8di
+	_mm512_conflict_epi64 (__v8di __W, __v8di __A)
+	{
+	  return (__v8di) __builtin_ia32_vpconflictdi_512_mask ((__v8di) __A,
+		  						 (__v8di) __W,
+			  					 -1);
+	}
+   } "-Wno-psabi -mavx512cd" ]
+}
+
+# Return 1 if avx512er instructions can be compiled.
+proc check_effective_target_avx512er { } {
+    return [check_no_compiler_messages avx512er_trans object {
+	typedef float __v16sf __attribute__ ((__vector_size__ (64)));
+	__v16sf
+	mm512_exp2a23_ps  (__v16sf __X)
+	{
+        __v16sf __W;
+	    return __builtin_ia32_exp2ps_mask (__X, __W, -1, 4);
+	}
+   } "-Wno-psabi -mavx512er" ]
+}
+
+# Return 1 if sha instructions can be compiled.
+proc check_effective_target_sha { } {
+    return [check_no_compiler_messages sha object {
+	typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+	typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+	__m128i _mm_sha1msg1_epu32 (__m128i __X, __m128i __Y)
+	{
+            return (__m128i) __builtin_ia32_sha1msg1 ((__v4si)__X,
+						      (__v4si)__Y);
+	}
+    } "-O2 -msha" ]
+}
+
+# If the linker used understands -M <mapfile>, pass it to clear hardware
+# capabilities set by the Sun assembler.
+# Try mapfile syntax v2 first which is the only way to clear hwcap_2 flags.
+set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcapv2.map"
+
+if ![check_no_compiler_messages mapfilev2 executable {
+    int main (void) { return 0; }
+} $clearcap_ldflags ] {
+    # If this doesn't work, fall back to the less capable v1 syntax.
+    set clearcap_ldflags "-Wl,-M,$srcdir/$subdir/clearcap.map"
+
+    if ![check_no_compiler_messages mapfile executable {
+	int main (void) { return 0; }
+    } $clearcap_ldflags ] {
+	unset clearcap_ldflags
+    }
+}
+
+if [info exists clearcap_ldflags] {
+  if { [info procs gcc_target_compile] != [list] \
+	&& [info procs saved_gcc_target_compile] == [list] } {
+    rename gcc_target_compile saved_gcc_target_compile
+
+    proc gcc_target_compile { source dest type options } {
+      global clearcap_ldflags
+      # Always pass -Wl,-M,<mapfile>, but don't let it show up in gcc.sum.
+      lappend options "additional_flags=$clearcap_ldflags"
+
+      return [saved_gcc_target_compile $source $dest $type $options]
+    }
+  }
+}
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Special case compilation of vect-args.c so we don't have to
+# replicate it 10 times.
+foreach type { "" -mmmx -m3dnow -msse -msse2 } {
+  foreach level { "" -O } {
+    set flags "$type $level"
+    verbose -log "Testing vect-args, $flags" 1
+    dg-test $srcdir/$subdir/vect-args.c $flags ""
+  }
+}
+
+# Everything else.
+set tests [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]]
+set tests [prune $tests $srcdir/$subdir/vect-args.c]
+
+# Main loop.
+dg-runtest $tests "" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c
new file mode 100644
index 000000000..7d26f31c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ifcvt-onecmpl-abs-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* This test checks for if-conversion of one's complement
+ * abs function.  */
+/* { dg-options "-O -mtune=generic" } */
+/* { dg-final { scan-assembler "cltd" } } */
+/* { dg-final { scan-assembler "xor" } } */
+
+/* Check code generation for one's complement version of abs */
+
+int onecmplabs(int x)
+{
+  if (x < 0)
+    x = ~x;
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-1.c
new file mode 100644
index 000000000..c59b208a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-1.c
@@ -0,0 +1,19 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */
+
+#include <emmintrin.h>
+
+extern void bar (int *);
+
+int
+foo(__m128 x, __m128 y, __m128 z, int size)
+{
+  int __attribute((aligned(16))) xxx;
+
+  xxx = 2;
+  bar (&xxx);
+  return size;
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-10.c
new file mode 100644
index 000000000..612fa7208
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-10.c
@@ -0,0 +1,19 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -fomit-frame-pointer -O3 -march=barcelona -mpreferred-stack-boundary=4" } */
+
+struct s {
+	int x[8];
+};
+
+void g(struct s *);
+
+void f()
+{
+	int i;
+	struct s s;
+	for (i = 0; i < sizeof(s.x) / sizeof(*s.x); i++) s.x[i] = 1;
+	g(&s);
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-11.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-11.c
new file mode 100644
index 000000000..a830c96f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-11.c
@@ -0,0 +1,18 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -fomit-frame-pointer -O3 -march=barcelona -mpreferred-stack-boundary=4" } */
+
+void g();
+
+int p[100];
+int q[100];
+
+void f()
+{
+	int i;
+	for (i = 0; i < 100; i++) p[i] = 1;
+	g();
+	for (i = 0; i < 100; i++) q[i] = 1;
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-12.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-12.c
new file mode 100644
index 000000000..21f3f01f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-12.c
@@ -0,0 +1,20 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+struct x {
+       v4si v;
+       v4si w;
+};
+
+void y(void *);
+
+v4si x(void)
+{
+       struct x x;
+       y(&x);
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-13.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-13.c
new file mode 100644
index 000000000..cad47a9c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-13.c
@@ -0,0 +1,15 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */
+
+extern double y(double *s3);
+
+extern double s1, s2;
+
+double x(void)
+{
+  double s3 = s1 + s2;
+  return y(&s3);
+}
+
+/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-14.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-14.c
new file mode 100644
index 000000000..03ef50b69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-14.c
@@ -0,0 +1,15 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */
+
+extern int y(int *s3);
+
+extern int s1, s2;
+
+int x(void)
+{
+  int s3 = s1 + s2;
+  return y(&s3);
+}
+
+/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-15.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-15.c
new file mode 100644
index 000000000..897f3bc3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-15.c
@@ -0,0 +1,15 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -O2 -mpreferred-stack-boundary=4" } */
+
+extern long long y(long long *s3);
+
+extern long long s1, s2;
+
+long long x(void)
+{
+  long long s3 = s1 + s2;
+  return y(&s3);
+}
+
+/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-2.c
new file mode 100644
index 000000000..4fc5629f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-2.c
@@ -0,0 +1,19 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */
+
+#include <emmintrin.h>
+
+extern void bar (int *);
+
+int
+foo(__m128 x, __m128 y, __m128 z, __m128 a, int size)
+{
+  int __attribute((aligned(16))) xxx;
+
+  xxx = 2;
+  bar (&xxx);
+  return size;
+}
+
+/* { dg-final { scan-assembler-not "and\[l\]\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-3.c
new file mode 100644
index 000000000..1d39b03f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-3.c
@@ -0,0 +1,19 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */
+
+#include <emmintrin.h>
+
+extern void bar (int *);
+
+int
+foo(__m128 y, int size, ...)
+{
+  int __attribute((aligned(16))) xxx;
+
+  xxx = 2;
+  bar (&xxx);
+  return size;
+}
+
+/* { dg-final { scan-assembler-not "and\[l\]\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-4.c
new file mode 100644
index 000000000..c3be961bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-4.c
@@ -0,0 +1,20 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" } */
+
+#include <stdarg.h>
+#include <emmintrin.h>
+
+extern void bar (int *);
+
+__m128
+foo(va_list arg) 
+{
+  int __attribute((aligned(16))) xxx;
+
+  xxx = 2;
+  bar (&xxx);
+  return va_arg (arg, __m128);
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-5.c
new file mode 100644
index 000000000..f68eefcb9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-5.c
@@ -0,0 +1,16 @@
+/* PR middle-end/37009 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-mincoming-stack-boundary=2 -mpreferred-stack-boundary=2" } */
+
+extern void bar (double *);
+
+double
+foo(double x)
+{
+  double xxx = x + 13.0;
+
+  bar (&xxx);
+  return xxx;
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-8,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-6.c
new file mode 100644
index 000000000..a2448ec3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-6.c
@@ -0,0 +1,17 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+extern v4si y(v4si *s3);
+
+extern v4si s1, s2;
+
+v4si x(void)
+{
+  v4si s3 = s1 + s2;
+  return y(&s3);
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-7.c
new file mode 100644
index 000000000..0b8bbd570
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-7.c
@@ -0,0 +1,16 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -O2 -msse2 -mpreferred-stack-boundary=4" } */
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+extern v4si y(v4si, v4si, v4si, v4si, v4si);
+
+extern v4si s1, s2;
+
+v4si x(void)
+{
+  return y(s1, s2, s1, s2, s2);
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-8.c
new file mode 100644
index 000000000..61d9cb37d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-8.c
@@ -0,0 +1,18 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -O3 -msse2 -mno-avx -mpreferred-stack-boundary=4" } */
+
+float
+foo (float f)
+{
+  float array[128];
+  float x;
+  int i;
+  for (i = 0; i < sizeof(array) / sizeof(*array); i++)
+    array[i] = f;
+  for (i = 0; i < sizeof(array) / sizeof(*array); i++)
+    x += array[i];
+  return x;
+}
+
+/* { dg-final { scan-assembler "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-9.c
new file mode 100644
index 000000000..178693791
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/incoming-9.c
@@ -0,0 +1,18 @@
+/* PR target/40838 */
+/* { dg-do compile { target { { ! *-*-darwin* } && ia32 } } } */
+/* { dg-options "-w -mstackrealign -O3 -mno-sse -mpreferred-stack-boundary=4" } */
+
+float
+foo (float f)
+{
+  float array[128];
+  float x;
+  int i;
+  for (i = 0; i < sizeof(array) / sizeof(*array); i++)
+    array[i] = f;
+  for (i = 0; i < sizeof(array) / sizeof(*array); i++)
+    x += array[i];
+  return x;
+}
+
+/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/inline-mcpy.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/inline-mcpy.c
new file mode 100644
index 000000000..c31be050e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/inline-mcpy.c
@@ -0,0 +1,11 @@
+/* Test if we inline memcpy even with -Os, when the user requested it.  */
+/* Don't name this test with memcpy in its name, otherwise the scan-assembler
+   would be confused.  */
+/* { dg-do compile { target *-*-linux* *-*-gnu* } } */
+/* { dg-options "-Os -minline-all-stringops" } */
+/* { dg-final { scan-assembler-not "memcpy" } } */
+char f(int i)
+{
+  char *ram_split[] = { "5:3", "3:1", "1:1", "3:5" };
+  return ram_split[i][0];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/inline_error.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/inline_error.c
new file mode 100644
index 000000000..da1cea10c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/inline_error.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mno-popcnt" } */
+
+inline int __attribute__ ((__gnu_inline__, __always_inline__, target("popcnt")))
+foo () /* { dg-error "inlining failed in call to always_inline .* target specific option mismatch" } */
+{
+  return 0;
+}
+
+int bar()
+{
+  return foo (); /* { dg-error "called from here" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_1.c
new file mode 100644
index 000000000..802979f3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_1.c
@@ -0,0 +1,13 @@
+/* Test case to check if intrinsics and function specific target
+   optimizations work together.  Check by including x86intrin.h  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -mno-sse4.1 -mno-sse4.2" } */
+
+#include <x86intrin.h>
+
+__attribute__((target("sse4.2")))
+__m128i foo(__m128i *V)
+{
+    return _mm_stream_load_si128(V);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_2.c
new file mode 100644
index 000000000..329ac8864
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_2.c
@@ -0,0 +1,13 @@
+/* Test case to check if intrinsics and function specific target
+   optimizations work together.  Check by including immintrin.h  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -mno-sse4.1" } */
+
+#include <immintrin.h>
+
+__attribute__((target("sse4.2")))
+__m128i foo(__m128i *V)
+{
+    return _mm_stream_load_si128(V);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_3.c
new file mode 100644
index 000000000..e5ea8a967
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_3.c
@@ -0,0 +1,15 @@
+/* Test case to check if intrinsics and function specific target
+   optimizations work together.  Check if the POPCNT specific intrinsics
+   in included with popcntintrin.h get enabled by directly including
+   popcntintrin.h  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -mno-sse4.1 -mno-sse4.2 -mno-popcnt" } */
+
+#include <popcntintrin.h>
+
+__attribute__((target("popcnt")))
+long long foo(unsigned long long X)
+{
+    return _mm_popcnt_u64 (X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_4.c
new file mode 100644
index 000000000..e7c074b31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_4.c
@@ -0,0 +1,21 @@
+/* Test case to check if AVX intrinsics and function specific target
+   optimizations work together.  Check by including immintrin.h  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -mno-avx" } */
+
+#include <immintrin.h>
+
+__m256 a[10], b[10], c[10];
+void __attribute__((target ("avx")))
+foo (void)
+{
+  a[0] = _mm256_and_ps (b[0], c[0]);
+}
+
+/* Try again with a combination of target and optimization attributes.  */
+void __attribute__((target ("avx"), optimize(3)))
+bar (void)
+{
+  a[0] = _mm256_and_ps (b[0], c[0]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_5.c
new file mode 100644
index 000000000..e4486b17a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_5.c
@@ -0,0 +1,16 @@
+/* Test case to check if intrinsics and function specific target
+   optimizations work together.  Check if an error is issued in
+   -O2 mode when foo calls an intrinsic without the right target
+   attribute.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -mno-sse4.1 -mno-sse4.2" } */
+
+#include <smmintrin.h>
+
+__m128i foo(__m128i *V)
+{
+    return _mm_stream_load_si128(V); /* { dg-error "called from here" } */
+}
+
+/* { dg-prune-output ".*inlining failed.*" }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_6.c
new file mode 100644
index 000000000..eea22bb79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/intrinsics_6.c
@@ -0,0 +1,16 @@
+/* Test case to check if intrinsics and function specific target
+   optimizations work together.  Check if an error is issued in
+   -O0 mode when foo calls an intrinsic without the right target
+   attribute.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse -mno-sse4.1 -mno-sse4.2" } */
+
+#include <smmintrin.h>
+
+__m128i foo(__m128i *V)
+{
+    return _mm_stream_load_si128(V); /* { dg-error "called from here" } */
+}
+
+/* { dg-prune-output ".*inlining failed.*" }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-1.c
new file mode 100644
index 000000000..d98c14ffb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if !defined __SSE4_1__
+  abort ();
+#endif
+#if !defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __AVX__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-10.c
new file mode 100644
index 000000000..5f57be913
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-10.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -mfma4 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-11.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-11.c
new file mode 100644
index 000000000..64755b099
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-11.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -mfma4 -mno-ssse3" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-12.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-12.c
new file mode 100644
index 000000000..fde84a21a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-12.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -mfma4 -mno-sse3" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-13.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-13.c
new file mode 100644
index 000000000..74e37d92d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-13.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -mfma4 -mno-sse2" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if defined __SSE2__
+  abort ();
+#endif
+#if defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-14.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-14.c
new file mode 100644
index 000000000..5d49e6e77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-14.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse4a -mfma4 -mno-sse" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if defined __SSE__
+  abort ();
+#endif
+#if defined __SSE2__
+  abort ();
+#endif
+#if defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-2.c
new file mode 100644
index 000000000..aa8958c93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse4 -mfma4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if !defined __SSE4_1__
+  abort ();
+#endif
+#if !defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if !defined __AVX__
+  abort ();
+#endif
+#if !defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-3.c
new file mode 100644
index 000000000..a4d93f4bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-march=x86-64 -msse4 -mfma4 -msse4a" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if !defined __SSE4_1__
+  abort ();
+#endif
+#if !defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if !defined __AVX__
+  abort ();
+#endif
+#if !defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-4.c
new file mode 100644
index 000000000..0137257c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-4.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-march=core2 -mfma4 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __AVX__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-5.c
new file mode 100644
index 000000000..39d065e68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-5.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-march=core2 -msse4a -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __AVX__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-6.c
new file mode 100644
index 000000000..a9a0ddb14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-6.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */
+/* { dg-options "-march=amdfam10 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __AVX__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-7.c
new file mode 100644
index 000000000..8dd628e92
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-7.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -mfma4 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __AVX__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-8.c
new file mode 100644
index 000000000..2ffd80fba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-8.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -mfma4 -mno-sse4a" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if !defined __SSSE3__
+  abort ();
+#endif
+#if !defined __SSE4_1__
+  abort ();
+#endif
+#if !defined __SSE4_2__
+  abort ();
+#endif
+#if defined __SSE4A__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-9.c
new file mode 100644
index 000000000..b312be11e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-9.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */
+/* { dg-options "-march=amdfam10 -mno-fma4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+  abort ();
+#endif
+#if !defined __SSE2__
+  abort ();
+#endif
+#if !defined __SSE3__
+  abort ();
+#endif
+#if defined __SSSE3__
+  abort ();
+#endif
+#if defined __SSE4_1__
+  abort ();
+#endif
+#if defined __SSE4_2__
+  abort ();
+#endif
+#if !defined __SSE4A__
+  abort ();
+#endif
+#if defined __FMA4__
+  abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-check.h
new file mode 100644
index 000000000..8ddbf4dfc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/isa-check.h
@@ -0,0 +1,85 @@
+#include "cpuid.h"
+
+extern void exit (int) __attribute__((noreturn));
+
+/* Determine what instruction set we've been compiled for,
+   and detect that we're running with it.  */
+static void __attribute__((constructor))
+check_isa (void)
+{
+  int a, b, c, d;
+  int c1, d1, c1e, d1e;
+
+  c1 = d1 = c1e = d1e = 0;
+
+#ifdef __MMX__
+  d1 |= bit_MMX;
+#endif
+#ifdef __3dNOW__
+  d1e |= bit_3DNOW;
+#endif
+#ifdef __3dNOW_A__
+  d1e |= bit_3DNOWP;
+#endif
+#ifdef __SSE__
+  d1 |= bit_SSE;
+#endif
+#ifdef __SSE2__
+  d1 |= bit_SSE2;
+#endif
+#ifdef __SSE3__
+  c1 |= bit_SSE3;
+#endif
+#ifdef __SSSE3__
+  c1 |= bit_SSSE3;
+#endif
+#ifdef __SSE4_1__
+  c1 |= bit_SSE4_1;
+#endif
+#ifdef __SSE4_2__
+  c1 |= bit_SSE4_2;
+#endif
+#ifdef __AES__
+  c1 |= bit_AES;
+#endif
+#ifdef __PCLMUL__
+  c1 |= bit_PCLMUL;
+#endif
+#ifdef __AVX__
+  c1 |= bit_AVX;
+#endif
+#ifdef __FMA__
+  c1 |= bit_FMA;
+#endif
+#ifdef __SSE4A__
+  c1e |= bit_SSE4a;
+#endif
+#ifdef __FMA4__
+  c1e |= bit_FMA4;
+#endif
+#ifdef __XOP__
+  c1e |= bit_XOP;
+#endif
+#ifdef __LWP__
+  c1e |= bit_LWP;
+#endif
+
+  if (c1 | d1)
+    {
+      if (!__get_cpuid (1, &a, &b, &c, &d))
+	goto fail;
+      if ((c & c1) != c1 || (d & d1) != d1)
+	goto fail;
+    }
+  if (c1e | d1e)
+    {
+      if (!__get_cpuid (0x80000001, &a, &b, &c, &d))
+	goto fail;
+      if ((c & c1e) != c1e || (d & d1e) != d1e)
+	goto fail;
+    }
+  return;
+
+ fail:
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_1.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_1.h
new file mode 100644
index 000000000..4a0fd6e00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_1.h
@@ -0,0 +1,133 @@
+
+#ifndef l_fma_1
+#define l_fma_1
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * a[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * a[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * a[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * a[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * a[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * a[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * a[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * a[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * a[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * a[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * a[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * a[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] - b[i];
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_2.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_2.h
new file mode 100644
index 000000000..fd64b61fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_2.h
@@ -0,0 +1,133 @@
+
+#ifndef l_fma_2
+#define l_fma_2
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * a[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * a[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * a[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * a[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * a[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * a[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * a[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * a[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * a[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * a[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * a[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * a[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * a[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * a[i] - c[i];
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_3.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_3.h
new file mode 100644
index 000000000..226af24a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_3.h
@@ -0,0 +1,133 @@
+
+#ifndef l_fma_3
+#define l_fma_3
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * b[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * b[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * b[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * b[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * b[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * b[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * b[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * b[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * b[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * b[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * b[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * b[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] - a[i];
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_4.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_4.h
new file mode 100644
index 000000000..e33fe25ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_4.h
@@ -0,0 +1,133 @@
+
+#ifndef l_fma_4
+#define l_fma_4
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * b[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * b[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * b[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * b[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * b[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * b[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * b[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * b[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * b[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * b[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * b[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * b[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * b[i] - c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] + c[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * b[i] - c[i];
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_5.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_5.h
new file mode 100644
index 000000000..a754812e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_5.h
@@ -0,0 +1,133 @@
+
+#ifndef l_fma_5
+#define l_fma_5
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * c[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * c[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * c[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * c[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * c[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * c[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * c[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * c[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * c[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * c[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * c[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * c[i] - a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] + a[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] - a[i];
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_6.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_6.h
new file mode 100644
index 000000000..39be29ad3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_6.h
@@ -0,0 +1,133 @@
+
+#ifndef l_fma_6
+#define l_fma_6
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * c[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) + c[i]) * c[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * c[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) + c[i]) * c[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * c[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = ((a[i] * b[i]) - c[i]) * c[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * c[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_noneg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -((a[i] * b[i]) - c[i]) * c[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * c[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) + c[i]) * c[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_add_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) + c[i]) * c[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * c[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_noneg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = (-(a[i] * b[i]) - c[i]) * c[i] - b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_add (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] + b[i];
+}
+
+void __attribute__((sseregparm))
+test_neg_sub_neg_sub (TYPE *a, TYPE *b, TYPE *c, TYPE *d, int n)
+{
+  int i;
+  for (i = 0; i < n; i++)
+    d[i] = -(-(a[i] * b[i]) - c[i]) * c[i] - b[i];
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_1.c
new file mode 100644
index 000000000..1d99b4caa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+typedef double adouble __attribute__((aligned(sizeof (double))));
+#define TYPE adouble
+
+#include "l_fma_1.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_2.c
new file mode 100644
index 000000000..e10110006
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+typedef double adouble __attribute__((aligned(sizeof (double))));
+#define TYPE adouble
+
+#include "l_fma_2.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_3.c
new file mode 100644
index 000000000..f099e25f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+typedef double adouble __attribute__((aligned(sizeof (double))));
+#define TYPE adouble
+
+#include "l_fma_3.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_4.c
new file mode 100644
index 000000000..969f31c7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+typedef double adouble __attribute__((aligned(sizeof (double))));
+#define TYPE adouble
+
+#include "l_fma_4.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_5.c
new file mode 100644
index 000000000..85ccdd0da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+typedef double adouble __attribute__((aligned(sizeof (double))));
+#define TYPE adouble
+
+#include "l_fma_5.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_6.c
new file mode 100644
index 000000000..019ed9ad0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_double_6.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+typedef double adouble __attribute__((aligned(sizeof (double))));
+#define TYPE adouble
+
+#include "l_fma_6.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+pd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+sd" 56 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+sd" 56 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_1.c
new file mode 100644
index 000000000..d1913d768
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_1.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_2.c
new file mode 100644
index 000000000..5e0142545
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_2.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_3.c
new file mode 100644
index 000000000..7b9e3f545
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_3.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_4.c
new file mode 100644
index 000000000..cc675c14a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_4.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_4.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_5.c
new file mode 100644
index 000000000..ac0b36147
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_5.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_5.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_6.c
new file mode 100644
index 000000000..c84ac1196
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_float_6.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma -mtune=generic" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_6.h"
+
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ps" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfmsub\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmadd\[123\]+ss" 120 } } */
+/* { dg-final { scan-assembler-times "vfnmsub\[123\]+ss" 120 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_main.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_main.h
new file mode 100644
index 000000000..a9dc5cd20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_main.h
@@ -0,0 +1,100 @@
+
+#ifndef l_fma_main
+#define l_fma_main
+
+#if DEBUG
+#include <stdio.h>
+#endif
+
+TYPE m1[32] = {
+		1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16,
+	       17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32
+	      };
+TYPE m2[32] = {
+		2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 17,
+	       18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33
+	      };
+TYPE m3[32] = {
+		3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 
+	       19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
+	      };
+TYPE m4[32];
+int test_fails = 0;
+
+void
+compare_result(char *title, TYPE *res)
+{
+  int i;
+  int good = 1;
+  for (i =0; i < 32; i++)
+    if (m4[i] != res[i])
+      {
+        if (good)
+          {
+#if DEBUG
+             printf ("!!!! %s miscompare\n", title);
+#endif
+             good = 0;
+          }
+#if DEBUG
+        printf ("res[%d] = %d, must be %d\n", i, (int)res[i], (int) m4[i]);
+#endif
+      }
+  if (!good)
+    test_fails = 1;
+}
+
+static void fma_test ()
+{
+  test_noneg_add_noneg_add (m1, m2, m3, m4, 32);
+  compare_result ("test0000", res_test0000);
+
+  test_noneg_add_noneg_sub (m1, m2, m3, m4, 32);
+  compare_result ("test0001", res_test0001);
+
+  test_noneg_add_neg_add (m1, m2, m3, m4, 32);
+  compare_result ("test0010", res_test0010);
+
+  test_noneg_add_neg_sub (m1, m2, m3, m4, 32);
+  compare_result ("test0011", res_test0011);
+
+  test_noneg_sub_noneg_add (m1, m2, m3, m4, 32);
+  compare_result ("test0100", res_test0100);
+
+  test_noneg_sub_noneg_sub (m1, m2, m3, m4, 32);
+  compare_result ("test0101", res_test0101);
+
+  test_noneg_sub_neg_add (m1, m2, m3, m4, 32);
+  compare_result ("test0110", res_test0110);
+
+  test_noneg_sub_neg_sub (m1, m2, m3, m4, 32);
+  compare_result ("test0111", res_test0111);
+
+  test_neg_add_noneg_add (m1, m2, m3, m4, 32);
+  compare_result ("test1000", res_test1000);
+
+  test_neg_add_noneg_sub (m1, m2, m3, m4, 32);
+  compare_result ("test1001", res_test1001);
+
+  test_neg_add_neg_add (m1, m2, m3, m4, 32);
+  compare_result ("test1010", res_test1010);
+
+  test_neg_add_neg_sub (m1, m2, m3, m4, 32);
+  compare_result ("test1011", res_test1011);
+
+  test_neg_sub_noneg_add (m1, m2, m3, m4, 32);
+  compare_result ("test1100", res_test1100);
+
+  test_neg_sub_noneg_sub (m1, m2, m3, m4, 32);
+  compare_result ("test1101", res_test1101);
+
+  test_neg_sub_neg_add (m1, m2, m3, m4, 32);
+  compare_result ("test1110", res_test1110);
+
+  test_neg_sub_neg_sub (m1, m2, m3, m4, 32);
+  compare_result ("test1111", res_test1111);
+
+  if (test_fails) abort ();
+}
+
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c
new file mode 100644
index 000000000..f1d3c3a6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_1.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "l_fma_1.h"
+
+#include "fma_run_double_results_1.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c
new file mode 100644
index 000000000..db85598c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_2.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "l_fma_2.h"
+
+#include "fma_run_double_results_2.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c
new file mode 100644
index 000000000..8043f6fbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_3.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "l_fma_3.h"
+
+#include "fma_run_double_results_3.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c
new file mode 100644
index 000000000..eef05f58c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_4.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "l_fma_4.h"
+
+#include "fma_run_double_results_4.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c
new file mode 100644
index 000000000..95b4b66d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_5.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "l_fma_5.h"
+
+#include "fma_run_double_results_5.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c
new file mode 100644
index 000000000..24c1a78cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_double_6.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE double
+
+#include "l_fma_6.h"
+
+#include "fma_run_double_results_6.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c
new file mode 100644
index 000000000..8a046131d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_1.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_1.h"
+
+#include "fma_run_float_results_1.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c
new file mode 100644
index 000000000..ea6df76f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_2.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_2.h"
+
+#include "fma_run_float_results_2.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c
new file mode 100644
index 000000000..5789867d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_3.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_3.h"
+
+#include "fma_run_float_results_3.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c
new file mode 100644
index 000000000..377370b89
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_4.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_4.h"
+
+#include "fma_run_float_results_4.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c
new file mode 100644
index 000000000..8b0cf3f0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_5.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_5.h"
+
+#include "fma_run_float_results_5.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c
new file mode 100644
index 000000000..1300618da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/l_fma_run_float_6.c
@@ -0,0 +1,15 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fma } */
+/* { dg-options "-O3 -Wno-attributes -mfpmath=sse -mfma" } */
+
+/* Test that the compiler properly optimizes floating point multiply
+   and add instructions into FMA3 instructions.  */
+
+#define TYPE float
+
+#include "l_fma_6.h"
+
+#include "fma_run_float_results_6.h"
+
+#include "fma-check.h"
+#include "l_fma_main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/large-frame.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/large-frame.c
new file mode 100644
index 000000000..2b6df1f6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/large-frame.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-final { scan-assembler "-429496" } } */
+extern void dump (int *buf, int a);
+
+void func (int a)
+{
+  int bigbuf[1 << 30];
+  dump (bigbuf, a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/large-size-array-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/large-size-array-3.c
new file mode 100644
index 000000000..07c877a93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/large-size-array-3.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mcmodel=medium" } */
+/* { dg-final { scan-assembler "8589934588" } } */
+int bigarray[2147483647];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lea.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lea.c
new file mode 100644
index 000000000..bba345ef0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lea.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=pentiumpro" } } */
+/* { dg-options "-O2 -march=pentiumpro" } */
+/* { dg-final { scan-assembler "leal" } } */
+typedef struct {
+  char **visbuf;
+  char **allbuf;
+} TScreen;
+
+void
+VTallocbuf(TScreen *screen, unsigned long savelines)
+{
+  screen->visbuf = &screen->allbuf[savelines];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/local.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/local.c
new file mode 100644
index 000000000..4423001f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/local.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -funit-at-a-time" } */
+/* { dg-final { scan-assembler "magic\[^\\n\]*eax" { target ia32 } } } */
+/* { dg-final { scan-assembler "magic\[^\\n\]*(edi|ecx)" { target { ! { ia32 } } } } } */
+
+/* Verify that local calling convention is used.  */
+static t(int) __attribute__ ((noinline));
+extern volatile int i;
+
+void m(void)
+{
+	t(i);
+}
+
+static t(int a)
+{
+	asm("magic %0"::"g"(a));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-1.c
new file mode 100644
index 000000000..cbd9bb5ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-128" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-2.c
new file mode 100644
index 000000000..9aef4bf0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */
+/* { dg-options "-O2 -mbionic" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-3.c
new file mode 100644
index 000000000..86b9b12e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */
+/* { dg-options "-O2 -mandroid" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-4.c
new file mode 100644
index 000000000..af7363581
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-4.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */
+/* { dg-options "-O2 -mlong-double-128 -mbionic" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-5.c
new file mode 100644
index 000000000..fb32c5b7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-5.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */
+/* { dg-options "-O2 -mlong-double-128 -mandroid" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-6.c
new file mode 100644
index 000000000..279751620
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-6.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-64 -mlong-double-128" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-7.c
new file mode 100644
index 000000000..eaa7f6302
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-7.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-64" } */
+
+__float128
+foo (__float128 x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-8.c
new file mode 100644
index 000000000..d869efc43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-8.c
@@ -0,0 +1,11 @@
+/* { dg-do run } */
+/* { dg-options "-O0 -mlong-double-64 -mfpmath=387" } */
+
+int
+main ()
+{
+  __float128 a = -0.23456789;
+  if ((double) a >= 0)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-9.c
new file mode 100644
index 000000000..bc90f2177
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-128-9.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-options "-O0 -mlong-double-64 -mfpmath=sse -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+static void
+sse2_test (void)
+{
+  __float128 a = -0.23456789;
+  if ((double) a >= 0)
+    __builtin_abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-1.c
new file mode 100644
index 000000000..f5c83a585
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-64" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-2.c
new file mode 100644
index 000000000..13a7be08b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { *-*-linux* && ia32 } } } */
+/* { dg-options "-O2 -mbionic" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-3.c
new file mode 100644
index 000000000..99d3d5ffc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { *-*-linux* && ia32 } } } */
+/* { dg-options "-O2 -mandroid" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-4.c
new file mode 100644
index 000000000..471f0bf72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-4.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-80 -mlong-double-64" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-5.c
new file mode 100644
index 000000000..f634425eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-5.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-128 -mlong-double-64" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-6.c
new file mode 100644
index 000000000..76b030d0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-6.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-80 -mlong-double-128 -mlong-double-64" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-7.c
new file mode 100644
index 000000000..9f66d37e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-7.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-128 -mlong-double-80 -mlong-double-64" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-8.c
new file mode 100644
index 000000000..fd2fdbc10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-8.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mlong-double-64 -mbionic" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-9.c
new file mode 100644
index 000000000..595dba358
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-64-9.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mlong-double-64 -mandroid" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler-not "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-1.c
new file mode 100644
index 000000000..887bd6c9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-80" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-10.c
new file mode 100644
index 000000000..311ae4f40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-10.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-128 -mlong-double-64 -mlong-double-80" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-2.c
new file mode 100644
index 000000000..7ca064394
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mlong-double-80 -mbionic" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-3.c
new file mode 100644
index 000000000..39dc8a450
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target *-*-linux* } } */
+/* { dg-options "-O2 -mlong-double-80 -mandroid" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-4.c
new file mode 100644
index 000000000..4ee21b662
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-4.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-64 -mlong-double-80" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-5.c
new file mode 100644
index 000000000..78a16037e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-5.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-64" } */
+
+__float80
+foo (__float80 x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-6.c
new file mode 100644
index 000000000..a395a2659
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-6.c
@@ -0,0 +1,11 @@
+/* { dg-do run } */
+/* { dg-options "-O0 -mlong-double-64 -mfpmath=387" } */
+
+int
+main ()
+{
+  __float80 a = -0.23456789;
+  if ((double) a >= 0)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-7.c
new file mode 100644
index 000000000..e6f9cbebe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-7.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-options "-O0 -mlong-double-64 -mfpmath=sse -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+static void
+sse2_test (void)
+{
+  __float80 a = -0.23456789;
+  if ((double) a >= 0)
+    __builtin_abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-8.c
new file mode 100644
index 000000000..b82305ffb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-8.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-128 -mlong-double-80" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-9.c
new file mode 100644
index 000000000..91ff9d10e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/long-double-80-9.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-double-64 -mlong-double-128 -mlong-double-80" } */
+
+long double
+foo (long double x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fldt" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?__multf3" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-1.c
new file mode 100644
index 000000000..1af62f284
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-1.c
@@ -0,0 +1,106 @@
+/* PR optimization/9888 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mtune=k6 -O3" } */
+
+/* Verify that GCC doesn't emit out of range 'loop' instructions.  */
+
+extern void abort (void);
+extern void exit (int);
+
+   
+f1 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (--a == -1)
+	return i;
+    }
+  return -1;
+}
+
+f2 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (--a != -1)
+	return i;
+    }
+  return -1;
+}
+
+f3 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (--a == 0)
+	return i;
+    }
+  return -1;
+}
+
+f4 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (--a != 0)
+	return i;
+    }
+  return -1;
+}
+
+f5 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (++a == 0)
+	return i;
+    }
+  return -1;
+}
+
+f6 (a)
+     long a;
+{
+  int i;
+  for (i = 0; i < 10; i++)
+    {
+      if (++a != 0)
+	return i;
+    }
+  return -1;
+}
+
+
+int main()
+{
+  if (f1 (5L) != 5)
+    abort ();
+  if (f2 (1L) != 0)
+    abort ();
+  if (f2 (0L) != 1)
+    abort ();
+  if (f3 (5L) != 4)
+    abort ();
+  if (f4 (1L) != 1)
+    abort ();
+  if (f4 (0L) != 0)
+    abort ();
+  if (f5 (-5L) != 4)
+    abort ();
+  if (f6 (-1L) != 1)
+    abort ();
+  if (f6 (0L) != 0)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-2.c
new file mode 100644
index 000000000..eec71636e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-2.c
@@ -0,0 +1,81 @@
+/* PR optimization/9888 */
+/* Originator: Jim Bray <jb@as220.org> */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mtune=k6 -Os" } */
+
+enum reload_type
+{
+  RELOAD_FOR_INPUT, RELOAD_FOR_OUTPUT, RELOAD_FOR_INSN,
+  RELOAD_FOR_INPUT_ADDRESS, RELOAD_FOR_INPADDR_ADDRESS,
+  RELOAD_FOR_OUTPUT_ADDRESS, RELOAD_FOR_OUTADDR_ADDRESS,
+  RELOAD_FOR_OPERAND_ADDRESS, RELOAD_FOR_OPADDR_ADDR,
+  RELOAD_OTHER, RELOAD_FOR_OTHER_ADDRESS
+};
+
+#define FOO_SIZE 3
+
+/* My results, varying with FOO_SIZE:
+   30: asm error "value of ..fff77 too large:
+   3 to 29: ....ff7d...
+   1 to 2: no error.  */
+
+struct reload
+{
+   int foo[FOO_SIZE];
+   int opnum; 
+   enum reload_type when_needed;
+   unsigned int optional:1; 
+   unsigned int secondary_p:1;
+};
+
+#define N_RELOADS  2
+
+struct reload rld[N_RELOADS];
+int n_reloads = N_RELOADS;
+
+int main(void)
+{
+  int i;
+
+  enum reload_type operand_type[1];
+
+  enum reload_type address_type[1];
+
+  int operand_reloadnum[1];
+  int goal_alternative_matches[1];
+
+  for (i = 0; i < n_reloads; i++)
+    {
+      if (rld[i].secondary_p
+          && rld[i].when_needed == operand_type[rld[i].opnum])
+        rld[i].when_needed = address_type[rld[i].opnum];
+
+      if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
+           || rld[i].when_needed == RELOAD_FOR_OUTPUT_ADDRESS
+           || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
+           || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
+          && (operand_reloadnum[rld[i].opnum] < 0
+              || rld[operand_reloadnum[rld[i].opnum]].optional))
+        {
+
+          if (rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS
+              || rld[i].when_needed == RELOAD_FOR_OUTADDR_ADDRESS)
+            rld[i].when_needed = RELOAD_FOR_OPADDR_ADDR;
+          else
+            rld[i].when_needed = RELOAD_FOR_OPERAND_ADDRESS;
+        }
+
+      if ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
+           || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
+          && operand_reloadnum[rld[i].opnum] >= 0
+          && (rld[operand_reloadnum[rld[i].opnum]].when_needed
+              == RELOAD_OTHER))
+        rld[i].when_needed = RELOAD_FOR_OTHER_ADDRESS;
+
+      if (goal_alternative_matches[rld[i].opnum] >= 0)
+        rld[i].opnum = goal_alternative_matches[rld[i].opnum];
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-3.c
new file mode 100644
index 000000000..4fcd39072
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/loop-3.c
@@ -0,0 +1,80 @@
+/* PR target/11044 */
+/* Originator: Tim McGrath <misty-@charter.net> */
+/* Testcase contributed by Eric Botcazou <ebotcazou@libertysurf.fr> */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mtune=k6 -O3 -ffast-math -funroll-loops" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+extern void abort (void);
+
+typedef struct
+{
+        unsigned char colormod;
+} entity_state_t;
+
+typedef struct
+{
+        int num_entities;
+        entity_state_t *entities;
+} packet_entities_t;
+
+typedef struct
+{
+        double senttime;
+        float ping_time;
+        packet_entities_t entities;
+} client_frame_t;
+
+typedef enum
+{
+        cs_free,
+        cs_server,
+        cs_zombie,
+        cs_connected,
+        cs_spawned
+} sv_client_state_t;
+
+typedef struct client_s
+{
+        sv_client_state_t state;
+        int ping;
+        client_frame_t frames[64];
+} client_t;
+
+int CalcPing (client_t *cl)
+{
+        float ping;
+        int count, i;
+        register client_frame_t *frame;
+
+        if (cl->state == cs_server)
+                return cl->ping;
+        ping = 0;
+        count = 0;
+        for (frame = cl->frames, i = 0; i < 64; i++, frame++) {
+                if (frame->ping_time > 0) {
+                        ping += frame->ping_time;
+                        count++;
+                }
+        }
+        if (!count)
+                return 9999;
+        ping /= count;
+
+        return ping * 1000;
+}
+
+int main(void)
+{
+   client_t cl;
+
+   memset(&cl, 0, sizeof(cl));
+
+   cl.frames[0].ping_time = 1.0f;
+
+   if (CalcPing(&cl) != 1000)
+     abort();
+
+   return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-1.c
new file mode 100644
index 000000000..f6240d1ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlzcnt " } */
+/* { dg-final { scan-assembler "lzcntw\[^\\n]*(%|)ax" } } */
+
+#include <x86intrin.h>
+
+unsigned int
+func_lzcnt16 (unsigned int X)
+{
+  return __lzcnt16(X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-2.c
new file mode 100644
index 000000000..329a11f97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-2.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { lzcnt } } } */
+/* { dg-options "-O2 -mlzcnt -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "lzcnt-check.h"
+
+short calc_lzcnt_u16 (short src)
+{
+  int i;
+  short res = 0;
+
+  while ((res < 16) && (((src >> (15 - res)) & 1) == 0))
+    ++res;
+
+  return res;
+}
+
+static void
+lzcnt_test ()
+{
+  unsigned i;
+  short src = 0x7ace;
+  short res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = src >> i;
+
+    res_ref = calc_lzcnt_u16 (src);
+    res = __lzcnt16 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-2a.c
new file mode 100644
index 000000000..fe1069fee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-2a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlzcnt" } */
+
+#include "lzcnt-2.c"
+
+/* { dg-final { scan-assembler "lzcntw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-3.c
new file mode 100644
index 000000000..147795117
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mlzcnt " } */
+/* { dg-final { scan-assembler "lzcntl\[^\\n]*(%|)eax" } } */
+
+#include <x86intrin.h>
+
+unsigned int
+func_lzcnt32 (unsigned int X)
+{
+  return __lzcnt32(X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-4.c
new file mode 100644
index 000000000..20653265b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-4.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { lzcnt } } } */
+/* { dg-options "-O2 -mlzcnt -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "lzcnt-check.h"
+
+int calc_lzcnt_u32 (int src)
+{
+  int i;
+  int res = 0;
+
+  while ((res < 32) && (((src >> (31 - res)) & 1) == 0))
+    ++res;
+
+  return res;
+}
+
+static void
+lzcnt_test ()
+{
+  unsigned i;
+  int src = 0xce7ace0;
+  int res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = src >> i;
+
+    res_ref = calc_lzcnt_u32 (src);
+    res = __lzcnt32 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-4a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-4a.c
new file mode 100644
index 000000000..6bba6a97d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-4a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlzcnt" } */
+
+#include "lzcnt-4.c"
+
+/* { dg-final { scan-assembler "lzcntl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-5.c
new file mode 100644
index 000000000..a4b9aafcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-5.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mlzcnt" } */
+/* { dg-final { scan-assembler "lzcntq\[^\\n]*(%|)rax" } } */
+
+#include <x86intrin.h>
+
+unsigned int
+func_lzcnt64 (unsigned long long X)
+{
+  return __lzcnt64(X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-6.c
new file mode 100644
index 000000000..f0bf5dab0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-6.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { lzcnt && { ! ia32 } } } } */
+/* { dg-options "-O2 -mlzcnt -fno-inline" } */
+
+#include <x86intrin.h>
+
+#include "lzcnt-check.h"
+
+long long calc_lzcnt_u64 (long long src)
+{
+  int i;
+  int res = 0;
+
+  while ((res < 64) && (((src >> (63 - res)) & 1) == 0))
+    ++res;
+
+  return res;
+}
+
+static void
+lzcnt_test ()
+{
+  unsigned i;
+  long long src = 0xce7ace0ce7ace0;
+  long long res, res_ref;
+
+  for (i=0; i<5; ++i) {
+    src = src >> i;
+
+    res_ref = calc_lzcnt_u64 (src);
+    res = __lzcnt64 (src);
+
+    if (res != res_ref)
+      abort();
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-6a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-6a.c
new file mode 100644
index 000000000..209009344
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-6a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mlzcnt" } */
+
+#include "lzcnt-6.c"
+
+/* { dg-final { scan-assembler "lzcntq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-check.h
new file mode 100644
index 000000000..8aad834d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/lzcnt-check.h
@@ -0,0 +1,37 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void lzcnt_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  lzcnt_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run LZCNT test only if host has LZCNT support.  */
+  if (ecx & bit_LZCNT)
+    {
+      do_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/m128-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/m128-check.h
new file mode 100644
index 000000000..98dc26998
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/m128-check.h
@@ -0,0 +1,191 @@
+#include <stdio.h>
+#include <xmmintrin.h>
+
+#ifdef __SSE2__
+#include <emmintrin.h>
+
+typedef union
+{
+  __m128i x;
+  char a[16];
+} union128i_b;
+
+typedef union
+{
+  __m128i x;
+  unsigned char a[16];
+} union128i_ub;
+
+typedef union
+{
+  __m128i x;
+  short a[8];
+} union128i_w;
+
+typedef union
+{
+  __m128i x;
+  unsigned short a[8];
+} union128i_uw;
+
+typedef union
+{
+  __m128i x;
+  int a[4];
+} union128i_d;
+
+typedef union
+{
+  __m128i x;
+  long long a[2];
+} union128i_q;
+
+typedef union
+{
+  __m128d x;
+  double a[2];
+} union128d;
+#endif
+
+typedef union
+{
+  __m128  x;
+  float a[4];
+} union128;
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(A) (sizeof (A) / sizeof ((A)[0]))
+#endif
+
+#ifdef DEBUG
+#define PRINTF printf
+#else
+#define PRINTF(...)	
+#endif
+
+#define CHECK_EXP(UINON_TYPE, VALUE_TYPE, FMT)		\
+static int						\
+__attribute__((noinline, unused))			\
+check_##UINON_TYPE (UINON_TYPE u, const VALUE_TYPE *v)	\
+{							\
+  int i;						\
+  int err = 0;						\
+							\
+  for (i = 0; i < ARRAY_SIZE (u.a); i++)		\
+    if (u.a[i] != v[i])					\
+      {							\
+	err++;						\
+	PRINTF ("%i: " FMT " != " FMT "\n",		\
+		i, v[i], u.a[i]);			\
+      }							\
+  return err;						\
+}
+
+#ifdef __SSE2__
+CHECK_EXP (union128i_b, char, "%d")
+CHECK_EXP (union128i_ub, unsigned char, "%d")
+CHECK_EXP (union128i_w, short, "%d")
+CHECK_EXP (union128i_uw, unsigned short, "%d")
+CHECK_EXP (union128i_d, int, "0x%x")
+CHECK_EXP (union128i_q, long long, "0x%llx")
+CHECK_EXP (union128d, double, "%f")
+#endif
+
+CHECK_EXP (union128, float, "%f")
+
+#define ESP_FLOAT 0.000001
+#define ESP_DOUBLE 0.000001
+#define CHECK_ARRAY(ARRAY, TYPE, FMT)                   \
+static int                                              \
+__attribute__((noinline, unused))                       \
+checkV##ARRAY (const TYPE *v, const TYPE *e, int n)     \
+{                                                       \
+  int i;                                                \
+  int err = 0;                                          \
+                                                        \
+  for (i = 0; i < n; i++)                               \
+    if (v[i] != e[i])                                   \
+      {                                                 \
+        err++;                                          \
+        PRINTF ("%i: " FMT " != " FMT "\n",             \
+                i, v[i], e[i]);                 \
+      }                                                 \
+  return err;                                           \
+}
+
+CHECK_ARRAY(c, char, "0x%hhx")
+CHECK_ARRAY(s, short, "0x%hx")
+CHECK_ARRAY(i, int, "0x%x")
+CHECK_ARRAY(l, long long, "0x%llx")
+
+#define CHECK_FP_ARRAY(ARRAY, TYPE, ESP, FMT)                   \
+static int                                              \
+__attribute__((noinline, unused))                       \
+checkV##ARRAY (const TYPE *v, const TYPE *e, int n)     \
+{                                                       \
+  int i;                                                \
+  int err = 0;                                          \
+                                                        \
+  for (i = 0; i < n; i++)                               \
+    if (v[i] > (e[i] + (ESP)) || v[i] < (e[i] - (ESP))) \
+    if (e[i] != v[i])                                   \
+      {                                                 \
+        err++;                                          \
+        PRINTF ("%i: " FMT " != " FMT "\n",             \
+                i, v[i], e[i]);                 \
+      }                                                 \
+  return err;                                           \
+}
+
+CHECK_FP_ARRAY (d, double, ESP_DOUBLE, "%f")
+CHECK_FP_ARRAY (f, float, ESP_FLOAT, "%f")
+
+#ifdef NEED_IEEE754_FLOAT
+union ieee754_float
+{
+   float d;
+   struct 
+   {
+      unsigned long frac : 23;
+      unsigned exp : 8;
+      unsigned sign : 1;
+   } bits __attribute__((packed));
+};
+#endif
+
+#ifdef NEED_IEEE754_DOUBLE
+union ieee754_double
+{
+   double d;
+   struct 
+   {
+      unsigned long frac1 : 32;
+      unsigned long frac0 : 20;
+      unsigned exp : 11;
+      unsigned sign : 1;
+   } bits __attribute__((packed));
+};
+#endif
+
+#define CHECK_FP_EXP(UINON_TYPE, VALUE_TYPE, ESP, FMT)		\
+static int							\
+__attribute__((noinline, unused))				\
+check_fp_##UINON_TYPE (UINON_TYPE u, const VALUE_TYPE *v)	\
+{								\
+  int i;							\
+  int err = 0;							\
+								\
+  for (i = 0; i < ARRAY_SIZE (u.a); i++)			\
+    if (u.a[i] > (v[i] + (ESP)) || u.a[i] < (v[i] - (ESP)))	\
+      {								\
+	err++;							\
+	PRINTF ("%i: " FMT " != " FMT "\n",			\
+		i, v[i], u.a[i]);				\
+      }								\
+  return err;							\
+}
+
+CHECK_FP_EXP (union128, float, ESP_FLOAT, "%f")
+#ifdef __SSE2__
+CHECK_FP_EXP (union128d, double, ESP_DOUBLE, "%f")
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-1.c
new file mode 100644
index 000000000..a40b9e88f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-1.c
@@ -0,0 +1,63 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <assert.h>
+#include "avx-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m256d n2 = { -93.83, 893.318, 3884.34, -3134.3 };
+__m256i n3 = { 893, -3180, 3334, -3984 };
+int n4 = -30;
+double n5 = 40.3;
+__m128i n6 = { 8931, -13984 };
+__m128d n7 = { 1893.318, -31134.3 };
+__m256 n8 =
+{
+  -913.87, 8193.518, 312884.34, -9134.9,
+  -19093.83, 89312.318, 7884.84, -4134.3
+};
+__m128 n9 = { -1283.3, -213.3, 3213.4, 81119.03 };
+__m128i n10 = { 28131, -313684 };
+int n11 = 103;
+double n12 = -3004.3;
+__m256d n13 = { 913.73, -93.38, 84.34, -734.3 };
+__m128d n14 = { -73.378, 934.31 };
+__m256 n15 =
+{
+  13.73, -8193.318, 384.74, 734.9,
+  193.83, 312.78, 7884.34, -8134.3
+};
+__m128i n16 = { 831, -3849 };
+
+void
+__attribute__((noinline))
+m256_test (__m128 a1, __m256d a2, __m256i a3, int a4, double a5,
+	   __m128i a6, __m128d a7, __m256 a8, __m128 a9, __m128i a10,
+	   int a11, double a12, __m256d a13, __m128d a14, __m256 a15,
+	   __m128i a16)
+{
+  assert (__builtin_memcmp (&a1, &n1, sizeof (a1)) == 0);
+  assert (__builtin_memcmp (&a2, &n2, sizeof (a2)) == 0);
+  assert (__builtin_memcmp (&a3, &n3, sizeof (a3)) == 0);
+  assert (a4 == n4);
+  assert (a5 == n5);
+  assert (__builtin_memcmp (&a6, &n6, sizeof (a6)) == 0);
+  assert (__builtin_memcmp (&a7, &n7, sizeof (a7)) == 0);
+  assert (__builtin_memcmp (&a8, &n8, sizeof (a8)) == 0);
+  assert (__builtin_memcmp (&a9, &n9, sizeof (a9)) == 0);
+  assert (__builtin_memcmp (&a10, &n10, sizeof (a10)) == 0);
+  assert (a11 == n11);
+  assert (a12 == n12);
+  assert (__builtin_memcmp (&a13, &n13, sizeof (a13)) == 0);
+  assert (__builtin_memcmp (&a14, &n14, sizeof (a14)) == 0);
+  assert (__builtin_memcmp (&a15, &n15, sizeof (a15)) == 0);
+  assert (__builtin_memcmp (&a16, &n16, sizeof (a16)) == 0);
+}
+
+static void
+avx_test (void)
+{
+  m256_test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	     n13, n14, n15, n16);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-2.c
new file mode 100644
index 000000000..64e38527d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-2.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <assert.h>
+#include "avx-check.h"
+
+struct m128
+{
+  __m128 v;
+};
+
+struct m256d
+{
+  __m256d v;
+};
+
+struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } };
+struct m256d n2 = { { -93.83, 893.318, 3884.34, -3134.3 } };
+__m256i n3 = { 893, -3180, 3334, -3984 };
+int n4 = -30;
+double n5 = 40.3;
+__m128i n6 = { 8931, -13984 };
+__m128d n7 = { 1893.318, -31134.3 };
+__m256 n8 =
+{
+  -913.87, 8193.518, 312884.34, -9134.9,
+  -19093.83, 89312.318, 7884.84, -4134.3
+};
+__m128 n9 = { -1283.3, -213.3, 3213.4, 81119.03 };
+__m128i n10 = { 28131, -313684 };
+int n11 = 103;
+double n12 = -3004.3;
+struct m256d n13 =  { { 913.73, -93.38, 84.34, -734.3 } };
+__m128d n14 = { -73.378, 934.31 };
+__m256 n15 =
+{
+  13.73, -8193.318, 384.74, 734.9,
+  193.83, 312.78, 7884.34, -8134.3
+};
+__m128i n16 = { 831, -3849 };
+
+void
+__attribute__((noinline))
+m256_test (struct m128 a1, struct m256d a2, __m256i a3, int a4, double a5,
+	   __m128i a6, __m128d a7, __m256 a8, __m128 a9, __m128i a10,
+	   int a11, double a12, struct m256d a13, __m128d a14, __m256 a15,
+	   __m128i a16)
+{
+  assert (__builtin_memcmp (&a1, &n1, sizeof (a1)) == 0);
+  assert (__builtin_memcmp (&a2, &n2, sizeof (a2)) == 0);
+  assert (__builtin_memcmp (&a3, &n3, sizeof (a3)) == 0);
+  assert (a4 == n4);
+  assert (a5 == n5);
+  assert (__builtin_memcmp (&a6, &n6, sizeof (a6)) == 0);
+  assert (__builtin_memcmp (&a7, &n7, sizeof (a7)) == 0);
+  assert (__builtin_memcmp (&a8, &n8, sizeof (a8)) == 0);
+  assert (__builtin_memcmp (&a9, &n9, sizeof (a9)) == 0);
+  assert (__builtin_memcmp (&a10, &n10, sizeof (a10)) == 0);
+  assert (a11 == n11);
+  assert (a12 == n12);
+  assert (__builtin_memcmp (&a13, &n13, sizeof (a13)) == 0);
+  assert (__builtin_memcmp (&a14, &n14, sizeof (a14)) == 0);
+  assert (__builtin_memcmp (&a15, &n15, sizeof (a15)) == 0);
+  assert (__builtin_memcmp (&a16, &n16, sizeof (a16)) == 0);
+}
+
+static void
+avx_test (void)
+{
+  m256_test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	     n13, n14, n15, n16);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-check.h
new file mode 100644
index 000000000..e1843550e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/m256-check.h
@@ -0,0 +1,73 @@
+#include <immintrin.h>
+#include "m128-check.h"
+
+#ifndef max
+#define max(a, b) (((a) > (b)) ? (a):(b))
+#endif
+#ifndef min
+#define min(a, b) (((a) < (b)) ? (a):(b))
+#endif
+
+typedef union
+{
+  __m256i x;
+  char a[32];
+} union256i_b;
+
+typedef union
+{
+  __m256i x;
+  short a[16];
+} union256i_w;
+
+typedef union
+{
+  __m256i x;
+  int a[8];
+} union256i_d;
+
+typedef union
+{
+  __m256i x;
+  long long a[4];
+} union256i_q;
+
+typedef union
+{
+  __m256 x;
+  float a[8];
+} union256;
+
+typedef union
+{
+  __m256d x;
+  double a[4];
+} union256d;
+
+CHECK_EXP (union256i_b, char, "%d")
+CHECK_EXP (union256i_w, short, "%d")
+CHECK_EXP (union256i_d, int, "0x%x")
+CHECK_EXP (union256i_q, long long, "0x%llx")
+CHECK_EXP (union256, float, "%f")
+CHECK_EXP (union256d, double, "%f")
+
+#define CHECK_FP_EXP(UINON_TYPE, VALUE_TYPE, ESP, FMT)		\
+static int							\
+__attribute__((noinline, unused))				\
+check_fp_##UINON_TYPE (UINON_TYPE u, const VALUE_TYPE *v)	\
+{								\
+  int i;							\
+  int err = 0;							\
+								\
+  for (i = 0; i < ARRAY_SIZE (u.a); i++)			\
+    if (u.a[i] > (v[i] + (ESP)) || u.a[i] < (v[i] - (ESP)))	\
+      {								\
+	err++;							\
+	PRINTF ("%i: " FMT " != " FMT "\n",			\
+		i, v[i], u.a[i]);				\
+      }								\
+  return err;							\
+}
+
+CHECK_FP_EXP (union256, float, ESP_FLOAT, "%f")
+CHECK_FP_EXP (union256d, double, ESP_DOUBLE, "%f")
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/m512-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/m512-check.h
new file mode 100644
index 000000000..375b15ade
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/m512-check.h
@@ -0,0 +1,83 @@
+#include <immintrin.h>
+#include "m256-check.h"
+
+typedef union
+{
+  __m512i x;
+  char a[64];
+} union512i_b;
+
+typedef union
+{
+  __m512i x;
+  short a[32];
+} union512i_w;
+
+typedef union
+{
+  __m512i x;
+  int a[16];
+} union512i_d;
+
+typedef union
+{
+  __m512i x;
+  long long a[8];
+} union512i_q;
+
+typedef union
+{
+  __m512 x;
+  float a[16];
+} union512;
+
+typedef union
+{
+  __m512d x;
+  double a[8];
+} union512d;
+
+CHECK_EXP (union512i_b, char, "%d")
+CHECK_EXP (union512i_w, short, "%d")
+CHECK_EXP (union512i_d, int, "0x%x")
+CHECK_EXP (union512i_q, long long, "0x%llx")
+CHECK_EXP (union512, float, "%f")
+CHECK_EXP (union512d, double, "%f")
+
+CHECK_FP_EXP (union512, float, ESP_FLOAT, "%f")
+CHECK_FP_EXP (union512d, double, ESP_DOUBLE, "%f")
+
+#define CHECK_ROUGH_EXP(UINON_TYPE, VALUE_TYPE, FMT)		\
+static int							\
+__attribute__((noinline, unused))				\
+check_rough_##UINON_TYPE (UINON_TYPE u, const VALUE_TYPE *v,	\
+			  VALUE_TYPE eps)			\
+{								\
+  int i;							\
+  int err = 0;							\
+								\
+  for (i = 0; i < ARRAY_SIZE (u.a); i++)			\
+    {								\
+      /* We can have have v[i] == 0 == u.a[i]  for some i,	\
+         when we test zero-masking.  */				\
+      if (v[i] == 0.0 && u.a[i] == 0.0)				\
+	continue;						\
+      if (v[i] == 0.0 && u.a[i] != 0.0)				\
+	{							\
+	  err++;						\
+	  PRINTF ("%i: " FMT " != " FMT "\n",			\
+		  i, v[i], u.a[i]);				\
+	}							\
+      VALUE_TYPE rel_err = (u.a[i] - v[i]) / v[i];		\
+      if (((rel_err < 0) ? -rel_err : rel_err) > eps)		\
+	{							\
+	  err++;						\
+	  PRINTF ("%i: " FMT " != " FMT "\n",			\
+		  i, v[i], u.a[i]);				\
+	}							\
+    }								\
+  return err;							\
+}
+
+CHECK_ROUGH_EXP (union512, float, "%f")
+CHECK_ROUGH_EXP (union512d, double, "%f")
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/ceil.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/ceil.c
new file mode 100644
index 000000000..dfccd7af4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/ceil.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_ceilf (x);
+}
+double testl (double x)
+{
+  return __builtin_ceil (x);
+}
+long double testll (long double x)
+{
+  return __builtin_ceill (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/floor.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/floor.c
new file mode 100644
index 000000000..0c3aa9156
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/floor.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_floorf (x);
+}
+double testl (double x)
+{
+  return __builtin_floor (x);
+}
+long double testll (long double x)
+{
+  return __builtin_floorl (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lceil.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lceil.c
new file mode 100644
index 000000000..d09847904
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lceil.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble } */
+
+long testlf (float x)
+{
+  return __builtin_lceilf (x);
+}
+long testl (double x)
+{
+  return __builtin_lceil (x);
+}
+long testll (long double x)
+{
+  return __builtin_lceill (x);
+}
+long long testllf (float x)
+{
+  return __builtin_llceilf (x);
+}
+long long testll_ (double x)
+{
+  return __builtin_llceil (x);
+}
+long long testlll (long double x)
+{
+  return __builtin_llceill (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c
new file mode 100644
index 000000000..2c2e96f2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lfloor.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble } */
+
+long testlf (float x)
+{
+  return __builtin_lfloorf (x);
+}
+long testl (double x)
+{
+  return __builtin_lfloor (x);
+}
+long testll (long double x)
+{
+  return __builtin_lfloorl (x);
+}
+long long testllf (float x)
+{
+  return __builtin_llfloorf (x);
+}
+long long testll_ (double x)
+{
+  return __builtin_llfloor (x);
+}
+long long testlll (long double x)
+{
+  return __builtin_llfloorl (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lrint.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lrint.c
new file mode 100644
index 000000000..73b75b7ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lrint.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble } */
+
+long testlf (float x)
+{
+  return __builtin_lrintf (x);
+}
+long testl (double x)
+{
+  return __builtin_lrint (x);
+}
+long testll (long double x)
+{
+  return __builtin_lrintl (x);
+}
+long long testllf (float x)
+{
+  return __builtin_llrintf (x);
+}
+long long testll_ (double x)
+{
+  return __builtin_llrint (x);
+}
+long long testlll (long double x)
+{
+  return __builtin_llrintl (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lround.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lround.c
new file mode 100644
index 000000000..756356d62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/lround.c
@@ -0,0 +1,26 @@
+/* { dg-do assemble } */
+
+long testlf (float x)
+{
+  return __builtin_lroundf (x);
+}
+long testl (double x)
+{
+  return __builtin_lround (x);
+}
+long testll (long double x)
+{
+  return __builtin_lroundl (x);
+}
+long long testllf (float x)
+{
+  return __builtin_llroundf (x);
+}
+long long testll_ (double x)
+{
+  return __builtin_llround (x);
+}
+long long testlll (long double x)
+{
+  return __builtin_llroundl (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp
new file mode 100644
index 000000000..112fb33ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/math-torture.exp
@@ -0,0 +1,70 @@
+# Copyright (C) 2006-2014 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# This harness is for tests that should be run at all optimisation levels.
+
+load_lib target-supports.exp
+
+# Exit immediately if this isn't a x86 target.
+if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then {
+  return
+}
+
+set MATH_TORTURE_OPTIONS [list \
+        { -O0 } \
+        { -O0 -mfpmath=387 } \
+        { -O0 -mfpmath=387 -ffast-math } \
+        { -O2 } \
+        { -O2 -mfpmath=387 } \
+        { -O2 -mfpmath=387 -ffast-math } \
+]
+
+if { [check_effective_target_sse] } {
+    lappend MATH_TORTURE_OPTIONS \
+        { -O0 -msse -mno-sse2 -mfpmath=sse } \
+        { -O0 -msse -mno-sse2 -mfpmath=sse,387 } \
+        { -O0 -msse -mno-sse2 -mfpmath=sse -ffast-math } \
+        { -O0 -msse -mno-sse2 -mfpmath=sse,387 -ffast-math } \
+        { -O2 -msse -mno-sse2 -mfpmath=sse } \
+        { -O2 -msse -mno-sse2 -mfpmath=sse,387 } \
+        { -O2 -msse -mno-sse2 -mfpmath=sse -ffast-math } \
+        { -O2 -msse -mno-sse2 -mfpmath=sse,387 -ffast-math } \
+}
+
+if { [check_effective_target_sse2] } {
+    lappend MATH_TORTURE_OPTIONS \
+        { -O0 -msse -msse2 -mfpmath=sse } \
+        { -O0 -msse -msse2 -mfpmath=sse,387 } \
+        { -O0 -msse -msse2 -mfpmath=sse -ffast-math } \
+        { -O0 -msse -msse2 -mfpmath=sse,387 -ffast-math } \
+        { -O2 -msse -msse2 -mfpmath=sse } \
+        { -O2 -msse -msse2 -mfpmath=sse,387 } \
+        { -O2 -msse -msse2 -mfpmath=sse -ffast-math } \
+        { -O2 -msse -msse2 -mfpmath=sse,387 -ffast-math } \
+}
+
+load_lib gcc-dg.exp
+load_lib torture-options.exp
+
+torture-init
+set-torture-options $MATH_TORTURE_OPTIONS {{}} $LTO_TORTURE_OPTIONS
+
+dg-init
+gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] ""
+torture-finish
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c
new file mode 100644
index 000000000..dd646f012
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/nearbyint.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_nearbyintf (x);
+}
+double testl (double x)
+{
+  return __builtin_nearbyint (x);
+}
+long double testll (long double x)
+{
+  return __builtin_nearbyintl (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/rint.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/rint.c
new file mode 100644
index 000000000..f9dfff7ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/rint.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_rintf (x);
+}
+double testl (double x)
+{
+  return __builtin_rint (x);
+}
+long double testll (long double x)
+{
+  return __builtin_rintl (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/round.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/round.c
new file mode 100644
index 000000000..fddac7abb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/round.c
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_roundf (x);
+}
+double testl (double x)
+{
+  return __builtin_round (x);
+}
+long double testll (long double x)
+{
+  return __builtin_roundl (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/trunc.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/trunc.c
new file mode 100644
index 000000000..a71e026c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/math-torture/trunc.c
@@ -0,0 +1,14 @@
+/* { dg-do assemble } */
+
+float testlf (float x)
+{
+  return __builtin_truncf (x);
+}
+double testl (double x)
+{
+  return __builtin_trunc (x);
+}
+long double testll (long double x)
+{
+  return __builtin_truncl (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/max-stack-align.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/max-stack-align.c
new file mode 100644
index 000000000..9f37a63e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/max-stack-align.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-fomit-frame-pointer" } */
+
+void foo()
+{
+  int a=0, b=0, c=0, e=0, f=0, g=0, h=0, i=0;
+    __asm__ __volatile__ (""
+    :
+    :
+    : "bp"
+  );
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-1.c
new file mode 100644
index 000000000..b716c5d95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=pentiumpro -minline-all-stringops -fno-common" } */
+/* { dg-final { scan-assembler "rep" } } */
+/* { dg-final { scan-assembler "movs" } } */
+/* { dg-final { scan-assembler-not "test" } } */
+/* { dg-final { scan-assembler "\.L?:" } } */
+
+/* A and B are aligned, but we used to lose track of it.
+   Ensure that memcpy is inlined and alignment prologue is missing.  */
+
+char a[2048];
+char b[2048];
+t()
+{
+  __builtin_memcpy (a,b,2048);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-2.c
new file mode 100644
index 000000000..56cdd56fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+void *a;
+void *b;
+t(unsigned int c)
+{
+  if (c<10)
+    __builtin_memcpy (a,b,c+1);
+}
+/* Memcpy should be inlined because block size is known.  */
+/* { dg-final { scan-assembler-not "(jmp|call)\[\\t \]*memcpy" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-3.c
new file mode 100644
index 000000000..b9ea9c28e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+void *a;
+void *b;
+t(int c)
+{
+  if (c<10)
+    __builtin_memcpy (a,b,c);
+}
+/* Memcpy should be inlined because block size is known.  */
+/* { dg-final { scan-assembler-not "(jmp|call)\[\\t \]*memcpy" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c
new file mode 100644
index 000000000..a2b66d966
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:-1:align" } */
+/* { dg-final { scan-assembler-times "movdqa" 8 { target { ! { ia32 } } } } } */
+/* { dg-final { scan-assembler-times "movdqa" 4 { target { ia32 } } } } */
+
+char a[2048];
+char b[2048];
+void t (void)
+{
+  __builtin_memcpy (a, b, 2048);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c
new file mode 100644
index 000000000..c2f49f0cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:3000:align,libcall:-1:align" } */
+/* { dg-final { scan-assembler-times "movdqa" 8 { target { ! { ia32 } } } } } */
+/* { dg-final { scan-assembler-times "movdqa" 4 { target { ia32 } } } } */
+
+char a[2048];
+char b[2048];
+void t (void)
+{
+  __builtin_memcpy (a, b, 2048);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-3.c
new file mode 100644
index 000000000..ddd1ef7c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-strategy-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -mmemcpy-strategy=vector_loop:2000:align,libcall:-1:align" } */
+/* { dg-final { scan-assembler-times "memcpy" 2  } } */
+
+char a[2048];
+char b[2048];
+void t (void)
+{
+  __builtin_memcpy (a, b, 2048);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c
new file mode 100644
index 000000000..c61c06795
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */
+/* { dg-final { scan-assembler-times "movdqa" 8 { target { ! { ia32 } } } } } */
+/* { dg-final { scan-assembler-times "movdqa" 4 { target { ia32 } } } } */
+
+char a[2048];
+char b[2048];
+void t (void)
+{
+  __builtin_memcpy (a, b, 2048);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c
new file mode 100644
index 000000000..8a646d509
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memcpy-vector_loop-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */
+/* { dg-final { scan-assembler-times "movdqa" 4} } */
+
+char *a;
+char *b;
+void t (void)
+{
+  __builtin_memcpy (a, b, 2048);
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-1.c
new file mode 100644
index 000000000..eaf3230ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-1.c
@@ -0,0 +1,104 @@
+/* Copyright (C) 2002, 2005  Free Software Foundation.
+
+   Test -minline-all-stringops memset with various combinations of pointer
+   alignments and lengths to make sure builtin optimizations are correct.
+   PR target/6456.
+
+   Written by Michael Meissner, March 9, 2002.
+   Target by Roger Sayle, April 25, 2002.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -minline-all-stringops" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+extern void abort (void);
+extern void exit (int);
+
+#ifndef MAX_OFFSET
+#define MAX_OFFSET (sizeof (long long))
+#endif
+
+#ifndef MAX_COPY
+#define MAX_COPY (8 * sizeof (long long))
+#endif
+
+#ifndef MAX_EXTRA
+#define MAX_EXTRA (sizeof (long long))
+#endif
+
+#define MAX_LENGTH (MAX_OFFSET + MAX_COPY + MAX_EXTRA)
+
+static union {
+  char buf[MAX_LENGTH];
+  long long align_int;
+  long double align_fp;
+} u;
+
+char A = 'A';
+
+main ()
+{
+  int off, len, i;
+  char *p, *q;
+
+  for (off = 0; off < MAX_OFFSET; off++)
+    for (len = 1; len < MAX_COPY; len++)
+      {
+	for (i = 0; i < MAX_LENGTH; i++)
+	  u.buf[i] = 'a';
+
+	p = memset (u.buf + off, '\0', len);
+	if (p != u.buf + off)
+	  abort ();
+
+	q = u.buf;
+	for (i = 0; i < off; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	for (i = 0; i < len; i++, q++)
+	  if (*q != '\0')
+	    abort ();
+
+	for (i = 0; i < MAX_EXTRA; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	p = memset (u.buf + off, A, len);
+	if (p != u.buf + off)
+	  abort ();
+
+	q = u.buf;
+	for (i = 0; i < off; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	for (i = 0; i < len; i++, q++)
+	  if (*q != 'A')
+	    abort ();
+
+	for (i = 0; i < MAX_EXTRA; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	p = memset (u.buf + off, 'B', len);
+	if (p != u.buf + off)
+	  abort ();
+
+	q = u.buf;
+	for (i = 0; i < off; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+
+	for (i = 0; i < len; i++, q++)
+	  if (*q != 'B')
+	    abort ();
+
+	for (i = 0; i < MAX_EXTRA; i++, q++)
+	  if (*q != 'a')
+	    abort ();
+      }
+
+  exit(0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-strategy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-strategy-1.c
new file mode 100644
index 000000000..d1b97c5df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-strategy-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -mmemset-strategy=libcall:-1:align" } */
+/* { dg-final { scan-assembler-times "memset" 2  } } */
+
+char a[2048];
+void t (void)
+{
+  __builtin_memset (a, 1, 2048);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c
new file mode 100644
index 000000000..ad0d13037
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */
+/* { dg-final { scan-assembler-times "movdqa" 4 } } */
+
+char a[2048];
+void t (void)
+{
+  __builtin_memset (a, 0, 2048);
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c
new file mode 100644
index 000000000..f2ceb442c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/memset-vector_loop-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom -minline-all-stringops -mstringop-strategy=vector_loop" } */
+/* { dg-final { scan-assembler-times "movdqa" 4} } */
+
+char *a;
+void t (void)
+{
+  __builtin_memset (a, 0, 2048);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/merge-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/merge-1.c
new file mode 100644
index 000000000..d52568510
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/merge-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse2" } */
+
+#include <x86intrin.h>
+
+void
+f (double *r, __m128d x, __m128d y, __m128d z)
+{
+  __m128d t=_mm_move_sd(x,y);
+  __m128d u=_mm_move_sd(t,z);
+  *r = u[0];
+}
+
+__m128d
+g(__m128d x, __m128d y, __m128d z)
+{
+  __m128d t=_mm_move_sd(x,y);
+  __m128d u=_mm_move_sd(t,z);
+  return u;
+}
+
+/* { dg-final { scan-assembler-times "movsd" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/minmax-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/minmax-1.c
new file mode 100644
index 000000000..ca7fb6a91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/minmax-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=opteron" } */
+/* { dg-final { scan-assembler "test" } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+#define max(a,b) (((a) > (b))? (a) : (b))
+t(int a)
+{
+  return (max(a,1));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/minmax-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/minmax-2.c
new file mode 100644
index 000000000..2021aaa07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/minmax-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "test" } } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+#define max(a,b) (((a) > (b))? (a) : (b))
+t(unsigned int a)
+{
+  return (max(a,1));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-1.c
new file mode 100644
index 000000000..e304acaa3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-do compile { target { nonpic } } } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -mmmx" } */
+
+/* Test that the intrinsics compile with optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mmintrin.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-2.c
new file mode 100644
index 000000000..d15ceb185
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -mmmx" } */
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in mmintrin.h that reference the proper
+   builtin functions.  Defining away "extern" and "__inline" results in
+   all of them being compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <mmintrin.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-3.c
new file mode 100644
index 000000000..6022d5294
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-3.c
@@ -0,0 +1,17 @@
+/* PR target/8870 */
+/* Originator: otaylor@redhat.com */
+/* { dg-do compile } */
+/* { dg-options "-O1 -mmmx -march=k8" } */
+
+typedef short v4hi __attribute__ ((vector_size (8)));
+
+static inline v4hi cvtsi_v4hi (int i)
+{
+  long long tmp = i;
+  return (v4hi) tmp;
+}
+
+v4hi bar (unsigned short a)
+{
+  return cvtsi_v4hi (a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h
new file mode 100644
index 000000000..4f2f7f3ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-3dnow-check.h
@@ -0,0 +1,28 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void mmx_3dnow_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  mmx_3dnow_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run 3DNow! test only if host has 3DNow! support.  */
+  if (edx & bit_3DNOW)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-4.c
new file mode 100644
index 000000000..05d2b553b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-4.c
@@ -0,0 +1,236 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include "mmx-check.h"
+
+#include <mmintrin.h>
+#include <string.h>
+
+#define SHIFT (4)
+
+typedef union {
+  __m64 v;
+  unsigned char c[8];
+  unsigned short int s[4];
+  unsigned long long t;
+  unsigned int u[2];
+}vecInWord;
+
+void mmx_tests (void) __attribute__((noinline));
+void dump64_16 (char *, char *, vecInWord);
+void dump64_32 (char *, char *, vecInWord);
+void dump64_64 (char *, char *, vecInWord);
+int check (const char *, const char *[]);
+
+char buf[8000];
+char comparison[8000];
+static int errors = 0;
+
+vecInWord a64, b64, c64, d64, e64;
+__m64 m64_16, s64, m64_32, m64_64;
+
+const char *reference_mmx[] = {
+  "_mm_srai_pi16 0012 0012 0012 0012 \n",
+  "_mm_sra_pi16 0012 0012 0012 0012 \n",
+  "_mm_srai_pi32 00123456 00123456 \n",
+  "_mm_sra_pi32 00123456 00123456 \n",
+  "_mm_srli_pi16 0012 0012 0012 0012 \n",
+  "_mm_srl_pi16 0012 0012 0012 0012 \n",
+  "_mm_srli_pi32 00123456 00123456 \n",
+  "_mm_srl_pi32 00123456 00123456 \n",
+  "_mm_srli_si64 00123456789abcde\n",
+  "_mm_srl_si64 00123456789abcde\n",
+  "_mm_slli_pi16 1230 1230 1230 1230 \n",
+  "_mm_sll_pi16 1230 1230 1230 1230 \n",
+  "_mm_slli_pi32 12345670 12345670 \n",
+  "_mm_sll_pi32 12345670 12345670 \n",
+  "_mm_slli_si64 123456789abcdef0\n",
+  "_mm_sll_si64 123456789abcdef0\n",
+  ""
+};
+
+
+static void
+mmx_test (void)
+{
+  d64.u[0]  = 0x01234567;
+  d64.u[1]  = 0x01234567;
+
+  m64_32 = d64.v;
+
+  e64.t  = 0x0123456789abcdefULL;
+
+  m64_64 = e64.v;
+
+  a64.s[0] = 0x0123;
+  a64.s[1] = 0x0123;
+  a64.s[2] = 0x0123;
+  a64.s[3] = 0x0123;
+
+  m64_16 = a64.v;
+
+  b64.s[0] = SHIFT;
+  b64.s[1] = 0;
+  b64.s[2] = 0;
+  b64.s[3] = 0;
+
+  s64 = b64.v;
+
+  mmx_tests();
+  check (buf, reference_mmx);
+#ifdef DEBUG
+  printf ("mmx testing:\n");
+  printf (buf);
+  printf ("\ncomparison:\n");
+  printf (comparison);
+#endif
+  buf[0] = '\0';
+
+  if (errors != 0)
+    abort ();
+}
+
+void __attribute__((noinline))
+mmx_tests (void)
+{
+  /* psraw */
+  c64.v = _mm_srai_pi16 (m64_16, SHIFT);
+  dump64_16 (buf, "_mm_srai_pi16", c64);
+  c64.v  = _mm_sra_pi16 (m64_16, s64);
+  dump64_16 (buf, "_mm_sra_pi16", c64);
+
+  /* psrad */
+  c64.v  = _mm_srai_pi32 (m64_32, SHIFT);
+  dump64_32 (buf, "_mm_srai_pi32", c64);
+  c64.v = _mm_sra_pi32 (m64_32, s64);
+  dump64_32 (buf, "_mm_sra_pi32", c64);
+
+  /* psrlw */
+  c64.v = _mm_srli_pi16 (m64_16, SHIFT);
+  dump64_16 (buf, "_mm_srli_pi16", c64);
+  c64.v = _mm_srl_pi16 (m64_16, s64);
+  dump64_16 (buf, "_mm_srl_pi16", c64);
+
+  /* psrld */
+  c64.v = _mm_srli_pi32 (m64_32, SHIFT);
+  dump64_32 (buf, "_mm_srli_pi32", c64);
+  c64.v = _mm_srl_pi32 (m64_32, s64);
+  dump64_32 (buf, "_mm_srl_pi32", c64);
+
+  /* psrlq */
+  c64.v = _mm_srli_si64 (m64_64, SHIFT);
+  dump64_64 (buf, "_mm_srli_si64", c64);
+  c64.v = _mm_srl_si64 (m64_64, s64);
+  dump64_64 (buf, "_mm_srl_si64", c64);
+
+  /* psllw */
+  c64.v = _mm_slli_pi16 (m64_16, SHIFT);
+  dump64_16 (buf, "_mm_slli_pi16", c64);
+  c64.v = _mm_sll_pi16 (m64_16, s64);
+  dump64_16 (buf, "_mm_sll_pi16", c64);
+
+  /* pslld */
+  c64.v = _mm_slli_pi32 (m64_32, SHIFT);
+  dump64_32 (buf, "_mm_slli_pi32", c64);
+  c64.v = _mm_sll_pi32 (m64_32, s64);
+  dump64_32 (buf, "_mm_sll_pi32", c64);
+
+  /* psllq */
+  c64.v = _mm_slli_si64 (m64_64, SHIFT);
+  dump64_64 (buf, "_mm_slli_si64", c64);
+  c64.v = _mm_sll_si64 (m64_64, s64);
+  dump64_64 (buf, "_mm_sll_si64", c64);
+}
+
+void
+dump64_16 (char *buf, char *name, vecInWord x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<4; i++)
+    {
+      sprintf (p, "%4.4x ", x.s[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump64_32 (char *buf, char *name, vecInWord x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<2; i++)
+    {
+      sprintf (p, "%8.8x ", x.u[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump64_64 (char *buf, char *name, vecInWord x)
+{
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+#if defined(_WIN32) && !defined(__CYGWIN__)
+  sprintf (p, "%16.16I64x\n", x.t);
+#else
+  sprintf (p, "%16.16llx\n", x.t);
+#endif
+}
+
+int
+check (const char *input, const char *reference[])
+{
+  int broken, i, j, len;
+  const char *p_input;
+  char *p_comparison;
+  int new_errors = 0;
+
+  p_comparison = &comparison[0];
+  p_input = input;
+
+  for (i = 0; *reference[i] != '\0'; i++)
+    {
+      broken = 0;
+      len = strlen (reference[i]);
+      for (j = 0; j < len; j++)
+	{
+	  /* Ignore the terminating NUL characters at the end of every string in 'reference[]'.  */
+	  if (!broken && *p_input != reference[i][j])
+	    {
+	      *p_comparison = '\0';
+	      strcat (p_comparison, " >>> ");
+	      p_comparison += strlen (p_comparison);
+	      new_errors++;
+	      broken = 1;
+	    }
+	  *p_comparison = *p_input;
+	  p_comparison++;
+	  p_input++;
+	}
+      if (broken)
+	{
+	  *p_comparison = '\0';
+	  strcat (p_comparison, "expected:\n");
+	  strcat (p_comparison, reference[i]);
+	  p_comparison += strlen (p_comparison);
+	}
+    }
+  *p_comparison = '\0';
+  strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ;
+  errors += new_errors;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-5.c
new file mode 100644
index 000000000..a58fbb7b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-5.c
@@ -0,0 +1,18 @@
+/* PR rtl-optimization/17853 */
+/* Contributed by Stuart Hastings <stuart@apple.com> */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+#include <mmintrin.h>
+#include <stdlib.h>
+
+__m64 global_mask;
+
+int main()
+{
+    __m64 zero = _mm_setzero_si64();
+    __m64 mask = _mm_cmpeq_pi8( zero, zero );
+    mask = _mm_unpacklo_pi8( mask, zero );
+    global_mask = mask;
+    return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-6.c
new file mode 100644
index 000000000..e0bc6bdd3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-6.c
@@ -0,0 +1,17 @@
+/* PR middle-end/17767 */
+/* Contributed by Volker Reichelt <reichelt@igpm.rwth-aachen.de> */
+/* { dg-do compile } */
+/* { dg-options "-O -mmmx" } */
+typedef int __m64 __attribute__ ((vector_size (8)));
+typedef short __v4hi __attribute__ ((vector_size (8)));
+
+__m64 foo ()
+{
+  int i;
+  __m64 m;
+
+  for (i = 0; i < 2; i++)
+    m = (__m64) __builtin_ia32_pcmpeqw ((__v4hi) m, (__v4hi) m);
+
+  return m;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-7.c
new file mode 100644
index 000000000..683ca102d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-7.c
@@ -0,0 +1,18 @@
+/* PR middle-end/26379 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include <mmintrin.h>
+
+void
+foo (__m64 *p)
+{
+  __m64 m;
+
+  m = p[0];
+  m = _mm_srli_pi16(m, 2);
+  m = _mm_slli_pi16(m, 8);
+
+  p[0] = m;
+  _mm_empty();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-8.c
new file mode 100644
index 000000000..c90083bab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-8.c
@@ -0,0 +1,137 @@
+/* PR middle-end/37809 */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include <mmintrin.h>
+
+#include "mmx-check.h"
+
+// Various tests of cases where it is incorrect to optimise vectors as if they
+// were integers of the same width.
+
+extern void abort (void);
+
+void __attribute__ ((noinline))
+Sshift()
+{
+    volatile __m64 y = (__m64) 0xffffffffll;
+    __m64 x = y & (__m64) 0xffffffffll;
+    x = _m_psradi (x, 1);
+    x &= (__m64) 0x80000000ll;
+    if (0 == (long long) x)
+        abort();
+}
+
+#define SHIFTU(F,B,S,T)                         \
+    void F()                                    \
+    {                                           \
+        volatile __m64 y = (__m64) 0ll;         \
+        __m64 x = y | (__m64) (1llu << B);      \
+        if (S > 0)                              \
+            x = _m_pslldi (x, S);               \
+        else                                    \
+            x = _m_psrldi (x, -S);              \
+        if (T > 0)                              \
+            x = _m_pslldi (x, T);               \
+        else                                    \
+            x = _m_psrldi (x, -T);              \
+        x &= (__m64) (1llu << (B + S + T));     \
+        if ((long long) x)                      \
+            abort();                            \
+    }
+
+SHIFTU (shiftU1, 31, 1, -1)
+SHIFTU (shiftU2, 32, -1, 1)
+SHIFTU (shiftU3, 31, 1, 0)
+SHIFTU (shiftU4, 32, -1, 0)
+
+void __attribute__ ((noinline))
+add_1()
+{
+    volatile long long ONE = 1;
+    long long one = ONE;
+
+    __m64 a = (__m64) one;
+    __m64 b = (__m64) -one;
+    __m64 c = a + b;
+    if (0 == (long long) c)
+        abort();
+}
+
+void __attribute__ ((noinline))
+add_2()
+{
+    volatile long long ONE = 1;
+    long long one = ONE;
+
+    __m64 a = (__m64) one;
+    __m64 b = (__m64) -one;
+    __m64 c = _m_paddd (a, b);
+    if (0 == (long long) c)
+        abort();
+}
+
+void __attribute__ ((noinline))
+mult_1()
+{
+    volatile __m64 y = (__m64) 0ll;
+    __m64 x = y | (__m64) (1ll << 32);
+    x = x * (__m64) 1ll;
+    x &= (__m64) (1ll << 32);
+    if (0 != (long long) x)
+        abort();
+}
+
+void __attribute__ ((noinline))
+mult_2()
+{
+    volatile int foo = 1;
+    unsigned long long one = foo & 1;
+
+    __m64 x = (__m64) (one << 16);
+    x *= x;
+    x &= (__m64) (1ll << 32);
+    if (0 != (long long) x)
+        abort();
+}
+
+void __attribute__ ((noinline))
+mult_3()
+{
+    volatile __m64 y = (__m64) (1ll << 32);
+    __m64 a = y;
+    __m64 b = y * (__m64) 1ll;
+    if (((long long) a) == (long long) b)
+        abort();
+}
+
+void __attribute__ ((noinline))
+div_1()
+{
+    volatile __m64 y = (__m64) 0ll;
+    __m64 x = y | (__m64) (1ull << 32);
+    x |= (__m64) 1ull;
+    x = x / x;
+    if (1ll == (long long) x)
+        abort();
+}
+
+
+void mmx_test (void)
+{
+    Sshift();
+    shiftU1();
+    shiftU2();
+    shiftU3();
+    shiftU4();
+
+    add_1();
+    add_2();
+
+    mult_1();
+    mult_2();
+    mult_3();
+
+    div_1();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-check.h
new file mode 100644
index 000000000..faf9b876f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mmx-check.h
@@ -0,0 +1,28 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void mmx_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  mmx_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run MMX test only if host has MMX support.  */
+  if (edx & bit_MMX)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mod-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mod-1.c
new file mode 100644
index 000000000..a7b1a9225
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mod-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -mtune=generic" } */
+
+typedef struct {
+  int a;
+} VCR;
+
+typedef struct {
+  VCR vcr[8];
+} VCRC;
+
+typedef struct {
+  char vcr;
+} OWN;
+
+OWN Own[16];
+
+void
+f (VCRC *x, OWN *own)
+{
+  x[own->vcr / 8].vcr[own->vcr % 8].a--;
+  x[own->vcr / 8].vcr[own->vcr % 8].a = x[own->vcr / 8].vcr[own->vcr % 8].a;
+}
+
+/* { dg-final { scan-assembler-times "idivb" 1 } } */
+/* { dg-final { scan-assembler-not "incl" } } */
+/* { dg-final { scan-assembler-not "orl" } } */
+/* { dg-final { scan-assembler-not "andb" } } */
+/* { dg-final { scan-assembler-not "jns" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/monitor.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/monitor.c
new file mode 100644
index 000000000..939969f79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/monitor.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3" } */
+
+/* Verify that they work in both 32bit and 64bit.  */
+
+#include <pmmintrin.h>
+
+void
+foo (char *p, int x, int y, int z)
+{
+   _mm_monitor (p, y, x);
+   _mm_mwait (z, y);
+}
+
+void
+bar (char *p, long x, long y, long z)
+{
+   _mm_monitor (p, y, x);
+   _mm_mwait (z, y);
+}
+
+void
+foo1 (char *p)
+{
+   _mm_monitor (p, 0, 0);
+   _mm_mwait (0, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movabs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movabs-1.c
new file mode 100644
index 000000000..75ef8d2a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movabs-1.c
@@ -0,0 +1,10 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 -masm=intel" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target masm_intel } */
+
+void
+foo (void)
+{
+  *(volatile long*)0xFFFF800000000000 = -1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movbe-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movbe-1.c
new file mode 100644
index 000000000..391d4ad98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movbe-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmovbe" } */
+
+extern int x;
+
+void
+foo (int i)
+{
+  x = __builtin_bswap32 (i);
+}
+
+int
+bar ()
+{
+  return __builtin_bswap32 (x);
+}
+
+/* { dg-final { scan-assembler-times "movbe\[ \t\]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movbe-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movbe-2.c
new file mode 100644
index 000000000..b322f774a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movbe-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmovbe" } */
+
+extern long long x;
+
+void
+foo (long long i)
+{
+  x = __builtin_bswap64 (i);
+}
+
+long long
+bar ()
+{
+  return __builtin_bswap64 (x);
+}
+
+/* { dg-final { scan-assembler-times "movbe\[ \t\]" 4 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "movbe\[ \t\]" 2 { target { ! { ia32 } } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movdi-rex64.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movdi-rex64.c
new file mode 100644
index 000000000..f8b838810
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movdi-rex64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-fPIE" } */
+/* { dg-require-effective-target pie } */
+
+char *strcpy (char *dest, const char *src);
+
+static __thread char buffer[25];
+const char * error_message (void)
+{
+    strcpy (buffer, "Unknown code ");
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movq-2.c
new file mode 100644
index 000000000..37194b88d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movq-2.c
@@ -0,0 +1,26 @@
+/* PR target/25199 */
+/* { dg-do compile } */
+/* { dg-options "-Os -mtune=pentium4" } */
+/* { dg-require-effective-target ia32 } */
+
+struct S
+{
+  void *p[30];
+  unsigned char c[4];
+};
+
+unsigned char d;
+
+void
+foo (struct S *x)
+{
+  register unsigned char e __asm ("esi");
+  e = x->c[3];
+  __asm __volatile ("" : : "r" (e));
+  e = x->c[0];
+  __asm __volatile ("" : : "r" (e));
+}
+
+/* { dg-final { scan-assembler-not "movl\[ \t\]*123" } } */
+/* { dg-final { scan-assembler "movzbl\[ \t\]*123" } } */
+/* { dg-final { scan-assembler "mov(zb)?l\[ \t\]*120" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movq.c
new file mode 100644
index 000000000..53cb42143
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movq.c
@@ -0,0 +1,10 @@
+/* { dg-do compile }
+/* { dg-options "-Os -march=pentium4 -mtune=prescott" } */
+/* { dg-require-effective-target ia32 } */
+
+register char foo asm("edi");
+char x;
+int bar() {
+  foo = x;
+}
+/* { dg-final { scan-assembler "movz" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movsd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movsd.c
new file mode 100644
index 000000000..32a19e79a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movsd.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse2 -mfpmath=sse" } */
+
+volatile double y;
+
+void
+test ()
+{
+  int z;
+
+  for (z = 0; z < 1000; z++)
+    y = 1.23;
+}
+
+/* { dg-final { scan-assembler-not "(fld|fst)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movsi-sm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movsi-sm-1.c
new file mode 100644
index 000000000..35941405d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movsi-sm-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fgcse-sm -minline-all-stringops" } */
+
+/* Store motion used to fail to recognize killed expressions within
+   parallels such as those generated for memory copying.  */
+
+static const char s[1024] __attribute__ ((__aligned__ (32)))
+  = "This is what we should get!";
+
+int bug (int arg) {
+  char str[sizeof(s) > 4 ? sizeof(s) : 4] __attribute__ ((__aligned__ (32)));
+
+  __builtin_memcpy (str, "Bug", 4);
+
+  if (arg <= 2)
+    __builtin_memcpy (str, s, sizeof (s));
+
+  if (arg <= 1)
+    __builtin_memcpy (str, "Err", 4);
+
+  __builtin_puts (str);
+
+  return str[0] != s[0];
+}
+
+int main () {
+  if (bug (2))
+    __builtin_abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/movti.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/movti.c
new file mode 100644
index 000000000..86a0279fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/movti.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -std=gnu99" } */
+
+_Decimal128 test (void)
+{
+  return 1234123412341234.123412341234dl;
+}
+
+/* { dg-final { scan-assembler-not "movabs" { target { ! x86_64-*-mingw* } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c
new file mode 100644
index 000000000..e11bcc049
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ms_hook_prologue.c
@@ -0,0 +1,38 @@
+/* Test that the ms_hook_prologue attribute generates the correct code.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ms_hook_prologue } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+int __attribute__ ((__ms_hook_prologue__)) foo ()
+{
+  unsigned char *ptr = (unsigned char *) foo;
+
+  /* The NOP mov must not be optimized away by optimizations.
+     The push %ebp, mov %esp, %ebp must not be removed by
+     -fomit-frame-pointer */
+#ifndef __x86_64__
+  /* movl.s %edi, %edi */
+  if(*ptr++ != 0x8b) return 1;
+  if(*ptr++ != 0xff) return 1;
+  /* push %ebp */
+  if(*ptr++ != 0x55) return 1;
+  /* movl.s %esp, %ebp */
+  if(*ptr++ != 0x8b) return 1;
+  if(*ptr++ != 0xec) return 1;
+#else
+  /* leaq 0(%rsp), %rsp */
+  if (*ptr++ != 0x48) return 1;
+  if (*ptr++ != 0x8d) return 1;
+  if (*ptr++ != 0xa4) return 1;
+  if (*ptr++ != 0x24) return 1;
+  if (ptr[0] != 0 || ptr[1] != 0 || ptr[2] != 0 || ptr[3] != 0)
+    return 1;
+#endif
+  return 0;
+}
+
+int main ()
+{
+  return foo();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/mul.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/mul.c
new file mode 100644
index 000000000..94f0b8dc8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/mul.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -march=k8" } */
+/* { dg-final { scan-assembler "and\[^\\n\]*magic" } } */
+
+/* Should be done as "andw $32767, magic".  */
+static unsigned short magic;
+void t(void)
+{
+	magic%=(unsigned short)0x8000U;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/nest-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/nest-1.c
new file mode 100644
index 000000000..ba75350fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/nest-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target llp64 } } */
+/* { dg-options "" } */
+
+void foo (int i)
+{
+  void nested (void)
+  {
+    char arr[(1U << 31) + 4U];
+    arr[i] = 0;
+  }
+
+  nested ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/nrv1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/nrv1.c
new file mode 100644
index 000000000..a02823697
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/nrv1.c
@@ -0,0 +1,12 @@
+/* Verify that gimple-level NRV is occurring even for SSA_NAMEs.  *./
+/* { dg-do compile } */
+/* { dg-options "-O -fdump-tree-optimized" } */
+/* { dg-require-effective-target ia32 } */
+
+_Complex double foo (_Complex double x)
+{
+  return __builtin_cexp (x);
+}
+
+/* { dg-final { scan-tree-dump-times "return slot optimization" 1 "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/opt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/opt-1.c
new file mode 100644
index 000000000..2585236a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/opt-1.c
@@ -0,0 +1,35 @@
+/* Test the attribute((optimize)) really works.  Do this test by checking
+   whether we vectorize a simple loop.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8 --param min-insn-to-prefetch-ratio=0" } */
+/* { dg-final { scan-assembler "prefetcht0" } } */
+/* { dg-final { scan-assembler "addps" } } */
+/* { dg-final { scan-assembler "subss" } } */
+
+#define SIZE 10240
+float a[SIZE] __attribute__((__aligned__(32)));
+float b[SIZE] __attribute__((__aligned__(32)));
+float c[SIZE] __attribute__((__aligned__(32)));
+
+/* This should vectorize.  */
+void opt3 (void) __attribute__((__optimize__(3,"unroll-all-loops,-fprefetch-loop-arrays")));
+
+void
+opt3 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
+
+/* This should not vectorize.  */
+void
+not_opt3 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] - c[i];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/opt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/opt-2.c
new file mode 100644
index 000000000..1fa18c1f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/opt-2.c
@@ -0,0 +1,38 @@
+/* Test the attribute((optimize)) really works.  Do this test by checking
+   whether we vectorize a simple loop.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse2 -mfpmath=sse -march=k8 --param min-insn-to-prefetch-ratio=0" } */
+/* { dg-final { scan-assembler "prefetcht0" } } */
+/* { dg-final { scan-assembler "addps" } } */
+/* { dg-final { scan-assembler "subss" } } */
+
+#define SIZE 10240
+float a[SIZE] __attribute__((__aligned__(32)));
+float b[SIZE] __attribute__((__aligned__(32)));
+float c[SIZE] __attribute__((__aligned__(32)));
+
+/* This should vectorize.  */
+#pragma GCC push_options
+#pragma GCC optimize (3, "unroll-all-loops", "-fprefetch-loop-arrays")
+
+void
+opt3 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
+
+#pragma GCC pop_options
+
+/* This should not vectorize.  */
+void
+not_opt3 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] - c[i];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ordcmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ordcmp-1.c
new file mode 100644
index 000000000..a136182ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ordcmp-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-final { scan-assembler "cmpordss" } } */
+/* { dg-final { scan-assembler "cmpordps" } } */
+/* { dg-final { scan-assembler "cmpordsd" } } */
+/* { dg-final { scan-assembler "cmpordpd" } } */
+/* { dg-final { scan-assembler-not "cmpunordss" } } */
+/* { dg-final { scan-assembler-not "cmpunordps" } } */
+/* { dg-final { scan-assembler-not "cmpunordsd" } } */
+/* { dg-final { scan-assembler-not "cmpunordpd" } } */
+
+#include <emmintrin.h>
+
+__m128
+f1 (__m128 x, __m128 y)
+{
+  return _mm_cmpord_ss (x, y);
+}
+
+__m128
+f2 (__m128 x, __m128 y)
+{
+  return _mm_cmpord_ps (x, y);
+}
+
+__m128d
+f3 (__m128d x, __m128d y)
+{
+  return _mm_cmpord_sd (x, y);
+}
+
+__m128d
+f4 (__m128d x, __m128d y)
+{
+  return _mm_cmpord_pd (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-1.c
new file mode 100644
index 000000000..c2e27c9e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */
+/* { dg-final { scan-assembler "rep" { target { ! x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-not "nop" } } */
+
+void
+foo ()
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-10.c
new file mode 100644
index 000000000..cd65041fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-not "nop" } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+extern void bar ();
+
+int
+foo2 (int z, int x)
+{
+  if (x == 1)
+    {
+      bar ();
+      return z;
+    }
+  else
+    return x - z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-2.c
new file mode 100644
index 000000000..fe45c19d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-times "nop" 8 { target { ! x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-times "nop" 6 { target { x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+void
+foo ()
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-3.c
new file mode 100644
index 000000000..43d654f3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-3.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom -fno-pic" } */
+/* { dg-final { scan-assembler-not "nop" } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+int s[8] = {1, 2, 3, 4, 5, 6, 7, 8};
+int d[8] = {11, 22, 33, 44, 55, 66, 77, 88};
+
+void
+foo ()
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    d[i] = s[i] + 0x1000;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-4.c
new file mode 100644
index 000000000..7b198a63d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom -fPIC" } */
+/* { dg-final { scan-assembler-times "nop" 8 } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+extern int bar;
+
+int
+foo ()
+{
+  asm volatile ("");
+  return bar;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-5a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-5a.c
new file mode 100644
index 000000000..3a02262a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-5a.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-times "nop" 2 } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+int
+foo (int x, int y, int z)
+{
+   return x + y + z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-5b.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-5b.c
new file mode 100644
index 000000000..4cd034092
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-5b.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-times "nop" 4 { target { ! x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-times "nop" 2 { target { x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+int
+foo (int x, int y, int z)
+{
+   return x + y + z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-6a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-6a.c
new file mode 100644
index 000000000..97af9f9ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-6a.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-times "nop" 4 } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+int
+foo (int x, int y)
+{
+   return x + y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-6b.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-6b.c
new file mode 100644
index 000000000..82a3d331c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-6b.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-times "nop" 6 { target { ! x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-times "nop" 4 { target { x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+int
+foo (int x, int y)
+{
+   return x + y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-7.c
new file mode 100644
index 000000000..a4dbd260b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-7.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-not "nop" } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+int
+foo (int x, int y, int z)
+{
+   return x + y + z + y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-8.c
new file mode 100644
index 000000000..634cd7417
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-8.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-times "nop" 6 { target { ! x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-times "nop" 4 { target { x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+int
+foo (int x, int y)
+{
+   return y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-9.c
new file mode 100644
index 000000000..226a0932b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pad-9.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=atom" } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=atom" } */
+/* { dg-final { scan-assembler-times "nop" 4 { target { ! x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-times "nop" 2 { target { x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler-not "rep" } } */
+
+extern void bar (void);
+
+void
+foo (int x)
+{
+  if (x)
+    bar ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/parity-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/parity-1.c
new file mode 100644
index 000000000..1b0001ef2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/parity-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mno-popcnt" } */
+/* { dg-final { scan-assembler "setnp" } } */
+
+int foo(unsigned int x)
+{
+  return __builtin_parity(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/parity-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/parity-2.c
new file mode 100644
index 000000000..9adca35a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/parity-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -mno-popcnt" } */
+/* { dg-final { scan-assembler "setnp" } } */
+
+int foo(unsigned long long int x)
+{
+  return __builtin_parityll(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pause-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pause-1.c
new file mode 100644
index 000000000..50eb8e7e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pause-1.c
@@ -0,0 +1,11 @@
+/* Test that we generate pause instruction.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -dp" } */
+/* { dg-final { scan-assembler-times "\\*pause" 1 } } */
+
+#include <x86intrin.h>
+
+void foo(void)
+{
+  __pause();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h
new file mode 100644
index 000000000..5eed2e220
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmul-avx-check.h
@@ -0,0 +1,41 @@
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+#include <stdlib.h>
+#include "cpuid.h"
+#include "avx-os-support.h"
+
+static void pclmul_avx_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  pclmul_avx_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run PCLMUL + AVX test only if host has PCLMUL + AVX support.  */
+  if (((ecx & (bit_AVX | bit_OSXSAVE | bit_PCLMUL))
+       == (bit_AVX | bit_OSXSAVE | bit_PCLMUL))
+      && avx_os_support ())
+    {
+      do_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmul-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmul-check.h
new file mode 100644
index 000000000..7526cbe2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmul-check.h
@@ -0,0 +1,37 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void pclmul_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  pclmul_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run PCLMULQDQ test only if host has PCLMULQDQ support.  */
+  if (ecx & bit_PCLMUL)
+    {
+      do_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmulqdq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmulqdq.c
new file mode 100644
index 000000000..1c1d2aabe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pclmulqdq.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-require-effective-target pclmul } */
+/* { dg-options "-O2 -mpclmul" } */
+
+#ifndef CHECK_H
+#define CHECK_H "pclmul-check.h"
+#endif
+
+#ifndef TEST
+#define TEST pclmul_test
+#endif
+
+#include CHECK_H
+
+#include <wmmintrin.h>
+#include <string.h>
+
+extern void abort (void);
+
+#define NUM 1024
+
+static __m128i s1[NUM];
+static __m128i s2[NUM];
+/* We need this array to generate mem form of inst */
+static __m128i s2m[NUM];
+
+static __m128i e_00[NUM];
+static __m128i e_01[NUM];
+static __m128i e_10[NUM];
+static __m128i e_11[NUM];
+
+static __m128i d_00[NUM];
+static __m128i d_01[NUM];
+static __m128i d_10[NUM];
+static __m128i d_11[NUM];
+
+/* Initialize input/output vectors.  (Currently, there is only one set
+   of input/output vectors).  */
+static void
+init_data (__m128i *ls1,   __m128i *ls2, __m128i *le_00, __m128i *le_01,
+	   __m128i *le_10, __m128i *le_11)
+{
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      ls1[i] = _mm_set_epi32 (0x7B5B5465, 0x73745665,
+			      0x63746F72, 0x5D53475D);
+      ls2[i] = _mm_set_epi32 (0x48692853, 0x68617929,
+			      0x5B477565, 0x726F6E5D);
+      s2m[i] = _mm_set_epi32 (0x48692853, 0x68617929,
+			      0x5B477565, 0x726F6E5D);
+      le_00[i] = _mm_set_epi32 (0x1D4D84C8, 0x5C3440C0,
+				0x929633D5, 0xD36F0451);
+      le_01[i] = _mm_set_epi32 (0x1A2BF6DB, 0x3A30862F,
+				0xBABF262D, 0xF4B7D5C9);
+      le_10[i] = _mm_set_epi32 (0x1BD17C8D, 0x556AB5A1,
+				0x7FA540AC, 0x2A281315);
+      le_11[i] = _mm_set_epi32 (0x1D1E1F2C, 0x592E7C45,
+				0xD66EE03E, 0x410FD4ED);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+
+  init_data (s1, s2, e_00, e_01, e_10, e_11);
+
+  for (i = 0; i < NUM; i += 2)
+    {
+      d_00[i] = _mm_clmulepi64_si128 (s1[i], s2m[i], 0x00);
+      d_01[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x01);
+      d_10[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x10);
+      d_11[i] = _mm_clmulepi64_si128 (s1[i], s2[i], 0x11);
+
+      d_11[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x11);
+      d_00[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x00);
+      d_10[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2m[i + 1], 0x10);
+      d_01[i + 1] = _mm_clmulepi64_si128 (s1[i + 1], s2[i + 1], 0x01);
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      if (memcmp (d_00 + i, e_00 + i, sizeof (__m128i)))
+	abort ();
+      if (memcmp (d_01 + i, e_01 + i, sizeof (__m128i)))
+	abort ();
+      if (memcmp (d_10 + i, e_10 + i, sizeof (__m128i)))
+	abort ();
+      if (memcmp(d_11 + i, e_11 + i, sizeof (__m128i)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c
new file mode 100644
index 000000000..c840c47e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=pentium4" } } */
+/* { dg-options "-O2 -march=pentium4" } */
+/* { dg-final { scan-assembler-not "imull" } } */
+
+/* Should be done not using imull.  */
+int t(int x)
+{
+  return x*29;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/perm-concat.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/perm-concat.c
new file mode 100644
index 000000000..10955c207
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/perm-concat.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mavx -mfpmath=sse" } */
+
+typedef double v2df __attribute__ ((__vector_size__ (16)));
+
+v2df
+f (double d)
+{
+  v2df x = {-d, d};
+  return __builtin_ia32_vpermilpd (x, 1);
+}
+
+/* { dg-final { scan-assembler-not "\tvpermilpd\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pic-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pic-1.c
new file mode 100644
index 000000000..af2424b07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pic-1.c
@@ -0,0 +1,21 @@
+/* PR target/8340 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-skip-if "No Windows PIC" { *-*-mingw* *-*-cygwin } { "*" } { "" } } */
+/* { dg-options "-fPIC" } */
+
+int foo ()
+{
+  static int a;
+
+  __asm__ __volatile__ (  /* { dg-error "PIC register" } */
+    "xorl %%ebx, %%ebx\n"
+    "movl %%ebx, %0\n"
+    : "=m" (a)
+    :
+    : "%ebx"
+  );
+
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pow-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pow-1.c
new file mode 100644
index 000000000..2e1ac61bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pow-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O -ffast-math" } */
+
+double test1 (double x)
+{
+  return __builtin_pow (x, 1./2.);
+}
+
+double test2 (double x)
+{
+  return __builtin_pow (x, 3./2.);
+}
+
+double test3 (double x)
+{
+  return __builtin_pow (x, 5./2.);
+}
+
+double test4 (double x)
+{
+  return __builtin_pow (x, -5./2.);
+}
+
+/* { dg-final { scan-assembler-not "call\[ \t\]*pow" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c
new file mode 100644
index 000000000..c63f84869
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-1.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep movX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+register int regvar asm("%esi");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memcpy (foo, bar, sizeof foo);
+  memcpy (baz, quux, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep movsl" } } */
+/* { dg-final { scan-assembler-not "rep movsb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c
new file mode 100644
index 000000000..ae1c3a886
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-2.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep movX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+register int regvar asm("%edi");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memcpy (foo, bar, sizeof foo);
+  memcpy (baz, quux, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep movsl" } } */
+/* { dg-final { scan-assembler-not "rep movsb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c
new file mode 100644
index 000000000..0f5bd561d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memcpy-3.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep movX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memcpy (void *, const void *, __SIZE_TYPE__);
+
+register int regvar asm("%ecx");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memcpy (foo, bar, sizeof foo);
+  memcpy (baz, quux, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep movsl" } } */
+/* { dg-final { scan-assembler-not "rep movsb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c
new file mode 100644
index 000000000..e44d32fb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-1.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep stoX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+
+register int regvar asm("%eax");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memset (foo, 0, sizeof foo);
+  memset (baz, 0, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep stosl" } } */
+/* { dg-final { scan-assembler-not "rep stosb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c
new file mode 100644
index 000000000..02fc8d319
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-2.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep stoX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+
+register int regvar asm("%ecx");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memset (foo, 0, sizeof foo);
+  memset (baz, 0, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep stosl" } } */
+/* { dg-final { scan-assembler-not "rep stosb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c
new file mode 100644
index 000000000..1bdfb8656
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-memset-3.c
@@ -0,0 +1,23 @@
+/* Ensure that we don't use 'rep stoX' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-Os -w" } */
+
+extern void *memset (void *, int, __SIZE_TYPE__);
+
+register int regvar asm("%edi");
+
+int foo[10];
+int bar[10];
+
+char baz[15];
+char quux[15];
+
+void
+do_copy ()
+{
+  memset (foo, 0, sizeof foo);
+  memset (baz, 0, sizeof baz);
+}
+
+/* { dg-final { scan-assembler-not "rep stosl" } } */
+/* { dg-final { scan-assembler-not "rep stosb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c
new file mode 100644
index 000000000..6e159e445
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-1.c
@@ -0,0 +1,16 @@
+/* Ensure that we don't use 'repnz scasb' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -w" } */
+
+extern __SIZE_TYPE__ strlen (const char *);
+extern void *malloc (__SIZE_TYPE__);
+
+register int regvar asm("%edi");
+
+char *
+do_copy (char *str)
+{
+  return malloc (strlen (str) + 1);
+}
+
+/* { dg-final { scan-assembler-not "repnz scasb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c
new file mode 100644
index 000000000..e03adb25f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-2.c
@@ -0,0 +1,16 @@
+/* Ensure that we don't use 'repnz scasb' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -w" } */
+
+extern __SIZE_TYPE__ strlen (const char *);
+extern void *malloc (__SIZE_TYPE__);
+
+register int regvar asm("%eax");
+
+char *
+do_copy (char *str)
+{
+  return malloc (strlen (str) + 1);
+}
+
+/* { dg-final { scan-assembler-not "repnz scasb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c
new file mode 100644
index 000000000..c7a379ae0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr11001-strlen-3.c
@@ -0,0 +1,16 @@
+/* Ensure that we don't use 'repnz scasb' in the presence of register globals.  */
+/* { dg-do compile } */
+/* { dg-options "-O1 -w" } */
+
+extern __SIZE_TYPE__ strlen (const char *);
+extern void *malloc (__SIZE_TYPE__);
+
+register int regvar asm("%ecx");
+
+char *
+do_copy (char *str)
+{
+  return malloc (strlen (str) + 1);
+}
+
+/* { dg-final { scan-assembler-not "repnz scasb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr12092-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr12092-1.c
new file mode 100644
index 000000000..c230c84b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr12092-1.c
@@ -0,0 +1,13 @@
+/* PR rtl-optimization/12092  */
+/* Test case reduced by Andrew Pinski <pinskia@physics.uc.edu> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -mtune=i486 -march=pentium4 -fprefetch-loop-arrays" } */
+
+void DecodeAC(int index,int *matrix)
+{
+  int *mptr;
+
+  for(mptr=matrix+index;mptr<matrix+64;mptr++) {*mptr = 0;}
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr12329.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr12329.c
new file mode 100644
index 000000000..e7b43a78e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr12329.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+int test_nested1 (int i)
+{
+  int __attribute__ ((__noinline__, __regparm__(3))) foo(int j, int k, int l)
+  {
+    return i + j + k + l;
+  }
+
+  return foo (i, i+1, i+2);
+}
+
+int test_nested2 (int i)
+{
+  int x;
+
+  int __attribute__ ((__noinline__, __regparm__(3))) foo(int j, int k, int l)
+  {
+    return i + j + k + l;
+  }
+
+  x = foo (i+3, i+1, i+2);
+  if (x != (4*i + 6))
+    abort ();
+
+  return x;
+}
+
+int
+main ()
+{
+  int i = test_nested1 (3);
+
+  if (i != 15)
+    abort ();
+
+  i = test_nested2 (4);
+
+  if (i != 22)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr13366.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr13366.c
new file mode 100644
index 000000000..f0dce0b24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr13366.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msse" } */
+
+#include <xmmintrin.h>
+
+typedef unsigned short v4hi __attribute__ ((vector_size (8)));
+
+int f(unsigned short n)
+{
+   __m64 vec = (__m64)(v4hi){ 0, 0, 1, n };
+   __m64 hw = _mm_mulhi_pi16 (vec, vec);
+   return _mm_extract_pi16 (hw, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr13685.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr13685.c
new file mode 100644
index 000000000..a50681bea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr13685.c
@@ -0,0 +1,32 @@
+/* PR target/13685 */
+/* { dg-do run } */
+/* { dg-options "-Os -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+
+void foo (__m128 *, __m64 *, int);
+
+__m128 xmm0 = { 0 };
+__m64 mm0 = { 0 };
+
+static void
+sse_test (void)
+{
+  foo (&xmm0, &mm0, 4);
+}
+
+void
+foo (__m128 *dst, __m64 *src, int n)
+{
+  __m128 xmm0 = { 0 };
+  while (n > 64)
+    {
+      puts ("");
+      xmm0 = _mm_cvtpi32_ps (xmm0, *src);
+      *dst = xmm0;
+      n--;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr14289-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr14289-1.c
new file mode 100644
index 000000000..e427b2d0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr14289-1.c
@@ -0,0 +1,12 @@
+/* PR middle-end/14289 */
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+register int a[2] asm("ebx");
+
+void Nase(void)
+{
+  int i=6;
+  a[i]=5;  /* { dg-error "address of global" } */
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr14552.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr14552.c
new file mode 100644
index 000000000..659257c32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr14552.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+
+typedef short mmxw  __attribute__ ((vector_size (8)));
+typedef int   mmxdw __attribute__ ((vector_size (8)));
+
+mmxdw dw;
+mmxw w;
+
+void test()
+{
+  w+=w;
+  dw= (mmxdw)w;
+}
+
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr17390.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr17390.c
new file mode 100644
index 000000000..9a3d61fcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr17390.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -mfpmath=387" } */
+
+double sgn (double __x)
+{
+  return __x == 0.0 ? 0.0 : (__x > 0.0 ? 1.0 : -1.0);
+}
+
+/* { dg-final { scan-assembler-times "fcom|ftst" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr17692.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr17692.c
new file mode 100644
index 000000000..476d8e3de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr17692.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mfpmath=sse -msse2" } */
+
+/* The fact that t1 and t2 are uninitialized is critical.  With them
+   uninitialized, the register allocator is free to put them in the same
+   hard register, which results in
+
+	xmm0 = xmm0 >= xmm0 ? xmm0 : xmm0
+
+   Which is of course a nop, but one for which we would ICE splitting the
+   pattern.  */
+   
+double out;
+
+static void foo(void)
+{
+    double t1, t2, t3, t4;
+    
+    t4 = t1 >= t2 ? t1 : t2;
+    t4 = t4 >= t3 ? t4 : t3;
+    out = t4;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr18614-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr18614-1.c
new file mode 100644
index 000000000..1a4997537
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr18614-1.c
@@ -0,0 +1,15 @@
+/* PR rtl-optimization/18614 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef double v2df __attribute__ ((vector_size (16)));
+
+v2df foo (void)
+{
+  v2df yd = { 1.0, 4.0 };
+  v2df xd;
+
+  xd = __builtin_ia32_cvtps2pd (__builtin_ia32_rsqrtps
+				(__builtin_ia32_cvtpd2ps (yd)));
+  return xd;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr19236-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr19236-1.c
new file mode 100644
index 000000000..38db79812
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr19236-1.c
@@ -0,0 +1,14 @@
+/* PR target/19236 */
+/* { dg-do compile } */
+/* { dg-options "-ffast-math" } */
+
+extern float log1pf (float);
+extern double log1p (double);  
+
+float testf (float __x) { 
+  return log1pf(1.0); 
+}
+
+double test (double __x) { 
+  return log1p(1.0); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr19398.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr19398.c
new file mode 100644
index 000000000..60931c0a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr19398.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -msse -mno-sse3 -mfpmath=387" } */
+
+int test (float a)
+{
+  return (a * a);
+}
+
+/* { dg-final { scan-assembler-not "cvttss2si\[^\\n\]*%xmm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-1.c
new file mode 100644
index 000000000..f36a8a095
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-1.c
@@ -0,0 +1,27 @@
+/* Check that 128-bit struct's are represented as TImode values.  */
+/* { dg-do compile { target int128 } } */
+/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */
+/* { dg-options "-O2 -fdump-rtl-expand" } */
+
+struct shared_ptr_struct
+{
+  unsigned long long phase:48;
+  unsigned short thread:16;
+  union
+    {
+      void *addr;
+      unsigned long long pad;
+    };
+};
+typedef struct shared_ptr_struct sptr_t;
+
+sptr_t S;
+
+sptr_t
+sptr_result (void)
+{
+  return S;
+}
+/* { dg-final { scan-rtl-dump "\\\(set \\\(reg:TI \[0-9\]* \\\[ <retval> \\\]\\\)" "expand" } } */
+/* { dg-final { scan-rtl-dump "\\\(set \\\(reg/i:TI 0 ax\\\)" "expand" } } */
+/* { dg-final { cleanup-rtl-dump "expand" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-2.c
new file mode 100644
index 000000000..fa5b6edaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-2.c
@@ -0,0 +1,25 @@
+/* Check that 128-bit struct's are represented as TImode values.  */
+/* { dg-do compile { target int128 } } */
+/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */
+/* { dg-options "-O2 -fdump-rtl-expand" } */
+
+struct shared_ptr_struct
+{
+  unsigned long long phase:48;
+  unsigned short thread:16;
+  union
+    {
+      void *addr;
+      unsigned long long pad;
+    };
+};
+typedef struct shared_ptr_struct sptr_t;
+
+void
+copy_sptr (sptr_t *dest, sptr_t src)
+{
+  *dest = src;
+}
+
+/* { dg-final { scan-rtl-dump "\\\(set \\\(reg:TI \[0-9\]*" "expand" } } */
+/* { dg-final { cleanup-rtl-dump "expand" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-3.c
new file mode 100644
index 000000000..a30fbc4b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20020-3.c
@@ -0,0 +1,28 @@
+/* Check that 128-bit struct's are represented as TImode values.  */
+/* { dg-do compile { target int128 } } */
+/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */
+/* { dg-options "-O2 -fdump-rtl-expand" } */
+
+struct shared_ptr_struct
+{
+  unsigned long long phase:48;
+  unsigned short thread:16;
+  union
+    {
+      void *addr;
+      unsigned long long pad;
+    };
+};
+typedef struct shared_ptr_struct sptr_t;
+
+sptr_t sptr_1, sptr_2;
+
+void
+copy_sptr (void)
+{
+  sptr_1 = sptr_2;  
+}
+
+/* { dg-final { scan-rtl-dump "\\\(set \\\(reg:TI \[0-9\]*" "expand" } } */
+/* { dg-final { scan-rtl-dump "\\\(set \\\(mem/c:TI" "expand" } } */
+/* { dg-final { cleanup-rtl-dump "expand" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20204.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20204.c
new file mode 100644
index 000000000..ca97a3ae9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr20204.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+void *x (void *pdst, const void *psrc, unsigned int pn)
+{
+  register void *return_dst = pdst;
+  register unsigned char *dst = pdst;
+  register unsigned const char *src = psrc;
+  register int n __asm__ ("ebx") = pn;
+
+  if (src < dst && dst < src + n)
+    {
+      src += n;
+      dst += n;
+      while (n--)
+        *--dst = *--src;
+      return return_dst;
+    }
+
+  while (n >= 16) n--;
+
+  return return_dst;
+}
+extern void abort ();
+extern void exit (int);
+char xx[30] = "abc";
+int main (void)
+{
+  char yy[30] = "aab";
+
+  if (x (xx + 1, xx, 2) != xx + 1 || memcmp (xx, yy, sizeof (yy)) != 0)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21101.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21101.c
new file mode 100644
index 000000000..104b08cd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21101.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -funroll-loops -march=nocona" } */
+
+#include <mmintrin.h>
+
+int W;
+void f()
+{
+  int j;
+  int B, C;
+  unsigned char* S;
+  __m64 *T = (__m64 *) &W;
+
+  for (j = 0; j < 16; j++, T++)
+  {
+    T[0] = T[1] = _mm_set1_pi8(*S);
+    S += W;
+  }
+
+  C = 3 * B;
+
+  __m64 E = _mm_set_pi16(3 * B, 3 * B, 3 * B, 5 * B);
+  __m64 G = _mm_set1_pi16(3 * B);
+
+  for (j = 0; j < 16; j++)
+  {
+    __m64 R = _mm_set1_pi16(B + j * C);
+    R = _m_paddw(R, E);
+    R = _m_paddw(R, G);
+    T[0] = _mm_srai_pi16(R, 3);
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21291.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21291.c
new file mode 100644
index 000000000..b59750985
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21291.c
@@ -0,0 +1,36 @@
+/* The asm has 2 "r" in/out operands, 1 earlyclobber "r" output, 1 "r"
+   input and 2 fixed "r" clobbers (eax and edx), so there are a total of
+   6 registers that must not conflict.  Add to that the PIC register,
+   the frame pointer, and the stack pointer, and we've run out of
+   registers on 32-bit targets.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+typedef unsigned long bngdigit;
+typedef bngdigit *bng;
+typedef unsigned int bngcarry;
+typedef unsigned long bngsize;
+
+bngdigit
+bng_ia32_mult_sub_digit (bng a, bngsize alen, bng b, bngsize blen, bngdigit d)
+{
+  bngdigit out, tmp;
+  bngcarry carry;
+  bngdigit a11;
+
+  alen -= blen;
+  out = 0;
+  asm (""
+       : "+r" (a), "+r" (b), "+mr" (blen), "+mr" (out), "=&r" (tmp)
+       : "mr" (d)
+       : "eax", "edx");
+  if (alen == 0)
+    {
+      a11 = out;
+      goto t;
+    }
+
+  a11 = 1;
+ t:
+  return a11;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21518.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21518.c
new file mode 100644
index 000000000..52cbed6f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr21518.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC -fno-tree-pre" } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target fpic } */
+
+extern void __attribute__ ((regparm (3)))
+drawPointsLines (char type, int first, int *dd);
+
+int
+do_locator (int *call)
+{
+  char prephitmp5;
+  int type;
+  int i;
+
+  if (call == 0)
+    prephitmp5 = 1;
+  else
+    {
+      type = *call;
+      i = 0;
+      do
+	{
+	  if (i != type)
+	    drawPointsLines ((int) (char) type, 0, call);
+	  i = i + 1;
+	}
+      while (i != 2);
+      prephitmp5 = (char) type;
+    }
+  drawPointsLines ((int) prephitmp5, 0, call);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22076.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22076.c
new file mode 100644
index 000000000..38b40a26b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22076.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fomit-frame-pointer -flax-vector-conversions -mmmx" } */
+/* { dg-options "-O2 -fomit-frame-pointer -flax-vector-conversions -mmmx -mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */
+
+#include <mmintrin.h>
+
+__v8qi test ()
+{
+  __v8qi mm0 = {1,2,3,4,5,6,7,8};
+  __v8qi mm1 = {11,22,33,44,55,66,77,88};
+  volatile __m64 x;
+
+  x = _mm_add_pi8 (mm0, mm1);
+
+  return x;
+}
+
+/* { dg-final { scan-assembler-times "movq" 3 } } */
+/* { dg-final { scan-assembler-not "movl" { target nonpic } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22152.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22152.c
new file mode 100644
index 000000000..b20a22a4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22152.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mtune=core2" } */
+/* { dg-additional-options "-mno-vect8-ret-in-mem" { target i?86-*-solaris2.9 *-*-vxworks* } } */
+/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
+
+#include <mmintrin.h>
+
+__m64
+unsigned_add3 (const __m64 * a, const __m64 * b, unsigned int count)
+{
+  __m64 sum;
+  unsigned int i;
+
+  for (i = 1; i < count; i++)
+    sum = _mm_add_si64 (a[i], b[i]);
+
+  return sum;
+}
+
+/* { dg-final { scan-assembler-times "movq\[ \\t\]+\[^\n\]*%mm" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22362.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22362.c
new file mode 100644
index 000000000..04d6b2706
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22362.c
@@ -0,0 +1,25 @@
+/* PR target/22362 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target ia32 } */
+
+register unsigned int reg0 __asm__ ("esi");
+register unsigned int reg1 __asm__ ("edi");
+register unsigned int reg2 __asm__ ("ebx");
+
+static unsigned int
+__attribute__((noinline))
+foo (unsigned long *x, void *y, void *z)
+{
+  int i;
+
+  for (i = 5; i > 0; i--)
+    x[i] = (unsigned long) foo ((unsigned long *) x[i], y, z);
+  return 0;
+}
+
+unsigned int
+bar (void)
+{
+  return foo (0, 0, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22432.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22432.c
new file mode 100644
index 000000000..86ae4b28f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22432.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+/* { dg-final { scan-assembler-not "paddb" } } */
+
+typedef int v2si __attribute__ ((__vector_size__ (8)));
+typedef short v4hi __attribute__ ((__vector_size__ (8)));
+typedef char v8qi __attribute__ ((__vector_size__ (8)));
+
+int
+foo (unsigned int *a, unsigned int *b)
+{
+  long long i, j, k;
+
+  i = (long long) __builtin_ia32_vec_init_v2si (*a, 0);
+  j = (long long) __builtin_ia32_vec_init_v2si (*b, 0);
+  i = (long long) __builtin_ia32_punpcklbw ((v8qi) i, (v8qi) 0ll);
+  j = (long long) __builtin_ia32_punpcklbw ((v8qi) j, (v8qi) 0ll);
+  k = (long long) __builtin_ia32_paddw ((v4hi) i, (v4hi) j);
+  return __builtin_ia32_vec_ext_v2si ((v2si) k, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22576.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22576.c
new file mode 100644
index 000000000..083fbf648
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22576.c
@@ -0,0 +1,10 @@
+/* PR target/22576 */
+/* Testcase reduced by Volker Reichelt */
+/* { dg-do compile } */
+/* { dg-options "-ffast-math" } */
+
+int
+foo (long double d)
+{
+  return d == 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22585.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22585.c
new file mode 100644
index 000000000..e5f027ce8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr22585.c
@@ -0,0 +1,12 @@
+/* PR target/22585 */
+/* Testcase reduced by Volker Reichelt */
+/* { dg-do compile } */
+/* { dg-options "-march=i386 -O -ffast-math" } */
+/* { dg-require-effective-target ia32 } */
+
+int
+foo (long double d, int i)
+{
+  if (d == (long double) i)
+    return 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23098.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23098.c
new file mode 100644
index 000000000..66ab0e122
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23098.c
@@ -0,0 +1,26 @@
+/* PR rtl-optimization/23098 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC" } */
+/* { dg-final { scan-assembler-not "\.LC\[0-9\]" { xfail *-*-vxworks* } } } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target fpic } */
+
+double foo (float);
+
+double
+f1 (void)
+{
+  return foo (1.0);
+}
+
+double
+f2 (void)
+{
+  return foo (0.0);
+}
+
+void
+f3 (float *x, float t)
+{
+  *x = 0.0 + t;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23268.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23268.c
new file mode 100644
index 000000000..b5645b297
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23268.c
@@ -0,0 +1,13 @@
+/* PR target/23268 */
+/* Testcase reduced by Andrew Pinski */
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffast-math" } */
+
+int
+f (float x)
+{
+  int a, b;
+  a = __builtin_log (2.f);
+  b = __builtin_lrint (x);
+  return (a + b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23376.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23376.c
new file mode 100644
index 000000000..0dee77f6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23376.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mmmx -funroll-loops -fvariable-expansion-in-unroller" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8)));
+typedef int __v2si __attribute__ ((__vector_size__ (8)));
+
+static __inline __m64 __attribute__((__always_inline__))
+_mm_add_pi32 (__m64 __m1, __m64 __m2)
+{
+  return (__m64) __builtin_ia32_paddd ((__v2si)__m1, (__v2si)__m2);
+}
+
+__m64
+simple_block_diff_up_mmx_4 (const int width, __m64 ref1)
+{
+  __m64 sum;
+  int count = width >>1;
+  while (count--)
+    sum = _mm_add_pi32 (sum, ref1);
+  return sum;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23570.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23570.c
new file mode 100644
index 000000000..1542663fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23570.c
@@ -0,0 +1,92 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef float __v4sf __attribute__ ((__vector_size__ (16)));
+typedef float __m128 __attribute__ ((__vector_size__ (16)));
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+static __inline __m128
+_mm_cmpeq_ps (__m128 __A, __m128 __B)
+{
+  return (__m128) __builtin_ia32_cmpeqps ((__v4sf)__A, (__v4sf)__B);
+}
+
+static __inline __m128
+_mm_setr_ps (float __Z, float __Y, float __X, float __W)
+{
+  return __extension__ (__m128)(__v4sf){__Z, __Y, __X, __W };
+}
+
+static __inline __m128
+_mm_and_si128 (__m128 __A, __m128 __B)
+{
+  return (__m128)__builtin_ia32_pand128 ((__v2di)__A, (__v2di)__B);
+}
+
+static __inline __m128
+_mm_or_si128 (__m128 __A, __m128 __B)
+{
+  return (__m128)__builtin_ia32_por128 ((__v2di)__A, (__v2di)__B);
+}
+
+typedef union
+{
+  __m128 xmmi;
+  int si[4];
+}
+__attribute__ ((aligned (16))) um128;
+
+um128 u;
+
+static inline int
+sse_max_abs_indexf (float *v, int step, int n)
+{
+  __m128 m1, mm;
+  __m128 mim, mi, msk;
+  um128 u, ui;
+  int n4, step2, step3;
+  mm = __builtin_ia32_andps ((__m128) (__v4sf)
+			     { 0.0, v[step], v[step2], v[step3] }
+			     , u.xmmi);
+  if (n4)
+    {
+      int i;
+      for (i = 0; i < n4; ++i);
+      msk = (__m128) _mm_cmpeq_ps (m1, mm);
+      mim = _mm_or_si128 (_mm_and_si128 (msk, mi), mim);
+    }
+  ui.xmmi = (__m128) mim;
+  return ui.si[n];
+}
+
+static void
+sse_swap_rowf (float *r1, float *r2, int n)
+{
+  int n4 = (n / 4) * 4;
+  float *r14end = r1 + n4;
+  while (r1 < r14end)
+    {
+      *r1 = *r2;
+      r1++;
+    }
+}
+
+void
+ludcompf (float *m, int nw, int *prow, int n)
+{
+  int i, s = 0;
+  float *pm;
+  for (i = 0, pm = m; i < n - 1; ++i, pm += nw)
+    {
+      int vi = sse_max_abs_indexf (pm + i, nw, n - i);
+      float *pt;
+      int j;
+      if (vi != 0)
+	{
+	  sse_swap_rowf (pm, pm + vi * nw, nw);
+	  swap_index (prow, i, i + vi);
+	}
+      for (j = i + 1, pt = pm + nw; j < n; ++j, pt += nw)
+	sse_add_rowf (pt + i + 1, pm + i + 1, -1.0, n - i - 1);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23575.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23575.c
new file mode 100644
index 000000000..522226ef7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23575.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+
+/* We used to ICE because of a bogous pattern.  */
+
+typedef double __v2df __attribute__ ((__vector_size__ (16)));
+typedef __v2df __m128d;
+static __inline __m128d __attribute__((__always_inline__)) _mm_set1_pd (double __F) {
+  return __extension__ (__m128d){__F, __F};
+}
+static __inline __m128d __attribute__((__always_inline__)) _mm_move_sd (__m128d __A, __m128d __B) {
+  return (__m128d) __builtin_ia32_movsd ((__v2df)__A, (__v2df)__B);
+}
+void g(__m128d b);
+__m128d cross(__m128d tmp9)
+{
+  __m128d t1 = _mm_set1_pd(1.0);
+  __m128d tmp10 = _mm_move_sd(t1, tmp9);
+  return tmp10;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23943.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23943.c
new file mode 100644
index 000000000..d70e5a6b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr23943.c
@@ -0,0 +1,21 @@
+/* This used to ICE in side_effects_p, due to a problem in cse.c.
+   Origin: marcus at jet dot franken dot de.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fPIC" } */
+
+__extension__ typedef __SIZE_TYPE__ size_t;
+
+extern size_t strlen (__const char *__s)
+    __attribute__ ((__nothrow__)) __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1)));
+
+static char savecallsin[256] = "";
+
+int read_agent_config(void)
+{
+  savecallsin[0] = '\0';
+
+  if (savecallsin[strlen(savecallsin) - 1] != '/')
+    __builtin___strncat_chk (savecallsin, "/", sizeof(savecallsin) - strlen(savecallsin) - 1, __builtin_object_size (savecallsin, 2 > 1)) ;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24055.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24055.c
new file mode 100644
index 000000000..5190ec4b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24055.c
@@ -0,0 +1,26 @@
+/* PR target/24055 */
+/* Testcase reduced by Serge Belyshev */
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+extern double rint(double);
+
+void foo_1 (int *p, double x)
+{
+  *p = rint (x);
+}
+
+void foo_2 (long long *p, double x)
+{
+  *p = rint (x);
+}
+
+int foo_3 (double x)
+{
+  return rint (x);
+}
+
+long long foo_4 (double x)
+{
+  return rint (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24178.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24178.c
new file mode 100644
index 000000000..b1a920813
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24178.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fdump-rtl-expand" } */
+
+struct S {
+    int l;
+    unsigned char c;
+};
+unsigned long f(unsigned char *p10) {
+    struct S *p = (struct S *) (p10 + 10);
+    return p->c;
+}
+
+/* The p->c memory access should have alignment of 4 bytes.  */
+
+/* { dg-final { scan-rtl-dump "MEM\[^\\n\]*A32" "expand" } } */
+/* { dg-final { cleanup-rtl-dump "expand" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24306.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24306.c
new file mode 100644
index 000000000..1319918c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24306.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+extern void abort(void);
+typedef int __attribute__ ((vector_size (16))) foo_t;
+
+struct s
+{
+  foo_t f[0];
+} s1;
+
+void
+check (int x, ...) __attribute__((noinline));
+void
+check (int x, ...)
+{
+  int y;
+  __builtin_va_list ap;
+
+  __builtin_va_start (ap, x);
+  __builtin_va_arg (ap, struct s);
+  y = __builtin_va_arg (ap, int);
+
+  if (y != 7)
+    abort ();
+}
+
+static void
+sse_test (void)
+{
+  check (3, s1, 7);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24315.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24315.c
new file mode 100644
index 000000000..dc6133eb9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr24315.c
@@ -0,0 +1,9 @@
+/* PR target/24315 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -fpeephole2" } */
+
+void s48_double_to_bignum (int exponent)
+{
+  long length = ((((exponent) + ((((sizeof (long)) * 8) - 2) - 1)) /
+		  (((sizeof (long)) * 8) - 2)));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25196.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25196.c
new file mode 100644
index 000000000..6ebdee174
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25196.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-march=i386 -O3 -fomit-frame-pointer" } */
+
+/* For this test case, we used to do an invalid load motion after
+   reload, because we missed autoincrements of the stack pointer.  */
+
+extern void abort (void);
+
+static int j;
+
+static void __attribute__((noinline))
+f1 (int a, int b, int c, int d, int e)
+{
+  j = a;
+}
+
+int __attribute__((noinline))
+f2 (int a, int b, int c, int d, int e)
+{
+  if ((b & 0x1111) != 1)
+    f1 (a, b, c, d, e);
+  return 0;
+}
+
+int
+main (void)
+{
+  f2 (123, 0, 0, 0, 0);
+  if (j != 123)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25254.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25254.c
new file mode 100644
index 000000000..ad602024c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25254.c
@@ -0,0 +1,12 @@
+/* PR target/25254 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mcmodel=medium -mlarge-data-threshold=1" } */
+
+const struct { int i; int j; } c = { 2, 6 };
+
+const char *
+foo (void)
+{
+  return "OK";
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25293.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25293.c
new file mode 100644
index 000000000..94923aba1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25293.c
@@ -0,0 +1,51 @@
+/* PR target/25293 */
+/* { dg-do compile } */
+/* { dg-options "-mpreferred-stack-boundary=2 -mtune=i586 -O2 -fomit-frame-pointer -g" } */
+/* { dg-require-effective-target ia32 } */
+
+struct T { unsigned short t1, t2, t3, t4, t5, t6, t7; };
+struct S { struct T s1; unsigned short s2, s3; };
+unsigned short v1;
+int f1 (void);
+int f2 (struct T);
+int f3 (const char *);
+
+int
+foo (struct S *x, struct T y)
+{
+  unsigned short a, b, c;
+  unsigned long d, e;
+  int f = 0;
+  y.t6 = 6;
+  a = y.t7;
+  b = y.t6;
+  c = y.t7;
+  switch (a)
+    {
+    case 8:
+    case 7:
+      c = 9;
+      break;
+    case 1:
+    case 6:
+    case 3:
+      b = 16;
+      c = 9;
+      break;
+    }
+  if ((f = f1 ()))
+    goto error;
+  if ((f = f2 (y)))
+    goto error;
+  d = (long) &y;
+  e = (long) &x->s1;
+  __asm __volatile ("" : "+D" (e), "+S" (d) :: "memory");
+  x->s2 = b;
+  x->s3 = c;
+  f3 ("foo");
+  return 0;
+error:
+  if (v1 >= 1)
+    f3 ("bar");
+  return f;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25654.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25654.c
new file mode 100644
index 000000000..d53a29794
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25654.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=2 -march=i686 -frename-registers" } */
+
+extern void abort (void) __attribute__((noreturn));
+
+struct wrapper {
+union setconflict
+{
+  short a[20];
+  int b[10];
+} a;
+};
+
+int
+main ()
+{
+  int sum = 0;
+  {
+    struct wrapper a;
+    short *c;
+    c = a.a.a;
+    asm ("": "=r" (c):"0" (c));
+    *c = 0;
+    asm ("": "=r" (c):"0" (c));
+    sum += *c;
+  }
+  {
+    struct wrapper a;
+    int *c;
+    c = a.a.b;
+    asm ("": "=r" (c):"0" (c));
+    *c = 1;
+    asm ("": "=r" (c):"0" (c));
+    sum += *c;
+  }
+
+  if (sum != 1)
+    abort();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25993.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25993.c
new file mode 100644
index 000000000..b079e257f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr25993.c
@@ -0,0 +1,18 @@
+/* { dg-do assemble } */
+/* { dg-skip-if "" { "*-*-darwin*" "*-*-mingw*" } { "*" } { "" } } */
+/* { dg-options "-std=c99 -x assembler-with-cpp" } */
+
+#ifndef __ASSEMBLER__
+extern int func(void);
+#else
+#ifdef __sun__
+.globl func
+#else
+.global func
+#endif
+.type func,@function
+.align 4
+func:
+        ret
+.size func,.-func
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26449-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26449-1.c
new file mode 100644
index 000000000..b4ef78048
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26449-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mtune=k8" } */
+
+typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+void sse2_test (void)
+{
+  union
+  {
+    __m128i x;
+  } val1, res[8], tmp;
+  short ins[8] = { 8, 5, 9, 4, 2, 6, 1, 20 };
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      tmp.x = val1.x;
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+        (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi) val1.x, ins[i], 0);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26449.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26449.c
new file mode 100644
index 000000000..4a976ff7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26449.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O1 -ftree-vectorize -march=pentium4 -std=c99" } */
+
+void matmul_i4 (int bbase_yn, int xcount)
+{
+  int x;
+  int * restrict dest_y;
+  const int * abase_n;
+
+  for (x = 0;  x < xcount;  x++)
+    {
+      dest_y[x] += abase_n[x] * bbase_yn;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26600.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26600.c
new file mode 100644
index 000000000..bbe0663da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26600.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O -ftree-vectorize -msse2" } */
+
+void foo(int *p, int N)
+{
+    int i;
+    for (i=0; i<8; ++i, ++p)
+    {
+        int j = N+2*(N+p[0]), k = 2*N+p[0];
+        p[0] = j+N;
+        p[5] = j+k;
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26778.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26778.c
new file mode 100644
index 000000000..f871b5d61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26778.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=pentium3" } */
+
+typedef union {
+  long long l;
+  double d;
+} db_number;
+
+double test(double x[3]) {
+  double th = x[1] + x[2];
+  if (x[2] != th - x[1]) {
+    db_number thdb;
+    thdb.d = th;
+    thdb.l++;
+    th = thdb.d;
+  }
+  return x[0] + th;
+}
+
+/* { dg-final { scan-assembler-not "mov.ps" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26826.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26826.c
new file mode 100644
index 000000000..062e1737f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr26826.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O -fomit-frame-pointer -march=i586" } */
+
+void foo(char* p, char c, int i)
+{
+    char a[2], *q=a+1;
+    if (p && i)
+        *p = q-a+bar(i);
+    if (c)
+        bar(i);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27266.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27266.c
new file mode 100644
index 000000000..8735780c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27266.c
@@ -0,0 +1,14 @@
+/* PR target/27266.
+   The testcase below used to trigger an ICE.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-march=pentium" } */
+
+signed long long sll;
+
+void
+foo (void)
+{
+  __sync_fetch_and_add (&sll, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27696.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27696.c
new file mode 100644
index 000000000..2f281e3f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27696.c
@@ -0,0 +1,11 @@
+/* PR target/27696
+   The testcase below uses to trigger an ICE.  */
+
+/* { dg-do compile } */
+/* { dg-options "-msse3" } */
+
+void
+foo (void const * P, unsigned int E, unsigned int H)
+{
+  __builtin_ia32_monitor (P, E, H);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27790.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27790.c
new file mode 100644
index 000000000..e8986c415
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27790.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O -ftree-vectorize -msse2" } */
+
+void binarize (int npixels, unsigned char *b)
+{
+  int i;
+  for (i = 0; i < npixels; i++)
+    b[i] = (b[i] > 225 ? 0xff : 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27827.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27827.c
new file mode 100644
index 000000000..3b337444a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27827.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mfpmath=387" } */
+
+double a, b;
+double f(double c)
+{
+  double x = a * b;
+  return x + c * a;
+}
+
+/* { dg-final { scan-assembler-not "fld\[ \t\]*%st" } } */
+/* { dg-final { scan-assembler "fmul\[ \t\]*%st" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27971.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27971.c
new file mode 100644
index 000000000..27888de6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr27971.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned array[4];
+
+#ifdef _WIN64
+__extension__ typedef unsigned long long TYPE;
+#else
+#define TYPE unsigned long
+#endif
+
+unsigned foo(TYPE x)
+{
+          return array[(x>>2)&3ul];
+}
+
+/* { dg-final { scan-assembler-not "shr\[^\\n\]*2" } } */
+/* { dg-final { scan-assembler "and\[^\\n\]*12" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr28839.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr28839.c
new file mode 100644
index 000000000..6a215164c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr28839.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize -funswitch-loops" } */
+
+static int ready[10];
+void abort (void);
+void test_once (int t,int t1)
+{
+  int i, repeat;
+  for (i = 0; i < 10; i++)
+    {
+      ready[i] = 0;
+      if (t1)
+	if (b())
+	  abort ();
+    }
+  if (t)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr28946.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr28946.c
new file mode 100644
index 000000000..327207977
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr28946.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fno-ident" } */
+/* { dg-final { scan-assembler-not "test" } } */
+
+int fct1 (void);
+int fct2 (void);
+
+int
+fct (unsigned nb)
+{
+  if ((nb >> 5) != 0)
+    return fct1 ();
+  else
+    return fct2 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr29978.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr29978.c
new file mode 100644
index 000000000..e27bbdcd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr29978.c
@@ -0,0 +1,16 @@
+/* PR target/29978 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+void g ();
+
+void
+f (long long v)
+{
+  if (v > 0xfffffffffLL)
+    g ();
+  g ();
+}
+
+/* Verify there are no redundant jumps jl .L2; jle .L2 */
+/* { dg-final { scan-assembler-not "jl\[^e\]*\\.L" { target ia32 } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30120.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30120.c
new file mode 100644
index 000000000..22fd843a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30120.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math" } */
+
+extern void abort (void);
+
+static void
+foo (double a, double weight, const double *ring, double *phase)
+{
+  *phase = *ring * weight;
+}
+
+void
+foo2 (void)
+{
+  foo (0, 1, (double *) 0, (double *) 0);
+}
+
+int
+main (void)
+{
+  double t1 = 1, c1;
+  foo (0, 1, &t1, &c1);
+  if (c1 < 0.5)
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30315.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30315.c
new file mode 100644
index 000000000..557b4f751
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30315.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "cmp" } } */
+
+extern void abort (void);
+int c;
+
+#define PLUSCC1(T, t, C)	\
+T pluscc##t##C (T a, T b)	\
+{	\
+  T sum = a + b;	\
+  if (sum < C)		\
+    abort ();		\
+  return sum;		\
+}
+#define PLUSCC(T, t) PLUSCC1(T, t, a) PLUSCC1(T, t, b)
+
+#define INCCC1(T, t, C)	\
+T inccc##t##C (T a, T b)	\
+{	\
+  T sum = a + b;	\
+  if (sum < C)		\
+    c ++;		\
+  return sum;		\
+}
+#define INCCC(T, t) INCCC1(T, t, a) INCCC1(T, t, b)
+
+#define PLUSCCONLY1(T, t, C)	\
+void pluscconly##t##C (T a, T b)	\
+{	\
+  T sum = a + b;	\
+  if (sum < C)		\
+    abort ();		\
+}
+#define PLUSCCONLY(T, t) PLUSCCONLY1(T, t, a) PLUSCCONLY1(T, t, b)
+
+#define TEST(T, t)	\
+  PLUSCC(T, t)		\
+  PLUSCCONLY(T, t)	\
+  INCCC(T, t)
+
+TEST (unsigned long,  l)
+TEST (unsigned int,   i)
+TEST (unsigned short, s) 
+TEST (unsigned char,  c)
+
+#define PLUSCCZEXT(C)	\
+unsigned long pluscczext##C (unsigned int a, unsigned int b)	\
+{	\
+  unsigned int sum = a + b;	\
+  if (sum < C)		\
+    abort ();		\
+  return sum;		\
+}
+
+PLUSCCZEXT(a)
+PLUSCCZEXT(b)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30413.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30413.c
new file mode 100644
index 000000000..1d3a94f97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30413.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+int test() {
+  char a, b = -1;
+  asm volatile ("mov%z0 %1, %0" : "=q"(a) : "m"(b));
+  return a;
+}
+
+int main()
+{
+  if (test() != -1)
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30505.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30505.c
new file mode 100644
index 000000000..3cebbe695
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30505.c
@@ -0,0 +1,20 @@
+/* PR inline-asm/30505 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+unsigned long long a, c;
+unsigned int b, d;
+
+void
+test ()
+{
+  unsigned int e, f;
+
+  __asm__ ("divl %5;movl %1, %0;movl %4, %1;divl %5"
+	   : "=&rm" (e), "=a" (f), "=d" (d)
+	   : "1" ((unsigned int) (a >> 32)), "g" ((unsigned int) a),
+	     "rm" (b), "2" (0)
+	   : "cc");
+  c = (unsigned long long) e << 32 | f;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30848.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30848.c
new file mode 100644
index 000000000..2a9285151
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30848.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+
+void foo(double d)
+{
+  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30961-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30961-1.c
new file mode 100644
index 000000000..c7c5e5383
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30961-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2" } */
+
+double
+convert (long long in)
+{
+  double f;
+  __builtin_memcpy( &f, &in, sizeof( in ) );
+  return f;
+}
+
+/* { dg-final { scan-assembler-not "movapd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30970.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30970.c
new file mode 100644
index 000000000..96d64e5a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr30970.c
@@ -0,0 +1,15 @@
+/* { dg-do compile }
+/* { dg-options "-msse2 -O2 -ftree-vectorize" } */
+
+#define N 256
+int b[N];
+
+void test()
+{  
+  int i;
+
+  for (i = 0; i < N; i++)
+    b[i] = 0;
+}
+
+/* { dg-final { scan-assembler-times "pxor" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31167.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31167.c
new file mode 100644
index 000000000..43d9f848b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31167.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O" } */
+
+typedef int int32_t;
+
+int32_t round32hi (const __int128_t arg)
+{
+  const int SHIFT = 96;
+  const int mshift = 96;
+  const __int128_t M = (~(__int128_t) 0) << mshift;
+  const __int128_t L = (~M) + 1;
+  const __int128_t L1 = ((__int128_t) L) >> 1;
+  const __int128_t Mlo = ((__int128_t) (~M)) >> 1;
+  __int128_t vv = arg & M;
+
+  if ((arg & (L1)) && ((arg & Mlo) || (arg & L)))
+    vv += L;
+
+  return (int32_t) (vv >> SHIFT);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31486.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31486.c
new file mode 100644
index 000000000..7082d3de9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31486.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-msse -mno-sse2" } */
+
+typedef double __v2df __attribute__ ((vector_size (16)));
+
+__v2df b = { 1.1, 1.2 };
+
+extern __v2df a2 (__v2df a, __v2df b);
+
+void test2 ()
+{
+  b = a2 (b, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31628.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31628.c
new file mode 100644
index 000000000..eece2a0db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31628.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fPIC" } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target fpic } */
+
+typedef int tt, *lptt;
+
+int __attribute__((__stdcall__)) bar(lptt);
+
+int __attribute__((__stdcall__)) bar(tt *x)
+{
+  return 0;
+}
+
+int
+foo (void)
+{
+  return bar (0);
+}
+
+int
+main()
+{
+  return foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31854.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31854.c
new file mode 100644
index 000000000..6fcd20ef0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr31854.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -std=gnu99" } */
+
+_Decimal128 d128;
+long double tf;
+
+void foo (void)
+{
+  d128 = tf;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32000-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32000-1.c
new file mode 100644
index 000000000..9c7bfa24b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32000-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -msse2 -std=gnu99" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef struct { _Decimal128 f __attribute__((packed)); } packed;
+
+_Decimal128 __attribute__((noinline))
+foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4,
+     _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  _Decimal128 y = -1;
+  x.f = y;
+  y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32000-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32000-2.c
new file mode 100644
index 000000000..374b23f83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32000-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-skip-if "" { ! { ia32 && dfp } } { "*" } { "" } } */
+/* { dg-options "-O -msse2 -std=gnu99 -mpreferred-stack-boundary=2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef struct { _Decimal128 f __attribute__((packed)); } packed;
+
+_Decimal128 __attribute__((noinline))
+foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4,
+     _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  _Decimal128 y = -1;
+  x.f = y;
+  y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32065-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32065-1.c
new file mode 100644
index 000000000..eefea27f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32065-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-msse -std=gnu99" } */
+
+_Decimal128 test (void)
+{
+  return 1234123412341234.123412341234dl;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32065-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32065-2.c
new file mode 100644
index 000000000..5f055b59c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32065-2.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+/* { dg-require-effective-target dfp } */
+/* { dg-require-effective-target sse } */
+/* { dg-options "-Os -msse -std=gnu99" } */
+
+#include "sse-check.h"
+
+extern void abort (void);
+
+static void
+sse_test (void)
+{
+  if (7.999999999999999999999999999999999E6144dl + 3.0E6144dl
+      != __builtin_infd32 ())
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32191.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32191.c
new file mode 100644
index 000000000..f5238b01d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32191.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99" } */
+
+typedef _Complex float __attribute__((mode(TC))) _Complex128;
+
+_Complex128 foo (_Complex128 x, _Complex128 y)
+{
+  return x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32268.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32268.c
new file mode 100644
index 000000000..66ed50619
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32268.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target *-*-linux* *-*-gnu* } } */
+/* { dg-options "-O2" } */
+
+extern void abort(void);
+
+int __attribute__ ((__noinline__))
+test_lt(__float128 x, __float128 y)
+{
+  return x < y;
+}
+
+int __attribute__ ((__noinline__))
+test_gt (__float128 x, __float128 y)
+{
+  return x > y;
+}
+
+int main()
+{
+  __float128 a = 0.0;
+  __float128 b = 1.0;
+
+  int r;
+
+  r = test_lt (a, b);
+  if (r != ((double) a < (double) b))
+    abort();
+
+  r = test_gt (a, b);
+  if (r != ((double) a > (double) b))
+    abort();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32280-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32280-1.c
new file mode 100644
index 000000000..e8619fa7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32280-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2" } */
+
+__uint128_t
+t1 (__uint128_t a)
+{
+  return a << 8;
+}
+
+__uint128_t
+t2 (__uint128_t a)
+{
+  return a >> 8;
+}
+
+/* { dg-final { scan-assembler-not "pslldq" } } */
+/* { dg-final { scan-assembler-not "psrldq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32280.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32280.c
new file mode 100644
index 000000000..d48a635a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32280.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+__m128i foo1(__m128i __a)
+{
+ return (__m128i)__builtin_ia32_pslldqi128 (__a, 8);
+}
+
+__m128i foo2(__m128i __a)
+{
+ return (__m128i)__builtin_ia32_psrldqi128 (__a, 8);
+}
+
+/* { dg-final { scan-assembler "psrldq" } } */
+/* { dg-final { scan-assembler "pslldq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32389.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32389.c
new file mode 100644
index 000000000..24c27674c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32389.c
@@ -0,0 +1,11 @@
+/* Testcase by Mike Frysinger <vapier@gentoo.org>  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-msse" } */
+
+double f1();
+int f2() {
+  __builtin_ia32_stmxcsr();
+  return f1();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32661-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32661-1.c
new file mode 100644
index 000000000..39cd8f90c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32661-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+long long foo_0(__m128i* val)
+{
+  return __builtin_ia32_vec_ext_v2di(*val, 0);
+}
+
+long long foo_1(__m128i* val)
+{
+  return __builtin_ia32_vec_ext_v2di(*val, 1);
+}
+
+/* { dg-final { scan-assembler-times "mov" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32661.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32661.c
new file mode 100644
index 000000000..247ae1319
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32661.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+typedef float __v4sf __attribute__ ((__vector_size__ (16)));
+
+int fooSI_1(__v4si *val)
+{
+  return __builtin_ia32_vec_ext_v4si(*val, 1);
+}
+/* { dg-final { scan-assembler-not "pshufd" } } */
+
+int fooSI_2(__v4si *val)
+{
+  return __builtin_ia32_vec_ext_v4si(*val, 2);
+}
+/* { dg-final { scan-assembler-not "punpckhdq" } } */
+
+float fooSF_2(__v4sf *val)
+{
+  return __builtin_ia32_vec_ext_v4sf(*val, 2);
+}
+/* { dg-final { scan-assembler-not "unpckhps" } } */
+
+float fooSF_3(__v4sf *val)
+{
+  return __builtin_ia32_vec_ext_v4sf(*val, 3);
+}
+/* { dg-final { scan-assembler-not "shufps" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-1.c
new file mode 100644
index 000000000..c5308937b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+static __inline __m128i __attribute__((__always_inline__))
+_mm_set_epi64x (long long __q1, long long __q0)
+{
+  return __extension__ (__m128i)(__v2di){ __q0, __q1 };
+}
+
+__m128i long2vector(long long __i)
+{
+  return _mm_set_epi64x (0, __i);
+}
+
+/* { dg-final { scan-assembler-not "movq2dq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-2.c
new file mode 100644
index 000000000..f28caf91a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mtune=k8" } */
+
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+static __inline __m128i __attribute__((__always_inline__))
+_mm_set_epi64x (long long __q1, long long __q0)
+{
+  return __extension__ (__m128i)(__v2di){ __q0, __q1 };
+}
+
+__m128i long2vector(long long __i)
+{
+  return _mm_set_epi64x (0, __i);
+}
+
+/* { dg-final { scan-assembler-not "movq2dq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-3.c
new file mode 100644
index 000000000..77e50b241
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32708-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+
+static __inline __m128i __attribute__((__always_inline__))
+_mm_set_epi64x (long long __q1, long long __q0)
+{
+  return __extension__ (__m128i)(__v2di){ __q0, __q1 };
+}
+
+__m128i long2vector(long long __i)
+{
+  return _mm_set_epi64x (0, __i);
+}
+
+/* { dg-final { scan-assembler-not "movq2dq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32961.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32961.c
new file mode 100644
index 000000000..a2326289a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr32961.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse2" } */
+
+#include <xmmintrin.h>
+
+void x (int n)
+{
+  __m128i a;
+  a = _mm_slli_epi32 (a, n);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33329.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33329.c
new file mode 100644
index 000000000..5aae9aa7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33329.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+
+extern void g (int *);
+
+void f (void)
+{
+  int tabs[1024], tabcount;
+
+  for (tabcount = 1; tabcount <= 8; tabcount += 7)
+    {
+      int i;
+      for (i = 0; i < 1024; i++)
+	tabs[i] = i * 12345;
+      g (tabs);
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33483.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33483.c
new file mode 100644
index 000000000..8fe2a946b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33483.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long double f1 (long double x)
+{
+  return __builtin_fmodl (x, x);
+}
+
+long double f2 (long double x)
+{
+  return __builtin_remainderl (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33552.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33552.c
new file mode 100644
index 000000000..68a81222e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33552.c
@@ -0,0 +1,41 @@
+/* PR rtl-optimization/33552 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+void
+__attribute__((noinline))
+foo (unsigned long *wp, unsigned long *up, long un, unsigned long *vp)
+{
+  long j;
+  unsigned long prod_low, prod_high;
+  unsigned long cy_dig;
+  unsigned long v_limb;
+  v_limb = vp[0];
+  cy_dig = 64;
+  for (j = un; j > 0; j--)
+    {
+      unsigned long u_limb, w_limb;
+      u_limb = *up++;
+      __asm__ (""
+               : "=r" (prod_low), "=r" (prod_high)
+               : "0" (u_limb), "1" (v_limb));
+      __asm__ ("mov %5, %1; add %5, %0"
+               : "=r" (cy_dig), "=&r" (w_limb)
+               : "0" (prod_high), "rm" (0), "1" (prod_low), "rm" (cy_dig));
+      *wp++ = w_limb;
+    }
+}
+
+int
+main (void)
+{
+  unsigned long wp[4];
+  unsigned long up[4] = { 0x1248, 0x248a, 0x1745, 0x1853 };
+  unsigned long vp = 0xdead;
+  foo (wp, up, 4, &vp);
+  if (wp[0] != 0x40 || wp[1] != 0xdeed || wp[2] != 0x1bd9a || wp[3] != 0x29c47)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33555.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33555.c
new file mode 100644
index 000000000..21c56b7bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33555.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "sbbl" } } */
+
+int test(unsigned long a, unsigned long b)
+{
+  return -(a < b);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33600.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33600.c
new file mode 100644
index 000000000..a2ab91e57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr33600.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+int f(int n)
+{
+        int x;
+
+        asm("" : "=&c"(n), "=r"(x) : "1"(n), "0"(n));
+
+        return n;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34012.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34012.c
new file mode 100644
index 000000000..00b1240d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34012.c
@@ -0,0 +1,25 @@
+/* PR rtl-optimization/34012 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+void bar (long int *);
+void
+foo (void)
+{
+  long int buf[10];
+  buf[0] = 0x0808080808080808;
+  buf[1] = 0x0808080808080808;
+  buf[2] = 0x0808080808080808;
+  buf[3] = 0x0808080808080808;
+  buf[4] = 0x0808080808080808;
+  buf[5] = 0x0808080808080808;
+  buf[6] = 0x0808080808080808;
+  buf[7] = 0x0808080808080808;
+  buf[8] = 0x0808080808080808;
+  buf[9] = 0x0808080808080808;
+  bar (buf);
+}
+
+/* Check that CSE did its job and fwprop hasn't undone it.  */
+/* { dg-final { scan-assembler-times "578721382704613384|0808080808080808" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34077.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34077.c
new file mode 100644
index 000000000..a2ec5d12b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34077.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -minline-all-stringops -minline-stringops-dynamically" } */
+
+#include <string.h>
+
+extern double ran(void);
+
+struct spec_fd_t {
+  int limit;
+  int len;
+  int pos;
+  unsigned char *buf;
+} spec_fd[3];
+
+int spec_random_load (int fd) {
+  int i, j;
+  char random_text[(32)][(128*1024)];
+
+  for (j = 0; j < (128*1024); j++) {
+    random_text[i][j] = (int)(ran()*256);
+  }
+
+  for (i = 0 ; i < spec_fd[fd].limit; i+= (128*1024)) {
+    memcpy(spec_fd[fd].buf + i, random_text[(int)(ran()*(32))],
+	   (128*1024));
+  }
+
+  spec_fd[fd].len = 1024*1024;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34215.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34215.c
new file mode 100644
index 000000000..9e194ff44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34215.c
@@ -0,0 +1,19 @@
+/* Testcase by Martin Michlmayr <tbm@cyrius.com> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2" } */
+
+double pow (double, double);
+
+void calc_score_dist (int mxdlen, long double d, long double **dist)
+{
+  unsigned long i, scr2;
+  for (i = 1; i <= mxdlen; i++)
+    {
+      for (scr2 = mxdlen; scr2 <= mxdlen + 10; scr2++)
+	{
+	}
+      dist[i][scr2] *= pow (1.0 / d, i);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34256.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34256.c
new file mode 100644
index 000000000..4ce7e30c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34256.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -fomit-frame-pointer -march=core2" } */
+
+#include <mmintrin.h>
+
+__m64 x;
+__m64 y;
+
+unsigned long long  foo(__m64 m) {
+  return _mm_cvtm64_si64(_mm_add_pi32(x, y));
+}
+
+/* { dg-final { scan-assembler-times "mov" 2 { target nonpic } } } */
+/* { dg-final { scan-assembler-times "mov" 4 { target { ! nonpic } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34283.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34283.c
new file mode 100644
index 000000000..60e11a509
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34283.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+__m128i _mm_set_epi64x (long long __q1, long long __q0)
+{
+  return __extension__ (__m128i)(__v2di){ __q0, __q1 };
+}
+
+/* { dg-final { scan-assembler-not "movdqa" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34312.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34312.c
new file mode 100644
index 000000000..876ac4040
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34312.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -march=pentium-m -fpic" } */
+
+typedef struct
+{
+  unsigned char seq[3];
+} JamoNormMap;
+
+static const JamoNormMap *
+JamoClusterSearch (JamoNormMap aKey, const JamoNormMap * aClusters,
+		   short aClustersSize)
+{
+  unsigned short l = 0, u = aClustersSize - 1;
+  unsigned short h = (l + u) / 2;
+
+  if ((aKey.seq[1] - aClusters[h].seq[1]) < 0)
+    return JamoClusterSearch (aKey, &(aClusters[l]), h - l);
+}
+
+short
+JamoSrchReplace (const JamoNormMap * aClusters, unsigned short aClustersSize,
+		 unsigned short * aIn, unsigned int * aLength,
+		 unsigned short aOffset)
+{
+  JamoNormMap key;
+
+  key.seq[0] = 0;
+  key.seq[1] = 1;
+  key.seq[2] = 2;
+
+  JamoClusterSearch (key, aClusters, aClustersSize);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34522.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34522.c
new file mode 100644
index 000000000..eb1e03a77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr34522.c
@@ -0,0 +1,13 @@
+/* { dg-options "-O2" } */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+
+int test(long long a, long long b)
+{
+        return a * b;
+}
+
+/* Check that we did not spill anything.  This is all that is needed
+   to qualify the generated code as "decent"...  */
+
+/* { dg-final { scan-assembler-not "%e\[sd\]i" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35083.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35083.c
new file mode 100644
index 000000000..c765d3254
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35083.c
@@ -0,0 +1,8 @@
+/* { dg-options "-O2 -mno-80387" } */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+
+float test (unsigned int x)
+{
+  return (float) x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35160.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35160.c
new file mode 100644
index 000000000..259c2a3ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35160.c
@@ -0,0 +1,32 @@
+/* PR inline-asm/35160 */
+/* { dg-do run } */
+/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+void
+__attribute__((noinline))
+foo (unsigned int *y)
+{
+   unsigned int c0, c1, c2, d0, d1, d2;
+   d0 = 0; d1 = 0; d2 = 0; c0 = c1 = c2 = 0;
+
+   __asm__ ("movl $7, %k0; movl $8, %k1; movl $9, %k2"
+	    : "+r" (d0), "+r" (d1), "+r" (d2));
+   __asm__ ("movl %3, %0; movl %4, %1; movl %5, %2"
+	    : "+r" (c0), "+r" (c1), "+r" (c2), "+r" (d0), "+r" (d1), "+r" (d2));
+   y[0] = c0;
+   y[1] = c1;
+   y[2] = c2;
+}
+
+int
+main (void)
+{
+  unsigned int y[3];
+  foo (y);
+  if (y[0] != 7 || y[1] != 8 || y[2] != 9)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35281.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35281.c
new file mode 100644
index 000000000..efd5c3d63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35281.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O2" } */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+
+unsigned long long a;
+unsigned int b;
+unsigned short c;
+
+unsigned long long mul32()
+{
+  return a * b;
+}
+
+unsigned long long mul16()
+{
+  return a * c;
+}
+
+/* { dg-final { scan-assembler-not "xor" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35540.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35540.c
new file mode 100644
index 000000000..00af637d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35540.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+int __attribute__ ((noinline))
+test (unsigned int *a, int b)
+{
+  return b ? 1 : __builtin_parity (*a);
+}
+
+int __attribute__ ((noinline))
+testl (unsigned long *a, int b)
+{
+  return b ? 1 : __builtin_parityl (*a);
+}
+
+int __attribute__ ((noinline))
+testll (unsigned long long *a, int b)
+{
+  return b ? 1 : __builtin_parityll (*a);
+}
+
+int
+main ()
+{
+  unsigned int a = 0;
+  unsigned long al;
+  unsigned long long all;
+
+  a = 0x12345670;
+  if (test (&a, 0))
+    abort ();
+
+  al = 0x12345670ul;
+  if (testl (&al, 0))
+    abort();
+
+#if 1
+  all = 0x12345678abcdef0ull;
+  if (testll (&all, 0))
+    abort ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35714.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35714.c
new file mode 100644
index 000000000..13ca47c23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35714.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+extern __m128i a;
+
+__m128i madd (__m128i b)
+{
+  return _mm_madd_epi16(a, b);
+}
+
+__m128i madd_swapped (__m128i b)
+{
+    return _mm_madd_epi16(b, a);
+}
+
+/* { dg-final { scan-assembler-not "movaps" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1.c
new file mode 100644
index 000000000..0945e19ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef struct { __m128 f __attribute__((packed)); } packed;
+
+__m128  __attribute__((noinline))
+foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4,
+     __m128 a5, __m128 a6, __m128 a7, __m128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  __m128 y = { 0 };
+  x.f = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1d.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1d.c
new file mode 100644
index 000000000..fa7d73f6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1d.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef struct { __m128d f __attribute__((packed)); } packed;
+
+__m128d  __attribute__((noinline))
+foo (__m128d a1, __m128d a2, __m128d a3, __m128d a4,
+     __m128d a5, __m128d a6, __m128d a7, __m128d a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  __m128d y = { 0 };
+  x.f = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1i.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1i.c
new file mode 100644
index 000000000..b76204802
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-1i.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef struct { __m128i f __attribute__((packed)); } packed;
+
+__m128i  __attribute__((noinline))
+foo (__m128i a1, __m128i a2, __m128i a3, __m128i a4,
+     __m128i a5, __m128i a6, __m128i a7, __m128i a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  __m128i y = { 0 };
+  x.f = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2.c
new file mode 100644
index 000000000..5457c4811
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef  __m128 __attribute__((aligned(1))) unaligned;
+
+__m128  __attribute__((noinline))
+foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4,
+     __m128 a5, __m128 a6, __m128 a7, __m128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y)
+{
+  return y;
+}
+
+void
+sse2_test (void)
+{
+  unaligned x;
+  __m128 y = { 0 };
+  x = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2d.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2d.c
new file mode 100644
index 000000000..cb9d74190
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2d.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef  __m128d __attribute__((aligned(1))) unaligned;
+
+__m128d  __attribute__((noinline))
+foo (__m128d a1, __m128d a2, __m128d a3, __m128d a4,
+     __m128d a5, __m128d a6, __m128d a7, __m128d a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y)
+{
+  return y;
+}
+
+void
+sse2_test (void)
+{
+  unaligned x;
+  __m128d y = { 0 };
+  x = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2i.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2i.c
new file mode 100644
index 000000000..f2dede9e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-2i.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef  __m128i __attribute__((aligned(1))) unaligned;
+
+__m128i  __attribute__((noinline))
+foo (__m128i a1, __m128i a2, __m128i a3, __m128i a4,
+     __m128i a5, __m128i a6, __m128i a7, __m128i a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y)
+{
+  return y;
+}
+
+void
+sse2_test (void)
+{
+  unaligned x;
+  __m128i y = { 0 };
+  x = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-3.c
new file mode 100644
index 000000000..19162cfe2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-3.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target dfp } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O -msse2 -std=gnu99" } */
+
+#include "sse2-check.h"
+
+typedef _Decimal128 unaligned __attribute__((aligned(1)));
+
+_Decimal128 __attribute__((noinline))
+foo (_Decimal128 a1, _Decimal128 a2, _Decimal128 a3, _Decimal128 a4,
+     _Decimal128 a5, _Decimal128 a6, _Decimal128 a7, _Decimal128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, unaligned y)
+{
+  return y;
+}
+
+void
+sse2_test (void)
+{
+  unaligned x;
+  _Decimal128 y = -1;
+  x = y;
+  y = foo (0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x, sizeof (y)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-4.c
new file mode 100644
index 000000000..1b58cfd4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-4.c
@@ -0,0 +1,14 @@
+/* Test that we generate aligned load when memory is aligned.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O -march=x86-64 -mtune=generic -std=gnu99" } */
+/* { dg-final { scan-assembler-not "movdqu" } } */
+/* { dg-final { scan-assembler "movdqa" { target { ! x86_64-*-mingw* } } } } */
+
+extern _Decimal128 foo (_Decimal128, _Decimal128, _Decimal128);
+
+void
+bar (void)
+{
+  foo (0, 0, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-5.c
new file mode 100644
index 000000000..4372d2e57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr35767-5.c
@@ -0,0 +1,17 @@
+/* Test that we generate aligned load when memory is aligned.  */
+/* { dg-do compile } */
+/* { dg-options "-O -msse2 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movups" } } */
+/* { dg-final { scan-assembler "movaps" } } */
+
+typedef float v4sf __attribute__ ((__vector_size__ (16)));
+
+extern void foo(v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf);
+
+int test(void)
+{
+  v4sf x = { 0.0, 1.0, 2.0, 3.0 };
+
+  foo (x, x, x, x, x, x, x, x, x);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36064.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36064.c
new file mode 100644
index 000000000..7964f280c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36064.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -march=core2" } */
+
+typedef long long ogg_int64_t;
+
+typedef struct vorbis_info
+{
+  long rate;
+} vorbis_info;
+
+typedef struct OggVorbis_File
+{
+  int seekable;
+  int links;
+  ogg_int64_t *pcmlengths;
+  vorbis_info *vi;
+  int ready_state;
+} OggVorbis_File;
+
+extern double ov_time_total (OggVorbis_File * vf, int i);
+extern int ov_pcm_seek_page (OggVorbis_File * vf, ogg_int64_t pos);
+
+int
+ov_time_seek_page (OggVorbis_File * vf, double seconds)
+{
+  int link = -1;
+  ogg_int64_t pcm_total = 0;
+  double time_total = 0.;
+
+  if (vf->ready_state < 2)
+    return (-131);
+  if (!vf->seekable)
+    return (-138);
+  if (seconds < 0)
+    return (-131);
+
+  for (link = 0; link < vf->links; link++)
+    {
+      double addsec = ov_time_total (vf, link);
+      if (seconds < time_total + addsec)
+	break;
+      time_total += addsec;
+      pcm_total += vf->pcmlengths[link * 2 + 1];
+    }
+
+  if (link == vf->links)
+    return (-131);
+
+  {
+    ogg_int64_t target =
+      pcm_total + (seconds - time_total) * vf->vi[link].rate;
+    return (ov_pcm_seek_page (vf, target));
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36073.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36073.c
new file mode 100644
index 000000000..b1587579e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36073.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O -march=core2 -mfpmath=sse,387 -ffast-math" } */
+
+extern double log (double x);
+extern int f (void);
+
+double cached_value;
+
+void g (void)
+{
+  cached_value = log (f ());
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36222-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36222-1.c
new file mode 100644
index 000000000..2d4c5b9b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36222-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+__m128i _mm_set_epi32 (int __q3, int __q2, int __q1, int __q0)
+{
+  return (__m128i)(__v4si){ __q0, __q1, __q2, __q3 };
+}
+
+/* { dg-final { scan-assembler-not "movdqa" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36246.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36246.c
new file mode 100644
index 000000000..51b8c349b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36246.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -fomit-frame-pointer -mtune=generic" } */
+
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+__m128i
+_mm_set_epi32 (int __q3, int __q2, int __q1, int __q0)
+{
+  return (__m128i)(__v4si){ __q0, __q1, __q2, __q3 };
+}
+
+/* { dg-final { scan-assembler-not "movq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36438.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36438.c
new file mode 100644
index 000000000..38376b8c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36438.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mmmx" } */
+
+#include <mmintrin.h>
+
+extern __m64 SetS16 (unsigned short, unsigned short,
+		     unsigned short, unsigned short);
+
+void foo(__m64* dest)
+{
+  __m64 mask = SetS16 (0x00FF, 0xFF00, 0x0000, 0x00FF);
+
+  mask = _mm_slli_si64(mask, 8);
+  mask = _mm_slli_si64(mask, 8);
+
+  *dest = mask;
+
+  _mm_empty ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36502.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36502.c
new file mode 100644
index 000000000..bc4c7ccf1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36502.c
@@ -0,0 +1,7 @@
+/* PR target/36502 */
+/* { dg-do compile { target { *-*-darwin* && ilp32 } } } */
+/* { dg-options "-O -fomit-frame-pointer -fno-pic" } */
+int a;
+void f() {a++;}
+/* { dg-final { scan-assembler-not "esp" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36533.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36533.c
new file mode 100644
index 000000000..8d71ece19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36533.c
@@ -0,0 +1,174 @@
+/* PR target/36533 */
+/* { dg-do run { target { mmap && ilp32 } } } */
+/* { dg-options "-Os" } */
+#include <string.h>
+#include <sys/mman.h>
+#ifndef MAP_ANONYMOUS
+#define MAP_ANONYMOUS MAP_ANON
+#endif
+
+typedef struct S1
+{
+  unsigned long s1;
+  struct S1 *s2;
+  char *s3;
+} S1;
+
+typedef struct
+{
+  unsigned int s4;
+  unsigned int s5;
+  int s6;
+  unsigned int *s7;
+} S2;
+
+typedef struct
+{
+  unsigned int s8;
+  unsigned short s9;
+  unsigned char s10;
+  unsigned char s11;
+  char s12[255];
+} S3;
+
+typedef struct
+{
+  unsigned int s4;
+  unsigned short s13;
+  unsigned short s14;
+} S4;
+
+typedef struct
+{
+  char s15[16];
+  unsigned long s16;
+} S5;
+
+typedef struct
+{
+  char s15[48];
+  S5 *s17;
+} S6;
+
+typedef struct
+{
+  S1 *s18;
+} S7;
+
+__attribute__((regparm (3), noinline)) int
+fn1 (const char *x, void *y, S1 *z)
+{
+  asm volatile ("" : : : "memory");
+  return *x + (y != 0);
+}
+
+__attribute__((regparm (3), noinline)) int
+fn2 (const char *x, int y, S2 *z)
+{
+  asm volatile ("" : : : "memory");
+  return 0;
+}
+
+static inline __attribute__ ((always_inline)) unsigned int
+fn4 (unsigned short x)
+{
+  unsigned len = x;
+  if (len == ((1 << 16) - 1))
+    return 1 << 16;
+  return len;
+}
+
+static inline __attribute__ ((always_inline)) S3 *
+fn3 (S3 *p)
+{
+  return (S3 *) ((char *) p + fn4 (p->s9));
+}
+
+__attribute__((regparm (3), noinline)) int
+fn5 (void)
+{
+  asm volatile ("" : : : "memory");
+  return 0;
+}
+
+static inline __attribute__ ((always_inline)) int
+fn6 (S3 *w, int x, S2 *y, S4 *z)
+{
+  int a = 2;
+  char *b = (char *) w;
+  S2 c = *y;
+
+  while ((char *) w < b + x - 2 * sizeof (S4))
+    {
+      if (w->s10 && w->s8)
+	{
+	  fn2 (w->s12, w->s10, &c);
+	  z--;
+	  z->s4 = c.s4;
+	  z->s13 = (unsigned short) ((char *) w - b);
+	  z->s14 = w->s9;
+	  a++;
+	  fn5 ();
+	}
+
+      w = fn3 (w);
+    }
+  return a;
+}
+
+__attribute__((regparm (3), noinline)) unsigned int
+test (void *u, S6 *v, S1 **w, S7 *x, S2 *y, S1 *z)
+{
+  unsigned b = v->s17->s16;
+  unsigned a;
+  S4 *c;
+  unsigned d, e, f, i;
+
+  fn1 (__func__, u, x->s18);
+  c = (S4 *) (z->s3 + b);
+  a = fn6 ((S3 *) (*w)->s3, b, y, c);
+  c -= a;
+  f = 0;
+  e = 2;
+  for (i = a - 1; ; i--)
+    {
+      if (f + (unsigned short) (c[i].s14 / 2) > b / 2)
+	break;
+      f += c[i].s14;
+      e++;
+    }
+  d = a - e;
+  return c[d].s4;
+}
+
+int main (void)
+{
+  char *p = mmap (NULL, 131072, PROT_READ | PROT_WRITE,
+		  MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+  S1 wb, z, *w;
+  S6 v;
+  S7 x;
+  S2 y;
+  S5 vb;
+  S4 s4;
+  if (p == MAP_FAILED)
+    return 0;
+  if (munmap (p + 65536, 65536) < 0)
+    return 0;
+  memset (&wb, 0, sizeof (wb));
+  memset (&z, 0, sizeof (z));
+  memset (&v, 0, sizeof (v));
+  memset (&x, 0, sizeof (x));
+  memset (&y, 0, sizeof (y));
+  memset (&vb, 0, sizeof (vb));
+  memset (&s4, 0, sizeof (s4));
+  s4.s14 = 254;
+  z.s3 = p + 65536 - 2 * sizeof (S4);
+  w = &wb;
+  v.s17 = &vb;
+  vb.s16 = 2 * sizeof (S4);
+  memcpy (z.s3, &s4, sizeof (s4));
+  memcpy (z.s3 + sizeof (s4), &s4, sizeof (s4));
+  test ((void *) 0, &v, &w, &x, &y, &z);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36578-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36578-1.c
new file mode 100644
index 000000000..5ede23a11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36578-1.c
@@ -0,0 +1,24 @@
+/* Test for unsafe floating-point conversions.  PR 36578.  */
+/* { dg-do run } */
+/* { dg-options "-msse2 -mfpmath=sse" } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-require-effective-target large_long_double } */
+
+#include "sse2-check.h"
+
+extern void abort (void);
+extern void exit (int);
+extern int printf(const char *, ...);
+
+volatile double d1 = 1.0;
+volatile double d2 = 0x1.00001p-53;
+volatile double d3;
+
+static void
+sse2_test (void)
+{
+  d3 = (double)((long double)d1 + (long double)d2);
+  if (d3 != d1)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36578-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36578-2.c
new file mode 100644
index 000000000..bfde2cb0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36578-2.c
@@ -0,0 +1,29 @@
+/* Test for unsafe floating-point conversions.  */
+/* { dg-do run } */
+/* { dg-options "-msse2 -mfpmath=sse" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+extern void abort (void);
+extern void exit (int);
+extern int printf(const char *, ...);
+
+volatile double d1 = 0x1.000001p0;
+volatile double d2 = 0x1p-54;
+volatile double d2d = 0x1p-52;
+volatile float f = 0x1.000002p0f;
+volatile float f2;
+
+static void
+sse2_test (void)
+{
+  if (sizeof(long double) > sizeof(double)  ) {
+	f2 = (float)((long double)d1 + (long double)d2);
+  } else {
+	f2 = (float)((long double)d1 + (long double)d2d);
+  }
+  if (f != f2)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36613.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36613.c
new file mode 100644
index 000000000..358e1cd72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36613.c
@@ -0,0 +1,44 @@
+/* { dg-do run { target { { i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } && ilp32 } } } */
+/* { dg-options "-Os" } */
+/* PR target/36613 */
+
+extern void abort (void);
+
+static inline int
+lshifts (int val, int cnt)
+{
+  if (val < 0)
+    return val;
+  return val << cnt;
+}
+
+static inline unsigned int
+lshiftu (unsigned int val, unsigned int cnt)
+{
+  if (cnt >= sizeof (unsigned int) * __CHAR_BIT__
+      || val > ((__INT_MAX__ * 2U) >> cnt))
+    return val;
+  return val << cnt;
+}
+
+static inline int
+rshifts (int val, unsigned int cnt)
+{
+  if (val < 0 || cnt >= sizeof (int) * __CHAR_BIT__)
+    return val;
+  return val >> cnt;
+}
+
+int
+foo (unsigned int val)
+{
+  return rshifts (1 + val, lshifts (lshiftu (val, val), 1));
+}
+
+int
+main (void)
+{
+  if (foo (1) != 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36753.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36753.c
new file mode 100644
index 000000000..2d43d42a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36753.c
@@ -0,0 +1,31 @@
+/* { dg-options "-O2" } */
+/* { dg-do run } */
+
+#if defined __i386__
+#define REG "edi"
+#else
+#define REG "r14"
+#endif
+
+register unsigned long *ds asm(REG);
+
+extern void abort (void);
+
+__attribute__ ((noinline)) void
+test (void)
+{
+  *++ds = 31337;
+}
+
+int
+main ()
+{
+  unsigned long stack[2];
+  stack[0] = 0;
+  stack[1] = 0;
+  ds = stack;
+  test ();
+  if (ds != stack + 1 || *ds != 31337)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36786.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36786.c
new file mode 100644
index 000000000..6b62e80e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36786.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+typedef int TItype __attribute__ ((mode (TI)));
+
+__floattisf (TItype u)
+{
+  DItype hi = u >> (8 * 8);
+  UDItype count, shift;
+  hi = u >> shift;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36992-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36992-1.c
new file mode 100644
index 000000000..345c1f276
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36992-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile }
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i
+test (__m128i b)
+{
+  return _mm_move_epi64 (b);
+}
+
+/* { dg-final { scan-assembler-times "movq\[ \\t\]+\[^\n\]*%xmm" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36992-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36992-2.c
new file mode 100644
index 000000000..25ff34be1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr36992-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile }
+/* { dg-options "-O2 -msse4" } */
+
+#include <emmintrin.h>
+
+__m128i
+test (__m128i b)
+{
+  return _mm_move_epi64 (b);
+}
+
+/* { dg-final { scan-assembler-times "movq\[ \\t\]+\[^\n\]*%xmm" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37101.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37101.c
new file mode 100644
index 000000000..8fd3bfc5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37101.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize -march=nocona" } */
+
+typedef __SIZE_TYPE__ size_t;
+extern void *malloc (size_t);
+extern void free (void *);
+
+typedef struct _Resource
+{
+  struct _Resource *next;
+  unsigned int id;
+} ResourceRec, *ResourcePtr;
+
+typedef struct _ClientResource
+{
+  ResourcePtr *resources;
+  int elements;
+  int buckets;
+  int hashsize;
+} ClientResourceRec;
+
+static ClientResourceRec clientTable[256];
+
+void
+RebuildTable (int client)
+{
+  int j;
+  ResourcePtr res, next;
+  ResourcePtr **tails, *resources;
+  ResourcePtr **tptr, *rptr;
+
+  j = 2 * clientTable[client].buckets;
+
+  tails =
+    (ResourcePtr **) malloc ((unsigned long) (j * sizeof (ResourcePtr *)));
+  resources =
+    (ResourcePtr *) malloc ((unsigned long) (j * sizeof (ResourcePtr)));
+
+  for (rptr = resources, tptr = tails; --j >= 0; rptr++, tptr++)
+    {
+      *rptr = ((ResourcePtr) ((void *) 0));
+      *tptr = rptr;
+    }
+
+  clientTable[client].hashsize++;
+  for (j = clientTable[client].buckets,
+       rptr = clientTable[client].resources; --j >= 0; rptr++)
+    {
+      for (res = *rptr; res; res = next)
+	{
+	  next = res->next;
+	  res->next = ((ResourcePtr) ((void *) 0));
+	  tptr = &tails[Hash (client, res->id)];
+	  **tptr = res;
+	  *tptr = &res->next;
+	}
+    }
+  free ((void *) tails);
+  clientTable[client].buckets *= 2;
+  free ((void *) clientTable[client].resources);
+  clientTable[client].resources = resources;
+}
+
+/* { dg-final { scan-assembler-not "movlps" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37184.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37184.c
new file mode 100644
index 000000000..14e11f707
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37184.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1" } */
+
+static inline unsigned int
+rshift_u_s (unsigned int left, int right)
+{
+  return left >> right;
+}
+
+unsigned int g_15;
+
+int func_29 (int p_30)
+{
+  unsigned int l_31;
+  unsigned long long int l_35 = 0x7736EAE11771B705LL;
+  unsigned int l_36 = 0xEDB553A8L;
+
+  l_31 = g_15;
+  if ((l_31 <
+       (rshift_u_s ((g_15 - (g_15 >= l_35)), (l_36 <= 1)))) + mod_rhs (1))
+    return 1;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37191.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37191.c
new file mode 100644
index 000000000..b315ce072
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37191.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mmmx" } */
+/* { dg-skip-if "no stdint" { vxworks_kernel } } */
+
+#include <mmintrin.h>
+#include <stddef.h>
+#include <stdint.h>
+
+extern const uint64_t ff_bone;
+
+static inline void transpose4x4(uint8_t *dst, uint8_t *src, ptrdiff_t dst_stride, ptrdiff_t src_stride) {
+    __m64 row0 = _mm_cvtsi32_si64(*(unsigned*)(src + (0 * src_stride)));
+    __m64 row1 = _mm_cvtsi32_si64(*(unsigned*)(src + (1 * src_stride)));
+    __m64 row2 = _mm_cvtsi32_si64(*(unsigned*)(src + (2 * src_stride)));
+    __m64 row3 = _mm_cvtsi32_si64(*(unsigned*)(src + (3 * src_stride)));
+    __m64 tmp0 = _mm_unpacklo_pi8(row0, row1);
+    __m64 tmp1 = _mm_unpacklo_pi8(row2, row3);
+    __m64 row01 = _mm_unpacklo_pi16(tmp0, tmp1);
+    __m64 row23 = _mm_unpackhi_pi16(tmp0, tmp1);
+    *((unsigned*)(dst + (0 * dst_stride))) = _mm_cvtsi64_si32(row01);
+    *((unsigned*)(dst + (1 * dst_stride))) = _mm_cvtsi64_si32(_mm_unpackhi_pi32(row01, row01));
+    *((unsigned*)(dst + (2 * dst_stride))) = _mm_cvtsi64_si32(row23);
+    *((unsigned*)(dst + (3 * dst_stride))) = _mm_cvtsi64_si32(_mm_unpackhi_pi32(row23, row23));
+}
+
+static inline void h264_loop_filter_chroma_intra_mmx2(uint8_t *pix, int stride, int alpha1, int beta1)
+{
+    asm volatile(
+        ""
+        :: "r"(pix-2*stride), "r"(pix), "r"((long)stride),
+           "m"(alpha1), "m"(beta1), "m"(ff_bone)
+    );
+}
+
+void h264_h_loop_filter_chroma_intra_mmx2(uint8_t *pix, int stride, int alpha, int beta)
+{
+
+    uint8_t trans[8*4] __attribute__ ((aligned (8)));
+    transpose4x4(trans, pix-2, 8, stride);
+    transpose4x4(trans+4, pix-2+4*stride, 8, stride);
+    h264_loop_filter_chroma_intra_mmx2(trans+2*8, 8, alpha-1, beta-1);
+    transpose4x4(pix-2, trans, stride, 8);
+    transpose4x4(pix-2+4*stride, trans+4, stride, 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37197.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37197.c
new file mode 100644
index 000000000..95565e802
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37197.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4" } */
+
+int testl (unsigned long *a, int b)
+{
+  return b ? 1 : __builtin_parityl (*a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37216.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37216.c
new file mode 100644
index 000000000..05eb2eea7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37216.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -msse2" } */
+/* { dg-options "-O3 -msse2 -mpe-aligned-commons" { target pe_aligned_commons } } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+int iarr[64];
+int iint = 0;
+
+void
+sse2_test (void)
+{
+  int i;
+
+  for (i = 0; i < 64; i++)
+    iarr[i] = -2;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-1.c
new file mode 100644
index 000000000..4107fd6e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-1.c
@@ -0,0 +1,20 @@
+/* PR middle-end/37248 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+struct S
+{
+  unsigned char a : 1;
+  unsigned char b : 1;
+  unsigned char c : 1;
+} s;
+
+int
+foo (struct S x)
+{
+  return x.a && x.b && x.c;
+}
+
+/* { dg-final { scan-tree-dump "& 7;" "optimized" } } */
+/* { dg-final { scan-tree-dump "== 7;" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-2.c
new file mode 100644
index 000000000..3ea4d6693
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-2.c
@@ -0,0 +1,24 @@
+/* PR middle-end/37248 */
+/* { dg-do compile { target { ! default_packed } } } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+struct S
+{
+  unsigned char a : 1;
+  unsigned char b : 1;
+  unsigned char c : 1;
+  unsigned int d : 26;
+  unsigned char e : 1;
+  unsigned char f : 1;
+  unsigned char g : 1;
+} s;
+
+int
+foo (struct S x)
+{
+  return x.a && x.g && x.b && x.f && x.c && x.e;
+}
+
+/* { dg-final { scan-tree-dump "& (3758096391|0x0e0000007);" "optimized" } } */
+/* { dg-final { scan-tree-dump "== (3758096391|0x0e0000007);" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-3.c
new file mode 100644
index 000000000..60ef71696
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37248-3.c
@@ -0,0 +1,26 @@
+/* PR middle-end/37248 */
+/* { dg-do compile { target { ! default_packed } } } */
+/* { dg-options "-O2 -fdump-tree-optimized -mno-ms-bitfields" } */
+
+struct S
+{
+  unsigned char a : 1;
+  unsigned char b : 1;
+  unsigned char c : 1;
+  unsigned int d : 6;
+  unsigned int e : 14;
+  unsigned int f : 6;
+  unsigned char g : 1;
+  unsigned char h : 1;
+  unsigned char i : 1;
+} s;
+
+int
+foo (struct S x)
+{
+  return x.a && x.i && x.b && x.h && x.c && x.g && x.e == 131;
+}
+
+/* { dg-final { scan-tree-dump "& (3766484487|0x0e07ffe07);" "optimized" } } */
+/* { dg-final { scan-tree-dump "== (3758163463|0x0e0010607);" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37275.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37275.c
new file mode 100644
index 000000000..cf748879e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37275.c
@@ -0,0 +1,138 @@
+/* PR middle-end/37275 */
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-g -dA -O2 -march=i686 -fstack-protector" } */
+/* { dg-require-visibility "" } */
+
+typedef __SIZE_TYPE__ size_t;
+extern void *memcpy (void *, const void *, size_t);
+extern void *malloc (size_t);
+
+typedef int A;
+
+struct B
+{
+  int x;
+};
+
+struct C
+{
+  struct F *c1;
+  void *c2;
+};
+
+enum D
+{
+  D0,
+  D1
+};
+
+struct E
+{
+  struct E *e1;
+  struct E *e2;
+  struct B e3;
+  void (*fn) (void *);
+  void *fn_data;
+  enum D e4;
+  _Bool e5;
+  _Bool e6;
+};
+
+struct F
+{
+  unsigned f1;
+  A f2;
+  int f3;
+};
+
+struct G
+{
+  void (*fn) (void *data);
+  void *data;
+  struct C g1;
+  struct E *t;
+};
+
+extern void fn1 (A * m);
+static inline void
+fn2 (A *x)
+{
+  if (!__sync_bool_compare_and_swap (x, 0, 1))
+    fn1 (x);
+}
+
+extern __thread struct G thr __attribute__ ((visibility ("hidden")));
+static inline struct G *
+fn3 (void)
+{
+  return &thr;
+}
+
+extern struct B *fn4 (void);
+extern struct B a;
+
+static inline struct B *
+fn5 (_Bool x)
+{
+  struct E *t = fn3 ()->t;
+  if (t)
+    return &t->e3;
+  else if (x)
+    return fn4 ();
+  else
+    return &a;
+}
+
+void
+fn6 (struct E *t, struct E *e1_t,
+		struct B *prev_e3)
+{
+  t->e1 = e1_t;
+  t->e3 = *prev_e3;
+  t->e4 = D0;
+  t->e5 = 0;
+  t->e6 = 0;
+  t->e2 = ((void *) 0);
+}
+
+void
+test (void (*fn) (void *), void *data, void (*cpyfn) (void *, void *), long x, long y, _Bool z)
+{
+  struct G *thr = fn3 ();
+  struct F *c1 = thr->g1.c1;
+  if (!z || c1 == 0 || (unsigned) c1->f3 > 64 * c1->f1)
+    {
+      struct E t;
+
+      fn6 (&t, thr->t, fn5 (0));
+      if (thr->t)
+	t.e6 = thr->t->e6;
+      thr->t = &t;
+      if (__builtin_expect (cpyfn != ((void *) 0), 0))
+	{
+	  char buf[x + y - 1];
+	  char *arg = (char *) (((unsigned long) buf + y - 1)
+				& ~(unsigned long) (y - 1));
+	  cpyfn (arg, data);
+	  fn (arg);
+	}
+    }
+  else
+    {
+      struct E *t;
+      struct E *e1 = thr->t;
+      char *arg;
+
+      t = malloc (sizeof (*t) + x + y - 1);
+      arg = (char *) (((unsigned long) (t + 1) + y - 1)
+		      & ~(unsigned long) (y - 1));
+      fn6 (t, e1, fn5 (0));
+      thr->t = t;
+      if (cpyfn)
+	cpyfn (arg, data);
+      else
+	memcpy (arg, data, x);
+      thr->t = e1;
+      fn2 (&c1->f2);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-1.c
new file mode 100644
index 000000000..b556bf084
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const short *val ) {
+  short D2073 = *val;
+  short D2076 = *(val + 2);
+  short D2079 = *(val + 4);
+  __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0};
+  return (__m128i)D2094;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-2.c
new file mode 100644
index 000000000..00ff9fd2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+
+typedef short __v8hi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const short *val ) {
+  short D2073 = *val;
+  short D2076 = *(val + 2);
+  short D2079 = *(val + 4);
+  __v8hi D2094 = {D2073, D2076, D2079, 0, D2073, D2076, D2079, 0};
+  return (__m128i)D2094;
+}
+
+/* { dg-final { scan-assembler "pinsrw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-3.c
new file mode 100644
index 000000000..2cc597b04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4.1" } */
+
+typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const char *val ) {
+  char D2073 = *val;
+  char D2074 = *(val + 1);
+  char D2075 = *(val + 2);
+  char D2076 = *(val + 3);
+  char D2077 = *(val + 4);
+  char D2078 = *(val + 5);
+  char D2079 = *(val + 6);
+  __v16qi D2094 = {D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0,
+  D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0};
+  return (__m128i)D2094;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-4.c
new file mode 100644
index 000000000..6848c6350
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37434-4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+__m128i Set_AC4R_SETUP_I( const char *val ) {
+  char D2073 = *val;
+  char D2074 = *(val + 1);
+  char D2075 = *(val + 2);
+  char D2076 = *(val + 3);
+  char D2077 = *(val + 4);
+  char D2078 = *(val + 5);
+  char D2079 = *(val + 6);
+  __v16qi D2094 = {D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0,
+  D2073, D2074, D2075, D2076,  D2077, D2078, D2079, 0};
+  return (__m128i)D2094;
+}
+
+/* { dg-final { scan-assembler "pinsrb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-1.c
new file mode 100644
index 000000000..981988223
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-1.c
@@ -0,0 +1,13 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target nonpic } } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=5" } */
+/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler "call\[\\t \]*_?foo" } } */
+/* { dg-final { scan-assembler-not "jmp\[\\t \]*_?foo" } } */
+
+extern int foo (void);
+
+int bar (void)
+{
+    return foo();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-2.c
new file mode 100644
index 000000000..fa177714a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-2.c
@@ -0,0 +1,13 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target nonpic } } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */
+/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */
+
+extern int foo (void);
+
+int bar (void)
+{
+    return foo();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-3.c
new file mode 100644
index 000000000..56f1170eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-3.c
@@ -0,0 +1,16 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target { ia32 && nonpic } } } */
+/* { dg-options "-O2 -msse2 -mpreferred-stack-boundary=4 -mstackrealign" } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */
+/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */
+
+#include <emmintrin.h>
+
+extern int foo (__m128, __m128, __m128, __m128);
+
+int bar (__m128 x1, __m128 x2, __m128 x3, __m128 x4)
+{
+    return foo (x1, x2, x3, x4);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-4.c
new file mode 100644
index 000000000..cd56bae41
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37843-4.c
@@ -0,0 +1,14 @@
+/* Test for stack alignment with sibcall optimization.  */
+/* { dg-do compile { target { ia32 && nonpic } } } */
+/* { dg-options "-O2 -msse2 -mpreferred-stack-boundary=4 -mstackrealign" } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */
+/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */
+
+extern int foo (void);
+
+int bar (void)
+{
+    return foo();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37870.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37870.c
new file mode 100644
index 000000000..19cfb2058
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr37870.c
@@ -0,0 +1,29 @@
+/* PR middle-end/37870 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+unsigned int
+foo (long double x)
+{
+  struct { char a[8]; unsigned int b:7; } c;
+  __builtin_memcpy (&c, &x, sizeof (c));
+  return c.b;
+}
+
+unsigned int
+bar (long double x)
+{
+  union { struct { char a[8]; unsigned int b:7; } c; long double d; } u;
+  u.d = x;
+  return u.c.b;
+}
+
+int
+main (void)
+{
+  if (foo (1.245L) != bar (1.245L)
+      || foo (245.67L) != bar (245.67L)
+      || foo (0.00567L) != bar (0.00567L))
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38151-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38151-1.c
new file mode 100644
index 000000000..6500a5029
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38151-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+void abort (void);
+
+struct S2848
+{
+  unsigned int a;
+  _Complex int b;
+};
+
+struct S2848 s2848;
+
+void __attribute__((noinline))
+check2848 (struct S2848 arg0)
+{
+  if (arg0.b != s2848.b)
+    abort ();
+}
+
+int main()
+{
+  s2848.a = 4027477739U;
+  s2848.b = (723419448 + -218144346 * __extension__ 1i);
+
+  check2848 (s2848);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38240.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38240.c
new file mode 100644
index 000000000..99e875894
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38240.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-msse" } */
+
+typedef float V
+  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+V __attribute__((target("sse"))) f(const V *ptr) { return *ptr; }
+
+V g(const V *ptr) { return *ptr; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38824.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38824.c
new file mode 100644
index 000000000..9fbfc502d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38824.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -mno-sse2" } */
+
+typedef float v4sf __attribute__ ((__vector_size__ (16)));
+
+void bench_1(float * out, float * in, float f, unsigned int n)
+{
+    n /= 4;
+    v4sf scalar = { f, f, f, f };
+    do
+    {
+        v4sf arg = *(v4sf *)in;
+        v4sf result = arg + scalar;
+        *(v4sf *) out = result;
+        in += 4;
+        out += 4;
+    }
+    while (--n);
+}
+
+/* { dg-final { scan-assembler-not "addps\[^\\n\]*%\[er\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38931.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38931.c
new file mode 100644
index 000000000..dd35dec75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38931.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8)));
+
+extern __m64 foo () ;
+
+void bar (const int input_bpl, const unsigned char *input,
+	  unsigned char *output, unsigned long x1)
+{
+  unsigned char *pix_end_ptr = output + x1 * 4;
+  __m64 m_original = { 0, 0 };
+  __m64 m_base_addr = __builtin_ia32_vec_init_v2si (0, input_bpl);
+  __m64 m_addr = __builtin_ia32_paddd (m_original, m_base_addr);
+  __m64 *a0 = (__m64 *) input;
+
+  for (; output < pix_end_ptr; output += 4)
+    {
+      a0 = (__m64 *) (input + __builtin_ia32_vec_ext_v2si (m_addr, 0));
+      m_addr = foo ();
+      __builtin_prefetch (a0, 0);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38988.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38988.c
new file mode 100644
index 000000000..8449cc69c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr38988.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fpic -mcmodel=large" } */
+
+__extension__ typedef __SIZE_TYPE__ size_t;
+typedef void (*func_ptr) (void);
+
+static func_ptr __DTOR_LIST__[1] = { (func_ptr) (-1) };
+
+void
+__do_global_dtors_aux (void)
+{
+  extern func_ptr __DTOR_END__[];
+  size_t dtor_idx = 0;
+  const size_t max_idx = __DTOR_END__ - __DTOR_LIST__ - 1;
+  func_ptr f;
+
+  while (dtor_idx < max_idx)
+    {
+      f = __DTOR_LIST__[++dtor_idx];
+      f ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39013-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39013-1.c
new file mode 100644
index 000000000..1bfab88b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39013-1.c
@@ -0,0 +1,15 @@
+/* PR target/39013 */
+/* { dg-do compile { target *-*-linux* *-*-gnu* } } */
+/* { dg-options "-O2 -fpie -std=gnu89" } */
+
+inline int foo (void);
+extern inline int bar (void);
+
+int
+main (void)
+{
+  return foo () + bar ();
+}
+
+/* { dg-final { scan-assembler "foo@PLT" } } */
+/* { dg-final { scan-assembler "bar@PLT" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39013-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39013-2.c
new file mode 100644
index 000000000..a85ce76e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39013-2.c
@@ -0,0 +1,15 @@
+/* PR target/39013 */
+/* { dg-do compile { target *-*-linux* *-*-gnu* } } */
+/* { dg-options "-O2 -fpie -std=gnu99" } */
+
+inline int foo (void);		/* { dg-warning "declared but never defined" } */
+extern inline int bar (void);	/* { dg-warning "declared but never defined" } */
+
+int
+main (void)
+{
+  return foo () + bar ();
+}
+
+/* { dg-final { scan-assembler "foo@PLT" } } */
+/* { dg-final { scan-assembler "bar@PLT" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39058.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39058.c
new file mode 100644
index 000000000..2982e8d14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39058.c
@@ -0,0 +1,34 @@
+/* PR inline-asm/39058 */
+/* { dg-options "-O2" } */
+
+double
+f1 ()
+{
+  double x;
+  asm ("" : "=r,r" (x) : "0,0" (x));
+  return x;
+}
+
+double
+f2 ()
+{
+  double x;
+  asm ("" : "=r" (x) : "0" (x));
+  return x;
+}
+
+double
+f3 ()
+{
+  double x, y;
+  asm ("" : "=r,r" (x), "=r,r" (y) : "%0,0" (x), "r,r" (0));
+  return x;
+}
+
+double
+f4 ()
+{
+  double x, y;
+  asm ("" : "=r" (x), "=r" (y) : "0" (x), "r" (0));
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39082-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39082-1.c
new file mode 100644
index 000000000..36d566dc1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39082-1.c
@@ -0,0 +1,35 @@
+/* PR target/39082 */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2" } */
+/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
+
+union un
+{
+  long double x;
+  int i;
+};
+
+extern int bar1 (union un);
+extern union un bar2 (int);
+
+int
+foo1 (union un u) /* { dg-message "note: the ABI of passing union with long double has changed in GCC 4.4" } */
+{
+  bar1 (u);
+  return u.i;
+}
+
+int
+foo2 (void)
+{
+  union un u;
+  u.i = 1;
+  return foo1 (u) + bar1 (u);
+}
+
+int
+foo3 (int x)
+{
+  union un u = bar2 (x);
+  return u.i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39139.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39139.c
new file mode 100644
index 000000000..e4cb845f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39139.c
@@ -0,0 +1,41 @@
+/* PR target/39139 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+#ifdef __x86_64__
+# define AX_REG asm ("rax")
+# define DI_REG asm ("rdi")
+# define SI_REG asm ("rsi")
+#else
+# define AX_REG asm ("eax")
+# define DI_REG asm ("edi")
+# define SI_REG asm ("esi")
+#endif
+
+__extension__ typedef __SIZE_TYPE__ size_t;
+
+static inline int
+foo (unsigned int x, void *y)
+{
+  register size_t r AX_REG;
+  register size_t a1 DI_REG;
+  register size_t a2 SI_REG;
+  a1 = (size_t) x;
+  a2 = (size_t) y;
+  asm volatile ("" : "=r" (r), "+r" (a1), "+r" (a2) : : "memory");
+  return (int) r;
+}
+
+struct T { size_t t1, t2; unsigned int t3, t4, t5; };
+
+int
+bar (size_t x, unsigned int y, size_t u, unsigned int v)
+{
+  long r;
+  struct T e = { .t1 = x, .t2 = u };
+
+  if (x << y != u << v)
+    return 5;
+  r = foo (11, &e);
+  return e.t3 == x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39162.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39162.c
new file mode 100644
index 000000000..efb46deae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39162.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-prune-output "ABI for passing parameters" } */
+/* { dg-options "-O2 -msse2 -mno-avx" } */
+/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__));
+
+extern __m256i y;
+
+void
+bar (__m256i x) /* { dg-warning "AVX" "" } */
+{
+  y = x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-1.c
new file mode 100644
index 000000000..16ba5d59f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-1.c
@@ -0,0 +1,18 @@
+/* PR middle-end/39315  */
+/* { dg-do compile } */
+/* { dg-options "-O -msse2 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movups" } } */
+/* { dg-final { scan-assembler-not "movlps" } } */
+/* { dg-final { scan-assembler-not "movhps" } } */
+/* { dg-final { scan-assembler "movaps" } } */
+
+typedef float __m128 __attribute__ ((__vector_size__ (16)));
+
+extern void bar (__m128 *);
+
+void
+foo (__m128 *x)
+{
+  __m128 b = *x;
+  bar (&b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-2.c
new file mode 100644
index 000000000..c1a3da75a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-2.c
@@ -0,0 +1,16 @@
+/* PR middle-end/39315  */
+/* { dg-do run } */
+/* { dg-options "-O -msse2 -mtune=generic" } */
+/* { dg-require-effective-target sse2_runtime } */
+/* { dg-additional-sources pr39315-check.c } */
+
+typedef float __m128 __attribute__ ((__vector_size__ (16)));
+
+extern void bar (__m128 *, int);
+
+void
+foo (__m128 *x)
+{
+  __m128 b = *x;
+  bar (&b, __alignof__ (x));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-3.c
new file mode 100644
index 000000000..3b61ad025
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-3.c
@@ -0,0 +1,19 @@
+/* PR middle-end/39315  */
+/* { dg-do compile } */
+/* { dg-options "-O -msse2 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movups" } } */
+/* { dg-final { scan-assembler-not "movlps" } } */
+/* { dg-final { scan-assembler-not "movhps" } } */
+/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" { target { ! x86_64-*-mingw* } } } } */
+/* { dg-final { scan-assembler "movaps" } } */
+
+typedef float __m128 __attribute__ ((__vector_size__ (16)));
+
+extern void bar (__m128 *);
+
+void
+foo (__m128 *x)
+{
+  __m128 b  __attribute__ ((aligned(128))) = *x;
+  bar (&b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-4.c
new file mode 100644
index 000000000..77258a7c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-4.c
@@ -0,0 +1,16 @@
+/* PR middle-end/39315  */
+/* { dg-do run } */
+/* { dg-options "-O -msse2 -mtune=generic" } */
+/* { dg-require-effective-target sse2_runtime } */
+/* { dg-additional-sources pr39315-check.c } */
+
+typedef float __m128 __attribute__ ((__vector_size__ (16)));
+
+extern void bar (__m128 *, int);
+
+void
+foo (__m128 *x)
+{
+  __m128 b __attribute__ ((aligned(128))) = *x;
+  bar (&b, __alignof__ (x));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-check.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-check.c
new file mode 100644
index 000000000..cb09d3f2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39315-check.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+
+typedef float __m128 __attribute__ ((__vector_size__ (16)));
+__extension__ typedef __PTRDIFF_TYPE__ ptrdiff_t;
+
+extern void foo (__m128 *);
+extern void abort (void);
+
+__m128 y = { 0.0, 1.0, 2.0, 3.0 };
+
+void
+bar (__m128 *x, int align)
+{
+  if ((((ptrdiff_t) x) & (align - 1)) != 0)
+    abort ();
+  if (__builtin_memcmp (x, &y, sizeof (y)) != 0)
+    abort ();
+}
+
+int
+main ()
+{
+  foo (&y);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39431.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39431.c
new file mode 100644
index 000000000..0db7d5643
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39431.c
@@ -0,0 +1,15 @@
+/* PR target/39431 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-options "-O2 -march=i686 -fpic" { target { ia32 && fpic } } } */
+
+extern void bar (char *, int);
+
+int
+foo (long long *p, long long oldv, long long *q, int n)
+{
+  char buf[n];
+  bar (buf, n);
+  p[256 + n] = __sync_val_compare_and_swap (p + n, oldv, oldv + 6);
+  return __sync_bool_compare_and_swap (q + n, oldv, oldv + 8);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39445.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39445.c
new file mode 100644
index 000000000..48e2d39a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39445.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-options "-Os -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef struct { __m128 f __attribute__((packed)); } packed;
+
+__m128  __attribute__((noinline))
+foo (__m128 a1, __m128 a2, __m128 a3, __m128 a4,
+     __m128 a5, __m128 a6, __m128 a7, __m128 a8,
+     int b1, int b2, int b3, int b4, int b5, int b6, int b7, packed y)
+{
+  return y.f;
+}
+
+void
+sse2_test (void)
+{
+  packed x;
+  __m128 y = { 0 };
+  x.f = y; 
+  y = foo (y, y, y, y, y, y, y, y, 1, 2, 3, 4, 5, 6, -1, x);
+  if (__builtin_memcmp (&y, &x.f, sizeof (y)) != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39482.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39482.c
new file mode 100644
index 000000000..4e2dfa724
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39482.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-sse2" } */
+
+extern double log (double __x);
+
+double foo (unsigned long int m_liOutputBufferLen)
+{
+  return log ((double) m_liOutputBufferLen);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39496.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39496.c
new file mode 100644
index 000000000..6efc0b8bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39496.c
@@ -0,0 +1,35 @@
+/* PR target/39496 */
+/* { dg-do compile { target { { i?86-*-linux* i?86-*-gnu* x86_64-*-linux* } && ia32 } } } */
+/* { dg-options "-O0 -fverbose-asm -fno-omit-frame-pointer -mtune=i686 -msse2 -mfpmath=sse" } */
+/* Verify that {foo,bar}{,2}param are all passed on the stack, using
+   normal calling conventions, when not optimizing.  */
+/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*fooparam," } } */
+/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*barparam," } } */
+/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*foo2param," } } */
+/* { dg-final { scan-assembler "\[^0-9-\]8\\(%ebp\\),\[^\n\]*bar2param," } } */
+
+static inline int foo (int fooparam)
+{
+  return fooparam;
+}
+
+static int bar (int barparam)
+{
+  return foo (barparam);
+}
+
+static inline double foo2 (double foo2param)
+{
+  return foo2param;
+}
+
+static double bar2 (double bar2param)
+{
+  return foo2 (bar2param);
+}
+
+int
+main ()
+{
+  return bar (0) + bar2 (0.0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-1.c
new file mode 100644
index 000000000..a8442b2e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-1.c
@@ -0,0 +1,52 @@
+/* PR inline-asm/39543 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fomit-frame-pointer" } */
+
+float __attribute__ ((aligned (16))) s0[128];
+const float s1 = 0.707;
+float s2[8] __attribute__ ((aligned (16)));
+float s3[8] __attribute__ ((aligned (16)));
+float s4[16] __attribute__ ((aligned (16)));
+float s5[16] __attribute__ ((aligned (16)));
+
+void
+foo (int k, float *x, float *y, const float *d, const float *z)
+{
+  float *a, *b, *c, *e;
+
+  a = x + 2 * k;
+  b = a + 2 * k;
+  c = b + 2 * k;
+  e = y + 2 * k;
+  __asm__ volatile (""
+		    : "=m" (x[0]), "=m" (b[0]), "=m" (a[0]), "=m" (c[0])
+		    : "m" (y[0]), "m" (y[k * 2]), "m" (x[0]), "m" (a[0])
+		    : "memory");
+  for (;;)
+    {
+      __asm__ volatile (""
+			:
+			: "m" (y[2]), "m" (d[2]), "m" (e[2]), "m" (z[2])
+			: "memory");
+      if (!--k)
+	break;
+    }
+  __asm__ volatile (""
+		    : "=m" (x[2]), "=m" (x[10]), "=m" (x[6]), "=m" (x[14])
+		    : "m" (y[2]), "m" (y[6]), "m" (x[2]), "m" (x[6]),
+		      "m" (y[18]), "m" (s1)
+		    : "memory");
+}
+
+void
+bar (float *a)
+{
+  foo (4, a, a + 16, s2, s3);
+  foo (8, a, a + 32, s4, s5);
+}
+
+void
+baz (void)
+{
+  bar (s0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-2.c
new file mode 100644
index 000000000..7f4e5a42a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-2.c
@@ -0,0 +1,52 @@
+/* PR inline-asm/39543 */
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+/* { dg-skip-if "" { ia32 && { ! nonpic } } { "*" } { "" } } */
+
+float __attribute__ ((aligned (16))) s0[128];
+const float s1 = 0.707;
+float s2[8] __attribute__ ((aligned (16)));
+float s3[8] __attribute__ ((aligned (16)));
+float s4[16] __attribute__ ((aligned (16)));
+float s5[16] __attribute__ ((aligned (16)));
+
+void
+foo (int k, float *x, float *y, const float *d, const float *z)
+{
+  float *a, *b, *c, *e;
+
+  a = x + 2 * k;
+  b = a + 2 * k;
+  c = b + 2 * k;
+  e = y + 2 * k;
+  __asm__ volatile (""
+		    : "=m" (x[0]), "=m" (b[0]), "=m" (a[0]), "=m" (c[0])
+		    : "m" (y[0]), "m" (y[k * 2]), "m" (x[0]), "m" (a[0])
+		    : "memory");
+  for (;;)
+    {
+      __asm__ volatile (""
+			:
+			: "m" (y[2]), "m" (d[2]), "m" (e[2]), "m" (z[2])
+			: "memory");
+      if (!--k)
+	break;
+    }
+  __asm__ volatile (""
+		    : "=m" (x[2]), "=m" (x[10]), "=m" (x[6]), "=m" (x[14])
+		    : "m" (y[2]), "m" (y[6]), "m" (x[2]), "m" (x[6]), "m" (s1)
+		    : "memory");
+}
+
+void
+bar (float *a)
+{
+  foo (4, a, a + 16, s2, s3);
+  foo (8, a, a + 32, s4, s5);
+}
+
+void
+baz (void)
+{
+  bar (s0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-3.c
new file mode 100644
index 000000000..4e103e671
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39543-3.c
@@ -0,0 +1,42 @@
+/* PR inline-asm/39543 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int s[128];
+
+void
+f1 (void)
+{
+  int i;
+  asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17"
+		: "=r" (i)
+		: "m" (s[0]), "m" (s[2]), "m" (s[4]), "m" (s[6]), "m" (s[8]),
+		  "m" (s[10]), "m" (s[12]), "m" (s[14]), "m" (s[16]), "m" (s[18]),
+		  "m" (s[20]), "m" (s[22]), "m" (s[24]), "m" (s[26]), "m" (s[28]),
+		  "m" (s[30]), "m" (s[32]));
+  asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17"
+		: "=r" (i)
+		: "m" (s[0]), "m" (s[2]), "m" (s[4]), "m" (s[6]), "m" (s[8]),
+		  "m" (s[10]), "m" (s[12]), "m" (s[14]), "m" (s[16]), "m" (s[18]),
+		  "m" (s[20]), "m" (s[22]), "m" (s[24]), "m" (s[26]), "m" (s[28]),
+		  "m" (s[30]), "m" (s[32]));
+}
+
+void
+f2 (int *q)
+{
+  int i;
+  int *p = q + 32;
+  asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17"
+		: "=r" (i)
+		: "m" (p[0]), "m" (p[2]), "m" (p[4]), "m" (p[6]), "m" (p[8]),
+		  "m" (p[10]), "m" (p[12]), "m" (p[14]), "m" (p[16]), "m" (p[18]),
+		  "m" (p[20]), "m" (p[22]), "m" (p[24]), "m" (p[26]), "m" (p[28]),
+		  "m" (p[30]), "m" (p[32]));
+  asm volatile ("# %0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17"
+		: "=r" (i)
+		: "m" (p[0]), "m" (p[2]), "m" (p[4]), "m" (p[6]), "m" (p[8]),
+		  "m" (p[10]), "m" (p[12]), "m" (p[14]), "m" (p[16]), "m" (p[18]),
+		  "m" (p[20]), "m" (p[22]), "m" (p[24]), "m" (p[26]), "m" (p[28]),
+		  "m" (p[30]), "m" (p[32]));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39545-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39545-1.c
new file mode 100644
index 000000000..e7e41164b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39545-1.c
@@ -0,0 +1,24 @@
+/* PR target/39545 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+struct flex
+{
+  int i;
+  int flex [];
+};
+
+int
+foo (struct flex s)
+{
+  return s.i;
+}
+
+struct flex
+bar (int x)
+{ /* { dg-message "note: the ABI of passing struct with a flexible array member has changed in GCC 4.4" } */
+  struct flex s;
+  s.i = x;
+  return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39545-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39545-2.c
new file mode 100644
index 000000000..46deecbe0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39545-2.c
@@ -0,0 +1,18 @@
+/* PR target/39545 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+struct flex
+{
+  int i;
+  int flex [];
+};
+
+struct flex
+foo (int x)
+{ /* { dg-message "note: the ABI of passing struct with a flexible array member has changed in GCC 4.4" } */
+  struct flex s;
+  s.i = x;
+  return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39592-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39592-1.c
new file mode 100644
index 000000000..a7f37043b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39592-1.c
@@ -0,0 +1,10 @@
+/* Test for ICE with C99-conforming excess precision and -msse.  PR
+   39592.  */
+/* { dg-do compile } */
+/* { dg-options "-ansi -msse" } */
+
+double
+foo (unsigned long var)
+{
+  return var;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39678.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39678.c
new file mode 100644
index 000000000..0548466d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39678.c
@@ -0,0 +1,19 @@
+/* PR target/39678 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2" } */
+
+struct X {
+  char c;
+  __complex__ float val;
+};
+
+struct X
+foo (float *p)
+{ /* { dg-message "note: the ABI of passing structure with complex float member has changed in GCC 4.4" } */
+  struct X x;
+  x.c = -3;
+  __real x.val = p[0];
+  __imag x.val = p[1];
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39804.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39804.c
new file mode 100644
index 000000000..3ff247908
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39804.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O" } */
+
+typedef unsigned char u8;
+struct __large_struct { unsigned long buf[100]; };
+static inline __attribute__((always_inline)) unsigned long
+__copy_from_user_inatomic(void *to, const void *from, unsigned long n)
+{
+  unsigned long ret = 0;
+  asm volatile("1:	mov""b"" %2,%""b""1\n" "2:\n"
+	       ".section .fixup,\"ax\"\n"
+	       "3:	mov %3,%0\n"
+	       "	xor""b"" %""b""1,%""b""1\n"
+	       "	jmp 2b\n"
+	       ".previous\n"
+	       " .section __ex_table,\"a\"\n"
+	       " " ".balign 4" " " "\n"
+	       " " ".long" " " "1b" "," "3b" "\n"
+	       " .previous\n"
+	       : "=r" (ret), "=q"(*(u8 *)to)
+	       : "m" ((*(struct __large_struct *)(from))), "i" (1), "0" (ret));
+  return ret;
+}
+void romchecksum(const unsigned char *rom, unsigned char c)
+{
+  unsigned char sum;
+  for (sum = 0;
+       !__copy_from_user_inatomic(&(c), ( typeof(c) *)(rom++), sizeof(c));)
+    sum += c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39911.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39911.c
new file mode 100644
index 000000000..8a78c0a28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr39911.c
@@ -0,0 +1,59 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+void 
+bar1 () 
+{
+  char foo;
+  asm volatile ("mov%z0 %1, %0": "=m" (foo): "iq" (-23));
+  asm volatile ("add%z0 %1, %0": "+m" (foo): "iq" (23));
+  asm volatile ("mov%z0 %1, %0": "=q" (foo): "iq" (-23));
+  asm volatile ("add%z0 %1, %0": "+q" (foo): "iq" (23));
+}
+
+void
+bar2 () 
+{
+  short foo;
+  asm volatile ("mov%z0 %1, %0": "=m" (foo): "ir" (-23));
+  asm volatile ("add%z0 %1, %0": "+m" (foo): "ir" (23));
+  asm volatile ("mov%z0 %1, %0": "=r" (foo): "ir" (-23));
+  asm volatile ("add%z0 %1, %0": "+r" (foo): "ir" (23));
+
+  asm volatile ("pop%z0 %0": "=m" (foo));
+  asm volatile ("pop%z0 %0": "=r" (foo));
+}
+
+void
+bar3 () 
+{
+  int foo;
+  asm volatile ("mov%z0 %1, %0": "=m" (foo): "ir" (-23));
+  asm volatile ("add%z0 %1, %0": "+m" (foo): "ir" (23));
+  asm volatile ("mov%z0 %1, %0": "=r" (foo): "ir" (-23));
+  asm volatile ("add%z0 %1, %0": "+r" (foo): "ir" (23));
+
+#ifndef __x86_64__
+  if (sizeof (void *) == sizeof (int))
+    {
+      asm volatile ("pop%z0 %0": "=m" (foo));
+      asm volatile ("pop%z0 %0": "=r" (foo));
+    }
+#endif
+}
+
+void
+bar4 () 
+{
+  if (sizeof (void *) == sizeof (long long))
+    {
+      long long foo;
+      asm volatile ("mov%z0 %1, %0": "=m" (foo): "er" (-23));
+      asm volatile ("add%z0 %1, %0": "+m" (foo): "er" (23));
+      asm volatile ("mov%z0 %1, %0": "=r" (foo): "er" (-23));
+      asm volatile ("add%z0 %1, %0": "+r" (foo): "er" (23));
+
+      asm volatile ("pop%z0 %0": "=m" (foo));
+      asm volatile ("pop%z0 %0": "=r" (foo));
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40718.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40718.c
new file mode 100644
index 000000000..1df3548e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40718.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O1 -foptimize-sibling-calls" } */
+
+void abort (void);
+
+struct S
+{
+  void (__attribute__((__stdcall__)) *f) (struct S *);
+  int i;
+};
+
+void __attribute__((__stdcall__))
+foo (struct S *s)
+{
+  s->i++;
+}
+
+void __attribute__((__stdcall__))
+bar (struct S *s)
+{
+  foo(s);
+  s->f(s);
+}
+
+int main (void)
+{
+  struct S s = { foo, 0 };
+
+  bar (&s);
+  if (s.i != 2)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40809.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40809.c
new file mode 100644
index 000000000..8b63e5526
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40809.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#define N 8
+
+unsigned int u4[N] = { 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u, 4000000000u };
+float f4[N];
+
+static void
+sse2_test (void)
+{
+  int j;
+
+  for (j = 0; j < N; j++)
+    f4[j] = u4[j];
+
+  /* check results:  */
+  for (j = 0; j < N; j++)
+    if (f4[j] != 4000000000.0)
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-1.c
new file mode 100644
index 000000000..233d8fdcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-1.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -mno-accumulate-outgoing-args" } */
+/* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args" { target *-*-mingw* *-*-cygwin* } } */
+
+void abort (void);
+
+void __attribute__((noinline))
+f (long double a)
+{
+  if (a != 1.23L)
+    abort ();
+}
+
+int __attribute__((noinline))
+g (long double b)
+{
+  f (b);
+  return 0;
+}
+
+int
+main (void)
+{
+  g (1.23L);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-2.c
new file mode 100644
index 000000000..58b076e1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-2.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -Wno-psabi -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -mno-accumulate-outgoing-args -m128bit-long-double" } */
+/* { dg-options "-O2 -Wno-psabi -fomit-frame-pointer -fno-asynchronous-unwind-tables -mpush-args -m128bit-long-double" { target *-*-mingw* *-*-cygwin* } } */
+
+void abort (void);
+
+void __attribute__((noinline))
+f (long double a)
+{
+  if (a != 1.23L)
+    abort ();
+}
+
+int __attribute__((noinline))
+g (long double b)
+{
+  f (b);
+  return 0;
+}
+
+int
+main (void)
+{
+  g (1.23L);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-3.c
new file mode 100644
index 000000000..13be303cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40906-3.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target *-*-linux* *-*-gnu* } } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -fomit-frame-pointer -fno-asynchronous-unwind-tables -msse2 -mpush-args -mno-accumulate-outgoing-args" } */
+
+#include "sse2-check.h"
+
+void __attribute__((noinline))
+f (__float128 a)
+{
+  if (a != 1.23Q)
+    abort ();
+}
+
+int __attribute__((noinline))
+g (__float128 b)
+{
+  f (b);
+  return 0;
+}
+
+static void
+sse2_test (void)
+{
+  g (1.23Q);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40934.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40934.c
new file mode 100644
index 000000000..651172299
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40934.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -march=i586 -ffast-math" } */
+
+extern double host_frametime;
+extern float pitchvel;
+V_DriftPitch (float delta, float move)
+{
+  if (!delta)
+    move = host_frametime;
+  if (delta > 0)
+    ;
+  else if (delta < 0 && move > -delta)
+    pitchvel = 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40957.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40957.c
new file mode 100644
index 000000000..b7ee26dff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr40957.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+typedef int __v8si __attribute__((__vector_size__(32)));
+typedef long long __m256i __attribute__((__vector_size__(32), __may_alias__));
+
+static __m256i
+_mm256_set1_epi32 (int __A)
+{
+  return __extension__ (__m256i)(__v8si){ __A, __A, __A, __A,
+					  __A, __A, __A, __A };
+}
+__m256i
+foo ()
+{
+  return _mm256_set1_epi32 (-1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41019.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41019.c
new file mode 100644
index 000000000..a6a2f4ee2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41019.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+long long int a[64];
+
+void
+sse2_test (void)
+{
+  int k;
+
+  for (k = 0; k < 64; k++)
+    a[k] = a[k] != 5 ? 12 : 10;
+
+  for (k = 0; k < 64; k++)
+    if (a[k] != 12)
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41442.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41442.c
new file mode 100644
index 000000000..feae791bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41442.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct LINK link;
+struct LINK
+{
+    link* next;
+};
+
+int haha(link* p1, link* p2)
+{
+  if ((p1->next && !p2->next) || p2->next)
+    return 0;
+
+  return 1;
+}
+
+/* { dg-final { scan-assembler-times "test|cmp" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41900.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41900.c
new file mode 100644
index 000000000..a23214c76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41900.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -mpreferred-stack-boundary=2" } */
+
+int main ()
+{
+  volatile unsigned code = 0xc3;
+
+  ((void (*)(void)) &code) ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "call\[ \\t\]+\\*%esp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41985.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41985.c
new file mode 100644
index 000000000..b38b6dc42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr41985.c
@@ -0,0 +1,11 @@
+/* PR target/41985 */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+int
+main ()
+{
+  int i;
+  asm volatile ("# %&": : "g" (i));	/* { dg-error "used without any local dynamic TLS references" } */
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1.c
new file mode 100644
index 000000000..761b91b18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1.c
@@ -0,0 +1,78 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2 -ftree-vectorize" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+unsigned int v1[] __attribute__ ((aligned(16))) =
+{
+  0x80000000, 1, 0xa0000000, 2,
+  3, 0xd0000000, 0xf0000000, 0xe0000000
+};
+unsigned int v2[] __attribute__ ((aligned(16))) =
+{
+  4, 0xb0000000, 5, 0xc0000000,
+  0xd0000000, 6, 7, 8
+};
+
+unsigned int max[] =
+{
+  0x80000000, 0xb0000000, 0xa0000000, 0xc0000000,
+  0xd0000000, 0xd0000000, 0xf0000000, 0xe0000000
+};
+
+unsigned int min[] =
+{
+  4, 1, 5, 2,
+  3, 6, 7, 8
+};
+
+unsigned int res[8] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 8; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 8; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1a.c
new file mode 100644
index 000000000..cd77175f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "pr42542-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1b.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1b.c
new file mode 100644
index 000000000..7651f07a6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-1b.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "pr42542-1.c"
+
+/* { dg-final { scan-assembler "pmaxud" } } */
+/* { dg-final { scan-assembler "pminud" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2.c
new file mode 100644
index 000000000..80ed9c35b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2.c
@@ -0,0 +1,78 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2 -ftree-vectorize" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+unsigned short v1[] __attribute__ ((aligned(16))) =
+{
+  0x8000, 0x9000, 1, 10, 0xa000, 0xb000, 2, 20,
+  3, 30, 0xd000, 0xe000, 0xf000, 0xe000, 25, 30
+};
+unsigned short v2[] __attribute__ ((aligned(16))) =
+{
+  4, 40, 0xb000, 0x8000, 5, 50, 0xc000, 0xf000,
+  0xd000, 0xa000, 6, 65, 7, 75, 0xe000, 0xc000
+};
+
+unsigned short max[] =
+{
+  0x8000, 0x9000, 0xb000, 0x8000, 0xa000, 0xb000, 0xc000, 0xf000,
+  0xd000, 0xa000, 0xd000, 0xe000, 0xf000, 0xe000, 0xe000, 0xc000
+};
+
+unsigned short min[] =
+{
+  4, 40, 1, 10, 5, 50, 2, 20,
+  3, 30, 6, 65, 7, 75, 25, 30
+};
+
+unsigned short res[16] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 16; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 16; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2a.c
new file mode 100644
index 000000000..bcefa9cfe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "pr42542-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2b.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2b.c
new file mode 100644
index 000000000..ddb539bf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-2b.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse4.1 -ftree-vectorize" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "pr42542-2.c"
+
+/* { dg-final { scan-assembler "pmaxuw" } } */
+/* { dg-final { scan-assembler "pminuw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-3.c
new file mode 100644
index 000000000..372f2c1e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-3.c
@@ -0,0 +1,86 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2 -ftree-vectorize" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+unsigned char v1[] __attribute__ ((aligned(16))) =
+{
+  0x80, 0xd0, 0x90, 0xa0, 1, 15, 10, 15,
+  0xa0, 0xc0, 0xb0, 0xf0, 2, 25, 20, 35,
+  3, 34, 30, 36, 0xd0, 0x80, 0xe0, 0xb0,
+  0xf0, 0xe0, 0xe0, 0x80, 25, 34, 30, 40
+};
+unsigned char v2[] __attribute__ ((aligned(16))) =
+{
+  4, 44, 40, 48, 0xb0, 0x80, 0x80, 0x90,
+  5, 55, 50, 51, 0xc0, 0xb0, 0xf0, 0xd0,
+  0xd0, 0x80, 0xa0, 0xf0, 6, 61, 65, 68,
+  7, 76, 75, 81, 0xe0, 0xf0, 0xc0, 0x90
+};
+
+unsigned char max[] =
+{
+  0x80, 0xd0, 0x90, 0xa0, 0xb0, 0x80, 0x80, 0x90,
+  0xa0, 0xc0, 0xb0, 0xf0, 0xc0, 0xb0, 0xf0, 0xd0,
+  0xd0, 0x80, 0xa0, 0xf0, 0xd0, 0x80, 0xe0, 0xb0,
+  0xf0, 0xe0, 0xe0, 0x80, 0xe0, 0xf0, 0xc0, 0x90
+};
+
+unsigned char min[] =
+{
+  4, 44, 40, 48, 1, 15, 10, 15,
+  5, 55, 50, 51, 2, 25, 20, 35,
+  3, 34, 30, 36, 6, 61, 65, 68,
+  7, 76, 75, 81, 25, 34, 30, 40
+};
+
+unsigned char res[32] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 32; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 32; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-3a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-3a.c
new file mode 100644
index 000000000..754e59e84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-3a.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse2 -ftree-vectorize" } */
+
+#include "pr42542-3.c"
+
+/* { dg-final { scan-assembler "pmaxub" } } */
+/* { dg-final { scan-assembler "pminub" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4.c
new file mode 100644
index 000000000..afb298989
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+
+#include "sse4_2-check.h"
+
+unsigned long long v1[] __attribute__ ((aligned(16))) =
+{
+  0x8000000000000000ULL, 2,
+  3, 0xd000000000000000ULL
+};
+unsigned long long v2[] __attribute__ ((aligned(16))) =
+{
+  4, 0xb000000000000000ULL,
+  0xf000000000000000ULL, 6
+};
+
+unsigned long long max[] =
+{
+  0x8000000000000000ULL, 0xb000000000000000ULL,
+  0xf000000000000000ULL, 0xd000000000000000ULL
+};
+
+unsigned long long min[] =
+{
+  4, 2,
+  3, 6
+};
+
+unsigned long long res[4] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+sse4_2_test (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 4; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 4; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4a.c
new file mode 100644
index 000000000..bea6c1f50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-4a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+
+#include "pr42542-4.c"
+
+/* { dg-final { scan-assembler "pcmpgtq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-5.c
new file mode 100644
index 000000000..7d77a18ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-5.c
@@ -0,0 +1,66 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+
+#include "sse4_2-check.h"
+
+long long v1[] __attribute__ ((aligned(16))) =
+{
+  -3, 2, 3, -4 
+};
+long long v2[] __attribute__ ((aligned(16))) =
+{
+  4, -10, -20, 6
+};
+
+long long max[] =
+{
+  4, 2, 3, 6
+};
+
+long long min[] =
+{
+  -3, -10, -20, -4
+};
+
+long long res[4] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+static void
+sse4_2_test (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 4; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 4; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-5a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-5a.c
new file mode 100644
index 000000000..bba0a118e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42542-5a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse4.2 -ftree-vectorize" } */
+
+#include "pr42542-5.c"
+
+/* { dg-final { scan-assembler "pcmpgtq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42549.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42549.c
new file mode 100644
index 000000000..733853cdc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42549.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-require-effective-target 3dnow } */
+/* { dg-options "-O2 -m3dnow" } */
+
+#include "mmx-3dnow-check.h"
+
+#include <mm3dnow.h>
+
+typedef union {
+  float f[2];
+  __m64 v;
+} vec_t;
+
+void __attribute__ ((noinline))
+Butterfly_3 (__m64 * D, __m64 SC)
+{
+  __m64 T, T1;
+
+  T = _m_pfmul (D[1], SC);
+  T1 = D[0];
+  D[0] = _m_pfadd (T1, T);
+  D[1] = _m_pfsub (T1, T);
+}
+
+static void
+mmx_3dnow_test (void)
+{
+  vec_t D[2] = { { .f = { 2.0f, 3.0f } },
+		 { .f = { 4.0f, 5.0f } } };
+
+  const vec_t SC = { .f = { 1.0f, 1.0f } };
+
+  Butterfly_3 (&D[0].v, SC.v);
+  _m_femms ();
+
+  if (D[1].f[0] != -2.0f || D[1].f[1] != -2.0f)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42589.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42589.c
new file mode 100644
index 000000000..863372b56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42589.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i486" } } */
+/* { dg-options "-O2 -march=i486" } */
+
+void
+foo (unsigned long long *p)
+{
+  unsigned long long tmp;
+  tmp = *p;
+  tmp = (tmp >> 32) | (tmp << 32);
+  tmp = (((tmp & 0xff00ff00ff00ff00ULL) >> 8)
+	 | ((tmp & 71777214294589695ULL) << 8));
+  *p = (((tmp & 0xffff0000ffff0000ULL) >> 16)
+	| ((tmp & 281470681808895ULL) << 16));
+}
+
+/* { dg-final { scan-assembler-times "bswap" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42881.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42881.c
new file mode 100644
index 000000000..c8ad09d20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42881.c
@@ -0,0 +1,15 @@
+/* PR target/42881 */
+/* { dg-do run } */
+/* { dg-options "-O0 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+static void
+sse2_test (void)
+{
+  double a[2];
+  __m128d x = _mm_set1_pd(3);
+  _mm_storeu_pd(a,x);
+  if (a[0] != 3.0 || a[1] != 3.0)
+    __builtin_abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42891.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42891.c
new file mode 100644
index 000000000..e3c7b9cf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr42891.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+union B { int i; float f; };
+
+extern void bar (void);
+
+void
+foo (union B x, union B y)
+{
+  if (!(y.f > x.i))
+    bar ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43067.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43067.c
new file mode 100644
index 000000000..7abb00279
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43067.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mxop -ftree-vectorize -fschedule-insns" } */
+
+union {
+  int i32[10240];
+  long long i64[10240];
+} a, b, c;
+
+void imul32_to_64 (void)
+{
+  int i;
+
+  for (i = 0; i < 10240; i++)
+    a.i64[i] = (long long) b.i32[i] * c.i32[i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43107.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43107.c
new file mode 100644
index 000000000..879652931
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43107.c
@@ -0,0 +1,20 @@
+/* PR target/43107 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx" } */
+
+extern void bar (float b[4][4]);
+
+void
+foo ()
+{
+  float a[4][4], b[4][4];
+  int i, j;
+  for (i = 0; i < 4; i++)
+    {
+      for (j = 0; j < 4; j++)
+	a[i][j] = 0;
+      for (j = 0; j < 4; j++)
+	b[i][j] = a[i][j];
+    }
+  bar (b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43508.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43508.c
new file mode 100644
index 000000000..c43982b3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43508.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-g -O -msse3" } */
+
+typedef float v4sf __attribute__ ((__vector_size__ (16)));
+typedef int v4si __attribute__ ((__vector_size__ (16)));
+
+v4sf bar(int);
+
+v4sf foo(v4si vi)
+{
+  int x = __builtin_ia32_vec_ext_v4si (vi, 0);
+  return bar(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43524.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43524.c
new file mode 100644
index 000000000..b2662702a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43524.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mstack-arg-probe" } */
+
+extern void bar (void);
+
+void foo (int i)
+{
+  bar ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43528.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43528.c
new file mode 100644
index 000000000..f33d96b19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43528.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mms-bitfields" } */
+
+struct S { int i[(1LL << 60) - 1]; };
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43546.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43546.c
new file mode 100644
index 000000000..53cb3a07f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43546.c
@@ -0,0 +1,12 @@
+/* PR target/43546 */
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+/* { dg-additional-options "-mpreferred-stack-boundary=2 -msseregparm -msse" { target ia32 } } */
+
+extern void bar (double);
+
+void
+foo (void)
+{
+  bar (1.0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43638.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43638.c
new file mode 100644
index 000000000..9af06aede
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43638.c
@@ -0,0 +1,9 @@
+/* PR target/43638 */
+/* { dg-do compile } */
+
+void
+foo (void)
+{
+  int x;
+  __asm __volatile ("mov $0,%e0" : "=r" (x));	/* { dg-error "invalid operand code" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43653.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43653.c
new file mode 100644
index 000000000..22928edac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43653.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -ftree-vectorize -msse" } */
+
+typedef struct {} S;
+
+void *foo()
+{
+  S a[64], *p[64];
+  int i;
+
+  for (i = 0; i < 64; i++)
+    p[i] = &a[i];
+  return p[0];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43662.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43662.c
new file mode 100644
index 000000000..2896a1a52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43662.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2" } */
+
+void __attribute__ ((ms_abi)) foo (void)
+{
+}
+
+typedef struct _IAVIStreamImpl
+{
+  int sInfo;
+  int has;
+} IAVIStreamImpl;
+
+extern int __attribute__ ((ms_abi)) aso (void *);
+extern int sre (void *);
+
+int AVIFILE_OpenCompressor (IAVIStreamImpl *This)
+{
+  if (This->has != 0)
+    aso (&This->has);
+  sre (&This->sInfo);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43668.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43668.c
new file mode 100644
index 000000000..b6c2114fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43668.c
@@ -0,0 +1,10 @@
+/* PR target/43668 */
+/* { dg-do run } */
+/* { dg-options "-fschedule-insns" } */
+
+int foo(int i, ...) {
+  return i;
+}
+int main() {
+  return foo(0, 0.0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43671.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43671.c
new file mode 100644
index 000000000..388cd65e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43671.c
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mtune=i686 -O1 -fpeel-loops -fschedule-insns2 -ftree-vectorize -fsched2-use-superblocks" } */
+
+extern void abort ();
+
+int main ()
+{
+  struct {
+    char ca[16];
+  } s;
+  int i;
+
+  for (i = 0; i < 16; i++)
+    {
+      s.ca[i] = 5;
+    }
+
+
+  for (i = 0; i < 16; i++)
+    {
+      if (s.ca[i] != 5)
+        abort ();
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43766.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43766.c
new file mode 100644
index 000000000..8ac16137f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43766.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-options "-O2 -msse -mregparm=3" { target ia32 } } */
+
+void p (int *a, int i)
+{
+  __builtin_prefetch (&a[i]);
+}
+
+/* { dg-final { scan-assembler-not "lea\[lq\]?\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43799.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43799.c
new file mode 100644
index 000000000..de9022d0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43799.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-options "-O -fschedule-insns" } */
+
+int f4 (int i, ...)
+{
+  int y = 0;
+   __builtin_va_list ap;
+   __builtin_va_start(ap, i);
+   if (i == 5) y = __builtin_va_arg(ap, double);
+   __builtin_va_end(ap);
+   return y;
+}
+
+int main (void)
+{
+  if (f4 (5, 7.0) != 7)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43869.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43869.c
new file mode 100644
index 000000000..4157db1d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr43869.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+
+int __attribute__((__noinline__))
+bugged(float f1, float f2, float f3, float f4,
+       float f5, float f6, float f7, float f8)
+{
+    return f1 || f2 || f3 || f4 || f5 != 1. || f6 != 1. || f7 != 1. || f8 != 1.;
+}
+
+int __attribute__((__noinline__, __ms_abi__)) isbugged(void)
+{
+    return bugged(0, 0, 0, 0, 1., 1., 1., 1.);
+}
+
+int main()
+{
+    return isbugged();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44071.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44071.c
new file mode 100644
index 000000000..514c5e2fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44071.c
@@ -0,0 +1,103 @@
+/* PR middle-end/44071 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+static inline int
+f1 (void)
+{
+  asm goto ("jmp %l[l1]" : : : : l1, l2);
+  __builtin_unreachable ();
+ l1:
+  return 1;
+ l2:
+  return 0;
+}
+
+__attribute__((noinline)) int
+b1 (int x)
+{
+  if (f1 () || x == 6)
+    x = 1;
+  else
+    x = 2;
+  return x;
+}
+
+static inline int
+f2 (void)
+{
+  asm goto ("jmp %l[l2]" : : : : l1, l2);
+  __builtin_unreachable ();
+ l1:
+  return 1;
+ l2:
+  return 0;
+}
+
+__attribute__((noinline)) int
+b2 (int x)
+{
+  if (f2 () || x == 6)
+    x = 1;
+  else
+    x = 2;
+  return x;
+}
+
+static inline int
+f3 (void)
+{
+  asm goto ("jmp %l[l1]" : : : : l1, l2);
+ l1:
+  return 1;
+ l2:
+  return 0;
+}
+
+__attribute__((noinline)) int
+b3 (int x)
+{
+  if (f3 () || x == 6)
+    x = 1;
+  else
+    x = 2;
+  return x;
+}
+
+static inline int
+f4 (void)
+{
+  asm goto ("jmp %l[l2]" : : : : l1, l2);
+ l1:
+  return 1;
+ l2:
+  return 0;
+}
+
+__attribute__((noinline)) int
+b4 (int x)
+{
+  if (f4 () || x == 6)
+    x = 1;
+  else
+    x = 2;
+  return x;
+}
+
+extern void abort (void);
+
+int
+main (void)
+{
+  int x;
+  asm ("" : "=r" (x) : "0" (0));
+  if (b1 (x) != 1 || b1 (x + 6) != 1)
+    abort ();
+  if (b2 (x) != 2 || b2 (x + 6) != 1)
+    abort ();
+  if (b3 (x) != 1 || b3 (x + 6) != 1)
+    abort ();
+  if (b4 (x) != 2 || b4 (x + 6) != 1)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44130.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44130.c
new file mode 100644
index 000000000..3e50c7b15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44130.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */
+/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */
+/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-32,\[\\t \]*%\[re\]?sp" } } */
+/* { dg-final { scan-assembler "vmovaps\[\\t \]*%ymm" } } */
+
+extern void abort (void);
+
+static float Yf[] = { 2.0, -2.0, -2.0, -2.0, -2.0, 2.0, -0.0, __builtin_inff () };
+static const float Zf[] = { 1.0, -1.0, -1.0, -0.0, -0.0, 0.0, -__builtin_inff (), __builtin_nanf ("") };
+
+void testf (void)
+{
+  float xxxxx[8];
+  int i;
+  xxxxx[0] = __builtin_copysignf (1.0, Yf[0]);
+  xxxxx[1] = __builtin_copysignf (1.0, Yf[1]);
+  xxxxx[2] = __builtin_copysignf (-1.0, Yf[2]);
+  xxxxx[3] = __builtin_copysignf (0.0, Yf[3]);
+  xxxxx[4] = __builtin_copysignf (-0.0, Yf[4]);
+  xxxxx[5] = __builtin_copysignf (-0.0, Yf[5]);
+  xxxxx[6] = __builtin_copysignf (__builtin_inff (), Yf[6]);
+  xxxxx[7] = __builtin_copysignf (-__builtin_nanf (""), Yf[7]);
+  for (i = 0; i < 8; ++i)
+    if (__builtin_memcmp (xxxxx+i, Zf+i, sizeof(float)) != 0)
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44144.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44144.c
new file mode 100644
index 000000000..8db0f4f3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44144.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */
+
+void
+foo (char * dest, int xcount, int ycount)
+{
+  int x, y;
+  for (y = 0; y < ycount; y++)
+    for (x = 0; x < xcount; x++)
+      dest[x + y*2] = 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44180.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44180.c
new file mode 100644
index 000000000..c327e94bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44180.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */
+
+#include "avx-check.h"
+
+#define N 16
+
+float b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+float c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+float d[N] = {0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30};
+
+static void
+__attribute__ ((noinline))
+avx_test ()
+{
+  int i;
+  float a[N];
+
+  /* Strided access. Vectorizable on platforms that support load of strided 
+     accesses (extract of even/odd vector elements).  */
+  for (i = 0; i < N/2; i++)
+    {
+      a[i] = b[2*i+1] * c[2*i+1] - b[2*i] * c[2*i];
+      d[i] = b[2*i] * c[2*i+1] + b[2*i+1] * c[2*i];
+    }
+
+  /* Check results.  */
+  for (i = 0; i < N/2; i++)
+    {
+      if (a[i] != b[2*i+1] * c[2*i+1] - b[2*i] * c[2*i]
+	  || d[i] != b[2*i] * c[2*i+1] + b[2*i+1] * c[2*i])
+	abort();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44223.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44223.c
new file mode 100644
index 000000000..3b8030c1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44223.c
@@ -0,0 +1,36 @@
+/* PR debug/44223 */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fsched-pressure -fschedule-insns -fpic -march=core2 -g" { target fpic } } */
+
+struct S { unsigned int s1; int s2; };
+struct T { int t; };
+
+extern void extfn (struct S *);
+
+static inline void
+foo (struct S *s, unsigned char *x, int y)
+{
+  s->s2 = 32;
+}
+
+static inline void
+bar (struct S *s, int n, unsigned int x)
+{
+  unsigned int s1;
+  int s2;
+  s1 = s->s1;
+  s2 = s->s2;
+  if (n < s2)
+    s1 = (s1 << n) | x;
+  s->s1 = s1;
+}
+
+int
+baz (struct T *u, unsigned char *v, int w)
+{
+  struct S y;
+  foo (&y, v, 7);
+  bar (&y, 12, 0xfff);
+  bar (&y, 2, u->t);
+  extfn (&y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44481.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44481.c
new file mode 100644
index 000000000..701268b56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44481.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+static inline unsigned
+parity (unsigned x)
+{
+  return (unsigned) __builtin_parity (x);
+}
+
+unsigned
+f (unsigned rpoly)
+{
+  return parity (rpoly & 1) ^ parity (rpoly & 6);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44546.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44546.c
new file mode 100644
index 000000000..517446fdc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44546.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -ffast-math -mfpmath=387" } */
+
+typedef __SIZE_TYPE__ size_t;
+typedef struct
+{
+  float *ewgts;
+} vtx_data;
+
+extern void *zmalloc (size_t);
+extern int whatever (vtx_data *);
+
+float *
+compute_apsp_artifical_weights_packed (vtx_data * graph, int n)
+{
+  float *weights;
+
+  weights = (float *) zmalloc (n * sizeof (float));
+  weights[n] =
+    whatever (graph) > graph[n].ewgts[n] ?
+    whatever (graph) : graph[n].ewgts[n];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44578.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44578.c
new file mode 100644
index 000000000..20f76c31c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44578.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mtune=athlon64" } */
+
+extern void abort (void);
+
+long double
+__attribute__((noinline, noclone))
+test (float num)
+{
+  unsigned int i;
+
+  if (num < 0.0)
+    num = 0.0;
+
+  __builtin_memcpy (&i, &num, sizeof(unsigned int));
+
+  return (long double)(unsigned long long) i;
+}
+
+int
+main ()
+{
+  long double x;
+
+  x = test (0.0);
+
+  if (x != 0.0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44942.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44942.c
new file mode 100644
index 000000000..d8164845c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44942.c
@@ -0,0 +1,44 @@
+/* PR target/44942 */
+/* { dg-do run { target { ! { ia32 } } } } */
+
+#include <stdarg.h>
+#include <emmintrin.h>
+
+void
+test1 (double a, double b, double c, double d, double e, double f,
+       double g, __m128d h, ...)
+{
+  double i;
+  va_list ap;
+
+  va_start (ap, h);
+  i = va_arg (ap, double);
+  if (i != 1234.0)
+    __builtin_abort ();
+  va_end (ap);
+}
+
+void
+test2 (double a, double b, double c, double d, double e, double f, double g,
+       __m128d h, double i, __m128d j, double k, __m128d l,
+       double m, __m128d n, ...)
+{
+  double o;
+  va_list ap;
+
+  va_start (ap, n);
+  o = va_arg (ap, double);
+  if (o != 1234.0)
+    __builtin_abort ();
+  va_end (ap);
+}
+
+int
+main ()
+{
+  __m128d m = _mm_set1_pd (7.0);
+  test1 (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, m, 1234.0);
+  test2 (0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, m, 0.0, m,
+	 0.0, m, 0.0, m, 1234.0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-1a.c
new file mode 100644
index 000000000..db58c04c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-1a.c
@@ -0,0 +1,18 @@
+/* PR target/44948 */
+/* { dg-do run } */
+/* { dg-options "-O -Wno-psabi -mtune=generic" } */
+/* { dg-require-effective-target avx_runtime } */
+/* { dg-additional-sources pr44948-1b.c } */
+
+#pragma GCC target ("avx")
+
+struct A { long b[8] __attribute__((aligned (32))); };
+void foo (long double, struct A);
+
+int
+main (void)
+{
+  struct A a = { { 0, 1, 2, 3, 4, 5, 6, 7 } };
+  foo (8.0L, a);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-1b.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-1b.c
new file mode 100644
index 000000000..1e2d4d3c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-1b.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mno-avx -Wno-psabi -mtune=generic" } */
+
+struct A { long b[8] __attribute__((aligned (32))); };
+
+void
+foo (long double x, struct A y)
+{
+  int i;
+  if (x != 8.0L)
+    __builtin_abort ();
+  for (i = 0; i < 8; i++)
+    if (y.b[i] != i)
+      __builtin_abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-2a.c
new file mode 100644
index 000000000..d84d1a6b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-2a.c
@@ -0,0 +1,21 @@
+/* PR target/44948 */
+/* { dg-do run } */
+/* { dg-options "-O -Wno-psabi -mno-sse -mtune=generic" } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target sse2_runtime } */
+/* { dg-additional-sources pr44948-2b.c } */
+
+#pragma GCC target ("sse2")
+
+struct A
+{ 
+  float V4SF __attribute__ ((vector_size (16)));
+};
+
+int
+main (void)
+{
+  struct A a = { { 0, 1, 2, 3 } };
+  foo (8.0L, a, 8.0L);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-2b.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-2b.c
new file mode 100644
index 000000000..fa1769b62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr44948-2b.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mno-sse -Wno-psabi -mtune=generic" } */
+
+struct A
+{ 
+  float V4SF __attribute__ ((vector_size (16)));
+};
+
+void
+foo (long double x, struct A y, long double z)
+{
+  int i;
+  struct A a = { { 0, 1, 2, 3 } };
+
+  if (x != 8.0L || z != 8.0L)
+    __builtin_abort ();
+  if (__builtin_memcmp (&a, &y, sizeof (a)))
+    __builtin_abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45206.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45206.c
new file mode 100644
index 000000000..7dd4bd263
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45206.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fno-omit-frame-pointer" } */
+
+struct _Unwind_Context { void *ra; };
+
+long uw_install_context_1 (struct _Unwind_Context *, struct _Unwind_Context *);
+
+void _Unwind_RaiseException(void)
+{
+  struct _Unwind_Context this_context, cur_context;
+  long offset = uw_install_context_1 (&this_context, &cur_context);
+  void *handler = __builtin_frob_return_addr ((&cur_context)->ra);
+
+  __builtin_eh_return (offset, handler);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45213.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45213.c
new file mode 100644
index 000000000..c575fb550
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45213.c
@@ -0,0 +1,9 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os -fno-omit-frame-pointer" } */
+
+void f (float, float, float, float, float, float, float, float, float, float);
+
+void g (void)
+{
+  f (0, 0, 0, 0, 0, 0, 0, 0, -1, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45234.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45234.c
new file mode 100644
index 000000000..3996fa27f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45234.c
@@ -0,0 +1,18 @@
+/* PR middle-end/45234 */
+/* { dg-do compile } */
+/* { dg-options "-march=i586" { target ia32 } } */
+
+struct S { union { double b[4]; } a[18]; } s, a[5];
+void foo (struct S);
+struct S bar (struct S, struct S *, struct S);
+
+void
+foo (struct S arg)
+{
+}
+
+void
+baz (void)
+{
+ foo (bar (s, &a[1], a[2]));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45296.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45296.c
new file mode 100644
index 000000000..307ee012a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45296.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+register long double F80 asm("st"); /* { dg-error "stack register" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-1.c
new file mode 100644
index 000000000..db6c9400d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-1.c
@@ -0,0 +1,16 @@
+/* PR target/45336 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movsbl" } } */
+/* { dg-final { scan-assembler-not "movswl" } } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+/* { dg-final { scan-assembler-not "movzwl" } } */
+/* { dg-final { scan-assembler-not "cwtl" } } */
+/* { dg-final { scan-assembler "pextrb" } } */
+/* { dg-final { scan-assembler "pextrw" } } */
+/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */
+
+#include <smmintrin.h>
+unsigned int foo8(__m128i x) { return _mm_extract_epi8(x, 4); }
+unsigned int foo16(__m128i x) { return _mm_extract_epi16(x, 3); }
+unsigned int foo32(__m128i x) { return _mm_extract_epi32(x, 2); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-2.c
new file mode 100644
index 000000000..3e51591fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-2.c
@@ -0,0 +1,20 @@
+/* PR target/45336 */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -msse4 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movsbl" } } */
+/* { dg-final { scan-assembler-not "movswl" } } */
+/* { dg-final { scan-assembler-not "movzbl" } } */
+/* { dg-final { scan-assembler-not "movzwl" } } */
+/* { dg-final { scan-assembler-not "cwtl" } } */
+/* { dg-final { scan-assembler-not "cltq" } } */
+/* { dg-final { scan-assembler "pextrb" } } */
+/* { dg-final { scan-assembler "pextrw" } } */
+/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */
+
+#include <smmintrin.h>
+unsigned long long int foo8(__m128i x) { return _mm_extract_epi8(x, 4); }
+unsigned long long int foo16(__m128i x) { return _mm_extract_epi16(x, 3); }
+unsigned long long int foo32(__m128i x)
+{ 
+  return (unsigned int) _mm_extract_epi32(x, 2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-3.c
new file mode 100644
index 000000000..b2168c006
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-3.c
@@ -0,0 +1,13 @@
+/* PR target/45336 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4 -mtune=generic" } */
+/* { dg-final { scan-assembler "movsbl" } } */
+/* { dg-final { scan-assembler "(movswl|cwtl)" } } */
+/* { dg-final { scan-assembler "pextrb" } } */
+/* { dg-final { scan-assembler "pextrw" } } */
+/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */
+
+#include <smmintrin.h>
+int foo8(__m128i x) { return (char) _mm_extract_epi8(x, 4); }
+int foo16(__m128i x) { return (short) _mm_extract_epi16(x, 3); }
+int foo32(__m128i x) { return _mm_extract_epi32(x, 2); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-4.c
new file mode 100644
index 000000000..8b66a6a1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45336-4.c
@@ -0,0 +1,14 @@
+/* PR target/45336 */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -msse4 -mtune=generic" } */
+/* { dg-final { scan-assembler "movsbq" } } */
+/* { dg-final { scan-assembler "movswq" } } */
+/* { dg-final { scan-assembler "(cltq|movslq)" } } */
+/* { dg-final { scan-assembler "pextrb" } } */
+/* { dg-final { scan-assembler "pextrw" } } */
+/* { dg-final { scan-assembler "pextrd" { target { ! x86_64-*-mingw* } } } } */
+
+#include <smmintrin.h>
+long long int foo8(__m128i x) { return (char) _mm_extract_epi8(x, 4); }
+long long int foo16(__m128i x) { return (short) _mm_extract_epi16(x, 3); }
+long long int foo32(__m128i x) { return (int) _mm_extract_epi32(x, 2); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352-1.c
new file mode 100644
index 000000000..5cd1bd842
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mtune=amdfam10 -O3 -fpeel-loops -fselective-scheduling2 -fsel-sched-pipelining -fPIC" } */
+
+static int FIR_Tab_16[16][16];
+
+void
+V_Pass_Avrg_16_C_ref (int *Dst, int *Src, int W, int BpS, int Rnd)
+{
+  while (W-- > 0)
+    {
+      int i, k;
+      int Sums[16] = { };
+      for (i = 0; i < 16; ++i)
+	for (k = 0; k < 16; ++k)
+	  Sums[k] += FIR_Tab_16[i][k] * Src[i];
+      for (i = 0; i < 16; ++i)
+	Dst[i] = Sums[i] + Src[i];
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352-2.c
new file mode 100644
index 000000000..52e5522a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352-2.c
@@ -0,0 +1,111 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mtune=amdfam10 -fexpensive-optimizations -fgcse -foptimize-register-move -freorder-blocks -fschedule-insns2 -funswitch-loops -fgcse-las -fselective-scheduling2 -fsel-sched-pipelining -funroll-all-loops" } */
+
+typedef char uint8_t;
+typedef uint32_t;
+typedef vo_frame_t;
+__extension__ typedef __SIZE_TYPE__ size_t;
+
+struct vo_frame_s
+{
+    uint8_t base[3];
+  int pitches[3];};
+typedef struct
+{
+void
+    (*proc_macro_block)
+    (void);
+}
+xine_xvmc_t;
+typedef struct
+{
+  uint8_t ref[2][3];
+int pmv;
+}
+motion_t;
+typedef struct
+{
+  uint32_t bitstream_buf;
+  int bitstream_bits;
+    uint8_t * bitstream_ptr;
+    uint8_t dest[3];
+  int pitches[3];
+  int offset;
+    motion_t b_motion;
+    motion_t f_motion;
+  int v_offset;
+  int coded_picture_width;
+  int picture_structure;
+struct vo_frame_s *current_frame;}
+picture_t;
+typedef struct
+{
+int xvmc_last_slice_code;}
+mpeg2dec_accel_t;
+static int bitstream_init (picture_t * picture, void *start)
+{
+  picture->bitstream_ptr = start;
+  return (int) (size_t) start;
+}
+static slice_xvmc_init (picture_t * picture, int code)
+{
+  int offset;
+  struct vo_frame_s *forward_reference_frame;
+  offset = picture->picture_structure == 2;
+  picture->pitches[0] = picture->current_frame->pitches[0];
+  picture->pitches[1] = picture->current_frame->pitches[1];
+  if (picture)
+    picture->f_motion.ref
+      [0]
+      [0]
+      = (char) (size_t) (forward_reference_frame->base + (offset ? picture->pitches[0] : 0));
+  picture->f_motion.ref[0][1] = (offset);
+  if (picture->picture_structure)
+      picture->pitches[0] <<= picture->pitches[1] <<= 1;
+  offset = 0;
+  while (1)
+    {
+      if (picture->bitstream_buf >= 0x08000000)
+	  break;
+      switch (picture->bitstream_buf >> 12)
+	{
+	case 8:
+	  offset += 33;
+		picture->bitstream_buf
+		  |=
+		  picture->bitstream_ptr[1] << picture->bitstream_bits;
+	}
+    }
+  picture->offset = (offset);
+  while (picture->offset - picture->coded_picture_width >= 0)
+    {
+      picture->offset -= picture->coded_picture_width;
+      if (picture->current_frame)
+	{
+	  picture->dest[0] += picture->pitches[0];
+	  picture->dest[1] += picture->pitches[1];
+	}
+      picture->v_offset += 16;
+    }
+}
+
+void
+mpeg2_xvmc_slice
+  (mpeg2dec_accel_t * accel, picture_t * picture, int code, uint8_t buffer,int mba_inc)
+{
+  xine_xvmc_t * xvmc = (xine_xvmc_t *) (size_t) bitstream_init (picture, (void *) (size_t) buffer);
+  slice_xvmc_init (picture, code);
+    while (1)
+      {
+	if (picture)
+	    break;
+	switch (picture->bitstream_buf)
+	  {
+	  case 8:
+	    mba_inc += accel->xvmc_last_slice_code = code;
+		  xvmc->proc_macro_block   ();
+	    while (mba_inc)
+	      ;
+	  }
+      }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352.c
new file mode 100644
index 000000000..ef710ce6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45352.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=amdfam10 -fselective-scheduling2 -fsel-sched-pipelining -funroll-all-loops" } */
+
+struct S
+{
+  struct
+  {
+    int i;
+  } **p;
+  int x;
+  int y;
+};
+
+extern int baz (void);
+extern int bar (void *, int, int);
+
+void
+foo (struct S *s)
+{
+  int i;
+  for (i = 0; i < s->x; i++)
+    bar (s->p[i], baz (), s->y);
+  for (i = 0; i < s->x; i++)
+    s->p[i]->i++;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45500.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45500.c
new file mode 100644
index 000000000..46e5100ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45500.c
@@ -0,0 +1,6 @@
+/* PR debug/45500 */
+/* { dg-do compile } */
+/* { dg-options "-g -msse" } */
+
+typedef char V __attribute__ ((__vector_size__ (16)));
+static const V s = { '\n', '\r', '?', '\\' };
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45617.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45617.c
new file mode 100644
index 000000000..58f977289
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45617.c
@@ -0,0 +1,22 @@
+/* PR rtl-optimization/45617 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int f1 (int x)
+{
+  return (x >> 23) > 12;
+}
+int f2 (int x)
+{
+  return x > ((13 << 23) - 1);
+}
+int f3 (int x)
+{
+  return (x >> 23) >= 12;
+}
+int f4 (int x)
+{
+  return x >= (12 << 23);
+}
+
+/* { dg-final { scan-assembler-not "sarl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45670.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45670.c
new file mode 100644
index 000000000..c50c4ba14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45670.c
@@ -0,0 +1,23 @@
+/* PR target/45670 */
+/* { dg-do compile } */
+/* { dg-options "-Os -mtune=generic" } */
+
+struct S
+{
+  float *buf;
+  int size;
+};
+
+void
+foo (struct S *s)
+{
+  int i;
+  for (i = 0; i < s->size; ++i)
+    s->buf[i] = 0;
+}
+
+/* Ensure we don't generate
+   lea (reg1,4),reg2; add (reg3),reg2; movl $0, (reg2)
+   instead of smaller
+   mov (reg3),reg2; movl $0, (reg2,reg1,4)  */
+/* { dg-final { scan-assembler-not "lea\[lq\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45739.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45739.c
new file mode 100644
index 000000000..bb36318a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45739.c
@@ -0,0 +1,24 @@
+/* PR rtl-optimization/45739 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i var;
+
+void
+foo (void)
+{
+  __m128i zero = _mm_setzero_si128 ();
+  var = _mm_xor_si128 (zero, var);
+}
+
+void
+bar (void)
+{
+  __m128i zero = _mm_setzero_si128 ();
+  var = _mm_or_si128 (var, zero);
+}
+
+/* { dg-final { scan-assembler-not "pxor\[^\n\]*xmm" } } */
+/* { dg-final { scan-assembler-not "por\[^\n\]*xmm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45830.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45830.c
new file mode 100644
index 000000000..85d5a3c5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45830.c
@@ -0,0 +1,31 @@
+/* PR target/45830 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-switchconv-all -mtune=generic" } */
+
+int
+foo (int *a)
+{
+  switch (*a)
+    {
+    case 0:
+    case 3:
+    case 1:
+    case 2:
+    case 4:
+    case 23:
+    case 26:
+    case 19:
+    case 5:
+    case 21:
+    case 20:
+    case 22:
+    case 27:
+      return 1;
+    default:
+      return 0;
+    }
+}
+
+/* { dg-final { scan-tree-dump "expanding as bit test is preferable" "switchconv" } } */
+/* { dg-final { scan-assembler-not "CSWTCH" } } */
+/* { dg-final { cleanup-tree-dump "switchconv" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45852.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45852.c
new file mode 100644
index 000000000..8b7bbfbe7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45852.c
@@ -0,0 +1,16 @@
+/* PR middle-end/45852 */
+/* { dg-options "-O2 -mcmodel=small" } */
+/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && { ! { ia32 } } } } } */
+/* { dg-require-visibility "" } */
+
+struct S { int s; };
+
+volatile struct S globvar __attribute__((visibility ("hidden"))) = { -6 };
+
+void
+foo (void)
+{
+  globvar = globvar;
+}
+
+/* { dg-final { scan-assembler-times "globvar.%?rip" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45903.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45903.c
new file mode 100644
index 000000000..5cb642a4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45903.c
@@ -0,0 +1,44 @@
+/* PR tree-optimization/45903 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned long long a, b;
+unsigned char c;
+
+void
+f1 (void)
+{
+  c = (a >> 8) + (b >> 8);
+}
+
+void
+f2 (void)
+{
+  c = (a >> 8) | (b >> 8);
+}
+
+void
+f3 (void)
+{
+  c = (a >> 16) ^ (b >> 56);
+}
+
+unsigned char
+f4 (void)
+{
+  return (a >> 48) + (b >> 40);
+}
+
+unsigned char
+f5 (void)
+{
+  return (a >> 32) | (b >> 16);
+}
+
+unsigned char
+f6 (void)
+{
+  return (a >> 24) ^ (b >> 32);
+}
+
+/* { dg-final { scan-assembler-not "shr\[qdl\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45913.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45913.c
new file mode 100644
index 000000000..46b9c66f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45913.c
@@ -0,0 +1,23 @@
+/* PR target/45913 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fselective-scheduling2 -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops" } */
+
+extern void bar (int, int);
+
+int ss[128];
+
+void
+foo (int i, int j, int k, int *p1, int *p2)
+{
+  int s[128];
+  __builtin_memcpy (s, ss, sizeof s);
+
+  while (i--)
+    {
+      int a = s[i];
+      while (j--)
+	bar (k, p2[a]);
+      j = s[i] & 0xFF;
+      bar (p1[a], k);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45946.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45946.c
new file mode 100644
index 000000000..81cd36026
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr45946.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-std=gnu99 -Os -fno-omit-frame-pointer" } */
+
+void
+__attribute__((noinline))
+bar (_Decimal128, _Decimal128, _Decimal128, _Decimal128, _Decimal128,
+     _Decimal128, _Decimal128, _Decimal128, _Decimal128);
+
+void
+foo (void)
+{
+  bar (0, 0, 0, 0, 0, 0, 0, 0, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46051.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46051.c
new file mode 100644
index 000000000..2da432faa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46051.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic" } */
+
+double val1[4][2], val2[4][2], chk[4][2];
+
+void
+foo (void)
+{
+  int i, j;
+  for (i = 0; i < 4; i++)
+    {
+      double tmp = 0;
+      for (j = 0; j < 2; j++)
+       tmp += val1[i][j] * val2[i][j];
+      for (j = 0; j < 2; j++)
+       chk[i][j] = tmp;
+    }
+}
+
+float val1f[8][2], val2f[8][2], chkf[8][2];
+
+void
+foof (void)
+{
+  int i, j;
+  for (i = 0; i < 8; i++)
+    {
+      float tmp = 0;
+      for (j = 0; j < 2; j++)
+       tmp += val1f[i][j] * val2f[i][j];
+      for (j = 0; j < 2; j++)
+       chkf[i][j] = tmp;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46084.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46084.c
new file mode 100644
index 000000000..30bac08cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46084.c
@@ -0,0 +1,69 @@
+/* This test needs to use setrlimit to set the stack size, so it can
+   only run on Unix.  */
+/* { dg-do run { target *-*-linux* *-*-gnu* *-*-solaris* *-*-darwin* } } */
+/* { dg-require-effective-target avx_runtime } */
+/* { dg-require-effective-target split_stack } */
+/* { dg-options "-fsplit-stack -O2 -mavx" } */
+
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/resource.h>
+
+/* Use a noinline function to ensure that the buffer is not removed
+   from the stack.  */
+static void use_buffer (char *buf, size_t) __attribute__ ((noinline));
+static void
+use_buffer (char *buf, size_t c)
+{
+  size_t i;
+
+  for (i = 0; i < c; ++i)
+    buf[i] = (char) i;
+}
+
+/* Each recursive call uses 10 * i bytes.  We call it 1000 times,
+   using a total of 5,000,000 bytes.  If -fsplit-stack is not working,
+   that will overflow our stack limit.  */
+
+static void
+down1 (int i)
+{
+  char buf[10 * i];
+
+  if (i > 0)
+    {
+      use_buffer (buf, 10 * i);
+      down1 (i - 1);
+    }
+}
+
+/* Same thing, using alloca.  */
+
+static void
+down2 (int i)
+{
+  char *buf = alloca (10 * i);
+
+  if (i > 0)
+    {
+      use_buffer (buf, 10 * i);
+      down2 (i - 1);
+    }
+}
+
+int
+main (void)
+{
+  struct rlimit r;
+
+  /* We set a stack limit because we are usually invoked via make, and
+     make sets the stack limit to be as large as possible.  */
+  r.rlim_cur = 8192 * 1024;
+  r.rlim_max = 8192 * 1024;
+  if (setrlimit (RLIMIT_STACK, &r) != 0)
+    abort ();
+  down1 (1000);
+  down2 (1000);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46085-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46085-1.c
new file mode 100644
index 000000000..0251556c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46085-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic -ffast-math" } */
+
+#include "avx-check.h"
+
+#define N 16
+#define DIFF 242
+
+float b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+float c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+
+void
+main1 (float x, float max_result)
+{
+  int i;
+  float diff = 2;
+  float max = x;
+  float min = 10;
+
+  for (i = 0; i < N; i++) {
+    diff += (b[i] - c[i]);
+  }
+
+  for (i = 0; i < N; i++) {
+    max = max < c[i] ? c[i] : max;
+  }
+
+  for (i = 0; i < N; i++) {
+    min = min > c[i] ? c[i] : min;
+  }
+
+  /* check results:  */
+  if (diff != DIFF)
+    abort ();
+  if (max != max_result)
+    abort ();
+  if (min != 0)
+    abort ();
+}
+
+static void
+avx_test (void)
+{ 
+  main1 (100, 100);
+  main1 (0, 15);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46085-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46085-2.c
new file mode 100644
index 000000000..568cdd96f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46085-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O2 -ftree-vectorize -mavx -mtune=generic -ffast-math" } */
+
+#include "avx-check.h"
+
+#define N 16
+#define DIFF 242
+
+double b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+double c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+
+void
+main1 (double x, double max_result)
+{
+  int i;
+  double diff = 2;
+  double max = x;
+  double min = 10;
+
+  for (i = 0; i < N; i++) {
+    diff += (b[i] - c[i]);
+  }
+
+  for (i = 0; i < N; i++) {
+    max = max < c[i] ? c[i] : max;
+  }
+
+  for (i = 0; i < N; i++) {
+    min = min > c[i] ? c[i] : min;
+  }
+
+  /* check results:  */
+  if (diff != DIFF)
+    abort ();
+  if (max != max_result)
+    abort ();
+  if (min != 0)
+    abort ();
+}
+
+static void
+avx_test (void)
+{ 
+  main1 (100, 100);
+  main1 (0, 15);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46095.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46095.c
new file mode 100644
index 000000000..ab9501e78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46095.c
@@ -0,0 +1,12 @@
+/* PR debug/46095 */
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O -fschedule-insns2 -fno-omit-frame-pointer -fstack-protector" } */
+
+extern void bar (char *);
+
+void
+foo (void)
+{
+  char c[0x80000000UL];
+  bar (c);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46098.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46098.c
new file mode 100644
index 000000000..4cc07c255
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46098.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -ffloat-store" } */
+
+typedef double v2df __attribute__((vector_size (16)));
+
+v2df foo (double *d)
+{
+  return __builtin_ia32_loadupd (d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46153.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46153.c
new file mode 100644
index 000000000..c6e0f52e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46153.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-msse -ffloat-store" } */
+
+typedef float v4sf __attribute__ ((__vector_size__ (16)));
+
+v4sf foo (v4sf a)
+{
+  return __builtin_ia32_movlhps (a, a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46178.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46178.c
new file mode 100644
index 000000000..661e3fd9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46178.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -m8bit-idiv -fira-algorithm=priority" } */
+/* This is the same as divmod-5.c, just with different options which
+   trigger an ICE.  We don't look at the output.  */
+
+extern void foo (int, int, int, int, int, int);
+
+void
+bar (int x, int y)
+{
+  foo (0, 0, 0, 0, x / y, x % y);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46226.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46226.c
new file mode 100644
index 000000000..168d80e2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46226.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-Os -fomit-frame-pointer -mno-accumulate-outgoing-args -fno-asynchronous-unwind-tables" } */
+/* { dg-options "-Os -fomit-frame-pointer -fno-asynchronous-unwind-tables" { target *-*-mingw* *-*-cygwin* } } */
+
+extern void abort(void);
+
+static void *p[2];
+
+void __attribute__((noinline))
+g(int x, ...)
+{
+  asm volatile ("" : : "g"(x));
+}
+
+void __attribute__((noinline))
+f(int x)
+{
+  p[0] = __builtin_return_address (0);
+  if (x == 0)
+    g(0);
+  g(1, 2, 3, 4, 5, 6, 7);
+
+  asm goto ("jmp %l0" : : : : label);
+  abort ();
+
+ label:
+  p[1] = __builtin_return_address (0);
+}
+
+int main()
+{
+  f(1);
+  if (p[0] != p[1])
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46253.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46253.c
new file mode 100644
index 000000000..406790aba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46253.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O -g -mf16c -mtune=generic -dp" } */
+
+typedef __m256i __attribute__ ((__vector_size__ (32)));
+
+__m256i bar (void);
+void foo (void)
+{
+  int i = 0;
+  bar ();
+  __builtin_ia32_vzeroupper ();
+  while (++i);
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46254.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46254.c
new file mode 100644
index 000000000..512287a5b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46254.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -mcx16 -fpic -mcmodel=large" } */
+
+__int128 i;
+
+void test ()
+{
+  __sync_val_compare_and_swap (&i, i, i);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46285.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46285.c
new file mode 100644
index 000000000..de705b08a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46285.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx -fsplit-stack -mtune=generic" } */
+/* { dg-require-effective-target split_stack } */
+
+typedef char __m256 __attribute__ ((__vector_size__ (32)));
+void foo (__m256 x) {}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46295.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46295.c
new file mode 100644
index 000000000..4ac7c101a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46295.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx -mtune=generic -dp" } */
+/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
+
+typedef double EXPRESS[5];
+void Parse_Rel_Factor (EXPRESS Express,int *Terms);
+void Parse_Vector ()
+{
+   EXPRESS Express;
+   int Terms;
+   for (Terms = 0; Terms < 5; Terms++)
+     Express[Terms] = 1.0;
+   Parse_Rel_Factor(Express,&Terms);
+}
+
+/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46419.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46419.c
new file mode 100644
index 000000000..3b722283e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46419.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+
+void __attribute__((noinline))
+sse_test (void)
+{
+  char image[4];
+  __m128 image4;
+  float out[4] __attribute__ ((aligned (16)));
+  int i;
+
+  for (i = 0; i < 4; i++)
+    image[i] = i + 1;
+
+  image4 =
+    _mm_cvtpi8_ps (_mm_setr_pi8
+		   (image[0], image[1], image[2], image[3], 0, 0, 0, 0));
+  _mm_store_ps (out, image4);
+  _mm_empty ();
+
+  for (i = 0; i < 4; i++)
+    if (out[i] != (float) (i + 1))
+      abort ();
+
+  image4 =
+    _mm_cvtpu8_ps (_mm_setr_pi8
+		   (image[0], image[1], image[2], image[3], 0, 0, 0, 0));
+  _mm_store_ps (out, image4);
+  _mm_empty ();
+
+  for (i = 0; i < 4; i++)
+    if (out[i] != (float) (i + 1))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46470.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46470.c
new file mode 100644
index 000000000..11eb51a03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46470.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* The pic register save adds unavoidable stack pointer references.  */
+/* { dg-skip-if "" { ia32 && { ! nonpic } }  { "*" } { "" } } */
+/* These options are selected to ensure 1 word needs to be allocated
+   on the stack to maintain alignment for the call.  This should be
+   transformed to push+pop.  We also want to force unwind info updates.  */
+/* { dg-options "-Os -fomit-frame-pointer -fasynchronous-unwind-tables" } */
+/* { dg-options "-Os -fomit-frame-pointer -mpreferred-stack-boundary=3 -fasynchronous-unwind-tables" { target ia32 } } */
+/* ms_abi has reserved stack-region.  */
+/* { dg-skip-if "" { x86_64-*-mingw* } { "*" } { "" } } */
+void f();
+void g() { f(); f(); }
+
+/* Both stack allocate and deallocate should be converted to push/pop.  */
+/* { dg-final { scan-assembler-not "sp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46491.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46491.c
new file mode 100644
index 000000000..82f704c26
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46491.c
@@ -0,0 +1,22 @@
+/* PR tree-optimization/46491 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+__attribute__((noinline)) int
+foo (int *p)
+{
+  int r;
+  asm ("movl $6, (%1)\n\txorl %0, %0" : "=r" (r) : "r" (p) : "memory");
+  return r;
+}
+
+int
+main (void)
+{
+  int p = 8;
+  if ((foo (&p) ? : p) != 6)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46647.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46647.c
new file mode 100644
index 000000000..c7e154287
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46647.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic" } */
+
+char a[5];
+int
+func1 (void)
+{
+  __builtin_memset (a,-1,sizeof (a));
+  return 0;
+}
+
+int a2[5];
+int
+func2 (void)
+{
+  __builtin_memset (a2,-1,sizeof (a2));
+  return 0;
+}
+
+char a3[5];
+int
+func3 (void)
+{
+  __builtin_memset (a3,0x8fffffff,sizeof (a3));
+  return 0;
+}
+
+char a4[5];
+int
+func4 (void)
+{
+  __builtin_memset (a4,0x8fffff00,sizeof (a4));
+  return 0;
+}
+
+int a5[5];
+int
+func5 (void)
+{
+  __builtin_memset (a5,0x8fffffff,sizeof (a5));
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "call\[\\t \]*_?memset" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46716.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46716.c
new file mode 100644
index 000000000..29c5e1e49
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46716.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse -mno-sse2" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+typedef double V __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef union
+{
+  V x;
+  double a[2];
+} u;
+
+#define EMM_FLT8(a) ((double *)&(a))
+
+void __attribute__ ((noinline))
+test (V s1, V s2)
+{
+  if (EMM_FLT8(s1)[0] != EMM_FLT8(s2)[0]
+      || EMM_FLT8(s1)[1] != EMM_FLT8(s2)[1])
+    abort ();
+}
+
+static void
+sse_test (void)
+{
+  u s1;
+
+  s1.a[0] = 1.0;
+  s1.a[1] = 2.0;
+
+  test (s1.x, s1.x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46829.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46829.c
new file mode 100644
index 000000000..d4c04d30f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46829.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fschedule-insns" } */
+
+struct S
+{
+  int i, j;
+};
+
+extern struct S s[];
+
+extern void bar (int, ...);
+
+void
+foo (int n)
+{
+  while (s[n].i)
+    bar (0, n, s[n].j, s, s[n].i / s[n].j);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46843.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46843.c
new file mode 100644
index 000000000..3b0d76d13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46843.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fschedule-insns" } */
+
+void foo (double *d1, double *u1, double *u2, double *d2, int s, int j, int i)
+{
+  int n = 1 << s;
+  double x = 0;
+
+  for (; j < n; j++)
+    x += d1[j] * d2[i];
+  d1[i] = x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46865-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46865-1.c
new file mode 100644
index 000000000..220a1c077
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46865-1.c
@@ -0,0 +1,31 @@
+/* PR rtl-optimization/46865 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern unsigned long f;
+
+#define m1(f)							\
+  if (f & 1)							\
+    asm volatile ("nop /* asmnop */\n");			\
+  else								\
+    asm volatile ("nop /* asmnop */\n");
+
+#define m2(f)							\
+  if (f & 1)							\
+    asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");	\
+  else								\
+    asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");
+
+void
+foo (void)
+{
+  m1 (f);
+}
+
+void
+bar (void)
+{
+  m2 (f);
+}
+
+/* { dg-final { scan-assembler-times "asmnop" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46865-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46865-2.c
new file mode 100644
index 000000000..4a91f7c96
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46865-2.c
@@ -0,0 +1,32 @@
+/* PR rtl-optimization/46865 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+extern unsigned long f;
+
+#define m1(f)							\
+  if (f & 1)							\
+    asm volatile ("nop /* asmnop */\n");			\
+  else								\
+    asm volatile ("nop /* asmnop */\n");
+
+#define m2(f)							\
+  if (f & 1)							\
+    asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");	\
+  else								\
+    asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");
+
+void
+foo (void)
+{
+  m1 (f);
+}
+
+void
+bar (void)
+{
+  m2 (f);
+}
+
+/* { dg-final { scan-assembler-times "asmnop" 2 } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46880.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46880.c
new file mode 100644
index 000000000..bc6d64299
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46880.c
@@ -0,0 +1,28 @@
+/* PR target/46880 */
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */
+/* { dg-require-effective-target sse2_runtime } */
+
+typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef double (*T)[2];
+
+static __attribute__ ((noinline, noclone)) __m128d
+foo (__m128d c, __m128d d)
+{
+  T cp = (T) &c;
+  T dp = (T) &d;
+  __m128d e = { (*cp)[1], (*dp)[1] };
+  return e;
+}
+
+int
+main ()
+{
+  __m128d c = { 1.0, 2.0 };
+  __m128d d = { 3.0, 4.0 };
+  union { __m128d x; double d[2]; } u;
+  u.x = foo (c, d);
+  if (u.d[0] != 2.0 || u.d[1] != 4.0)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46939.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46939.c
new file mode 100644
index 000000000..0fd8607bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr46939.c
@@ -0,0 +1,121 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+__extension__ typedef __SIZE_TYPE__ size_t;
+
+int
+php_filter_parse_int (char const *str, unsigned int str_len, long *ret)
+{
+  long ctx_value;
+  int sign;
+  int digit;
+  char const *end;
+  int tmp;
+  char const *tmp___0;
+  char const *tmp___1;
+
+  sign = 0;
+  digit = 0;
+  end = str + str_len;
+  switch ((int) *str)
+    {
+    case 45:
+      sign = 1;
+    case 43:
+      str++;
+    default:;
+      break;
+    }
+  if ((size_t) str < (size_t) end)
+    {
+      if ((int const) *str >= 49)
+	{
+	  if ((int const) *str <= 57)
+	    {
+	      if (sign)
+		{
+		  tmp = -1;
+		}
+	      else
+		{
+		  tmp = 1;
+		}
+	      tmp___0 = str;
+	      str++;
+	      ctx_value = (long) (tmp * (int) ((int const) *tmp___0 - 48));
+	    }
+	  else
+	    {
+	      return (-1);
+	    }
+	}
+      else
+	{
+	  return (-1);
+	}
+    }
+  else
+    {
+      return (-1);
+    }
+  if (end - str > 19)
+    {
+      return (-1);
+    }
+  while ((size_t) str < (size_t) end)
+    {
+      if ((int const) *str >= 48)
+	{
+	  if ((int const) *str <= 57)
+	    {
+	      tmp___1 = str;
+	      str++;
+	      digit = (int) ((int const) *tmp___1 - 48);
+	      if (!sign)
+		{
+		  if (ctx_value <=
+		      (9223372036854775807L - (long) digit) / 10L)
+		    {
+		      ctx_value = ctx_value * 10L + (long) digit;
+		    }
+		  else
+		    {
+		      goto _L;
+		    }
+		}
+	      else
+		{
+		_L:
+		  if (sign)
+		    {
+		      if (ctx_value >=
+			  ((-0x7FFFFFFFFFFFFFFF - 1) + (long) digit) / 10L)
+			{
+			  ctx_value = ctx_value * 10L - (long) digit;
+			}
+		      else
+			{
+			  return (-1);
+			}
+		    }
+		  else
+		    {
+		      return (-1);
+		    }
+		}
+	    }
+	  else
+	    {
+	      return (-1);
+	    }
+	}
+      else
+	{
+	  return (-1);
+	}
+    }
+  *ret = ctx_value;
+  return (1);
+}
+
+/* { dg-final { scan-assembler-not "idiv" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47312.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47312.c
new file mode 100644
index 000000000..03769a1cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47312.c
@@ -0,0 +1,25 @@
+/* PR target/47312 */
+/* { dg-do link } */
+/* { dg-require-effective-target lto } */
+/* { dg-require-effective-target xop } */
+/* { dg-require-effective-target c99_runtime } */
+/* { dg-options "-O -flto -mno-sse3 -mxop" } */
+/* { dg-add-options c99_runtime } */
+
+extern double fma (double, double, double);
+extern float fmaf (float, float, float);
+extern long double fmal (long double, long double, long double);
+
+volatile float f;
+volatile double d;
+volatile long double ld;
+
+int
+main ()
+{
+  f = fmaf (f, f, f);
+  d = fma (d, d, d);
+  ld = fmal (ld, ld, ld);
+  __asm__ volatile ("" : : "r" (&f), "r" (&d), "r" (&ld) : "memory");
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47315.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47315.c
new file mode 100644
index 000000000..871d3f1bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47315.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mvzeroupper" } */
+
+__attribute__ ((__target__ ("avx")))
+float bar (float f) {}
+
+void foo (float f)
+{
+    bar (f);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47381.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47381.c
new file mode 100644
index 000000000..c4b2127c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47381.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=atom" } */
+
+struct foo_t {
+  int limit;
+} foo[3];
+void
+bar () {
+  int i;
+  for (i = 0; i < 3; i++) {
+    __builtin_memset (&foo[i], 0, sizeof(*foo));
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47449.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47449.c
new file mode 100644
index 000000000..99ef32f26
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47449.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void bar (void *, void *);
+int
+foo (void *p1, void *p2)
+{
+  int ret1, ret2;
+  __asm ("" : "=D" (ret1), "=S" (ret2));
+  bar (p1, p2);
+  return ret1 + ret2;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47502-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47502-1.c
new file mode 100644
index 000000000..727afe944
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47502-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+void
+foo (const void *xxxxx, void *yyyyy, long y)
+{
+  asm volatile ("" :: "c" ((xxxxx)), "d" ((yyyyy)), "S" (y));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47502-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47502-2.c
new file mode 100644
index 000000000..a8dc1ca01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47502-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-pic" } */
+
+int
+foo (int how, const void *set, void *oset)
+{
+  int resultvar;
+  asm volatile (""
+                : "=a" (resultvar)
+                : "0" (14) , "b" (how), "c" ((set)), "d" ((oset)), "S" (65 / 8) : "memory", "cc");
+  return resultvar;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47564.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47564.c
new file mode 100644
index 000000000..5d3f25d10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47564.c
@@ -0,0 +1,42 @@
+/* PR target/47564 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+static inline unsigned long long
+foo (const unsigned char *p)
+{
+  return 1;
+}
+
+__attribute__ ((__target__ ("sse4"))) void
+bar (unsigned long long *x, const void *b, long long m)
+{
+  const unsigned char *p = (const unsigned char *) b;
+  const unsigned char *e = p + m;
+  unsigned int l = *x;
+  unsigned long long n = l;
+
+  if ((e - p) >= 8192)
+    {
+      while ((e - p) >= 128)
+	{
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	  n = __builtin_ia32_crc32di (n, foo (p));
+	}
+    }
+
+  while ((e - p) >= 16)
+    {
+      n = __builtin_ia32_crc32di (n, foo (p));
+      n = __builtin_ia32_crc32di (n, foo (p));
+    }
+  l = n;
+  *x = l;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47581.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47581.c
new file mode 100644
index 000000000..dfc02a144
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47581.c
@@ -0,0 +1,10 @@
+/* PR middle-end/47581 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fomit-frame-pointer -mpreferred-stack-boundary=4 -mincoming-stack-boundary=4" } */
+/* { dg-final { scan-assembler-not "(sub|add)l\[\\t \]*\\$\[0-9\]*,\[\\t \]*%\[re\]?sp" } } */
+
+unsigned
+foo (unsigned a, unsigned b)
+{
+  return ((unsigned long long) a * (unsigned long long) b) >> 32;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47665.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47665.c
new file mode 100644
index 000000000..10fabb517
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47665.c
@@ -0,0 +1,11 @@
+/* PR target/47665 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128d
+foo (double *x, __m128i y)
+{
+  return _mm_load_pd (x + _mm_cvtsi128_si32 (_mm_srli_si128 (_mm_slli_epi32 (y, 2), 0)));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47735.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47735.c
new file mode 100644
index 000000000..0d44df4d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47735.c
@@ -0,0 +1,16 @@
+/* PR middle-end/47735 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+unsigned
+mulh (unsigned a, unsigned b)
+{
+  unsigned long long l __attribute__ ((aligned (32)))
+    = ((unsigned long long) a * (unsigned long long) b) >> 32;
+  return l;
+}
+
+/* No need to dynamically realign the stack here.  */
+/* { dg-final { scan-assembler-not "and\[^\n\r]*%\[re\]sp" } } */
+/* Nor use a frame pointer.  */
+/* { dg-final { scan-assembler-not "%\[re\]bp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47780.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47780.c
new file mode 100644
index 000000000..89fe4093d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47780.c
@@ -0,0 +1,14 @@
+/* PR debug/47780 */
+/* { dg-do compile } */
+/* { dg-options "-O -fgcse -fgcse-las -fstack-protector-all -fno-tree-ccp -fno-tree-dominator-opts -fcompare-debug -Wno-psabi" } */
+
+typedef int V2SF __attribute__ ((vector_size (128)));
+
+V2SF
+foo (int x, V2SF a)
+{
+  V2SF b = a + (V2SF) {};
+  while (x--)
+    a += b;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47800.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47800.c
new file mode 100644
index 000000000..45c817bc6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47800.c
@@ -0,0 +1,15 @@
+/* PR target/47800 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=nocona" } */
+
+int
+foo (unsigned char *x, unsigned char *y)
+{
+  unsigned char a;
+  for (a = 0; x < y; x++)
+    if (a & 0x80)
+      a = (unsigned char) (a << 1) + 1 + *x;
+    else
+      a = (unsigned char) (a << 1) + *x;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47809.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47809.c
new file mode 100644
index 000000000..5832a65d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr47809.c
@@ -0,0 +1,13 @@
+/* PR c/47809 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+double bar (double, double);
+
+__m128d
+foo (__m128d x)
+{
+  x *= (__m128d) { bar (1.0, 1.0), 0.0 };
+  return (__m128d) ((__m128i) x ^ (__m128i) { 0, 0});
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48037-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48037-1.c
new file mode 100644
index 000000000..1b64a7d19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48037-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O -fno-math-errno" } */
+
+typedef double __m128d __attribute__((vector_size(16)));
+__m128d vsqrt1 (__m128d const x)
+{
+  double const* __restrict__ const y = (double const*)&x;
+  double const a = __builtin_sqrt(y[0]);
+  double const b = __builtin_sqrt(y[1]);
+  return (__m128d) { a, b };
+}
+
+/* Verify we do not spill x to the stack.  */
+/* { dg-final { scan-assembler-not "%rsp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-1.c
new file mode 100644
index 000000000..d9eef495c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__));
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
+typedef float __v4sf __attribute__ ((__vector_size__ (16)));
+void
+_mm_storeh_pi (__m64 *__P, __m128 __A)
+{
+  __builtin_ia32_storehps ((__v2sf *)__P, (__v4sf)__A);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-2.c
new file mode 100644
index 000000000..2b41c0bba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef int __m64 __attribute__ ((__vector_size__ (8), __may_alias__));
+typedef char __v8qi __attribute__ ((__vector_size__ (8)));
+void
+_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
+{
+    __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-3.c
new file mode 100644
index 000000000..423c59804
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3" } */
+
+void
+_mm_monitor (void const * __P, unsigned int __E, unsigned int __H)
+{
+   __builtin_ia32_monitor (__P, __E, __H);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-4.c
new file mode 100644
index 000000000..df465a313
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-4.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse2" } */
+
+void
+_mm_clflush (void const *__A)
+{
+  __builtin_ia32_clflush (__A);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-5.c
new file mode 100644
index 000000000..d6ed8e5fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48084-5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mrdrnd" } */
+
+int
+_rdrand16_step (unsigned short *__P)
+{
+  return __builtin_ia32_rdrand16_step (__P);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48237.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48237.c
new file mode 100644
index 000000000..e20446eab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48237.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fcaller-saves -fschedule-insns2 -fselective-scheduling2 -mtune=core2" } */
+
+union double_union
+{
+  double d;
+  int i[2];
+};
+
+void bar (int, ...);
+
+void
+foo (double d)
+{
+  union double_union du = { d };
+  while (1)
+    {
+      du.i[1] -= 0x100000L;
+      bar (0, du.d);
+      du.d += d;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48335-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48335-1.c
new file mode 100644
index 000000000..08c5284ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48335-1.c
@@ -0,0 +1,32 @@
+/* PR middle-end/48335 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-tree-sra -msse2" } */
+
+#include <emmintrin.h>
+
+typedef __float128 T __attribute__((may_alias));
+
+struct S
+{
+  _Complex double d __attribute__((aligned (16)));
+};
+
+void bar (struct S);
+
+void
+f1 (T x)
+{
+  struct S s;
+  *(T *) &s.d = x;
+  __real__ s.d *= 7.0;
+  bar (s);
+}
+
+void
+f2 (__m128d x)
+{
+  struct S s;
+  _mm_store_pd ((double *) &s.d, x);
+  __real__ s.d *= 7.0;
+  bar (s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48389.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48389.c
new file mode 100644
index 000000000..2ac18cdbe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48389.c
@@ -0,0 +1,13 @@
+/* PR middle-end/48389 */
+/* { dg-do compile } */
+/* { dg-options "-O -mtune=pentiumpro -Wno-abi" } */
+/* { dg-require-effective-target ia32 } */
+typedef float V2SF __attribute__ ((vector_size (128)));
+V2SF foo (int x, V2SF a)
+{
+  V2SF b = {};
+  if (x & 42)
+    b = a;
+  a += b;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48678.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48678.c
new file mode 100644
index 000000000..6f6727fff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48678.c
@@ -0,0 +1,16 @@
+/* PR target/48678 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+typedef short T __attribute__((may_alias));
+struct S { __m128i d; };
+
+__m128i
+foo (short *x, struct S *y, __m128i *z)
+{
+  struct S s = *y;
+  ((T *) &s.d)[0] = *x;
+  return _mm_cmpeq_epi16 (s.d, *z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48688.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48688.c
new file mode 100644
index 000000000..f4d663a21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48688.c
@@ -0,0 +1,24 @@
+/* PR target/48688 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int fn1 (int x) { return (x << 3) | 5; }
+int fn2 (int x) { return (x * 8) | 5; }
+int fn3 (int x) { return (x << 3) + 5; }
+int fn4 (int x) { return (x * 8) + 5; }
+int fn5 (int x) { return (x << 3) ^ 5; }
+int fn6 (int x) { return (x * 8) ^ 5; }
+long fn7 (long x) { return (x << 3) | 5; }
+long fn8 (long x) { return (x * 8) | 5; }
+long fn9 (long x) { return (x << 3) + 5; }
+long fn10 (long x) { return (x * 8) + 5; }
+long fn11 (long x) { return (x << 3) ^ 5; }
+long fn12 (long x) { return (x * 8) ^ 5; }
+long fn13 (unsigned x) { return (x << 3) | 5; }
+long fn14 (unsigned x) { return (x * 8) | 5; }
+long fn15 (unsigned x) { return (x << 3) + 5; }
+long fn16 (unsigned x) { return (x * 8) + 5; }
+long fn17 (unsigned x) { return (x << 3) ^ 5; }
+long fn18 (unsigned x) { return (x * 8) ^ 5; }
+
+/* { dg-final { scan-assembler-not "\[ \t\]x?or\[bwlq\]\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48708.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48708.c
new file mode 100644
index 000000000..355c2b269
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48708.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+typedef long long T __attribute__((may_alias));
+struct S { __m128i d; };
+
+__m128i
+foo (long long *x, struct S *y, __m128i *z)
+{
+  struct S s = *y;
+  ((T *) &s.d)[0] = *x;
+  return _mm_cmpeq_epi16 (s.d, *z);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48721.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48721.c
new file mode 100644
index 000000000..f37a16949
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48721.c
@@ -0,0 +1,51 @@
+/* PR rtl-optimization/48721 */
+/* { dg-do compile } */
+/* { dg-options "-O -foptimize-sibling-calls -fsched2-use-superblocks -fschedule-insns2 -mtune=core2" } */
+
+extern unsigned char a[];
+extern int b[], d[], e[], f[], g[], *h[], m[], *n[], o[];
+extern char c[];
+
+struct S
+{
+  unsigned char s1;
+  int s2, s3, s4, s5, s6, s7, s8;
+};
+
+__attribute__((noinline, noclone)) int
+foo (int x)
+{
+  return 0;
+}
+
+int
+bar (int x, struct S *y)
+{
+  int z;
+  switch (x)
+    {
+    case 1:
+    case 2:
+      {
+	int t2, t4, t5, t6, t7, t8;
+	z = o[y->s8 * 6];
+	t8 = *n[m[x] * 5];
+	t4 = *h[y->s7];
+	t7 = z;
+	z = g[f[x] + y->s6];
+	t6 = e[y->s5];
+	t5 = d[c[x] + y->s3 * 17];
+	if (z)
+	  t2 = b[z];
+	if (a[z] != y->s1)
+	  return foo (x);
+	y->s8 = t8;
+	y->s4 = t4;
+	y->s7 = t7;
+	y->s6 = t6;
+	y->s5 = t5;
+	y->s2 = t2;
+      }
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48722.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48722.c
new file mode 100644
index 000000000..a35fe7e22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48722.c
@@ -0,0 +1,13 @@
+/* PR middle-end/48722 */
+/* { dg-do compile } */
+/* { dg-options "-Os -mno-push-args" } */
+
+extern long long a;
+extern int b;
+void bar (int, long long);
+
+void
+foo (void)
+{
+  bar (a > 0x85, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48723.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48723.c
new file mode 100644
index 000000000..ad102090e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr48723.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-fstack-check -mavx" } */
+
+struct S0
+{
+  int f0, f1, f2, f3;
+} g_106;
+
+struct S0
+func_99 ()
+{
+  return (g_106);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49002-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49002-1.c
new file mode 100644
index 000000000..7553e8290
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49002-1.c
@@ -0,0 +1,16 @@
+/* PR target/49002 */
+/* { dg-do compile } */
+/* { dg-options "-O -mavx" } */
+
+#include <immintrin.h>
+
+void foo(const __m128d *from, __m256d *to, int s)
+{
+  __m256d var = _mm256_castpd128_pd256(from[0]);
+  var = _mm256_insertf128_pd(var, from[s], 1);
+  to[0] = var;
+}
+
+/* Ensure we load into xmm, not ymm.  */
+/* { dg-final { scan-assembler-not "vmovapd\[\t \]*\[^,\]*,\[\t \]*%ymm" } } */
+/* { dg-final { scan-assembler "vmovapd\[\t \]*\[^,\]*,\[\t \]*%xmm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49002-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49002-2.c
new file mode 100644
index 000000000..dfb83b4a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49002-2.c
@@ -0,0 +1,15 @@
+/* PR target/49002 */
+/* { dg-do compile } */
+/* { dg-options "-O -mavx" } */
+
+#include <immintrin.h>
+
+void foo(const __m128d from, __m256d *to)
+{
+  *to = _mm256_castpd128_pd256(from);
+}
+
+/* Ensure we store ymm, not xmm.  */
+/* { dg-final { scan-assembler-not "vmovapd\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+/* { dg-final { scan-assembler-not "vmovaps\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+/* { dg-final { scan-assembler "vmovap\[sd\]\[\t \]*%ymm\[0-9\]\+,\[^,\]*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49095.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49095.c
new file mode 100644
index 000000000..b7d1fb280
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49095.c
@@ -0,0 +1,73 @@
+/* PR rtl-optimization/49095 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+/* { dg-options "-Os -mregparm=2" { target ia32 } } */
+
+void foo (void *);
+
+int *
+f1 (int *x)
+{
+  if (!--*x)
+    foo (x);
+  return x;
+}
+
+int
+g1 (int x)
+{
+  if (!--x)
+    foo ((void *) 0);
+  return x;
+}
+
+#define F(T, OP, OPN) \
+T *			\
+f##T##OPN (T *x, T y)	\
+{			\
+  *x OP y;		\
+  if (!*x)		\
+    foo (x);		\
+  return x;		\
+}			\
+			\
+T			\
+g##T##OPN (T x, T y)	\
+{			\
+  x OP y;		\
+  if (!x)		\
+    foo ((void *) 0);	\
+  return x;		\
+}			\
+			\
+T *			\
+h##T##OPN (T *x)	\
+{			\
+  *x OP 24;		\
+  if (!*x)		\
+    foo (x);		\
+  return x;		\
+}			\
+			\
+T			\
+i##T##OPN (T x, T y)	\
+{			\
+  x OP 24;		\
+  if (!x)		\
+    foo ((void *) 0);	\
+  return x;		\
+}
+
+#define G(T) \
+F (T, +=, plus)		\
+F (T, -=, minus)	\
+F (T, &=, and)		\
+F (T, |=, or)		\
+F (T, ^=, xor)
+
+G (char)
+G (short)
+G (int)
+G (long)
+
+/* { dg-final { scan-assembler-not "test\[lq\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49168-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49168-1.c
new file mode 100644
index 000000000..4ca5e34d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49168-1.c
@@ -0,0 +1,12 @@
+/* PR target/49168  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movdqa\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+/* { dg-final { scan-assembler-not "movaps\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+/* { dg-final { scan-assembler "movups\[\t \]*%xmm\[0-9\]\+,\[^,\]*" } } */
+
+void
+flt128_va (void *mem, __float128 d)
+{ 
+  __builtin_memcpy (mem, &d, sizeof (d));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49504.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49504.c
new file mode 100644
index 000000000..503e6c238
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49504.c
@@ -0,0 +1,18 @@
+/* PR target/49504 */
+/* { dg-do run { target { x32 } } } */
+/* { dg-options "-O" } */
+
+unsigned long long 
+foo (const void* p, unsigned long long q)
+{
+  unsigned long long a = (((unsigned long long) ((unsigned long) p)) + q) >> 32;
+  return a;
+}
+
+int
+main ()
+{
+  if (foo (foo, 0x100000000ULL) != 0x1)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49567.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49567.c
new file mode 100644
index 000000000..309deb479
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49567.c
@@ -0,0 +1,13 @@
+/* PR debug/49567 */
+/* { dg-do compile } */
+/* { dg-options "-g -O2 -msse4" } */
+
+#include <x86intrin.h>
+
+__m128
+foo (__m128i x)
+{
+  __m128i y;
+  y = _mm_cvtepi16_epi32 (x);
+  return _mm_cvtepi32_ps (y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49715-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49715-1.c
new file mode 100644
index 000000000..d959f9e37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49715-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -mfpmath=sse" } */
+
+float func(unsigned x)
+{
+  return (x & 0xfffff) * 0.01f;
+}
+
+/* { dg-final { scan-assembler-times "cvtsi2ss" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49715-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49715-2.c
new file mode 100644
index 000000000..76d713790
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49715-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2" } */
+
+double func(unsigned long long x)
+{
+  if (x <= 0x7ffffffffffffffeULL)
+    return (x + 1) * 0.01;
+  return 0.0;
+}
+
+/* { dg-final { scan-assembler-times "cvtsi2sdq" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49781-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49781-1.c
new file mode 100644
index 000000000..60f9d50d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49781-1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fpic -mtune=generic" } */
+/* { dg-require-effective-target fpic } */
+
+static int heap[2*(256 +1+29)+1];
+static int heap_len;
+static int heap_max;
+void 
+foo (int elems)
+{
+  int n, m;
+  int max_code = -1;
+  int node = elems;
+  heap_len = 0, heap_max = (2*(256 +1+29)+1);
+  for (n = 0; n < elems; n++)
+    heap[++heap_len] = max_code = n;
+  do {
+    n = heap[1];
+    heap[1] = heap[heap_len--];
+    m = heap[1];
+    heap[--heap_max] = n;
+    heap[--heap_max] = m;
+  } while (heap_len >= 2);
+}
+
+/* { dg-final { scan-assembler-not "lea\[lq\]?\[ \t\]\\((%|)r\[a-z0-9\]*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49866.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49866.c
new file mode 100644
index 000000000..823305df7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49866.c
@@ -0,0 +1,23 @@
+/* PR target/49866 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mcmodel=large" { target lp64 } } */
+
+void fn (void *, int, int);
+int fn2 (void);
+void baz (int);
+
+static void
+foo (void *x, int y)
+{
+  int i;
+  for (i = 0; i < y; i++)
+    fn (x, fn2 (), i);
+}
+
+void
+bar (int u, int v, int w, void *x)
+{
+  baz (u);
+  foo (x, w);
+  baz (u);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49920.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49920.c
new file mode 100644
index 000000000..ef2a18512
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49920.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target ia32 } */
+
+typedef __SIZE_TYPE__ size_t;
+extern void *malloc (size_t);
+
+register unsigned int MR_mr0 asm ("esi");
+register unsigned int MR_mr1 asm ("edi");
+
+void ml_backend__ml_closure_gen_module11 (void)
+{
+  unsigned int MR_tempr1, MR_tempr2, MR_tempr3;
+
+  MR_tempr1 = (unsigned int)((char *) malloc (sizeof (unsigned int)) + 4);
+  MR_tempr3 = ((unsigned int *) MR_mr0)[0];
+
+  ((unsigned int *) (MR_tempr1 - 4))[0] = MR_tempr3;
+
+  MR_tempr2 = (unsigned int)((char *) malloc (2 * sizeof (unsigned int)));
+
+  ((unsigned int *) MR_tempr2)[1] = MR_tempr1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49927.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49927.c
new file mode 100644
index 000000000..5850597d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr49927.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+char a[1][1];
+long long b;
+
+void
+foo (void)
+{
+  --a[b][b];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50038.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50038.c
new file mode 100644
index 000000000..e111574c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50038.c
@@ -0,0 +1,20 @@
+/* PR target/50038 */
+/* { dg-options "-O2" } */
+
+void
+test (int len, unsigned char *in, unsigned char *out)
+{
+  int i;
+  unsigned char xr, xg;
+  unsigned char xy=0;
+  for (i = 0; i < len; i++)
+    {
+      xr = *in++;
+      xg = *in++;
+      xy = (unsigned char) ((19595 * xr + 38470 * xg) >> 16);
+
+      *out++ = xy;
+    }
+}
+
+/* { dg-final { scan-assembler-times "movzbl" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50155.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50155.c
new file mode 100644
index 000000000..c641d4c47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50155.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx -mno-avx2" } */
+
+void
+foo (int x, double *a, double *b, double c)
+{
+  int i;
+
+  for (i = 0; i < x; i++)
+    *a++ = *b++ * i / c;
+}
+
+/* { dg-final { scan-assembler-not "vpaddd\[ \\t\]+\[^\n\]*%ymm\[0-9\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50202.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50202.c
new file mode 100644
index 000000000..2023ec86d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50202.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fno-tree-dse -fno-dce -msse4" } */
+/* { dg-require-effective-target sse4 } */
+
+typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+
+__v16qi v;
+int i;
+
+void
+foo (void)
+{
+  i = __builtin_ia32_pcmpistri128 (v, v, 255);
+  i = 255;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50482.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50482.c
new file mode 100644
index 000000000..64c2686bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50482.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse4" } */
+
+void
+test (int code, unsigned int * image, int * colors)
+{
+  int i;
+
+  for (i = 0; i < code; ++i)
+    image[i] = (colors[i] < 0 ? ~(unsigned int) 0 : colors[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50603.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50603.c
new file mode 100644
index 000000000..101ef8548
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50603.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern int *foo;
+
+int
+bar (int x)
+{
+  return foo[x];
+}
+/* { dg-final { scan-assembler-not "lea\[lq\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50712.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50712.c
new file mode 100644
index 000000000..90cc75db3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50712.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+typedef __builtin_va_list __va_list;
+typedef __va_list __gnuc_va_list;
+typedef __gnuc_va_list va_list;
+struct MSVCRT__iobuf { };
+typedef struct MSVCRT__iobuf MSVCRT_FILE;
+typedef union _printf_arg { } printf_arg;
+MSVCRT_FILE MSVCRT__iob[20];
+int pf_print_a (va_list *);
+int __attribute__((__cdecl__))
+MSVCRT_vfprintf_s(MSVCRT_FILE* file, const char *format, va_list valist)
+{
+  if(!((file != ((void *)0))
+       || (MSVCRT__invalid_parameter(((void *)0), ((void *)0),
+				     ((void *)0), 0, 0),0)))
+      return -1;
+  return pf_printf_a(&valist);
+}
+int __attribute__((__cdecl__))
+MSVCRT_vprintf_s(const char *format, va_list valist)
+{
+  return MSVCRT_vfprintf_s((MSVCRT__iob+1),format,valist);
+}
+int __attribute__((__cdecl__))
+MSVCRT_fprintf_s(MSVCRT_FILE* file, const char *format, ...)
+{
+  va_list valist;
+  va_start (valist, format);
+  return MSVCRT_vfprintf_s(file, format, valist);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50725.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50725.c
new file mode 100644
index 000000000..c9ca7d947
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50725.c
@@ -0,0 +1,48 @@
+/* PR target/50725 */
+/* { dg-do run { target avx_runtime } } */
+/* { dg-options "-O2 -mavx" } */
+
+extern void abort (void);
+
+typedef int __attribute__((vector_size (32))) m256i;
+
+__attribute__((noinline, noclone)) void
+foo (int *x, m256i *y)
+{
+  asm volatile ("" : : "r" (x), "r" (y) : "memory");
+}
+
+__attribute__((noinline, noclone)) int
+bar (int x)
+{
+  if (x > 20)
+    return 24;
+  m256i i;
+  foo (__builtin_alloca (x), &i);
+  return 128;
+}
+
+__attribute__((noinline, noclone)) int
+baz (int d0, int d1, int d2, int d3, int d4, int d5, int x)
+{
+  if (x > 20)
+    return 24;
+  m256i i;
+  d0 += d1 + d2 + d3 + d4 + d5; d1 += d0;
+  foo (__builtin_alloca (x), &i);
+  return 128;
+}
+
+int
+main ()
+{
+  if (bar (22) != 24 || bar (20) != 128)
+    abort ();
+#ifdef __x86_64__
+  register long long r10 __asm__ ("r10") = 0xdeadbeefdeadbeefULL;
+  asm volatile ("" : "+r" (r10));
+#endif
+  if (baz (0, 0, 0, 0, 0, 0, 22) != 24 || baz (0, 0, 0, 0, 0, 0, 20) != 128)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50766.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50766.c
new file mode 100644
index 000000000..9923de424
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50766.c
@@ -0,0 +1,17 @@
+/* PR target/50766 */
+/* { dg-do assemble } */
+/* { dg-options "-mbmi2" } */
+/* { dg-require-effective-target bmi2 } */
+
+#include <x86intrin.h>
+
+unsigned z;
+
+void
+foo ()
+{
+  unsigned x = 0x23593464;
+  unsigned y = 0xF9494302;
+  z = _pext_u32(x, y);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50788.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50788.c
new file mode 100644
index 000000000..29a19634c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr50788.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -fpeel-loops -fstack-protector-all" } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32)));
+typedef double __m256d __attribute__ ((__vector_size__ (32)));
+
+__m256d foo (__m256d *__P, __m256i __M)
+{
+  return __builtin_ia32_maskloadpd256 ( __P, __M);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51235.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51235.c
new file mode 100644
index 000000000..c99d5c0e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51235.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O -ftree-vectorize -mxop -mavx2" } */
+
+void *foo (int count, void **list)
+{
+  void *minaddr = list[0];
+  int i;
+
+  for (i = 1; i < count; i++)
+    {
+      void *addr = list[i];
+      if (addr < minaddr)
+	minaddr = addr;
+    }
+
+  return minaddr;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51236.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51236.c
new file mode 100644
index 000000000..63bfaeeb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51236.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O -ftree-vectorize -mavx2" } */
+
+long foo (long *p, int i)
+{
+  long x = 0;
+
+  while (--i)
+    x ^= p[i];
+
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51393.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51393.c
new file mode 100644
index 000000000..51175c87a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51393.c
@@ -0,0 +1,21 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O -mavx" } */
+
+#include "avx-check.h"
+#include <immintrin.h>
+
+static void
+__attribute__((noinline))
+avx_test (void)
+{
+  long long in = 0x800000000ll;
+  long long out;
+
+  __m256i zero = _mm256_setzero_si256();
+  __m256i tmp  = _mm256_insert_epi64 (zero, in, 0);
+  out = _mm256_extract_epi64(tmp, 0);
+
+  if (in != out)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51987.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51987.c
new file mode 100644
index 000000000..6ac2e6395
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr51987.c
@@ -0,0 +1,33 @@
+/* PR tree-optimization/51987 */
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+union U { unsigned long long l; struct { unsigned int l, h; } i; };
+
+__attribute__((noinline, noclone)) void
+foo (char *x, char *y)
+{
+  int i;
+  for (i = 0; i < 64; i++)
+    {
+      union U u;
+      asm ("movl %1, %k0; salq $32, %0" : "=r" (u.l) : "r" (i));
+      x[i] = u.i.h;
+      union U v;
+      asm ("movl %1, %k0; salq $32, %0" : "=r" (v.l) : "r" (i));
+      y[i] = v.i.h;
+    }
+}
+
+int
+main ()
+{
+  char a[64], b[64];
+  int i;
+  foo (a, b);
+  for (i = 0; i < 64; i++)
+    if (a[i] != i || b[i] != i)
+      abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52146.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52146.c
new file mode 100644
index 000000000..4eb91c06d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52146.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mx32" } */
+
+void
+test1 (void)
+{
+  int* apic_tpr_addr = (int *) 0xfee00080;
+  *apic_tpr_addr += 4;
+}
+
+void
+test2 (void)
+{
+  int* apic_tpr_addr = (int *) 0xfee00080;
+  *apic_tpr_addr = 0;
+}
+
+/* { dg-final { scan-assembler-not "\[,\\t \]+-18874240" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52330.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52330.c
new file mode 100644
index 000000000..22ba0b21a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52330.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+void foo (int a)
+{
+  asm volatile ("# %H0" : : "r" (a));  /* { dg-error "not an offsettable" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52698.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52698.c
new file mode 100644
index 000000000..d84685cb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52698.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mx32 -maddress-mode=long" } */
+
+extern void abort (void);
+static __thread unsigned char foo [32]
+__attribute__ ((tls_model ("initial-exec"), aligned (sizeof (void *))));
+
+void
+test2 (void)
+{
+  unsigned int s;
+  for (s = 0; s < sizeof (foo); ++s)
+    {
+      if (foo [s] != s)
+	abort ();
+      foo [s] = sizeof (foo) - s;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52736.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52736.c
new file mode 100644
index 000000000..f35c1fd6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52736.c
@@ -0,0 +1,29 @@
+/* PR target/52736 */
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2" } */
+/* { dg-require-effective-target sse2_runtime } */
+
+#include <x86intrin.h>
+
+typedef double D __attribute__((may_alias));
+__attribute__((aligned(16))) static const double r[4] = { 1., 5., 1., 3. };
+
+__attribute__((noinline, noclone))
+void
+foo (int x)
+{
+  asm volatile ("" : "+g" (x) : : "memory");
+  if (x != 3)
+    __builtin_abort ();
+}
+
+int
+main ()
+{
+  __m128d t = _mm_set1_pd (5.);
+  ((D *)(&t))[0] = 1.;
+  foo (_mm_movemask_pd (_mm_cmpeq_pd (t, _mm_load_pd (&r[0]))));
+  ((D *)(&t))[1] = 3.;
+  foo (_mm_movemask_pd (_mm_cmpeq_pd (t, _mm_load_pd (&r[2]))));
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52754.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52754.c
new file mode 100644
index 000000000..0f2dbff2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52754.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fpredictive-commoning -msse2 -std=c99" } */
+/* { dg-require-effective-target sse2 } */
+
+#include <x86intrin.h>
+
+#include "isa-check.h"
+#include "sse-os-support.h"
+
+int main()
+{
+    const float mem[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+    unsigned int indexes[8];
+    for (unsigned int i = 0; i < 8; ++i) indexes[i] = i;
+
+    check_isa ();
+
+    if (!sse_os_support ())
+      exit (0);
+
+    __m128 x = _mm_setr_ps(0, 1, 2, 3);
+    for (unsigned int i = 0; i + 4 < 6; ++i) {
+        const unsigned int *ii = &indexes[i];
+        const __m128 tmp = _mm_setr_ps(mem[ii[0]], mem[ii[1]], mem[ii[2]], mem[ii[3]]);
+        if (0xf != _mm_movemask_ps(_mm_cmpeq_ps(tmp, x))) {
+            __builtin_abort();
+        }
+        x = _mm_add_ps(x, _mm_set1_ps(1));
+    }
+
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52857-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52857-1.c
new file mode 100644
index 000000000..16fd78f96
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52857-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-g -O -mx32 -maddress-mode=long" } */
+
+extern void get_BID128 (int *);
+void 
+__bid128_div (void)
+{
+  int res;
+  get_BID128 (&res);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52857-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52857-2.c
new file mode 100644
index 000000000..879240a75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52857-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-g -O -mx32 -maddress-mode=long" } */
+
+void uw_init_context_1 (void *);
+void _Unwind_ForcedUnwind (void)
+{
+  uw_init_context_1 (__builtin_dwarf_cfa ());
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52876.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52876.c
new file mode 100644
index 000000000..6d5e47a94
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52876.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { x32 } } } */
+/* { dg-options "-O2 -mx32 -maddress-mode=long" } */
+
+extern void abort (void);
+
+long long li;
+
+long long 
+__attribute__ ((noinline))
+testfunc (void* addr)
+{
+  li = (long long)(int)addr;
+  li &= 0xffffffff;
+  return li;
+}
+
+int main (void)
+{
+  volatile long long rv_test;
+  rv_test = testfunc((void*)0x87651234);
+  if (rv_test != 0x87651234ULL)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52882.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52882.c
new file mode 100644
index 000000000..5f0f12a72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52882.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+struct S1 {
+  int f0;
+  int f1;
+};
+
+int fn1 ();
+void fn2 (struct S1);
+
+void
+fn3 () {
+  struct S1 a = { 1, 0 };
+  if (fn1 ())
+    fn2 (a);
+  for (; a.f1;) {
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52883.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52883.c
new file mode 100644
index 000000000..766e87ee1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr52883.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+int a, b, d, e, f, i, j, k, l, m;
+unsigned c;
+int g[] = { }, h[0];
+
+int
+fn1 () {
+  return 0;
+}
+
+void
+fn2 () {
+  c = 0;
+  e = 0;
+  for (;; e = 0)
+    if (f > j) {
+      k = fn1 ();
+      l = (d || k) * b;
+      m = l * a;
+      h[0] = m <= i;
+    } else
+      i = g[c];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53249.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53249.c
new file mode 100644
index 000000000..c41d3e9ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53249.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O2 -mx32 -ftls-model=initial-exec -maddress-mode=short" } */
+
+struct gomp_task
+{
+  struct gomp_task *parent;
+};
+
+struct gomp_thread
+{
+  int foo1;
+  struct gomp_task *task;
+};
+
+extern __thread struct gomp_thread gomp_tls_data;
+
+void
+__attribute__ ((noinline))
+gomp_end_task (void)
+{
+  struct gomp_thread *thr = &gomp_tls_data;
+  struct gomp_task *task = thr->task;
+
+  thr->task = task->parent;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53315.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53315.c
new file mode 100644
index 000000000..350efa724
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53315.c
@@ -0,0 +1,27 @@
+/* PR target/53315 and PR target/53291 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mrtm" } */
+/* { dg-require-effective-target rtm } */
+
+#include <x86intrin.h>
+#include "rtm-check.h"
+
+static void
+rtm_test (void)
+{
+  int flag = -1;
+  unsigned status;
+
+  if ((status = _xbegin ()) == _XBEGIN_STARTED)
+    {
+      flag = _xtest ();
+      _xend ();
+    }
+  else
+    return;
+
+  if (flag != 1)
+    abort ();
+  if (_xtest () != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53366-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53366-1.c
new file mode 100644
index 000000000..c24a594b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53366-1.c
@@ -0,0 +1,5 @@
+/* PR tree-optimization/53366 */
+/* { dg-do run { target avx_runtime } } */
+/* { dg-options "-O3 -mavx" } */
+
+#include "../../gcc.dg/torture/pr53366-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53366-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53366-2.c
new file mode 100644
index 000000000..77270a0b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53366-2.c
@@ -0,0 +1,5 @@
+/* PR tree-optimization/53366 */
+/* { dg-do run { target avx_runtime } } */
+/* { dg-options "-O3 -mavx" } */
+
+#include "../../gcc.dg/torture/pr53366-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53397-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53397-1.c
new file mode 100644
index 000000000..63650366c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53397-1.c
@@ -0,0 +1,28 @@
+/* Prefetching when the step is loop invariant.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O3 -msse2 -fprefetch-loop-arrays -fdump-tree-aprefetch-details --param min-insn-to-prefetch-ratio=3 --param simultaneous-prefetches=10 -fdump-tree-aprefetch-details" } */
+
+
+double data[16384];
+void prefetch_when_non_constant_step_is_invariant(int step, int n)
+{
+     int a;
+     int b;
+     for (a = 1; a < step; a++) {
+        for (b = 0; b < n; b += 2 * step) {
+
+          int i = 2*(b + a);
+          int j = 2*(b + a + step);
+
+
+          data[j]   = data[i];
+          data[j+1] = data[i+1];
+        }
+     }
+}
+
+/* { dg-final { scan-tree-dump "Issued prefetch" "aprefetch" } } */
+/* { dg-final { scan-assembler "prefetcht0" } } */
+
+/* { dg-final { cleanup-tree-dump "aprefetch" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53397-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53397-2.c
new file mode 100644
index 000000000..b34fafc52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53397-2.c
@@ -0,0 +1,28 @@
+/* Not prefetching when the step is loop variant.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O3 -msse2 -fprefetch-loop-arrays -fdump-tree-aprefetch-details --param min-insn-to-prefetch-ratio=3 --param simultaneous-prefetches=10 -fdump-tree-aprefetch-details" } */
+
+double data[16384];
+void donot_prefetch_when_non_constant_step_is_variant(int step, int n)
+{ 
+     int a;
+     int b;
+     for (a = 1; a < step; a++,step*=2) {
+        for (b = 0; b < n; b += 2 * step) {
+
+          int i = 2*(b + a);
+          int j = 2*(b + a + step);
+
+
+          data[j]   = data[i];
+          data[j+1] = data[i+1];
+        }
+     } 
+}
+
+/* { dg-final { scan-tree-dump "Not prefetching" "aprefetch" } } */
+/* { dg-final { scan-tree-dump "loop variant step" "aprefetch" } } */
+
+/* { dg-final { cleanup-tree-dump "aprefetch" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53416.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53416.c
new file mode 100644
index 000000000..68abe8bdd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53416.c
@@ -0,0 +1,17 @@
+/* PR target/53416 */
+/* { dg-options "-O2 -mrdrnd" } */
+
+int test (void)
+{
+  unsigned int number = 0;
+  int result0, result1, result2, result3;
+
+  result0 = __builtin_ia32_rdrand32_step (&number);
+  result1 = __builtin_ia32_rdrand32_step (&number);
+  result2 = __builtin_ia32_rdrand32_step (&number);
+  result3 = __builtin_ia32_rdrand32_step (&number);
+
+  return result0 + result1 +result2 + result3;
+}
+
+/* { dg-final { scan-assembler-times "rdrand" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53425-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53425-1.c
new file mode 100644
index 000000000..00143f32a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53425-1.c
@@ -0,0 +1,15 @@
+/* PR target/53425 */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mno-sse" } */
+/* { dg-skip-if "no SSE vector" { x86_64-*-mingw* } } */
+
+typedef double __v2df __attribute__ ((__vector_size__ (16)));
+
+extern __v2df x;
+
+extern void bar (__v2df);
+void
+foo (void)
+{
+  bar (x); /* { dg-message "warning: SSE vector argument without SSE enabled changes the ABI" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53425-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53425-2.c
new file mode 100644
index 000000000..97523f35b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53425-2.c
@@ -0,0 +1,15 @@
+/* PR target/53425 */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mno-sse" } */
+/* { dg-skip-if "no SSE vector" { x86_64-*-mingw* } } */
+
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+extern __v2sf x;
+
+extern void bar (__v2sf);
+void
+foo (void)
+{
+  bar (x); /* { dg-message "warning: SSE vector argument without SSE enabled changes the ABI" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53623.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53623.c
new file mode 100644
index 000000000..35c578bd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53623.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target {! ia32 } } } */
+/* { dg-options "-O2 -fdump-rtl-ree" } */
+
+
+#include <stdint.h>
+
+typedef (*inst_t)(int64_t rdi, int64_t rsi, int64_t rdx);
+
+int16_t code[256];
+inst_t dispatch[256];
+
+void an_inst(int64_t rdi, int64_t rsi, int64_t rdx) {
+  rdx = code[rdx];
+  uint8_t inst = (uint8_t) rdx;
+  rdx >>= 8;
+  dispatch[inst](rdi, rsi, rdx);
+}
+
+int main(void) {
+  return 0;
+}
+
+/* { dg-final { scan-rtl-dump "copy needed" "ree" } } */
+/* { dg-final { cleanup-rtl-dump "ree" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53698.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53698.c
new file mode 100644
index 000000000..3acefba00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53698.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O -mx32 -maddress-mode=long -fno-tree-dominator-opts" } */
+
+extern char foo[];
+
+void
+test2 (void)
+{
+  int s;
+  for (s = 0;; ++s)
+    {
+      if (foo[s] != s)
+	__builtin_abort ();
+      foo[s] = s;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53712.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53712.c
new file mode 100644
index 000000000..5c47e20c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53712.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4.2" } */
+
+typedef char v16qi __attribute__ ((__vector_size__ (16)));
+
+int test (const char *s1, const char *s2)
+{
+  v16qi s1chars = __builtin_ia32_loaddqu ((const char *) s2);
+  v16qi s2chars = __builtin_ia32_loaddqu ((const char *) s1);
+  return __builtin_ia32_pcmpistri128 (s1chars, s2chars, 0);
+}
+
+/* { dg-final { scan-assembler-times "movdqu" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53759.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53759.c
new file mode 100644
index 000000000..b824b9845
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53759.c
@@ -0,0 +1,17 @@
+/* PR target/53759 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+/* { dg-require-effective-target avx } */
+
+#include <xmmintrin.h>
+
+void
+foo (__m128 *x, __m64 *y)
+{
+  __m128 a = _mm_setzero_ps ();
+  __m128 b = _mm_loadl_pi (a, y);
+  *x = _mm_add_ps (b, b);
+}
+
+/* { dg-final { scan-assembler "vmovlps\[ \\t\]" } } */
+/* { dg-final { scan-assembler-not "vshufps\[ \\t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53907.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53907.c
new file mode 100644
index 000000000..27e2e0298
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr53907.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msse2" } */
+
+#include <emmintrin.h>
+
+__extension__ typedef __UINTPTR_TYPE__ uintptr_t;
+
+__m128i x(char *s)
+{
+  __m128i sz,z,mvec;
+  s-=((uintptr_t) s)%16;
+  sz=_mm_load_si128((__m128i *)s);
+  return sz;
+}
+
+/* { dg-final { scan-assembler "movdqa" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54157.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54157.c
new file mode 100644
index 000000000..b5c4528b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54157.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mx32 -maddress-mode=long -ftree-vectorize" } */
+
+struct s2{
+  int n[24 -1][24 -1][24 -1];
+};
+
+struct test2{
+  struct s2 e;
+};
+
+struct test2 tmp2[4];
+
+void main1 ()
+{
+  int i,j;
+
+  for (i = 0; i < 24 -4; i++)
+      for (j = 0; j < 24 -4; j++)
+          tmp2[2].e.n[1][i][j] = 8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54400.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54400.c
new file mode 100644
index 000000000..5ed5ba066
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54400.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#include <x86intrin.h>
+
+double f (__m128d p)
+{
+  return p[0] - p[1];
+}
+
+double g1 (__m128d p)
+{
+  return p[0] + p[1];
+}
+
+double g2 (__m128d p)
+{
+  return p[1] + p[0];
+}
+
+__m128d h (__m128d p, __m128d q)
+{
+  __m128d r = { p[0] - p[1], q[0] - q[1] };
+  return r;
+}
+
+__m128d i1 (__m128d p, __m128d q)
+{
+  __m128d r = { p[0] + p[1], q[0] + q[1] };
+  return r;
+}
+
+__m128d i2 (__m128d p, __m128d q)
+{
+  __m128d r = { p[0] + p[1], q[1] + q[0] };
+  return r;
+}
+
+__m128d i3 (__m128d p, __m128d q)
+{
+  __m128d r = { p[1] + p[0], q[0] + q[1] };
+  return r;
+}
+
+__m128d i4 (__m128d p, __m128d q)
+{
+  __m128d r = { p[1] + p[0], q[1] + q[0] };
+  return r;
+}
+
+/* { dg-final { scan-assembler-times "hsubpd" 2 } } */
+/* { dg-final { scan-assembler-times "haddpd" 6 } } */
+/* { dg-final { scan-assembler-not "unpck" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54445-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54445-1.c
new file mode 100644
index 000000000..ebac532eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54445-1.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target tls_runtime } } */
+/* { dg-options "-O2" } */
+/* { dg-add-options tls } */
+
+__thread unsigned char tls_array[64];
+
+unsigned char
+__attribute__ ((noinline))
+tls_array_lookup_with_negative_constant(long long int position) {
+  return tls_array[position - 1];
+}
+
+int
+main ()
+{
+  int i;
+
+  for (i = 0; i < sizeof (tls_array) / sizeof (tls_array[0]); i++)
+    tls_array[i] = i;
+
+  for (i = 0; i < sizeof (tls_array) / sizeof (tls_array[0]); i++)
+    if (i != tls_array_lookup_with_negative_constant (i + 1))
+      __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54445-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54445-2.c
new file mode 100644
index 000000000..5151c1328
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54445-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { *-*-linux* && { ! { ia32 } } } } } */
+/* { dg-options "-O2 -fno-pic" } */
+
+__thread unsigned char tls_array[64];
+
+unsigned char
+tls_array_lookup_with_negative_constant(long long int position) {
+  return tls_array[position - 1];
+}
+
+/* { dg-final { scan-assembler "mov(b|zbl)\[ \t\](%fs:)?tls_array@tpoff-1\\(%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54457.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54457.c
new file mode 100644
index 000000000..9abfbd320
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54457.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O2 -mx32 -maddress-mode=short" } */
+
+extern char array[40];
+
+char foo (long long position)
+{
+  return array[position + 1];
+}
+
+/* { dg-final { scan-assembler-not "add\[lq\]?\[^\n\]*1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54592.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54592.c
new file mode 100644
index 000000000..20dc11c23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54592.c
@@ -0,0 +1,17 @@
+/* PR target/54592 */
+/* { dg-do compile } */
+/* { dg-options "-Os -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include <emmintrin.h>
+
+void
+func (__m128i * foo, size_t a, size_t b, int *dst)
+{
+  __m128i x = foo[a];
+  __m128i y = foo[b];
+  __m128i sum = _mm_add_epi32 (x, y);
+  *dst = _mm_cvtsi128_si32 (sum);
+}
+
+/* { dg-final { scan-assembler "paddd\[^\n\r\]*(\\(\[^\n\r\]*\\)|XMMWORD PTR)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54694.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54694.c
new file mode 100644
index 000000000..bcf82c2a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54694.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+register void *hfp __asm__("%ebp");	/* { dg-message "note: for" } */
+
+extern void g(void *);
+
+void f(int x)			/* { dg-error "frame pointer required" } */
+{
+  g(__builtin_alloca(x));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54703.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54703.c
new file mode 100644
index 000000000..e30c293c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr54703.c
@@ -0,0 +1,36 @@
+/* PR target/54703 */
+/* { dg-do run { target sse2_runtime } } */
+/* { dg-options "-O -msse2" } */
+/* { dg-additional-options "-mavx -mtune=bdver1" { target avx_runtime } } */
+
+extern void abort (void);
+typedef double V __attribute__((vector_size(16)));
+
+union {
+  unsigned long long m[2];
+  V v;
+} u = { { 0xffffffffff000000ULL, 0xffffffffff000000ULL } };
+
+static inline V
+foo (V x)
+{
+  V y = __builtin_ia32_andpd (x, u.v);
+  V z = __builtin_ia32_subpd (x, y);
+  return __builtin_ia32_mulpd (y, z);
+}
+
+void
+test (V *x)
+{
+  V a = { 2.1, 2.1 };
+  *x = foo (foo (a));
+}
+
+int
+main ()
+{
+  test (&u.v);
+  if (u.m[0] != 0x3acbf487f0a30550ULL || u.m[1] != u.m[0])
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55049-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55049-1.c
new file mode 100644
index 000000000..cb7fb9b3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55049-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fPIC -mx32" } */
+
+extern void __morestack_fail (const char *msg);
+void
+foo (void)
+{
+  static const char msg[] = "munmap of stack space failed: errno ";
+  __morestack_fail (msg);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55093.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55093.c
new file mode 100644
index 000000000..3d32a5799
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55093.c
@@ -0,0 +1,81 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mx32 -maddress-mode=long" } */
+/* { dg-skip-if "different ABI" { x86_64-*-mingw* } } */
+
+typedef union tree_node *tree;
+typedef const union tree_node *const_tree;
+typedef struct {
+  unsigned long long low;
+  long long high;
+} double_int;
+struct real_value {
+};
+struct real_format {
+  int has_signed_zero;
+};
+extern const struct real_format *   real_format_for_mode[];
+extern int real_isnegzero (const struct real_value *);
+enum tree_code { REAL_CST, SSA_NAME };
+struct tree_base {
+  enum tree_code code : 16;
+  union {
+    unsigned int version;
+  }
+  u;
+};
+extern void tree_check_failed (const_tree, const char *, int, const char *,           ...) __attribute__ ((__noreturn__));
+union tree_node {
+  struct tree_base base;
+};
+inline tree tree_check (tree __t, const char *__f, int __l, const char *__g, enum tree_code __c) {
+  if (((enum tree_code) (__t)->base.code) != __c)
+    tree_check_failed (__t, __f, __l, __g, __c, 0);
+  return __t;
+}
+struct prop_value_d {
+  int lattice_val;
+  tree value;
+  double_int mask;
+};
+typedef struct prop_value_d prop_value_t;
+static prop_value_t *const_val;
+static void canonicalize_float_value (prop_value_t *);
+typedef void (*ssa_prop_visit_stmt_fn) (prop_value_t);
+typedef void (*ssa_prop_visit_phi_fn) (void);
+typedef void (*ssa_prop_fold_stmt_fn) (void *gsi);
+typedef void (*ssa_prop_get_value_fn) ( prop_value_t *val);
+void ssa_propagate (ssa_prop_visit_stmt_fn, ssa_prop_visit_phi_fn);
+int substitute_and_fold (ssa_prop_get_value_fn, ssa_prop_fold_stmt_fn);
+void ccp_fold_stmt (void *);
+static void get_constant_value (prop_value_t *val) {
+  canonicalize_float_value (val);
+}
+static void canonicalize_float_value (prop_value_t *val) {
+  int mode;
+  struct real_value d;
+  if (val->lattice_val != 1
+      || ((enum tree_code) (val->value)->base.code) != REAL_CST)
+    return;
+  mode = val->lattice_val;
+  if (real_format_for_mode[mode]->has_signed_zero && real_isnegzero (&d))
+    ccp_fold_stmt (0);
+}
+static void set_lattice_value (tree var, prop_value_t new_val) {
+  prop_value_t *old_val = &const_val[(tree_check ((var), "",
+						  0, "",
+						  (SSA_NAME)))->base.u.version];
+  canonicalize_float_value (&new_val);
+  canonicalize_float_value (old_val);
+}
+static void ccp_visit_phi_node (void) {
+  prop_value_t new_val;
+  set_lattice_value (0, new_val);
+}
+static void ccp_visit_stmt (prop_value_t v) {
+  set_lattice_value (0, v);
+}
+unsigned int do_ssa_ccp (void) {
+  ssa_propagate (ccp_visit_stmt, ccp_visit_phi_node);
+  substitute_and_fold (get_constant_value, ccp_fold_stmt);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55116-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55116-1.c
new file mode 100644
index 000000000..de272445a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55116-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mx32 -maddress-mode=long" } */
+
+int glob_int_arr[100];
+int glob_int = 4;
+
+void
+expr_global (void)
+{
+  __builtin_prefetch (glob_int_arr + glob_int, 0, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55116-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55116-2.c
new file mode 100644
index 000000000..7ef8eade0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55116-2.c
@@ -0,0 +1,86 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mx32 -maddress-mode=long" } */
+
+typedef struct rtx_def *rtx;
+enum rtx_code { MINUS };
+union rtunion_def {
+  rtx rt_rtx;
+};
+typedef union rtunion_def rtunion;
+struct rtx_def {
+  enum rtx_code code: 16;
+  union u {
+    rtunion fld[1];
+  }
+  u;
+};
+rtx simplify_binary_operation (enum rtx_code code, int mode,
+			       rtx op0, rtx op1);
+struct simplify_plus_minus_op_data {
+  rtx op;
+  short neg;
+};
+void simplify_plus_minus (enum rtx_code code, int mode, rtx op0, rtx op1)
+{
+  struct simplify_plus_minus_op_data ops[8];
+  rtx tem = (rtx) 0;
+  int n_ops = 2, input_ops = 2;
+  int changed, canonicalized = 0;
+  int i, j;
+  __builtin_memset (ops, 0, sizeof (ops));
+  do
+    {
+      changed = 0;
+      for (i = 0; i < n_ops; i++)
+	{
+	  rtx this_op = ops[i].op;
+	  int this_neg = ops[i].neg;
+	  enum rtx_code this_code = ((enum rtx_code) (this_op)->code);
+	  switch (this_code)
+	    {
+	    case MINUS:
+	      if (n_ops == 7)
+		return;
+	      n_ops++;
+	      input_ops++;
+	      changed = 1;
+	      canonicalized |= this_neg; 
+	      break;
+	    }
+	}
+    }
+  while (changed);
+  do 
+    {
+      j =  n_ops - 1;
+      for (i = n_ops - 1; j >= 0; j--)
+	{
+	  rtx lhs = ops[j].op, rhs = ops[i].op;
+	  int lneg = ops[j].neg, rneg = ops[i].neg;
+	  if (lhs != 0 && rhs != 0)
+	    {
+	      enum rtx_code ncode = MINUS;
+	      if (((enum rtx_code) (lhs)->code) == MINUS)
+		tem = simplify_binary_operation (ncode, mode, lhs, rhs);
+	      if (tem && ! (((enum rtx_code) (tem)->code) == MINUS 
+			    && ((((((tem)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx) == lhs
+			    && ((((((tem)->u.fld[0]).rt_rtx))->u.fld[1]).rt_rtx) == rhs))
+		{
+		  lneg &= rneg;
+		  ops[i].op = tem;
+		  ops[i].neg = lneg;
+		  ops[j].op = (rtx) 0;
+		  changed = 1;
+		  canonicalized = 1;
+		}
+	    }
+	}
+      for (i = 0, j = 0; j < n_ops; j++)
+	if (ops[j].op)
+	  {
+	    ops[i] = ops[j];
+	    i++;
+	  }
+    }
+  while (changed);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55130.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55130.c
new file mode 100644
index 000000000..61b98dc93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55130.c
@@ -0,0 +1,15 @@
+/* PR middle-end/55130 */
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-O1 -mregparm=3 -mpreferred-stack-boundary=2" } */
+
+extern void bar(long long);
+
+int foo(long long a, char b, long long c, long long d)
+{
+  if (c == 0)
+    c = d;
+
+  bar(b + c);
+
+  return a == d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55141.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55141.c
new file mode 100644
index 000000000..a45775599
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55141.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options "-O -fno-split-wide-types" } */
+
+typedef struct
+{
+  long int p_x, p_y;
+} Point;
+
+static __attribute__ ((noinline, noclone))
+     void foo (Point p0, Point p1, Point p2, Point p3)
+{
+  if (p0.p_x != 1
+      || p1.p_x != 3
+      || p2.p_x != 5
+      || p3.p_x != 7)
+    __builtin_abort ();
+}
+
+int
+main (int argc, char *argv[])
+{
+  Point p0, p1, p2, p3, p4, p5;
+  p0.p_x = 1;
+  p1.p_x = 3;
+  p2.p_x = 5;
+  p3.p_x = 7;
+  foo (p0, p1, p2, p3);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55142-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55142-1.c
new file mode 100644
index 000000000..e6b5f126c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55142-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -mx32 -maddress-mode=long -fpic" } */
+
+typedef int int32_t;
+typedef unsigned int uint32_t;
+typedef int32_t Elf32_Sword;
+typedef struct
+{
+  Elf32_Sword d_tag;
+} Elf32_Dyn;
+struct link_map
+{
+  Elf32_Dyn *l_ld;
+  Elf32_Dyn *l_info[34];
+};
+extern struct link_map _dl_rtld_map __attribute__ ((visibility ("hidden")));
+static void elf_get_dynamic_info (struct link_map *l)
+{
+  Elf32_Dyn *dyn = l->l_ld;
+  Elf32_Dyn **info;
+  info = l->l_info;
+  while (dyn->d_tag != 0)
+    {
+      if ((uint32_t) (0x6ffffeff - dyn->d_tag) < 11)
+	info[0x6ffffeff - dyn->d_tag + 12] = dyn;
+      ++dyn;
+    }
+}
+void
+foo (void)
+{
+  elf_get_dynamic_info (&_dl_rtld_map);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55142-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55142-2.c
new file mode 100644
index 000000000..34f468719
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55142-2.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O3 -mx32 -maddress-mode=long -fpic" } */
+/* { dg-final { scan-assembler-not "movl\[\\t \]*%.*,\[\\t \]*-1073742592\\(%r(.x|.i|.p|\[1-9\]*)\\)" } } */
+
+typedef int int32_t;
+typedef unsigned int uint32_t;
+typedef uint32_t Elf32_Word;
+typedef int32_t Elf32_Sword;
+typedef uint32_t Elf32_Addr;
+typedef struct {
+  Elf32_Sword d_tag;
+  union {
+    Elf32_Word d_val;
+    Elf32_Addr d_ptr;
+  } d_un;
+} Elf32_Dyn;
+struct link_map {
+  Elf32_Dyn *l_ld;
+  Elf32_Dyn *l_info[34 + 16 + 3 + 12 + 11];
+};
+void
+elf_get_dynamic_info (struct link_map *l)
+{
+  Elf32_Dyn *dyn = l->l_ld;
+  Elf32_Dyn **info = l->l_info;
+  typedef Elf32_Word d_tag_utype;
+  while (dyn->d_tag != 0) {
+    if ((d_tag_utype) (0x6ffffeff - dyn->d_tag) < 11)
+      info[(0x6ffffeff - dyn->d_tag) + 34 + 16 + 3 + 12] = dyn;
+    ++dyn;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55147.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55147.c
new file mode 100644
index 000000000..5be02f11c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55147.c
@@ -0,0 +1,25 @@
+/* PR target/55147 */
+/* { dg-do run } */
+/* { dg-options "-O1" } */
+/* { dg-additional-options "-march=i486" { target ia32 } } */
+
+extern void abort (void);
+
+__attribute__((noclone, noinline)) unsigned int
+foo (unsigned long long *p, int i)
+{
+  return __builtin_bswap64 (p[i]);
+}
+
+int
+main ()
+{
+  unsigned long long p[64];
+  int i;
+  for (i = 0; i < 64; i++)
+    p[i] = 0x123456789abcdef0ULL ^ (1ULL << i) ^ (1ULL << (63 - i));
+  for (i = 0; i < 64; i++)
+    if (foo (p, i) != __builtin_bswap32 (p[i] >> 32))
+      abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55151.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55151.c
new file mode 100644
index 000000000..2bf68df4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55151.c
@@ -0,0 +1,13 @@
+/* PR rtl-optimization/55151 */
+/* { dg-do compile  { target { ! { ia32 } } } } */
+/* { dg-options "-fPIC" } */
+
+int a, b, c, d, e, f, g, h, i, j, k, l;
+void f4 (void)
+{
+  __asm__ volatile ("":[a] "=r,m" (a),[b] "=r,m" (b),[c] "=r,m" (c),
+		    [d] "=r,m" (d),[e] "=r,m" (e),[f] "=r,m" (f),
+		    [g] "=r,m" (g),[h] "=r,m" (h),[i] "=r,m" (i),
+		    [j] "=r,m" (j),[k] "=r,m" (k),[l] "=r,m" (l):"[a],m" (a),
+		    "[j],m" (j), "[k],m" (k), "[l],m" (l));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55154.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55154.c
new file mode 100644
index 000000000..2ed3f00ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55154.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -mcx16 -fpic -mcmodel=large -fno-split-wide-types" } */
+
+__int128 i;
+
+void test ()
+{
+  __sync_val_compare_and_swap (&i, i, i);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55247-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55247-2.c
new file mode 100644
index 000000000..d91b504e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55247-2.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O2 -mx32 -mtune=generic -maddress-mode=long" } */
+
+typedef unsigned int uint32_t;
+typedef uint32_t Elf32_Word;
+typedef uint32_t Elf32_Addr;
+typedef struct {
+  Elf32_Word st_name;
+  Elf32_Addr st_value;
+  Elf32_Word st_size;
+  unsigned char st_other;
+} Elf32_Sym;
+typedef struct {
+  Elf32_Word r_info;
+}
+Elf32_Rela;
+typedef struct {
+  union {
+    Elf32_Addr d_ptr;
+  }
+  d_un;
+} Elf32_Dyn;
+struct link_map   {
+  Elf32_Dyn *l_info[34];
+};
+extern void symbind32 (Elf32_Sym *);
+void
+_dl_profile_fixup (struct link_map *l, Elf32_Word reloc_arg)
+{
+  const Elf32_Sym *const symtab  = (const void *) l->l_info[6]->d_un.d_ptr;
+  const Elf32_Rela *const reloc  = (const void *) (l->l_info[23]->d_un.d_ptr + reloc_arg * sizeof (Elf32_Rela));
+  Elf32_Sym sym = symtab[(reloc->r_info) >> 8];
+  symbind32 (&sym);
+}
+
+/* { dg-final { scan-assembler-not "%xmm\[0-9\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55247.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55247.c
new file mode 100644
index 000000000..6259ea4f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55247.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O2 -mno-sse -mno-mmx -mx32 -maddress-mode=long" } */
+
+typedef unsigned int uint32_t;
+typedef uint32_t Elf32_Word;
+typedef uint32_t Elf32_Addr;
+typedef struct {
+  Elf32_Word st_name;
+  Elf32_Addr st_value;
+  Elf32_Word st_size;
+  unsigned char st_other;
+} Elf32_Sym;
+typedef struct {
+  Elf32_Word r_info;
+}
+Elf32_Rela;
+typedef struct {
+  union {
+    Elf32_Addr d_ptr;
+  }
+  d_un;
+} Elf32_Dyn;
+struct link_map   {
+  Elf32_Dyn *l_info[34];
+};
+extern void symbind32 (Elf32_Sym *);
+void
+_dl_profile_fixup (struct link_map *l, Elf32_Word reloc_arg)
+{
+  const Elf32_Sym *const symtab  = (const void *) l->l_info[6]->d_un.d_ptr;
+  const Elf32_Rela *const reloc  = (const void *) (l->l_info[23]->d_un.d_ptr + reloc_arg * sizeof (Elf32_Rela));
+  Elf32_Sym sym = symtab[(reloc->r_info) >> 8];
+  symbind32 (&sym);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55277.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55277.c
new file mode 100644
index 000000000..0bdcdc47f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55277.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1" } */
+
+int a, c;
+
+void f(long long p)
+{
+  long long b;
+
+  if(b)
+    b = p ? : 0;
+
+  for (; p; p++)
+    p *= a & (c = p *= !a < 2);
+
+  a = b += !(b & 3740917449u);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55342.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55342.c
new file mode 100644
index 000000000..0d9e6c623
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55342.c
@@ -0,0 +1,28 @@
+/* PR rtl-optimization/55342 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "notb" } } */
+
+
+void convert_image(unsigned char *in, unsigned char *out, int size) {
+    int i;
+    unsigned char * read = in,
+     * write = out;
+    for(i = 0; i < size; i++) {
+        unsigned char r = *read++;
+        unsigned char g = *read++;
+        unsigned char b = *read++;
+        unsigned char c, m, y, k, tmp;
+        c = 255 - r;
+        m = 255 - g;
+        y = 255 - b;
+	if (c < m)
+	  k = ((c) > (y)?(y):(c));
+	else
+          k = ((m) > (y)?(y):(m));
+        *write++ = c - k;
+        *write++ = m - k;
+        *write++ = y - k;
+        *write++ = k;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55359.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55359.c
new file mode 100644
index 000000000..222affc66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55359.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O2" } */
+
+#include <x86intrin.h>
+
+__m128d
+f (__m256d x)
+{
+  return *((__m128d*) ((double *) &x + 1));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55433.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55433.c
new file mode 100644
index 000000000..6a2602ad4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55433.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { *-*-darwin* } } } */
+/* { dg-options "-O1" } */
+
+typedef unsigned long long tick_t;
+extern int foo(void);
+extern tick_t tick(void);
+double test(void) {
+  struct { tick_t ticks; } st;
+  st.ticks = tick();
+  foo();
+  return (double)st.ticks;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55448.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55448.c
new file mode 100644
index 000000000..874a5077f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55448.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+#include <immintrin.h>
+
+static inline __m256 add1(const __m256 *a, const __m256 *b)
+{
+  return _mm256_add_ps(*a, *b);
+}
+
+void foo1(__m256 *a, const __m256 b)
+{
+  *a = add1(a, &b);
+}
+
+static inline __m128 add2(const __m128 *a, const __m128 *b)
+{
+  return _mm_add_ps(*a, *b);
+}
+
+void foo2(__m128 *a, const __m128 b)
+{
+  *a = add2(a, &b);
+}
+
+/* { dg-final { scan-assembler-not "vmovups" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55458.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55458.c
new file mode 100644
index 000000000..81d85ec8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55458.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-fPIC" } */
+
+int a, b, c;
+
+void
+foo (void)
+{
+  asm volatile ("":"+m" (a), "+m" (b), "+m" (c)); /* { dg-error "operand has impossible constraints" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-1.c
new file mode 100644
index 000000000..de88f60f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int x)
+{
+  asm goto ("" : : "r" (x), "r" (x + 1), "r" (x + 2), "r" (x + 3), /* { dg-error "operand has impossible constraints" } */
+	    "r" (x + 4), "r" (x + 5), "r" (x + 6), "r" (x + 7),
+	    "r" (x + 8), "r" (x + 9), "r" (x + 10), "r" (x + 11),
+	    "r" (x + 12), "r" (x + 13), "r" (x + 14), "r" (x + 15) : : lab);
+  __builtin_unreachable ();
+ lab:
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-2.c
new file mode 100644
index 000000000..114710c6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int x)
+{
+  asm goto ("" : : "r" (x), "r" (x + 1), "r" (x + 2), "r" (x + 3), /* { dg-error "operand has impossible constraints" } */
+	    "r" (x + 4), "r" (x + 5), "r" (x + 6), "r" (x + 7),
+	    "r" (x + 8), "r" (x + 9), "r" (x + 10), "r" (x + 11),
+	    "r" (x + 12), "r" (x + 13), "r" (x + 14), "r" (x + 15) : : lab);
+ lab:
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-3.c
new file mode 100644
index 000000000..2a351c3be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+bar (int x)
+{
+  asm goto ("" : : "r" (x), "r" (x + 1), "r" (x + 2), "r" (x + 3), /* { dg-error "operand has impossible constraints" } */
+	    "r" (x + 4), "r" (x + 5), "r" (x + 6), "r" (x + 7),
+	    "r" (x + 8), "r" (x + 9), "r" (x + 10), "r" (x + 11),
+	    "r" (x + 12), "r" (x + 13), "r" (x + 14), "r" (x + 15),
+	    "r" (x + 16) : : lab);
+  __builtin_unreachable ();
+ lab:
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-4.c
new file mode 100644
index 000000000..250243afb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55512-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+bar (int x)
+{
+  asm goto ("" : : "r" (x), "r" (x + 1), "r" (x + 2), "r" (x + 3), /* { dg-error "operand has impossible constraints" } */
+	    "r" (x + 4), "r" (x + 5), "r" (x + 6), "r" (x + 7),
+	    "r" (x + 8), "r" (x + 9), "r" (x + 10), "r" (x + 11),
+	    "r" (x + 12), "r" (x + 13), "r" (x + 14), "r" (x + 15),
+	    "r" (x + 16) : : lab);
+ lab:
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55590-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55590-1.c
new file mode 100644
index 000000000..a8dd91232
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55590-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+#include <immintrin.h>
+
+struct S
+{
+  __m128 a, b;
+};
+
+struct T
+{
+  int a;
+  struct S s;
+};
+
+
+void foo (struct T *p, __m128 v)
+{
+  struct S s;
+
+  s = p->s;
+  s.b = _mm_add_ps(s.b, v);
+  p->s = s;
+}
+
+/* { dg-final { scan-assembler-not "vmovups" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55590-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55590-2.c
new file mode 100644
index 000000000..afc0a6379
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55590-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+#include <immintrin.h>
+
+struct S
+{
+  __m128 a, b;
+};
+
+struct T
+{
+  int a;
+  struct S s[8];
+};
+
+
+void foo (struct T *p, int i, __m128 v)
+{
+  struct S s;
+
+  s = p->s[i];
+  s.b = _mm_add_ps(s.b, v);
+  p->s[i] = s;
+}
+
+/* { dg-final { scan-assembler-not "vmovups" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55597.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55597.c
new file mode 100644
index 000000000..0ed7a3a2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55597.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fPIC -mx32 -maddress-mode=long" } */
+
+struct initial_sp
+{
+  void *sp;
+  int mask;
+};
+
+__thread struct initial_sp __morestack_initial_sp;
+
+void foo (int *);
+
+void __morestack_release_segments (void)
+{
+  foo (&__morestack_initial_sp.mask);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55672.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55672.c
new file mode 100644
index 000000000..6f1c898c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55672.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fstack-check=generic" } */
+
+int main ()
+{
+  int x[8];
+  if (x[0] != 4)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55686.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55686.c
new file mode 100644
index 000000000..a263b08dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55686.c
@@ -0,0 +1,16 @@
+/* PR target/55686 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (long x, long *y)
+{
+  long *a = y - 64, i;
+  for (i = 0; i < x; i++)
+    {
+      long v = y[i];
+      *a++ = v;
+    }
+  register void **c __asm__ ("di");
+  goto **c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55775.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55775.c
new file mode 100644
index 000000000..1902f6883
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55775.c
@@ -0,0 +1,56 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int *ptr;
+int *fn1 (int *);
+int fn2 (int, int);
+int fn3 (void);
+int fn4 (int);
+
+static int
+foo (int x, int y, int z)
+{
+  int b;
+  asm ("" : "=a" (b), "=&d" (x) : "0" (y), "1" (x), "mr" (z));
+  return x;
+}
+
+static int
+bar (int x, int y)
+{
+  int a;
+  if (!y)
+    {
+      for (a = 0; a <= (x >> 1); )
+	;
+      a = foo (y, fn2 (2, x), x);
+      if (x)
+	a = x;
+      return a;
+    }
+}
+
+static int
+baz (int x, int y)
+{
+  int *a = ptr;
+  int t, xk1 = fn3 (), xk = x * xk1;
+  for (t = 0; t < xk; t += xk1)
+    {
+      if (fn4 (a[2]))
+	return -y;
+      a = fn1 (a);
+    }
+  return 0;
+}
+
+void
+test (int x, long y, int z)
+{
+  int a = fn3 ();
+  int b;
+  int c = bar (x, z);
+  for (b = 0; b <= y; b++)
+    c = baz (x, c);
+  fn2 (c, a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55829.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55829.c
new file mode 100644
index 000000000..be70ba2f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55829.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3 -fno-expensive-optimizations" } */
+
+typedef double __m128d __attribute__ ((__vector_size__ (16)));
+
+extern double p1[];
+extern double p2[];
+extern double ck[];
+extern int n;
+
+__attribute__((__noinline__, __noclone__)) int chk_pd (double *v1, double *v2)
+{
+  return v2[n] != v1[n];
+}
+
+static inline void sse3_test_movddup_reg_subsume_ldsd (double *i1, double *r)
+{
+  __m128d t1 = (__m128d){*i1, 0};
+  __m128d t2 = __builtin_ia32_shufpd (t1, t1, 0);
+  __builtin_ia32_storeupd (r, t2);
+}
+
+int sse3_test (void)
+{
+  int i = 0;
+  int fail = 0;
+  for (; i < 80; i += 1)
+    {
+      ck[0] = p1[0];
+      fail += chk_pd (ck, p2);
+      sse3_test_movddup_reg_subsume_ldsd (p1, p2);
+    }
+  return fail;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55845.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55845.c
new file mode 100644
index 000000000..daf04e54a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55845.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -ffast-math -fschedule-insns -mavx -mvzeroupper" } */
+
+#include "avx-check.h"
+
+#define N 100
+
+double
+__attribute__((noinline))
+foo (int size, double *y, double *x)
+{
+  double sum = 0.0;
+  int i;
+
+  for (i = 0; i < size; i++)
+    sum += y[i] * x[i];
+
+  return sum;
+}
+
+static void
+__attribute__ ((noinline))
+avx_test ()
+{
+  double x[N], y[N];
+  double s;
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      x[i] = i;
+      y[i] = i;
+    }
+
+  s = foo (N, y, x);
+
+  if (s != 328350.0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55934.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55934.c
new file mode 100644
index 000000000..ea489559c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55934.c
@@ -0,0 +1,11 @@
+/* PR inline-asm/55934 */
+/* { dg-do compile } */
+/* { dg-require-effective-target sse } */
+/* { dg-options "-std=c99 -msse" } */
+_Complex float
+foo (void)
+{
+  _Complex float x;
+  __asm ("" : "=x" (x)); /* { dg-error "inconsistent .* constraint" } */
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55981.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55981.c
new file mode 100644
index 000000000..36498d63c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr55981.c
@@ -0,0 +1,54 @@
+/* { dg-do compile  { target { ! { ia32 } } } } */
+/* { dg-options "-O2" } */
+
+volatile int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p;
+
+volatile long long y;
+
+void
+test ()
+{
+  int a_ = a;
+  int b_ = b;
+  int c_ = c;
+  int d_ = d;
+  int e_ = e;
+  int f_ = f;
+  int g_ = g;
+  int h_ = h;
+  int i_ = i;
+  int j_ = j;
+  int k_ = k;
+  int l_ = l;
+  int m_ = m;
+  int n_ = n;
+  int o_ = o;
+  int p_ = p;
+
+  int z;
+
+  for (z = 0; z < 1000; z++)
+    {
+      __atomic_store_n (&y, 0x100000002ll, __ATOMIC_SEQ_CST);
+      __atomic_store_n (&y, 0x300000004ll, __ATOMIC_SEQ_CST);
+    }
+
+  a = a_;
+  b = b_;
+  c = c_;
+  d = d_;
+  e = e_;
+  f = f_;
+  g = g_;
+  h = h_;
+  i = i_;
+  j = j_;
+  k = k_;
+  l = l_;
+  m = m_;
+  n = n_;
+  o = o_;
+  p = p_;
+}
+
+/* { dg-final { scan-assembler-times "movabs" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56022.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56022.c
new file mode 100644
index 000000000..db43162fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56022.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx" } */
+
+typedef float __m256 __attribute__ ((__vector_size__ (32), __may_alias__));
+__attribute__((target("no-avx"))) static int currentImplementationSupported()
+{}
+__m256 foo0(__m256 a) {}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56028.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56028.c
new file mode 100644
index 000000000..18ae25398
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56028.c
@@ -0,0 +1,54 @@
+/* { dg-do compile  { target { ! { ia32 } } } } */
+/* { dg-options "-O2" } */
+
+volatile int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p;
+
+volatile long long y;
+
+void
+test ()
+{
+  int a_ = a;
+  int b_ = b;
+  int c_ = c;
+  int d_ = d;
+  int e_ = e;
+  int f_ = f;
+  int g_ = g;
+  int h_ = h;
+  int i_ = i;
+  int j_ = j;
+  int k_ = k;
+  int l_ = l;
+  int m_ = m;
+  int n_ = n;
+  int o_ = o;
+  int p_ = p;
+
+  int z;
+
+  for (z = 0; z < 1000; z++)
+    {
+      y = 0x100000002ll;
+      y = 0x300000004ll;
+    }
+
+  a = a_;
+  b = b_;
+  c = c_;
+  d = d_;
+  e = e_;
+  f = f_;
+  g = g_;
+  h = h_;
+  i = i_;
+  j = j_;
+  k = k_;
+  l = l_;
+  m = m_;
+  n = n_;
+  o = o_;
+  p = p_;
+}
+
+/* { dg-final { scan-assembler-times "movabs" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56114.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56114.c
new file mode 100644
index 000000000..43e62ae3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56114.c
@@ -0,0 +1,10 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 -masm=intel" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target masm_intel } */
+
+long
+foo2 (void)
+{
+  return *(volatile int *) 0xFEE00000;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56148.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56148.c
new file mode 100644
index 000000000..78d2efba1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56148.c
@@ -0,0 +1,12 @@
+/* PR inline-asm/56148 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+foo (void)
+{
+  unsigned char e[16];
+  unsigned long a, b, c, d;
+  __asm__ __volatile__ ("" : "=d" (a), "=&c" (c), "=&D" (d), "=&a" (b)
+               : "0" (-1U), "mr" (e), "1" (128 >> 5), "2" (e), "3" (-1U));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56151.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56151.c
new file mode 100644
index 000000000..24a1b8ae4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56151.c
@@ -0,0 +1,17 @@
+/* PR rtl-optimization/56151 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int vara, varb;
+
+void
+foo (int i, int j)
+{
+  vara = varb | vara;
+}
+
+/* Verify the above is compiled into movl varb, %reg; orl %reg, vara instead
+   of longer movl vara, %reg; orl varb, %reg; movl %reg, vara.  */
+/* { dg-final { scan-assembler-not "mov\[^\n\r]*vara" { target nonpic } } } */
+/* { dg-final { scan-assembler-times "mov\[^\n\r]*varb" 1 { target nonpic } } } */
+/* { dg-final { scan-assembler-times "or\[^\n\r]*vara" 1 { target nonpic } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56225.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56225.c
new file mode 100644
index 000000000..638c0cef5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56225.c
@@ -0,0 +1,12 @@
+/* PR target/56225 */
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O2 -march=pentium3 -mtune=generic" } */
+
+void bar (int);
+
+void
+foo (int x, int y)
+{
+  __attribute__ ((vector_size (8 * sizeof (short)))) short s0 = { x };
+  bar ((short) (long) &s0 + y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56246.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56246.c
new file mode 100644
index 000000000..b4d527396
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56246.c
@@ -0,0 +1,7 @@
+/* PR target/56225 */
+/* { dg-do compile { target { ia32 && fpic } } } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -march=i686 -fpic" } */
+
+void NoBarrier_AtomicExchange (long long *ptr) {
+  while (__sync_val_compare_and_swap (ptr, 1, 0) );
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56348.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56348.c
new file mode 100644
index 000000000..af6382812
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56348.c
@@ -0,0 +1,38 @@
+/* PR target/56348 */
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O2 -fPIC -mfpmath=sse -msse2" } */
+
+typedef unsigned int size_t;
+
+extern double fabs (double __x) __attribute__ ((__nothrow__, __leaf__))
+  __attribute__ ((__const__));
+
+typedef struct cholmod_sparse_struct
+{
+  size_t ncol;
+  void *p;
+} cholmod_sparse;
+
+int cholmod_l_reallocate_sparse (size_t, cholmod_sparse *, void *);
+
+int
+cholmod_l_drop (double tol, cholmod_sparse * A)
+{
+  double aij;
+  double *Ax;
+  long long *Ap, *Ai, *Anz;
+  long long packed, i, j, nrow, ncol, p, pend, nz, values;
+  Ap = A->p;
+  ncol = A->ncol;
+  nz = 0;
+  for (j = 0; j < ncol; j++)
+    for (; p < pend; p++)
+      {
+        i = Ai[p];
+        aij = Ax[p];
+        if (i <= j && (fabs (aij) > tol || ((aij) != (aij))))
+          nz++;
+      }
+  Ap[ncol] = nz;
+  cholmod_l_reallocate_sparse (nz, A, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-1.c
new file mode 100644
index 000000000..13955bcd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-1.c
@@ -0,0 +1,26 @@
+/* PR target/56564 */
+/* { dg-do compile { target { fpic && lp64 } } } */
+/* { dg-skip-if "No symbol interposition for PIC" { *-*-mingw* *-*-cygwin* *-*-darwin* } } */
+/* { dg-options "-O3 -fpic -fdump-tree-optimized" } */
+
+struct S { long a, b; } s = { 5, 6 };
+char t[16] = { 7 };
+
+int
+foo (void)
+{
+  return ((__UINTPTR_TYPE__) &s) & 15;
+}
+
+int
+bar (void)
+{
+  return ((__UINTPTR_TYPE__) &t[0]) & 15;
+}
+
+/* { dg-final { scan-tree-dump-times "&s" 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "&t" 0 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "return 0" 1 "optimized" } } */
+/* { dg-final { scan-assembler ".align\[ \t]*16\[^:]*\[\n\r]s:" { target { *-*-linux* } } } } */
+/* { dg-final { scan-assembler ".align\[ \t]*16\[^:]*\[\n\r]t:" { target { *-*-linux* } } } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-2.c
new file mode 100644
index 000000000..fc89a4cca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-2.c
@@ -0,0 +1,25 @@
+/* PR target/56564 */
+/* { dg-do compile { target { *-*-linux* && lp64 } } } */
+/* { dg-options "-O3 -fno-pic -fdump-tree-optimized" } */
+
+struct S { long a, b; } s = { 5, 6 };
+char t[16] = { 7 };
+
+int
+foo (void)
+{
+  return ((__UINTPTR_TYPE__) &s) & 15;
+}
+
+int
+bar (void)
+{
+  return ((__UINTPTR_TYPE__) &t[0]) & 15;
+}
+
+/* { dg-final { scan-tree-dump-times "&s" 0 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "&t" 0 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "return 0" 2 "optimized" } } */
+/* { dg-final { scan-assembler ".align\[ \t]*16\[^:]*\[\n\r]s:" { target { *-*-linux* } } } } */
+/* { dg-final { scan-assembler ".align\[ \t]*16\[^:]*\[\n\r]t:" { target { *-*-linux* } } } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-3.c
new file mode 100644
index 000000000..d45bffb06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-3.c
@@ -0,0 +1,29 @@
+/* PR target/56564 */
+/* { dg-do compile { target { fpic && lp64 } } } */
+/* { dg-skip-if "No symbol interposition for PIC" { *-*-mingw* *-*-cygwin* *-*-darwin* } } */
+/* { dg-options "-O3 -fpic -fdump-tree-optimized" } */
+
+__thread struct S { long a, b; } s = { 5, 6 };
+__thread char t[16] = { 7 };
+
+int
+foo (void)
+{
+  return ((__UINTPTR_TYPE__) &s) & 15;
+}
+
+/* For backwards compatibility we don't assume that t must
+   be aligned to 16 bytes, but align it anyway.  */
+
+int
+bar (void)
+{
+  return ((__UINTPTR_TYPE__) &t[0]) & 15;
+}
+
+/* { dg-final { scan-tree-dump-times "&s" 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "&t" 1 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "return 0" 0 "optimized" } } */
+/* { dg-final { scan-assembler-not ".align\[ \t]*16\[^:]*\[\n\r]s:" { target { *-*-linux* } } } } */
+/* { dg-final { scan-assembler ".align\[ \t]*16\[^:]*\[\n\r]t:" { target { *-*-linux* } } } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-4.c
new file mode 100644
index 000000000..a0b3d3d39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56564-4.c
@@ -0,0 +1,22 @@
+/* PR target/56564 */
+/* { dg-do compile { target { *-*-linux* && lp64 } } } */
+/* { dg-options "-O3 -fno-pic -fdump-tree-optimized" } */
+
+__thread struct S { long a, b; } s = { 5, 6 };
+__thread char t[16] = { 7 };
+
+int
+foo (void)
+{
+  return ((__UINTPTR_TYPE__) &s) & 15;
+}
+
+int
+bar (void)
+{
+  return ((__UINTPTR_TYPE__) &t[0]) & 15;
+}
+
+/* { dg-final { scan-assembler-not ".align\[ \t]*16\[^:]*\[\n\r]s:" { target { *-*-linux* } } } } */
+/* { dg-final { scan-assembler ".align\[ \t]*16\[^:]*\[\n\r]t:" { target { *-*-linux* } } } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56866.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56866.c
new file mode 100644
index 000000000..fbd151745
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56866.c
@@ -0,0 +1,16 @@
+/* PR target/56866 */
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O3 -mxop" } */
+
+#define main xop_test_main
+#include "../../gcc.c-torture/execute/pr56866.c"
+#undef main
+
+#include "xop-check.h"
+
+static void
+xop_test (void)
+{
+  xop_test_main ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56903.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56903.c
new file mode 100644
index 000000000..9e6a1c391
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr56903.c
@@ -0,0 +1,18 @@
+/* PR rtl-optimization/56903 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+/* { dg-additional-options "-march=pentium3" { target ia32 } } */
+
+int a, *b, c;
+struct S { int s : 1; } *fn1 (void);
+extern int fn3 (void), fn4 (int *);
+
+void
+fn2 (void)
+{
+  int e = fn3 ();
+  char f = c + fn1 ()->s * 4;
+  if (*b && f == e)
+    a = *b;
+  fn4 (b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57003.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57003.c
new file mode 100644
index 000000000..dfa6b8b50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57003.c
@@ -0,0 +1,54 @@
+/* PR rtl-optimization/57003 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#define N 2001
+unsigned short *b, *c, *d;
+
+__attribute__ ((noinline, noclone)) unsigned
+bar (void)
+{
+  asm volatile ("" : : : "memory");
+  return N;
+}
+
+__attribute__ ((noinline, noclone)) unsigned short *
+baz (unsigned long x)
+{
+  if (x != N * sizeof (unsigned short) + 20)
+    __builtin_abort ();
+  asm volatile ("" : : : "memory");
+  return d;
+}
+
+__attribute__ ((ms_abi, noinline, noclone))
+foo (void)
+{
+  unsigned d;
+  unsigned short *e;
+  if ((d = bar ()))
+    {
+      e = baz (d * sizeof (unsigned short) + 20);
+      __builtin_memcpy (e, b, d * sizeof (unsigned short));
+      c = e;
+    }
+}
+
+int
+main ()
+{
+  unsigned short a[2 * N];
+  int i;
+  for (i = 0; i < 2 * N; i++)
+    a[i] = i + 1;
+  b = a;
+  d = a + N;
+  asm volatile ("" : : : "memory");
+  foo ();
+  for (i = 0; i < N; i++)
+    if (a[i] != i + 1 || a[i + N] != i + 1)
+      __builtin_abort ();
+  if (c != a + N)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57018.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57018.c
new file mode 100644
index 000000000..fb0d849ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57018.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-Os -fomit-frame-pointer -fno-asynchronous-unwind-tables" } */
+/* { dg-additional-options "-march=i686" { target ia32 } } */
+
+struct A { char a[16]; } a;
+
+void __attribute__((noinline, noclone))
+foo (struct A b)
+{
+  if (__builtin_memcmp (b.a, "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0", 16))
+    __builtin_abort ();
+  asm volatile ("" : : : "memory");
+}
+
+void __attribute__((noinline, noclone))
+bar (struct A b)
+{
+  foo (a);
+  a = b;
+}
+
+int
+main ()
+{
+  struct A b = { "\0\1\2\3\4\5\6\7\10\11\12\13\14\15\16\17" };
+  bar (b);
+  if (__builtin_memcmp (a.a, b.a, 16))
+    __builtin_abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57046.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57046.c
new file mode 100644
index 000000000..0aa43f9df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57046.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+struct emac {
+        unsigned reg[23];
+};
+
+struct mop {
+        unsigned long long addr;
+        unsigned int size;
+};
+
+unsigned int __attribute__((__noinline__))
+level(const struct emac *obj)
+{
+	return 0;
+}
+
+void __attribute__((__noinline__))
+info(struct emac *dev, unsigned long long addr)
+{
+	asm("" : : : "memory");
+}
+
+unsigned long long __attribute__((__noinline__))
+get_value(const struct mop *mop)
+{
+        return 0x1234567890abcdefull;
+}
+
+int __attribute__((__noinline__))
+emac_operation(struct emac *obj, struct mop *mop)
+{
+        unsigned long long addr = mop->addr;
+        int index = addr >> 2;
+	unsigned int value, old_value;
+
+        if (mop->size != 4)
+                return 0;
+
+        if (index >= 23) {
+                if (level(obj) >= 1)
+                        info(obj, addr);
+                return 0;
+        }
+
+        value = get_value(mop);
+        old_value = obj->reg[index];
+
+        info(obj, 0);
+
+        switch (index) {
+        case 0:
+                obj->reg[0] = old_value;
+                break;
+        case 7:
+        case 8:
+                obj->reg[index] = value;
+                break;
+        }
+
+        return 0;
+}
+
+int main(void)
+{
+	struct emac e = { { 0 } };
+	struct mop mop = { 32, 4 };
+
+	e.reg[8] = 0xdeadbeef;
+	emac_operation(&e, &mop);
+
+	if (e.reg[8] != 0x90abcdef)
+	   __builtin_abort();
+
+	   return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57091.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57091.c
new file mode 100644
index 000000000..4fc7ed769
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57091.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcmodel=large"  { target lp64 } } */
+void (*bar)();
+
+void foo (void)
+{
+  bar ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57097.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57097.c
new file mode 100644
index 000000000..2f0093840
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57097.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC" } */
+extern double ad[], bd[], cd[], dd[];
+extern long long all[], bll[], cll[], dll[];
+
+int
+main (int i, char **a)
+{
+  bd[i] = i + 64;
+  if (i % 3 == 0)
+    {
+      cd[i] = i;
+    }
+  dd[i] = i / 2;
+  ad[i] = i * 2;
+  if (i % 3 == 1)
+    {
+      dll[i] = 127;
+    }
+  dll[i] = i;
+  cll[i] = i * 2;
+  switch (i % 3)
+    {
+    case 0:
+      bll[i] = i + 64;
+    }
+  all[i] = i / 2;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57098.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57098.c
new file mode 100644
index 000000000..c0f1cc34c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57098.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-msse4 -mcmodel=large" } */
+
+typedef int V __attribute__((vector_size(16)));
+
+void
+foo (V *p, V *mask)
+{
+  *p = __builtin_shuffle (*p, *mask);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57106.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57106.c
new file mode 100644
index 000000000..6fccd8aac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57106.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fschedule-insns -funroll-all-loops -fcompare-debug" } */
+
+typedef void block128_f (int *, int);
+
+void
+foo (int *out, int *iv, block128_f block)
+{
+  while (1)
+    {
+      *out = *out ^ *iv;
+      block (out, *out);
+      iv = out;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57189.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57189.c
new file mode 100644
index 000000000..389052cd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57189.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler-not "movaps" } } */
+
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+int test (__v4si __A)
+{
+  return __builtin_ia32_vec_ext_v4si (__A, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57264.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57264.c
new file mode 100644
index 000000000..46fce7f04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57264.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mcld" } */
+
+void test (int x, int **pp)
+{
+  while (x)
+    {
+      int *ip = *pp;
+      int *op = *pp;
+      while (*ip)
+	{
+	  int v = *ip++;
+	  *op++ = v + 1;
+	}
+    }
+}
+
+/* { dg-final { scan-assembler-not "stosl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57275.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57275.c
new file mode 100644
index 000000000..01b9bb416
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57275.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -march=native" } */
+
+extern void abort (void);
+
+#define N 1024
+
+float a[N], b[N], c[N];
+int k[N];
+
+__attribute__((noinline, noclone)) void
+f (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    {
+      a[i] = b[k[i]];
+      b[i] = c[i];
+    }
+}
+
+int main ()
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+  {
+    k[i] = i%2;
+    b[i] = i;
+    c[i] = 179;
+  }
+
+  f ();
+
+  if (a[2] != 179 || a[3] != 179)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57293.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57293.c
new file mode 100644
index 000000000..fa016d55f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57293.c
@@ -0,0 +1,20 @@
+/* { dg-do compile  { target { ia32 } } } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+/* { dg-final { scan-assembler-not "%ebp" } } */
+
+__attribute__((__noinline__, __noclone__, __stdcall__)) void g(int a)
+{
+  __builtin_printf("in g(): %d\n", a);
+}
+
+__attribute__((__noinline__, __noclone__, __thiscall__)) void h(int a, int b)
+{
+  __builtin_printf("in h(): %d %d\n", a, b);
+}
+
+void f()
+{
+  g(0);
+  h(0, 1);
+  __builtin_puts("in f()");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57410.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57410.c
new file mode 100644
index 000000000..6ca65d000
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57410.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fpeel-loops" } */
+
+extern char outbuffer[];
+extern char buffer[];
+
+void foo(int j)
+{
+  unsigned i, fp = fp;
+  for (i = 0; i < 6; i++)
+    buffer[j++] = outbuffer[fp - i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57459.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57459.c
new file mode 100644
index 000000000..75101145a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57459.c
@@ -0,0 +1,60 @@
+/* PR rtl-optimization/57459 */
+/* { dg-do run } */
+/* { dg-options "-fno-inline -O2 -minline-all-stringops -fno-omit-frame-pointer" } */
+
+int total1[10], total2[10], total3[10], total4[10], total5[10], a[20];
+int len;
+
+void stackclean() {
+  void *ptr = __builtin_alloca(20000);
+  __builtin_memset(ptr, 0, 20000);
+}
+
+void foo(const char *s) {
+  int r1 = a[1];
+  int r2 = a[2];
+  int r3 = a[3];
+  int r4 = a[4];
+  int r5 = a[5];
+
+  len =  __builtin_strlen(s);
+
+  if (s != 0)
+    return;
+
+  while (r1) {
+   total1[r1] = r1;
+   r1--;
+  }
+
+  while (r2) {
+   total2[r2] = r2;
+   r2--;
+  }
+
+  while (r3) {
+   total3[r3] = r3;
+   r3--;
+  }
+
+  while (r4) {
+   total4[r4] = r4;
+   r4--;
+  }
+
+  while (r5) {
+   total5[r5] = r5;
+   r5--;
+  }
+}
+
+extern void abort (void);
+
+int main() {
+  stackclean();
+  foo("abcdefgh");
+  if (len != 8)
+    abort ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57655.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57655.c
new file mode 100644
index 000000000..586d33862
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57655.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx -mvzeroupper -mno-fp-ret-in-387" }
+
+/* { dg-error "x87 register return with x87 disabled" "" { target { ! ia32 } } 8 } */
+
+long double
+foo (long double x)
+{
+  return __builtin_ilogbl (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57736.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57736.c
new file mode 100644
index 000000000..120e5dc3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57736.c
@@ -0,0 +1,41 @@
+/* PR target/57736 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+#include <x86intrin.h>
+
+unsigned long long
+f1 (void)
+{
+  return __rdtsc ();
+}
+
+unsigned long long
+f2 (unsigned int *x)
+{
+  return __rdtscp (x);
+}
+
+unsigned long long
+f3 (unsigned int x)
+{
+  return __rdpmc (x);
+}
+
+void
+f4 (void)
+{
+  __rdtsc ();
+}
+
+void
+f5 (unsigned int *x)
+{
+  __rdtscp (x);
+}
+
+void
+f6 (unsigned int x)
+{
+  __rdpmc (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57756.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57756.c
new file mode 100644
index 000000000..f3faa4f81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57756.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-sse3" } */
+
+/* callee cannot be inlined into caller because it has a higher target ISA.  */
+__attribute__((always_inline,target("sse4.2")))
+__inline int callee () /* { dg-error "inlining failed in call to always_inline" }  */
+{
+  return 0;
+}
+
+__attribute__((target("sse")))
+__inline int caller ()
+{
+  return callee(); /* { dg-error "called from here" }  */
+}
+
+int main ()
+{
+  return caller();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57756_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57756_2.c
new file mode 100644
index 000000000..0227d8ff4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57756_2.c
@@ -0,0 +1,132 @@
+/* { dg-do run } */
+/* { dg-options "-mno-sse2 -mno-popcnt -mno-avx" } */
+
+
+__attribute__((always_inline,target("avx2")))
+__inline int c1 ()
+{
+  return 0;
+}
+
+__attribute__((always_inline,target("avx")))
+__inline int c2 ()
+{
+  return 0;
+}
+
+__attribute__((always_inline,target("popcnt")))
+__inline int c3 ()
+{
+  return 0;
+}
+
+__attribute__((always_inline,target("sse4.2")))
+__inline int c4 ()
+{
+  return 0;
+}
+
+__attribute__((always_inline,target("sse4.1")))
+__inline int c5 ()
+{
+  return 0;
+}
+
+__attribute__((always_inline,target("ssse3")))
+__inline int c6 ()
+{
+  return 0;
+}
+
+__attribute__((always_inline,target("sse3")))
+__inline int c7 ()
+{
+  return 0;
+}
+
+__attribute__((always_inline,target("sse2")))
+__inline int c8 ()
+{
+  return 0;
+}
+
+int nop ()
+{
+  return 1;
+}
+
+#pragma GCC push_options
+#pragma GCC target("sse2")
+int C8 ()
+{
+  return c8 ();
+}
+#pragma GCC pop_options
+
+
+#pragma GCC push_options
+#pragma GCC target("sse3")
+int C7 ()
+{
+  return c7 ();
+}
+#pragma GCC pop_options
+
+
+#pragma GCC push_options
+#pragma GCC target("ssse3")
+int C6 ()
+{
+  return c6 ();
+}
+#pragma GCC pop_options
+
+
+#pragma GCC push_options
+#pragma GCC target("sse4.1")
+int C5 ()
+{
+  return c5 ();
+}
+#pragma GCC pop_options
+
+
+#pragma GCC push_options
+#pragma GCC target("sse4.2")
+int C4 ()
+{
+  return c4 ();
+}
+#pragma GCC pop_options
+
+
+#pragma GCC push_options
+#pragma GCC target("popcnt")
+int C3 ()
+{
+  return c3 ();
+}
+#pragma GCC pop_options
+
+
+#pragma GCC push_options
+#pragma GCC target("avx")
+int C2 ()
+{
+  return c2 ();
+}
+#pragma GCC pop_options
+
+
+#pragma GCC push_options
+#pragma GCC target("avx2")
+int C1 ()
+{
+  return c1 ();
+}
+#pragma GCC pop_options
+
+int main ()
+{
+  return C1 () + C2 () + C3 () + C4 () + C5 () + C6 () + C7 () + C8 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57777.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57777.c
new file mode 100644
index 000000000..9c1a392aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57777.c
@@ -0,0 +1,13 @@
+/* PR target/57777 */
+/* { dg-do assemble { target avx2 } } */
+/* { dg-options "-O3 -mavx2" } */
+/* { dg-additional-options "-fpic" { target fpic } } */
+
+void
+foo (unsigned long *x, int *y)
+{
+  static unsigned long b[2] = { 0x0UL, 0x9908b0dfUL };
+  int c;
+  for (c = 0; c < 512; c++)
+    x[c] = b[x[c] & 1UL];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57807.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57807.c
new file mode 100644
index 000000000..48c1e99e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57807.c
@@ -0,0 +1,11 @@
+/* { dg-do assemble } */
+/* { dg-options "-msse2 -masm=intel" } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-require-effective-target masm_intel } */
+
+typedef double __v2df __attribute__((__vector_size__(16)));
+typedef double __m128d __attribute__((__vector_size__(16), __may_alias__));
+
+__m128d _mm_unpacklo_pd(__m128d __A, __m128d __B) {
+  return (__m128d)__builtin_ia32_unpcklpd((__v2df)__A, (__v2df)__B);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57819.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57819.c
new file mode 100644
index 000000000..b086a40c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57819.c
@@ -0,0 +1,38 @@
+/* PR target/57819 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=core2" } */
+
+void foo (void);
+
+__extension__ typedef __INTPTR_TYPE__ intptr_t;
+
+int
+test1 (intptr_t x, intptr_t n)
+{
+  n &= sizeof (intptr_t) * __CHAR_BIT__ - 1;
+
+  if (x & ((intptr_t) 1 << n))
+    foo ();
+
+  return 0;
+}
+
+int
+test2 (intptr_t x, intptr_t n)
+{
+  if (x & ((intptr_t) 1 << ((int) n & (sizeof (intptr_t) * __CHAR_BIT__ - 1))))
+    foo ();
+
+  return 0;
+}
+
+int
+test3 (intptr_t x, intptr_t n)
+{
+  if (x & ((intptr_t) 1 << ((int) n & ((int) sizeof (intptr_t) * __CHAR_BIT__ - 1))))
+    foo ();
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "and\[lq\]\[ \t\]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57848.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57848.c
new file mode 100644
index 000000000..c686b3728
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57848.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+extern unsigned int __builtin_ia32_crc32si (unsigned int, unsigned int);
+#pragma GCC target("sse4.2")
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57915.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57915.c
new file mode 100644
index 000000000..0b143e0cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr57915.c
@@ -0,0 +1,33 @@
+/* PR rtl-optimization/57915 */
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+extern struct T { char a[8]; char b[16]; } t;
+int c;
+void foo (void);
+
+extern inline char *
+baz (char *x, const char *y)
+{
+  const char *e = y;
+  unsigned long f, g;
+  asm ("" : "+c" (f), "+D" (e) : "a" ('\0'), "X" (*e));
+  g = e - 1 - y;
+  __builtin_memcpy (x, y, g);
+  x[g] = '\0';
+  return x;
+}
+
+void
+bar (void)
+{
+  char d[16];
+  baz (d, t.b);
+
+  for (;;)
+    {
+      foo ();
+      if (c)
+	baz (d, t.b);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58048.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58048.c
new file mode 100644
index 000000000..a7249d0a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58048.c
@@ -0,0 +1,11 @@
+/* PR target/58048 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void
+div3 (void)
+{
+    double tmp1;
+
+    asm volatile ("fscale":"=t" (tmp1):"0" (0), "u" (0)); /* { dg-error "inconsistent operand constraints in an 'asm'"  } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58137.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58137.c
new file mode 100644
index 000000000..0a7daf83c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58137.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx2" } */
+
+typedef unsigned int U32;
+
+struct sv {
+  void* sv_any;
+  U32 sv_refcnt;
+  U32 sv_flags;
+};
+typedef struct sv SV;
+
+struct xrv {
+  SV * xrv_rv;
+};
+typedef struct xrv XRV;
+
+extern XRV * PL_xrv_root;
+
+void
+more_xrv (void)
+{
+  register XRV* xrv;
+  register XRV* xrvend;
+  xrv = PL_xrv_root;
+  xrvend = &xrv[200 / sizeof (XRV) - 1];
+  while (xrv < xrvend)
+  {
+    xrv->xrv_rv = (SV*)(xrv + 1);
+    xrv++;
+  }
+  xrv->xrv_rv = 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58218.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58218.c
new file mode 100644
index 000000000..414524205
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58218.c
@@ -0,0 +1,5 @@
+/* PR target/58218 */
+/* { dg-do assemble { target lp64 } } */
+/* { dg-options "-mcmodel=medium" } */
+
+struct { float x[16385]; } a = { { 0.f, } };
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58418.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58418.c
new file mode 100644
index 000000000..27634c9c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58418.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+int a, b, *c = &b, d = -1, e, f, *g, *h = &f, **i = &g, j;
+
+unsigned int
+foo (unsigned int p)
+{
+  return p == 0 ? 0 : 1 / p;
+}
+
+static int *
+bar ()
+{
+  *c = *h = foo (d) & (-9 < d);
+  for (e = 0; e; e++)
+    ;
+  return 0;
+}
+
+int
+main ()
+{
+  for (; j; j++)
+    for (;; a--)
+      ;
+  *i = bar ();
+  if (f != 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58679-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58679-1.c
new file mode 100644
index 000000000..91db8e63e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58679-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+typedef struct { char a; long long b; } S;
+
+S foo (S x, S y)
+{
+  S z;
+
+  z.a = 0;
+  z.b = x.b / y.b;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58679-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58679-2.c
new file mode 100644
index 000000000..b63545bc0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58679-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+int f (long long a, long long b)
+{
+  return (a * b) >> 16;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58690.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58690.c
new file mode 100644
index 000000000..87a87cc9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58690.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O2 -mx32 -maddress-mode=short" } */
+
+struct gomp_thread
+{
+  char foo[41];
+};
+extern __thread struct gomp_thread gomp_tls_data;
+void
+foo (void)
+{
+  __builtin_memset (&gomp_tls_data, '\0', sizeof (gomp_tls_data));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58759.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58759.c
new file mode 100644
index 000000000..8257dde53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58759.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+
+int a, b, c, d, e, f, h, l, m, n, k, o;
+long long g;
+
+struct S
+{
+  int f1;
+  int f2;
+  int f3;
+  int f4;
+};
+
+static struct S i = {0,0,0,0}, j;
+
+void
+foo ()
+{
+  m = 1 & d;
+  n = b + c;
+  o = k >> 1;
+  f = 0 == e;
+}
+
+int
+main ()
+{
+  for (; h < 1; h++)
+    {
+      g = 1 | (0 > 1 - a ? 0 : a);
+      foo ();
+      for (l = 0; l < 3; l++)
+      j = i;
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58853.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58853.c
new file mode 100644
index 000000000..046da8bee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58853.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-minline-all-stringops" } */
+/* { dg-additional-options "-mtune=pentiumpro" { target { ia32 } } } */
+
+void
+my_memcpy (char *dest, const char *src, int n)
+{
+  __builtin_memcpy (dest, src, n);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58944.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58944.c
new file mode 100644
index 000000000..9a92e9b6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr58944.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-Wunused-macros" } */
+
+#pragma GCC push_options
+#pragma GCC target("xsaveopt")
+void fn1(void) {}
+#pragma GCC pop_options
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59021.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59021.c
new file mode 100644
index 000000000..a1df27b10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59021.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -mvzeroupper" } */
+
+extern void abort (void);
+
+struct S {
+  int i1;
+  int i2;
+  int i3;
+};
+
+typedef double v4df  __attribute__ ((vector_size (32)));
+
+extern int foo (v4df, int i1, int i2, int i3, int i4, int i5, struct S s);
+
+void bar (v4df v, struct S s)
+{
+  int r = foo (v, 1, 2, 3, 4, 5, s);
+  if (r)
+    abort ();
+}
+
+/* { dg-final { scan-assembler-not "vzeroupper" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59034-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59034-1.c
new file mode 100644
index 000000000..1f4c4e04a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59034-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O -mx32 -mtune=corei7 -maddress-mode=short" } */
+
+extern int foo(int, ...);
+int bar(void) {
+  long double l = 1.2345E6;
+  foo(0, l);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59034-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59034-2.c
new file mode 100644
index 000000000..14e594ba6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59034-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target maybe_x32 } */
+/* { dg-options "-O -mx32 -mtune=corei7 -maddress-mode=long" } */
+
+extern int foo(int, ...);
+int bar(void) {
+  long double l = 1.2345E6;
+  foo(0, l);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59099.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59099.c
new file mode 100644
index 000000000..cf4a8da7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59099.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fPIC" } */
+
+void (*pfn)(void);
+
+struct s
+{
+  void** q;
+  int h;
+  int t;
+  int s;
+};
+
+
+void* f (struct s *, struct s *) __attribute__ ((noinline, regparm(1)));
+
+void*
+__attribute__ ((regparm(1)))
+f (struct s *p, struct s *p2)
+{
+  void *gp, *gp1;
+  int t, h, s, t2, h2, c, i;
+
+  if (p2->h == p2->t)
+    return 0;
+
+  (*pfn) ();
+
+  h = p->h;
+  t = p->t;
+  s = p->s;
+
+  h2 = p2->h;
+  t2 = p2->t;
+
+  gp = p2->q[h2++];
+
+  c = (t2 - h2) / 2;
+  for (i = 0; i != c; i++)
+    {
+      if (t == h || (h == 0 && t == s - 1))
+	break;
+      gp1 = p2->q[h2++];
+      p->q[t++] = gp1;
+      if (t == s)
+	t = 0;
+    }
+
+  p2->h = h2;
+  return gp;
+}
+
+static void gn () { }
+
+int
+main()
+{
+  struct s s1, s2;
+  void *q[10];
+
+  pfn = gn;
+
+  s1.q = q;
+  s1.h = 0;
+  s1.t = 2;
+  s1.s = 4;
+
+  s2.q = q;
+  s2.h = 0;
+  s2.t = 4;
+  s2.s = 2;
+
+  f (&s1, &s2);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59133.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59133.c
new file mode 100644
index 000000000..ef8ef741d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59133.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -ffast-math -march=core-avx2" } */
+
+#define XX 0
+#define YY 1
+#define ZZ 2
+#define DIM 3
+typedef float matrix[DIM][DIM];
+typedef float rvec[DIM];
+extern int det (matrix);
+extern void foo(matrix);
+
+void bar1 (int n,int *index,rvec x[],matrix trans)
+{
+  float   xt,yt,zt;
+  int    i,ii;
+  
+  for(i=0; (i<n); i++) {
+    ii=index ? index[i] : i;
+    xt=x[ii][XX];
+    yt=x[ii][YY];
+    zt=x[ii][ZZ];
+    x[ii][XX]=trans[XX][XX]*xt+trans[XX][YY]*yt+trans[XX][ZZ]*zt;
+    x[ii][YY]=trans[YY][XX]*xt+trans[YY][YY]*yt+trans[YY][ZZ]*zt;
+    x[ii][ZZ]=trans[ZZ][XX]*xt+trans[ZZ][YY]*yt+trans[ZZ][ZZ]*zt;
+  }
+}
+
+
+void bar2 (int n, rvec x[]) 
+{
+  int     m;
+  matrix  trans;
+  
+  foo (trans);
+  
+  if (det (trans) < 0) {
+    for(m=0; (m<DIM); m++)
+      trans[ZZ][m] = -trans[ZZ][m];
+  }  
+  bar1 (n,(int*) 0,x,trans);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59153.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59153.c
new file mode 100644
index 000000000..262726a94
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59153.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -flive-range-shrinkage -mdispatch-scheduler -march=bdver1" } */
+
+int foo (float f)
+{
+  union
+  {
+    float f;
+    int i;
+  } z = { .f = f };
+
+  return z.i - 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59363.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59363.c
new file mode 100644
index 000000000..a4e124035
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59363.c
@@ -0,0 +1,24 @@
+/* PR target/59363 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mtune=amdfam10" } */
+
+typedef struct {
+  int ctxlen;
+  long interhunkctxlen;
+  int flags;
+  long find_func;
+  void *find_func_priv;
+  int hunk_func;
+} xdemitconf_t;
+
+__attribute__((noinline))
+int xdi_diff(xdemitconf_t *xecfg) {
+  if (xecfg->hunk_func == 0)
+    __builtin_abort();
+  return 0;
+}
+int main() {
+  xdemitconf_t xecfg = {0};
+  xecfg.hunk_func = 1;
+  return xdi_diff(&xecfg);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390.c
new file mode 100644
index 000000000..7dc925ae9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -O3" } */
+
+extern double fma (double, double, double);
+void fun() __attribute__((target("fma")));
+
+void 
+other_fun(double *restrict out, double * restrict a, double * restrict b, double * restrict c, int n)
+{
+    int i;
+    for (i = 0; i < n; i++) {
+        out[i] = fma(a[i], b[i], c[i]);
+    }   
+}
+
+/* { dg-final { scan-assembler-not "vfmadd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390_1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390_1.c
new file mode 100644
index 000000000..632eb6f9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390_1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -O3" } */
+
+extern double fma (double, double, double);
+void fun() __attribute__((target("fma")));
+
+__attribute__((target("fma")))
+void 
+other_fun(double *restrict out, double * restrict a, double * restrict b, double * restrict c, int n)
+{
+    int i;
+    for (i = 0; i < n; i++) {
+        out[i] = fma(a[i], b[i], c[i]);
+    }   
+}
+
+/* { dg-final { scan-assembler "vfmadd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390_2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390_2.c
new file mode 100644
index 000000000..6142a085e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59390_2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -O3 -mfma" } */
+
+extern double fma (double, double, double);
+void fun() __attribute__((target("fma")));
+
+void 
+other_fun(double *restrict out, double * restrict a, double * restrict b, double * restrict c, int n)
+{
+    int i;
+    for (i = 0; i < n; i++) {
+        out[i] = fma(a[i], b[i], c[i]);
+    }   
+}
+
+/* { dg-final { scan-assembler "vfmadd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59405.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59405.c
new file mode 100644
index 000000000..1136e2e45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59405.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-mmmx -mfpmath=387" } */
+
+#include "mmx-check.h"
+
+#include <mmintrin.h>
+
+typedef float float32x2_t __attribute__ ((vector_size (8)));
+
+float
+foo32x2_be (float32x2_t x)
+{
+  _mm_empty ();
+  return x[1];
+}
+
+static void
+mmx_test (void)
+{
+  float32x2_t b = { 0.0f, 1.0f };
+
+  if (foo32x2_be (b) != 1.0f)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59470.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59470.c
new file mode 100644
index 000000000..0d9952fb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59470.c
@@ -0,0 +1,17 @@
+/* PR middle-end/58956 */
+/* PR middle-end/59470 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+int a, b, d[1024];
+
+int
+main ()
+{
+  int c = a;
+  asm ("{movl $6, (%2); movl $1, %0|mov dword ptr [%2], 6; mov %0, 1}"
+       : "=r" (d[c]) : "rm" (b), "r" (&a) : "memory");
+  if (d[0] != 1 || d[6] != 0)
+    __builtin_abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-1.c
new file mode 100644
index 000000000..18db93a9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-1.c
@@ -0,0 +1,31 @@
+/* PR target/59501 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx -mno-accumulate-outgoing-args" } */
+/* { dg-require-effective-target avx } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include CHECK_H
+
+typedef double V __attribute__ ((vector_size (32)));
+
+__attribute__((noinline, noclone)) V
+foo (double *x, unsigned *y)
+{
+  V r = { x[y[0]], x[y[1]], x[y[2]], x[y[3]] };
+  return r;
+}
+
+static void
+TEST (void)
+{
+  double a[16];
+  unsigned b[4] = { 5, 0, 15, 7 };
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = 0.5 + i;
+  V v = foo (a, b);
+  if (v[0] != 5.5 || v[1] != 0.5 || v[2] != 15.5 || v[3] != 7.5)
+    __builtin_abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-1a.c
new file mode 100644
index 000000000..5b468e556
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-1a.c
@@ -0,0 +1,17 @@
+/* PR target/59501 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx -mno-accumulate-outgoing-args" } */
+
+typedef double V __attribute__ ((vector_size (32)));
+
+V
+foo (double *x, unsigned *y)
+{
+  V r = { x[y[0]], x[y[1]], x[y[2]], x[y[3]] };
+  return r;
+}
+
+/* Verify no dynamic realignment is performed.  */
+/* { dg-final { scan-assembler-not "and\[^\n\r]*sp" } } */
+/* And DRAP isn't needed either.  */
+/* { dg-final { scan-assembler-not "r10" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-2.c
new file mode 100644
index 000000000..1d53d2ead
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-2.c
@@ -0,0 +1,6 @@
+/* PR target/59501 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx -maccumulate-outgoing-args" } */
+/* { dg-require-effective-target avx } */
+
+#include "pr59501-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-2a.c
new file mode 100644
index 000000000..c0fe36269
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-2a.c
@@ -0,0 +1,10 @@
+/* PR target/59501 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx -maccumulate-outgoing-args" } */
+
+#include "pr59501-1a.c"
+
+/* Verify no dynamic realignment is performed.  */
+/* { dg-final { scan-assembler-not "and\[^\n\r]*sp" } } */
+/* And DRAP isn't needed either.  */
+/* { dg-final { scan-assembler-not "r10" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-3.c
new file mode 100644
index 000000000..f27e9b3bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-3.c
@@ -0,0 +1,31 @@
+/* PR target/59501 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx -mno-accumulate-outgoing-args" } */
+/* { dg-require-effective-target avx } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include CHECK_H
+
+typedef double V __attribute__ ((vector_size (32)));
+
+__attribute__((noinline, noclone)) V
+foo (double *x, int a, int b, int c, int d, int e, int f, unsigned *y)
+{
+  V r = { x[y[0]], x[y[1]], x[y[2]], x[y[3]] };
+  return r;
+}
+
+static void
+TEST (void)
+{
+  double a[16];
+  unsigned b[4] = { 5, 0, 15, 7 };
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = 0.5 + i;
+  V v = foo (a, 0, 0, 0, 0, 0, 0, b);
+  if (v[0] != 5.5 || v[1] != 0.5 || v[2] != 15.5 || v[3] != 7.5)
+    __builtin_abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-3a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-3a.c
new file mode 100644
index 000000000..ded4336fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-3a.c
@@ -0,0 +1,15 @@
+/* PR target/59501 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx -mno-accumulate-outgoing-args" } */
+
+typedef double V __attribute__ ((vector_size (32)));
+
+V
+foo (double *x, int a, int b, int c, int d, int e, int f, unsigned *y)
+{
+  V r = { x[y[0]], x[y[1]], x[y[2]], x[y[3]] };
+  return r;
+}
+
+/* Verify no dynamic realignment is performed.  */
+/* { dg-final { scan-assembler-not "and\[^\n\r]*sp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-4.c
new file mode 100644
index 000000000..57da10780
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-4.c
@@ -0,0 +1,6 @@
+/* PR target/59501 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx -maccumulate-outgoing-args" } */
+/* { dg-require-effective-target avx } */
+
+#include "pr59501-3.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-4a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-4a.c
new file mode 100644
index 000000000..5c3cb683a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-4a.c
@@ -0,0 +1,8 @@
+/* PR target/59501 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx -maccumulate-outgoing-args" } */
+
+#include "pr59501-3a.c"
+
+/* Verify no dynamic realignment is performed.  */
+/* { dg-final { scan-assembler-not "and\[^\n\r]*sp" { xfail *-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-5.c
new file mode 100644
index 000000000..2ec9f0cb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-5.c
@@ -0,0 +1,40 @@
+/* PR target/59501 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx -mno-accumulate-outgoing-args" } */
+/* { dg-require-effective-target avx } */
+
+#define CHECK_H "avx-check.h"
+#define TEST avx_test
+
+#include CHECK_H
+
+typedef double V __attribute__ ((vector_size (32)));
+
+__attribute__((noinline, noclone)) void
+bar (char *p)
+{
+  p[0] = 1;
+  p[37] = 2;
+  asm volatile ("" : : "r" (p) : "memory");
+}
+
+__attribute__((noinline, noclone)) V
+foo (double *x, int a, int b, int c, int d, int e, int f, unsigned *y)
+{
+  bar (__builtin_alloca (a + b + c + d + e + f));
+  V r = { x[y[0]], x[y[1]], x[y[2]], x[y[3]] };
+  return r;
+}
+
+static void
+TEST (void)
+{
+  double a[16];
+  unsigned b[4] = { 5, 0, 15, 7 };
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = 0.5 + i;
+  V v = foo (a, 0, 30, 0, 0, 8, 0, b);
+  if (v[0] != 5.5 || v[1] != 0.5 || v[2] != 15.5 || v[3] != 7.5)  
+    __builtin_abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-6.c
new file mode 100644
index 000000000..8d166cef2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59501-6.c
@@ -0,0 +1,6 @@
+/* PR target/59501 */
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx -maccumulate-outgoing-args" } */
+/* { dg-require-effective-target avx } */
+
+#include "pr59501-5.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59539-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59539-1.c
new file mode 100644
index 000000000..9b34053c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59539-1.c
@@ -0,0 +1,16 @@
+/* PR target/59539 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx" } */
+
+#include <immintrin.h>
+
+int
+foo (void *p1, void *p2)
+{
+  __m128i d1 = _mm_loadu_si128 ((__m128i *) p1);
+  __m128i d2 = _mm_loadu_si128 ((__m128i *) p2);
+  __m128i result = _mm_cmpeq_epi16 (d1, d2);
+  return _mm_movemask_epi8 (result);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59539-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59539-2.c
new file mode 100644
index 000000000..b53b8c407
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59539-2.c
@@ -0,0 +1,16 @@
+/* PR target/59539 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx2" } */
+
+#include <immintrin.h>
+
+int
+foo (void *p1, void *p2)
+{
+  __m256i d1 = _mm256_loadu_si256 ((__m256i *) p1);
+  __m256i d2 = _mm256_loadu_si256 ((__m256i *) p2);
+  __m256i result = _mm256_cmpeq_epi16 (d1, d2);
+  return _mm256_movemask_epi8 (result);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqu" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59544.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59544.c
new file mode 100644
index 000000000..5499a53d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59544.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx -ftree-vectorize -fdump-tree-vect-details" } */
+
+void test1(short * __restrict__ x, short * __restrict__ y, short * __restrict__ z)
+{
+    int i;
+    for (i=127; i>=0; i--) {
+	x[i] = y[127-i] + z[127-i];
+    }
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59588-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59588-1.c
new file mode 100644
index 000000000..6f5fb7238
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59588-1.c
@@ -0,0 +1,7 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-march=i686" } */
+
+#ifndef __tune_i686__
+#error "__tune_i686__ should be defined for this test"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59588-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59588-2.c
new file mode 100644
index 000000000..7c427e3e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59588-2.c
@@ -0,0 +1,7 @@
+/* { dg-do preprocess } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mtune=i686" } */
+
+#ifndef __tune_i686__
+#error "__tune_i686__ should be defined for this test"
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59591-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59591-1.c
new file mode 100644
index 000000000..a88c6fd93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59591-1.c
@@ -0,0 +1,17 @@
+/* PR tree-optimization/59591 */
+/* { dg-do run } */
+/* { dg-options "-O2 -fopenmp-simd -mavx2 -fno-vect-cost-model" } */
+/* { dg-require-effective-target avx2 } */
+
+#define CHECK_H "avx2-check.h"
+#define TEST avx2_test
+
+#include "../../gcc.dg/vect/pr59591-1.c"
+
+#include CHECK_H
+
+static void
+TEST (void)
+{
+  bar ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59591-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59591-2.c
new file mode 100644
index 000000000..c0323649b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59591-2.c
@@ -0,0 +1,17 @@
+/* PR tree-optimization/59591 */
+/* { dg-do run } */
+/* { dg-options "-O2 -fopenmp-simd -mavx2 -fno-vect-cost-model" } */
+/* { dg-require-effective-target avx2 } */
+
+#define CHECK_H "avx2-check.h"
+#define TEST avx2_test
+
+#include "../../gcc.dg/vect/pr59591-2.c"
+
+#include CHECK_H
+
+static void
+TEST (void)
+{
+  bar ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59625.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59625.c
new file mode 100644
index 000000000..8e1a7794b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59625.c
@@ -0,0 +1,36 @@
+/* PR target/59625 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=atom" } */
+
+int
+foo (void)
+{
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  asm goto ("" : : : : lab);
+  return 0;
+lab:
+  return 1;
+}
+
+/* Verify we don't consider asm goto as a jump for four jumps limit
+   optimization.  asm goto doesn't have to contain a jump at all,
+   the branching to labels can happen through different means.  */
+/* { dg-final { scan-assembler-not "(p2align\[^\n\r\]*\[\n\r]*\[^\n\r\]*){8}p2align" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59644.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59644.c
new file mode 100644
index 000000000..96006b3e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59644.c
@@ -0,0 +1,42 @@
+/* PR target/59644 */
+/* { dg-do run { target lp64 } } */
+/* { dg-options "-O2 -ffreestanding -mno-sse -mpreferred-stack-boundary=3 -maccumulate-outgoing-args -mno-red-zone" } */
+
+/* This test uses __builtin_trap () instead of e.g. abort,
+   because due to -mpreferred-stack-boundary=3 it should not call
+   any library function from within main ().  */
+
+#include <stdarg.h>
+
+__attribute__((noinline, noclone))
+int
+bar (int x, int y, int z, int w, const char *fmt, va_list ap)
+{
+  if (x != 1 || y != 2 || z != 3 || w != 4)
+    __builtin_trap ();
+  if (fmt[0] != 'f' || fmt[1] != 'o' || fmt[2] != 'o' || fmt[3])
+    __builtin_trap ();
+  if (va_arg (ap, int) != 5 || va_arg (ap, int) != 6
+      || va_arg (ap, long long) != 7LL)
+    __builtin_trap ();
+  return 9;
+}
+
+__attribute__((noinline, noclone, optimize ("Os")))
+int
+foo (const char *fmt, ...)
+{
+  va_list ap;
+  va_start (ap, fmt);
+  int r = bar (1, 2, 3, 4, fmt, ap);
+  va_end (ap);
+  return r;
+}
+
+int
+main ()
+{
+  if (foo ("foo", 5, 6, 7LL) != 9)
+    __builtin_trap ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59789.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59789.c
new file mode 100644
index 000000000..b1440254b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59789.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O -march=i686" } */
+
+#pragma GCC push_options
+#pragma GCC target("sse2")
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
+extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_set_epi32 (int __q3, int __q2, int __q1, int __q0) /* { dg-error "target specific option mismatch" } */
+{
+  return __extension__ (__m128i)(__v4si){ __q0, __q1, __q2, __q3 };
+}
+#pragma GCC pop_options
+
+
+__m128i
+f1(void)
+{ /* { dg-message "warning: SSE vector return without SSE enabled changes the ABI" } */
+  return _mm_set_epi32 (0, 0, 0, 0); /* { dg-error "called from here" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-1.c
new file mode 100644
index 000000000..46bff0181
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-1.c
@@ -0,0 +1,15 @@
+/* PR target/59794 */
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O2 -mno-mmx" } */
+/* { dg-skip-if "no MMX vector" { *-*-mingw* } } */
+
+typedef int __v2si __attribute__ ((__vector_size__ (8)));
+
+extern __v2si x;
+
+extern void bar (__v2si);
+void
+foo (void)
+{
+  bar (x); /* { dg-message "warning: MMX vector argument without MMX enabled changes the ABI" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-2.c
new file mode 100644
index 000000000..f13998214
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-2.c
@@ -0,0 +1,15 @@
+/* PR target/59794 */
+/* { dg-prune-output "ABI for passing parameters" } */
+/* { dg-options "-O2 -mno-sse" } */
+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */
+
+typedef double __v2df __attribute__ ((__vector_size__ (16)));
+
+extern __v2df x;
+
+extern void bar (__v2df);
+void
+foo (void)
+{
+  bar (x); /* { dg-message "warning: SSE vector argument without SSE enabled changes the ABI" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-3.c
new file mode 100644
index 000000000..a65893c63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-3.c
@@ -0,0 +1,15 @@
+/* PR target/59794 */
+/* { dg-prune-output "ABI for passing parameters" } */
+/* { dg-options "-O2 -mno-avx" } */
+/* { dg-skip-if "no AVX vector" { *-*-mingw* } } */
+
+typedef int __v8si __attribute__ ((__vector_size__ (32)));
+
+extern __v8si x;
+
+extern void bar (__v8si);
+void
+foo (void)
+{
+  bar (x); /* { dg-message "warning: AVX vector argument without AVX enabled changes the ABI" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-4.c
new file mode 100644
index 000000000..5ad0b070a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-4.c
@@ -0,0 +1,14 @@
+/* PR target/59794 */
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O2 -mno-mmx" } */
+/* { dg-skip-if "no MMX vector" { *-*-mingw* } } */
+
+typedef int __v2si __attribute__ ((__vector_size__ (8)));
+
+extern __v2si x;
+
+__v2si
+foo (void)
+{ /* { dg-warning "MMX vector return without MMX enabled changes the ABI" } */
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-5.c
new file mode 100644
index 000000000..24c88be09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-5.c
@@ -0,0 +1,14 @@
+/* PR target/59794 */
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-O2 -mno-sse" } */
+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */
+
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+extern __v4si x;
+
+__v4si
+foo (void)
+{ /* { dg-warning "SSE vector return without SSE enabled changes the ABI" } */
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-6.c
new file mode 100644
index 000000000..c809f9579
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-6.c
@@ -0,0 +1,14 @@
+/* PR target/59794 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mno-sse" } */
+/* { dg-skip-if "no SSE vector" { *-*-mingw* } } */
+
+typedef int __v4si __attribute__ ((__vector_size__ (16)));
+
+extern __v4si x;
+
+__v4si
+foo (void)
+{ /* { dg-error "SSE register return with SSE disabled" } */
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-7.c
new file mode 100644
index 000000000..57fd3d276
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59794-7.c
@@ -0,0 +1,13 @@
+/* PR target/59794 */
+/* { dg-options "-O2 -mno-avx" } */
+/* { dg-skip-if "no AVX vector" { *-*-mingw* } } */
+
+typedef int __v8si __attribute__ ((__vector_size__ (32)));
+
+extern __v8si x;
+
+__v8si
+foo (void)
+{ /* { dg-warning "AVX vector return without AVX enabled changes the ABI" } */
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59839.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59839.c
new file mode 100644
index 000000000..dfb89456f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59839.c
@@ -0,0 +1,12 @@
+/* PR target/59839 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx2" } */
+
+#include <x86intrin.h>
+
+void
+test (const float *x)
+{
+  __m256i i = _mm256_set1_epi32 (1);
+  __m256 d = _mm256_i32gather_ps (x, i, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59880.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59880.c
new file mode 100644
index 000000000..5a116925f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59880.c
@@ -0,0 +1,14 @@
+/* PR target/59880 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mtune=silvermont" } */
+
+register unsigned int r13 __asm ("r13");
+unsigned long long
+foo (void)
+{
+  return r13;
+}
+
+/* Ensure we don't emit a useless zero-extension after another
+   zero-extension.  */
+/* { dg-final { scan-assembler-not "%eax, %eax" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59927.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59927.c
new file mode 100644
index 000000000..693c76595
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59927.c
@@ -0,0 +1,17 @@
+/* PR target/59927 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -g" } */
+
+extern void baz (int) __attribute__ ((__ms_abi__));
+
+void
+foo (void (__attribute__ ((ms_abi)) *fn) (int))
+{
+  fn (0);
+}
+
+void
+bar (void)
+{
+  baz (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59929.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59929.c
new file mode 100644
index 000000000..4591dc4d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr59929.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O0 -mno-accumulate-outgoing-args" } */
+/* { dg-options "-O0 -mno-accumulate-outgoing-args -mx32 -maddress-mode=short" { target x32 } } */
+
+void
+__attribute__ ((noinline))
+test (float x1, float x2, float x3, float x4, float x5, float x6,
+      float x7, float x8, float x9, float x10, float x11, float x12,
+      float x13, float x14, float x15, float x16)
+{
+  if (x1 != 91
+      || x2 != 92
+      || x3 != 93
+      || x4 != 94
+      || x5 != 95
+      || x6 != 96
+      || x7 != 97
+      || x8 != 98
+      || x9 != 99
+      || x10 != 100
+      || x11 != 101
+      || x12 != 102
+      || x13 != 103
+      || x14 != 104
+      || x15 != 105
+      || x16 != 106)
+    __builtin_abort ();
+}
+
+float x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13,
+      x14, x15, x16;
+
+int
+main ()
+{
+  x1 = 91;
+  x2 = 92;
+  x3 = 93;
+  x4 = 94;
+  x5 = 95;
+  x6 = 96;
+  x7 = 97;
+  x8 = 98;
+  x9 = 99;
+  x10 = 100;
+  x11 = 101;
+  x12 = 102;
+  x13 = 103;
+  x14 = 104;
+  x15 = 105;
+  x16 = 106;
+  test (x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13,
+	x14, x15, x16);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60077-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60077-1.c
new file mode 100644
index 000000000..f20ca0a3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60077-1.c
@@ -0,0 +1,18 @@
+/* Test that we generate aligned load when memory is aligned.  */
+/* { dg-do compile } */
+/* { dg-options "-O -mavx -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movups" } } */
+/* { dg-final { scan-assembler "movaps" } } */
+
+typedef float v8sf __attribute__ ((__vector_size__ (32)));
+
+extern void foo (v8sf, v8sf, v8sf, v8sf, v8sf, v8sf, v8sf, v8sf, v8sf);
+
+int
+test (void)
+{
+  v8sf x = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0 };
+
+  foo (x, x, x, x, x, x, x, x, x);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60077-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60077-2.c
new file mode 100644
index 000000000..bbf846f68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60077-2.c
@@ -0,0 +1,18 @@
+/* Test that we generate aligned load when memory is aligned.  */
+/* { dg-do compile } */
+/* { dg-options "-O -mavx -mtune=generic" } */
+/* { dg-final { scan-assembler-not "movups" } } */
+/* { dg-final { scan-assembler "movaps" } } */
+
+typedef float v8sf __attribute__ ((__vector_size__ (32)));
+
+extern void foo (int, int, int, int, int, int, int, v8sf, v8sf, v8sf, v8sf, v8sf, v8sf, v8sf, v8sf, v8sf);
+
+int
+test (void)
+{
+  v8sf x = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0 };
+
+  foo (1, 2, 3, 4, 5, 6, 7, x, x, x, x, x, x, x, x, x);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60205-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60205-1.c
new file mode 100644
index 000000000..259959a8e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60205-1.c
@@ -0,0 +1,15 @@
+/* PR target/60205 */
+/* { dg-prune-output "ABI for passing parameters" } */
+/* { dg-options "-O2 -mno-avx512f" } */
+/* { dg-skip-if "no AVX512F vector" { *-*-mingw* } } */
+
+typedef int __v16si __attribute__ ((__vector_size__ (64)));
+
+extern __v16si x;
+
+extern void bar (__v16si);
+void
+foo (void)
+{
+  bar (x); /* { dg-message "warning: AVX512F vector argument without AVX512F enabled changes the ABI" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60205-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60205-2.c
new file mode 100644
index 000000000..8a6558793
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60205-2.c
@@ -0,0 +1,13 @@
+/* PR target/60205 */
+/* { dg-options "-O2 -mno-avx512f" } */
+/* { dg-skip-if "no AVX512F vector" { *-*-mingw* } } */
+
+typedef int __v16si __attribute__ ((__vector_size__ (64)));
+
+extern __v16si x;
+
+__v16si
+foo (void)
+{ /* { dg-warning "AVX512F vector return without AVX512F enabled changes the ABI" } */
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60508.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60508.c
new file mode 100644
index 000000000..78dfb7815
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60508.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O -w" } */
+int a = 1, g, h = 1, d, e, *f;
+char b;
+static int c[] = { 0, 0 };
+void fn2 (void);
+
+void
+fn1 (short x, int l)
+{
+lab:
+  {
+    int k, m[0];
+    long j = h ? 0 : 0 / 0;
+    unsigned char n = j;
+    unsigned char i = x >= 0 ? n : n >> x;
+    g = i;
+    for (;;)
+      {
+        if (a)
+          goto lab;
+        while (d)
+          {
+            e = b = c[l];
+            fn2 ();
+          }
+        int o = m[0];
+        f = &k;
+      }
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60516.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60516.c
new file mode 100644
index 000000000..575c8b61d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr60516.c
@@ -0,0 +1,20 @@
+/* PR target/60516 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct S { char c[65536]; };
+
+__attribute__((ms_abi, thiscall)) void
+foo (void *x, struct S y)
+{
+}
+
+__attribute__((ms_abi, fastcall)) void
+bar (void *x, void *y, struct S z)
+{
+}
+
+__attribute__((ms_abi, stdcall)) void
+baz (struct S x)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/pr9771-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr9771-1.c
new file mode 100644
index 000000000..9fa21ff0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/pr9771-1.c
@@ -0,0 +1,63 @@
+/* PR rtl-optimization/9771 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -fomit-frame-pointer -ffixed-ebp" } */
+
+extern void abort(void);
+extern void exit(int);
+
+register long *B asm ("ebp");
+
+long x = 10;
+long y = 20;
+
+void bar(void)
+{
+  B = &y;
+}
+
+void foo()
+{
+  long *adr = B;
+  long save = *adr;
+
+  *adr = 123;
+
+  bar();
+
+  *adr = save;
+}
+
+/* This must not be inlined because main() requires the frame pointer
+   for stack alignment.  */
+void test(void) __attribute__((noinline));
+void test(void)
+{
+  B = &x;
+
+  foo();
+
+  if (x != 10 || y != 20)
+    abort();
+
+  /* We can't return, as our caller may assume %ebp is preserved!  */
+  /* We could save/restore it (like foo), but its easier to exit.  */
+  exit(0);
+}
+
+/* main usually performs dynamic realignment of the stack in case
+   _start would fail to properly align the stack, but for dynamic
+   stack realignment we need frame pointer which is incompatible
+   with -ffixed-ebp and the global register var.  So, cheat here
+   and hide from the compiler that main is really main.  */
+#define ASMNAME(cname)  ASMNAME2 (__USER_LABEL_PREFIX__, cname)
+#define ASMNAME2(prefix, cname) STRING (prefix) cname
+#define STRING(x)    #x
+int real_main() __asm (ASMNAME ("main"));
+
+int real_main()
+{
+  test();
+  return 0;
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/prefetchw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/prefetchw-1.c
new file mode 100644
index 000000000..d0babe4d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/prefetchw-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mprfchw -O2" } */
+/* { dg-final { scan-assembler "\[ \\t\]+prefetchw\[ \\t\]+" } } */
+
+#include <x86intrin.h>
+
+void *p;
+
+void extern
+prefetchw__test (void)
+{
+    _m_prefetchw (p);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/prefetchwt1-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/prefetchwt1-1.c
new file mode 100644
index 000000000..1b88516ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/prefetchwt1-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mprefetchwt1 -O2" } */
+/* { dg-final { scan-assembler "\[ \\t\]+prefetchwt1\[ \\t\]+" } } */
+
+#include <x86intrin.h>
+
+void *p;
+
+void extern
+prefetchw__test (void)
+{
+    _mm_prefetch (p, _MM_HINT_ET1);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/quad-sse.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/quad-sse.c
new file mode 100644
index 000000000..4b6fe7925
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/quad-sse.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+__float128 x, y;
+
+__float128 test_1(void)
+{
+  return -x;
+}
+
+__float128 test_2(void)
+{
+  return __builtin_fabsq (x);
+}
+
+__float128 test_3(void)
+{
+  return __builtin_copysignq (x, y);
+}
+
+/* { dg-final { scan-assembler-not "call.*(neg|fabs|copysign)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdfsbase-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdfsbase-1.c
new file mode 100644
index 000000000..2ed33cd47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdfsbase-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfsgsbase" } */
+/* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)eax" } } */
+
+#include <immintrin.h>
+
+unsigned int
+read_fs_base32 (void)
+{
+  return _readfsbase_u32 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdfsbase-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdfsbase-2.c
new file mode 100644
index 000000000..f319cea57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdfsbase-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfsgsbase" } */
+/* { dg-final { scan-assembler "rdfsbase\[ \t]+(%|)rax" } } */
+
+#include <immintrin.h>
+
+unsigned long long
+read_fs_base64 (void)
+{
+  return _readfsbase_u64 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdgsbase-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdgsbase-1.c
new file mode 100644
index 000000000..cb2a3d581
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdgsbase-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfsgsbase" } */
+/* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)eax" } } */
+
+#include <immintrin.h>
+
+unsigned int
+read_gs_base32 (void)
+{
+  return _readgsbase_u32 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdgsbase-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdgsbase-2.c
new file mode 100644
index 000000000..d514cd961
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdgsbase-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfsgsbase" } */
+/* { dg-final { scan-assembler "rdgsbase\[ \t]+(%|)rax" } } */
+
+#include <immintrin.h>
+
+unsigned long long
+read_gs_base64 (void)
+{
+  return _readgsbase_u64 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-1.c
new file mode 100644
index 000000000..beec9f1b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mrdrnd -dp" } */
+/* { dg-final { scan-assembler-times "rdrandhi_1" 1 } } */
+/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
+
+#include <immintrin.h>
+
+int
+foo (unsigned short *x)
+{
+  return _rdrand16_step (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-2.c
new file mode 100644
index 000000000..ea8e90649
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mrdrnd -dp" } */
+/* { dg-final { scan-assembler-times "rdrandsi_1" 1 } } */
+/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
+
+#include <immintrin.h>
+
+int
+foo (unsigned int *x)
+{
+  return _rdrand32_step (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-3.c
new file mode 100644
index 000000000..de0e730ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdrand-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mrdrnd -dp" } */
+/* { dg-final { scan-assembler-times "rdranddi_1" 1 } } */
+/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
+
+#include <immintrin.h>
+
+int
+foo (unsigned long long *x)
+{
+  return _rdrand64_step (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed16-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed16-1.c
new file mode 100644
index 000000000..fe637f1ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed16-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mrdseed -O2" } */
+/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */
+
+#include <x86intrin.h>
+
+void extern
+rdseed_test (unsigned short *p)
+{
+    volatile int r;
+    r = _rdseed16_step (p);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed32-1.c
new file mode 100644
index 000000000..646dff26d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed32-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mrdseed -O2" } */
+/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */
+
+#include <x86intrin.h>
+
+void extern
+rdseed_test (unsigned int *p)
+{
+    volatile int r;
+    r = _rdseed32_step (p);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed64-1.c
new file mode 100644
index 000000000..bdacd7ad6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rdseed64-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mrdseed -O2" } */
+/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */
+
+#include <x86intrin.h>
+
+void extern
+rdseed_test (unsigned long long *p)
+{
+    volatile int r;
+    r = _rdseed64_step (p);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/readeflags-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/readeflags-1.c
new file mode 100644
index 000000000..6b2fa7e8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/readeflags-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O0" } */
+
+#include <x86intrin.h>
+
+#ifdef __x86_64__
+#define EFLAGS_TYPE unsigned long long int
+#else
+#define EFLAGS_TYPE unsigned int
+#endif
+
+static EFLAGS_TYPE
+readeflags_test (unsigned int a, unsigned int b)
+{
+  unsigned x = (a == b);
+  return __readeflags ();
+}
+
+int
+main ()
+{
+  EFLAGS_TYPE flags;
+
+  flags = readeflags_test (100, 100);
+
+  if ((flags & 1) != 0)  /* Read CF */
+    abort ();
+
+  flags = readeflags_test (100, 101);
+
+  if ((flags & 1) == 0)  /* Read CF */
+    abort ();
+
+#ifdef DEBUG
+    printf ("PASSED\n");
+#endif
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-divf.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-divf.c
new file mode 100644
index 000000000..b4447d33a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-divf.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */
+
+float t1(float a, float b)
+{
+  return a / b;
+}
+
+/* { dg-final { scan-assembler "rcpss" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-sqrtf.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-sqrtf.c
new file mode 100644
index 000000000..859d2180a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-sqrtf.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */
+
+extern float sqrtf (float);
+
+float t1(float a, float b)
+{
+  return a/sqrtf(b);
+}
+
+float t2(float a, float b)
+{
+  return sqrtf(a/b);
+}
+
+float t3(float a)
+{
+  return sqrtf(a);
+}
+
+/* { dg-final { scan-assembler-times "rsqrtss" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c
new file mode 100644
index 000000000..8aeec20d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-divf-avx.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mtune=generic -mfpmath=sse -mrecip" } */
+
+float a[32];
+float b[32];
+float r[32];
+
+void t1(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++)
+   r[i] = a[i] / b[i];
+}
+
+/* { dg-final { scan-assembler "vrcpps\[ \\t\]+\[^\n\]*%ymm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-divf.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-divf.c
new file mode 100644
index 000000000..fa126e45f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-divf.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip -fno-common" } */
+
+float a[4];
+float b[4];
+float r[4];
+
+void t1(void)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+   r[i] = a[i] / b[i];
+}
+
+/* { dg-final { scan-assembler "rcpps" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c
new file mode 100644
index 000000000..9cf3cc81b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf-avx.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mtune=generic -mfpmath=sse -mrecip" } */
+
+float a[32];
+float b[32];
+float r[32];
+
+extern float sqrtf (float);
+
+void t1(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++)
+   r[i] = a[i] / sqrtf (b[i]);
+}
+
+void t2(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++)
+   r[i] = sqrtf (a[i] / b[i]);
+}
+
+void t3(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++)
+   r[i] = sqrtf (a[i]);
+}
+
+/* { dg-final { scan-assembler-times "vrsqrtps\[ \\t\]+\[^\n\]*%ymm" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c
new file mode 100644
index 000000000..6c0d49b22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/recip-vec-sqrtf.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip -fno-common" } */
+
+float a[4];
+float b[4];
+float r[4];
+
+extern float sqrtf (float);
+
+void t1(void)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+   r[i] = a[i] / sqrtf (b[i]);
+}
+
+void t2(void)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+   r[i] = sqrtf (a[i] / b[i]);
+}
+
+void t3(void)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+   r[i] = sqrtf (a[i]);
+}
+
+/* { dg-final { scan-assembler-times "rsqrtps" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/regparm-stdcall.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/regparm-stdcall.c
new file mode 100644
index 000000000..fbb3be549
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/regparm-stdcall.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+/* { dg-options -mpreferred-stack-boundary=4 } */
+/* { dg-require-effective-target ia32 } */
+
+extern void abort(void);
+
+void __attribute__((regparm(2), stdcall)) foo(int i, int j, float x)
+{
+  static int last_align = -1;
+  int dummy, align = (int)&dummy & 15;
+  if (last_align < 0)
+    last_align = align;
+  else if (align != last_align)
+    abort ();
+}
+
+int main()
+{
+	foo(0,0,0.0);
+	foo(0,0,0.0);
+	return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/regparm.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/regparm.c
new file mode 100644
index 000000000..4cfd11020
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/regparm.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-W -Wall" } */
+
+/* Verify that GCC correctly detects non-matching regparm attributes.  */
+int __attribute__((regparm(3))) f (void);  /* { dg-message "note: previous" } */
+
+int __attribute__((regparm(2))) f (void) { /* { dg-error "conflicting" } */
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/reload-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/reload-1.c
new file mode 100644
index 000000000..9c6cd3222
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/reload-1.c
@@ -0,0 +1,115 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O3 -msse2 -fdump-rtl-csa" } */
+/* { dg-skip-if "no stdint" { vxworks_kernel } } */
+
+#include <emmintrin.h>
+#include <stdint.h>
+
+typedef __SIZE_TYPE__ size_t;
+typedef float vFloat __attribute__ ((__vector_size__ (16)));
+typedef double vDouble __attribute__ ((__vector_size__ (16)));
+typedef struct buf
+{
+  void *data;
+  unsigned long h;
+  unsigned long  w;
+  size_t bytes;
+} buf;
+
+typedef struct job
+{
+  struct Job *next;
+  void * info;
+  long (*func)(struct Job *job);
+  long error;
+} job;
+
+typedef struct fj
+{
+    job hd;
+    buf src;
+    buf dest;
+    float g;
+    unsigned int flags;
+} fj;
+
+static const double r[256], t[256];
+
+long bar (const buf *src, const buf *dest, float g, unsigned int flags)
+{
+  float *d0 = (float*) src->data;
+  float *d1 = (float*) dest->data;
+  uintptr_t w = dest->w;
+  uintptr_t idx;
+  vFloat p0;
+  static const vFloat m0;
+  static const vDouble p[3], m, b;
+  float *sr = d0;
+  float *dr = d1;
+  for( idx = 0; idx + 8 <= w; idx += 8 )
+  {
+    vFloat f0 = _mm_loadu_ps (sr);
+    vFloat f1 = _mm_loadu_ps (sr + 4);
+    sr += 8;
+    vFloat fa0 = _mm_andnot_ps (m0, f0);
+    vFloat fa1 = _mm_andnot_ps (m0, f1);
+    vDouble v0 = _mm_cvtps_pd (fa0);
+    vDouble v1 = _mm_cvtps_pd (_mm_movehl_ps (fa0, fa0));
+    vDouble v2 = _mm_cvtps_pd (fa1);
+    vDouble v3 = _mm_cvtps_pd (_mm_movehl_ps (fa1, fa1));
+    vDouble  vi0, vi1, vi2, vi3;
+    __m128i b0, b1, b2, b3;
+    b0 = _mm_packs_epi32 (_mm_packs_epi32 (b0, b1), _mm_packs_epi32 (b2, b3));
+    b1 = _mm_srli_epi64 (b0, 32);
+    unsigned int i0 = _mm_cvtsi128_si32 (b0); 
+    unsigned int i2 = _mm_cvtsi128_si32 (b1);
+    v0 -= _mm_loadh_pd (_mm_load_sd (r + (i0 & 0xff)), r + (i0 >> 16));
+    v1 -= _mm_loadh_pd (_mm_load_sd (r + (i2 & 0xff)), r + (i2 >> 16));
+    b0 = _mm_unpackhi_epi64 (b0, b0);
+    b1 = _mm_unpackhi_epi64 (b1, b1);
+    unsigned int i4 = _mm_cvtsi128_si32 (b0);
+    unsigned int i6 = _mm_cvtsi128_si32 (b1);
+    v2 -= _mm_loadh_pd (_mm_load_sd (r + (i4 & 0xff)), r + (i4 >> 16));
+    v3 -= _mm_loadh_pd (_mm_load_sd (r + (i6 & 0xff)), r + (i6 >> 16));
+    v0 = p[0] + (p[1] + p[2] * v0) * v0;
+    v1 = p[0] + (p[1] + p[2] * v1) * v1;
+    v2 = p[0] + (p[1] + p[2] * v2) * v2;
+    v3 = p[0] + (p[1] + p[2] * v3) * v3;
+    vi0 = (vDouble) _mm_slli_epi64 ((__m128i)((vi0 + b) + m), 52);
+    vi1 = (vDouble) _mm_slli_epi64 ((__m128i)((vi1 + b) + m), 52);
+    vi2 = (vDouble) _mm_slli_epi64 ((__m128i)((vi2 + b) + m), 52);
+    vi3 = (vDouble) _mm_slli_epi64 ((__m128i)((vi3 + b) + m), 52);
+    vi0 *= _mm_loadh_pd (_mm_load_sd (t + (i0 & 0xff)), t + (i0 >> 16));
+    vi1 *= _mm_loadh_pd (_mm_load_sd (t + (i2 & 0xff)), t + (i2 >> 16));
+    vi2 *= _mm_loadh_pd (_mm_load_sd (t + (i4 & 0xff)), t + (i4 >> 16));
+    vi3 *= _mm_loadh_pd (_mm_load_sd (t + (i6 & 0xff)), t + (i6 >> 16));
+    v0 *= vi0;
+    v1 *= vi1;
+    v2 *= vi2;
+    v3 *= vi3;
+    vFloat r0 = _mm_movelh_ps (_mm_cvtpd_ps( v0 ), _mm_cvtpd_ps (v1));
+    vFloat r1 = _mm_movelh_ps (_mm_cvtpd_ps( v2 ), _mm_cvtpd_ps (v3));
+    vFloat z0 = _mm_cmpeq_ps (f0, _mm_setzero_ps());
+    vFloat z1 = _mm_cmpeq_ps (f1, _mm_setzero_ps());
+    r0 = _mm_andnot_ps (z0, r0);
+    r1 = _mm_andnot_ps (z1, r1);
+    z0 = _mm_and_ps (z0, p0);
+    z1 = _mm_and_ps (z1, p0);
+    r0 = _mm_or_ps (r0, z0);
+    r1 = _mm_or_ps (r1, z1);
+    _mm_storeu_ps (dr, r0);
+    _mm_storeu_ps (dr + 4, r1);
+    dr += 8;
+  }
+  return 0;
+}
+
+long foo (job *j )
+{
+  fj *jd = (fj*) j;
+  return bar (&jd->src, &jd->dest, jd->g, jd->flags);
+}
+
+/* { dg-final { scan-rtl-dump-not "deleted 1 dead insns" "csa" } } */
+/* { dg-final { cleanup-rtl-dump "csa" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/retarg.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/retarg.c
new file mode 100644
index 000000000..a69b60fea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/retarg.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2" } */
+
+#include <string.h>
+
+void *p (void *x, void *y, int z)
+{
+  memcpy (x, y, z);
+  return x;
+}
+
+/* { dg-final { scan-assembler-not "%\[re\]di" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-1.c
new file mode 100644
index 000000000..399cbd96c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-1.c
@@ -0,0 +1,16 @@
+/* Verify that rolb instruction is emitted on IA-32/x86-64.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void foo (unsigned char *);
+
+int
+main (void)
+{
+  unsigned char c = 0;
+  foo (&c);
+  c = c >> 1 | c << 7;
+  return c;
+}
+
+/* { dg-final { scan-assembler "ro\[lr]b" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-2.c
new file mode 100644
index 000000000..71fd7edbd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2" } */
+
+typedef unsigned int UTItype __attribute__ ((mode (TI)));
+
+void foo (UTItype *);
+
+UTItype
+test (void)
+{
+  UTItype c = 0;
+  foo (&c);
+  c = c >> 5 | c << 123;
+  return c;
+}
+/* { dg-final { scan-assembler-times "shrdq" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-3.c
new file mode 100644
index 000000000..7f255732b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-3.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2 -fdump-tree-vect-details" } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+
+unsigned int a[1024] __attribute__((aligned (32)));
+
+__attribute__((noinline, noclone)) void
+foo (void)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    {
+      int j = i & 31;
+      a[i] = (a[i] << j) | (a[i] >> ((-j) & 31));
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-3a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-3a.c
new file mode 100644
index 000000000..0685efbd0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-3a.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx2 } */
+/* { dg-options "-O3 -mavx2" } */
+
+#include "avx2-check.h"
+
+#include "rotate-3.c"
+
+static void
+__attribute__((noinline))
+avx2_test (void)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    a[i] = i * 1073741789U;
+  foo ();
+  for (i = 0; i < 1024; i++)
+    {
+      int j = i & 31;
+      unsigned int x = i * 1073741789U;
+      if (a[i] != ((x << j) | (x >> ((-j) & 31))))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-4.c
new file mode 100644
index 000000000..7faa052cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-4.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -mavx -fdump-tree-vect-details" } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+
+unsigned int a[1024] __attribute__((aligned (32)));
+
+__attribute__((noinline, noclone)) void
+foo (int j)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    a[i] = (a[i] << j) | (a[i] >> ((-j) & 31));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-4a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-4a.c
new file mode 100644
index 000000000..3da440fb7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-4a.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -mavx" } */
+
+#include "avx-check.h"
+
+#include "rotate-4.c"
+
+static void
+__attribute__((noinline))
+avx_test (void)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    a[i] = i * 1073741789U;
+  foo (3);
+  for (i = 0; i < 1024; i++)
+    {
+      unsigned int x = i * 1073741789U;
+      if (a[i] != ((x << 3) | (x >> ((-3) & 31))))
+	abort ();
+    }
+  foo (0);
+  for (i = 0; i < 1024; i++)
+    {
+      unsigned int x = i * 1073741789U;
+      if (a[i] != ((x << 3) | (x >> ((-3) & 31))))
+	abort ();
+    }
+  foo (29);
+  for (i = 0; i < 1024; i++)
+    if (a[i] != i * 1073741789U)
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-5.c
new file mode 100644
index 000000000..7d5888db2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-5.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -mavx -fdump-tree-vect-details" } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
+
+unsigned int a[1024] __attribute__((aligned (32)));
+
+__attribute__((noinline, noclone)) void
+foo (void)
+{
+  int i, j = 3;
+  for (i = 0; i < 1024; i++)
+    a[i] = (a[i] << j) | (a[i] >> ((-j) & 31));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-5a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-5a.c
new file mode 100644
index 000000000..581365401
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rotate-5a.c
@@ -0,0 +1,23 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-O3 -mavx" } */
+
+#include "avx-check.h"
+
+#include "rotate-5.c"
+
+static void
+__attribute__((noinline))
+avx_test (void)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    a[i] = i * 1073741789U;
+  foo ();
+  for (i = 0; i < 1024; i++)
+    {
+      unsigned int x = i * 1073741789U;
+      if (a[i] != ((x << 3) | (x >> ((-3) & 31))))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-check.h
new file mode 100644
index 000000000..593b40391
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-check.h
@@ -0,0 +1,32 @@
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void rtm_test (void);
+
+static void __attribute__ ((noinline)) do_test (void)
+{
+  rtm_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (__get_cpuid_max (0, NULL) >= 7)
+    {
+      __cpuid_count (7, 0, eax, ebx, ecx, edx);
+      if (ebx & bit_RTM)
+	{
+	  do_test ();
+#ifdef DEBUG
+	  printf ("PASSED\n");
+#endif
+	  return 0;
+	}
+    }
+#ifdef DEBUG
+  printf ("SKIPPED\n");
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c
new file mode 100644
index 000000000..808095d27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xabort-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtm" } */
+/* { dg-final { scan-assembler "\txabort" } } */
+
+#include <immintrin.h>
+
+void
+rtm_test (void)
+{
+  _xabort (13);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c
new file mode 100644
index 000000000..caced5f5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xbegin-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtm" } */
+/* { dg-final { scan-assembler "\txbegin" } } */
+
+#include <immintrin.h>
+
+unsigned int
+rtm_test (void)
+{
+  return _xbegin ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xend-1.c
new file mode 100644
index 000000000..2bd8a0a9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xend-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtm" } */
+/* { dg-final { scan-assembler "\txend" } } */
+
+#include <immintrin.h>
+
+void
+rtm_test (void)
+{
+  _xend ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c
new file mode 100644
index 000000000..cdf346fcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/rtm-xtest-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mrtm -dp" } */
+/* { dg-final { scan-assembler "\txtest" } } */
+
+#include <immintrin.h>
+
+int
+rtm_xtest (void)
+{
+  return _xtest ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-1.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-1.h
new file mode 100644
index 000000000..79556e874
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-1.h
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include CHECK_H
+
+static __m128i
+__attribute__((noinline))
+foo (char *v)
+{
+  return _mm_set_epi8 (v[15], v[14], v[13], v[12],
+		       v[11], v[10], v[9], v[8],
+		       v[7], v[6], v[5], v[4],
+		       v[3], v[2], v[1], v[0]);
+}
+
+static void
+TEST (void)
+{
+  char v[16] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68
+    };
+  union128i_b u;
+
+  u.x = foo (v);
+  if (check_union128i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-2.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-2.h
new file mode 100644
index 000000000..9768806c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-2.h
@@ -0,0 +1,30 @@
+#include CHECK_H
+
+static __m128i
+__attribute__((noinline))
+foo (char x1, char x2, char x3, char x4,
+     char x5, char x6, char x7, char x8,
+     char x9, char x10, char x11, char x12,
+     char x13, char x14, char x15, char x16)
+{
+  return _mm_set_epi8 (x1, x2, x3, x4, x5, x6, x7, x8,
+		       x9, x10, x11, x12, x13, x14, x15, x16);
+}
+
+static void
+TEST (void)
+{
+  char v[16] =
+    { 
+      -3, 60, 48, 104, -90, 37, -48, 78,
+      4, 33, 81, 4, -89, 17, 8, 68
+    };
+  union128i_b u;
+
+  u.x = foo (v[15], v[14], v[13], v[12],
+	     v[11], v[10], v[9], v[8],
+	     v[7], v[6], v[5], v[4],
+	     v[3], v[2], v[1], v[0]);
+  if (check_union128i_b (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-3.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-3.h
new file mode 100644
index 000000000..faf3cd344
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v16qi-3.h
@@ -0,0 +1,63 @@
+#include CHECK_H
+
+static __m128i
+__attribute__((noinline))
+foo (char x, int i)
+{
+  switch (i)
+    {
+    case 15:
+      return _mm_set_epi8 (x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 14:
+      return _mm_set_epi8 (1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 13:
+      return _mm_set_epi8 (1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 12:
+      return _mm_set_epi8 (1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 11:
+      return _mm_set_epi8 (1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 10:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 9:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 8:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1, 1);
+    case 7:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1, 1);
+    case 6:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1, 1);
+    case 5:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1, 1);
+    case 4:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1, 1);
+    case 3:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1, 1);
+    case 2:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1, 1);
+    case 1:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x, 1);
+    case 0:
+      return _mm_set_epi8 (1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, x);
+    default:
+      abort ();
+    }
+}
+
+static void
+TEST (void)
+{
+  char e = 0x13;
+  char v[16];
+  union128i_b u;
+  int i, j;
+
+  for (i = 0; i < ARRAY_SIZE (v); i++)
+    {
+      for (j = 0; j < ARRAY_SIZE (v); j++)
+	v[j] = 1;
+      v[i] = e;
+      u.x = foo (e, i);
+      if (check_union128i_b (u, v))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v8hi-1.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v8hi-1.h
new file mode 100644
index 000000000..87762b82e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v8hi-1.h
@@ -0,0 +1,19 @@
+#include CHECK_H
+
+static __m128i
+__attribute__((noinline))
+foo (short *v)
+{
+  return _mm_set_epi16 (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+}
+
+static void
+TEST (void)
+{
+  short v[8] = { -3, 6000, 48, 104, -90, 34567, -1248, 34678 };
+  union128i_w u;
+
+  u.x = foo (v);
+  if (check_union128i_w (u, v))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v8hi-2.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v8hi-2.h
new file mode 100644
index 000000000..835e7b4d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/set-v8hi-2.h
@@ -0,0 +1,21 @@
+#include CHECK_H
+
+__m128i
+__attribute__((noinline))
+foo (short x1, short x2, short x3, short x4,
+     short x5, short x6, short x7, short x8)
+{
+  return _mm_set_epi16 (x1, x2, x3, x4, x5, x6, x7, x8);
+}
+
+static void
+TEST (void)
+{
+  short v[8] = { -3, 2, 1, 9, 23, -173, -13, 69 };
+  union128i_w u;
+
+  u.x = foo (v[7], v[6], v[5], v[4], v[3], v[2], v[1], v[0]);
+
+  if (check_union128i_w (u, v))
+     abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha-check.h
new file mode 100644
index 000000000..e0a18076e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha-check.h
@@ -0,0 +1,37 @@
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void sha_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  sha_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (__get_cpuid_max (0, NULL) >= 7)
+    {
+      __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+      /* Run SHA test only if host has SHA support.  */
+      if (ebx & bit_SHA)
+	{
+	  do_test ();
+#ifdef DEBUG
+	  printf ("PASSED\n");
+#endif
+	  return 0;
+	}
+    }
+
+#ifdef DEBUG
+  printf ("SKIPPED\n");
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg1-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg1-1.c
new file mode 100644
index 000000000..808f3617f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg1-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-final { scan-assembler "sha1msg1\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x;
+
+void extern
+sha_test (void)
+{
+  x = _mm_sha1msg1_epu32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg1-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg1-2.c
new file mode 100644
index 000000000..35a60571f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg1-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-require-effective-target sha } */
+
+#include "sha-check.h"
+#include "m128-check.h"
+#include <immintrin.h>
+
+static void
+compute_sha1msg1 (int *s1, int *s2, int *r)
+{
+  int w0, w1, w2, w3, w4, w5;
+
+  w0 = s1[3];
+  w1 = s1[2];
+  w2 = s1[1];
+  w3 = s1[0];
+  w4 = s2[3];
+  w5 = s2[2];
+
+  r[0] = w5 ^ w3;
+  r[1] = w4 ^ w2;
+  r[2] = w3 ^ w1;
+  r[3] = w2 ^ w0;
+}
+
+static void
+sha_test (void)
+{
+  union128i_d s1, s2, res;
+  int res_ref[4];
+
+  s1.x = _mm_set_epi32 (111, 222, 333, 444);
+  s2.x = _mm_set_epi32 (555, 666, 0, 0);
+
+  res.x = _mm_sha1msg1_epu32 (s1.x, s2.x);
+
+  compute_sha1msg1 (s1.a, s2.a, res_ref);
+
+  if (check_union128i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg2-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg2-1.c
new file mode 100644
index 000000000..9c0ffc13f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg2-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-final { scan-assembler "sha1msg2\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x;
+
+void extern
+sha_test (void)
+{
+  x = _mm_sha1msg2_epu32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg2-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg2-2.c
new file mode 100644
index 000000000..21eaf8dd9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1msg2-2.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-require-effective-target sha } */
+
+#include "sha-check.h"
+#include "m128-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static void
+compute_sha1msg2 (int *s1, int *s2, int *r)
+{
+  int w13, w14, w15, w16, w17, w18, w19;
+
+  w13 = s2[2];
+  w14 = s2[1];
+  w15 = s2[0];
+  w16 = __rold (s1[3] ^ w13, 1);
+  w17 = __rold (s1[2] ^ w14, 1);
+  w18 = __rold (s1[1] ^ w15, 1);
+  w19 = __rold (s1[0] ^ w16, 1);
+
+  r[0] = w19;
+  r[1] = w18;
+  r[2] = w17;
+  r[3] = w16;
+}
+
+static void
+sha_test (void)
+{
+  union128i_d s1, s2, res;
+  int res_ref[4];
+
+  s1.x = _mm_set_epi32 (111, 222, 333, 444);
+  s2.x = _mm_set_epi32 (555, 666, 777, 0);
+
+  res.x = _mm_sha1msg2_epu32 (s1.x, s2.x);
+
+  compute_sha1msg2 (s1.a, s2.a, res_ref);
+
+  if (check_union128i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1nexte-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1nexte-1.c
new file mode 100644
index 000000000..40edc780f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1nexte-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-final { scan-assembler "sha1nexte\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x;
+
+void extern
+sha_test (void)
+{
+  x = _mm_sha1nexte_epu32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1nexte-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1nexte-2.c
new file mode 100644
index 000000000..f0dc6cbc6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1nexte-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-require-effective-target sha } */
+
+#include "sha-check.h"
+#include "m128-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static void
+compute_sha1nexte (int *s1, int *s2, int *r)
+{
+  int tmp = __rold (s1[3], 30);
+
+  r[0] = s2[0];
+  r[1] = s2[1];
+  r[2] = s2[2];
+  r[3] = s2[3] + tmp;
+}
+
+static void
+sha_test (void)
+{
+  union128i_d s1, s2, res;
+  int res_ref[4];
+
+  s1.x = _mm_set_epi32 (111, 0, 0, 0);
+  s2.x = _mm_set_epi32 (222, 333, 444, 555);
+
+  res.x = _mm_sha1nexte_epu32 (s1.x, s2.x);
+
+  compute_sha1nexte (s1.a, s2.a, res_ref);
+
+  if (check_union128i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1rnds4-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1rnds4-1.c
new file mode 100644
index 000000000..c9da57df0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1rnds4-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-final { scan-assembler "sha1rnds4\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x;
+
+void extern
+sha_test (void)
+{
+  x = _mm_sha1rnds4_epu32 (x, x, 3);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1rnds4-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1rnds4-2.c
new file mode 100644
index 000000000..91210b1f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha1rnds4-2.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-require-effective-target sha } */
+
+#include "sha-check.h"
+#include "m128-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static int
+f0 (int b, int c, int d)
+{
+  return (b & c) ^ (~b & d);
+}
+
+static int
+f1 (int b, int c, int d)
+{
+  return b ^ c ^ d;
+}
+
+static int
+f2 (int b, int c, int d)
+{
+  return (b & c) ^ (b & d) ^ (c & d);
+}
+
+int (*f_arr[4])(int, int, int) = { f0, f1, f2, f1 };
+const int k_arr[4] = { 0x5A827999, 0x6ED9EBA1, 0x8F1BBCDC, 0xCA62C1D6 };
+
+
+static void
+compute_sha1rnds4 (int *src1, int *src2, int imm, int *res)
+{
+  int k = k_arr[imm];
+  int (*f)(int, int, int) = f_arr[imm];
+
+  int w[4] = { src2[3], src2[2], src2[1], src2[0] };
+  int a[5], b[5], c[5], d[5], e[5];
+
+  a[0] = src1[3];
+  b[0] = src1[2];
+  c[0] = src1[1];
+  d[0] = src1[0];
+  e[0] = 0;
+
+  int i;
+  for (i = 0; i <= 3; i++)
+    {
+      a[i+1] = f(b[i], c[i], d[i]) + __rold (a[i], 5) + w[i] + e[i] + k;
+      b[i+1] = a[i];
+      c[i+1] = __rold (b[i], 30);
+      d[i+1] = c[i];
+      e[i+1] = d[i];
+    }
+
+  res[0] = d[4];
+  res[1] = c[4];
+  res[2] = b[4];
+  res[3] = a[4];
+}
+
+
+static void
+sha_test (void)
+{
+  int imm;
+  union128i_d s1, s2, res;
+  int res_ref[4];
+
+  s1.x = _mm_set_epi32 (111, 222, 333, 444);
+  s2.x = _mm_set_epi32 (555, 666, 777, 888);
+
+  res.x = _mm_sha1rnds4_epu32 (s1.x, s2.x, 0);
+  compute_sha1rnds4 (s1.a, s2.a, 0, res_ref);
+  if (check_union128i_d (res, res_ref))
+    abort ();
+
+  res.x = _mm_sha1rnds4_epu32 (s1.x, s2.x, 1);
+  compute_sha1rnds4 (s1.a, s2.a, 1, res_ref);
+  if (check_union128i_d (res, res_ref))
+    abort ();
+
+  res.x = _mm_sha1rnds4_epu32 (s1.x, s2.x, 2);
+  compute_sha1rnds4 (s1.a, s2.a, 2, res_ref);
+  if (check_union128i_d (res, res_ref))
+    abort ();
+
+  res.x = _mm_sha1rnds4_epu32 (s1.x, s2.x, 3);
+  compute_sha1rnds4 (s1.a, s2.a, 3, res_ref);
+  if (check_union128i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg1-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg1-1.c
new file mode 100644
index 000000000..020874e4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg1-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-final { scan-assembler "sha256msg1\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x;
+
+void extern
+sha_test (void)
+{
+  x = _mm_sha256msg1_epu32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg1-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg1-2.c
new file mode 100644
index 000000000..2b70920b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg1-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-require-effective-target sha } */
+
+#include "sha-check.h"
+#include "m128-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static int
+s0 (int w)
+{
+  return __rord (w, 7) ^ __rord (w, 18) ^ (w >> 3);
+}
+
+static void
+compute_sha256msg1 (int *src1, int *src2, int *res)
+{
+  int w0, w1, w2, w3, w4;
+
+  w0 = src1[0];
+  w1 = src1[1];
+  w2 = src1[2];
+  w3 = src1[3];
+  w4 = src2[0];
+
+  res[0] = w0 + s0 (w1);
+  res[1] = w1 + s0 (w2);
+  res[2] = w2 + s0 (w3);
+  res[3] = w3 + s0 (w4);
+}
+
+static void
+sha_test (void)
+{
+  union128i_d s1, s2, res;
+  int res_ref[4];
+
+  s1.x = _mm_set_epi32 (111, 222, 333, 444);
+  s2.x = _mm_set_epi32 (0, 0, 0, 555);
+
+  res.x = _mm_sha256msg1_epu32 (s1.x, s2.x);
+
+  compute_sha256msg1 (s1.a, s2.a, res_ref);
+
+  if (check_union128i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg2-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg2-1.c
new file mode 100644
index 000000000..88a9a03e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg2-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-final { scan-assembler "sha256msg2\[ \\t\]+\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x;
+
+void extern
+sha_test (void)
+{
+  x = _mm_sha256msg2_epu32 (x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg2-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg2-2.c
new file mode 100644
index 000000000..ffb0c2582
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256msg2-2.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-require-effective-target sha } */
+
+#include "sha-check.h"
+#include "m128-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static int
+s1 (int w)
+{
+  return __rord (w, 17) ^ __rord (w, 19) ^ (w >> 10);
+}
+
+static void
+compute_sha256msg2 (int *src1, int *src2, int *res)
+{
+  int w14, w15, w16, w17, w18, w19;
+
+  w14 = src2[2];
+  w15 = src2[3];
+  w16 = src1[0] + s1 (w14);
+  w17 = src1[1] + s1 (w15);
+  w18 = src1[2] + s1 (w16);
+  w19 = src1[3] + s1 (w17);
+
+  res[0] = w16;
+  res[1] = w17;
+  res[2] = w18;
+  res[3] = w19;
+}
+
+static void
+sha_test (void)
+{
+  union128i_d s1, s2, res;
+  int res_ref[4];
+
+  s1.x = _mm_set_epi32 (111, 222, 333, 444);
+  s2.x = _mm_set_epi32 (555, 666, 0, 0);
+
+  res.x = _mm_sha256msg2_epu32 (s1.x, s2.x);
+
+  compute_sha256msg2 (s1.a, s2.a, res_ref);
+
+  if (check_union128i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256rnds2-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256rnds2-1.c
new file mode 100644
index 000000000..8bdf66420
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256rnds2-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-final { scan-assembler "sha256rnds2\[ \\t\]+\[^\n\]*%xmm0\[^\n\]*%xmm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x;
+
+void extern
+sha_test (void)
+{
+  x = _mm_sha256rnds2_epu32 (x, x, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256rnds2-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256rnds2-2.c
new file mode 100644
index 000000000..4e586749d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sha256rnds2-2.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha" } */
+/* { dg-require-effective-target sha } */
+
+#include "sha-check.h"
+#include "m128-check.h"
+#include <x86intrin.h>
+#include <immintrin.h>
+
+static int
+ch (int e, int f, int g)
+{
+  return (e & f) ^ (~e & g);
+}
+
+static int
+maj (int a, int b, int c)
+{
+  return (a & b) ^ (a & c) ^ (b & c);
+}
+
+static int
+s0 (int a)
+{
+  return __rord (a, 2) ^ __rord (a, 13) ^ __rord (a, 22);
+}
+
+static int
+s1 (int e)
+{
+  return __rord (e, 6) ^ __rord (e, 11) ^ __rord (e, 25);
+}
+
+static void
+compute_sha256rnds2 (int *src0, int *src1, int *src2, int *res)
+{
+  int wk[2] = { src0[0], src0[1] };
+  int a[3], b[3], c[3], d[3], e[3], f[3], g[3], h[3];
+
+  a[0] = src2[3];
+  b[0] = src2[2];
+  c[0] = src1[3];
+  d[0] = src1[2];
+  e[0] = src2[1];
+  f[0] = src2[0];
+  g[0] = src1[1];
+  h[0] = src1[0];
+
+  int i;
+  for (i = 0; i <= 1; i++)
+    {
+      a[i+1] = ch (e[i], f[i], g[i]) + s1 (e[i]) + wk[i] + h[i]
+	       + maj (a[i], b[i], c[i]) + s0 (a[i]);
+      b[i+1] = a[i];
+      c[i+1] = b[i];
+      d[i+1] = c[i];
+      e[i+1] = ch (e[i], f[i], g[i]) + s1 (e[i]) + wk[i] + h[i] + d[i];
+      f[i+1] = e[i];
+      g[i+1] = f[i];
+      h[i+1] = g[i];
+    }
+
+  res[0] = f[2];
+  res[1] = e[2];
+  res[2] = b[2];
+  res[3] = a[2];
+}
+
+static void
+sha_test (void)
+{
+  union128i_d s0, s1, s2, res;
+  int res_ref[4];
+
+  s0.x = _mm_set_epi32 (0, 0, 111, 222);
+  s1.x = _mm_set_epi32 (333, 444, 555, 666);
+  s2.x = _mm_set_epi32 (777, 888, 999, 123);
+
+  res.x = _mm_sha256rnds2_epu32 (s1.x, s2.x, s0.x);
+
+  compute_sha256rnds2 (s0.a, s1.a, s2.a, res_ref);
+
+  if (check_union128i_d (res, res_ref))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/shift_mask.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/shift_mask.c
new file mode 100644
index 000000000..29c84bd1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/shift_mask.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int test_sal (int a, int c)
+{
+  return a << (c & 0x1f);
+}
+
+int test_sar (int a, int c)
+{
+  return a >> (c & 0x1f);
+}
+
+unsigned int test_shr (unsigned int a, int c)
+{
+  return a >> (c & 0x1f);
+}
+
+unsigned int test_rol (unsigned int a, int c)
+{
+  int z = c & 0x1f;
+  return (a << z) | (a >> (32 - z));
+}
+
+unsigned int test_ror (unsigned int a, int c)
+{
+  int z = c & 0x1f;
+  return (a >> z) | (a << (32 - z));
+}
+
+/* { dg-final { scan-assembler-not "and" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/shuf-concat.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/shuf-concat.c
new file mode 100644
index 000000000..04ed4a9db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/shuf-concat.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msse2 -mfpmath=sse" } */
+
+typedef double v2df __attribute__ ((__vector_size__ (16)));
+
+v2df f(double d,double e){
+  v2df x={-d,d};
+  v2df y={-e,e};
+  return __builtin_ia32_shufpd(x,y,1);
+}
+
+/* { dg-final { scan-assembler-not "\tv?shufpd\[ \t\]" } } */
+/* { dg-final { scan-assembler-times "\tv?unpcklpd\[ \t\]" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sibcall-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sibcall-5.c
new file mode 100644
index 000000000..7cf67dbe1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sibcall-5.c
@@ -0,0 +1,44 @@
+/* Check that indirect sibcalls understand regparm.  */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2" } */
+
+extern void abort (void);
+
+int (*f)(int, int) __attribute__((regparm(2)));
+int (*g)(int, int, int) __attribute__((regparm(3)));
+
+int __attribute__((noinline))
+foo(void)
+{
+  return f(1, 2);
+}
+
+int __attribute__((noinline))
+bar(void)
+{
+  return g(1, 2, 3);
+}
+
+int __attribute__((regparm(2)))
+f1(int x, int y)
+{
+  return x*3 + y;
+}
+
+int __attribute__((regparm(3)))
+g1(int x, int y, int z)
+{
+  return x*9 + y*3 + z;
+}
+
+int main()
+{
+  f = f1;
+  g = g1;
+  if (foo() != 1*3 + 2)
+    abort ();
+  if (bar() != 1*9 + 2*3 + 3)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-1.c
new file mode 100644
index 000000000..3f31f5e2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-1.c
@@ -0,0 +1,29 @@
+/* PR optimization/8746 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O1 -mtune=i586" } */
+
+extern void abort (void);
+
+unsigned char r0;
+
+int foo(int x)
+{
+  unsigned char r = x&0xf0;
+
+  if (!(r&0x80))
+  {
+    r0 = r;
+    return 0;
+  }
+  else
+    return 1;
+}
+
+int main(void)
+{
+  if (foo(0x80) != 1)
+    abort();
+
+   return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-2.c
new file mode 100644
index 000000000..bc8e4f824
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-2.c
@@ -0,0 +1,29 @@
+/* PR optimization/8746 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O1 -mtune=i586" } */
+
+extern void abort (void);
+
+unsigned short r0;
+
+int foo(int x)
+{
+  unsigned short r = x&0xf000;
+
+  if (!(r&0x8000))
+  {
+    r0 = r;
+    return 0;
+  }
+  else
+    return 1;
+}
+
+int main(void)
+{
+  if (foo(0x8000) != 1)
+    abort();
+
+   return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-3.c
new file mode 100644
index 000000000..8f1de5129
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/signbit-3.c
@@ -0,0 +1,33 @@
+/* PR optimization/8746 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O1 -mtune=i586" } */
+
+extern void abort (void);
+
+volatile int j;
+
+void f0() { j=0; }
+void f1() { j=1; }
+
+int foo(int x)
+{
+  if ((short int)(x&0x8000) > (short int)0)
+  {
+    f0();
+    return 0;
+  }
+  else
+  {
+    f1();
+    return 1;
+  }
+}
+
+int main(void)
+{
+  if (foo(0x8000) != 1)
+    abort();
+
+   return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-1.c
new file mode 100644
index 000000000..afae22d37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-1.c
@@ -0,0 +1,25 @@
+/* PR 12902 */
+/* { dg-do compile } */
+/* { dg-options "-O1 -msse" } */
+
+#include <xmmintrin.h>
+
+typedef union
+{
+  int i[4];
+  float f[4];
+  __m128 v;
+} vector4_t;
+
+void
+swizzle (const void *a, vector4_t * b, vector4_t * c)
+{
+  b->v = _mm_loadl_pi (b->v, (__m64 *) a);
+  c->v = _mm_loadl_pi (c->v, ((__m64 *) a) + 1);
+}
+
+/* While one legal rendering of each statement would be movaps;movlps;movaps,
+   we can implmenent this with just movlps;movlps.  Since we do now, anything
+   less would be a regression.  */
+/* { dg-final { scan-assembler-not "movaps" } } */
+/* { dg-final { scan-assembler "movlps" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-10.c
new file mode 100644
index 000000000..798551db2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-10.c
@@ -0,0 +1,32 @@
+/* PR 17930 */
+/* { dg-do run } */
+/* { dg-options "-O1 -msse2 -mfpmath=sse -mno-accumulate-outgoing-args -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer" } */
+/* { dg-options "-O1 -msse2 -mfpmath=sse -fno-omit-frame-pointer" { target *-*-mingw* *-*-cygwin* } } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+typedef _Complex double complex_16;
+
+void __attribute__((noinline))
+test (complex_16 a[5][5])
+{
+  int i, j, k;
+  complex_16 x;
+
+  for (j = 0; j < 5; j++)
+    for (i = 0; i < 5; i++)
+      {
+        for (k = 0; k < j - 1; ++k)
+	  x = a[k][i] * ~a[k][j];
+	a[j][i] = x;
+      }
+}
+
+static void
+sse2_test (void)
+{
+  static complex_16 work[5][5];
+
+  test (work); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-11.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-11.c
new file mode 100644
index 000000000..c764c0be5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-11.c
@@ -0,0 +1,75 @@
+/* PR rtl-optimization/21239 */
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+void
+foo (unsigned int x, double *y, const double *z)
+{
+  __m128d tmp;
+  while (x)
+    {
+      tmp = _mm_load_sd (z);
+      _mm_store_sd (y, tmp);
+      --x; ++z; ++y;
+    }
+}
+
+void
+bar (unsigned int x, float *y, const float *z)
+{
+  __m128 tmp;
+  unsigned int i;
+  for (i = 0; i < x; ++i)
+    {
+      tmp = (__m128) { *z, 0, 0, 0 };
+      *y = __builtin_ia32_vec_ext_v4sf (tmp, 0);
+      ++z; ++y;
+    }
+  for (i = 0; i < x; ++i)
+    {
+      tmp = (__m128) { 0, *z, 0, 0 };
+      *y = __builtin_ia32_vec_ext_v4sf (tmp, 1);
+      ++z; ++y;
+    }
+  for (i = 0; i < x; ++i)
+    {
+      tmp = (__m128) { 0, 0, *z, 0 };
+      *y = __builtin_ia32_vec_ext_v4sf (tmp, 2);
+      ++z; ++y;
+    }
+  for (i = 0; i < x; ++i)
+    {
+      tmp = (__m128) { 0, 0, 0, *z };
+      *y = __builtin_ia32_vec_ext_v4sf (tmp, 3);
+      ++z; ++y;
+    }
+}
+
+static void
+sse2_test (void)
+{
+  unsigned int i;
+  double a[16], b[16];
+  float c[16], d[16];
+  for (i = 0; i < 16; ++i)
+    {
+      a[i] = 1;
+      b[i] = 2;
+      c[i] = 3;
+      d[i] = 4;
+    }
+  foo (16, a, b);
+  bar (4, c, d);
+  for (i = 0; i < 16; ++i)
+    {
+      if (a[i] != 2)
+	abort ();
+      if (c[i] != 4)
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-12.c
new file mode 100644
index 000000000..51de357cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -0,0 +1,10 @@
+/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
+   xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
+   popcntintrin.h and mm_malloc.h are usable
+   with -O -std=c89 -pedantic-errors.  */
+/* { dg-do compile } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1" } */
+
+#include <x86intrin.h>
+
+int dummy;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-13.c
new file mode 100644
index 000000000..171e24238
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -0,0 +1,384 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile with optimization.  All of them
+   are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h,
+   mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h,
+   tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h 
+   that reference the proper builtin functions.
+
+   Defining away "extern" and "__inline" results in all of them being
+   compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+/* Following intrinsics require immediate arguments. */
+
+/* ammintrin.h */
+#define __builtin_ia32_extrqi(X, I, L)  __builtin_ia32_extrqi(X, 1, 1)
+#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1)
+
+/* immintrin.h */
+#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1)
+#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1)
+#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1)
+#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1)
+#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1)
+#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1)
+#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1)
+#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1)
+#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1)
+#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1)
+#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1)
+#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1)
+#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1)
+#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1)
+#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1)
+#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1)
+#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1)
+#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1)
+#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1)
+#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1)
+#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
+#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
+#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
+#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 1)
+#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 1)
+
+/* avx512pfintrin.h */
+#define __builtin_ia32_gatherpfdps(A, B, C, D, E) __builtin_ia32_gatherpfdps (A, B, C, 1, 1)
+#define __builtin_ia32_gatherpfqps(A, B, C, D, E) __builtin_ia32_gatherpfqps (A, B, C, 1, 1)
+#define __builtin_ia32_scatterpfdps(A, B, C, D, E) __builtin_ia32_scatterpfdps (A, B, C, 1, 1)
+#define __builtin_ia32_scatterpfqps(A, B, C, D, E) __builtin_ia32_scatterpfqps (A, B, C, 1, 1)
+
+/* avx512erintrin.h */
+#define __builtin_ia32_exp2pd_mask(A, B, C, D) __builtin_ia32_exp2pd_mask (A, B, C, 1)
+#define __builtin_ia32_exp2ps_mask(A, B, C, D) __builtin_ia32_exp2ps_mask (A, B, C, 1)
+#define __builtin_ia32_rcp28pd_mask(A, B, C, D) __builtin_ia32_rcp28pd_mask (A, B, C, 1)
+#define __builtin_ia32_rcp28ps_mask(A, B, C, D) __builtin_ia32_rcp28ps_mask (A, B, C, 1)
+#define __builtin_ia32_rsqrt28pd_mask(A, B, C, D) __builtin_ia32_rsqrt28pd_mask (A, B, C, 1)
+#define __builtin_ia32_rsqrt28ps_mask(A, B, C, D) __builtin_ia32_rsqrt28ps_mask (A, B, C, 1)
+
+/* wmmintrin.h */
+#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1)
+#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1)
+
+/* smmintrin.h */
+#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1)
+#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1)
+#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1)
+#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1)
+
+#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1)
+#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1)
+#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1)
+#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1)
+#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1)
+#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1)
+#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1)
+#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1)
+#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1)
+#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1)
+#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1)
+#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1)
+#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1)
+#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1)
+#define __builtin_ia32_pcmpistrm128(X, Y, M) \
+  __builtin_ia32_pcmpistrm128(X, Y, 1)
+#define __builtin_ia32_pcmpistri128(X, Y, M) \
+  __builtin_ia32_pcmpistri128(X, Y, 1)
+#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpistria128(X, Y, M) \
+  __builtin_ia32_pcmpistria128(X, Y, 1)
+#define __builtin_ia32_pcmpistric128(X, Y, M) \
+  __builtin_ia32_pcmpistric128(X, Y, 1)
+#define __builtin_ia32_pcmpistrio128(X, Y, M) \
+  __builtin_ia32_pcmpistrio128(X, Y, 1)
+#define __builtin_ia32_pcmpistris128(X, Y, M) \
+  __builtin_ia32_pcmpistris128(X, Y, 1)
+#define __builtin_ia32_pcmpistriz128(X, Y, M) \
+  __builtin_ia32_pcmpistriz128(X, Y, 1)
+#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1)
+
+/* tmmintrin.h */
+#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8)
+#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8)
+
+/* emmintrin.h */
+#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8)
+#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8)
+#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0)
+#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0)
+#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0)
+#define __builtin_ia32_vec_set_v8hi(A, D, N) \
+  __builtin_ia32_vec_set_v8hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0)
+#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
+
+/* xmmintrin.h */
+#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, 0, _MM_HINT_NTA)
+#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
+#define __builtin_ia32_vec_set_v4hi(A, D, N) \
+  __builtin_ia32_vec_set_v4hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
+#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
+
+/* xopintrin.h */
+#define __builtin_ia32_vprotbi(A, N) __builtin_ia32_vprotbi (A,1)
+#define __builtin_ia32_vprotwi(A, N) __builtin_ia32_vprotwi (A,1)
+#define __builtin_ia32_vprotdi(A, N) __builtin_ia32_vprotdi (A,1)
+#define __builtin_ia32_vprotqi(A, N) __builtin_ia32_vprotqi (A,1)
+
+/* lwpintrin.h */
+#define __builtin_ia32_lwpval32(D2, D1, F) __builtin_ia32_lwpval32 (D2, D1, 1)
+#define __builtin_ia32_lwpval64(D2, D1, F) __builtin_ia32_lwpval64 (D2, D1, 1)
+#define __builtin_ia32_lwpins32(D2, D1, F) __builtin_ia32_lwpins32 (D2, D1, 1)
+#define __builtin_ia32_lwpins64(D2, D1, F) __builtin_ia32_lwpins64 (D2, D1, 1)
+
+/* tbmintrin.h */
+#define __builtin_ia32_bextri_u32(X, Y) __builtin_ia32_bextri_u32 (X, 1)
+#define __builtin_ia32_bextri_u64(X, Y) __builtin_ia32_bextri_u64 (X, 1)
+
+/* avx2intrin.h */
+#define __builtin_ia32_mpsadbw256(X, Y, Z) __builtin_ia32_mpsadbw256 (X, Y, 1)
+#define __builtin_ia32_palignr256(X, Y, Z) __builtin_ia32_palignr256 (X, Y, 8)
+#define __builtin_ia32_pblendw256(X, Y, Z) __builtin_ia32_pblendw256 (X, Y, 1)
+#define __builtin_ia32_pshufd256(X, Y) __builtin_ia32_pshufd256(X, 1)
+#define __builtin_ia32_pshufhw256(X, Y) __builtin_ia32_pshufhw256(X, 1)
+#define __builtin_ia32_pshuflw256(X, Y) __builtin_ia32_pshuflw256(X, 1)
+#define __builtin_ia32_pslldqi256(X, Y) __builtin_ia32_pslldqi256(X, 8)
+#define __builtin_ia32_psrldqi256(X, Y) __builtin_ia32_psrldqi256(X, 8)
+#define __builtin_ia32_pblendd128(X, Y, Z) __builtin_ia32_pblendd128(X, Y, 1)
+#define __builtin_ia32_pblendd256(X, Y, Z) __builtin_ia32_pblendd256(X, Y, 1)
+#define __builtin_ia32_permdf256(X, Y) __builtin_ia32_permdf256(X, 1)
+#define __builtin_ia32_permdi256(X, Y) __builtin_ia32_permdi256(X, 1)
+#define __builtin_ia32_permti256(X, Y, Z) __builtin_ia32_permti256(X, Y, 1)
+#define __builtin_ia32_extract128i256(X, Y) __builtin_ia32_extract128i256(X, 1)
+#define __builtin_ia32_insert128i256(X, Y, Z) __builtin_ia32_insert128i256(X, Y, 1)
+#define __builtin_ia32_gathersiv2df(X, Y, Z, K, M) __builtin_ia32_gathersiv2df(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv4df(X, Y, Z, K, M) __builtin_ia32_gathersiv4df(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv2df(X, Y, Z, K, M) __builtin_ia32_gatherdiv2df(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4df(X, Y, Z, K, M) __builtin_ia32_gatherdiv4df(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv4sf(X, Y, Z, K, M) __builtin_ia32_gathersiv4sf(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv8sf(X, Y, Z, K, M) __builtin_ia32_gathersiv8sf(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4sf(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv2di(X, Y, Z, K, M) __builtin_ia32_gathersiv2di(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv4di(X, Y, Z, K, M) __builtin_ia32_gathersiv4di(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv2di(X, Y, Z, K, M) __builtin_ia32_gatherdiv2di(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4di(X, Y, Z, K, M) __builtin_ia32_gatherdiv4di(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv4si(X, Y, Z, K, M) __builtin_ia32_gathersiv4si(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv8si(X, Y, Z, K, M) __builtin_ia32_gathersiv8si(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4si(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4si256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si256(X, Y, Z, K, 1)
+
+/* rtmintrin.h */
+#define __builtin_ia32_xabort (N) __builtin_ia32_xabort (1)
+
+/* avx512fintrin.h */
+#define __builtin_ia32_addpd512_mask(A, B, C, D, E) __builtin_ia32_addpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_addps512_mask(A, B, C, D, E) __builtin_ia32_addps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_addsd_mask(A, B, C, D, E) __builtin_ia32_addsd_mask(A, B, C, D, 8)
+#define __builtin_ia32_addss_mask(A, B, C, D, E) __builtin_ia32_addss_mask(A, B, C, D, 8)
+#define __builtin_ia32_alignd512_mask(A, B, F, D, E) __builtin_ia32_alignd512_mask(A, B, 1, D, E)
+#define __builtin_ia32_alignq512_mask(A, B, F, D, E) __builtin_ia32_alignq512_mask(A, B, 1, D, E)
+#define __builtin_ia32_cmpd512_mask(A, B, E, D) __builtin_ia32_cmpd512_mask(A, B, 1, D)
+#define __builtin_ia32_cmppd512_mask(A, B, F, D, E) __builtin_ia32_cmppd512_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpps512_mask(A, B, F, D, E) __builtin_ia32_cmpps512_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpq512_mask(A, B, E, D) __builtin_ia32_cmpq512_mask(A, B, 1, D)
+#define __builtin_ia32_cmpsd_mask(A, B, F, D, E) __builtin_ia32_cmpsd_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpss_mask(A, B, F, D, E) __builtin_ia32_cmpss_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cvtdq2ps512_mask(A, B, C, D) __builtin_ia32_cvtdq2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2dq512_mask(A, B, C, D) __builtin_ia32_cvtpd2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2ps512_mask(A, B, C, D) __builtin_ia32_cvtpd2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2udq512_mask(A, B, C, D) __builtin_ia32_cvtpd2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2dq512_mask(A, B, C, D) __builtin_ia32_cvtps2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2pd512_mask(A, B, C, D) __builtin_ia32_cvtps2pd512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2udq512_mask(A, B, C, D) __builtin_ia32_cvtps2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtsd2ss_mask(A, B, C, D, E) __builtin_ia32_cvtsd2ss_mask(A, B, C, D, 8)
+#define __builtin_ia32_cvtsi2sd64(A, B, C) __builtin_ia32_cvtsi2sd64(A, B, 8)
+#define __builtin_ia32_cvtsi2ss32(A, B, C) __builtin_ia32_cvtsi2ss32(A, B, 8)
+#define __builtin_ia32_cvtsi2ss64(A, B, C) __builtin_ia32_cvtsi2ss64(A, B, 8)
+#define __builtin_ia32_cvtss2sd_mask(A, B, C, D, E) __builtin_ia32_cvtss2sd_mask(A, B, C, D, 8)
+#define __builtin_ia32_cvttpd2dq512_mask(A, B, C, D) __builtin_ia32_cvttpd2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttpd2udq512_mask(A, B, C, D) __builtin_ia32_cvttpd2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttps2dq512_mask(A, B, C, D) __builtin_ia32_cvttps2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttps2udq512_mask(A, B, C, D) __builtin_ia32_cvttps2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtudq2ps512_mask(A, B, C, D) __builtin_ia32_cvtudq2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtusi2sd64(A, B, C) __builtin_ia32_cvtusi2sd64(A, B, 8)
+#define __builtin_ia32_cvtusi2ss32(A, B, C) __builtin_ia32_cvtusi2ss32(A, B, 8)
+#define __builtin_ia32_cvtusi2ss64(A, B, C) __builtin_ia32_cvtusi2ss64(A, B, 8)
+#define __builtin_ia32_divpd512_mask(A, B, C, D, E) __builtin_ia32_divpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_divps512_mask(A, B, C, D, E) __builtin_ia32_divps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_divsd_mask(A, B, C, D, E) __builtin_ia32_divsd_mask(A, B, C, D, 8)
+#define __builtin_ia32_divss_mask(A, B, C, D, E) __builtin_ia32_divss_mask(A, B, C, D, 8)
+#define __builtin_ia32_extractf32x4_mask(A, E, C, D) __builtin_ia32_extractf32x4_mask(A, 1, C, D)
+#define __builtin_ia32_extractf64x4_mask(A, E, C, D) __builtin_ia32_extractf64x4_mask(A, 1, C, D)
+#define __builtin_ia32_extracti32x4_mask(A, E, C, D) __builtin_ia32_extracti32x4_mask(A, 1, C, D)
+#define __builtin_ia32_extracti64x4_mask(A, E, C, D) __builtin_ia32_extracti64x4_mask(A, 1, C, D)
+#define __builtin_ia32_fixupimmpd512_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmpd512_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmpd512_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmpd512_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmps512_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmps512_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmps512_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmps512_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmsd_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmsd_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmsd_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmsd_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmss_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmss_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmss_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmss_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_gatherdiv8df(A, B, C, D, F) __builtin_ia32_gatherdiv8df(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv8di(A, B, C, D, F) __builtin_ia32_gatherdiv8di(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv16sf(A, B, C, D, F) __builtin_ia32_gatherdiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv16si(A, B, C, D, F) __builtin_ia32_gatherdiv16si(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv16sf(A, B, C, D, F) __builtin_ia32_gathersiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv16si(A, B, C, D, F) __builtin_ia32_gathersiv16si(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv8df(A, B, C, D, F) __builtin_ia32_gathersiv8df(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv8di(A, B, C, D, F) __builtin_ia32_gathersiv8di(A, B, C, D, 8)
+#define __builtin_ia32_getexppd512_mask(A, B, C, D) __builtin_ia32_getexppd512_mask(A, B, C, 8)
+#define __builtin_ia32_getexpps512_mask(A, B, C, D) __builtin_ia32_getexpps512_mask(A, B, C, 8)
+#define __builtin_ia32_getexpsd128_mask(A, B, C, D, E) __builtin_ia32_getexpsd128_mask(A, B, C, D, 8)
+#define __builtin_ia32_getexpss128_mask(A, B, C, D, E) __builtin_ia32_getexpss128_mask(A, B, C, D, 8)
+#define __builtin_ia32_getmantpd512_mask(A, F, C, D, E) __builtin_ia32_getmantpd512_mask(A, 1, C, D, 8)
+#define __builtin_ia32_getmantps512_mask(A, F, C, D, E) __builtin_ia32_getmantps512_mask(A, 1, C, D, 8)
+#define __builtin_ia32_getmantsd_mask(A, B, I, D, E, F) __builtin_ia32_getmantsd_mask(A, B, 1, D, E, 8)
+#define __builtin_ia32_getmantss_mask(A, B, I, D, E, F) __builtin_ia32_getmantss_mask(A, B, 1, D, E, 8)
+#define __builtin_ia32_insertf32x4_mask(A, B, F, D, E) __builtin_ia32_insertf32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_insertf64x4_mask(A, B, F, D, E) __builtin_ia32_insertf64x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_inserti32x4_mask(A, B, F, D, E) __builtin_ia32_inserti32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_inserti64x4_mask(A, B, F, D, E) __builtin_ia32_inserti64x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_maxpd512_mask(A, B, C, D, E) __builtin_ia32_maxpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_maxps512_mask(A, B, C, D, E) __builtin_ia32_maxps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_maxsd_mask(A, B, C, D, E) __builtin_ia32_maxsd_mask(A, B, C, D, 8)
+#define __builtin_ia32_maxss_mask(A, B, C, D, E) __builtin_ia32_maxss_mask(A, B, C, D, 8)
+#define __builtin_ia32_minpd512_mask(A, B, C, D, E) __builtin_ia32_minpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_minps512_mask(A, B, C, D, E) __builtin_ia32_minps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_minsd_mask(A, B, C, D, E) __builtin_ia32_minsd_mask(A, B, C, D, 8)
+#define __builtin_ia32_minss_mask(A, B, C, D, E) __builtin_ia32_minss_mask(A, B, C, D, 8)
+#define __builtin_ia32_mulpd512_mask(A, B, C, D, E) __builtin_ia32_mulpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_mulps512_mask(A, B, C, D, E) __builtin_ia32_mulps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_mulsd_mask(A, B, C, D, E) __builtin_ia32_mulsd_mask(A, B, C, D, 8)
+#define __builtin_ia32_mulss_mask(A, B, C, D, E) __builtin_ia32_mulss_mask(A, B, C, D, 8)
+#define __builtin_ia32_permdf512_mask(A, E, C, D) __builtin_ia32_permdf512_mask(A, 1, C, D)
+#define __builtin_ia32_permdi512_mask(A, E, C, D) __builtin_ia32_permdi512_mask(A, 1, C, D)
+#define __builtin_ia32_prold512_mask(A, E, C, D) __builtin_ia32_prold512_mask(A, 1, C, D)
+#define __builtin_ia32_prolq512_mask(A, E, C, D) __builtin_ia32_prolq512_mask(A, 1, C, D)
+#define __builtin_ia32_prord512_mask(A, E, C, D) __builtin_ia32_prord512_mask(A, 1, C, D)
+#define __builtin_ia32_prorq512_mask(A, E, C, D) __builtin_ia32_prorq512_mask(A, 1, C, D)
+#define __builtin_ia32_pshufd512_mask(A, E, C, D) __builtin_ia32_pshufd512_mask(A, 1, C, D)
+#define __builtin_ia32_pslldi512_mask(A, E, C, D) __builtin_ia32_pslldi512_mask(A, 1, C, D)
+#define __builtin_ia32_psllqi512_mask(A, E, C, D) __builtin_ia32_psllqi512_mask(A, 1, C, D)
+#define __builtin_ia32_psradi512_mask(A, E, C, D) __builtin_ia32_psradi512_mask(A, 1, C, D)
+#define __builtin_ia32_psraqi512_mask(A, E, C, D) __builtin_ia32_psraqi512_mask(A, 1, C, D)
+#define __builtin_ia32_psrldi512_mask(A, E, C, D) __builtin_ia32_psrldi512_mask(A, 1, C, D)
+#define __builtin_ia32_psrlqi512_mask(A, E, C, D) __builtin_ia32_psrlqi512_mask(A, 1, C, D)
+#define __builtin_ia32_pternlogd512_mask(A, B, C, F, E) __builtin_ia32_pternlogd512_mask(A, B, C, 1, E)
+#define __builtin_ia32_pternlogd512_maskz(A, B, C, F, E) __builtin_ia32_pternlogd512_maskz(A, B, C, 1, E)
+#define __builtin_ia32_pternlogq512_mask(A, B, C, F, E) __builtin_ia32_pternlogq512_mask(A, B, C, 1, E)
+#define __builtin_ia32_pternlogq512_maskz(A, B, C, F, E) __builtin_ia32_pternlogq512_maskz(A, B, C, 1, E)
+#define __builtin_ia32_rndscalepd_mask(A, F, C, D, E) __builtin_ia32_rndscalepd_mask(A, 1, C, D, 8)
+#define __builtin_ia32_rndscaleps_mask(A, F, C, D, E) __builtin_ia32_rndscaleps_mask(A, 1, C, D, 8)
+#define __builtin_ia32_rndscalesd_mask(A, B, I, D, E, F) __builtin_ia32_rndscalesd_mask(A, B, 1, D, E, 8)
+#define __builtin_ia32_rndscaless_mask(A, B, I, D, E, F) __builtin_ia32_rndscaless_mask(A, B, 1, D, E, 8)
+#define __builtin_ia32_scalefpd512_mask(A, B, C, D, E) __builtin_ia32_scalefpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_scalefps512_mask(A, B, C, D, E) __builtin_ia32_scalefps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_scalefsd_mask(A, B, C, D, E) __builtin_ia32_scalefsd_mask(A, B, C, D, 8)
+#define __builtin_ia32_scalefss_mask(A, B, C, D, E) __builtin_ia32_scalefss_mask(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv8df(A, B, C, D, F) __builtin_ia32_scatterdiv8df(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv8di(A, B, C, D, F) __builtin_ia32_scatterdiv8di(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv16sf(A, B, C, D, F) __builtin_ia32_scatterdiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv16si(A, B, C, D, F) __builtin_ia32_scatterdiv16si(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv16sf(A, B, C, D, F) __builtin_ia32_scattersiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv16si(A, B, C, D, F) __builtin_ia32_scattersiv16si(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv8df(A, B, C, D, F) __builtin_ia32_scattersiv8df(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv8di(A, B, C, D, F) __builtin_ia32_scattersiv8di(A, B, C, D, 8)
+#define __builtin_ia32_shuf_f32x4_mask(A, B, F, D, E) __builtin_ia32_shuf_f32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_f64x2_mask(A, B, F, D, E) __builtin_ia32_shuf_f64x2_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_i32x4_mask(A, B, F, D, E) __builtin_ia32_shuf_i32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_i64x2_mask(A, B, F, D, E) __builtin_ia32_shuf_i64x2_mask(A, B, 1, D, E)
+#define __builtin_ia32_shufpd512_mask(A, B, F, D, E) __builtin_ia32_shufpd512_mask(A, B, 1, D, E)
+#define __builtin_ia32_shufps512_mask(A, B, F, D, E) __builtin_ia32_shufps512_mask(A, B, 1, D, E)
+#define __builtin_ia32_sqrtpd512_mask(A, B, C, D) __builtin_ia32_sqrtpd512_mask(A, B, C, 8)
+#define __builtin_ia32_sqrtps512_mask(A, B, C, D) __builtin_ia32_sqrtps512_mask(A, B, C, 8)
+#define __builtin_ia32_sqrtsd_mask(A, B, C, D, E) __builtin_ia32_sqrtsd_mask(A, B, C, D, 8)
+#define __builtin_ia32_sqrtss_mask(A, B, C, D, E) __builtin_ia32_sqrtss_mask(A, B, C, D, 8)
+#define __builtin_ia32_subpd512_mask(A, B, C, D, E) __builtin_ia32_subpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_subps512_mask(A, B, C, D, E) __builtin_ia32_subps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_subsd_mask(A, B, C, D, E) __builtin_ia32_subsd_mask(A, B, C, D, 8)
+#define __builtin_ia32_subss_mask(A, B, C, D, E) __builtin_ia32_subss_mask(A, B, C, D, 8)
+#define __builtin_ia32_ucmpd512_mask(A, B, E, D) __builtin_ia32_ucmpd512_mask(A, B, 1, D)
+#define __builtin_ia32_ucmpq512_mask(A, B, E, D) __builtin_ia32_ucmpq512_mask(A, B, 1, D)
+#define __builtin_ia32_vcomisd(A, B, C, D) __builtin_ia32_vcomisd(A, B, 1, 8)
+#define __builtin_ia32_vcomiss(A, B, C, D) __builtin_ia32_vcomiss(A, B, 1, 8)
+#define __builtin_ia32_vcvtph2ps512_mask(A, B, C, D) __builtin_ia32_vcvtph2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_vcvtps2ph512_mask(A, E, C, D) __builtin_ia32_vcvtps2ph512_mask(A, 1, C, D)
+#define __builtin_ia32_vcvtsd2si32(A, B) __builtin_ia32_vcvtsd2si32(A, 8)
+#define __builtin_ia32_vcvtsd2si64(A, B) __builtin_ia32_vcvtsd2si64(A, 8)
+#define __builtin_ia32_vcvtsd2usi32(A, B) __builtin_ia32_vcvtsd2usi32(A, 8)
+#define __builtin_ia32_vcvtsd2usi64(A, B) __builtin_ia32_vcvtsd2usi64(A, 8)
+#define __builtin_ia32_vcvtss2si32(A, B) __builtin_ia32_vcvtss2si32(A, 8)
+#define __builtin_ia32_vcvtss2si64(A, B) __builtin_ia32_vcvtss2si64(A, 8)
+#define __builtin_ia32_vcvtss2usi32(A, B) __builtin_ia32_vcvtss2usi32(A, 8)
+#define __builtin_ia32_vcvtss2usi64(A, B) __builtin_ia32_vcvtss2usi64(A, 8)
+#define __builtin_ia32_vcvttsd2si32(A, B) __builtin_ia32_vcvttsd2si32(A, 8)
+#define __builtin_ia32_vcvttsd2si64(A, B) __builtin_ia32_vcvttsd2si64(A, 8)
+#define __builtin_ia32_vcvttsd2usi32(A, B) __builtin_ia32_vcvttsd2usi32(A, 8)
+#define __builtin_ia32_vcvttsd2usi64(A, B) __builtin_ia32_vcvttsd2usi64(A, 8)
+#define __builtin_ia32_vcvttss2si32(A, B) __builtin_ia32_vcvttss2si32(A, 8)
+#define __builtin_ia32_vcvttss2si64(A, B) __builtin_ia32_vcvttss2si64(A, 8)
+#define __builtin_ia32_vcvttss2usi32(A, B) __builtin_ia32_vcvttss2usi32(A, 8)
+#define __builtin_ia32_vcvttss2usi64(A, B) __builtin_ia32_vcvttss2usi64(A, 8)
+#define __builtin_ia32_vfmaddpd512_mask(A, B, C, D, E) __builtin_ia32_vfmaddpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddpd512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddpd512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_mask(A, B, C, D, E) __builtin_ia32_vfmaddps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddps512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsd3_mask(A, B, C, D, E) __builtin_ia32_vfmaddsd3_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsd3_mask3(A, B, C, D, E) __builtin_ia32_vfmaddsd3_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsd3_maskz(A, B, C, D, E) __builtin_ia32_vfmaddsd3_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddss3_mask(A, B, C, D, E) __builtin_ia32_vfmaddss3_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddss3_mask3(A, B, C, D, E) __builtin_ia32_vfmaddss3_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddss3_maskz(A, B, C, D, E) __builtin_ia32_vfmaddss3_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubpd512_mask(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubpd512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_mask(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubaddpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubaddpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubaddps512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubaddps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubsd3_mask3(A, B, C, D, E) __builtin_ia32_vfmsubsd3_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubss3_mask3(A, B, C, D, E) __builtin_ia32_vfmsubss3_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd512_mask(A, B, C, D, E) __builtin_ia32_vfnmaddpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps512_mask(A, B, C, D, E) __builtin_ia32_vfnmaddps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubpd512_mask(A, B, C, D, E) __builtin_ia32_vfnmsubpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubps512_mask(A, B, C, D, E) __builtin_ia32_vfnmsubps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vpermilpd512_mask(A, E, C, D) __builtin_ia32_vpermilpd512_mask(A, 1, C, D)
+#define __builtin_ia32_vpermilps512_mask(A, E, C, D) __builtin_ia32_vpermilps512_mask(A, 1, C, D)
+
+/* shaintrin.h */
+#define __builtin_ia32_sha1rnds4(A, B, C) __builtin_ia32_sha1rnds4(A, B, 1)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-14.c
new file mode 100644
index 000000000..d9a5fedda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -0,0 +1,643 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile without optimization.  All of them are
+   defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h,
+   fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, 
+   lwpintrin.h, fmaintrin.h and mm_malloc.h that reference the proper 
+   builtin functions.
+
+   Defining away "extern" and "__inline" results in all of them being compiled
+   as proper functions.  */
+
+#define extern
+#define __inline
+
+#include <x86intrin.h>
+
+#define _CONCAT(x,y) x ## y
+
+#define test_0(func, type, imm)						\
+  type _CONCAT(_,func) (int const I)					\
+  { return func (imm); }
+
+#define test_1(func, type, op1_type, imm)				\
+  type _CONCAT(_,func) (op1_type A, int const I)			\
+  { return func (A, imm); }
+
+#define test_1x(func, type, op1_type, imm1, imm2)			\
+  type _CONCAT(_,func) (op1_type A, int const I, int const L)		\
+  { return func (A, imm1, imm2); }
+
+#define test_1y(func, type, op1_type, imm1, imm2, imm3)			\
+  type _CONCAT(_,func) (op1_type A, int const I, int const L, int const R)\
+  { return func (A, imm1, imm2, imm3); }
+
+#define test_2(func, type, op1_type, op2_type, imm)			\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I)		\
+  { return func (A, B, imm); }
+
+#define test_2x(func, type, op1_type, op2_type, imm1, imm2)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
+  { return func (A, B, imm1, imm2); }
+
+#define test_2y(func, type, op1_type, op2_type, imm1, imm2, imm3)	 \
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L,\
+			int const R)					 \
+  { return func (A, B, imm1, imm2, imm3); }
+
+#define test_2vx(func, op1_type, op2_type, imm1, imm2)     \
+  _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
+  { func (A, B, imm1, imm2); }
+
+#define test_3(func, type, op1_type, op2_type, op3_type, imm)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I)			\
+  { return func (A, B, C, imm); }
+
+#define test_3x(func, type, op1_type, op2_type, op3_type, imm1, imm2)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I, int const L)			\
+  { return func (A, B, C, imm1, imm2); }
+
+#define test_3y(func, type, op1_type, op2_type, op3_type, imm1, imm2, imm3)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I, int const L, int const R)	\
+  { return func (A, B, C, imm1, imm2, imm3); }
+
+#define test_3v(func, op1_type, op2_type, op3_type, imm)		\
+  _CONCAT(_,func) (op1_type A, op2_type B,				\
+		   op3_type C, int const I)				\
+  { func (A, B, C, imm); }
+
+#define test_3vx(func, op1_type, op2_type, op3_type, imm1, imm2)   \
+  _CONCAT(_,func) (op1_type A, op2_type B,             \
+           op3_type C, int const I, int const L)       \
+  { func (A, B, C, imm1, imm2); }
+
+#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, op4_type D, int const I)		\
+  { return func (A, B, C, D, imm); }
+
+#define test_4x(func, type, op1_type, op2_type, op3_type, op4_type, imm1, imm2)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, op4_type D, int const I, int const L)		\
+  { return func (A, B, C, D, imm1, imm2); }
+
+#define test_4y(func, type, op1_type, op2_type, op3_type, op4_type, imm1, imm2, imm3)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,	op3_type C,		\
+			op4_type D, int const I, int const L, int const R)		\
+  { return func (A, B, C, D, imm1, imm2, imm3); }
+
+#define test_4v(func, op1_type, op2_type, op3_type, op4_type, imm)	\
+  _CONCAT(_,func) (op1_type A, op2_type B,				\
+		   op3_type C, op4_type D, int const I)			\
+  { func (A, B, C, D, imm); }
+
+
+/* Following intrinsics require immediate arguments.  They
+   are defined as macros for non-optimized compilations. */
+
+/* ammintrin.h */
+test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
+test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
+
+/* immintrin.h */
+test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1)
+test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1)
+test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1)
+test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1)
+test_1 (_mm256_extractf128_ps, __m128, __m256, 1)
+test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1)
+test_1 (_mm256_extract_epi8, int, __m256i, 20)
+test_1 (_mm256_extract_epi16, int, __m256i, 13)
+test_1 (_mm256_extract_epi32, int, __m256i, 6)
+#ifdef __x86_64__
+test_1 (_mm256_extract_epi64, long long, __m256i, 2)
+#endif
+test_1 (_mm_permute_pd, __m128d, __m128d, 1)
+test_1 (_mm256_permute_pd, __m256d, __m256d, 1)
+test_1 (_mm_permute_ps, __m128, __m128, 1)
+test_1 (_mm256_permute_ps, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1)
+test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1)
+test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1)
+test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1)
+test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30)
+test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7)
+test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3)
+#ifdef __x86_64__
+test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1)
+#endif
+test_1 (_mm256_round_pd, __m256d, __m256d, 9)
+test_1 (_mm256_round_ps, __m256, __m256, 9)
+test_1 (_cvtss_sh, unsigned short, float, 1)
+test_1 (_mm_cvtps_ph, __m128i, __m128, 1)
+test_1 (_mm256_cvtps_ph, __m128i, __m256, 1)
+test_0 (_xabort, void, 1)
+test_1 (_mm512_cvt_roundepi32_ps, __m512, __m512i, 9)
+test_1 (_mm512_cvt_roundepu32_ps, __m512, __m512i, 9)
+test_1 (_mm512_cvt_roundpd_epi32, __m256i, __m512d, 9)
+test_1 (_mm512_cvt_roundpd_epu32, __m256i, __m512d, 9)
+test_1 (_mm512_cvt_roundpd_ps, __m256, __m512d, 9)
+test_1 (_mm512_cvt_roundph_ps, __m512, __m256i, 8)
+test_1 (_mm512_cvt_roundps_epi32, __m512i, __m512, 9)
+test_1 (_mm512_cvt_roundps_epu32, __m512i, __m512, 9)
+test_1 (_mm512_cvt_roundps_pd, __m512d, __m256, 8)
+test_1 (_mm512_cvtps_ph, __m256i, __m512, 1)
+test_1 (_mm512_cvtt_roundpd_epi32, __m256i, __m512d, 8)
+test_1 (_mm512_cvtt_roundpd_epu32, __m256i, __m512d, 8)
+test_1 (_mm512_cvtt_roundps_epi32, __m512i, __m512, 8)
+test_1 (_mm512_cvtt_roundps_epu32, __m512i, __m512, 8)
+test_1 (_mm512_extractf32x4_ps, __m128, __m512, 1)
+test_1 (_mm512_extractf64x4_pd, __m256d, __m512d, 1)
+test_1 (_mm512_extracti32x4_epi32, __m128i, __m512i, 1)
+test_1 (_mm512_extracti64x4_epi64, __m256i, __m512i, 1)
+test_1 (_mm512_getexp_round_pd, __m512d, __m512d, 8)
+test_1 (_mm512_getexp_round_ps, __m512, __m512, 8)
+test_1y (_mm512_getmant_round_pd, __m512d, __m512d, 1, 1, 8)
+test_1y (_mm512_getmant_round_ps, __m512, __m512, 1, 1, 8)
+test_1 (_mm512_permute_pd, __m512d, __m512d, 1)
+test_1 (_mm512_permute_ps, __m512, __m512, 1)
+test_1 (_mm512_permutex_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_permutex_pd, __m512d, __m512d, 1)
+test_1 (_mm512_rol_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_rol_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_ror_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_ror_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_shuffle_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_slli_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_slli_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_sqrt_round_pd, __m512d, __m512d, 9)
+test_1 (_mm512_sqrt_round_ps, __m512, __m512, 9)
+test_1 (_mm512_srai_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_srai_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_srli_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_srli_epi64, __m512i, __m512i, 1)
+test_1 (_mm_cvt_roundsd_i32, int, __m128d, 9)
+test_1 (_mm_cvt_roundsd_u32, unsigned, __m128d, 9)
+test_1 (_mm_cvt_roundss_i32, int, __m128, 9)
+test_1 (_mm_cvt_roundss_u32, unsigned, __m128, 9)
+test_1 (_mm_cvtt_roundsd_i32, int, __m128d, 8)
+test_1 (_mm_cvtt_roundsd_u32, unsigned, __m128d, 8)
+test_1 (_mm_cvtt_roundss_i32, int, __m128, 8)
+test_1 (_mm_cvtt_roundss_u32, unsigned, __m128, 8)
+test_1x (_mm512_getmant_pd, __m512d, __m512d, 1, 1)
+test_1x (_mm512_getmant_ps, __m512, __m512, 1, 1)
+test_1x (_mm512_roundscale_round_pd, __m512d, __m512d, 1, 8)
+test_1x (_mm512_roundscale_round_ps, __m512, __m512, 1, 8)
+test_1x (_mm_cvt_roundi32_ss, __m128, __m128, 1, 9)
+test_2 (_mm512_add_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_add_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm512_alignr_epi32, __m512i, __m512i, __m512i, 1)
+test_2 (_mm512_alignr_epi64, __m512i, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_epi32_mask, __mmask16, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_epi64_mask, __mmask8, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_epu32_mask, __mmask16, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_epu64_mask, __mmask8, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_pd_mask, __mmask8, __m512d, __m512d, 1)
+test_2 (_mm512_cmp_ps_mask, __mmask16, __m512, __m512, 1)
+test_2 (_mm512_div_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_div_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm512_i32gather_epi32, __m512i, __m512i, void const *, 1)
+test_2 (_mm512_i32gather_epi64, __m512i, __m256i, void const *, 1)
+test_2 (_mm512_i32gather_pd, __m512d, __m256i, void const *, 1)
+test_2 (_mm512_i32gather_ps, __m512, __m512i, void const *, 1)
+test_2 (_mm512_i64gather_epi32, __m256i, __m512i, void const *, 1)
+test_2 (_mm512_i64gather_epi64, __m512i, __m512i, void const *, 1)
+test_2 (_mm512_i64gather_pd, __m512d, __m512i, void const *, 1)
+test_2 (_mm512_i64gather_ps, __m256, __m512i, void const *, 1)
+test_2 (_mm512_insertf32x4, __m512, __m512, __m128, 1)
+test_2 (_mm512_insertf64x4, __m512d, __m512d, __m256d, 1)
+test_2 (_mm512_inserti32x4, __m512i, __m512i, __m128i, 1)
+test_2 (_mm512_inserti64x4, __m512i, __m512i, __m256i, 1)
+test_2 (_mm512_maskz_cvt_roundepi32_ps, __m512, __mmask16, __m512i, 9)
+test_2 (_mm512_maskz_cvt_roundepu32_ps, __m512, __mmask16, __m512i, 9)
+test_2 (_mm512_maskz_cvt_roundpd_epi32, __m256i, __mmask8, __m512d, 9)
+test_2 (_mm512_maskz_cvt_roundpd_epu32, __m256i, __mmask8, __m512d, 9)
+test_2 (_mm512_maskz_cvt_roundpd_ps, __m256, __mmask8, __m512d, 9)
+test_2 (_mm512_maskz_cvt_roundph_ps, __m512, __mmask16, __m256i, 8)
+test_2 (_mm512_maskz_cvt_roundps_epi32, __m512i, __mmask16, __m512, 9)
+test_2 (_mm512_maskz_cvt_roundps_epu32, __m512i, __mmask16, __m512, 9)
+test_2 (_mm512_maskz_cvt_roundps_pd, __m512d, __mmask8, __m256, 8)
+test_2 (_mm512_maskz_cvtps_ph, __m256i, __mmask16, __m512, 1)
+test_2 (_mm512_maskz_cvtt_roundpd_epi32, __m256i, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_cvtt_roundpd_epu32, __m256i, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_cvtt_roundps_epi32, __m512i, __mmask16, __m512, 8)
+test_2 (_mm512_maskz_cvtt_roundps_epu32, __m512i, __mmask16, __m512, 8)
+test_2 (_mm512_maskz_extractf32x4_ps, __m128, __mmask8, __m512, 1)
+test_2 (_mm512_maskz_extractf64x4_pd, __m256d, __mmask8, __m512d, 1)
+test_2 (_mm512_maskz_extracti32x4_epi32, __m128i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_extracti64x4_epi64, __m256i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_getexp_round_pd, __m512d, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_getexp_round_ps, __m512, __mmask16, __m512, 8)
+test_2y (_mm512_maskz_getmant_round_pd, __m512d, __mmask8, __m512d, 1, 1, 8)
+test_2y (_mm512_maskz_getmant_round_ps, __m512, __mmask16, __m512, 1, 1, 8)
+test_2 (_mm512_maskz_permute_pd, __m512d, __mmask8, __m512d, 1)
+test_2 (_mm512_maskz_permute_ps, __m512, __mmask16, __m512, 1)
+test_2 (_mm512_maskz_permutex_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_permutex_pd, __m512d, __mmask8, __m512d, 1)
+test_2 (_mm512_maskz_rol_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_rol_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_ror_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_ror_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_shuffle_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_slli_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_slli_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_sqrt_round_pd, __m512d, __mmask8, __m512d, 9)
+test_2 (_mm512_maskz_sqrt_round_ps, __m512, __mmask16, __m512, 9)
+test_2 (_mm512_maskz_srai_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_srai_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_srli_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_srli_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_max_round_pd, __m512d, __m512d, __m512d, 8)
+test_2 (_mm512_max_round_ps, __m512, __m512, __m512, 8)
+test_2 (_mm512_min_round_pd, __m512d, __m512d, __m512d, 8)
+test_2 (_mm512_min_round_ps, __m512, __m512, __m512, 8)
+test_2 (_mm512_mul_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_mul_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm512_scalef_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_scalef_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm512_shuffle_f32x4, __m512, __m512, __m512, 1)
+test_2 (_mm512_shuffle_f64x2, __m512d, __m512d, __m512d, 1)
+test_2 (_mm512_shuffle_i32x4, __m512i, __m512i, __m512i, 1)
+test_2 (_mm512_shuffle_i64x2, __m512i, __m512i, __m512i, 1)
+test_2 (_mm512_shuffle_pd, __m512d, __m512d, __m512d, 1)
+test_2 (_mm512_shuffle_ps, __m512, __m512, __m512, 1)
+test_2 (_mm512_sub_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_sub_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm_add_round_sd, __m128d, __m128d, __m128d, 9)
+test_2 (_mm_add_round_ss, __m128, __m128, __m128, 9)
+test_2 (_mm_cmp_sd_mask, __mmask8, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ss_mask, __mmask8, __m128, __m128, 1)
+#ifdef __x86_64__
+test_2 (_mm_cvt_roundi64_sd, __m128d, __m128d, long long, 9)
+test_2 (_mm_cvt_roundi64_ss, __m128, __m128, long long, 9)
+#endif
+test_2 (_mm_cvt_roundsd_ss, __m128, __m128, __m128d, 9)
+test_2 (_mm_cvt_roundss_sd, __m128d, __m128d, __m128, 8)
+test_2 (_mm_cvt_roundu32_ss, __m128, __m128, unsigned, 9)
+#ifdef __x86_64__
+test_2 (_mm_cvt_roundu64_sd, __m128d, __m128d, unsigned long long, 9)
+test_2 (_mm_cvt_roundu64_ss, __m128, __m128, unsigned long long, 9)
+#endif
+test_2 (_mm_div_round_sd, __m128d, __m128d, __m128d, 9)
+test_2 (_mm_div_round_ss, __m128, __m128, __m128, 9)
+test_2 (_mm_getexp_round_sd, __m128d, __m128d, __m128d, 8)
+test_2 (_mm_getexp_round_ss, __m128, __m128, __m128, 8)
+test_2y (_mm_getmant_round_sd, __m128d, __m128d, __m128d, 1, 1, 8)
+test_2y (_mm_getmant_round_ss, __m128, __m128, __m128, 1, 1, 8)
+test_2 (_mm_mul_round_sd, __m128d, __m128d, __m128d, 9)
+test_2 (_mm_mul_round_ss, __m128, __m128, __m128, 9)
+test_2 (_mm_scalef_round_sd, __m128d, __m128d, __m128d, 9)
+test_2 (_mm_scalef_round_ss, __m128, __m128, __m128, 9)
+test_2 (_mm_sqrt_round_sd, __m128d, __m128d, __m128d, 9)
+test_2 (_mm_sqrt_round_ss, __m128, __m128, __m128, 9)
+test_2 (_mm_sub_round_sd, __m128d, __m128d, __m128d, 9)
+test_2 (_mm_sub_round_ss, __m128, __m128, __m128, 9)
+test_2x (_mm512_cmp_round_pd_mask, __mmask8, __m512d, __m512d, 1, 8)
+test_2x (_mm512_cmp_round_ps_mask, __mmask16, __m512, __m512, 1, 8)
+test_2x (_mm512_maskz_roundscale_round_pd, __m512d, __mmask8, __m512d, 1, 8)
+test_2x (_mm512_maskz_roundscale_round_ps, __m512, __mmask16, __m512, 1, 8)
+test_2x (_mm_cmp_round_sd_mask, __mmask8, __m128d, __m128d, 1, 8)
+test_2x (_mm_cmp_round_ss_mask, __mmask8, __m128, __m128, 1, 8)
+test_2x (_mm_comi_round_sd, int, __m128d, __m128d, 1, 8)
+test_2x (_mm_comi_round_ss, int, __m128, __m128, 1, 8)
+test_2x (_mm_roundscale_round_sd, __m128d, __m128d, __m128d, 1, 8)
+test_2x (_mm_roundscale_round_ss, __m128, __m128, __m128, 1, 8)
+test_3 (_mm512_fmadd_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fmadd_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fmaddsub_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fmaddsub_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fmsub_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fmsub_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fmsubadd_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fmsubadd_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fnmadd_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fnmadd_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fnmsub_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fnmsub_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_mask_cmp_epi32_mask, __mmask16, __mmask16, __m512i, __m512i, 1)
+test_3 (_mm512_mask_cmp_epi64_mask, __mmask8, __mmask8, __m512i, __m512i, 1)
+test_3 (_mm512_mask_cmp_epu32_mask, __mmask16, __mmask16, __m512i, __m512i, 1)
+test_3 (_mm512_mask_cmp_epu64_mask, __mmask8, __mmask8, __m512i, __m512i, 1)
+test_3 (_mm512_mask_cmp_pd_mask, __mmask8, __mmask8, __m512d, __m512d, 1)
+test_3 (_mm512_mask_cmp_ps_mask, __mmask16, __mmask16, __m512, __m512, 1)
+test_3 (_mm512_mask_cvt_roundepi32_ps, __m512, __m512, __mmask16, __m512i, 9)
+test_3 (_mm512_mask_cvt_roundepu32_ps, __m512, __m512, __mmask16, __m512i, 9)
+test_3 (_mm512_mask_cvt_roundpd_epi32, __m256i, __m256i, __mmask8, __m512d, 9)
+test_3 (_mm512_mask_cvt_roundpd_epu32, __m256i, __m256i, __mmask8, __m512d, 9)
+test_3 (_mm512_mask_cvt_roundpd_ps, __m256, __m256, __mmask8, __m512d, 9)
+test_3 (_mm512_mask_cvt_roundph_ps, __m512, __m512, __mmask16, __m256i, 8)
+test_3 (_mm512_mask_cvt_roundps_epi32, __m512i, __m512i, __mmask16, __m512, 9)
+test_3 (_mm512_mask_cvt_roundps_epu32, __m512i, __m512i, __mmask16, __m512, 9)
+test_3 (_mm512_mask_cvt_roundps_pd, __m512d, __m512d, __mmask8, __m256, 8)
+test_3 (_mm512_mask_cvtps_ph, __m256i, __m256i, __mmask16, __m512, 1)
+test_3 (_mm512_mask_cvtt_roundpd_epi32, __m256i, __m256i, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_cvtt_roundpd_epu32, __m256i, __m256i, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_cvtt_roundps_epi32, __m512i, __m512i, __mmask16, __m512, 8)
+test_3 (_mm512_mask_cvtt_roundps_epu32, __m512i, __m512i, __mmask16, __m512, 8)
+test_3 (_mm512_mask_extractf32x4_ps, __m128, __m128, __mmask8, __m512, 1)
+test_3 (_mm512_mask_extractf64x4_pd, __m256d, __m256d, __mmask8, __m512d, 1)
+test_3 (_mm512_mask_extracti32x4_epi32, __m128i, __m128i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_extracti64x4_epi64, __m256i, __m256i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_getexp_round_pd, __m512d, __m512d, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_getexp_round_ps, __m512, __m512, __mmask16, __m512, 8)
+test_3y (_mm512_mask_getmant_round_pd, __m512d, __m512d, __mmask8, __m512d, 1, 1, 8)
+test_3y (_mm512_mask_getmant_round_ps, __m512, __m512, __mmask16, __m512, 1, 1, 8)
+test_3 (_mm512_mask_permute_pd, __m512d, __m512d, __mmask8, __m512d, 1)
+test_3 (_mm512_mask_permute_ps, __m512, __m512, __mmask16, __m512, 1)
+test_3 (_mm512_mask_permutex_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_permutex_pd, __m512d, __m512d, __mmask8, __m512d, 1)
+test_3 (_mm512_mask_rol_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_rol_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_ror_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_ror_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_shuffle_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_slli_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_slli_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_sqrt_round_pd, __m512d, __m512d, __mmask8, __m512d, 9)
+test_3 (_mm512_mask_sqrt_round_ps, __m512, __m512, __mmask16, __m512, 9)
+test_3 (_mm512_mask_srai_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_srai_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_srli_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_srli_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_maskz_add_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_add_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_maskz_alignr_epi32, __m512i, __mmask16, __m512i, __m512i, 1)
+test_3 (_mm512_maskz_alignr_epi64, __m512i, __mmask8, __m512i, __m512i, 1)
+test_3 (_mm512_maskz_div_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_div_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_maskz_insertf32x4, __m512, __mmask16, __m512, __m128, 1)
+test_3 (_mm512_maskz_insertf64x4, __m512d, __mmask8, __m512d, __m256d, 1)
+test_3 (_mm512_maskz_inserti32x4, __m512i, __mmask16, __m512i, __m128i, 1)
+test_3 (_mm512_maskz_inserti64x4, __m512i, __mmask8, __m512i, __m256i, 1)
+test_3 (_mm512_maskz_max_round_pd, __m512d, __mmask8, __m512d, __m512d, 8)
+test_3 (_mm512_maskz_max_round_ps, __m512, __mmask16, __m512, __m512, 8)
+test_3 (_mm512_maskz_min_round_pd, __m512d, __mmask8, __m512d, __m512d, 8)
+test_3 (_mm512_maskz_min_round_ps, __m512, __mmask16, __m512, __m512, 8)
+test_3 (_mm512_maskz_mul_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_mul_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_maskz_scalef_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_scalef_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_maskz_shuffle_f32x4, __m512, __mmask16, __m512, __m512, 1)
+test_3 (_mm512_maskz_shuffle_f64x2, __m512d, __mmask8, __m512d, __m512d, 1)
+test_3 (_mm512_maskz_shuffle_i32x4, __m512i, __mmask16, __m512i, __m512i, 1)
+test_3 (_mm512_maskz_shuffle_i64x2, __m512i, __mmask8, __m512i, __m512i, 1)
+test_3 (_mm512_maskz_shuffle_pd, __m512d, __mmask8, __m512d, __m512d, 1)
+test_3 (_mm512_maskz_shuffle_ps, __m512, __mmask16, __m512, __m512, 1)
+test_3 (_mm512_maskz_sub_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_sub_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_ternarylogic_epi32, __m512i, __m512i, __m512i, __m512i, 1)
+test_3 (_mm512_ternarylogic_epi64, __m512i, __m512i, __m512i, __m512i, 1)
+test_3 (_mm_fmadd_round_sd, __m128d, __m128d, __m128d, __m128d, 9)
+test_3 (_mm_fmadd_round_ss, __m128, __m128, __m128, __m128, 9)
+test_3 (_mm_fmsub_round_sd, __m128d, __m128d, __m128d, __m128d, 9)
+test_3 (_mm_fmsub_round_ss, __m128, __m128, __m128, __m128, 9)
+test_3 (_mm_fnmadd_round_sd, __m128d, __m128d, __m128d, __m128d, 9)
+test_3 (_mm_fnmadd_round_ss, __m128, __m128, __m128, __m128, 9)
+test_3 (_mm_fnmsub_round_sd, __m128d, __m128d, __m128d, __m128d, 9)
+test_3 (_mm_fnmsub_round_ss, __m128, __m128, __m128, __m128, 9)
+test_3 (_mm_mask_cmp_sd_mask, __mmask8, __mmask8, __m128d, __m128d, 1)
+test_3 (_mm_mask_cmp_ss_mask, __mmask8, __mmask8, __m128, __m128, 1)
+test_3v (_mm512_i32scatter_epi32, void *, __m512i, __m512i, 1)
+test_3v (_mm512_i32scatter_epi64, void *, __m256i, __m512i, 1)
+test_3v (_mm512_i32scatter_pd, void *, __m256i, __m512d, 1)
+test_3v (_mm512_i32scatter_ps, void *, __m512i, __m512, 1)
+test_3v (_mm512_i64scatter_epi32, void *, __m512i, __m256i, 1)
+test_3v (_mm512_i64scatter_epi64, void *, __m512i, __m512i, 1)
+test_3v (_mm512_i64scatter_pd, void *, __m512i, __m512d, 1)
+test_3v (_mm512_i64scatter_ps, void *, __m512i, __m256, 1)
+test_3x (_mm512_mask_roundscale_round_pd, __m512d, __m512d, __mmask8, __m512d, 1, 8)
+test_3x (_mm512_mask_roundscale_round_ps, __m512, __m512, __mmask16, __m512, 1, 8)
+test_3x (_mm_fixupimm_round_sd, __m128d, __m128d, __m128d, __m128i, 1, 8)
+test_3x (_mm_fixupimm_round_ss, __m128, __m128, __m128, __m128i, 1, 8)
+test_3x (_mm_mask_cmp_round_sd_mask, __mmask8, __mmask8, __m128d, __m128d, 1, 8)
+test_3x (_mm_mask_cmp_round_ss_mask, __mmask8, __mmask8, __m128, __m128, 1, 8)
+test_4 (_mm512_mask3_fmadd_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fmadd_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fmaddsub_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fmaddsub_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fmsub_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fmsub_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fmsubadd_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fmsubadd_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fnmadd_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fnmadd_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fnmsub_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fnmsub_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask_add_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_add_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_alignr_epi32, __m512i, __m512i, __mmask16, __m512i, __m512i, 1)
+test_4 (_mm512_mask_alignr_epi64, __m512i, __m512i, __mmask8, __m512i, __m512i, 1)
+test_4 (_mm512_mask_div_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_div_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fmadd_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fmadd_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fmaddsub_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fmaddsub_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fmsub_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fmsub_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fmsubadd_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fmsubadd_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fnmadd_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fnmadd_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fnmsub_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fnmsub_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_i32gather_epi32, __m512i, __m512i, __mmask16, __m512i, void const *, 1)
+test_4 (_mm512_mask_i32gather_epi64, __m512i, __m512i, __mmask8, __m256i, void const *, 1)
+test_4 (_mm512_mask_i32gather_pd, __m512d, __m512d, __mmask8, __m256i, void const *, 1)
+test_4 (_mm512_mask_i32gather_ps, __m512, __m512, __mmask16, __m512i, void const *, 1)
+test_4 (_mm512_mask_i64gather_epi32, __m256i, __m256i, __mmask8, __m512i, void const *, 1)
+test_4 (_mm512_mask_i64gather_epi64, __m512i, __m512i, __mmask8, __m512i, void const *, 1)
+test_4 (_mm512_mask_i64gather_pd, __m512d, __m512d, __mmask8, __m512i, void const *, 1)
+test_4 (_mm512_mask_i64gather_ps, __m256, __m256, __mmask8, __m512i, void const *, 1)
+test_4 (_mm512_mask_insertf32x4, __m512, __m512, __mmask16, __m512, __m128, 1)
+test_4 (_mm512_mask_insertf64x4, __m512d, __m512d, __mmask8, __m512d, __m256d, 1)
+test_4 (_mm512_mask_inserti32x4, __m512i, __m512i, __mmask16, __m512i, __m128i, 1)
+test_4 (_mm512_mask_inserti64x4, __m512i, __m512i, __mmask8, __m512i, __m256i, 1)
+test_4 (_mm512_mask_max_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 8)
+test_4 (_mm512_mask_max_round_ps, __m512, __m512, __mmask16, __m512, __m512, 8)
+test_4 (_mm512_mask_min_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 8)
+test_4 (_mm512_mask_min_round_ps, __m512, __m512, __mmask16, __m512, __m512, 8)
+test_4 (_mm512_mask_mul_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_mul_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_scalef_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_scalef_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_shuffle_f32x4, __m512, __m512, __mmask16, __m512, __m512, 1)
+test_4 (_mm512_mask_shuffle_f64x2, __m512d, __m512d, __mmask8, __m512d, __m512d, 1)
+test_4 (_mm512_mask_shuffle_i32x4, __m512i, __m512i, __mmask16, __m512i, __m512i, 1)
+test_4 (_mm512_mask_shuffle_i64x2, __m512i, __m512i, __mmask8, __m512i, __m512i, 1)
+test_4 (_mm512_mask_shuffle_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 1)
+test_4 (_mm512_mask_shuffle_ps, __m512, __m512, __mmask16, __m512, __m512, 1)
+test_4 (_mm512_mask_sub_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_sub_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_ternarylogic_epi32, __m512i, __m512i, __mmask16, __m512i, __m512i, 1)
+test_4 (_mm512_mask_ternarylogic_epi64, __m512i, __m512i, __mmask8, __m512i, __m512i, 1)
+test_4 (_mm512_maskz_fmadd_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fmadd_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fmaddsub_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fmaddsub_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fmsub_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fmsub_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fmsubadd_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fmsubadd_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fnmadd_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fnmadd_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fnmsub_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fnmsub_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_ternarylogic_epi32, __m512i, __mmask16, __m512i, __m512i, __m512i, 1)
+test_4 (_mm512_maskz_ternarylogic_epi64, __m512i, __mmask8, __m512i, __m512i, __m512i, 1)
+test_4v (_mm512_mask_i32scatter_epi32, void *, __mmask16, __m512i, __m512i, 1)
+test_4v (_mm512_mask_i32scatter_epi64, void *, __mmask8, __m256i, __m512i, 1)
+test_4v (_mm512_mask_i32scatter_pd, void *, __mmask8, __m256i, __m512d, 1)
+test_4v (_mm512_mask_i32scatter_ps, void *, __mmask16, __m512i, __m512, 1)
+test_4v (_mm512_mask_i64scatter_epi32, void *, __mmask8, __m512i, __m256i, 1)
+test_4v (_mm512_mask_i64scatter_epi64, void *, __mmask8, __m512i, __m512i, 1)
+test_4v (_mm512_mask_i64scatter_pd, void *, __mmask8, __m512i, __m512d, 1)
+test_4v (_mm512_mask_i64scatter_ps, void *, __mmask8, __m512i, __m256, 1)
+test_4x (_mm512_mask_fixupimm_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512i, 1, 8)
+test_4x (_mm512_mask_fixupimm_round_ps, __m512, __m512, __mmask16, __m512, __m512i, 1, 8)
+test_4x (_mm512_maskz_fixupimm_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512i, 1, 8)
+test_4x (_mm512_maskz_fixupimm_round_ps, __m512, __mmask16, __m512, __m512, __m512i, 1, 8)
+test_4x (_mm_mask_fixupimm_round_sd, __m128d, __m128d, __mmask8, __m128d, __m128i, 1, 8)
+test_4x (_mm_mask_fixupimm_round_ss, __m128, __m128, __mmask8, __m128, __m128i, 1, 8)
+test_4x (_mm_maskz_fixupimm_round_sd, __m128d, __mmask8, __m128d, __m128d, __m128i, 1, 8)
+test_4x (_mm_maskz_fixupimm_round_ss, __m128, __mmask8, __m128, __m128, __m128i, 1, 8)
+
+/* avx512pfintrin.h */
+test_3vx (_mm512_mask_prefetch_i32gather_ps, __m512i, __mmask16, void const *, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i32scatter_ps, void const *, __mmask16, __m512i, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i64gather_ps, __m512i, __mmask8, void const *, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i64scatter_ps, void const *, __mmask8, __m512i, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i32gather_pd, __m256i, __mmask8, void const *, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i32scatter_pd, void const *, __mmask8, __m256i, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i64gather_pd, __m512i, __mmask8, void const *, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i64scatter_pd, void const *, __mmask8, __m512i, 1, _MM_HINT_T0)
+
+/* avx512erintrin.h */
+test_1 (_mm512_exp2a23_round_pd, __m512d, __m512d, 8)
+test_1 (_mm512_exp2a23_round_ps, __m512, __m512, 8)
+test_1 (_mm512_rcp28_round_pd, __m512d, __m512d, 8)
+test_1 (_mm512_rcp28_round_ps, __m512, __m512, 8)
+test_1 (_mm512_rsqrt28_round_pd, __m512d, __m512d, 8)
+test_1 (_mm512_rsqrt28_round_ps, __m512, __m512, 8)
+test_2 (_mm512_maskz_exp2a23_round_pd, __m512d, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_exp2a23_round_ps, __m512, __mmask16, __m512, 8)
+test_2 (_mm512_maskz_rcp28_round_pd, __m512d, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_rcp28_round_ps, __m512, __mmask16, __m512, 8)
+test_2 (_mm512_maskz_rsqrt28_round_pd, __m512d, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_rsqrt28_round_ps, __m512, __mmask16, __m512, 8)
+test_3 (_mm512_mask_exp2a23_round_pd, __m512d, __m512d, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_exp2a23_round_ps, __m512, __m512, __mmask16, __m512, 8)
+test_3 (_mm512_mask_rcp28_round_pd, __m512d, __m512d, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_rcp28_round_ps, __m512, __m512, __mmask16, __m512, 8)
+test_3 (_mm512_mask_rsqrt28_round_pd, __m512d, __m512d, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_rsqrt28_round_ps, __m512, __m512, __mmask16, __m512, 8)
+
+/* shaintrin.h */
+test_2 (_mm_sha1rnds4_epu32, __m128i, __m128i, __m128i, 1)
+
+/* wmmintrin.h */
+test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
+test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
+
+/* smmintrin.h */
+test_1 (_mm_round_pd, __m128d, __m128d, 9)
+test_1 (_mm_round_ps, __m128, __m128, 9)
+test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 9)
+test_2 (_mm_round_ss, __m128, __m128, __m128, 9)
+
+test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_dp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_insert_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_ps, int, __m128, 1)
+test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1)
+test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1)
+#ifdef __x86_64__
+test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1)
+#endif
+test_1 (_mm_extract_epi8, int, __m128i, 1)
+test_1 (_mm_extract_epi32, int, __m128i, 1)
+#ifdef __x86_64__
+test_1 (_mm_extract_epi64, long long, __m128i, 1)
+#endif
+test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistri, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1)
+test_2 (_mm_cmpistra, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistro, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
+
+/* tmmintrin.h */
+test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1)
+
+/* emmintrin.h */
+test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1)
+test_1 (_mm_srli_si128, __m128i, __m128i, 1)
+test_1 (_mm_slli_si128, __m128i, __m128i, 1)
+test_1 (_mm_extract_epi16, int, __m128i, 1)
+test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1)
+test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1)
+
+/* xmmintrin.h */
+test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_pi16, int, __m64, 1)
+test_1 (_m_pextrw, int, __m64, 1)
+test_2 (_mm_insert_pi16, __m64, __m64, int, 1)
+test_2 (_m_pinsrw, __m64, __m64, int, 1)
+test_1 (_mm_shuffle_pi16, __m64, __m64, 1)
+test_1 (_m_pshufw, __m64, __m64, 1)
+test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
+
+/* xopintrin.h */
+test_1 ( _mm_roti_epi8, __m128i, __m128i, 1)
+test_1 ( _mm_roti_epi16, __m128i, __m128i, 1)
+test_1 ( _mm_roti_epi32, __m128i, __m128i, 1)
+test_1 ( _mm_roti_epi64, __m128i, __m128i, 1)
+test_3 (_mm_permute2_pd, __m128d, __m128d, __m128d, __m128d, 1)
+test_3 (_mm256_permute2_pd, __m256d, __m256d, __m256d, __m256d, 1)
+test_3 (_mm_permute2_ps, __m128, __m128, __m128, __m128, 1)
+test_3 (_mm256_permute2_ps, __m256, __m256, __m256, __m256, 1)
+
+/* lwpintrin.h */
+test_2 ( __lwpval32, void, unsigned int, unsigned int, 1)
+test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1)
+#ifdef __x86_64__
+test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1)
+test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1)
+#endif
+
+/* tbmintrin.h */
+test_1 ( __bextri_u32, unsigned int, unsigned int, 1)
+#ifdef __x86_64__
+test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-15.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-15.c
new file mode 100644
index 000000000..5a1da7a75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-15.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse -msse2" } */
+
+/* Test that the intrinsics compile with optimization.  These were not
+   tested in i386-sse-[12].c because these builtins require immediate
+   operands.  */
+
+#include <xmmintrin.h>
+
+__m128
+test_shuf (void)
+{
+  __m128 a = _mm_set1_ps (1.0);
+  __m128 b = _mm_set1_ps (2.0);
+  return _mm_shuffle_ps (a, b, _MM_SHUFFLE (0,1,2,3));
+}
+
+__m64
+test_ins_ext (__m64 a)
+{
+  return _mm_insert_pi16 (a, _mm_extract_pi16 (a, 0), 3);
+}
+
+__m64
+test_shuf2 (__m64 a)
+{
+  return _mm_shuffle_pi16 (a, 0xA5);
+}
+
+void
+test_prefetch (char *p)
+{
+  _mm_prefetch (p, _MM_HINT_T0);
+  _mm_prefetch (p+4, _MM_HINT_T1);
+  _mm_prefetch (p+8, _MM_HINT_T2);
+  _mm_prefetch (p+12, _MM_HINT_NTA);
+}
+
+__m128i
+test__slli_si128 (__m128i a)
+{
+  return _mm_slli_si128 (a, 3);
+}
+
+__m128i
+test__srli_si128 (__m128i a)
+{
+  return _mm_srli_si128 (a, 3);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-16.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-16.c
new file mode 100644
index 000000000..e429630cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-16.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse" } */
+
+typedef float __vr __attribute__ ((vector_size (16)));
+
+struct vector
+{
+  union
+  {
+    __vr v;
+    float f[4];
+  };
+};
+
+void
+doit ()
+{
+  float f[4];
+  struct vector v;
+
+  f[0] = 0;
+  f[1] = 1;
+  f[2] = 2;
+  f[3] = 3;
+
+  v.v = __builtin_ia32_loadups (f);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-17.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-17.c
new file mode 100644
index 000000000..3386a3b58
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-17.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+#include "sse2-check.h"
+#include <xmmintrin.h>
+extern void abort();
+int untrue = 0;
+typedef union {
+  __v4sf v;
+  float f[4];
+} u;
+void foo (u, u) __attribute__((noinline));
+void foo (u a, u b) {
+  if (b.f[0] != 7.0 || b.f[1] != 8.0 || b.f[2] != 3.0 || b.f[3] != 4.0)
+    abort();
+}
+void bar (__v4sf, __v4sf) __attribute__((noinline));
+void bar (__v4sf a __attribute((unused)), __v4sf b __attribute((unused))) { untrue = 0;}
+__v4sf setupa () __attribute((noinline));
+__v4sf setupa () { __v4sf t = { 1.0, 2.0, 3.0, 4.0 }; return t; }
+__v4sf setupb () __attribute((noinline));
+__v4sf setupb () { __v4sf t = { 5.0, 6.0, 7.0, 8.0 }; return t; }
+void __attribute__((noinline))
+sse2_test(void) {
+  u a, b;
+  a.v = setupa ();
+  b.v = setupb ();
+  if (untrue)
+    bar(a.v, b.v);
+  b.v = (__v4sf) _mm_movehl_ps ((__m128)a.v, (__m128)b.v);
+  foo (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-18.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-18.c
new file mode 100644
index 000000000..6a1352b82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-18.c
@@ -0,0 +1,33 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+__m128i foo (char) __attribute__((noinline));
+__m128i foo (char x) {
+  return _mm_set1_epi8(x);
+}
+__m128i bar (char) __attribute__((noinline));
+__m128i bar (char x) {
+  return _mm_set_epi8 (x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x);
+}
+
+static void
+sse2_test (void) {
+  int i, j;
+  union u { __m128i v; char c[16]; };
+  union u x, y;
+
+  for (i = -128; i <= 127; i++)
+    {
+      x.v = foo ((char)i);
+      y.v = bar ((char)i);
+      for (j=0; j<16; j++)
+	if (x.c[j] != y.c[j])
+	  abort();
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-19.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-19.c
new file mode 100644
index 000000000..3025567fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-19.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=x86-64" } } */
+/* { dg-options "-O3 -march=x86-64 -msse2 -mno-ssse3" } */
+/* { dg-final { scan-assembler "punpcklbw" } } */
+extern void abort();
+#include <emmintrin.h>
+__m128i foo (char) __attribute__((noinline));
+__m128i foo (char x) {
+  return _mm_set1_epi8(x);
+}
+__m128i bar (char) __attribute__((noinline));
+__m128i bar (char x) {
+  return _mm_set_epi8 (x,x,x,x,x,x,x,x,x,x,x,x,x,x,x,x);
+}
+
+main() {
+  int i, j;
+  union u { __m128i v; char c[16]; };
+  union u x, y;
+  for (i = -128; i <= 127; i++)
+    {
+      x.v = foo ((char)i);
+      y.v = bar ((char)i);
+      for (j=0; j<16; j++)
+	if (x.c[j] != y.c[j])
+	  abort();
+    }
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-2.c
new file mode 100644
index 000000000..c2f3e0b17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse" } */
+
+#include <xmmintrin.h>
+static const __m128 v_sign = {-.0f, -.0f, -.0f, -.0f};
+static const __m128 v_half = {0.5f, 0.5f, 0.5f, 0.5f};
+static const __m128 v_one  = {1.0f, 1.0f, 1.0f, 1.0f};
+static inline __m128 insn_ABS (__m128 a)
+{
+  return _mm_andnot_ps (v_sign, a);
+}
+__m128 voodoo (__m128 a)
+{
+  __m128 x = insn_ABS (a), y = _mm_rsqrt_ps (x);
+  y = _mm_add_ps (_mm_mul_ps (_mm_sub_ps (_mm_setzero_ps(), _mm_sub_ps (_mm_mul_ps (x, _mm_add_ps (_mm_mul_ps (y, y), _mm_setzero_ps())), v_one)), _mm_add_ps (_mm_mul_ps (y, v_half), _mm_setzero_ps())), y);
+  return y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-20.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-20.c
new file mode 100644
index 000000000..fc0744f25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-20.c
@@ -0,0 +1,27 @@
+/* PR target/13685 */
+/* { dg-options "-Os -msse" } */
+/* { dg-require-effective-target sse } */
+
+typedef float __m128 __attribute__ ((vector_size (16)));
+typedef int __m64 __attribute__ ((vector_size (8)));
+
+int puts (const char *s);
+void foo (__m128 *, __m64 *, int);
+
+int main (void)
+{
+  foo (0, 0, 0);
+  return 0;
+}
+
+void foo (__m128 *dst, __m64 *src, int n)
+{
+  __m128 xmm0 = { 0 };
+  while (n > 64)
+    {
+      puts ("");
+      xmm0 = __builtin_ia32_cvtpi2ps (xmm0, *src);
+      *dst = xmm0;
+      n --;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-21.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-21.c
new file mode 100644
index 000000000..d006cdc0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-21.c
@@ -0,0 +1,24 @@
+/* Test that we don't generate a fisttp instruction when -mno-sse3.  */
+/* { dg-do compile } */
+/* { dg-options "-O -mfpmath=387 -march=nocona -mno-sse3 -mno-avx" } */
+/* { dg-final { scan-assembler-not "fisttp" } } */
+struct foo
+{
+ long a;
+ long b;
+};
+
+extern double c;
+
+extern unsigned long long baz (void);
+
+int
+walrus (const struct foo *input)
+{
+    unsigned long long d;
+
+    d = baz ()
+      + (unsigned long long) (((double) input->a * 1000000000
+			      + (double) input->b) * c);
+    return (d ? 1 : 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-22.c
new file mode 100644
index 000000000..e9f227a2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -0,0 +1,722 @@
+/* Same as sse-14, except converted to use #pragma GCC option.  */
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile with optimization.  All of them
+   are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h,
+   mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h,
+   tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h 
+   that reference the proper builtin functions.
+
+   Defining away "extern" and "__inline" results in all of them being
+   compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+#define _CONCAT(x,y) x ## y
+
+#define test_0(func, type, imm)						\
+  type _CONCAT(_,func) (int const I)					\
+  { return func (imm); }
+
+#define test_1(func, type, op1_type, imm)				\
+  type _CONCAT(_,func) (op1_type A, int const I)			\
+  { return func (A, imm); }
+
+#define test_1x(func, type, op1_type, imm1, imm2)			\
+  type _CONCAT(_,func) (op1_type A, int const I, int const L)		\
+  { return func (A, imm1, imm2); }
+
+#define test_1y(func, type, op1_type, imm1, imm2, imm3)			\
+  type _CONCAT(_,func) (op1_type A, int const I, int const L, int const R)\
+  { return func (A, imm1, imm2, imm3); }
+
+#define test_2(func, type, op1_type, op2_type, imm)			\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I)		\
+  { return func (A, B, imm); }
+
+#define test_2x(func, type, op1_type, op2_type, imm1, imm2)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
+  { return func (A, B, imm1, imm2); }
+
+#define test_2y(func, type, op1_type, op2_type, imm1, imm2, imm3)	 \
+  type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L,\
+			int const R)					 \
+  { return func (A, B, imm1, imm2, imm3); }
+
+#define test_2vx(func, op1_type, op2_type, imm1, imm2)     \
+  _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
+  { func (A, B, imm1, imm2); }
+
+#define test_3(func, type, op1_type, op2_type, op3_type, imm)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I)			\
+  { return func (A, B, C, imm); }
+
+#define test_3x(func, type, op1_type, op2_type, op3_type, imm1, imm2)		\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I, int const L)			\
+  { return func (A, B, C, imm1, imm2); }
+
+#define test_3y(func, type, op1_type, op2_type, op3_type, imm1, imm2, imm3)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, int const I, int const L, int const R)	\
+  { return func (A, B, C, imm1, imm2, imm3); }
+
+#define test_3v(func, op1_type, op2_type, op3_type, imm)		\
+  _CONCAT(_,func) (op1_type A, op2_type B,				\
+		   op3_type C, int const I)				\
+  { func (A, B, C, imm); }
+
+#define test_3vx(func, op1_type, op2_type, op3_type, imm1, imm2)   \
+  _CONCAT(_,func) (op1_type A, op2_type B,             \
+           op3_type C, int const I, int const L)       \
+  { func (A, B, C, imm1, imm2); }
+
+#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, op4_type D, int const I)		\
+  { return func (A, B, C, D, imm); }
+
+#define test_4x(func, type, op1_type, op2_type, op3_type, op4_type, imm1, imm2)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,				\
+			op3_type C, op4_type D, int const I, int const L)		\
+  { return func (A, B, C, D, imm1, imm2); }
+
+#define test_4y(func, type, op1_type, op2_type, op3_type, op4_type, imm1, imm2, imm3)	\
+  type _CONCAT(_,func) (op1_type A, op2_type B,	op3_type C,		\
+			op4_type D, int const I, int const L, int const R)		\
+  { return func (A, B, C, D, imm1, imm2, imm3); }
+
+
+#define test_4v(func, op1_type, op2_type, op3_type, op4_type, imm)	\
+  _CONCAT(_,func) (op1_type A, op2_type B,				\
+		   op3_type C, op4_type D, int const I)			\
+  { func (A, B, C, D, imm); }
+
+
+#ifndef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1")
+#endif
+
+/* Following intrinsics require immediate arguments.  They
+   are defined as macros for non-optimized compilations. */
+
+/* mmintrin.h (MMX).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("mmx")
+#endif
+#include <mmintrin.h>
+
+/* mm3dnow.h (3DNOW).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("3dnow")
+#endif
+#include <mm3dnow.h>
+
+/* xmmintrin.h (SSE).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse")
+#endif
+#include <xmmintrin.h>
+test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_pi16, int, __m64, 1)
+test_1 (_m_pextrw, int, __m64, 1)
+test_2 (_mm_insert_pi16, __m64, __m64, int, 1)
+test_2 (_m_pinsrw, __m64, __m64, int, 1)
+test_1 (_mm_shuffle_pi16, __m64, __m64, 1)
+test_1 (_m_pshufw, __m64, __m64, 1)
+test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
+
+/* emmintrin.h (SSE2).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse2")
+#endif
+#include <emmintrin.h>
+test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1)
+test_1 (_mm_srli_si128, __m128i, __m128i, 1)
+test_1 (_mm_slli_si128, __m128i, __m128i, 1)
+test_1 (_mm_extract_epi16, int, __m128i, 1)
+test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1)
+test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1)
+test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1)
+
+/* pmmintrin.h (SSE3).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse3")
+#endif
+#include <pmmintrin.h>
+
+/* tmmintrin.h (SSSE3).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("ssse3")
+#endif
+#include <tmmintrin.h>
+test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1)
+
+/* ammintrin.h (SSE4A).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse4a")
+#endif
+#include <ammintrin.h>
+test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
+test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
+
+/* Note, nmmintrin.h includes smmintrin.h, and smmintrin.h
+   checks for the #ifdef.  So just set the option to SSE4.2.  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("sse4.2")
+#endif
+#include <nmmintrin.h>
+/* smmintrin.h (SSE4.2).  */
+test_1 (_mm_round_pd, __m128d, __m128d, 9)
+test_1 (_mm_round_ps, __m128, __m128, 9)
+test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 9)
+test_2 (_mm_round_ss, __m128, __m128, __m128, 9)
+
+test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_dp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_insert_ps, __m128, __m128, __m128, 1)
+test_1 (_mm_extract_ps, int, __m128, 1)
+test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1)
+test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1)
+#ifdef __x86_64__
+test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1)
+#endif
+test_1 (_mm_extract_epi8, int, __m128i, 1)
+test_1 (_mm_extract_epi32, int, __m128i, 1)
+#ifdef __x86_64__
+test_1 (_mm_extract_epi64, long long, __m128i, 1)
+#endif
+test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1)
+test_2 (_mm_cmpistri, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1)
+test_2 (_mm_cmpistra, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistro, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1)
+test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1)
+test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
+test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
+
+/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha")
+#endif
+#include <immintrin.h>
+test_1 (_cvtss_sh, unsigned short, float, 1)
+test_1 (_mm_cvtps_ph, __m128i, __m128, 1)
+test_1 (_mm256_cvtps_ph, __m128i, __m256, 1)
+
+/* avxintrin.h */
+test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1)
+test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1)
+test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1)
+test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1)
+test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1)
+test_1 (_mm256_extractf128_ps, __m128, __m256, 1)
+test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1)
+test_1 (_mm256_extract_epi8, int, __m256i, 20)
+test_1 (_mm256_extract_epi16, int, __m256i, 13)
+test_1 (_mm256_extract_epi32, int, __m256i, 6)
+#ifdef __x86_64__
+test_1 (_mm256_extract_epi64, long long, __m256i, 2)
+#endif
+test_1 (_mm_permute_pd, __m128d, __m128d, 1)
+test_1 (_mm256_permute_pd, __m256d, __m256d, 1)
+test_1 (_mm_permute_ps, __m128, __m128, 1)
+test_1 (_mm256_permute_ps, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1)
+test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1)
+test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1)
+test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1)
+test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1)
+test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1)
+test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30)
+test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7)
+test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3)
+#ifdef __x86_64__
+test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1)
+#endif
+test_1 (_mm256_round_pd, __m256d, __m256d, 9)
+test_1 (_mm256_round_ps, __m256, __m256, 9)
+
+/* avx2intrin.h */
+test_2 ( _mm256_mpsadbw_epu8, __m256i, __m256i, __m256i, 1)
+test_2 ( _mm256_alignr_epi8, __m256i, __m256i, __m256i, 1)
+test_2 ( _mm256_blend_epi16, __m256i, __m256i, __m256i, 1)
+test_1 ( _mm256_shuffle_epi32, __m256i, __m256i, 1)
+test_1 ( _mm256_shufflehi_epi16, __m256i, __m256i, 1)
+test_1 ( _mm256_shufflelo_epi16, __m256i, __m256i, 1)
+test_1 ( _mm256_slli_si256, __m256i, __m256i, 8)
+test_1 ( _mm256_srli_si256, __m256i, __m256i, 8)
+test_2 ( _mm_blend_epi32, __m128i, __m128i, __m128i, 1)
+test_2 ( _mm256_blend_epi32, __m256i, __m256i, __m256, 1)
+test_1 ( _mm256_permute4x64_pd, __m256d, __m256d, 1)
+test_1 ( _mm256_permute4x64_epi64, __m256i, __m256i, 1)
+test_2 ( _mm256_permute2x128_si256, __m256i, __m256i, __m256i, 1)
+test_1 ( _mm256_extracti128_si256, __m128i, __m256i, 1)
+test_2 ( _mm256_inserti128_si256, __m256i, __m256i, __m128i, 1)
+test_2 ( _mm_i32gather_pd, __m128d, double const *, __m128i, 1)
+test_2 ( _mm256_i32gather_pd, __m256d, double const *, __m128i, 1)
+test_2 ( _mm_i64gather_pd, __m128d, double const *, __m128i, 1)
+test_2 ( _mm256_i64gather_pd, __m256d, double const *, __m256i, 1)
+test_2 ( _mm_i32gather_ps, __m128, float const *, __m128i, 1)
+test_2 ( _mm256_i32gather_ps, __m256, float const *, __m256i, 1)
+test_2 ( _mm_i64gather_ps, __m128, float const *, __m128i, 1)
+test_2 ( _mm256_i64gather_ps, __m128, float const *, __m256i, 1)
+test_2 ( _mm_i32gather_epi64, __m128i, long long int const *, __m128i, 1)
+test_2 ( _mm256_i32gather_epi64, __m256i, long long int const *, __m128i, 1)
+test_2 ( _mm_i64gather_epi64, __m128i, long long int const *, __m128i, 1)
+test_2 ( _mm256_i64gather_epi64,  __m256i, long long int const *, __m256i, 1)
+test_2 ( _mm_i32gather_epi32, __m128i, int const *, __m128i, 1)
+test_2 ( _mm256_i32gather_epi32, __m256i, int const *, __m256i, 1)
+test_2 ( _mm_i64gather_epi32, __m128i, int const *, __m128i, 1)
+test_2 ( _mm256_i64gather_epi32, __m128i, int const *, __m256i, 1)
+
+/* rtmintrin.h */
+test_0 ( _xabort, void, 1)
+
+/* avx512fintrin.h */
+test_1 (_mm512_cvt_roundepi32_ps, __m512, __m512i, 9)
+test_1 (_mm512_cvt_roundepu32_ps, __m512, __m512i, 9)
+test_1 (_mm512_cvt_roundpd_epi32, __m256i, __m512d, 9)
+test_1 (_mm512_cvt_roundpd_epu32, __m256i, __m512d, 9)
+test_1 (_mm512_cvt_roundpd_ps, __m256, __m512d, 9)
+test_1 (_mm512_cvt_roundph_ps, __m512, __m256i, 8)
+test_1 (_mm512_cvt_roundps_epi32, __m512i, __m512, 9)
+test_1 (_mm512_cvt_roundps_epu32, __m512i, __m512, 9)
+test_1 (_mm512_cvt_roundps_pd, __m512d, __m256, 8)
+test_1 (_mm512_cvtps_ph, __m256i, __m512, 1)
+test_1 (_mm512_cvtt_roundpd_epi32, __m256i, __m512d, 8)
+test_1 (_mm512_cvtt_roundpd_epu32, __m256i, __m512d, 8)
+test_1 (_mm512_cvtt_roundps_epi32, __m512i, __m512, 8)
+test_1 (_mm512_cvtt_roundps_epu32, __m512i, __m512, 8)
+test_1 (_mm512_extractf32x4_ps, __m128, __m512, 1)
+test_1 (_mm512_extractf64x4_pd, __m256d, __m512d, 1)
+test_1 (_mm512_extracti32x4_epi32, __m128i, __m512i, 1)
+test_1 (_mm512_extracti64x4_epi64, __m256i, __m512i, 1)
+test_1 (_mm512_getexp_round_pd, __m512d, __m512d, 8)
+test_1 (_mm512_getexp_round_ps, __m512, __m512, 8)
+test_1y (_mm512_getmant_round_pd, __m512d, __m512d, 1, 1, 8)
+test_1y (_mm512_getmant_round_ps, __m512, __m512, 1, 1, 8)
+test_1 (_mm512_permute_pd, __m512d, __m512d, 1)
+test_1 (_mm512_permute_ps, __m512, __m512, 1)
+test_1 (_mm512_permutex_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_permutex_pd, __m512d, __m512d, 1)
+test_1 (_mm512_rol_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_rol_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_ror_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_ror_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_shuffle_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_slli_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_slli_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_sqrt_round_pd, __m512d, __m512d, 9)
+test_1 (_mm512_sqrt_round_ps, __m512, __m512, 9)
+test_1 (_mm512_srai_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_srai_epi64, __m512i, __m512i, 1)
+test_1 (_mm512_srli_epi32, __m512i, __m512i, 1)
+test_1 (_mm512_srli_epi64, __m512i, __m512i, 1)
+test_1 (_mm_cvt_roundsd_i32, int, __m128d, 9)
+test_1 (_mm_cvt_roundsd_u32, unsigned, __m128d, 9)
+test_1 (_mm_cvt_roundss_i32, int, __m128, 9)
+test_1 (_mm_cvt_roundss_u32, unsigned, __m128, 9)
+test_1 (_mm_cvtt_roundsd_i32, int, __m128d, 8)
+test_1 (_mm_cvtt_roundsd_u32, unsigned, __m128d, 8)
+test_1 (_mm_cvtt_roundss_i32, int, __m128, 8)
+test_1 (_mm_cvtt_roundss_u32, unsigned, __m128, 8)
+test_1x (_mm512_getmant_pd, __m512d, __m512d, 1, 1)
+test_1x (_mm512_getmant_ps, __m512, __m512, 1, 1)
+test_1x (_mm_cvt_roundi32_ss, __m128, __m128, 1, 9)
+test_2 (_mm512_add_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_add_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm512_alignr_epi32, __m512i, __m512i, __m512i, 1)
+test_2 (_mm512_alignr_epi64, __m512i, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_epi32_mask, __mmask16, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_epi64_mask, __mmask8, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_epu32_mask, __mmask16, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_epu64_mask, __mmask8, __m512i, __m512i, 1)
+test_2 (_mm512_cmp_pd_mask, __mmask8, __m512d, __m512d, 1)
+test_2 (_mm512_cmp_ps_mask, __mmask16, __m512, __m512, 1)
+test_2 (_mm512_div_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_div_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm512_i32gather_epi32, __m512i, __m512i, void const *, 1)
+test_2 (_mm512_i32gather_epi64, __m512i, __m256i, void const *, 1)
+test_2 (_mm512_i32gather_pd, __m512d, __m256i, void const *, 1)
+test_2 (_mm512_i32gather_ps, __m512, __m512i, void const *, 1)
+test_2 (_mm512_i64gather_epi32, __m256i, __m512i, void const *, 1)
+test_2 (_mm512_i64gather_epi64, __m512i, __m512i, void const *, 1)
+test_2 (_mm512_i64gather_pd, __m512d, __m512i, void const *, 1)
+test_2 (_mm512_i64gather_ps, __m256, __m512i, void const *, 1)
+test_2 (_mm512_insertf32x4, __m512, __m512, __m128, 1)
+test_2 (_mm512_insertf64x4, __m512d, __m512d, __m256d, 1)
+test_2 (_mm512_inserti32x4, __m512i, __m512i, __m128i, 1)
+test_2 (_mm512_inserti64x4, __m512i, __m512i, __m256i, 1)
+test_2 (_mm512_maskz_cvt_roundepi32_ps, __m512, __mmask16, __m512i, 9)
+test_2 (_mm512_maskz_cvt_roundepu32_ps, __m512, __mmask16, __m512i, 9)
+test_2 (_mm512_maskz_cvt_roundpd_epi32, __m256i, __mmask8, __m512d, 9)
+test_2 (_mm512_maskz_cvt_roundpd_epu32, __m256i, __mmask8, __m512d, 9)
+test_2 (_mm512_maskz_cvt_roundpd_ps, __m256, __mmask8, __m512d, 9)
+test_2 (_mm512_maskz_cvt_roundph_ps, __m512, __mmask16, __m256i, 8)
+test_2 (_mm512_maskz_cvt_roundps_epi32, __m512i, __mmask16, __m512, 9)
+test_2 (_mm512_maskz_cvt_roundps_epu32, __m512i, __mmask16, __m512, 9)
+test_2 (_mm512_maskz_cvt_roundps_pd, __m512d, __mmask8, __m256, 8)
+test_2 (_mm512_maskz_cvtps_ph, __m256i, __mmask16, __m512, 1)
+test_2 (_mm512_maskz_cvtt_roundpd_epi32, __m256i, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_cvtt_roundpd_epu32, __m256i, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_cvtt_roundps_epi32, __m512i, __mmask16, __m512, 8)
+test_2 (_mm512_maskz_cvtt_roundps_epu32, __m512i, __mmask16, __m512, 8)
+test_2 (_mm512_maskz_extractf32x4_ps, __m128, __mmask8, __m512, 1)
+test_2 (_mm512_maskz_extractf64x4_pd, __m256d, __mmask8, __m512d, 1)
+test_2 (_mm512_maskz_extracti32x4_epi32, __m128i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_extracti64x4_epi64, __m256i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_getexp_round_pd, __m512d, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_getexp_round_ps, __m512, __mmask16, __m512, 8)
+test_2y (_mm512_maskz_getmant_round_pd, __m512d, __mmask8, __m512d, 1, 1, 8)
+test_2y (_mm512_maskz_getmant_round_ps, __m512, __mmask16, __m512, 1, 1, 8)
+test_2 (_mm512_maskz_permute_pd, __m512d, __mmask8, __m512d, 1)
+test_2 (_mm512_maskz_permute_ps, __m512, __mmask16, __m512, 1)
+test_2 (_mm512_maskz_permutex_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_permutex_pd, __m512d, __mmask8, __m512d, 1)
+test_2 (_mm512_maskz_rol_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_rol_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_ror_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_ror_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_shuffle_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_slli_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_slli_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_sqrt_round_pd, __m512d, __mmask8, __m512d, 9)
+test_2 (_mm512_maskz_sqrt_round_ps, __m512, __mmask16, __m512, 9)
+test_2 (_mm512_maskz_srai_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_srai_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_maskz_srli_epi32, __m512i, __mmask16, __m512i, 1)
+test_2 (_mm512_maskz_srli_epi64, __m512i, __mmask8, __m512i, 1)
+test_2 (_mm512_max_round_pd, __m512d, __m512d, __m512d, 8)
+test_2 (_mm512_max_round_ps, __m512, __m512, __m512, 8)
+test_2 (_mm512_min_round_pd, __m512d, __m512d, __m512d, 8)
+test_2 (_mm512_min_round_ps, __m512, __m512, __m512, 8)
+test_2 (_mm512_mul_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_mul_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm512_scalef_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_scalef_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm512_shuffle_f32x4, __m512, __m512, __m512, 1)
+test_2 (_mm512_shuffle_f64x2, __m512d, __m512d, __m512d, 1)
+test_2 (_mm512_shuffle_i32x4, __m512i, __m512i, __m512i, 1)
+test_2 (_mm512_shuffle_i64x2, __m512i, __m512i, __m512i, 1)
+test_2 (_mm512_shuffle_pd, __m512d, __m512d, __m512d, 1)
+test_2 (_mm512_shuffle_ps, __m512, __m512, __m512, 1)
+test_2 (_mm512_sub_round_pd, __m512d, __m512d, __m512d, 9)
+test_2 (_mm512_sub_round_ps, __m512, __m512, __m512, 9)
+test_2 (_mm_cmp_sd_mask, __mmask8, __m128d, __m128d, 1)
+test_2 (_mm_cmp_ss_mask, __mmask8, __m128, __m128, 1)
+#ifdef __x86_64__
+test_2 (_mm_cvt_roundi64_sd, __m128d, __m128d, long long, 9)
+test_2 (_mm_cvt_roundi64_ss, __m128, __m128, long long, 9)
+#endif
+test_2 (_mm_cvt_roundu32_ss, __m128, __m128, unsigned, 9)
+#ifdef __x86_64__
+test_2 (_mm_cvt_roundu64_sd, __m128d, __m128d, unsigned long long, 9)
+test_2 (_mm_cvt_roundu64_ss, __m128, __m128, unsigned long long, 9)
+#endif
+test_2x (_mm512_cmp_round_pd_mask, __mmask8, __m512d, __m512d, 1, 8)
+test_2x (_mm512_cmp_round_ps_mask, __mmask16, __m512, __m512, 1, 8)
+test_2x (_mm512_maskz_roundscale_round_pd, __m512d, __mmask8, __m512d, 1, 8)
+test_2x (_mm512_maskz_roundscale_round_ps, __m512, __mmask16, __m512, 1, 8)
+test_2x (_mm_cmp_round_sd_mask, __mmask8, __m128d, __m128d, 1, 8)
+test_2x (_mm_cmp_round_ss_mask, __mmask8, __m128, __m128, 1, 8)
+test_2x (_mm_comi_round_sd, int, __m128d, __m128d, 1, 8)
+test_2x (_mm_comi_round_ss, int, __m128, __m128, 1, 8)
+test_3 (_mm512_fmadd_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fmadd_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fmaddsub_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fmaddsub_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fmsub_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fmsub_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fmsubadd_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fmsubadd_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fnmadd_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fnmadd_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_fnmsub_round_pd, __m512d, __m512d, __m512d, __m512d, 9)
+test_3 (_mm512_fnmsub_round_ps, __m512, __m512, __m512, __m512, 9)
+test_3 (_mm512_mask_cmp_epi32_mask, __mmask16, __mmask16, __m512i, __m512i, 1)
+test_3 (_mm512_mask_cmp_epi64_mask, __mmask8, __mmask8, __m512i, __m512i, 1)
+test_3 (_mm512_mask_cmp_epu32_mask, __mmask16, __mmask16, __m512i, __m512i, 1)
+test_3 (_mm512_mask_cmp_epu64_mask, __mmask8, __mmask8, __m512i, __m512i, 1)
+test_3 (_mm512_mask_cmp_pd_mask, __mmask8, __mmask8, __m512d, __m512d, 1)
+test_3 (_mm512_mask_cmp_ps_mask, __mmask16, __mmask16, __m512, __m512, 1)
+test_3 (_mm512_mask_cvt_roundepi32_ps, __m512, __m512, __mmask16, __m512i, 9)
+test_3 (_mm512_mask_cvt_roundepu32_ps, __m512, __m512, __mmask16, __m512i, 9)
+test_3 (_mm512_mask_cvt_roundpd_epi32, __m256i, __m256i, __mmask8, __m512d, 9)
+test_3 (_mm512_mask_cvt_roundpd_epu32, __m256i, __m256i, __mmask8, __m512d, 9)
+test_3 (_mm512_mask_cvt_roundpd_ps, __m256, __m256, __mmask8, __m512d, 9)
+test_3 (_mm512_mask_cvt_roundph_ps, __m512, __m512, __mmask16, __m256i, 8)
+test_3 (_mm512_mask_cvt_roundps_epi32, __m512i, __m512i, __mmask16, __m512, 9)
+test_3 (_mm512_mask_cvt_roundps_epu32, __m512i, __m512i, __mmask16, __m512, 9)
+test_3 (_mm512_mask_cvt_roundps_pd, __m512d, __m512d, __mmask8, __m256, 8)
+test_3 (_mm512_mask_cvtps_ph, __m256i, __m256i, __mmask16, __m512, 1)
+test_3 (_mm512_mask_cvtt_roundpd_epi32, __m256i, __m256i, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_cvtt_roundpd_epu32, __m256i, __m256i, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_cvtt_roundps_epi32, __m512i, __m512i, __mmask16, __m512, 8)
+test_3 (_mm512_mask_cvtt_roundps_epu32, __m512i, __m512i, __mmask16, __m512, 8)
+test_3 (_mm512_mask_extractf32x4_ps, __m128, __m128, __mmask8, __m512, 1)
+test_3 (_mm512_mask_extractf64x4_pd, __m256d, __m256d, __mmask8, __m512d, 1)
+test_3 (_mm512_mask_extracti32x4_epi32, __m128i, __m128i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_extracti64x4_epi64, __m256i, __m256i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_getexp_round_pd, __m512d, __m512d, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_getexp_round_ps, __m512, __m512, __mmask16, __m512, 8)
+test_3y (_mm512_mask_getmant_round_pd, __m512d, __m512d, __mmask8, __m512d, 1, 1, 8)
+test_3y (_mm512_mask_getmant_round_ps, __m512, __m512, __mmask16, __m512, 1, 1, 8)
+test_3 (_mm512_mask_permute_pd, __m512d, __m512d, __mmask8, __m512d, 1)
+test_3 (_mm512_mask_permute_ps, __m512, __m512, __mmask16, __m512, 1)
+test_3 (_mm512_mask_permutex_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_permutex_pd, __m512d, __m512d, __mmask8, __m512d, 1)
+test_3 (_mm512_mask_rol_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_rol_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_ror_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_ror_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_shuffle_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_slli_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_slli_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_sqrt_round_pd, __m512d, __m512d, __mmask8, __m512d, 9)
+test_3 (_mm512_mask_sqrt_round_ps, __m512, __m512, __mmask16, __m512, 9)
+test_3 (_mm512_mask_srai_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_srai_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_mask_srli_epi32, __m512i, __m512i, __mmask16, __m512i, 1)
+test_3 (_mm512_mask_srli_epi64, __m512i, __m512i, __mmask8, __m512i, 1)
+test_3 (_mm512_maskz_add_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_add_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_maskz_alignr_epi32, __m512i, __mmask16, __m512i, __m512i, 1)
+test_3 (_mm512_maskz_alignr_epi64, __m512i, __mmask8, __m512i, __m512i, 1)
+test_3 (_mm512_maskz_div_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_div_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_maskz_insertf32x4, __m512, __mmask16, __m512, __m128, 1)
+test_3 (_mm512_maskz_insertf64x4, __m512d, __mmask8, __m512d, __m256d, 1)
+test_3 (_mm512_maskz_inserti32x4, __m512i, __mmask16, __m512i, __m128i, 1)
+test_3 (_mm512_maskz_inserti64x4, __m512i, __mmask8, __m512i, __m256i, 1)
+test_3 (_mm512_maskz_max_round_pd, __m512d, __mmask8, __m512d, __m512d, 8)
+test_3 (_mm512_maskz_max_round_ps, __m512, __mmask16, __m512, __m512, 8)
+test_3 (_mm512_maskz_min_round_pd, __m512d, __mmask8, __m512d, __m512d, 8)
+test_3 (_mm512_maskz_min_round_ps, __m512, __mmask16, __m512, __m512, 8)
+test_3 (_mm512_maskz_mul_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_mul_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_maskz_scalef_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_scalef_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_maskz_shuffle_f32x4, __m512, __mmask16, __m512, __m512, 1)
+test_3 (_mm512_maskz_shuffle_f64x2, __m512d, __mmask8, __m512d, __m512d, 1)
+test_3 (_mm512_maskz_shuffle_i32x4, __m512i, __mmask16, __m512i, __m512i, 1)
+test_3 (_mm512_maskz_shuffle_i64x2, __m512i, __mmask8, __m512i, __m512i, 1)
+test_3 (_mm512_maskz_shuffle_pd, __m512d, __mmask8, __m512d, __m512d, 1)
+test_3 (_mm512_maskz_shuffle_ps, __m512, __mmask16, __m512, __m512, 1)
+test_3 (_mm512_maskz_sub_round_pd, __m512d, __mmask8, __m512d, __m512d, 9)
+test_3 (_mm512_maskz_sub_round_ps, __m512, __mmask16, __m512, __m512, 9)
+test_3 (_mm512_ternarylogic_epi32, __m512i, __m512i, __m512i, __m512i, 1)
+test_3 (_mm512_ternarylogic_epi64, __m512i, __m512i, __m512i, __m512i, 1)
+test_3 (_mm_mask_cmp_sd_mask, __mmask8, __mmask8, __m128d, __m128d, 1)
+test_3 (_mm_mask_cmp_ss_mask, __mmask8, __mmask8, __m128, __m128, 1)
+test_3v (_mm512_i32scatter_epi32, void *, __m512i, __m512i, 1)
+test_3v (_mm512_i32scatter_epi64, void *, __m256i, __m512i, 1)
+test_3v (_mm512_i32scatter_pd, void *, __m256i, __m512d, 1)
+test_3v (_mm512_i32scatter_ps, void *, __m512i, __m512, 1)
+test_3v (_mm512_i64scatter_epi32, void *, __m512i, __m256i, 1)
+test_3v (_mm512_i64scatter_epi64, void *, __m512i, __m512i, 1)
+test_3v (_mm512_i64scatter_pd, void *, __m512i, __m512d, 1)
+test_3v (_mm512_i64scatter_ps, void *, __m512i, __m256, 1)
+test_3x (_mm512_mask_roundscale_round_pd, __m512d, __m512d, __mmask8, __m512d, 1, 8)
+test_3x (_mm512_mask_roundscale_round_ps, __m512, __m512, __mmask16, __m512, 1, 8)
+test_3x (_mm512_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m512d, __m512d, 1, 8)
+test_3x (_mm512_mask_cmp_round_ps_mask, __mmask16, __mmask16, __m512, __m512, 1, 8)
+test_3x (_mm_fixupimm_round_sd, __m128d, __m128d, __m128d, __m128i, 1, 8)
+test_3x (_mm_fixupimm_round_ss, __m128, __m128, __m128, __m128i, 1, 8)
+test_3x (_mm_mask_cmp_round_sd_mask, __mmask8, __mmask8, __m128d, __m128d, 1, 8)
+test_3x (_mm_mask_cmp_round_ss_mask, __mmask8, __mmask8, __m128, __m128, 1, 8)
+test_4 (_mm512_mask3_fmadd_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fmadd_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fmaddsub_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fmaddsub_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fmsub_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fmsub_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fmsubadd_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fmsubadd_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fnmadd_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fnmadd_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask3_fnmsub_round_pd, __m512d, __m512d, __m512d, __m512d, __mmask8, 9)
+test_4 (_mm512_mask3_fnmsub_round_ps, __m512, __m512, __m512, __m512, __mmask16, 9)
+test_4 (_mm512_mask_add_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_add_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_alignr_epi32, __m512i, __m512i, __mmask16, __m512i, __m512i, 1)
+test_4 (_mm512_mask_alignr_epi64, __m512i, __m512i, __mmask8, __m512i, __m512i, 1)
+test_4 (_mm512_mask_div_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_div_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fmadd_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fmadd_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fmaddsub_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fmaddsub_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fmsub_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fmsub_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fmsubadd_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fmsubadd_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fnmadd_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fnmadd_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_fnmsub_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_fnmsub_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_i32gather_epi32, __m512i, __m512i, __mmask16, __m512i, void const *, 1)
+test_4 (_mm512_mask_i32gather_epi64, __m512i, __m512i, __mmask8, __m256i, void const *, 1)
+test_4 (_mm512_mask_i32gather_pd, __m512d, __m512d, __mmask8, __m256i, void const *, 1)
+test_4 (_mm512_mask_i32gather_ps, __m512, __m512, __mmask16, __m512i, void const *, 1)
+test_4 (_mm512_mask_i64gather_epi32, __m256i, __m256i, __mmask8, __m512i, void const *, 1)
+test_4 (_mm512_mask_i64gather_epi64, __m512i, __m512i, __mmask8, __m512i, void const *, 1)
+test_4 (_mm512_mask_i64gather_pd, __m512d, __m512d, __mmask8, __m512i, void const *, 1)
+test_4 (_mm512_mask_i64gather_ps, __m256, __m256, __mmask8, __m512i, void const *, 1)
+test_4 (_mm512_mask_insertf32x4, __m512, __m512, __mmask16, __m512, __m128, 1)
+test_4 (_mm512_mask_insertf64x4, __m512d, __m512d, __mmask8, __m512d, __m256d, 1)
+test_4 (_mm512_mask_inserti32x4, __m512i, __m512i, __mmask16, __m512i, __m128i, 1)
+test_4 (_mm512_mask_inserti64x4, __m512i, __m512i, __mmask8, __m512i, __m256i, 1)
+test_4 (_mm512_mask_max_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 8)
+test_4 (_mm512_mask_max_round_ps, __m512, __m512, __mmask16, __m512, __m512, 8)
+test_4 (_mm512_mask_min_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 8)
+test_4 (_mm512_mask_min_round_ps, __m512, __m512, __mmask16, __m512, __m512, 8)
+test_4 (_mm512_mask_mul_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_mul_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_scalef_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_scalef_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_shuffle_f32x4, __m512, __m512, __mmask16, __m512, __m512, 1)
+test_4 (_mm512_mask_shuffle_f64x2, __m512d, __m512d, __mmask8, __m512d, __m512d, 1)
+test_4 (_mm512_mask_shuffle_i32x4, __m512i, __m512i, __mmask16, __m512i, __m512i, 1)
+test_4 (_mm512_mask_shuffle_i64x2, __m512i, __m512i, __mmask8, __m512i, __m512i, 1)
+test_4 (_mm512_mask_shuffle_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 1)
+test_4 (_mm512_mask_shuffle_ps, __m512, __m512, __mmask16, __m512, __m512, 1)
+test_4 (_mm512_mask_sub_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512d, 9)
+test_4 (_mm512_mask_sub_round_ps, __m512, __m512, __mmask16, __m512, __m512, 9)
+test_4 (_mm512_mask_ternarylogic_epi32, __m512i, __m512i, __mmask16, __m512i, __m512i, 1)
+test_4 (_mm512_mask_ternarylogic_epi64, __m512i, __m512i, __mmask8, __m512i, __m512i, 1)
+test_4 (_mm512_maskz_fmadd_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fmadd_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fmaddsub_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fmaddsub_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fmsub_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fmsub_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fmsubadd_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fmsubadd_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fnmadd_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fnmadd_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_fnmsub_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512d, 9)
+test_4 (_mm512_maskz_fnmsub_round_ps, __m512, __mmask16, __m512, __m512, __m512, 9)
+test_4 (_mm512_maskz_ternarylogic_epi32, __m512i, __mmask16, __m512i, __m512i, __m512i, 1)
+test_4 (_mm512_maskz_ternarylogic_epi64, __m512i, __mmask8, __m512i, __m512i, __m512i, 1)
+test_4v (_mm512_mask_i32scatter_epi32, void *, __mmask16, __m512i, __m512i, 1)
+test_4v (_mm512_mask_i32scatter_epi64, void *, __mmask8, __m256i, __m512i, 1)
+test_4v (_mm512_mask_i32scatter_pd, void *, __mmask8, __m256i, __m512d, 1)
+test_4v (_mm512_mask_i32scatter_ps, void *, __mmask16, __m512i, __m512, 1)
+test_4v (_mm512_mask_i64scatter_epi32, void *, __mmask8, __m512i, __m256i, 1)
+test_4v (_mm512_mask_i64scatter_epi64, void *, __mmask8, __m512i, __m512i, 1)
+test_4v (_mm512_mask_i64scatter_pd, void *, __mmask8, __m512i, __m512d, 1)
+test_4v (_mm512_mask_i64scatter_ps, void *, __mmask8, __m512i, __m256, 1)
+test_4x (_mm512_mask_fixupimm_round_pd, __m512d, __m512d, __mmask8, __m512d, __m512i, 1, 8)
+test_4x (_mm512_mask_fixupimm_round_ps, __m512, __m512, __mmask16, __m512, __m512i, 1, 8)
+test_4x (_mm512_maskz_fixupimm_round_pd, __m512d, __mmask8, __m512d, __m512d, __m512i, 1, 8)
+test_4x (_mm512_maskz_fixupimm_round_ps, __m512, __mmask16, __m512, __m512, __m512i, 1, 8)
+test_4x (_mm_mask_fixupimm_round_sd, __m128d, __m128d, __mmask8, __m128d, __m128i, 1, 8)
+test_4x (_mm_mask_fixupimm_round_ss, __m128, __m128, __mmask8, __m128, __m128i, 1, 8)
+test_4x (_mm_maskz_fixupimm_round_sd, __m128d, __mmask8, __m128d, __m128d, __m128i, 1, 8)
+test_4x (_mm_maskz_fixupimm_round_ss, __m128, __mmask8, __m128, __m128, __m128i, 1, 8)
+
+/* avx512pfintrin.h */
+test_3vx (_mm512_mask_prefetch_i32gather_ps, __m512i, __mmask16, void const *, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i32scatter_ps, void const *, __mmask16, __m512i, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i64gather_ps, __m512i, __mmask8, void const *, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i64scatter_ps, void const *, __mmask8, __m512i, 1, _MM_HINT_T0)
+
+test_3vx (_mm512_mask_prefetch_i32gather_pd, __m256i, __mmask8, void const *, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i32scatter_pd, void const *, __mmask8, __m256i, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i64gather_pd, __m512i, __mmask8, long long *, 1, _MM_HINT_T0)
+test_3vx (_mm512_mask_prefetch_i64scatter_pd, void const *, __mmask8, __m512i, 1, _MM_HINT_T0)
+
+/* avx512erintrin.h */
+test_1 (_mm512_exp2a23_round_pd, __m512d, __m512d, 8)
+test_1 (_mm512_exp2a23_round_ps, __m512, __m512, 8)
+test_1 (_mm512_rcp28_round_pd, __m512d, __m512d, 8)
+test_1 (_mm512_rcp28_round_ps, __m512, __m512, 8)
+test_1 (_mm512_rsqrt28_round_pd, __m512d, __m512d, 8)
+test_1 (_mm512_rsqrt28_round_ps, __m512, __m512, 8)
+test_2 (_mm512_maskz_exp2a23_round_pd, __m512d, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_exp2a23_round_ps, __m512, __mmask16, __m512, 8)
+test_2 (_mm512_maskz_rcp28_round_pd, __m512d, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_rcp28_round_ps, __m512, __mmask16, __m512, 8)
+test_2 (_mm512_maskz_rsqrt28_round_pd, __m512d, __mmask8, __m512d, 8)
+test_2 (_mm512_maskz_rsqrt28_round_ps, __m512, __mmask16, __m512, 8)
+test_3 (_mm512_mask_exp2a23_round_pd, __m512d, __m512d, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_exp2a23_round_ps, __m512, __m512, __mmask16, __m512, 8)
+test_3 (_mm512_mask_rcp28_round_pd, __m512d, __m512d, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_rcp28_round_ps, __m512, __m512, __mmask16, __m512, 8)
+test_3 (_mm512_mask_rsqrt28_round_pd, __m512d, __m512d, __mmask8, __m512d, 8)
+test_3 (_mm512_mask_rsqrt28_round_ps, __m512, __m512, __mmask16, __m512, 8)
+test_2 (_mm_rcp28_round_sd, __m128d, __m128d, __m128d, 8)
+test_2 (_mm_rcp28_round_ss, __m128, __m128, __m128, 8)
+test_2 (_mm_rsqrt28_round_sd, __m128d, __m128d, __m128d, 8)
+test_2 (_mm_rsqrt28_round_ss, __m128, __m128, __m128, 8)
+
+/* shaintrin.h */
+test_2 (_mm_sha1rnds4_epu32, __m128i, __m128i, __m128i, 1)
+
+/* wmmintrin.h (AES/PCLMUL).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("aes,pclmul")
+#endif
+#include <wmmintrin.h>
+test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
+test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
+
+/* popcnintrin.h (POPCNT).  */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("popcnt")
+#endif
+#include <popcntintrin.h>
+
+/* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */
+#ifdef DIFFERENT_PRAGMAS
+#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw,adx,fxsr,xsaveopt")
+#endif
+#include <x86intrin.h>
+/* xopintrin.h */
+test_1 ( _mm_roti_epi8, __m128i, __m128i, 1)
+test_1 ( _mm_roti_epi16, __m128i, __m128i, 1)
+test_1 ( _mm_roti_epi32, __m128i, __m128i, 1)
+test_1 ( _mm_roti_epi64, __m128i, __m128i, 1)
+test_3 (_mm_permute2_pd, __m128d, __m128d, __m128d, __m128d, 1)
+test_3 (_mm256_permute2_pd, __m256d, __m256d, __m256d, __m256d, 1)
+test_3 (_mm_permute2_ps, __m128, __m128, __m128, __m128, 1)
+test_3 (_mm256_permute2_ps, __m256, __m256, __m256, __m256, 1)
+
+/* lwpintrin.h */
+test_2 ( __lwpval32, void, unsigned int, unsigned int, 1)
+test_2 ( __lwpins32, unsigned char, unsigned int, unsigned int, 1)
+#ifdef __x86_64__
+test_2 ( __lwpval64, void, unsigned long long, unsigned int, 1)
+test_2 ( __lwpins64, unsigned char, unsigned long long, unsigned int, 1)
+#endif
+
+/* tbmintrin.h */
+test_1 ( __bextri_u32, unsigned int, unsigned int, 1)
+#ifdef __x86_64__
+test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1)
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-22a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-22a.c
new file mode 100644
index 000000000..688908f9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-22a.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8" } */
+
+#define DIFFERENT_PRAGMAS
+
+#include "sse-22.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-23.c
new file mode 100644
index 000000000..d227babb8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -0,0 +1,392 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8" } */
+
+#include <mm_malloc.h>
+
+/* Test that the intrinsics compile with optimization.  All of them
+   are defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h,
+   mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h,
+   tbmintrin.h, lwpintrin.h, popcntintrin.h, fmaintrin.h and mm_malloc.h 
+   that reference the proper builtin functions.
+
+   Defining away "extern" and "__inline" results in all of them being
+   compiled as proper functions.  */
+
+#define extern
+#define __inline
+
+/* Following intrinsics require immediate arguments. */
+
+/* ammintrin.h */
+#define __builtin_ia32_extrqi(X, I, L)  __builtin_ia32_extrqi(X, 1, 1)
+#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1)
+
+/* wmmintrin.h */
+#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1)
+#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1)
+
+/* smmintrin.h */
+#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1)
+#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1)
+#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1)
+#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1)
+
+#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1)
+#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1)
+#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1)
+#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1)
+#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1)
+#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1)
+#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1)
+#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1)
+#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1)
+#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1)
+#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1)
+#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1)
+#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1)
+#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1)
+#define __builtin_ia32_pcmpistrm128(X, Y, M) \
+  __builtin_ia32_pcmpistrm128(X, Y, 1)
+#define __builtin_ia32_pcmpistri128(X, Y, M) \
+  __builtin_ia32_pcmpistri128(X, Y, 1)
+#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpistria128(X, Y, M) \
+  __builtin_ia32_pcmpistria128(X, Y, 1)
+#define __builtin_ia32_pcmpistric128(X, Y, M) \
+  __builtin_ia32_pcmpistric128(X, Y, 1)
+#define __builtin_ia32_pcmpistrio128(X, Y, M) \
+  __builtin_ia32_pcmpistrio128(X, Y, 1)
+#define __builtin_ia32_pcmpistris128(X, Y, M) \
+  __builtin_ia32_pcmpistris128(X, Y, 1)
+#define __builtin_ia32_pcmpistriz128(X, Y, M) \
+  __builtin_ia32_pcmpistriz128(X, Y, 1)
+#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1)
+#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \
+  __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1)
+
+/* tmmintrin.h */
+#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8)
+#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8)
+
+/* emmintrin.h */
+#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8)
+#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8)
+#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0)
+#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0)
+#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0)
+#define __builtin_ia32_vec_set_v8hi(A, D, N) \
+  __builtin_ia32_vec_set_v8hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0)
+#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
+
+/* xmmintrin.h */
+#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, 0, _MM_HINT_NTA)
+#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
+#define __builtin_ia32_vec_set_v4hi(A, D, N) \
+  __builtin_ia32_vec_set_v4hi(A, D, 0)
+#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
+#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
+
+/* immintrin.h */
+#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1)
+#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1)
+#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1)
+#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1)
+#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1)
+#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1)
+#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1)
+#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1)
+#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1)
+#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1)
+#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1)
+#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1)
+#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1)
+#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1)
+#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1)
+#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1)
+#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1)
+#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1)
+#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1)
+#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1)
+#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1)
+#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1)
+#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1)
+#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
+#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
+#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
+#define __builtin_ia32_vcvtps2ph(A, I) __builtin_ia32_vcvtps2ph(A, 1)
+#define __builtin_ia32_vcvtps2ph256(A, I) __builtin_ia32_vcvtps2ph256(A, 1)
+
+/* xopintrin.h */
+#define __builtin_ia32_vprotbi(A, B) __builtin_ia32_vprotbi(A,1)
+#define __builtin_ia32_vprotwi(A, B) __builtin_ia32_vprotwi(A,1)
+#define __builtin_ia32_vprotdi(A, B) __builtin_ia32_vprotdi(A,1)
+#define __builtin_ia32_vprotqi(A, B) __builtin_ia32_vprotqi(A,1)
+
+/* lwpintrin.h */
+#define __builtin_ia32_lwpval32(D2, D1, F) __builtin_ia32_lwpval32 (D2, D1, 1)
+#define __builtin_ia32_lwpval64(D2, D1, F) __builtin_ia32_lwpval64 (D2, D1, 1)
+#define __builtin_ia32_lwpins32(D2, D1, F) __builtin_ia32_lwpins32 (D2, D1, 1)
+#define __builtin_ia32_lwpins64(D2, D1, F) __builtin_ia32_lwpins64 (D2, D1, 1)
+
+/* tbmintrin.h */
+#define __builtin_ia32_bextri_u32(X, Y) __builtin_ia32_bextr_u32 (X, 1)
+#define __builtin_ia32_bextri_u64(X, Y) __builtin_ia32_bextr_u64 (X, 1)
+
+/* avx2intrin.h */
+#define __builtin_ia32_mpsadbw256(X, Y, Z) __builtin_ia32_mpsadbw256 (X, Y, 1)
+#define __builtin_ia32_palignr256(X, Y, Z) __builtin_ia32_palignr256 (X, Y, 8)
+#define __builtin_ia32_pblendw256(X, Y, Z) __builtin_ia32_pblendw256 (X, Y, 1)
+#define __builtin_ia32_pshufd256(X, Y) __builtin_ia32_pshufd256(X, 1)
+#define __builtin_ia32_pshufhw256(X, Y) __builtin_ia32_pshufhw256(X, 1)
+#define __builtin_ia32_pshuflw256(X, Y) __builtin_ia32_pshuflw256(X, 1)
+#define __builtin_ia32_pslldqi256(X, Y) __builtin_ia32_pslldqi256(X, 8)
+#define __builtin_ia32_psrldqi256(X, Y) __builtin_ia32_psrldqi256(X, 8)
+#define __builtin_ia32_pblendd128(X, Y, Z) __builtin_ia32_pblendd128(X, Y, 1)
+#define __builtin_ia32_pblendd256(X, Y, Z) __builtin_ia32_pblendd256(X, Y, 1)
+#define __builtin_ia32_permdf256(X, Y) __builtin_ia32_permdf256(X, 1)
+#define __builtin_ia32_permdi256(X, Y) __builtin_ia32_permdi256(X, 1)
+#define __builtin_ia32_permti256(X, Y, Z) __builtin_ia32_permti256(X, Y, 1)
+#define __builtin_ia32_extract128i256(X, Y) __builtin_ia32_extract128i256(X, 1)
+#define __builtin_ia32_insert128i256(X, Y, Z) __builtin_ia32_insert128i256(X, Y, 1)
+#define __builtin_ia32_gathersiv2df(X, Y, Z, K, M) __builtin_ia32_gathersiv2df(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv4df(X, Y, Z, K, M) __builtin_ia32_gathersiv4df(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv2df(X, Y, Z, K, M) __builtin_ia32_gatherdiv2df(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4df(X, Y, Z, K, M) __builtin_ia32_gatherdiv4df(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv4sf(X, Y, Z, K, M) __builtin_ia32_gathersiv4sf(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv8sf(X, Y, Z, K, M) __builtin_ia32_gathersiv8sf(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4sf(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4sf256(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv2di(X, Y, Z, K, M) __builtin_ia32_gathersiv2di(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv4di(X, Y, Z, K, M) __builtin_ia32_gathersiv4di(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv2di(X, Y, Z, K, M) __builtin_ia32_gatherdiv2di(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4di(X, Y, Z, K, M) __builtin_ia32_gatherdiv4di(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv4si(X, Y, Z, K, M) __builtin_ia32_gathersiv4si(X, Y, Z, K, 1)
+#define __builtin_ia32_gathersiv8si(X, Y, Z, K, M) __builtin_ia32_gathersiv8si(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4si(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si(X, Y, Z, K, 1)
+#define __builtin_ia32_gatherdiv4si256(X, Y, Z, K, M) __builtin_ia32_gatherdiv4si256(X, Y, Z, K, 1)
+
+/* rtmintrin.h */
+#define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1)
+
+/* avx512fintrin.h */
+#define __builtin_ia32_addpd512_mask(A, B, C, D, E) __builtin_ia32_addpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_addps512_mask(A, B, C, D, E) __builtin_ia32_addps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_addsd_round(A, B, C) __builtin_ia32_addsd_round(A, B, 8)
+#define __builtin_ia32_addss_round(A, B, C) __builtin_ia32_addss_round(A, B, 8)
+#define __builtin_ia32_alignd512_mask(A, B, F, D, E) __builtin_ia32_alignd512_mask(A, B, 1, D, E)
+#define __builtin_ia32_alignq512_mask(A, B, F, D, E) __builtin_ia32_alignq512_mask(A, B, 1, D, E)
+#define __builtin_ia32_cmpd512_mask(A, B, E, D) __builtin_ia32_cmpd512_mask(A, B, 1, D)
+#define __builtin_ia32_cmppd512_mask(A, B, F, D, E) __builtin_ia32_cmppd512_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpps512_mask(A, B, F, D, E) __builtin_ia32_cmpps512_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpq512_mask(A, B, E, D) __builtin_ia32_cmpq512_mask(A, B, 1, D)
+#define __builtin_ia32_cmpsd_mask(A, B, F, D, E) __builtin_ia32_cmpsd_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cmpss_mask(A, B, F, D, E) __builtin_ia32_cmpss_mask(A, B, 1, D, 8)
+#define __builtin_ia32_cvtdq2ps512_mask(A, B, C, D) __builtin_ia32_cvtdq2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2dq512_mask(A, B, C, D) __builtin_ia32_cvtpd2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2ps512_mask(A, B, C, D) __builtin_ia32_cvtpd2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtpd2udq512_mask(A, B, C, D) __builtin_ia32_cvtpd2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2dq512_mask(A, B, C, D) __builtin_ia32_cvtps2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2pd512_mask(A, B, C, D) __builtin_ia32_cvtps2pd512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtps2udq512_mask(A, B, C, D) __builtin_ia32_cvtps2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtsd2ss_round(A, B, C) __builtin_ia32_cvtsd2ss_round(A, B, 8)
+#define __builtin_ia32_cvtss2sd_round(A, B, C) __builtin_ia32_cvtss2sd_round(A, B, 4)
+#define __builtin_ia32_cvtsi2sd64(A, B, C) __builtin_ia32_cvtsi2sd64(A, B, 8)
+#define __builtin_ia32_cvtsi2ss32(A, B, C) __builtin_ia32_cvtsi2ss32(A, B, 8)
+#define __builtin_ia32_cvtsi2ss64(A, B, C) __builtin_ia32_cvtsi2ss64(A, B, 8)
+#define __builtin_ia32_cvttpd2dq512_mask(A, B, C, D) __builtin_ia32_cvttpd2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttpd2udq512_mask(A, B, C, D) __builtin_ia32_cvttpd2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttps2dq512_mask(A, B, C, D) __builtin_ia32_cvttps2dq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvttps2udq512_mask(A, B, C, D) __builtin_ia32_cvttps2udq512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtudq2ps512_mask(A, B, C, D) __builtin_ia32_cvtudq2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_cvtusi2sd64(A, B, C) __builtin_ia32_cvtusi2sd64(A, B, 8)
+#define __builtin_ia32_cvtusi2ss32(A, B, C) __builtin_ia32_cvtusi2ss32(A, B, 8)
+#define __builtin_ia32_cvtusi2ss64(A, B, C) __builtin_ia32_cvtusi2ss64(A, B, 8)
+#define __builtin_ia32_divpd512_mask(A, B, C, D, E) __builtin_ia32_divpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_divps512_mask(A, B, C, D, E) __builtin_ia32_divps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_divsd_round(A, B, C) __builtin_ia32_divsd_round(A, B, 8)
+#define __builtin_ia32_divss_round(A, B, C) __builtin_ia32_divss_round(A, B, 8)
+#define __builtin_ia32_extractf32x4_mask(A, E, C, D) __builtin_ia32_extractf32x4_mask(A, 1, C, D)
+#define __builtin_ia32_extractf64x4_mask(A, E, C, D) __builtin_ia32_extractf64x4_mask(A, 1, C, D)
+#define __builtin_ia32_extracti32x4_mask(A, E, C, D) __builtin_ia32_extracti32x4_mask(A, 1, C, D)
+#define __builtin_ia32_extracti64x4_mask(A, E, C, D) __builtin_ia32_extracti64x4_mask(A, 1, C, D)
+#define __builtin_ia32_fixupimmpd512_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmpd512_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmpd512_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmpd512_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmps512_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmps512_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmps512_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmps512_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmsd_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmsd_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmsd_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmsd_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmss_mask(A, B, C, I, E, F) __builtin_ia32_fixupimmss_mask(A, B, C, 1, E, 8)
+#define __builtin_ia32_fixupimmss_maskz(A, B, C, I, E, F) __builtin_ia32_fixupimmss_maskz(A, B, C, 1, E, 8)
+#define __builtin_ia32_gatherdiv8df(A, B, C, D, F) __builtin_ia32_gatherdiv8df(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv8di(A, B, C, D, F) __builtin_ia32_gatherdiv8di(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv16sf(A, B, C, D, F) __builtin_ia32_gatherdiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_gatherdiv16si(A, B, C, D, F) __builtin_ia32_gatherdiv16si(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv16sf(A, B, C, D, F) __builtin_ia32_gathersiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv16si(A, B, C, D, F) __builtin_ia32_gathersiv16si(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv8df(A, B, C, D, F) __builtin_ia32_gathersiv8df(A, B, C, D, 8)
+#define __builtin_ia32_gathersiv8di(A, B, C, D, F) __builtin_ia32_gathersiv8di(A, B, C, D, 8)
+#define __builtin_ia32_getexppd512_mask(A, B, C, D) __builtin_ia32_getexppd512_mask(A, B, C, 8)
+#define __builtin_ia32_getexpps512_mask(A, B, C, D) __builtin_ia32_getexpps512_mask(A, B, C, 8)
+#define __builtin_ia32_getexpsd128_round(A, B, C) __builtin_ia32_getexpsd128_round(A, B, 4)
+#define __builtin_ia32_getexpss128_round(A, B, C) __builtin_ia32_getexpss128_round(A, B, 4)
+#define __builtin_ia32_getmantpd512_mask(A, F, C, D, E) __builtin_ia32_getmantpd512_mask(A, 1, C, D, 8)
+#define __builtin_ia32_getmantps512_mask(A, F, C, D, E) __builtin_ia32_getmantps512_mask(A, 1, C, D, 8)
+#define __builtin_ia32_getmantsd_round(A, B, C, D) __builtin_ia32_getmantsd_round(A, B, 1, 4)
+#define __builtin_ia32_getmantss_round(A, B, C, D) __builtin_ia32_getmantss_round(A, B, 1, 4)
+#define __builtin_ia32_insertf32x4_mask(A, B, F, D, E) __builtin_ia32_insertf32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_insertf64x4_mask(A, B, F, D, E) __builtin_ia32_insertf64x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_inserti32x4_mask(A, B, F, D, E) __builtin_ia32_inserti32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_inserti64x4_mask(A, B, F, D, E) __builtin_ia32_inserti64x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_maxpd512_mask(A, B, C, D, E) __builtin_ia32_maxpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_maxps512_mask(A, B, C, D, E) __builtin_ia32_maxps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_maxsd_round(A, B, C) __builtin_ia32_maxsd_round(A, B, 4)
+#define __builtin_ia32_maxss_round(A, B, C) __builtin_ia32_maxss_round(A, B, 4)
+#define __builtin_ia32_minpd512_mask(A, B, C, D, E) __builtin_ia32_minpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_minps512_mask(A, B, C, D, E) __builtin_ia32_minps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_minsd_round(A, B, C) __builtin_ia32_minsd_round(A, B, 4)
+#define __builtin_ia32_minss_round(A, B, C) __builtin_ia32_minss_round(A, B, 4)
+#define __builtin_ia32_mulpd512_mask(A, B, C, D, E) __builtin_ia32_mulpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_mulps512_mask(A, B, C, D, E) __builtin_ia32_mulps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_mulsd_round(A, B, C) __builtin_ia32_mulsd_round(A, B, 8)
+#define __builtin_ia32_mulss_round(A, B, C) __builtin_ia32_mulss_round(A, B, 8)
+#define __builtin_ia32_permdf512_mask(A, E, C, D) __builtin_ia32_permdf512_mask(A, 1, C, D)
+#define __builtin_ia32_permdi512_mask(A, E, C, D) __builtin_ia32_permdi512_mask(A, 1, C, D)
+#define __builtin_ia32_prold512_mask(A, E, C, D) __builtin_ia32_prold512_mask(A, 1, C, D)
+#define __builtin_ia32_prolq512_mask(A, E, C, D) __builtin_ia32_prolq512_mask(A, 1, C, D)
+#define __builtin_ia32_prord512_mask(A, E, C, D) __builtin_ia32_prord512_mask(A, 1, C, D)
+#define __builtin_ia32_prorq512_mask(A, E, C, D) __builtin_ia32_prorq512_mask(A, 1, C, D)
+#define __builtin_ia32_pshufd512_mask(A, E, C, D) __builtin_ia32_pshufd512_mask(A, 1, C, D)
+#define __builtin_ia32_pslldi512_mask(A, E, C, D) __builtin_ia32_pslldi512_mask(A, 1, C, D)
+#define __builtin_ia32_psllqi512_mask(A, E, C, D) __builtin_ia32_psllqi512_mask(A, 1, C, D)
+#define __builtin_ia32_psradi512_mask(A, E, C, D) __builtin_ia32_psradi512_mask(A, 1, C, D)
+#define __builtin_ia32_psraqi512_mask(A, E, C, D) __builtin_ia32_psraqi512_mask(A, 1, C, D)
+#define __builtin_ia32_psrldi512_mask(A, E, C, D) __builtin_ia32_psrldi512_mask(A, 1, C, D)
+#define __builtin_ia32_psrlqi512_mask(A, E, C, D) __builtin_ia32_psrlqi512_mask(A, 1, C, D)
+#define __builtin_ia32_pternlogd512_mask(A, B, C, F, E) __builtin_ia32_pternlogd512_mask(A, B, C, 1, E)
+#define __builtin_ia32_pternlogd512_maskz(A, B, C, F, E) __builtin_ia32_pternlogd512_maskz(A, B, C, 1, E)
+#define __builtin_ia32_pternlogq512_mask(A, B, C, F, E) __builtin_ia32_pternlogq512_mask(A, B, C, 1, E)
+#define __builtin_ia32_pternlogq512_maskz(A, B, C, F, E) __builtin_ia32_pternlogq512_maskz(A, B, C, 1, E)
+#define __builtin_ia32_rndscalepd_mask(A, F, C, D, E) __builtin_ia32_rndscalepd_mask(A, 1, C, D, 8)
+#define __builtin_ia32_rndscaleps_mask(A, F, C, D, E) __builtin_ia32_rndscaleps_mask(A, 1, C, D, 8)
+#define __builtin_ia32_rndscalesd_round(A, B, C, D) __builtin_ia32_rndscalesd_round(A, B, 1, 4)
+#define __builtin_ia32_rndscaless_round(A, B, C, D) __builtin_ia32_rndscaless_round(A, B, 1, 4)
+#define __builtin_ia32_scalefpd512_mask(A, B, C, D, E) __builtin_ia32_scalefpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_scalefps512_mask(A, B, C, D, E) __builtin_ia32_scalefps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_scalefsd_round(A, B, C) __builtin_ia32_scalefsd_round(A, B, 8)
+#define __builtin_ia32_scalefss_round(A, B, C) __builtin_ia32_scalefss_round(A, B, 8)
+#define __builtin_ia32_scatterdiv8df(A, B, C, D, F) __builtin_ia32_scatterdiv8df(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv8di(A, B, C, D, F) __builtin_ia32_scatterdiv8di(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv16sf(A, B, C, D, F) __builtin_ia32_scatterdiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_scatterdiv16si(A, B, C, D, F) __builtin_ia32_scatterdiv16si(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv16sf(A, B, C, D, F) __builtin_ia32_scattersiv16sf(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv16si(A, B, C, D, F) __builtin_ia32_scattersiv16si(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv8df(A, B, C, D, F) __builtin_ia32_scattersiv8df(A, B, C, D, 8)
+#define __builtin_ia32_scattersiv8di(A, B, C, D, F) __builtin_ia32_scattersiv8di(A, B, C, D, 8)
+#define __builtin_ia32_shuf_f32x4_mask(A, B, F, D, E) __builtin_ia32_shuf_f32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_f64x2_mask(A, B, F, D, E) __builtin_ia32_shuf_f64x2_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_i32x4_mask(A, B, F, D, E) __builtin_ia32_shuf_i32x4_mask(A, B, 1, D, E)
+#define __builtin_ia32_shuf_i64x2_mask(A, B, F, D, E) __builtin_ia32_shuf_i64x2_mask(A, B, 1, D, E)
+#define __builtin_ia32_shufpd512_mask(A, B, F, D, E) __builtin_ia32_shufpd512_mask(A, B, 1, D, E)
+#define __builtin_ia32_shufps512_mask(A, B, F, D, E) __builtin_ia32_shufps512_mask(A, B, 1, D, E)
+#define __builtin_ia32_sqrtpd512_mask(A, B, C, D) __builtin_ia32_sqrtpd512_mask(A, B, C, 8)
+#define __builtin_ia32_sqrtps512_mask(A, B, C, D) __builtin_ia32_sqrtps512_mask(A, B, C, 8)
+#define __builtin_ia32_sqrtss_round(A, B, C) __builtin_ia32_sqrtss_round(A, B, 8)
+#define __builtin_ia32_sqrtsd_round(A, B, C) __builtin_ia32_sqrtsd_round(A, B, 8)
+#define __builtin_ia32_subpd512_mask(A, B, C, D, E) __builtin_ia32_subpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_subps512_mask(A, B, C, D, E) __builtin_ia32_subps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_subsd_round(A, B, C) __builtin_ia32_subsd_round(A, B, 8)
+#define __builtin_ia32_subss_round(A, B, C) __builtin_ia32_subss_round(A, B, 8)
+#define __builtin_ia32_ucmpd512_mask(A, B, E, D) __builtin_ia32_ucmpd512_mask(A, B, 1, D)
+#define __builtin_ia32_ucmpq512_mask(A, B, E, D) __builtin_ia32_ucmpq512_mask(A, B, 1, D)
+#define __builtin_ia32_vcomisd(A, B, C, D) __builtin_ia32_vcomisd(A, B, 1, 8)
+#define __builtin_ia32_vcomiss(A, B, C, D) __builtin_ia32_vcomiss(A, B, 1, 8)
+#define __builtin_ia32_vcvtph2ps512_mask(A, B, C, D) __builtin_ia32_vcvtph2ps512_mask(A, B, C, 8)
+#define __builtin_ia32_vcvtps2ph512_mask(A, E, C, D) __builtin_ia32_vcvtps2ph512_mask(A, 1, C, D)
+#define __builtin_ia32_vcvtsd2si32(A, B) __builtin_ia32_vcvtsd2si32(A, 8)
+#define __builtin_ia32_vcvtsd2si64(A, B) __builtin_ia32_vcvtsd2si64(A, 8)
+#define __builtin_ia32_vcvtsd2usi32(A, B) __builtin_ia32_vcvtsd2usi32(A, 8)
+#define __builtin_ia32_vcvtsd2usi64(A, B) __builtin_ia32_vcvtsd2usi64(A, 8)
+#define __builtin_ia32_vcvtss2si32(A, B) __builtin_ia32_vcvtss2si32(A, 8)
+#define __builtin_ia32_vcvtss2si64(A, B) __builtin_ia32_vcvtss2si64(A, 8)
+#define __builtin_ia32_vcvtss2usi32(A, B) __builtin_ia32_vcvtss2usi32(A, 8)
+#define __builtin_ia32_vcvtss2usi64(A, B) __builtin_ia32_vcvtss2usi64(A, 8)
+#define __builtin_ia32_vcvttsd2si32(A, B) __builtin_ia32_vcvttsd2si32(A, 8)
+#define __builtin_ia32_vcvttsd2si64(A, B) __builtin_ia32_vcvttsd2si64(A, 8)
+#define __builtin_ia32_vcvttsd2usi32(A, B) __builtin_ia32_vcvttsd2usi32(A, 8)
+#define __builtin_ia32_vcvttsd2usi64(A, B) __builtin_ia32_vcvttsd2usi64(A, 8)
+#define __builtin_ia32_vcvttss2si32(A, B) __builtin_ia32_vcvttss2si32(A, 8)
+#define __builtin_ia32_vcvttss2si64(A, B) __builtin_ia32_vcvttss2si64(A, 8)
+#define __builtin_ia32_vcvttss2usi32(A, B) __builtin_ia32_vcvttss2usi32(A, 8)
+#define __builtin_ia32_vcvttss2usi64(A, B) __builtin_ia32_vcvttss2usi64(A, 8)
+#define __builtin_ia32_vfmaddpd512_mask(A, B, C, D, E) __builtin_ia32_vfmaddpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddpd512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddpd512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_mask(A, B, C, D, E) __builtin_ia32_vfmaddps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddps512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddps512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsd3_round(A, B, C, D) __builtin_ia32_vfmaddsd3_round(A, B, C, 8)
+#define __builtin_ia32_vfmaddss3_round(A, B, C, D) __builtin_ia32_vfmaddss3_round(A, B, C, 8)
+#define __builtin_ia32_vfmaddsubpd512_mask(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubpd512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddsubpd512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_mask(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmaddsubps512_maskz(A, B, C, D, E) __builtin_ia32_vfmaddsubps512_maskz(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubaddpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubaddpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubaddps512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubaddps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfmsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfmsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddpd512_mask(A, B, C, D, E) __builtin_ia32_vfnmaddpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmaddps512_mask(A, B, C, D, E) __builtin_ia32_vfnmaddps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubpd512_mask(A, B, C, D, E) __builtin_ia32_vfnmsubpd512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubpd512_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubpd512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubps512_mask(A, B, C, D, E) __builtin_ia32_vfnmsubps512_mask(A, B, C, D, 8)
+#define __builtin_ia32_vfnmsubps512_mask3(A, B, C, D, E) __builtin_ia32_vfnmsubps512_mask3(A, B, C, D, 8)
+#define __builtin_ia32_vpermilpd512_mask(A, E, C, D) __builtin_ia32_vpermilpd512_mask(A, 1, C, D)
+#define __builtin_ia32_vpermilps512_mask(A, E, C, D) __builtin_ia32_vpermilps512_mask(A, 1, C, D)
+
+/* avx512pfintrin.h */
+#define __builtin_ia32_gatherpfdps(A, B, C, D, E) __builtin_ia32_gatherpfdps(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_gatherpfqps(A, B, C, D, E) __builtin_ia32_gatherpfqps(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_scatterpfdps(A, B, C, D, E) __builtin_ia32_scatterpfdps(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_scatterpfqps(A, B, C, D, E) __builtin_ia32_scatterpfqps(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_gatherpfdpd(A, B, C, D, E) __builtin_ia32_gatherpfdpd(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_gatherpfqpd(A, B, C, D, E) __builtin_ia32_gatherpfqpd(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_scatterpfdpd(A, B, C, D, E) __builtin_ia32_scatterpfdpd(A, B, C, 1, _MM_HINT_T0)
+#define __builtin_ia32_scatterpfqpd(A, B, C, D, E) __builtin_ia32_scatterpfqpd(A, B, C, 1, _MM_HINT_T0)
+
+/* avx512erintrin.h */
+#define __builtin_ia32_exp2pd_mask(A, B, C, D) __builtin_ia32_exp2pd_mask (A, B, C, 8)
+#define __builtin_ia32_exp2ps_mask(A, B, C, D) __builtin_ia32_exp2ps_mask (A, B, C, 8)
+#define __builtin_ia32_rcp28pd_mask(A, B, C, D) __builtin_ia32_rcp28pd_mask (A, B, C, 8)
+#define __builtin_ia32_rcp28ps_mask(A, B, C, D) __builtin_ia32_rcp28ps_mask (A, B, C, 8)
+#define __builtin_ia32_rsqrt28pd_mask(A, B, C, D) __builtin_ia32_rsqrt28pd_mask (A, B, C, 8)
+#define __builtin_ia32_rsqrt28ps_mask(A, B, C, D) __builtin_ia32_rsqrt28ps_mask (A, B, C, 8)
+#define __builtin_ia32_rcp28sd_round(A, B, C) __builtin_ia32_rcp28sd_round(A, B, 8)
+#define __builtin_ia32_rcp28ss_round(A, B, C) __builtin_ia32_rcp28ss_round(A, B, 8)
+#define __builtin_ia32_rsqrt28sd_round(A, B, C) __builtin_ia32_rsqrt28sd_round(A, B, 8)
+#define __builtin_ia32_rsqrt28ss_round(A, B, C) __builtin_ia32_rsqrt28ss_round(A, B, 8)
+
+/* shaintrin.h */
+#define __builtin_ia32_sha1rnds4(A, B, C) __builtin_ia32_sha1rnds4(A, B, 1)
+
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1")
+#include <wmmintrin.h>
+#include <smmintrin.h>
+#include <mm3dnow.h>
+#include <x86intrin.h>
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-24.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-24.c
new file mode 100644
index 000000000..daeb968a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-24.c
@@ -0,0 +1,5 @@
+/* PR target/44338 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -ffp-contract=off" } */
+
+#include "sse-23.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-3.c
new file mode 100644
index 000000000..1be1d1aa2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-3.c
@@ -0,0 +1,37 @@
+/* PR target/21149 */
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+
+void
+__attribute__((noinline))
+check (__m128 x, float a, float b, float c, float d)
+{
+  union { __m128 m; float f[4]; } u;
+  u.m = x;
+  if (u.f[0] != a || u.f[1] != b || u.f[2] != c || u.f[3] != d)
+    abort ();
+}
+
+static inline
+void
+foo (__m128 *x)
+{
+  __m128 y = _mm_setzero_ps ();
+  __m128 v = _mm_movehl_ps (y, *x);
+  __m128 w = _mm_movehl_ps (*x, y);
+  check (*x, 9, 1, 2, -3);
+  check (v, 2, -3, 0, 0);
+  check (w, 0, 0, 2, -3);
+}
+
+static void
+sse_test (void)
+{
+  __m128 y = _mm_set_ps (-3, 2, 1, 9);
+  foo (&y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-4.c
new file mode 100644
index 000000000..394ad9d7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-4.c
@@ -0,0 +1,10 @@
+/* This testcase caused a buffer overflow in simplify_immed_subreg.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i foo (__m128i x)
+{
+  return _mm_min_epu8 (x, _mm_set1_epi8 (10));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-5.c
new file mode 100644
index 000000000..8f5d9bc24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-5.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-prune-output "ABI for passing parameters" } */
+/* { dg-options "-Winline -O2 -mno-sse" } */
+
+typedef double v2df __attribute__ ((vector_size (16)));
+v2df p;
+q(v2df t) /* { dg-warning "SSE" "" } */
+{
+	p=t;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-6.c
new file mode 100644
index 000000000..77131d40d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-6.c
@@ -0,0 +1,305 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+#include <string.h>
+
+#define SHIFT (4)
+
+typedef union {
+  __m128i v;
+  unsigned int s[4];
+  unsigned short int t[8];
+  unsigned long long u[2];
+  unsigned char c[16];
+}vecInLong;
+
+void sse2_tests (void) __attribute__((noinline));
+void dump128_16 (char *, char *, vecInLong);
+void dump128_32 (char *, char *, vecInLong);
+void dump128_64 (char *, char *, vecInLong);
+void dump128_128 (char *, char *, vecInLong);
+int check (const char *, const char *[]);
+
+char buf[8000];
+char comparison[8000];
+static int errors = 0;
+
+vecInLong a128, b128, c128, d128, e128, f128;
+__m128i m128_16, m128_32, s128, m128_64, m128_128;
+__m64 m64_16, s64, m64_32, m64_64;
+
+const char *reference_sse2[] = {
+  "_mm_srai_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n",
+  "_mm_sra_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n",
+  "_mm_srai_epi32 00123456 00123456 00123456 00123456 \n",
+  "_mm_sra_epi32 00123456 00123456 00123456 00123456 \n",
+  "_mm_srli_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n",
+  "_mm_srl_epi16 0012 0012 0012 0012 0012 0012 0012 0012 \n",
+  "_mm_srli_epi32 00123456 00123456 00123456 00123456 \n",
+  "_mm_srl_epi32 00123456 00123456 00123456 00123456 \n",
+  "_mm_srli_epi64 00123456789abcde 00123456789abcde \n",
+  "_mm_srl_epi64 00123456789abcde 00123456789abcde \n",
+  "_mm_srli_si128 (byte shift)  00000000ffeeddccbbaa998877665544\n",
+  "_mm_slli_epi16 1230 1230 1230 1230 1230 1230 1230 1230 \n",
+  "_mm_sll_epi16 1230 1230 1230 1230 1230 1230 1230 1230 \n",
+  "_mm_slli_epi32 12345670 12345670 12345670 12345670 \n",
+  "_mm_sll_epi32 12345670 12345670 12345670 12345670 \n",
+  "_mm_slli_epi64 123456789abcdef0 123456789abcdef0 \n",
+  "_mm_sll_epi64 123456789abcdef0 123456789abcdef0 \n",
+  "_mm_sll_si128 (byte shift) bbaa9988776655443322110000000000\n",
+  "_mm_shuffle_epi32 ffeeddcc bbaa9988 77665544 33221100 \n",
+  "_mm_shuffelo_epi16 7766 5544 3322 1100 9988 bbaa ddcc ffee \n",
+  "_mm_shuffehi_epi16 1100 3322 5544 7766 ffee ddcc bbaa 9988 \n",
+  ""
+};
+
+static void
+sse2_test (void)
+{
+  a128.s[0] = 0x01234567;
+  a128.s[1] = 0x01234567;
+  a128.s[2] = 0x01234567;
+  a128.s[3] = 0x01234567;
+
+  m128_32 = a128.v;
+
+  d128.u[0] = 0x0123456789abcdefULL;
+  d128.u[1] = 0x0123456789abcdefULL;
+
+  m128_64 = d128.v;
+
+  /* This is the 128-bit constant 0x00112233445566778899aabbccddeeff,
+     expressed as two little-endian 64-bit words.  */
+  e128.u[0] = 0x7766554433221100ULL;
+  e128.u[1] = 0xffeeddccbbaa9988ULL;
+
+  f128.t[0] = 0x0123;
+  f128.t[1] = 0x0123;
+  f128.t[2] = 0x0123;
+  f128.t[3] = 0x0123;
+  f128.t[4] = 0x0123;
+  f128.t[5] = 0x0123;
+  f128.t[6] = 0x0123;
+  f128.t[7] = 0x0123;
+
+  m128_16 = f128.v;
+
+  m128_128 = e128.v;
+
+  b128.s[0] = SHIFT;
+  b128.s[1] = 0;
+  b128.s[2] = 0;
+  b128.s[3] = 0;
+
+  s128 = b128.v;
+
+  sse2_tests();
+  check (buf, reference_sse2);
+#ifdef DEBUG
+  printf ("sse2 testing:\n");
+  printf (buf);
+  printf ("\ncomparison:\n");
+  printf (comparison);
+#endif
+  buf[0] = '\0';
+
+  if (errors != 0)
+    abort ();
+}
+
+void __attribute__((noinline))
+sse2_tests (void)
+{
+  /* psraw */
+  c128.v = _mm_srai_epi16 (m128_16, SHIFT);
+  dump128_16 (buf, "_mm_srai_epi16", c128);
+  c128.v = _mm_sra_epi16 (m128_16, s128);
+  dump128_16 (buf, "_mm_sra_epi16", c128);
+
+  /* psrad */
+  c128.v = _mm_srai_epi32 (m128_32, SHIFT);
+  dump128_32 (buf, "_mm_srai_epi32", c128);
+  c128.v = _mm_sra_epi32 (m128_32, s128);
+  dump128_32 (buf, "_mm_sra_epi32", c128);
+
+  /* psrlw */
+  c128.v = _mm_srli_epi16 (m128_16, SHIFT);
+  dump128_16 (buf, "_mm_srli_epi16", c128);
+  c128.v = _mm_srl_epi16 (m128_16, s128);
+  dump128_16 (buf, "_mm_srl_epi16", c128);
+
+  /* psrld */
+  c128.v = _mm_srli_epi32 (m128_32, SHIFT);
+  dump128_32 (buf, "_mm_srli_epi32", c128);
+  c128.v = _mm_srl_epi32 (m128_32, s128);
+  dump128_32 (buf, "_mm_srl_epi32", c128);
+
+  /* psrlq */
+  c128.v = _mm_srli_epi64 (m128_64, SHIFT);
+  dump128_64 (buf, "_mm_srli_epi64", c128);
+  c128.v = _mm_srl_epi64 (m128_64, s128);
+  dump128_64 (buf, "_mm_srl_epi64", c128);
+
+  /* psrldq */
+  c128.v = _mm_srli_si128 (m128_128, SHIFT);
+  dump128_128 (buf, "_mm_srli_si128 (byte shift) ", c128);
+
+  /* psllw */
+  c128.v = _mm_slli_epi16 (m128_16, SHIFT);
+  dump128_16 (buf, "_mm_slli_epi16", c128);
+  c128.v = _mm_sll_epi16 (m128_16, s128);
+  dump128_16 (buf, "_mm_sll_epi16", c128);
+
+  /* pslld */
+  c128.v = _mm_slli_epi32 (m128_32, SHIFT);
+  dump128_32 (buf, "_mm_slli_epi32", c128);
+  c128.v = _mm_sll_epi32 (m128_32, s128);
+  dump128_32 (buf, "_mm_sll_epi32", c128);
+
+  /* psllq */
+  c128.v = _mm_slli_epi64 (m128_64, SHIFT);
+  dump128_64 (buf, "_mm_slli_epi64", c128);
+  c128.v = _mm_sll_epi64 (m128_64, s128);
+  dump128_64 (buf, "_mm_sll_epi64", c128);
+
+  /* pslldq */
+  c128.v = _mm_slli_si128 (m128_128, SHIFT);
+  dump128_128 (buf, "_mm_sll_si128 (byte shift)", c128);
+
+  /* Shuffle constant 0x1b == 0b_00_01_10_11, e.g. swap words: ABCD => DCBA.  */
+
+  /* pshufd */
+  c128.v = _mm_shuffle_epi32 (m128_128, 0x1b);
+  dump128_32 (buf, "_mm_shuffle_epi32", c128);
+
+  /* pshuflw */
+  c128.v = _mm_shufflelo_epi16 (m128_128, 0x1b);
+  dump128_16 (buf, "_mm_shuffelo_epi16", c128);
+
+  /* pshufhw */
+  c128.v = _mm_shufflehi_epi16 (m128_128, 0x1b);
+  dump128_16 (buf, "_mm_shuffehi_epi16", c128);
+}
+
+void
+dump128_16 (char *buf, char *name, vecInLong x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<8; i++)
+    {
+      sprintf (p, "%4.4x ", x.t[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump128_32 (char *buf, char *name, vecInLong x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<4; i++)
+    {
+      sprintf (p, "%8.8x ", x.s[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump128_64 (char *buf, char *name, vecInLong x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<2; i++)
+    {
+#if defined(_WIN32) && !defined(__CYGWIN__)
+      sprintf (p, "%16.16I64x ", x.u[i]);
+#else
+      sprintf (p, "%16.16llx ", x.u[i]);
+#endif
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+void
+dump128_128 (char *buf, char *name, vecInLong x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=15; i>=0; i--)
+    {
+      /* This is cheating; we don't have a 128-bit int format code.
+	 Running the loop backwards to compensate for the
+	 little-endian layout. */
+      sprintf (p, "%2.2x", x.c[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+int
+check (const char *input, const char *reference[])
+{
+  int broken, i, j, len;
+  const char *p_input;
+  char *p_comparison;
+  int new_errors = 0;
+
+  p_comparison = &comparison[0];
+  p_input = input;
+
+  for (i = 0; *reference[i] != '\0'; i++)
+    {
+      broken = 0;
+      len = strlen (reference[i]);
+      for (j = 0; j < len; j++)
+	{
+	  /* Ignore the terminating NUL characters at the end of every string in 'reference[]'.  */
+	  if (!broken && *p_input != reference[i][j])
+	    {
+	      *p_comparison = '\0';
+	      strcat (p_comparison, " >>> ");
+	      p_comparison += strlen (p_comparison);
+	      new_errors++;
+	      broken = 1;
+	    }
+	  *p_comparison = *p_input;
+	  p_comparison++;
+	  p_input++;
+	}
+      if (broken)
+	{
+	  *p_comparison = '\0';
+	  strcat (p_comparison, "expected:\n");
+	  strcat (p_comparison, reference[i]);
+	  p_comparison += strlen (p_comparison);
+	}
+    }
+  *p_comparison = '\0';
+  strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ;
+  errors += new_errors;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-7.c
new file mode 100644
index 000000000..30e2c13ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-7.c
@@ -0,0 +1,124 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+#include <string.h>
+
+#define SHIFT (4)
+
+typedef union {
+  __m64 v;
+  unsigned char c[8];
+  unsigned short int s[4];
+  unsigned long long t;
+  unsigned int u[2];
+}vecInWord;
+
+void sse_tests (void) __attribute__((noinline));
+void dump64_16 (char *, char *, vecInWord);
+int check (const char *, const char *[]);
+
+char buf[8000];
+char comparison[8000];
+static int errors = 0;
+
+vecInWord c64, e64;
+__m64 m64_64;
+
+const char *reference_sse[] = {
+  "_mm_shuffle_pi16 0123 4567 89ab cdef \n",
+  ""
+};
+
+static void
+sse_test (void)
+{
+  e64.t  = 0x0123456789abcdefULL;
+
+  m64_64 = e64.v;
+
+  sse_tests();
+  check (buf, reference_sse);
+#ifdef DEBUG
+  printf ("sse testing:\n");
+  printf (buf);
+  printf ("\ncomparison:\n");
+  printf (comparison);
+#endif
+  buf[0] = '\0';
+
+  if (errors != 0)
+    abort ();
+}
+
+void __attribute__((noinline))
+sse_tests (void)
+{
+  /* pshufw */
+  c64.v = _mm_shuffle_pi16 (m64_64, 0x1b);
+  dump64_16 (buf, "_mm_shuffle_pi16", c64);
+}
+
+void
+dump64_16 (char *buf, char *name, vecInWord x)
+{
+  int i;
+  char *p = buf + strlen (buf);
+
+  sprintf (p, "%s ", name);
+  p += strlen (p);
+
+  for (i=0; i<4; i++)
+    {
+      sprintf (p, "%4.4x ", x.s[i]);
+      p += strlen (p);
+    }
+  strcat (p, "\n");
+}
+
+int
+check (const char *input, const char *reference[])
+{
+  int broken, i, j, len;
+  const char *p_input;
+  char *p_comparison;
+  int new_errors = 0;
+
+  p_comparison = &comparison[0];
+  p_input = input;
+
+  for (i = 0; *reference[i] != '\0'; i++)
+    {
+      broken = 0;
+      len = strlen (reference[i]);
+      for (j = 0; j < len; j++)
+	{
+	  /* Ignore the terminating NUL characters at the end of every string in 'reference[]'.  */
+	  if (!broken && *p_input != reference[i][j])
+	    {
+	      *p_comparison = '\0';
+	      strcat (p_comparison, " >>> ");
+	      p_comparison += strlen (p_comparison);
+	      new_errors++;
+	      broken = 1;
+	    }
+	  *p_comparison = *p_input;
+	  p_comparison++;
+	  p_input++;
+	}
+      if (broken)
+	{
+	  *p_comparison = '\0';
+	  strcat (p_comparison, "expected:\n");
+	  strcat (p_comparison, reference[i]);
+	  p_comparison += strlen (p_comparison);
+	}
+    }
+  *p_comparison = '\0';
+  strcat (p_comparison, new_errors ? "failure\n\n" : "O.K.\n\n") ;
+  errors += new_errors;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-8.c
new file mode 100644
index 000000000..31e8c32fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-8.c
@@ -0,0 +1,14 @@
+/* PR target/14343 */
+/* Origin: <Pawe Sikora <pluto@ds14.agh.edu.pl> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-march=pentium3" } */
+
+int main() 
+{ 
+  typedef long long int v __attribute__ ((vector_size (16))); 
+  v a, b; 
+  a = b; 
+  return 0; 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-9.c
new file mode 100644
index 000000000..e1a0a2270
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-9.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#include <xmmintrin.h>
+#include <stddef.h>
+#include <string.h>
+
+static void
+sse_test (void)
+{
+  int alignment, n;
+  void *ptr;
+  int errors = 0;
+  const char test [] = "This is a test.";
+
+  for (alignment = 1; alignment <= (1 << 20); alignment += alignment)
+    {
+      ptr = _mm_malloc (alignment, alignment);
+      if (((ptrdiff_t) ptr) & (alignment - 1))
+	abort ();
+      if (ptr)
+	{
+	  n = alignment > sizeof test ? sizeof test : alignment;
+	  memcpy (ptr, test, n);
+	  if (memcmp (ptr, test, n) != 0)
+	    errors++;
+	  _mm_free (ptr);
+	}
+      else
+	errors++;
+    }
+   
+  if (errors != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-addps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-addps-1.c
new file mode 100644
index 000000000..b280667b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-addps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_add_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] + s2.a[i];   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-addss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-addss-1.c
new file mode 100644
index 000000000..43aa2d53e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-addss-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_add_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+
+  e[0] = s1.a[0] + s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-andnps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-andnps-1.c
new file mode 100644
index 000000000..eeeec020a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-andnps-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_andnot_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  int source1[4]={34, 545, 955, 67};
+  int source2[4]={67, 4, 57, 897};
+  int e[4];
+   
+  s1.x = _mm_loadu_ps ((float *)source1);
+  s2.x = _mm_loadu_ps ((float *)source2);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = (~source1[0]) & source2[0];
+  e[1] = (~source1[1]) & source2[1];
+  e[2] = (~source1[2]) & source2[2];
+  e[3] = (~source1[3]) & source2[3];
+
+  if (check_union128 (u, (float *)e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-andps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-andps-1.c
new file mode 100644
index 000000000..6094dba7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-andps-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_and_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  union
+  {
+    float f[4];
+    int   i[4];
+  }source1, source2, e;
+
+  s1.x = _mm_set_ps (34, 545, 955, 67);
+  s2.x = _mm_set_ps (67, 4, 57, 897);
+
+  _mm_storeu_ps (source1.f, s1.x);
+  _mm_storeu_ps (source2.f, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+   
+  e.i[0] = source1.i[0] & source2.i[0];
+  e.i[1] = source1.i[1] & source2.i[1];
+  e.i[2] = source1.i[2] & source2.i[2];
+  e.i[3] = source1.i[3] & source2.i[3];
+
+  if (check_union128 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-check.h
new file mode 100644
index 000000000..11b71bc3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-check.h
@@ -0,0 +1,28 @@
+#include <stdlib.h>
+#include "m128-check.h"
+#include "cpuid.h"
+#include "sse-os-support.h"
+
+static void sse_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  sse_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE test only if host has SSE support.  */
+  if ((edx & bit_SSE) && sse_os_support ())
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c
new file mode 100644
index 000000000..45438bcd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cmpss-1.c
@@ -0,0 +1,61 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse -std=c99" } */
+/* { dg-require-effective-target sse } */
+/* { dg-require-effective-target c99_runtime } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+float s1[]={2134.3343, 6678.346, 453.345635, 54646.464356};
+float s2[]={41124.234, 6678.346, 8653.65635, 856.43576};
+int dd[] = {1, 2, 3, 4};
+float d[4];
+union{int i[4]; float f[4];} e;
+
+void check(char *id)
+{
+    if(checkVi((int*)d, e.i, 4)){
+	printf("mm_cmp%s_ss FAILED\n", id);
+    }
+}
+
+static void
+TEST ()
+{
+    __m128 source1, source2, dest;
+    int i;
+
+#define CMP(cmp, rel)					\
+    e.i[0] = rel ? -1 : 0;	                        \
+    dest = _mm_loadu_ps((float*)dd);			\
+    source1 = _mm_loadu_ps(s1);				\
+    source2 = _mm_loadu_ps(s2);				\
+    dest = _mm_cmp##cmp##_ss(source1, source2);		\
+    _mm_storeu_ps(d, dest);			        \
+    check("" #cmp "");
+
+    for(i = 1; i < 4; i++) e.f[i] = s1[i];
+    
+    CMP(eq, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(lt, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(le, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(unord, isunordered(s1[0], s2[0]));
+    CMP(neq, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(nlt, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(nle, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(ord, !isunordered(s1[0], s2[0]));
+
+    CMP(ge, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(gt, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(nge, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(ngt, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-1.c
new file mode 100644
index 000000000..ff623aa8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comieq_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] == s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-2.c
new file mode 100644
index 000000000..d674bed00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comilt_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] < s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-3.c
new file mode 100644
index 000000000..d2301ad8e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-3.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comile_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] <= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-4.c
new file mode 100644
index 000000000..7f372e249
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-4.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comigt_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] > s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-5.c
new file mode 100644
index 000000000..104fdd701
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-5.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comige_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] >= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-6.c
new file mode 100644
index 000000000..8229b7d55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-comiss-6.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_comineq_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] != s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c
new file mode 100644
index 000000000..5b1cfe795
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-copysignf-vec.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+extern float copysignf (float, float);
+
+#define N 16
+
+float a[N] = {-0.1f,-3.2f,-6.3f,-9.4f,-12.5f,-15.6f,-18.7f,-21.8f,24.9f,27.1f,30.2f,33.3f,36.4f,39.5f,42.6f,45.7f};
+float b[N] = {-1.2f,3.4f,-5.6f,7.8f,-9.0f,1.0f,-2.0f,3.0f,-4.0f,-5.0f,6.0f,7.0f,-8.0f,-9.0f,10.0f,11.0f};
+float r[N];
+
+static void
+TEST (void)
+{  
+  int i;
+
+  for (i = 0; i < N; i++)
+    r[i] = copysignf (a[i], b[i]);
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    if (r[i] != copysignf (a[i], b[i]))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c
new file mode 100644
index 000000000..740227fee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 p, int b)
+{
+  return _mm_cvtsi32_ss (p, b); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  int b = 498;
+  float e[4] = { 24.43, 68.346, 43.35, 546.46 };
+   
+  s1.x = _mm_set_ps (e[3], e[2], e[1], e[0]);
+  u.x = test (s1.x, b); 
+  e[0] = (float)b;  
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c
new file mode 100644
index 000000000..76ce912a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtsi2ss-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 p, long long b)
+{
+  return _mm_cvtsi64_ss (p, b); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  long long b = 4294967295133LL;
+  float e[4] = { 24.43, 68.346, 43.35, 546.46 };
+   
+  s1.x = _mm_set_ps (e[3], e[2], e[1], e[0]);
+  u.x = test (s1.x, b); 
+  e[0] = (float)b;  
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c
new file mode 100644
index 000000000..3f8c549c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtss2si-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvtss_si32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  int d;
+  int e;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  d = test (s1.x); 
+  e = (int)s1.a[0];  
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c
new file mode 100644
index 000000000..909c3880e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvtss2si-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvtss_si64 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  long long d;
+  long long e;
+   
+  s1.x = _mm_set_ps (344.4, 68.346, 43.35, 429496729501.4);
+  d = test (s1.x); 
+  e = (long long)s1.a[0];  
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c
new file mode 100644
index 000000000..667806d97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvttss2si-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvttss_si32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  int d;
+  int e;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  d = test (s1.x); 
+  e = (int)s1.a[0];  
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c
new file mode 100644
index 000000000..cbfdddd40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-cvttss2si-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse } */
+/* { dg-options "-O2 -msse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvttss_si64 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  long long d;
+  long long e;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 429496729501.4);
+  d = test (s1.x); 
+  e = (long long)s1.a[0];  
+
+  if (e != d)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-divps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-divps-1.c
new file mode 100644
index 000000000..321bb5ac7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-divps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_div_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] / s2.a[0];
+  e[1] = s1.a[1] / s2.a[1];
+  e[2] = s1.a[2] / s2.a[2];
+  e[3] = s1.a[3] / s2.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-divss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-divss-1.c
new file mode 100644
index 000000000..1427e4f1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-divss-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_div_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] / s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c
new file mode 100644
index 000000000..f25131547
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-init-v4hi-1.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <mmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m64 x, unsigned short *v, int j)
+{
+  union
+    {
+      __m64 x;
+      unsigned short i[8];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned short *v)
+{
+  __m64 x;
+
+  x = _mm_set_pi16 (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_pi16 (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_pi16 (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_pi16 (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse_test (void)
+{
+  unsigned short v[4]
+    = { 0x7B5B, 0x5465, 0x7374, 0x5665};
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c
new file mode 100644
index 000000000..eea03ecad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-init-v4sf-1.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128 x, float *v, int j)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.f[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: %f != %f\n", i, v[i], u.f[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.f[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: %f != 0\n", i, u.f[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (float *v)
+{
+  __m128 x;
+
+  x = _mm_set_ps (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_ps (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_ps (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_ps (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse_test (void)
+{
+  float v[4] = { -3, 2, 1, 9 };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-maxps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-maxps-1.c
new file mode 100644
index 000000000..9a82f665a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-maxps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_max_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] > s2.a[i] ? s1.a[i]:s2.a[i];   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-maxss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-maxss-1.c
new file mode 100644
index 000000000..7b88dfce7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-maxss-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_max_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0];   
+  e[1] = s1.a[1]; 
+  e[2] = s1.a[2];
+  e[3] = s1.a[3]; 
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-minps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-minps-1.c
new file mode 100644
index 000000000..452df8318
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-minps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_min_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[i] < s2.a[i] ? s1.a[i]:s2.a[i];   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-minss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-minss-1.c
new file mode 100644
index 000000000..b7288f859
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-minss-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_min_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+  
+  e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0];   
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movaps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movaps-1.c
new file mode 100644
index 000000000..ed3562ba5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movaps-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm_load_ps (e); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] __attribute__ ((aligned (16))) = {2134.3343,1234.635654, 1.2234, 876.8976};
+
+  u.x = test (e);   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movaps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movaps-2.c
new file mode 100644
index 000000000..fcfa80beb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movaps-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m128 a)
+{
+  _mm_store_ps (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] __attribute__ ((aligned (16))) = {0.0};
+
+  u.x = _mm_set_ps (2134.3343,1234.635654, 1.414, 3.3421);
+
+  test (e, u.x);
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c
new file mode 100644
index 000000000..4d7b3edc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhlps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_movehl_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = test (s1.x, s2.x); 
+
+  e[0] = s2.a[2];
+  e[1] = s2.a[3];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhps-1.c
new file mode 100644
index 000000000..44b885927
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhps-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 a, __m64 *p)
+{
+  return _mm_loadh_pi (a, p); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  float d[2] = {24.43, 68.346};
+  float e[4] = {1.17, 2.16, 3.15, 4.14};
+
+  s1.x = _mm_set_ps (5.13, 6.12, 7.11, 8.9);
+  u.x = _mm_loadu_ps (e);
+ 
+  u.x = test (s1.x, (__m64 *)d);
+
+  e[0] = s1.a[0];
+  e[1] = s1.a[1];
+  e[2] = d[0];
+  e[3] = d[1];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhps-2.c
new file mode 100644
index 000000000..11ab38397
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movhps-2.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (__m64 *p, __m128 a)
+{
+  return _mm_storeh_pi (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128 s1;
+  float e[2];
+  float d[2];
+
+  s1.x = _mm_set_ps (5.13, 6.12, 7.11, 8.9);
+ 
+  test ((__m64 *)d, s1.x);
+
+  e[0] = s1.a[2];
+  e[1] = s1.a[3];
+
+  if (checkVf (d, e, 2))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c
new file mode 100644
index 000000000..4ce3edf59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movlhps-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 a, __m128 b)
+{
+  return _mm_movelh_ps (a, b); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4]; 
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  u.x = _mm_set1_ps (0.0);
+
+  u.x = test (s1.x, s2.x);
+
+  e[0] = s1.a[0];
+  e[1] = s1.a[1];
+  e[2] = s2.a[0];
+  e[3] = s2.a[1];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c
new file mode 100644
index 000000000..8557a3021
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movmskps-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128 a)
+{
+  return _mm_movemask_ps (a); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float s[4] = {2134.3343,1234.635654, 1.2234, 876.8976};
+  int d;
+  int e = 0;
+  int i;
+
+  u.x = _mm_loadu_ps (s);   
+  d = test (u.x);
+
+  for (i = 0; i < 4; i++)
+    if (s[i] < 0)
+      e |= (1 << i);
+
+  if (checkVi (&d, &e, 1))
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movntps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movntps-1.c
new file mode 100644
index 000000000..067f29616
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movntps-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void 
+__attribute__((noinline, unused))
+test (float *p, __m128 s)
+{
+  return _mm_stream_ps (p, s); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] __attribute__ ((aligned(16)));
+
+  u.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  test (e, u.x); 
+  
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-1.c
new file mode 100644
index 000000000..ee53d5faf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm_load_ss (e); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] = {1.1, 2.2, 3.3, 4.4};
+ 
+  u.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976);
+
+  u.x = test (e);
+
+  e[1] = u.a[1];
+  e[2] = u.a[2];
+  e[3] = u.a[3];   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-2.c
new file mode 100644
index 000000000..638666594
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m128 a)
+{
+  return _mm_store_ss (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float d[1];
+  float e[1];
+ 
+  u.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976);
+
+  test (d, u.x);
+
+  e[0] = u.a[0];
+
+  if (checkVf (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-3.c
new file mode 100644
index 000000000..a090aada7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movss-3.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 a, __m128 b)
+{
+  return _mm_move_ss (a, b); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+ 
+  s1.x = _mm_set_ps (2134.3343,1234.635654, 1.2234, 876.8976);
+  s2.x = _mm_set_ps (1.1, 2.2, 3.3, 4.4);
+  u.x = _mm_set_ps (5.5, 6.6, 7.7, 8.8);
+  u.x = test (s1.x, s2.x);
+  
+  e[0] = s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movups-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movups-1.c
new file mode 100644
index 000000000..7ea912289
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movups-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (float *e)
+{
+  return _mm_loadu_ps (e); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] = {2134.3343,1234.635654, 1.2234, 876.8976};
+
+  u.x = test (e);   
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movups-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movups-2.c
new file mode 100644
index 000000000..188967a2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-movups-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (float *e, __m128 a)
+{
+  _mm_storeu_ps (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  float e[4] = {0.0};
+
+  u.x = _mm_set_ps (2134.3343,1234.635654, 1.414, 3.3421);
+
+  test (e, u.x);
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-mulps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-mulps-1.c
new file mode 100644
index 000000000..de66a28e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-mulps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_mul_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[1] * s2.a[1];
+  e[2] = s1.a[2] * s2.a[2];
+  e[3] = s1.a[3] * s2.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-mulss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-mulss-1.c
new file mode 100644
index 000000000..99161a811
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-mulss-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_mul_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-orps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-orps-1.c
new file mode 100644
index 000000000..605603726
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-orps-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_or_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union {
+    float f[4];
+    int   i[4];
+  }source1, source2, e;
+
+  union128 u, s1, s2;
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 168.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (10.17, 2.16, 3.15, 4.14);
+
+  _mm_storeu_ps (source1.f, s1.x);
+  _mm_storeu_ps (source2.f, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e.i[i] = source1.i[i] | source2.i[i];   
+
+  if (check_union128 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-os-support.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-os-support.h
new file mode 100644
index 000000000..a2b4e2d3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-os-support.h
@@ -0,0 +1,55 @@
+#if defined(__sun__) && defined(__svr4__)
+/* Make sure sigaction() is declared even with -std=c99.  */
+#define __EXTENSIONS__
+#include <signal.h>
+#include <ucontext.h>
+
+static volatile sig_atomic_t sigill_caught;
+
+static void
+sigill_hdlr (int sig __attribute((unused)),
+	     siginfo_t *sip __attribute__((unused)),
+	     ucontext_t *ucp)
+{
+  sigill_caught = 1;
+  /* Set PC to the instruction after the faulting one to skip over it,
+     otherwise we enter an infinite loop.  */
+  ucp->uc_mcontext.gregs[EIP] += 4;
+  setcontext (ucp);
+}
+#endif
+
+/* Check if the OS supports executing SSE instructions.  This function is
+   only used in sse-check.h, sse2-check.h, and sse3-check.h so far since
+   Solaris 8 and 9 won't run on newer CPUs anyway.  */
+
+static int
+sse_os_support (void)
+{
+#if defined(__sun__) && defined(__svr4__)
+  /* Solaris 2 before Solaris 9 4/04 cannot execute SSE instructions
+     even if the CPU supports them.  Programs receive SIGILL instead, so
+     check for that at runtime.  */
+
+  struct sigaction act, oact;
+
+  act.sa_handler = sigill_hdlr;
+  sigemptyset (&act.sa_mask);
+  /* Need to set SA_SIGINFO so a ucontext_t * is passed to the handler.  */
+  act.sa_flags = SA_SIGINFO;
+  sigaction (SIGILL, &act, &oact);
+
+  /* We need a single SSE instruction here so the handler can safely skip
+     over it.  */
+  __asm__ volatile ("movss %xmm2,%xmm1");
+
+  sigaction (SIGILL, &oact, NULL);
+
+  if (sigill_caught)
+    exit (0);
+  else
+    return 1;
+#else
+  return 1;
+#endif /* __sun__ && __svr4__ */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c
new file mode 100644
index 000000000..4d0783515
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-rcpps-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1)
+{
+  return _mm_rcp_ps (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  u.x = test (s1.x); 
+  
+  for (i = 0; i < 4; i++)
+    {
+      __m128 tmp = _mm_load_ss (&s1.a[i]);
+      tmp = _mm_rcp_ss (tmp);
+      _mm_store_ss (&e[i], tmp);
+    }
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-recip-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-recip-vec.c
new file mode 100644
index 000000000..de2f3d297
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-recip-vec.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse -mfpmath=sse -mrecip" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+extern float sqrtf (float);
+extern float fabsf (float);
+
+#define N 8
+
+float a[N] = { 0.f, 18.f, 108.f, 324.f, 720.f, 1944.f, 3087.f, 5832.f };
+float b[N] = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f };
+float r[N];
+
+float rc[N] = { 0.f, 3.f, 6.f, 9.f, 12.f, 18.f, 21.f, 27.f };
+
+static void
+TEST (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      r[i] = sqrtf (a[i] / b[i]);
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (fabsf (r[i] - rc[i]) > 0.0001)
+	abort();
+    }   
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-recip.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-recip.c
new file mode 100644
index 000000000..4f7d3bf3d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-recip.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -msse -mfpmath=sse -mrecip" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+extern float sqrtf (float);
+extern float fabsf (float);
+
+#define N 8
+
+static void
+sse_test (void)
+{
+  float a[N] = { 0.f, 18.f, 108.f, 324.f, 720.f, 1944.f, 3087.f, 5832.f };
+  float b[N] = { 1.f, 2.f, 3.f, 4.f, 5.f, 6.f, 7.f, 8.f };
+  float r[N];
+
+  float rc[N] = { 0.f, 3.f, 6.f, 9.f, 12.f, 18.f, 21.f, 27.f };
+
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      r[i] = sqrtf (a[i] / b[i]);
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (fabsf (r[i] - rc[i]) > 0.0001)
+	abort();
+    }   
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c
new file mode 100644
index 000000000..c2db72549
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-rsqrtps-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1)
+{
+  return _mm_rsqrt_ps (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  u.x = test (s1.x); 
+  
+  for (i = 0; i < 4; i++)
+    {
+      __m128 tmp = _mm_load_ss (&s1.a[i]);
+      tmp = _mm_rsqrt_ss (tmp);
+      _mm_store_ss (&e[i], tmp);
+    }
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c
new file mode 100644
index 000000000..5a0c9b95d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-set-ps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline))
+test (float *v)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_ps (v[3], v[2], v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.f[i])
+      {
+#ifdef DEBUG
+	printf ("%i: %f != %f\n", i, v[i], u.f[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse_test (void)
+{
+  float v[4] = { -3, 2, 1, 9 };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c
new file mode 100644
index 000000000..1dbd260e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-sqrtps-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1)
+{
+  return _mm_sqrt_ps (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1;
+  float e[4];
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  u.x = test (s1.x); 
+  
+  for (i = 0; i < 4; i++) {
+    __m128 tmp = _mm_load_ss (&s1.a[i]);
+    tmp = _mm_sqrt_ss (tmp);
+    _mm_store_ss (&e[i], tmp);
+    }
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-subps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-subps-1.c
new file mode 100644
index 000000000..e63e4784a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-subps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_sub_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] - s2.a[0];
+  e[1] = s1.a[1] - s2.a[1];
+  e[2] = s1.a[2] - s2.a[2];
+  e[3] = s1.a[3] - s2.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-subss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-subss-1.c
new file mode 100644
index 000000000..5d9a5f504
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-subss-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_sub_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] - s2.a[0];
+  e[1] = s1.a[1];
+  e[2] = s1.a[2];
+  e[3] = s1.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c
new file mode 100644
index 000000000..4d72b0187
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomieq_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] == s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c
new file mode 100644
index 000000000..dc4ba8045
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomilt_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] < s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c
new file mode 100644
index 000000000..042898bf6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-3.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomile_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] <= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c
new file mode 100644
index 000000000..a3f32bb35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-4.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomigt_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] > s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c
new file mode 100644
index 000000000..821dd7726
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-5.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomige_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] >= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c
new file mode 100644
index 000000000..602a923a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-ucomiss-6.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_ucomineq_ss (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128  s1, s2;
+  int d[1];
+  int e[1];
+
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] != s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c
new file mode 100644
index 000000000..005924b5b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-unpckhps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_unpackhi_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[2];
+  e[1] = s2.a[2];
+  e[2] = s1.a[3];
+  e[3] = s2.a[3];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c
new file mode 100644
index 000000000..456ef201b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-unpcklps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_unpacklo_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4];
+   
+  s1.x = _mm_set_ps (41124.234,6678.346,8653.65635,856.43576);
+  s2.x = _mm_set_ps (2134.3343,6678.346,453.345635,54646.464356);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+  e[2] = s1.a[1];
+  e[3] = s2.a[1];
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-vect-types.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-vect-types.c
new file mode 100644
index 000000000..9cb6f3e07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-vect-types.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -msse2" } */
+
+#include <xmmintrin.h>
+
+__m128d foo1(__m128d z, __m128d  a, int N) { 
+  int i;
+  for (i=0; i<N; i++) {
+    a = _mm_add_ps(z, a); /* { dg-error "incompatible type" } */
+  }
+  return a;
+}
+/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-xorps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-xorps-1.c
new file mode 100644
index 000000000..8ec500838
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse-xorps-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target sse } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse_test
+#endif
+
+#include CHECK_H
+
+#include <xmmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_xor_ps (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union {
+    float f[4];
+    int   i[4];
+  }source1, source2, e;
+
+  union128 u, s1, s2;
+  int i;
+   
+  s1.x = _mm_set_ps (24.43, 68.346, 43.35, 546.46);
+  s2.x = _mm_set_ps (1.17, 2.16, 3.15, 4.14);
+
+  _mm_storeu_ps (source1.f, s1.x);
+  _mm_storeu_ps (source2.f, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+  
+  for (i = 0; i < 4; i++)
+    e.i[i] = source1.i[i] ^ source2.i[i];   
+
+  if (check_union128 (u, e.f))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c
new file mode 100644
index 000000000..99ff02f1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-addpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_add_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] + s2.a[0];
+  e[1] = s1.a[1] + s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c
new file mode 100644
index 000000000..2297539f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-addsd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_add_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] + s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c
new file mode 100644
index 000000000..0250d6be1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-andnpd-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_andnot_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  long long source1[2]={34545, 95567};
+  long long source2[2]={674, 57897};
+  long long e[2];
+   
+  s1.x = _mm_loadu_pd ((double *)source1);
+  s2.x = _mm_loadu_pd ((double *)source2);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = (~source1[0]) & source2[0];
+  e[1] = (~source1[1]) & source2[1];
+
+  if (check_union128d (u, (double *)e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c
new file mode 100644
index 000000000..9f037ab5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-andpd-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_and_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  
+  union
+  {
+    double d[2];
+    long long ll[2];
+  }source1, source2, e;
+   
+  s1.x = _mm_set_pd (34545, 95567);
+  s2.x = _mm_set_pd (674, 57897);
+
+  _mm_storeu_pd (source1.d, s1.x);
+  _mm_storeu_pd (source2.d, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+   
+  e.ll[0] = source1.ll[0] & source2.ll[0];
+  e.ll[1] = source1.ll[1] & source2.ll[1];
+
+  if (check_union128d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-check.h
new file mode 100644
index 000000000..fd4a6ce1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-check.h
@@ -0,0 +1,28 @@
+#include <stdlib.h>
+#include "cpuid.h"
+#include "m128-check.h"
+#include "sse-os-support.h"
+
+static void sse2_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  sse2_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE2 test only if host has SSE2 support.  */
+  if ((edx & bit_SSE2) && sse_os_support ())
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c
new file mode 100644
index 000000000..153fd2bf0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cmpsd-1.c
@@ -0,0 +1,59 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2 -std=c99" } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-require-effective-target c99_runtime } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+double s1[] = {2134.3343, 6678.346};
+double s2[] = {41124.234, 6678.346};
+long long dd[] =  {1, 2}, d[2];
+union{long long l[2]; double d[2];} e;
+
+void check(char *id)
+{
+    if(checkVl(d, e.l, 2)){
+	printf("mm_cmp%s_sd FAILED\n", id);
+    }
+}
+
+#define CMP(cmp, rel)					\
+    e.l[0] = rel ? -1 : 0;	                        \
+    dest = _mm_loadu_pd((double*)dd);	      		\
+    source1 = _mm_loadu_pd(s1);				\
+    source2 = _mm_loadu_pd(s2);				\
+    dest = _mm_cmp##cmp##_sd(source1, source2);		\
+    _mm_storeu_pd((double*) d, dest);			\
+    check("" #cmp "");
+
+static void
+TEST ()
+{
+    __m128d source1, source2, dest;
+
+    e.d[1] = s1[1];
+    
+    CMP(eq, !isunordered(s1[0], s2[0]) && s1[0] == s2[0]);
+    CMP(lt, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(le, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+    CMP(unord, isunordered(s1[0], s2[0]));
+    CMP(neq, isunordered(s1[0], s2[0]) || s1[0] != s2[0]);
+    CMP(nlt, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(nle, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(ord, !isunordered(s1[0], s2[0]));
+
+    CMP(ge, isunordered(s1[0], s2[0]) || s1[0] >= s2[0]);
+    CMP(gt, isunordered(s1[0], s2[0]) || s1[0] > s2[0]);
+    CMP(nge, !isunordered(s1[0], s2[0]) && s1[0] < s2[0]);
+    CMP(ngt, !isunordered(s1[0], s2[0]) && s1[0] <= s2[0]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c
new file mode 100644
index 000000000..7229906b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comieq_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] == s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c
new file mode 100644
index 000000000..03b5b9eab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comilt_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] < s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c
new file mode 100644
index 000000000..720c63e24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-3.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comile_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] <= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c
new file mode 100644
index 000000000..e33ec7127
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-4.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comigt_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] > s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c
new file mode 100644
index 000000000..e41ee0c1f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-5.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comige_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] >= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c
new file mode 100644
index 000000000..9d32b7ad1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-comisd-6.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_comineq_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] != s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c
new file mode 100644
index 000000000..b336b3284
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-copysign-vec.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+extern double copysign (double, double);
+
+#define N 16
+
+double a[N] = {-0.1,-3.2,-6.3,-9.4,-12.5,-15.6,-18.7,-21.8,24.9,27.1,30.2,33.3,36.4,39.5,42.6,45.7};
+double b[N] = {-1.2,3.4,-5.6,7.8,-9.0,1.0,-2.0,3.0,-4.0,-5.0,6.0,7.0,-8.0,-9.0,10.0,11.0};
+double r[N];
+
+static void
+TEST (void)
+{  
+  int i;
+
+  for (i = 0; i < N; i++)
+    r[i] = copysign (a[i], b[i]);
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    if (r[i] != copysign (a[i], b[i]))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c
new file mode 100644
index 000000000..4d5683108
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-1.c
@@ -0,0 +1,111 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -msse2 -mno-avx" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#define N 16
+float f[N];
+double d[N];
+int n[N];
+
+__attribute__((noinline)) void
+f1 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = d[i];
+}
+
+__attribute__((noinline)) void
+f2 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    f[i] = n[i];
+}
+
+__attribute__((noinline)) void
+f3 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    d[i] = f[i];
+}
+
+__attribute__((noinline)) void
+f4 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    n[i] = f[i];
+}
+
+__attribute__((noinline)) void
+f5 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    d[i] = n[i];
+}
+
+__attribute__((noinline)) void
+f6 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    f[i] = d[i];
+}
+
+static void
+TEST ()
+{
+  int i;
+  for (i = 0; i < N; i++)
+    {
+      asm ("");
+      d[i] = i + 2.5;
+    }
+  f1 ();
+  for (i = 0; i < N; i++)
+    if (n[i] != i + 2)
+      abort ();
+    else
+      n[i] = i + 7;
+  f2 ();
+  for (i = 0; i < N; i++)
+    if (f[i] != i + 7)
+      abort ();
+    else
+      f[i] = i - 2.25f;
+  f3 ();
+  for (i = 0; i < N; i++)
+    if (d[i] != i - 2.25)
+      abort ();
+    else
+      f[i] = i + 3.5;
+  f4 ();
+  for (i = 0; i < N; i++)
+    if (n[i] != i + 3)
+      abort ();
+    else
+      n[i] = i + 9;
+  f5 ();
+  for (i = 0; i < N; i++)
+    if (d[i] != i + 9)
+      abort ();
+    else
+      d[i] = i - 7.25;
+  f6 ();
+  for (i = 0; i < N; i++)
+    if (f[i] != i - 7.25)
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c
new file mode 100644
index 000000000..00f13254c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse2 -mno-sse3 -mtune=generic -fdump-tree-vect-details" } */
+
+#include "sse2-cvt-1.c"
+
+/* { dg-final { scan-tree-dump-times "note: vectorized 1 loops in function" 6 "vect" } } */
+/* { dg-final { scan-assembler "cvttpd2dq" } } */
+/* { dg-final { scan-assembler "cvtdq2ps" } } */
+/* { dg-final { scan-assembler "cvtps2pd" } } */
+/* { dg-final { scan-assembler "cvttps2dq" } } */
+/* { dg-final { scan-assembler "cvtdq2pd" } } */
+/* { dg-final { scan-assembler "cvtpd2ps" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c
new file mode 100644
index 000000000..8a811a3de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvt-vec.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=sse")))
+TEST (void)
+{
+  double a[NUM];
+  float r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (float) a[i];
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (float) a[i])
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c
new file mode 100644
index 000000000..9d85f5cac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtdq2pd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128i p)
+{
+  return _mm_cvtepi32_pd (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  union128i_d s;
+  double e[2];
+
+  s.x = _mm_set_epi32 (123, 321, 456, 987);
+
+  u.x = test (s.x);
+
+  e[0] = (double)s.a[0]; 
+  e[1] = (double)s.a[1]; 
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c
new file mode 100644
index 000000000..4b2965e6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtdq2ps-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128i p)
+{
+  return _mm_cvtepi32_ps (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  union128i_d s;
+  float e[4];
+
+  s.x = _mm_set_epi32 (123, 321, 456, 987);
+
+  u.x = test (s.x);
+
+  e[0] = (float)s.a[0]; 
+  e[1] = (float)s.a[1]; 
+  e[2] = (float)s.a[2]; 
+  e[3] = (float)s.a[3]; 
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c
new file mode 100644
index 000000000..ebcf1539b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtpd2dq-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvtpd_epi32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  union128d s;
+  int e[4] = {0};
+
+  s.x = _mm_set_pd (2.78, 7777768.82);
+
+  u.x = test (s.x);
+
+  e[0] = (int)(s.a[0] + 0.5); 
+  e[1] = (int)(s.a[1] + 0.5); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c
new file mode 100644
index 000000000..15c8188cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtpd2ps-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvtpd_ps (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 u;
+  union128d s;
+  float e[4] = {0};
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  u.x = test (s.x);
+
+  e[0] = (float)s.a[0]; 
+  e[1] = (float)s.a[1]; 
+
+  if (check_union128 (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c
new file mode 100644
index 000000000..e4dcd11fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtps2dq-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvtps_epi32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  union128 s;
+  int e[4] = {0};
+
+  s.x = _mm_set_ps (2.78, 7777768.82, 2.331, 3.456);
+
+  u.x = test (s.x);
+
+  e[0] = (int)(s.a[0] + 0.5); 
+  e[1] = (int)(s.a[1] + 0.5); 
+  e[2] = (int)(s.a[2] + 0.5); 
+  e[3] = (int)(s.a[3] + 0.5); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c
new file mode 100644
index 000000000..cdc6051d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtps2pd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvtps_pd (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  union128 s;
+  double e[2];
+
+  s.x = _mm_set_ps (2.78, 7777768.82, 2.331, 3.456);
+
+  u.x = test (s.x);
+
+  e[0] = (double)s.a[0]; 
+  e[1] = (double)s.a[1]; 
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c
new file mode 100644
index 000000000..9c5a0e2b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvtsd_si32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  int e;
+  int d;
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  d = test (s.x);
+
+  e = (int)(s.a[0] + 0.5);
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c
new file mode 100644
index 000000000..a79a25836
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2si-2.c
@@ -0,0 +1,39 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvtsd_si64 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  long long e;
+  long long d;
+
+  s.x = _mm_set_pd (829496729501.4, 429496729501.4);
+
+  d = test (s.x);
+
+  e = (long long)(s.a[0] + 0.5);
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c
new file mode 100644
index 000000000..6f8a7a7b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsd2ss-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+
+static __m128 
+__attribute__((noinline, unused))
+test (__m128 p1, __m128d p2)
+{
+  return _mm_cvtsd_ss (p1, p2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1;
+  union128 u, s2;
+  double source1[2] = {123.345, 67.3321};
+  float  e[4] = {5633.098, 93.21, 3.34, 4555.2};
+
+  s1.x = _mm_loadu_pd (source1);
+  s2.x = _mm_loadu_ps (e);
+
+  u.x = test(s2.x, s1.x);
+
+  e[0] = (float)source1[0];
+
+  if (check_union128(u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c
new file mode 100644
index 000000000..cda223ce5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d 
+__attribute__((noinline, unused))
+test (__m128d p, int b)
+{
+  return _mm_cvtsi32_sd (p, b); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  int b = 128;
+  double e[2];
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  u.x = test (s.x, b);
+  e[0] = (double)b;
+  e[1] = s.a[1];
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c
new file mode 100644
index 000000000..ee047baa9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtsi2sd-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d 
+__attribute__((noinline, unused))
+test (__m128d p, long long b)
+{
+  return _mm_cvtsi64_sd (p, b); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  long long b = 42949672951333LL;
+  double e[2];
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  u.x = test (s.x, b);
+  e[0] = (double)b;
+  e[1] = s.a[1];
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c
new file mode 100644
index 000000000..eda870d4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvtss2sd-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d 
+__attribute__((noinline, unused))
+test (__m128d a, __m128 b)
+{
+  return _mm_cvtss_sd (a, b); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1;
+  union128 s2;
+  double e[2];
+
+  s1.x = _mm_set_pd (123.321, 456.987);
+  s2.x = _mm_set_ps (123.321, 456.987, 666.45, 231.987);
+
+  u.x = test (s1.x, s2.x);
+
+  e[0] = (double)s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c
new file mode 100644
index 000000000..eebc25950
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttpd2dq-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvttpd_epi32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  union128i_d u;
+  int e[4] = {0};
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  u.x = test (s.x);
+
+  e[0] = (int)s.a[0]; 
+  e[1] = (int)s.a[1]; 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c
new file mode 100644
index 000000000..d80a1a9ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttps2dq-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128 p)
+{
+  return _mm_cvttps_epi32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128 s;
+  union128i_d u;
+  int e[4] = {0};
+
+  s.x = _mm_set_ps (123.321, 456.987, 33.56, 7765.321);
+
+  u.x = test (s.x);
+
+  e[0] = (int)s.a[0]; 
+  e[1] = (int)s.a[1]; 
+  e[2] = (int)s.a[2]; 
+  e[3] = (int)s.a[3]; 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c
new file mode 100644
index 000000000..d04d6d420
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvttsd_si32 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  int e;
+  int d;
+
+  s.x = _mm_set_pd (123.321, 456.987);
+
+  d = test (s.x);
+  e = (int)(s.a[0]);
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c
new file mode 100644
index 000000000..cd913a19f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-cvttsd2si-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_cvttsd_si64 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  long long e;
+  long long d;
+
+  s.x = _mm_set_pd (123.321, 42949672339501.4);
+
+  d = test (s.x);
+  e = (long long)(s.a[0]);
+
+  if (d != e)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c
new file mode 100644
index 000000000..2cf160c9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-divpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_div_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] / s2.a[0];
+  e[1] = s1.a[1] / s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c
new file mode 100644
index 000000000..fb72320d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-divsd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_div_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] / s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-extract-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-extract-1.c
new file mode 100644
index 000000000..f701cee8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-extract-1.c
@@ -0,0 +1,102 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2_runtime } */
+
+extern void abort (void);
+typedef unsigned long long uint64_t;
+
+#define vector(elcount, type)  \
+__attribute__((vector_size((elcount)*sizeof(type)))) type
+
+#define FN(elcount, type, idx) \
+__attribute__((noinline, noclone)) \
+type f##type##elcount##_##idx (vector (elcount, type) x) { return x[idx] + 1; }
+#define T2(elcount, type) \
+  H (elcount, type) \
+  F (elcount, type, 0) \
+  F (elcount, type, 1)
+#define T4(elcount, type) \
+  T2 (elcount, type) \
+  F (elcount, type, 2) \
+  F (elcount, type, 3)
+#define T8(elcount, type) \
+  T4 (elcount, type) \
+  F (elcount, type, 4) \
+  F (elcount, type, 5) \
+  F (elcount, type, 6) \
+  F (elcount, type, 7)
+#define T16(elcount, type) \
+  T8 (elcount, type) \
+  F (elcount, type, 8) \
+  F (elcount, type, 9) \
+  F (elcount, type, 10) \
+  F (elcount, type, 11) \
+  F (elcount, type, 12) \
+  F (elcount, type, 13) \
+  F (elcount, type, 14) \
+  F (elcount, type, 15)
+#define T32(elcount, type) \
+  T16 (elcount, type) \
+  F (elcount, type, 16) \
+  F (elcount, type, 17) \
+  F (elcount, type, 18) \
+  F (elcount, type, 19) \
+  F (elcount, type, 20) \
+  F (elcount, type, 21) \
+  F (elcount, type, 22) \
+  F (elcount, type, 23) \
+  F (elcount, type, 24) \
+  F (elcount, type, 25) \
+  F (elcount, type, 26) \
+  F (elcount, type, 27) \
+  F (elcount, type, 28) \
+  F (elcount, type, 29) \
+  F (elcount, type, 30) \
+  F (elcount, type, 31)
+#define TESTS_SSE2 \
+T2 (2, double) E \
+T2 (2, uint64_t) E \
+T4 (4, float) E \
+T4 (4, int) E \
+T8 (8, short) E \
+T16 (16, char) E
+#define TESTS_AVX \
+T4 (4, double) E \
+T4 (4, uint64_t) E \
+T8 (8, float) E \
+T8 (8, int) E \
+T16 (16, short) E \
+T32 (32, char) E
+#ifdef __AVX__
+#define TESTS TESTS_SSE2 TESTS_AVX
+#else
+#define TESTS TESTS_SSE2
+#endif
+
+#define F FN
+#define H(elcount, type)
+#define E
+TESTS
+
+int
+main ()
+{
+#undef F
+#undef H
+#undef E
+#define H(elcount, type) \
+  vector (elcount, type) v##type##elcount = {
+#define E };
+#define F(elcount, type, idx) idx + 1,
+  TESTS
+#undef F
+#undef H
+#undef E
+#define H(elcount, type)
+#define E
+#define F(elcount, type, idx) \
+  if (f##type##elcount##_##idx (v##type##elcount) != idx + 2) \
+    abort ();
+  TESTS
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c
new file mode 100644
index 000000000..652880046
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v16qi-1.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned char *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned char i[16];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned char *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[3], 0, 0, 0);
+  check (x, v, 3);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[4], 0, 0, 0, 0);
+  check (x, v, 4);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[5], 0, 0, 0, 0, 0);
+  check (x, v, 5);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, v[6], 0, 0, 0, 0, 0, 0);
+  check (x, v, 6);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, v[7], 0, 0, 0, 0, 0, 0, 0);
+  check (x, v, 7);
+}
+
+static void
+sse2_test (void)
+{
+  unsigned char v[16]
+    = { 0x7B, 0x5B, 0x54, 0x65, 0x73, 0x74, 0x56, 0x65,
+	0x63, 0x74, 0x6F, 0x72, 0x5D, 0x53, 0x47, 0x5D };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c
new file mode 100644
index 000000000..ef1863c57
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-1.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned long long *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long i[2];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%llx != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned long long *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi64x (0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi64x (v[1], 0);
+  check (x, v, 1);
+}
+
+static void
+sse2_test (void)
+{
+  unsigned long long v[2]
+    = { 0x7B5B546573745665LL, 0x63746F725D53475DLL };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
new file mode 100644
index 000000000..a2313a4b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v2di-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -msse4 -march=core2 -dp" } */
+
+#include <emmintrin.h>
+
+__m128i
+test (long long b)
+{
+  return _mm_cvtsi64_si128 (b); 
+}
+
+/* { dg-final { scan-assembler-times "vec_concatv2di/3" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c
new file mode 100644
index 000000000..bcb94055c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v4si-1.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned int *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned int *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi32 (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi32 (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi32 (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi32 (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse2_test (void)
+{
+  unsigned int v[4]
+    = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c
new file mode 100644
index 000000000..62734820d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-init-v8hi-1.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned short *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned short i[8];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned short *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi16 (0, 0, 0, 0, 0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi16 (0, 0, 0, 0, 0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi16 (0, 0, 0, 0, 0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi16 (0, 0, 0, 0, v[3], 0, 0, 0);
+  check (x, v, 3);
+  x = _mm_set_epi16 (0, 0, 0, v[4], 0, 0, 0, 0);
+  check (x, v, 4);
+  x = _mm_set_epi16 (0, 0, v[5], 0, 0, 0, 0, 0);
+  check (x, v, 5);
+  x = _mm_set_epi16 (0, v[6], 0, 0, 0, 0, 0, 0);
+  check (x, v, 6);
+  x = _mm_set_epi16 (v[7], 0, 0, 0, 0, 0, 0, 0);
+  check (x, v, 7);
+}
+
+static void
+sse2_test (void)
+{
+  unsigned short v[8]
+    = { 0x7B5B, 0x5465, 0x7374, 0x5665,
+	0x6374, 0x6F72, 0x5D53, 0x475D };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-insvhi.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-insvhi.c
new file mode 100644
index 000000000..03a287042
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-insvhi.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+#include <string.h>
+
+typedef short T __attribute__((may_alias));
+struct S { __m128i d; };
+
+__m128i
+__attribute__((noinline))
+foo (__m128i y, short x)
+{
+  struct S s;
+
+  s.d = y;
+  ((T *) &s.d)[1] = x;
+  return s.d;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned short s[8];
+    } res, val, tmp;
+  unsigned short ins[4] = { 3, 4, 5, 6 };
+
+  val.i[0] = 0x35251505;
+  val.i[1] = 0x75655545;
+  val.i[2] = 0xB5A59585;
+  val.i[3] = 0xF5E5D5C5;
+
+  res.x = foo (val.x, ins[3]);
+
+  tmp.x = val.x;
+  tmp.s[1] = ins[3];
+  if (memcmp (&tmp, &res, sizeof (tmp)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c
new file mode 100644
index 000000000..111e9b274
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-lrint-vec.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+extern long lrint (double);
+
+#define N 32
+
+double a[N] = {0.4,3.5,6.6,9.4,12.5,15.6,18.4,21.5,24.6,27.4,30.5,33.6,36.4,39.5,42.6,45.4,0.5,3.6,6.4,9.5,12.6,15.4,18.5,21.6,24.4,27.5,30.6,33.4,36.5,39.6,42.4,45.5};
+long r[N];
+
+static void
+TEST (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      r[i] = lrint (a[i]);
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (r[i] != lrint (a[i]))
+	abort();
+    }   
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c
new file mode 100644
index 000000000..ee917623c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-lrintf-vec.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+extern long lrintf (float);
+
+#define N 32
+
+float a[N] = {0.4,3.5,6.6,9.4,12.5,15.6,18.4,21.5,24.6,27.4,30.5,33.6,36.4,39.5,42.6,45.4,0.5,3.6,6.4,9.5,12.6,15.4,18.5,21.6,24.4,27.5,30.6,33.4,36.5,39.6,42.4,45.5};
+long r[N];
+
+static void
+TEST (void)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      r[i] = lrintf (a[i]);
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (r[i] != lrintf (a[i]))
+	abort();
+    }   
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c
new file mode 100644
index 000000000..b401c85b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maskmovdqu.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+#ifndef MASK
+#define MASK 0x7986
+#endif
+
+#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 7)
+
+void static
+TEST (void)
+{
+  __m128i src, mask;
+  char s[16] = { 1,-2,3,-4,5,-6,7,-8,9,-10,11,-12,13,-14,15,-16 };
+  char m[16];
+
+  char u[20] = { 0 };
+  int i;
+
+  for (i = 0; i < 16; i++)
+    m[i] = mask_v (i);
+
+  src = _mm_loadu_si128 ((__m128i *)s);
+  mask = _mm_loadu_si128 ((__m128i *)m);
+
+  _mm_maskmoveu_si128 (src, mask, u+3);
+
+  for (i = 0; i < 16; i++)
+    if (u[i+3] != (m[i] ? s[i] : 0))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c
new file mode 100644
index 000000000..f6360c769
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maxpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_max_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0];
+  e[1] = s1.a[1] > s2.a[1] ? s1.a[1]:s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c
new file mode 100644
index 000000000..24377cc25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-maxsd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_max_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] > s2.a[0] ? s1.a[0]:s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c
new file mode 100644
index 000000000..e64091e19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-minpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_min_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0];
+  e[1] = s1.a[1] < s2.a[1] ? s1.a[1]:s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c
new file mode 100644
index 000000000..3c34d98b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-minsd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_min_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] < s2.a[0] ? s1.a[0]:s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mmx.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mmx.c
new file mode 100644
index 000000000..fb226a8e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mmx.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <mmintrin.h>
+
+#define N 4
+
+unsigned long long a[N], b[N], result[N];
+
+unsigned long long check[N] =
+  { 0x101010101010100full,
+    0x1010101010101010ull,
+    0x1010101010101010ull,
+    0x1010101010101010ull };
+
+__m64
+unsigned_add3 (const __m64 * a, const __m64 * b,
+	       __m64 * result, unsigned int count)
+{
+  __m64 _a, _b, one, sum, carry, onesCarry;
+
+  unsigned int i;
+
+  carry = _mm_setzero_si64 ();
+
+  one = _mm_cmpeq_pi8 (carry, carry);
+  one = _mm_sub_si64 (carry, one);
+
+  for (i = 0; i < count; i++)
+    {
+      _a = a[i];
+      _b = b[i];
+
+      sum = _mm_add_si64 (_a, _b);
+      sum = _mm_add_si64 (sum, carry);
+
+      result[i] = sum;
+
+      onesCarry = _mm_and_si64 (_mm_xor_si64 (_a, _b), carry);
+      onesCarry = _mm_or_si64 (_mm_and_si64 (_a, _b), onesCarry);
+      onesCarry = _mm_and_si64 (onesCarry, one);
+
+      _a = _mm_srli_si64 (_a, 1);
+      _b = _mm_srli_si64 (_b, 1);
+
+      carry = _mm_add_si64 (_mm_add_si64 (_a, _b), onesCarry);
+      carry = _mm_srli_si64 (carry, 63);
+    }
+
+  return carry;
+}
+
+void __attribute__((noinline))
+sse2_test (void)
+{
+  unsigned long long carry;
+  int i;
+
+  /* Really long numbers.  */
+  a[3] = a[2] = a[1] = a[0] = 0xd3d3d3d3d3d3d3d3ull;
+  b[3] = b[2] = b[1] = b[0] = 0x3c3c3c3c3c3c3c3cull;
+
+  carry = (unsigned long long) unsigned_add3
+    ((__m64 *)a, (__m64 *)b, (__m64 *)result, N);
+
+  _mm_empty ();
+
+  if (carry != 1)
+    abort ();
+
+  for (i = 0; i < N; i++)
+    if (result [i] != check[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c
new file mode 100644
index 000000000..55d9f594f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movapd-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (double *e)
+{
+  return _mm_load_pd (e); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] __attribute__ ((aligned (16))) = {2134.3343,1234.635654};
+
+  u.x = test (e);   
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c
new file mode 100644
index 000000000..87da33277
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movapd-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m128d a)
+{
+  _mm_store_pd (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] __attribute__ ((aligned (16))) = {0.0};
+
+  u.x = _mm_set_pd (2134.3343,1234.635654);
+
+  test (e, u.x);
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movd-1.c
new file mode 100644
index 000000000..67f0a87ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movd-1.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (int b)
+{
+  return _mm_cvtsi32_si128 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int b = 128;
+  int e[4] = {0};
+
+  u.x = test (b);
+
+  e[0] = b;
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movd-2.c
new file mode 100644
index 000000000..a12787b7a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movd-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128i b)
+{
+  return _mm_cvtsi128_si32 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e;
+
+  u.x = _mm_set_epi32 (2134, -128, 655366, 9999);
+  e = test (u.x);
+  if (e != u.a[0])
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c
new file mode 100644
index 000000000..7599b0523
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqa-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i *p)
+{
+  return _mm_load_si128 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4] __attribute__ ((aligned(16))) = {1, 2, 3, 4};
+   
+  u.x = test ((__m128i *)e); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c
new file mode 100644
index 000000000..ff6c91fda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqa-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (__m128i *p, __m128i a)
+{
+  return _mm_store_si128 (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4] __attribute__ ((aligned(16))) = {0};
+
+  u.x = _mm_set_epi32 (1, 2, 3, 4);
+   
+  test ((__m128i *)e, u.x); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c
new file mode 100644
index 000000000..0688dd9b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqu-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i *p)
+{
+  return _mm_loadu_si128 (p); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4]  = {1, 2, 3, 4};
+   
+  u.x = test ((__m128i *)e); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c
new file mode 100644
index 000000000..20e79eac6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movdqu-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (__m128i *p, __m128i a)
+{
+  return _mm_storeu_si128 (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4]  = {0};
+
+  u.x = _mm_set_epi32 (1, 2, 3, 4);
+   
+  test ((__m128i *)e, u.x); 
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c
new file mode 100644
index 000000000..e906cbc2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movhpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mfpmath=sse -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, double *p)
+{
+  return _mm_loadh_pd (s1, p); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1;
+  double s2[2] = {41124.234,2344.2354};
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  u.x = test (s1.x, s2); 
+
+  e[0] = s1.a[0];
+  e[1] = s2[0];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c
new file mode 100644
index 000000000..e86259acb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movhpd-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mfpmath=sse -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (double *p, __m128d a)
+{
+  return _mm_storeh_pd (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d s;
+  double d[1];
+  double e[1];
+   
+  s.x = _mm_set_pd (2134.3343,1234.635654);
+  test (d, s.x);
+
+  e[0] = s.a[1];
+
+  if (e[0] != d[0])
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c
new file mode 100644
index 000000000..9e7432b35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movlpd-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d a, double *e)
+{
+  return _mm_loadl_pd (a, e); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1;
+  double d[2] = {2134.3343,1234.635654};
+  double e[2];
+
+  s1.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = _mm_loadu_pd (d);
+
+  u.x = test (s1.x, d);  
+
+  e[0] = d[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c
new file mode 100644
index 000000000..1bbb74123
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movlpd-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m128d a)
+{
+  return _mm_storel_pd (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2];
+
+  u.x = _mm_set_pd (41124.234,2344.2354);
+
+  test (e, u.x);  
+
+  e[1] = u.a[1];
+  
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c
new file mode 100644
index 000000000..6a865fe75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movmskpd-1.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128d p)
+{
+  return _mm_movemask_pd (p); 
+}
+
+static void
+TEST (void)
+{
+  double source[2] = {1.234, -2234.23};
+  union128d s1;
+  int d;
+  int e;
+
+  s1.x = _mm_loadu_pd (source);
+
+  d = test (s1.x);
+
+  e = 0;
+  if (source[0] < 0)
+    e |= 1;
+  
+  if (source[1] < 0)
+    e |= 1 << 1;
+
+  if (checkVi (&d, &e, 1))
+    abort ();  
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c
new file mode 100644
index 000000000..4435ad806
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movntdq-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (__m128i *p, __m128i s)
+{
+  return _mm_stream_si128 (p, s); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u;
+  int e[4] __attribute__ ((aligned(16)));
+
+  u.x = _mm_set_epi32 (21, 34, 334, 8567);
+
+  test ((__m128i *)e, u.x);
+  
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c
new file mode 100644
index 000000000..204174ecf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movntpd-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void 
+__attribute__((noinline, unused))
+test (double *p, __m128d s)
+{
+  return _mm_stream_pd (p, s); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] __attribute__ ((aligned(16)));
+   
+  u.x = _mm_set_pd (2134.3343,1234.635654);
+  test (e, u.x); 
+   
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-1.c
new file mode 100644
index 000000000..718b51a41
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i b)
+{
+  return _mm_move_epi64 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1;
+  long long e[2] = {0};
+
+  s1.x = _mm_set_epi64x(12876, 3376590);
+  u.x = test (s1.x);
+  e[0] = s1.a[0];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-2.c
new file mode 100644
index 000000000..e1e9b14cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-2.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (long long b)
+{
+  return _mm_cvtsi64_si128 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u;
+  long long b = 4294967295133LL;
+  long long e[2] = {0};
+
+  u.x = test (b);
+
+  e[0] = b;
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-3.c
new file mode 100644
index 000000000..0a17e3e70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movq-3.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static long long
+__attribute__((noinline, unused))
+test (__m128i b)
+{
+  return _mm_cvtsi128_si64 (b); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u;
+  long long e;
+
+  u.x = _mm_set_epi64x (4294967295133LL, 3844294967295133LL);
+  e = test (u.x);
+  if (e != u.a[0])
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c
new file mode 100644
index 000000000..14342ea86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movsd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (double *p)
+{
+  return _mm_load_sd (p); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double d[2] = {128.023, 3345.1234};
+  double e[2];
+
+  u.x = _mm_loadu_pd (e);
+  u.x = test (d);
+
+  e[0] = d[0];
+  e[1] = 0.0;
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c
new file mode 100644
index 000000000..f1958f09d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movsd-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void 
+__attribute__((noinline, unused))
+test (double *p, __m128d a)
+{
+  _mm_store_sd (p, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double d[1];
+  double e[1];
+
+  u.x = _mm_set_pd (128.023, 3345.1234);
+  test (d, u.x);
+
+  e[0] = u.a[0];
+
+  if (checkVd (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c
new file mode 100644
index 000000000..6533b4c4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movupd-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (double *e)
+{
+  return _mm_loadu_pd (e); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] = {2134.3343,1234.635654};
+
+  u.x = test (e);   
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c
new file mode 100644
index 000000000..c66e70c4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-movupd-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline, unused))
+test (double *e, __m128d a)
+{
+  _mm_storeu_pd (e, a); 
+}
+
+static void
+TEST (void)
+{
+  union128d u;
+  double e[2] = {0.0};
+
+  u.x = _mm_set_pd (2134.3343,1234.635654);
+
+  test (e, u.x);
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mul-1.c
new file mode 100644
index 000000000..9cdc12763
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mul-1.c
@@ -0,0 +1,214 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O3 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <stdlib.h>
+
+/* mingw runtime don't provide random().  */
+#ifdef __MINGW32__
+#define random rand
+#endif
+
+#define N 512
+static short a1[N], a2[N], a3[N];
+static unsigned short b1[N], b2[N], b3[N];
+static int c1[N], c2[N], c3[N];
+static unsigned int d1[N], d2[N], d3[N];
+static long long e1[N], e2[N], e3[N];
+static unsigned long long g1[N], g2[N], g3[N];
+
+__attribute__((noinline, noclone)) void
+f1 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    a1[i] = a2[i] * a3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f2 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    b1[i] = b2[i] * b3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f3 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    c1[i] = c2[i] * c3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f4 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    d1[i] = d2[i] * d3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f5 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    e1[i] = e2[i] * e3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f6 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    g1[i] = g2[i] * g3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f7 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    c1[i] = a2[i] * a3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f8 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    d1[i] = (unsigned int) b2[i] * b3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f9 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    e1[i] = (long long) c2[i] * (long long) c3[i];
+}
+
+__attribute__((noinline, noclone)) void
+f10 (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    g1[i] = (unsigned long long) d2[i] * (unsigned long long) d3[i];
+}
+
+__attribute__((noinline, noclone)) int
+f11 (void)
+{
+  int i, r = 0;
+  for (i = 0; i < N; ++i)
+    r += a2[i] * a3[i];
+  return r;
+}
+
+__attribute__((noinline, noclone)) unsigned int
+f12 (void)
+{
+  int i;
+  unsigned r = 0;
+  for (i = 0; i < N; ++i)
+    r += (unsigned int) b2[i] * b3[i];
+  return r;
+}
+
+__attribute__((noinline, noclone)) long long
+f13 (void)
+{
+  int i;
+  long long r = 0;
+  for (i = 0; i < N; ++i)
+    r += (long long) c2[i] * (long long) c3[i];
+  return r;
+}
+
+__attribute__((noinline, noclone)) unsigned long long
+f14 (void)
+{
+  int i;
+  unsigned long long r = 0;
+  for (i = 0; i < N; ++i)
+    r += (unsigned long long) d2[i] * (unsigned long long) d3[i];
+  return r;
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int s1 = 0;
+  unsigned int s2 = 0;
+  long long s3 = 0;
+  unsigned long long s4 = 0;
+  for (i = 0; i < N; ++i)
+    {
+      asm volatile ("" : : "r" (&s1) : "memory");
+      asm volatile ("" : : "r" (&s2) : "memory");
+      asm volatile ("" : : "r" (&s3) : "memory");
+      asm volatile ("" : : "r" (&s4) : "memory");
+      b2[i] = (int) random ();
+      b3[i] = (int) random ();
+      a2[i] = b2[i];
+      a3[i] = b3[i];
+      d2[i] = (((int) random ()) << 16) | b2[i];
+      d3[i] = (((int) random ()) << 16) | b3[i];
+      c2[i] = d2[i];
+      c3[i] = d3[i];
+      s1 += a2[i] * a3[i];
+      s2 += (unsigned int) b2[i] * b3[i];
+      s3 += (long long) c2[i] * (long long) c3[i];
+      s4 += (unsigned long long) d2[i] * (unsigned long long) d3[i];
+    }
+  f1 ();
+  f2 ();
+  f3 ();
+  f4 ();
+  f5 ();
+  f6 ();
+  for (i = 0; i < N; ++i)
+    {
+      if (a1[i] != (short) (a2[i] * a3[i]))
+	abort ();
+      if (b1[i] != (unsigned short) (b2[i] * b3[i]))
+	abort ();
+      if (c1[i] != c2[i] * c3[i])
+	abort ();
+      if (d1[i] != d2[i] * d3[i])
+	abort ();
+      if (e1[i] != e2[i] * e3[i])
+	abort ();
+      if (g1[i] != g2[i] * g3[i])
+	abort ();
+    }
+  f7 ();
+  f8 ();
+  f9 ();
+  f10 ();
+  for (i = 0; i < N; ++i)
+    {
+      if (c1[i] != a2[i] * a3[i])
+	abort ();
+      if (d1[i] != b2[i] * b3[i])
+	abort ();
+      if (e1[i] != (long long) c2[i] * (long long) c3[i])
+	abort ();
+      if (g1[i] != (unsigned long long) d2[i] * (unsigned long long) d3[i])
+	abort ();
+    }
+  if (f11 () != s1 || f12 () != s2 || f13 () != s3 || f14 () != s4)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c
new file mode 100644
index 000000000..737730e6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mulpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_mul_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[1] * s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c
new file mode 100644
index 000000000..777b439f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-mulsd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_mul_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c
new file mode 100644
index 000000000..1d88474aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-orpd-1.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_or_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+
+  union
+  {
+     double d[2];
+     long long ll[2];
+  }d1, d2, e;
+
+  s1.x = _mm_set_pd (1234, 44386);
+  s2.x = _mm_set_pd (5198, 23098);
+
+  _mm_storeu_pd (d1.d, s1.x);
+  _mm_storeu_pd (d2.d, s2.x);
+
+  u.x = test (s1.x, s2.x);
+  
+  e.ll[0] = d1.ll[0] | d2.ll[0];
+  e.ll[1] = d1.ll[1] | d2.ll[1];
+
+  if (check_union128d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c
new file mode 100644
index 000000000..187b880db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packssdw-1.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_packs_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d s1, s2;
+  union128i_w u;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi32 (2134, -128, 655366, 9999);
+  s2.x = _mm_set_epi32 (41124, 234, 2, -800900);
+  u.x = test (s1.x, s2.x); 
+
+  for (i = 0; i < 4; i++)
+    {
+      if (s1.a[i] > 32767)
+        e[i] = 32767;
+      else if (s1.a[i] < -32768)
+        e[i] = -32768;
+      else
+        e[i] = s1.a[i];
+    }
+  
+  for (i = 0; i < 4; i++)
+   {
+      if (s2.a[i] > 32767)
+        e[i+4] = 32767;
+      else if (s2.a[i] < -32768)
+        e[i+4] = -32768;
+      else
+        e[i+4] = s2.a[i];
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c
new file mode 100644
index 000000000..3643a8ac8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packsswb-1.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_packs_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w s1, s2;
+  union128i_b u;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi16 (2134, -128, 1234, 6354, 1002, 3004, 4050, 9999);
+  s2.x = _mm_set_epi16 (41124, 234, 2344, 2354, 607, 1, 2, -8009);
+  u.x = test (s1.x, s2.x); 
+
+  for (i = 0; i < 8; i++)
+    {
+      if (s1.a[i] > 127)
+        e[i] = 127;
+      else if (s1.a[i] < -128)
+        e[i] = -128;
+      else
+        e[i] = s1.a[i];
+    }
+  
+  for (i = 0; i < 8; i++)
+   {
+      if (s2.a[i] > 127)
+        e[i+8] = 127;
+      else if (s2.a[i] < -128)
+        e[i+8] = -128;
+      else
+        e[i+8] = s2.a[i];
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c
new file mode 100644
index 000000000..6fd00ae6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-packuswb-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_packus_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w s1, s2;
+  union128i_ub u;
+  unsigned char e[16];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (1, 2, 3, 4, -5, -6, -7, -8);
+  s2.x = _mm_set_epi16 (-9, -10, -11, -12, 13, 14, 15, 16);
+  u.x = test (s1.x, s2.x); 
+
+  for (i=0; i<8; i++)
+    {
+      tmp = s1.a[i]<0 ? 0 : s1.a[i];
+      tmp = tmp>255 ? 255 : tmp;
+      e[i] = tmp;
+
+      tmp = s2.a[i]<0 ? 0 : s2.a[i];
+      tmp = tmp>255 ? 255 : tmp;
+      e[i+8] = tmp;
+    }
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c
new file mode 100644
index 000000000..faea05cfc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddb-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_add_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c
new file mode 100644
index 000000000..0c910c8cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_add_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (30,90,-80,-40);
+  s2.x = _mm_set_epi32 (76, -100, -34, -78);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+     e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c
new file mode 100644
index 000000000..136397818
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddq-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_add_epi64 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1, s2;
+  long long e[2];
+  int i;
+   
+  s1.x = _mm_set_epi64x (90,-80);
+  s2.x = _mm_set_epi64x (76, -100);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 2; i++)
+     e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c
new file mode 100644
index 000000000..6b2195e66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddsb-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_adds_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+
+      if (tmp > 127)
+        tmp = 127;
+      if (tmp < -128)
+        tmp = -128;
+
+      e[i] = tmp;
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c
new file mode 100644
index 000000000..5fec2f2a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddsw-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_adds_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+      
+      if (tmp > 32767)
+        tmp = 32767;
+      if (tmp < -32768)
+        tmp = -32768;
+      
+      e[i] = tmp;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c
new file mode 100644
index 000000000..807287e27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddusb-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_adds_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16] = {0};
+  int i, tmp;
+   
+  s1.x = _mm_set_epi8 (30, 2,  3,  4,  10, 20, 30, 90,   80, 40, 100, 15, 98, 25, 98, 7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100,  34, 78, 39,   6,  3,  4,  5,  119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+
+      if (tmp > 255)
+        tmp = -1;
+      if (tmp < 0)
+        tmp = 0; 
+
+      e[i] = tmp; 
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c
new file mode 100644
index 000000000..90a226950
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddusw-1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_adds_epu16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,80,40,100,15);
+  s2.x = _mm_set_epi16 (11, 98, 76, 100, 34, 78, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] + s2.a[i];
+      
+      if (tmp > 65535)
+        tmp = -1;
+
+      if (tmp < 0)
+        tmp = 0;
+      
+      e[i] = tmp;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c
new file mode 100644
index 000000000..3ed73299b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-paddw-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_add_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = s1.a[i] + s2.a[i];
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pand-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pand-1.c
new file mode 100644
index 000000000..a6a1702d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pand-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_and_si128 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = s1.a[i] & s2.a[i];
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c
new file mode 100644
index 000000000..d9c653fd5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pandn-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_andnot_si128 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = (~s1.a[i]) & s2.a[i];
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c
new file mode 100644
index 000000000..98b489437
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pavgb-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_avg_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub u, s1, s2;
+  unsigned char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = (s1.a[i] + s2.a[i]+1)>>1;
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c
new file mode 100644
index 000000000..4f9bf2199
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pavgw-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_avg_epu16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_uw u, s1, s2;
+  unsigned short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,80,40,100,15);
+  s2.x = _mm_set_epi16 (11, 98, 76, 100, 34, 78, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = (s1.a[i] + s2.a[i]+1)>>1;
+
+  if (check_union128i_uw (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c
new file mode 100644
index 000000000..7db34ba15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqb-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpeq_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = (s1.a[i] == s2.a[i]) ? -1:0;
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c
new file mode 100644
index 000000000..d4018925f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpeq_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (98, 25, 98,7);
+  s2.x = _mm_set_epi32 (88, 44, 33, 229);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+     e[i] = (s1.a[i] == s2.a[i]) ? -1:0;
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c
new file mode 100644
index 000000000..f3415831e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpeqw-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpeq_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (20,30,90,80,40,100,15,98);
+  s2.x = _mm_set_epi16 (34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = (s1.a[i] == s2.a[i]) ? -1:0;
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c
new file mode 100644
index 000000000..34c74e8e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtb-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpgt_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = (s1.a[i] > s2.a[i]) ? -1:0;
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c
new file mode 100644
index 000000000..8d0353636
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpgt_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (98, 25, 98,7);
+  s2.x = _mm_set_epi32 (88, 44, 33, 229);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+     e[i] = (s1.a[i] > s2.a[i]) ? -1:0;
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c
new file mode 100644
index 000000000..835ba365b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pcmpgtw-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_cmpgt_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (20,30,90,80,40,100,15,98);
+  s2.x = _mm_set_epi16 (34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = (s1.a[i] > s2.a[i]) ? -1:0;
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c
new file mode 100644
index 000000000..16167437c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pinsrw.c
@@ -0,0 +1,86 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -msse2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+#define msk4 0x04
+#define msk5 0x05
+#define msk6 0x06
+#define msk7 0x07
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned short s[8];
+    } res [8], val, tmp;
+  int masks[8];
+  unsigned short ins[4] = { 3, 4, 5, 6 };
+  int i;
+
+  val.i[0] = 0x35251505;
+  val.i[1] = 0x75655545;
+  val.i[2] = 0xB5A59585;
+  val.i[3] = 0xF5E5D5C5;
+
+  /* Check pinsrw imm8, r32, xmm.  */
+  res[0].x = _mm_insert_epi16 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi16 (val.x, ins[0], msk1);
+  res[2].x = _mm_insert_epi16 (val.x, ins[0], msk2);
+  res[3].x = _mm_insert_epi16 (val.x, ins[0], msk3);
+  res[4].x = _mm_insert_epi16 (val.x, ins[0], msk4);
+  res[5].x = _mm_insert_epi16 (val.x, ins[0], msk5);
+  res[6].x = _mm_insert_epi16 (val.x, ins[0], msk6);
+  res[7].x = _mm_insert_epi16 (val.x, ins[0], msk7);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+
+  for (i = 0; i < 8; i++)
+    {
+      tmp.x = val.x;
+      tmp.s[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrw imm8, m16, xmm.  */
+  for (i = 0; i < 8; i++)
+    {
+      res[i].x = _mm_insert_epi16 (val.x, ins[i % 2], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 8; i++)
+    {
+      tmp.x = val.x;
+      tmp.s[masks[i]] = ins[i % 2];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c
new file mode 100644
index 000000000..c26d02b39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaddwd-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_madd_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w  s1, s2;
+  union128i_d u;
+  int e[4]; 
+  int i; 
+ 
+  s1.x = _mm_set_epi16 (2134,3343,1234,6354, 1, 3, 4, 5);
+  s2.x = _mm_set_epi16 (41124,234,2344,2354,9, -1, -8, -10);
+  u.x = test (s1.x, s2.x); 
+
+  for (i = 0; i < 4; i++)
+    e[i] = (s1.a[i*2] * s2.a[i*2])+(s1.a[(i*2) + 1] * s2.a[(i*2) + 1]);   
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c
new file mode 100644
index 000000000..836f2c6d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaxsw-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_max_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (1,2,3,4,5,6,7,8);
+  s2.x = _mm_set_epi16 (8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i=0; i<8; i++)
+    e[i] = s1.a[i]>s2.a[i]?s1.a[i]:s2.a[i]; 
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c
new file mode 100644
index 000000000..6447aa30b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmaxub-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_max_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub u, s1, s2;
+  unsigned char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16);
+  s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i=0; i<16; i++)
+    e[i] = s1.a[i]>s2.a[i]?s1.a[i]:s2.a[i]; 
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c
new file mode 100644
index 000000000..5c553d1b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pminsw-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_min_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (1,2,3,4,5,6,7,8);
+  s2.x = _mm_set_epi16 (8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i=0; i<8; i++)
+    e[i] = s1.a[i]<s2.a[i]?s1.a[i]:s2.a[i]; 
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c
new file mode 100644
index 000000000..6c4598cc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pminub-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_min_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub u, s1, s2;
+  unsigned char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16);
+  s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i=0; i<16; i++)
+    e[i] = s1.a[i]<s2.a[i]?s1.a[i]:s2.a[i]; 
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c
new file mode 100644
index 000000000..fce068c09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmovmskb-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_movemask_epi8 (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b s1;
+  int i, u, e=0;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  u = test (s1.x); 
+  
+  for (i = 0; i < 16; i++)
+    if (s1.a[i] & (1<<7))
+      e = e | (1<<i);
+
+  if (checkVi (&u, &e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c
new file mode 100644
index 000000000..f77ec6afd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmulhuw-1.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_mulhi_epu16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_uw u, s1, s2;
+  unsigned short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,2067,3033,90,80,40,1000,15);
+  s2.x = _mm_set_epi16 (11, 9834, 7444, 10222, 34, 7833, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] * s2.a[i];
+    
+      e[i] = (tmp & 0xffff0000)>>16;
+    }
+
+  if (check_union128i_uw (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c
new file mode 100644
index 000000000..ac3838930
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmulhw-1.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_mulhi_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,2067,-3033,90,80,40,-1000,15);
+  s2.x = _mm_set_epi16 (11, 9834, 7444, -10222, 34, -7833, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] * s2.a[i];
+    
+      e[i] = (tmp & 0xffff0000)>>16;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c
new file mode 100644
index 000000000..38014b788
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmullw-1.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_mullo_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,2067,-3033,90,80,40,-1000,15);
+  s2.x = _mm_set_epi16 (11, 9834, 7444, -10222, 34, -7833, 39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] * s2.a[i];
+    
+      e[i] = tmp;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c
new file mode 100644
index 000000000..51540c143
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pmuludq-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_mul_epu32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d s1, s2;
+  union128i_q u;
+  long long e[2];
+   
+  s1.x = _mm_set_epi32 (10,2067,3033,905);
+  s2.x = _mm_set_epi32 (11, 9834, 7444, 10222);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] * s2.a[0];
+  e[1] = s1.a[2] * s2.a[2];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-por-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-por-1.c
new file mode 100644
index 000000000..a5a0183bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-por-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_or_si128 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      e[i] = s1.a[i] | s2.a[i];
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c
new file mode 100644
index 000000000..83e83cb16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psadbw-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sad_epu8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub s1, s2;
+  union128i_w u;
+  short e[8] = {0};
+  unsigned char tmp[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16);
+  s2.x = _mm_set_epi8 (16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1);
+  u.x = test (s1.x, s2.x);
+
+  for (i = 0; i < 16; i++)
+    tmp [i] = __builtin_abs (s1.a[i] - s2.a[i]);
+
+  for (i = 0; i < 8; i++)
+    e[0] += tmp[i];
+
+  for (i = 8; i < 16; i++)
+    e[4] += tmp[i]; 
+
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c
new file mode 100644
index 000000000..b0f8834c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshufd-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xec
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_shuffle_epi32 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1;
+  int e[4] = {0};
+  int i;
+   
+  s1.x = _mm_set_epi32 (16,15,14,13);
+  u.x = test (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = s1.a[((N & (0x3<<(2*i)))>>(2*i))];
+
+  if (check_union128i_d(u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c
new file mode 100644
index 000000000..cfff7577d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshufhw-1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xec
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_shufflehi_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q s1;
+  union128i_w u;
+  short  e[8] = {0};
+  int i;
+  int m1[4] = {0x3, 0x3<<2, 0x3<<4, 0x3<<6};
+  int m2[4];
+  
+  s1.x = _mm_set_epi64x (0xabcde,0xef58a234);
+  u.x = test (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (s1.a[0]>>(16 * i)) & 0xffff;
+
+  for (i = 0; i < 4; i++)
+    m2[i] = (N & m1[i])>>(2*i);
+
+  for (i = 0; i < 4; i++)
+    e[i+4] = (s1.a[1] >> (16 * m2[i])) & 0xffff;
+
+  if (check_union128i_w(u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c
new file mode 100644
index 000000000..9915ca4ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pshuflw-1.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xec
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_shufflelo_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q s1;
+  union128i_w u;
+  short  e[8] = {0};
+  int i;
+  int m1[4] = {0x3, 0x3<<2, 0x3<<4, 0x3<<6};
+  int m2[4];
+  
+  s1.x = _mm_set_epi64x (0xabcde,0xef58a234);
+  u.x = test (s1.x);
+
+  for (i = 0; i < 4; i++)
+    e[i+4] = (s1.a[1]>>(16 * i)) & 0xffff;
+
+  for (i = 0; i < 4; i++)
+    m2[i] = (N & m1[i])>>(2*i);
+
+  for (i = 0; i < 4; i++)
+    e[i] = (s1.a[0] >> (16 * m2[i])) & 0xffff;
+
+  if (check_union128i_w(u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c
new file mode 100644
index 000000000..31474e323
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslld-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xf
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_slli_epi32 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  int e[4] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+
+  u.x = test (s.x);
+
+  if (N < 32)
+    for (i = 0; i < 4; i++)
+      e[i] = s.a[i] << N; 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c
new file mode 100644
index 000000000..17411415b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslld-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_sll_epi32 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  union128i_q c;
+  int e[4] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi32 (2, -3, 0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 23);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 32)
+    for (i = 0; i < 4; i++)
+      e[i] = s.a[i] << c.a[0]; 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c
new file mode 100644
index 000000000..2d4dc1b9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pslldq-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0x5
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_slli_si128 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s;
+  char src[16] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
+  char e[16] = {0};
+  int i;
+   
+  s.x = _mm_loadu_si128 ((__m128i *)src);
+
+  u.x = test (s.x);
+
+  for (i = 0; i < 16-N; i++)
+    e[i+N] = src[i];
+
+  if (check_union128i_b (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c
new file mode 100644
index 000000000..a07cfc4da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllq-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 60
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_slli_epi64 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s;
+  long long e[2] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi64x (-1, 0xf);
+
+  u.x = test (s.x);
+
+  if (N < 64)
+    for (i = 0; i < 2; i++)
+      e[i] = s.a[i] << N; 
+
+  if (check_union128i_q (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c
new file mode 100644
index 000000000..6792fd325
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllq-2.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_sll_epi64 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s, c;
+  long long e[2] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi64x (-1, 0xf);
+  c.x = _mm_set_epi64x (60,50);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 64)
+    for (i = 0; i < 2; i++)
+      e[i] = s.a[i] << c.a[0]; 
+
+  if (check_union128i_q (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c
new file mode 100644
index 000000000..3153ec455
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllw-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xb
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_slli_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  short e[8] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, 2, 3, 4, 5, 6, 0x7000, 0x9000);
+
+  u.x = test (s.x);
+
+  if (N < 16)
+    for (i = 0; i < 8; i++)
+      e[i] = s.a[i] << N; 
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c
new file mode 100644
index 000000000..e3170405e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psllw-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_sll_epi16 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  union128i_q c;
+  short e[8] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, 2, 3, 4, 5, 6, 0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 13);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 16)
+    for (i = 0; i < 8; i++)
+      e[i] = s.a[i] << c.a[0]; 
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c
new file mode 100644
index 000000000..ea27439ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrad-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xf
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srai_epi32 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  int e[4] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+
+  u.x = test (s.x);
+
+  if (N < 32)
+    for (i = 0; i < 4; i++)
+      e[i] = s.a[i] >> N; 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c
new file mode 100644
index 000000000..0b8d5b888
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrad-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i count)
+{
+  return _mm_sra_epi32 (s1, count); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  union128i_q c;
+  int e[4] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+  c.x = _mm_set_epi64x (16, 29);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 32)
+    for (i = 0; i < 4; i++)
+      e[i] = s.a[i] >> c.a[0]; 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c
new file mode 100644
index 000000000..49db1b2c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psraw-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xb
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srai_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  short e[8] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, -2, 3, 4, -5, 6, 0x7000, 0x9000);
+
+  u.x = test (s.x);
+
+  if (N < 16)
+    for (i = 0; i < 8; i++)
+      e[i] = s.a[i] >> N; 
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c
new file mode 100644
index 000000000..8aa6681b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psraw-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_sra_epi16 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  union128i_q c;
+  short e[8] = {0};
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, -2, 3, 4, 5, 6, -0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 13);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 16)
+    for (i = 0; i < 8; i++)
+      e[i] = s.a[i] >> c.a[0]; 
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c
new file mode 100644
index 000000000..d310fc452
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrld-1.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xf
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srli_epi32 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  int e[4] = {0};
+  unsigned int tmp;
+  int i;
+ 
+  s.x = _mm_set_epi32 (1, -2, 3, 4);
+
+  u.x = test (s.x);
+
+  if (N < 32)
+    for (i = 0; i < 4; i++) {
+      tmp  = s.a[i];
+      e[i] = tmp >> N; 
+    }
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c
new file mode 100644
index 000000000..a5ddce1f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrld-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_srl_epi32 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s;
+  union128i_q c;
+  int e[4] = {0};
+  unsigned int tmp;
+  int i;
+ 
+  s.x = _mm_set_epi32 (2, -3, 0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 23);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 32)
+    for (i = 0; i < 4; i++) {
+      tmp = s.a[i];
+      e[i] = tmp >> c.a[0];
+    } 
+
+  if (check_union128i_d (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c
new file mode 100644
index 000000000..c4484bc30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrldq-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0x5
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srli_si128 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s;
+  char src[16] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
+  char e[16] = {0};
+  int i;
+   
+  s.x = _mm_loadu_si128 ((__m128i *)src);
+
+  u.x = test (s.x);
+
+  for (i = 0; i < 16-N; i++)
+    e[i] = src[i+N];
+
+  if (check_union128i_b (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c
new file mode 100644
index 000000000..12ace3775
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlq-1.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 60
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srli_epi64 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s;
+  long long e[2] = {0};
+  unsigned long long tmp;
+  int i;
+ 
+  s.x = _mm_set_epi64x (-1, 0xf);
+
+  u.x = test (s.x);
+
+  if (N < 64)
+    for (i = 0; i < 2; i++) {
+      tmp = s.a[i]; 
+      e[i] = tmp >> N;
+    }
+
+  if (check_union128i_q (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c
new file mode 100644
index 000000000..ee4fb0472
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlq-2.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_srl_epi64 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s, c;
+  long long e[2] = {0};
+  unsigned long long tmp;
+  int i;
+ 
+  s.x = _mm_set_epi64x (-1, 0xf);
+  c.x = _mm_set_epi64x (60,50);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 64)
+    for (i = 0; i < 2; i++){
+      tmp = s.a[i];
+      e[i] =tmp >> c.a[0];
+    } 
+
+  if (check_union128i_q (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c
new file mode 100644
index 000000000..d51ee45ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlw-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xb
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1)
+{
+  return _mm_srli_epi16 (s1, N); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  short e[8] = {0};
+  unsigned short tmp;
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, -2, 3, -4, 5, 6, 0x7000, 0x9000);
+
+  u.x = test (s.x);
+
+  if (N < 16)
+    for (i = 0; i < 8; i++)
+      {
+        tmp = s.a[i];
+        e[i] = tmp >> N;
+      }
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c
new file mode 100644
index 000000000..0d4004c3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psrlw-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i c)
+{
+  return _mm_srl_epi16 (s1, c); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s;
+  union128i_q c;
+  short e[8] = {0};
+  unsigned short tmp;
+  int i;
+ 
+  s.x = _mm_set_epi16 (1, -2, 3, 4, 5, 6, -0x7000, 0x9000);
+  c.x = _mm_set_epi64x (12, 13);
+
+  u.x = test (s.x, c.x);
+
+  if (c.a[0] < 16)
+    for (i = 0; i < 8; i++)
+      {
+        tmp = s.a[i];
+        e[i] = tmp >> c.a[0];
+      }
+
+  if (check_union128i_w (u, e))
+    abort (); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c
new file mode 100644
index 000000000..a416f57a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubb-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sub_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+     e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c
new file mode 100644
index 000000000..9700a7791
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubd-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sub_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (30,90,-80,-40);
+  s2.x = _mm_set_epi32 (76, -100, -34, -78);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+     e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c
new file mode 100644
index 000000000..a31ec689c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubq-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sub_epi64 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1, s2;
+  long long e[2];
+  int i;
+   
+  s1.x = _mm_set_epi64x (90,-80);
+  s2.x = _mm_set_epi64x (76, -100);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 2; i++)
+     e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c
new file mode 100644
index 000000000..88308cb10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubsb-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_subs_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 16; i++)
+    {
+      tmp = s1.a[i] - s2.a[i];
+
+      if (tmp > 127)
+        tmp = 127;
+      if (tmp < -128)
+        tmp = -128;
+
+      e[i] = tmp;
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c
new file mode 100644
index 000000000..a0f421538
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubsw-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_subs_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i, tmp;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      tmp = s1.a[i] - s2.a[i];
+      
+      if (tmp > 32767)
+        tmp = 32767;
+      if (tmp < -32768)
+        tmp = -32768;
+      
+      e[i] = tmp;
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c
new file mode 100644
index 000000000..dbf08ade1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-psubw-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_sub_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+     e[i] = s1.a[i] - s2.a[i];
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c
new file mode 100644
index 000000000..33f30202d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhbw-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      e[2*i] = s1.a[8+i];
+      e[2*i + 1] = s2.a[8+i];
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c
new file mode 100644
index 000000000..26689aa43
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhdq-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (10,20,-80,-40);
+  s2.x = _mm_set_epi32 (11, -34, -78, -39);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 2; i++)
+    {
+      e[2*i] = s1.a[2+i];
+      e[2*i+1] = s2.a[2+i];
+    }
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c
new file mode 100644
index 000000000..4dbd46bda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhqdq-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi64 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1, s2;
+  long long  e[2];
+   
+  s1.x = _mm_set_epi64x (10,-40);
+  s2.x = _mm_set_epi64x (1134, -7839);
+  u.x = test (s1.x, s2.x); 
+  
+  e[0] = s1.a[1];
+  e[1] = s2.a[1];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c
new file mode 100644
index 000000000..11fd91e20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckhwd-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+    {
+      e[2*i] = s1.a[4+i];
+      e[2*i+1] = s2.a[4+i];
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c
new file mode 100644
index 000000000..d3d5a71aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklbw-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi8 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_b u, s1, s2;
+  char e[16];
+  int i;
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,-80,-40,-100,-15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, -100, -34, -78, -39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 8; i++)
+    {
+      e[2*i] = s1.a[i];
+      e[2*i + 1] = s2.a[i];
+    }
+
+  if (check_union128i_b (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c
new file mode 100644
index 000000000..c24ee1ee5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpckldq-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi32 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_d u, s1, s2;
+  int e[4];
+  int i;
+   
+  s1.x = _mm_set_epi32 (10,20,-80,-40);
+  s2.x = _mm_set_epi32 (11, -34, -78, -39);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 2; i++)
+    {
+      e[2*i] = s1.a[i];
+      e[2*i+1] = s2.a[i];
+    }
+
+  if (check_union128i_d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c
new file mode 100644
index 000000000..ce9b88599
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklqdq-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi64 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_q u, s1, s2;
+  long long  e[2];
+   
+  s1.x = _mm_set_epi64x (10,-40);
+  s2.x = _mm_set_epi64x (1134, -7839);
+  u.x = test (s1.x, s2.x); 
+  
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+
+  if (check_union128i_q (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c
new file mode 100644
index 000000000..6736186a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-punpcklwd-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi16 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_w u, s1, s2;
+  short e[8];
+  int i;
+   
+  s1.x = _mm_set_epi16 (10,20,30,90,-80,-40,-100,-15);
+  s2.x = _mm_set_epi16 (11, 98, 76, -100, -34, -78, -39, 14);
+  u.x = test (s1.x, s2.x); 
+   
+  for (i = 0; i < 4; i++)
+    {
+      e[2*i] = s1.a[i];
+      e[2*i+1] = s2.a[i];
+    }
+
+  if (check_union128i_w (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c
new file mode 100644
index 000000000..c9d2b90b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-pxor-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128i
+__attribute__((noinline, unused))
+test (__m128i s1, __m128i s2)
+{
+  return _mm_xor_si128 (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128i_ub u, s1, s2;
+  unsigned char e[16] = {0};
+  int i; 
+   
+  s1.x = _mm_set_epi8 (1,2,3,4,10,20,30,90,80,40,100,15,98, 25, 98,7);
+  s2.x = _mm_set_epi8 (88, 44, 33, 22, 11, 98, 76, 100, 34, 78, 39, 6, 3, 4, 5, 119);
+  u.x = test (s1.x, s2.x); 
+ 
+  for (i = 0; i < 16; i++)
+    e[i] = s1.a[i] ^ s2.a[i];
+
+  if (check_union128i_ub (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c
new file mode 100644
index 000000000..c1f5d0f74
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-epi32-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+test (unsigned int *v)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_epi32 (v[3], v[2], v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.i[i])
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse2_test (void)
+{
+  unsigned int v[4]
+    = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c
new file mode 100644
index 000000000..ac32015a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-epi64x-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+test (unsigned long long *v)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long i[2];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_epi64x (v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.i[i])
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse2_test (void)
+{
+  unsigned long long v[2]
+    = { 0x7B5B546573745665LL, 0x63746F725D53475DLL };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c
new file mode 100644
index 000000000..cc0af7c9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v16qi-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c
new file mode 100644
index 000000000..01f2699b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v16qi-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c
new file mode 100644
index 000000000..3c3ae26fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v16qi-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v16qi-3.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c
new file mode 100644
index 000000000..e4231a4f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c
new file mode 100644
index 000000000..b2a8778db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-1a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c
new file mode 100644
index 000000000..2d500b791
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c
new file mode 100644
index 000000000..1afe68bcf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-set-v8hi-2a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mtune=core2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#define CHECK_H "sse2-check.h"
+#define TEST sse2_test
+
+#include "set-v8hi-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c
new file mode 100644
index 000000000..0a05680a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-shufpd-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define N 0xab
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_shuffle_pd (s1, s2, N); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2] = {0.0};
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (453.345635,54646.464356);
+  u.x = test (s1.x, s2.x);
+
+  e[0] = (N & (1 << 0)) ? s1.a[1] : s1.a[0];
+  e[1] = (N & (1 << 1)) ? s2.a[1] : s2.a[0];
+
+  if (check_union128d(u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c
new file mode 100644
index 000000000..6095aaa29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-shufps-1.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#define MASK 0xab
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+float select4(const float *src, unsigned int control)
+{
+    switch(control) {
+    case 0:
+        return src[0];
+    case 1:
+        return src[1];
+    case 2:
+        return src[2];
+    case 3:
+        return src[3];
+    }
+    return -1;
+}
+
+static __m128
+__attribute__((noinline, unused))
+test (__m128 s1, __m128 s2)
+{
+  return _mm_shuffle_ps (s1, s2, MASK); 
+}
+
+static void
+TEST (void)
+{
+  union128 u, s1, s2;
+  float e[4] = {0.0};
+   
+  s1.x = _mm_set_ps (1.1, 1.2, 1.3, 1.4);
+  s2.x = _mm_set_ps (2.1, 2.2, 2.3, 2.4);
+  u.x = test (s1.x, s2.x);
+
+  e[0] = select4(s1.a,   (MASK >> 0) & 0x3);
+  e[1] = select4(s1.a,   (MASK >> 2) & 0x3);
+  e[2] = select4(s2.a,   (MASK >> 4) & 0x3);
+  e[3] = select4(s2.a,   (MASK >> 6) & 0x3);
+
+  if (check_union128(u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c
new file mode 100644
index 000000000..edbf829e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-sqrtpd-1.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+#include <math.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1)
+{
+  return _mm_sqrt_pd (s1); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1;
+  double e[2];
+  int i;
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  u.x = test (s1.x); 
+
+  for (i = 0; i < 2; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s1.a[i]);
+      tmp = _mm_sqrt_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c
new file mode 100644
index 000000000..6a91e218a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-subpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_sub_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] - s2.a[0];
+  e[1] = s1.a[1] - s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c
new file mode 100644
index 000000000..954f81ad5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-subsd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_sub_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0] - s2.a[0];
+  e[1] = s1.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c
new file mode 100644
index 000000000..0bf8708f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-1.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomieq_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,2344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] == s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c
new file mode 100644
index 000000000..fd566f059
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-2.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomilt_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] < s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c
new file mode 100644
index 000000000..df9e09bce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-3.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomile_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1] = {0};
+  int e[1] = {0};
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] <= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c
new file mode 100644
index 000000000..f65572a4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-4.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomigt_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] > s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c
new file mode 100644
index 000000000..b08c4416b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-5.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomige_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] >= s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c
new file mode 100644
index 000000000..bb0bee579
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-ucomisd-6.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static int 
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_ucomineq_sd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d s1, s2;
+  int d[1];
+  int e[1];
+ 
+  s1.x = _mm_set_pd (2134.3343,12344.2354);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  d[0] = test (s1.x, s2.x); 
+  e[0] = s1.a[0] != s2.a[0];
+
+  if (checkVi (d, e, 1))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c
new file mode 100644
index 000000000..a2676396c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpack-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i
+foo1 (__m128i s1, __m128i s2)
+{
+  return _mm_unpackhi_epi64 (s1, s2); 
+}
+
+__m128i
+foo2 (__m128i s1, __m128i s2)
+{
+  return _mm_unpacklo_epi64 (s1, s2); 
+}
+
+/* { dg-final { scan-assembler "punpcklqdq" } } */
+/* { dg-final { scan-assembler "punpckhqdq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c
new file mode 100644
index 000000000..a07302c4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpckhpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_unpackhi_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[1];
+  e[1] = s2.a[1];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c
new file mode 100644
index 000000000..3562edc6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-unpcklpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_unpacklo_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union128d u, s1, s2;
+  double e[2];
+   
+  s1.x = _mm_set_pd (2134.3343,1234.635654);
+  s2.x = _mm_set_pd (41124.234,2344.2354);
+  u.x = test (s1.x, s2.x); 
+   
+  e[0] = s1.a[0];
+  e[1] = s2.a[0];
+
+  if (check_union128d (u, e))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-1.c
new file mode 100644
index 000000000..ab2ca5b22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-1.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+#define msk0   0
+#define msk1   1
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128d x;
+      double d[2];
+    } val1;
+  double res[2];
+  int masks[2];
+  int i;
+
+  val1.d[0] = 23.;
+  val1.d[1] = 45;
+
+  res[0] = __builtin_ia32_vec_ext_v2df ((__v2df)val1.x, msk0);
+  res[1] = __builtin_ia32_vec_ext_v2df ((__v2df)val1.x, msk1);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+
+  for (i = 0; i < 2; i++)
+    if (res[i] != val1.d [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-2.c
new file mode 100644
index 000000000..6f5c514aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1;
+  long long res[2];
+  int masks[2];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0] = __builtin_ia32_vec_ext_v2di ((__v2di)val1.x, 0);
+  res[1] = __builtin_ia32_vec_ext_v2di ((__v2di)val1.x, 1);
+
+  for (i = 0; i < 2; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 2; i++)
+    if (res[i] != val1.ll [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-2a.c
new file mode 100644
index 000000000..f230f27d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-2a.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2 -mtune=atom" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-vec-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-3.c
new file mode 100644
index 000000000..fa18de5a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-3.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1;
+  int res[4];
+  int masks[4];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 0);
+  res[1] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 1);
+  res[2] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 2);
+  res[3] = __builtin_ia32_vec_ext_v4si ((__v4si)val1.x, 3);
+
+  for (i = 0; i < 4; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 4; i++)
+    if (res[i] != val1.i [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-4.c
new file mode 100644
index 000000000..0867e9ca8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-4.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1;
+  short res[8];
+  int masks[8];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 0);
+  res[1] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 1);
+  res[2] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 2);
+  res[3] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 3);
+  res[4] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 4);
+  res[5] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 5);
+  res[6] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 6);
+  res[7] = __builtin_ia32_vec_ext_v8hi ((__v8hi)val1.x, 7);
+
+  for (i = 0; i < 8; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 8; i++)
+    if (res[i] != val1.s [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-5.c
new file mode 100644
index 000000000..c676bbd3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-5.c
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1;
+  char res[16];
+  int masks[16];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 0);
+  res[1] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 1);
+  res[2] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 2);
+  res[3] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 3);
+  res[4] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 4);
+  res[5] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 5);
+  res[6] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 6);
+  res[7] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 7);
+  res[8] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 8);
+  res[9] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 9);
+  res[10] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 10);
+  res[11] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 11);
+  res[12] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 12);
+  res[13] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 13);
+  res[14] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 14);
+  res[15] = __builtin_ia32_vec_ext_v16qi ((__v16qi)val1.x, 15);
+
+  for (i = 0; i < 16; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 16; i++)
+    if (res[i] != val1.c [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-6.c
new file mode 100644
index 000000000..856c3e70c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-vec-6.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <emmintrin.h>
+#include <string.h>
+
+static void
+sse2_test (void)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+      int i[4];
+      long long ll[2];
+    } val1, res[16], tmp;
+  short ins[8] = { 8, 5, 9, 4, 2, 6, 1, 20 };
+  int masks[8];
+  int i;
+
+  for (i = 0; i < 16; i++)
+    val1.c[i] = i;
+
+  res[0].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 0);
+  res[1].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 1);
+  res[2].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 2);
+  res[3].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 3);
+  res[4].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 4);
+  res[5].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 5);
+  res[6].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 6);
+  res[7].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+						    ins[0], 7);
+
+  for (i = 0; i < 8; i++)
+    masks[i] = i;
+
+  for (i = 0; i < 8; i++)
+    {
+      tmp.x = val1.x;
+      tmp.s[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+
+  for (i = 0; i < 8; i++)
+    {
+      res[i].x = (__m128i) __builtin_ia32_vec_set_v8hi ((__v8hi)val1.x,
+							ins[i], 0);
+      masks[i] = 0;
+    }
+
+  for (i = 0; i < 8; i++)
+    {
+      tmp.x = val1.x;
+      tmp.s[masks[i]] = ins[i];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c
new file mode 100644
index 000000000..669f57149
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse2-xorpd-1.c
@@ -0,0 +1,49 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse2_test
+#endif
+
+#include CHECK_H
+
+#include <emmintrin.h>
+
+static __m128d
+__attribute__((noinline, unused))
+test (__m128d s1, __m128d s2)
+{
+  return _mm_xor_pd (s1, s2); 
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      double d[2];
+      long long l[2];
+    }source1, source2, e;
+
+  union128d u, s1, s2;
+  int i; 
+   
+  s1.x = _mm_set_pd (11.1321456, 2.287332);
+  s2.x = _mm_set_pd (3.37768, 4.43222234);
+
+  _mm_storeu_pd (source1.d, s1.x);
+  _mm_storeu_pd (source2.d, s2.x);
+
+  u.x = test (s1.x, s2.x); 
+ 
+  for (i = 0; i < 2; i++)
+    e.l[i] = source1.l[i] ^ source2.l[i];
+
+  if (check_union128d (u, e.d))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c
new file mode 100644
index 000000000..147a1ecb8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-addsubpd.c
@@ -0,0 +1,99 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_addsubpd (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_loadu_pd (i2);
+
+  t1 = _mm_addsub_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static void
+sse3_test_addsubpd_subsume (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_load_pd (i1);
+  __m128d t2 = _mm_load_pd (i2);
+
+  t1 = _mm_addsub_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2] __attribute__ ((aligned(16)));
+static double p2[2] __attribute__ ((aligned(16)));
+static double p3[2];
+static double ck[2];
+
+double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 4)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+
+      p2[0] = vals[i+2];
+      p2[1] = vals[i+3];
+
+      ck[0] = p1[0] - p2[0];
+      ck[1] = p1[1] + p2[1];
+
+      sse3_test_addsubpd (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+
+      sse3_test_addsubpd_subsume (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-addsubps.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-addsubps.c
new file mode 100644
index 000000000..604c40493
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-addsubps.c
@@ -0,0 +1,105 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_addsubps (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_loadu_ps (i2);
+
+  t1 = _mm_addsub_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static void
+sse3_test_addsubps_subsume (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_load_ps (i2);
+
+  t1 = _mm_addsub_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static int
+chk_ps (float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4] __attribute__ ((aligned(16)));
+static float p3[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 8)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+      p1[2] = vals[i+2];
+      p1[3] = vals[i+3];
+
+      p2[0] = vals[i+4];
+      p2[1] = vals[i+5];
+      p2[2] = vals[i+6];
+      p2[3] = vals[i+7];
+
+      ck[0] = p1[0] - p2[0];
+      ck[1] = p1[1] + p2[1];
+      ck[2] = p1[2] - p2[2];
+      ck[3] = p1[3] + p2[3];
+
+      sse3_test_addsubps (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+
+      sse3_test_addsubps_subsume (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-check.h
new file mode 100644
index 000000000..5a0a0b1a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-check.h
@@ -0,0 +1,28 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "cpuid.h"
+#include "sse-os-support.h"
+
+static void sse3_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  sse3_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+ 
+  /* Run SSE3 test only if host has SSE3 support.  */
+  if ((ecx & bit_SSE3) && sse_os_support ())
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-haddpd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-haddpd.c
new file mode 100644
index 000000000..ae4f94a93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-haddpd.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+#include <pmmintrin.h>
+
+static void
+sse3_test_haddpd (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_loadu_pd (i2);
+
+  t1 = _mm_hadd_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static void
+sse3_test_haddpd_subsume (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_load_pd (i1);
+  __m128d t2 = _mm_load_pd (i2);
+
+  t1 = _mm_hadd_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2] __attribute__ ((aligned(16)));
+static double p2[2] __attribute__ ((aligned(16)));
+static double p3[2];
+static double ck[2];
+
+static double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 4)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+
+      p2[0] = vals[i+2];
+      p2[1] = vals[i+3];
+
+      ck[0] = p1[0] + p1[1];
+      ck[1] = p2[0] + p2[1];
+
+      sse3_test_haddpd (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+
+      sse3_test_haddpd_subsume (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-haddps.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-haddps.c
new file mode 100644
index 000000000..e944eab66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-haddps.c
@@ -0,0 +1,105 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_haddps (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_loadu_ps (i2);
+
+  t1 = _mm_hadd_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static void
+sse3_test_haddps_subsume (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_load_ps (i2);
+
+  t1 = _mm_hadd_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static int
+chk_ps(float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4] __attribute__ ((aligned(16)));
+static float p3[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST ()
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 8)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+      p1[2] = vals[i+2];
+      p1[3] = vals[i+3];
+
+      p2[0] = vals[i+4];
+      p2[1] = vals[i+5];
+      p2[2] = vals[i+6];
+      p2[3] = vals[i+7];
+
+      ck[0] = p1[0] + p1[1];
+      ck[1] = p1[2] + p1[3];
+      ck[2] = p2[0] + p2[1];
+      ck[3] = p2[2] + p2[3];
+
+      sse3_test_haddps (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+
+      sse3_test_haddps_subsume (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c
new file mode 100644
index 000000000..37bd60c39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-hsubpd.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+#include <pmmintrin.h>
+
+static void
+sse3_test_hsubpd (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_loadu_pd (i2);
+
+  t1 = _mm_hsub_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static void
+sse3_test_hsubpd_subsume (double *i1, double *i2, double *r)
+{
+  __m128d t1 = _mm_load_pd (i1);
+  __m128d t2 = _mm_load_pd (i2);
+
+  t1 = _mm_hsub_pd (t1, t2);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2] __attribute__ ((aligned(16)));
+static double p2[2] __attribute__ ((aligned(16)));
+static double p3[2];
+static double ck[2];
+
+static double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 4)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+
+      p2[0] = vals[i+2];
+      p2[1] = vals[i+3];
+
+      ck[0] = p1[0] - p1[1];
+      ck[1] = p2[0] - p2[1];
+
+      sse3_test_hsubpd (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+
+      sse3_test_hsubpd_subsume (p1, p2, p3);
+
+      fail += chk_pd (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-hsubps.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-hsubps.c
new file mode 100644
index 000000000..1980638de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-hsubps.c
@@ -0,0 +1,106 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+#include <pmmintrin.h>
+
+static void
+sse3_test_hsubps (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_loadu_ps (i2);
+
+  t1 = _mm_hsub_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static void
+sse3_test_hsubps_subsume (float *i1, float *i2, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_load_ps (i2);
+
+  t1 = _mm_hsub_ps (t1, t2);
+
+  _mm_storeu_ps (r, t1);
+}
+
+static int
+chk_ps (float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++) {
+    if (v1[i] != v2[i]) {
+      n_fails += 1;
+    }
+  }
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4] __attribute__ ((aligned(16)));
+static float p3[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 8)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+      p1[2] = vals[i+2];
+      p1[3] = vals[i+3];
+
+      p2[0] = vals[i+4];
+      p2[1] = vals[i+5];
+      p2[2] = vals[i+6];
+      p2[3] = vals[i+7];
+
+      ck[0] = p1[0] - p1[1];
+      ck[1] = p1[2] - p1[3];
+      ck[2] = p2[0] - p2[1];
+      ck[3] = p2[2] - p2[3];
+
+      sse3_test_hsubps (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+
+      sse3_test_hsubps_subsume (p1, p2, p3);
+
+      fail += chk_ps (ck, p3);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-lddqu.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-lddqu.c
new file mode 100644
index 000000000..700bd571d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-lddqu.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+#include <pmmintrin.h>
+
+static void
+sse3_test_lddqu (double *i1, double *r)
+{
+  __m128i t1 = _mm_lddqu_si128 ((__m128i *) i1);
+
+  _mm_storeu_si128 ((__m128i *) r, t1);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2];
+static double p2[2];
+static double ck[2];
+
+static double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 2)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = vals[i+1];
+
+      sse3_test_lddqu (p1, p2);
+
+      ck[0] = p1[0];
+      ck[1] = p1[1];
+
+      fail += chk_pd (ck, p2);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movddup.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movddup.c
new file mode 100644
index 000000000..cbf320666
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movddup.c
@@ -0,0 +1,133 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_movddup_mem (double *i1, double *r)
+{
+  __m128d t1 = _mm_loaddup_pd (i1);
+
+  _mm_storeu_pd (r, t1);
+}
+
+static double cnst1 [2] = {1.0, 1.0};
+
+static void
+sse3_test_movddup_reg (double *i1, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_loadu_pd (&cnst1[0]);
+
+  t1  = _mm_mul_pd (t1, t2);
+  t2  = _mm_movedup_pd (t1);
+
+  _mm_storeu_pd (r, t2);
+}
+
+static void
+sse3_test_movddup_reg_subsume_unaligned (double *i1, double *r)
+{
+  __m128d t1 = _mm_loadu_pd (i1);
+  __m128d t2 = _mm_movedup_pd (t1);
+
+  _mm_storeu_pd (r, t2);
+}
+
+static void
+sse3_test_movddup_reg_subsume_ldsd (double *i1, double *r)
+{
+  __m128d t1 = _mm_load_sd (i1);
+  __m128d t2 = _mm_movedup_pd (t1);
+
+  _mm_storeu_pd (r, t2);
+}
+
+static void
+sse3_test_movddup_reg_subsume (double *i1, double *r)
+{
+  __m128d t1 = _mm_load_pd (i1);
+  __m128d t2 = _mm_movedup_pd (t1);
+
+  _mm_storeu_pd (r, t2);
+}
+
+static int
+chk_pd (double *v1, double *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 2; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static double p1[2] __attribute__ ((aligned(16)));
+static double p2[2];
+static double ck[2];
+
+static double vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 1)
+    {
+      p1[0] = vals[i+0];
+
+      ck[0] = p1[0];
+      ck[1] = p1[0];
+
+      sse3_test_movddup_mem (p1, p2);
+
+      fail += chk_pd (ck, p2);
+
+      sse3_test_movddup_reg (p1, p2);
+
+      fail += chk_pd (ck, p2);
+
+      sse3_test_movddup_reg_subsume (p1, p2);
+
+      fail += chk_pd (ck, p2);
+
+      sse3_test_movddup_reg_subsume_unaligned (p1, p2);
+
+      fail += chk_pd (ck, p2);
+
+      sse3_test_movddup_reg_subsume_ldsd (p1, p2);
+
+      fail += chk_pd (ck, p2);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movshdup.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movshdup.c
new file mode 100644
index 000000000..0d30ccb5b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movshdup.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_movshdup_reg (float *i1, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_movehdup_ps (t1);
+
+  _mm_storeu_ps (r, t2);
+}
+
+static void
+sse3_test_movshdup_reg_subsume (float *i1, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_movehdup_ps (t1);
+
+  _mm_storeu_ps (r, t2);
+}
+
+static int
+chk_ps (float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 2)
+    {
+      p1[0] = 0.0;
+      p1[1] = vals[i+0];
+      p1[2] = 1.0;
+      p1[3] = vals[i+1];
+
+      ck[0] = p1[1];
+      ck[1] = p1[1];
+      ck[2] = p1[3];
+      ck[3] = p1[3];
+
+      sse3_test_movshdup_reg (p1, p2);
+
+      fail += chk_ps (ck, p2);
+
+      sse3_test_movshdup_reg_subsume (p1, p2);
+
+      fail += chk_ps (ck, p2);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movsldup.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movsldup.c
new file mode 100644
index 000000000..1ef2dd1b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse3-movsldup.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse3 } */
+/* { dg-options "-O2 -msse3 -mfpmath=sse" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse3_test
+#endif
+
+#include CHECK_H
+
+#include <pmmintrin.h>
+
+static void
+sse3_test_movsldup_reg (float *i1, float *r)
+{
+  __m128 t1 = _mm_loadu_ps (i1);
+  __m128 t2 = _mm_moveldup_ps (t1);
+
+  _mm_storeu_ps (r, t2);
+}
+
+static void
+sse3_test_movsldup_reg_subsume (float *i1, float *r)
+{
+  __m128 t1 = _mm_load_ps (i1);
+  __m128 t2 = _mm_moveldup_ps (t1);
+
+  _mm_storeu_ps (r, t2);
+}
+
+static int
+chk_ps (float *v1, float *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static float p1[4] __attribute__ ((aligned(16)));
+static float p2[4];
+static float ck[4];
+
+static float vals[80] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, -1.0, .345, -21.5,
+    1100.0, 0.235, 321.3, 53.40, 0.3, 10.0, 42.0, 32.52,
+    32.6,   123.3, 1.234, 2.156, 0.1, 3.25, 4.75, 32.44,
+    12.16,  52.34, 64.12, 71.13, -.1, 2.30, 5.12, 3.785,
+    541.3,  321.4, 231.4, 531.4, 71., 321., 231., -531.,
+    23.45,  23.45, 23.45, 23.45, 23.45, 23.45, 23.45, 23.45,
+    23.45,  -1.43, -6.74, 6.345, -20.1, -20.1, -40.1, -40.1,
+    1.234,  2.345, 3.456, 4.567, 5.678, 6.789, 7.891, 8.912,
+    -9.32,  -8.41, -7.50, -6.59, -5.68, -4.77, -3.86, -2.95,
+    9.32,  8.41, 7.50, 6.59, -5.68, -4.77, -3.86, -2.95
+  };
+
+static void
+TEST (void)
+{
+  int i;
+  int fail = 0;
+
+  for (i = 0; i < 80; i += 2)
+    {
+      p1[0] = vals[i+0];
+      p1[1] = 0.0;
+      p1[2] = vals[i+1];
+      p1[3] = 1.0;
+
+      ck[0] = p1[0];
+      ck[1] = p1[0];
+      ck[2] = p1[2];
+      ck[3] = p1[2];
+
+      sse3_test_movsldup_reg (p1, p2);
+
+      fail += chk_ps (ck, p2);
+
+      sse3_test_movsldup_reg_subsume (p1, p2);
+
+      fail += chk_ps (ck, p2);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c
new file mode 100644
index 000000000..aff188c63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendpd.c
@@ -0,0 +1,89 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+#ifndef MASK
+#define MASK 0x03
+#endif
+
+static void
+init_blendpd (double *src1, double *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 2; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_blendpd (__m128d *dst, double *src1, double *src2)
+{
+  double tmp[2];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+
+  for(j = 0; j < 2; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+TEST (void)
+{
+  __m128d x, y;
+  union
+    {
+      __m128d x[NUM];
+      double d[NUM * 2];
+    } dst, src1, src2;
+  union
+    {
+      __m128d x;
+      double d[2];
+    } src3;
+  int i;
+
+  init_blendpd (src1.d, src2.d);
+
+  /* Check blendpd imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_pd (src1.x[i], src2.x[i], MASK);
+      if (check_blendpd (&dst.x[i], &src1.d[i * 2], &src2.d[i * 2]))
+	abort ();
+    }
+    
+  /* Check blendpd imm8, xmm, xmm */
+  src3.x = _mm_setzero_pd ();
+
+  x = _mm_blend_pd (dst.x[2], src3.x, MASK);
+  y = _mm_blend_pd (src3.x, dst.x[2], MASK);
+
+  if (check_blendpd (&x, &dst.d[4], &src3.d[0]))
+    abort ();
+
+  if (check_blendpd (&y, &src3.d[0], &dst.d[4]))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c
new file mode 100644
index 000000000..8fe71b71c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendps-2.c
@@ -0,0 +1,86 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* mingw runtime don't provide random().  */
+#ifdef __MINGW32__
+#define random rand
+#endif
+
+#define NUM 20
+
+#undef MASK
+#define MASK 0xe
+
+static void
+init_blendps (float *src1, float *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_blendps (__m128 *dst, float *src1, float *src2)
+{
+  float tmp[4];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 4; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+sse4_1_test (void)
+{
+  __m128 x, y;
+  union
+    {
+      __m128 x[NUM];
+      float f[NUM * 4];
+    } dst, src1, src2;
+  union
+    {
+      __m128 x;
+      float f[4];
+    } src3;
+  int i;
+
+  init_blendps (src1.f, src2.f);
+
+  for (i = 0; i < 4; i++)
+    src3.f[i] = (int) random ();
+
+  /* Check blendps imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_ps (src1.x[i], src2.x[i], MASK); 
+      if (check_blendps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4]))
+	abort ();
+    }
+    
+   /* Check blendps imm8, xmm, xmm */
+  x = _mm_blend_ps (dst.x[2], src3.x, MASK);
+  y = _mm_blend_ps (src3.x, dst.x[2], MASK);
+
+  if (check_blendps (&x, &dst.f[8], &src3.f[0]))
+    abort ();
+
+  if (check_blendps (&y, &src3.f[0], &dst.f[8]))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c
new file mode 100644
index 000000000..3f4b335ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendps.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* mingw runtime don't provide random().  */
+#ifdef __MINGW32__
+#define random rand
+#endif
+
+#define NUM 20
+
+#ifndef MASK
+#define MASK 0x0f
+#endif
+
+static void
+init_blendps (float *src1, float *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 4; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_blendps (__m128 *dst, float *src1, float *src2)
+{
+  float tmp[4];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 4; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+TEST (void)
+{
+  __m128 x, y;
+  union
+    {
+      __m128 x[NUM];
+      float f[NUM * 4];
+    } dst, src1, src2;
+  union
+    {
+      __m128 x;
+      float f[4];
+    } src3;
+  int i;
+
+  init_blendps (src1.f, src2.f);
+
+  for (i = 0; i < 4; i++)
+    src3.f[i] = (int) random ();
+
+  /* Check blendps imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_ps (src1.x[i], src2.x[i], MASK); 
+      if (check_blendps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4]))
+	abort ();
+    }
+    
+   /* Check blendps imm8, xmm, xmm */
+  x = _mm_blend_ps (dst.x[2], src3.x, MASK);
+  y = _mm_blend_ps (src3.x, dst.x[2], MASK);
+
+  if (check_blendps (&x, &dst.f[8], &src3.f[0]))
+    abort ();
+
+  if (check_blendps (&y, &src3.f[0], &dst.f[8]))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c
new file mode 100644
index 000000000..8478234e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendvpd.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_blendvpd (double *src1, double *src2, double *mask)
+{
+  int i, msk, sign = 1; 
+
+  msk = -1;
+  for (i = 0; i < NUM * 2; i++)
+    {
+      if((i % 2) == 0)
+	msk++;
+      src1[i] = i* (i + 1) * sign;
+      src2[i] = (i + 20) * sign;
+      mask[i] = (i + 120) * i;
+      if( (msk & (1 << (i % 2))))
+	mask[i] = -mask[i];
+      sign = -sign;
+    }
+}
+
+static int
+check_blendvpd (__m128d *dst, double *src1, double *src2,
+		double *mask)
+{
+  double tmp[2];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 2; j++)
+    if (mask [j] < 0.0)
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+sse4_1_test (void)
+{
+  union
+    {
+      __m128d x[NUM];
+      double d[NUM * 2];
+    } dst, src1, src2, mask;
+  int i;
+
+  init_blendvpd (src1.d, src2.d, mask.d);
+
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blendv_pd (src1.x[i], src2.x[i], mask.x[i]);
+      if (check_blendvpd (&dst.x[i], &src1.d[i * 2], &src2.d[i * 2],
+			  &mask.d[i * 2]))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c
new file mode 100644
index 000000000..7ff464900
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-blendvps.c
@@ -0,0 +1,65 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_blendvps (float *src1, float *src2, float *mask)
+{
+  int i, msk, sign = 1; 
+
+  msk = -1;
+  for (i = 0; i < NUM * 4; i++)
+    {
+      if((i % 4) == 0)
+	msk++;
+      src1[i] = i* (i + 1) * sign;
+      src2[i] = (i + 20) * sign;
+      mask[i] = (i + 120) * i;
+      if( (msk & (1 << (i % 4))))
+	mask[i] = -mask[i];
+      sign = -sign;
+    }
+}
+
+static int
+check_blendvps (__m128 *dst, float *src1, float *src2,
+		float *mask)
+{
+  float tmp[4];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 4; j++)
+    if (mask [j] < 0.0)
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+sse4_1_test (void)
+{
+  union
+    {
+      __m128 x[NUM];
+      float f[NUM * 4];
+    } dst, src1, src2, mask;
+  int i;
+
+  init_blendvps (src1.f, src2.f, mask.f);
+
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blendv_ps (src1.x[i], src2.x[i], mask.x[i]);
+      if (check_blendvps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4],
+			  &mask.f[i * 4]))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c
new file mode 100644
index 000000000..ca07d9c00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceil-sfix-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double ceil (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) ceil (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) ceil (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c
new file mode 100644
index 000000000..20bb2641f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceil-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double ceil (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  double r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = ceil (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != ceil (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c
new file mode 100644
index 000000000..b0559bf39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-sfix-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern float ceilf (float);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) ceilf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) ceilf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c
new file mode 100644
index 000000000..314be91fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ceilf-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern float ceilf (float);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  float r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = ceilf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != ceilf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-check.h
new file mode 100644
index 000000000..788f65d61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-check.h
@@ -0,0 +1,30 @@
+#include <stdlib.h>
+
+#include "cpuid.h"
+#include "m128-check.h"
+
+static void sse4_1_test (void);
+
+#define MASK 0x2
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  sse4_1_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE4.1 test only if host has SSE4.1 support.  */
+  if (ecx & bit_SSE4_1)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c
new file mode 100644
index 000000000..41e69e59f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-cond-1.c
@@ -0,0 +1,75 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O3 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+extern void abort (void);
+double ad[64], bd[64], cd[64], dd[64], ed[64];
+float af[64], bf[64], cf[64], df[64], ef[64];
+signed char ac[64], bc[64], cc[64], dc[64], ec[64];
+short as[64], bs[64], cs[64], ds[64], es[64];
+int ai[64], bi[64], ci[64], di[64], ei[64];
+long long all[64], bll[64], cll[64], dll[64], ell[64];
+unsigned char auc[64], buc[64], cuc[64], duc[64], euc[64];
+unsigned short aus[64], bus[64], cus[64], dus[64], eus[64];
+unsigned int au[64], bu[64], cu[64], du[64], eu[64];
+unsigned long long aull[64], bull[64], cull[64], dull[64], eull[64];
+
+#define F(var) \
+__attribute__((noinline, noclone)) void \
+f##var (void) \
+{ \
+  int i; \
+  for (i = 0; i < 64; i++) \
+    { \
+      __typeof (a##var[0]) d = d##var[i], e = e##var[i]; \
+      a##var[i] = b##var[i] > c##var[i] ? d : e; \
+    } \
+}
+
+#define TESTS \
+F (d) F (f) F (c) F (s) F (i) F (ll) F (uc) F (us) F (u) F (ull)
+
+TESTS
+
+void
+TEST ()
+{
+  int i;
+  for (i = 0; i < 64; i++)
+    {
+#undef F
+#define F(var) \
+      b##var[i] = i + 64; \
+      switch (i % 3) \
+	{ \
+	case 0: c##var[i] = i + 64; break; \
+	case 1: c##var[i] = 127 - i; break; \
+	case 2: c##var[i] = i; break; \
+	} \
+      d##var[i] = i / 2; \
+      e##var[i] = i * 2;
+      TESTS
+    }
+#undef F
+#define F(var) f##var ();
+  TESTS
+  for (i = 0; i < 64; i++)
+    {
+      asm volatile ("" : : : "memory");
+#undef F
+#define F(var) \
+      if (a##var[i] != (b##var[i] > c##var[i] ? d##var[i] : e##var[i])) \
+	abort ();
+      TESTS
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c
new file mode 100644
index 000000000..b8e58d47a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dppd-1.c
@@ -0,0 +1,71 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define lmskN  0x00
+#define lmsk0  0x01
+#define lmsk1  0x02
+#define lmsk01 0x03
+
+#define hmskA  0x30
+#define hmsk0  0x10
+#define hmsk1  0x20
+#define hmsk01 0x30
+#define hmskN  0x00
+
+#ifndef HIMASK
+#define HIMASK hmskA
+#endif
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128d x;
+      double d[2];
+    } val1, val2, res[4];
+  int masks[4];
+  int i, j;
+
+  val1.d[0] = 2.;
+  val1.d[1] = 3.;
+
+  val2.d[0] = 10.;
+  val2.d[1] = 100.;
+
+  res[0].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmskN);
+  res[1].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk0);
+  res[2].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk1);
+  res[3].x = _mm_dp_pd (val1.x, val2.x, HIMASK | lmsk01);
+
+  masks[0] = HIMASK | lmskN;
+  masks[1] = HIMASK | lmsk0;
+  masks[2] = HIMASK | lmsk1;
+  masks[3] = HIMASK | lmsk01; 
+
+  for (i = 0; i < 4; i++)
+    {
+      double tmp = 0.;
+
+      for (j = 0; j < 2; j++)
+	if (HIMASK & (0x10 << j))
+	  tmp = tmp + (val1.d[j] * val2.d[j]);
+
+      for (j = 0; j < 2; j++)
+	if ((masks[i] & (1 << j)) && res[i].d[j] != tmp)
+	  abort ();
+   }
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c
new file mode 100644
index 000000000..6dc328c05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dppd-2.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#include <string.h>
+
+#define lmskN  0x00
+#define lmsk0  0x01
+#define lmsk1  0x02
+#define lmsk01 0x03
+
+#define hmskA  0x30
+#define hmsk0  0x10
+#define hmsk1  0x20
+#define hmsk01 0x30
+#define hmskN  0x00
+
+#ifndef HIMASK
+#define HIMASK hmskA
+#endif
+
+#ifndef LOMASK
+#define LOMASK lmsk01
+#endif
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128d x;
+      double d[2];
+    } val1[4], val2[4], res[4], chk[4];
+  int i, j;
+  double tmp;
+
+  for (i = 0; i < 4; i++)
+    {
+      val1[i].d [0] = 2.;
+      val1[i].d [1] = 3.;
+
+      val2[i].d [0] = 10.;
+      val2[i].d [1] = 100.;
+
+      tmp = 0.;
+      for (j = 0; j < 2; j++)
+	if ((HIMASK & (0x10 << j)))
+	  tmp += val1[i].d [j] * val2[i].d [j];
+
+      for (j = 0; j < 2; j++)
+        if ((LOMASK & (1 << j)))
+	  chk[i].d[j] = tmp;
+    }
+
+  for (i = 0; i < 4; i++)
+    {
+      res[i].x = _mm_dp_pd (val1[i].x, val2[i].x, HIMASK | LOMASK); 
+      if (memcmp (&res[i], &chk[i], sizeof (chk[i])))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c
new file mode 100644
index 000000000..77232567c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dpps-1.c
@@ -0,0 +1,114 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define lmskN  0x00
+#define lmsk0  0x01
+#define lmsk1  0x02
+#define lmsk2  0x04
+#define lmsk3  0x08
+#define lmsk01 0x03
+#define lmsk02 0x05
+#define lmsk03 0x09
+#define lmsk12 0x06
+#define lmsk13 0x0A
+#define lmsk23 0x0C
+#define lmskA  0x0F
+
+#define hmskN  0x00
+#define hmskA  0xF0
+#define hmsk0  0x10
+#define hmsk1  0x20
+#define hmsk2  0x40
+#define hmsk3  0x80
+#define hmsk01 0x30
+#define hmsk02 0x50
+#define hmsk03 0x90
+#define hmsk12 0x60
+#define hmsk13 0xA0
+#define hmsk23 0xC0
+
+#ifndef HIMASK
+#define HIMASK hmskA
+#endif
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } val1, val2, res[16];
+  int masks[16];
+  int i, j;
+
+  val1.f[0] = 2.;
+  val1.f[1] = 3.;
+  val1.f[2] = 4.;
+  val1.f[3] = 5.;
+
+  val2.f[0] = 10.;
+  val2.f[1] = 100.;
+  val2.f[2] = 1000.;
+  val2.f[3] = 10000.;
+
+  res[0].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk0); 
+  res[1].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk1); 
+  res[2].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk2); 
+  res[3].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk3); 
+  res[4].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk01); 
+  res[5].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk02); 
+  res[6].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk03); 
+  res[7].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk12); 
+  res[8].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk13); 
+  res[9].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmsk23); 
+  res[10].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk0)); 
+  res[11].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk1)); 
+  res[12].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk2)); 
+  res[13].x = _mm_dp_ps (val1.x, val2.x, HIMASK | (0x0F & ~lmsk3)); 
+  res[14].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmskN); 
+  res[15].x = _mm_dp_ps (val1.x, val2.x, HIMASK | lmskA); 
+
+  masks[0] = HIMASK | lmsk0; 
+  masks[1] = HIMASK | lmsk1; 
+  masks[2] = HIMASK | lmsk2; 
+  masks[3] = HIMASK | lmsk3; 
+  masks[4] = HIMASK | lmsk01; 
+  masks[5] = HIMASK | lmsk02; 
+  masks[6] = HIMASK | lmsk03; 
+  masks[7] = HIMASK | lmsk12; 
+  masks[8] = HIMASK | lmsk13; 
+  masks[9] = HIMASK | lmsk23; 
+  masks[10] = HIMASK | (0x0F & ~lmsk0); 
+  masks[11] = HIMASK | (0x0F & ~lmsk1); 
+  masks[12] = HIMASK | (0x0F & ~lmsk2); 
+  masks[13] = HIMASK | (0x0F & ~lmsk3); 
+  masks[14] = HIMASK | lmskN; 
+  masks[15] = HIMASK | lmskA; 
+
+  for (i = 0; i <= 15; i++)
+    {
+      float tmp = 0.;
+
+      for (j = 0; j < 4; j++)
+	if ((HIMASK & (0x10 << j)))
+	  tmp += val1.f[j] * val2.f[j];
+
+      for (j = 0; j < 4; j++)
+	if ((masks[i] & (1 << j)) && res[i].f[j] != tmp)
+	  abort ();
+   }
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c
new file mode 100644
index 000000000..48483b6c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-dpps-2.c
@@ -0,0 +1,92 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#include <string.h>
+
+#define lmskN  0x00
+#define lmsk0  0x01
+#define lmsk1  0x02
+#define lmsk2  0x04
+#define lmsk3  0x08
+#define lmsk01 0x03
+#define lmsk02 0x05
+#define lmsk03 0x09
+#define lmsk12 0x06
+#define lmsk13 0x0A
+#define lmsk23 0x0C
+#define lmskA  0x0F
+
+#define hmskN  0x00
+#define hmskA  0xF0
+#define hmsk0  0x10
+#define hmsk1  0x20
+#define hmsk2  0x40
+#define hmsk3  0x80
+#define hmsk01 0x30
+#define hmsk02 0x50
+#define hmsk03 0x90
+#define hmsk12 0x60
+#define hmsk13 0xA0
+#define hmsk23 0xC0
+
+#ifndef HIMASK
+#define HIMASK hmskA
+#endif
+
+#ifndef LOMASK
+#define LOMASK lmskA
+#endif
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } val1[16], val2[16], res[16], chk[16];
+  int i,j;
+  float tmp;
+
+  for (i = 0; i < 16; i++)
+    {
+      val1[i].f[0] = 2.;
+      val1[i].f[1] = 3.;
+      val1[i].f[2] = 4.;
+      val1[i].f[3] = 5.;
+
+      val2[i].f[0] = 10.;
+      val2[i].f[1] = 100.;
+      val2[i].f[2] = 1000.;
+      val2[i].f[3] = 10000.;
+
+      tmp = 0.;
+      for (j = 0; j < 4; j++)
+        if ((HIMASK & (0x10 << j)))
+	  tmp += val1[i].f [j] * val2[i].f [j];
+
+      for (j = 0; j < 4; j++)
+	if ((LOMASK & (1 << j)))
+	  chk[i].f[j] = tmp;
+    }
+
+   for (i = 0; i < 16; i++)
+     {
+       res[i].x = _mm_dp_ps (val1[i].x, val2[i].x, HIMASK | LOMASK);
+       if (memcmp (&res[i], &chk[i], sizeof (chk[i])))
+	 abort ();
+     }
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c
new file mode 100644
index 000000000..d63296fe2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-extractps.c
@@ -0,0 +1,72 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+int masks[4];
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } val1, val2;
+  union
+    {
+      int i;
+      float f;
+    } res[4];
+  float resm[4];
+  int i;
+
+  val1.f[0] = 10.;
+  val1.f[1] = 2.;
+  val1.f[2] = 3.;
+  val1.f[3] = 40.;
+
+  val2.f[0] = 77.;
+  val2.f[1] = 21.;
+  val2.f[2] = 34.;
+  val2.f[3] = 49.;
+
+  res[0].i = _mm_extract_ps (val1.x, msk0);
+  res[1].i = _mm_extract_ps (val1.x, msk1);
+  res[2].i = _mm_extract_ps (val1.x, msk2);
+  res[3].i = _mm_extract_ps (val1.x, msk3);
+
+  _MM_EXTRACT_FLOAT (resm[0], val2.x, msk0);
+  _MM_EXTRACT_FLOAT (resm[1], val2.x, msk1);
+  _MM_EXTRACT_FLOAT (resm[2], val2.x, msk2);
+  _MM_EXTRACT_FLOAT (resm[3], val2.x, msk3);
+  
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for( i=0; i < 4; i++ )
+    {
+      if (res[i].f != val1.f[masks[i]])
+	abort ();
+      if (resm[i] != val2.f[masks[i]])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c
new file mode 100644
index 000000000..2083a60e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floor-sfix-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double floor (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) floor (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) floor (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c
new file mode 100644
index 000000000..d250413c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floor-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double floor (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  double r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = floor (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != floor (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c
new file mode 100644
index 000000000..7e18b46f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floorf-sfix-vec.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) __builtin_floorf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) __builtin_floorf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c
new file mode 100644
index 000000000..019ef8941
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-floorf-vec.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  float r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = __builtin_floorf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != __builtin_floorf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c
new file mode 100644
index 000000000..6a3ccee58
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v16qi-1.c
@@ -0,0 +1,77 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned char *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned char i[16];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned char *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[3], 0, 0, 0);
+  check (x, v, 3);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[4], 0, 0, 0, 0);
+  check (x, v, 4);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, v[5], 0, 0, 0, 0, 0);
+  check (x, v, 5);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, 0, v[6], 0, 0, 0, 0, 0, 0);
+  check (x, v, 6);
+  x = _mm_set_epi8 (0, 0, 0, 0, 0, 0, 0, 0, v[7], 0, 0, 0, 0, 0, 0, 0);
+  check (x, v, 7);
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned char v[16]
+    = { 0x7B, 0x5B, 0x54, 0x65, 0x73, 0x74, 0x56, 0x65,
+	0x63, 0x74, 0x6F, 0x72, 0x5D, 0x53, 0x47, 0x5D };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c
new file mode 100644
index 000000000..cd9fa7978
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v2di-1.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned long long *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long i[2];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%llx != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned long long *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi64x (0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi64x (v[1], 0);
+  check (x, v, 1);
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned long long v[2]
+    = { 0x7B5B546573745665LL, 0x63746F725D53475DLL };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c
new file mode 100644
index 000000000..f97604235
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v4sf-1.c
@@ -0,0 +1,67 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128 x, float *v, int j)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.f[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: %f != %f\n", i, v[i], u.f[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.f[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: %f != 0\n", i, u.f[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (float *v)
+{
+  __m128 x;
+
+  x = _mm_set_ps (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_ps (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_ps (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_ps (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse4_1_test (void)
+{
+  float v[4] = { -3, 2, 1, 9 };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c
new file mode 100644
index 000000000..63501b7ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-init-v4si-1.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+check (__m128i x, unsigned int *v, int j)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } u;
+  unsigned int i;
+
+  u.x = x;
+  
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (i == j)
+      {
+	if (v[i] != u.i[i])
+	  {
+#ifdef DEBUG
+	    printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	    abort ();
+	  }
+      }
+    else if (u.i[i] != 0)
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0\n", i, u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+__attribute__((noinline))
+test (unsigned int *v)
+{
+  __m128i x;
+
+  x = _mm_set_epi32 (0, 0, 0, v[0]);
+  check (x, v, 0);
+  x = _mm_set_epi32 (0, 0, v[1], 0);
+  check (x, v, 1);
+  x = _mm_set_epi32 (0, v[2], 0, 0);
+  check (x, v, 2);
+  x = _mm_set_epi32 (v[3], 0, 0, 0);
+  check (x, v, 3);
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned int v[4]
+    = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c
new file mode 100644
index 000000000..2f5741288
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-1.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x01
+#define msk1 0x10
+#define msk2 0x29
+#define msk3 0x30
+
+#define msk4 0xFC
+#define msk5 0x05
+#define msk6 0x0A
+#define msk7 0x0F
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } res[8], val1, val2, tmp;
+  int masks[8];
+  int i, j;
+
+  val2.f[0] = 55.0;
+  val2.f[1] = 55.0;
+  val2.f[2] = 55.0;
+  val2.f[3] = 55.0;
+
+  val1.f[0] = 1.;
+  val1.f[1] = 2.;
+  val1.f[2] = 3.;
+  val1.f[3] = 4.;
+
+  res[0].x = _mm_insert_ps (val2.x, val1.x, msk0);
+  res[1].x = _mm_insert_ps (val2.x, val1.x, msk1);
+  res[2].x = _mm_insert_ps (val2.x, val1.x, msk2);
+  res[3].x = _mm_insert_ps (val2.x, val1.x, msk3);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for (i = 0; i < 4; i++)
+    res[i + 4].x = _mm_insert_ps (val2.x, val1.x, msk4);
+
+  masks[4] = msk4;
+  masks[5] = msk4;
+  masks[6] = msk4;
+  masks[7] = msk4;
+
+  for (i=0; i < 8; i++)
+    {
+      tmp = val2;
+      tmp.f[(masks[i] & 0x30) >> 4] = val1.f[(masks[i] & 0xC0) >> 6];
+
+      for (j = 0; j < 4; j++)
+	if (masks[i] & (0x1 << j))
+	  tmp.f[j] = 0.f;
+
+      if (memcmp (&res[i], &tmp, sizeof (tmp)))
+	abort ();
+    }
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c
new file mode 100644
index 000000000..fbb96ca50
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-2.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } vals[4], val;
+  int i, j;
+
+  val.f[0]= 1.;
+  val.f[1]= 2.;
+  val.f[2]= 3.;
+  val.f[3]= 4.;
+
+  vals[0].x = _MM_PICK_OUT_PS (val.x, 0);
+  vals[1].x = _MM_PICK_OUT_PS (val.x, 1);
+  vals[2].x = _MM_PICK_OUT_PS (val.x, 2);
+  vals[3].x = _MM_PICK_OUT_PS (val.x, 3);
+
+  for (i = 0; i < 4; i++)
+    for (j = 0; j < 4; j++)
+      if ((j != 0 && vals[i].f[j] != 0)
+	  || (j == 0 && vals[i].f[j] != val.f[i]))
+	abort ();
+
+  if (_MM_MK_INSERTPS_NDX(0, 0, 0x1) != 0x01
+      || _MM_MK_INSERTPS_NDX(0, 1, 0x2) != 0x12
+      || _MM_MK_INSERTPS_NDX(0, 2, 0x3) != 0x23
+      || _MM_MK_INSERTPS_NDX(0, 3, 0x4) != 0x34
+      || _MM_MK_INSERTPS_NDX(1, 0, 0x5) != 0x45
+      || _MM_MK_INSERTPS_NDX(1, 1, 0x6) != 0x56
+      || _MM_MK_INSERTPS_NDX(2, 2, 0x7) != 0xA7
+      || _MM_MK_INSERTPS_NDX(3, 3, 0x8) != 0xF8)
+    abort ();
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c
new file mode 100644
index 000000000..7c71664a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-3.c
@@ -0,0 +1,5 @@
+/* { dg-do run { target ia32 } } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1 -mtune=geode" } */
+
+#include "sse4_1-insertps-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-4.c
new file mode 100644
index 000000000..30defca25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insertps-4.c
@@ -0,0 +1,92 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x41
+#define msk1 0x90
+#define msk2 0xe9
+#define msk3 0x70
+
+#define msk4 0xFC
+#define msk5 0x05
+#define msk6 0x0A
+#define msk7 0x0F
+
+union
+  {
+    __m128 x;
+    float f[4];
+  } val1;
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } res[8], val2, tmp;
+  int masks[8];
+  int i, j;
+
+  val2.f[0] = 55.0;
+  val2.f[1] = 55.0;
+  val2.f[2] = 55.0;
+  val2.f[3] = 55.0;
+
+  val1.f[0] = 1.;
+  val1.f[1] = 2.;
+  val1.f[2] = 3.;
+  val1.f[3] = 4.;
+
+  asm volatile ("" : "+m" (val1));
+  res[0].x = _mm_insert_ps (val2.x, val1.x, msk0);
+  asm volatile ("" : "+m" (val1));
+  res[1].x = _mm_insert_ps (val2.x, val1.x, msk1);
+  asm volatile ("" : "+m" (val1));
+  res[2].x = _mm_insert_ps (val2.x, val1.x, msk2);
+  asm volatile ("" : "+m" (val1));
+  res[3].x = _mm_insert_ps (val2.x, val1.x, msk3);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for (i = 0; i < 4; i++)
+    {
+      asm volatile ("" : "+m" (val1));
+      res[i + 4].x = _mm_insert_ps (val2.x, val1.x, msk4);
+    }
+
+  masks[4] = msk4;
+  masks[5] = msk4;
+  masks[6] = msk4;
+  masks[7] = msk4;
+
+  for (i=0; i < 8; i++)
+    {
+      tmp = val2;
+      tmp.f[(masks[i] & 0x30) >> 4] = val1.f[(masks[i] & 0xC0) >> 6];
+
+      for (j = 0; j < 4; j++)
+	if (masks[i] & (0x1 << j))
+	  tmp.f[j] = 0.f;
+
+      if (memcmp (&res[i], &tmp, sizeof (tmp)))
+	abort ();
+    }
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c
new file mode 100644
index 000000000..da090ba15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvdi.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+typedef long T __attribute__((may_alias));
+struct S { __m128i d; };
+
+__m128i
+__attribute__((noinline))
+foo (__m128i y, long x)
+{
+  struct S s;
+
+  s.d = y;
+  ((T *) &s.d)[1] = x;
+  return s.d;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned long l[2];
+    } res, val, tmp;
+  unsigned long ins[4] = { 3, 4, 5, 6 };
+
+  val.i[0] = 0x35251505;
+  val.i[1] = 0x75655545;
+  val.i[2] = 0xB5A59585;
+  val.i[3] = 0xF5E5D5C5;
+
+  res.x = foo (val.x, ins[3]);
+
+  tmp.x = val.x;
+  tmp.l[1] = ins[3];
+  if (memcmp (&tmp, &res, sizeof (tmp)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c
new file mode 100644
index 000000000..784201e2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvqi.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+typedef char T __attribute__((may_alias));
+struct S { __m128i d; };
+
+__m128i
+__attribute__((noinline))
+foo (__m128i y, char x)
+{
+  struct S s;
+
+  s.d = y;
+  ((T *) &s.d)[1] = x;
+  return s.d;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned char c[16];
+    } res, val, tmp;
+  unsigned char ins[4] = { 3, 4, 5, 6 };
+
+  val.i[0] = 0x35251505;
+  val.i[1] = 0x75655545;
+  val.i[2] = 0xB5A59585;
+  val.i[3] = 0xF5E5D5C5;
+
+  res.x = foo (val.x, ins[3]);
+
+  tmp.x = val.x;
+  tmp.c[1] = ins[3];
+  if (memcmp (&tmp, &res, sizeof (tmp)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c
new file mode 100644
index 000000000..569b8f269
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-insvsi.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+typedef int T __attribute__((may_alias));
+struct S { __m128i d; };
+
+__m128i
+__attribute__((noinline))
+foo (__m128i y, int x)
+{
+  struct S s;
+
+  s.d = y;
+  ((T *) &s.d)[1] = x;
+  return s.d;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } res, val, tmp;
+  unsigned int ins[4] = { 3, 4, 5, 6 };
+
+  val.i[0] = 0x35251505;
+  val.i[1] = 0x75655545;
+  val.i[2] = 0xB5A59585;
+  val.i[3] = 0xF5E5D5C5;
+
+  res.x = foo (val.x, ins[3]);
+
+  tmp.x = val.x;
+  tmp.i[1] = ins[3];
+  if (memcmp (&tmp, &res, sizeof (tmp)))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c
new file mode 100644
index 000000000..bc5cf2383
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-movntdqa.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_movntdqa (int *src)
+{
+  int i, j, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    for (j = 0; j < 4; j++)
+      {
+	src[i * 4 + j] = j * i * i * sign;
+	sign = -sign;
+      }
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      int i[NUM * 4];
+    } dst, src;
+  int i;
+
+  init_movntdqa (src.i);
+
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_stream_load_si128 (&src.x[i]);
+
+  for (i = 0; i < NUM; i++)
+    if (memcmp (&dst.x[i], &src.x[i], sizeof(src.x[i])))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c
new file mode 100644
index 000000000..0fc24e861
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-mpsadbw.c
@@ -0,0 +1,130 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0xC0
+#define msk1 0x01
+#define msk2 0xF2
+#define msk3 0x03
+#define msk4 0x84
+#define msk5 0x05
+#define msk6 0xE6
+#define msk7 0x67
+
+static __m128i
+compute_mpsadbw (unsigned char *v1, unsigned char *v2, int mask)
+{
+  union
+    {
+      __m128i x;
+      unsigned short s[8];
+    } ret;
+  unsigned char s[4];
+  int i, j;
+  int offs1, offs2;
+
+  offs2 = 4 * (mask & 3);
+  for (i = 0; i < 4; i++)
+    s[i] = v2[offs2 + i];
+
+  offs1 = 4 * ((mask & 4) >> 2);
+  for (j = 0; j < 8; j++)
+    {
+      ret.s[j] = 0;
+      for (i = 0; i < 4; i++)
+	ret.s[j] += abs (v1[offs1 + j + i] - s[i]);
+    }
+
+  return ret.x;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned char c[16];
+    } val1, val2, val3 [8];
+  __m128i res[8], tmp;
+  unsigned char masks[8];
+  int i;
+
+  val1.i[0] = 0x35251505;
+  val1.i[1] = 0x75655545;
+  val1.i[2] = 0xB5A59585;
+  val1.i[3] = 0xF5E5D5C5;
+
+  val2.i[0] = 0x31211101;
+  val2.i[1] = 0x71615141;
+  val2.i[2] = 0xB1A19181;
+  val2.i[3] = 0xF1E1D1C1;
+
+  for (i=0; i < 8; i++)
+    switch (i % 3)
+      {
+      case 1:
+	val3[i].i[0] = 0xF1E1D1C1;
+	val3[i].i[1] = 0xB1A19181;
+	val3[i].i[2] = 0x71615141;
+	val3[i].i[3] = 0x31211101;
+	break;
+      default:
+	val3[i].x = val2.x;
+	break;
+      }
+
+  /* Check mpsadbw imm8, xmm, xmm.  */
+  res[0] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk0);
+  res[1] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk1);
+  res[2] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk2);
+  res[3] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk3);
+  res[4] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk4);
+  res[5] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk5);
+  res[6] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk6);
+  res[7] = _mm_mpsadbw_epu8 (val1.x, val2.x, msk7);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+
+  for (i=0; i < 8; i++)
+    {
+      tmp = compute_mpsadbw (val1.c, val2.c, masks[i]);
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check mpsadbw imm8, m128, xmm.  */
+  for (i=0; i < 8; i++)
+    {
+      res[i] = _mm_mpsadbw_epu8 (val1.x, val3[i].x, msk4);
+      masks[i] = msk4;
+    }
+
+  for (i=0; i < 8; i++)
+    {
+      tmp = compute_mpsadbw (val1.c, val3[i].c, masks[i]);
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c
new file mode 100644
index 000000000..20d03a515
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-mul-1.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O3 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include "sse2-mul-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c
new file mode 100644
index 000000000..f98157794
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-packusdw.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static unsigned short
+int_to_ushort (int iVal)
+{
+  unsigned short sVal;
+
+  if (iVal < 0)
+    sVal = 0;
+  else if (iVal > 0xffff)
+    sVal = 0xffff;
+  else sVal = iVal;
+
+  return sVal;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+    } src1, src2;
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned short s[NUM * 2];
+    } dst;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_packus_epi32 (src1.x [i / 4], src2.x [i / 4]);
+
+  for (i = 0; i < NUM; i ++)
+    {
+      int dstIndex;
+      unsigned short sVal;
+
+      sVal = int_to_ushort (src1.i[i]);
+      dstIndex = (i % 4) + (i / 4) * 8;
+      if (sVal != dst.s[dstIndex])
+	abort ();
+
+      sVal = int_to_ushort (src2.i[i]);
+      dstIndex += 4;
+      if (sVal != dst.s[dstIndex])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c
new file mode 100644
index 000000000..58e94471e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendvb.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+static void
+init_pblendvb (unsigned char *src1, unsigned char *src2,
+	       unsigned char *mask)
+{
+  int i, sign = 1; 
+
+  for (i = 0; i < NUM * 16; i++)
+    {
+      src1[i] = i* i * sign;
+      src2[i] = (i + 20) * sign;
+      mask[i] = (i % 3) + ((i * (14 + sign))
+			   ^ (src1[i] | src2[i] | (i*3)));
+      sign = -sign;
+    }
+}
+
+static int
+check_pblendvb (__m128i *dst, unsigned char *src1,
+		unsigned char *src2, unsigned char *mask)
+{
+  unsigned char tmp[16];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 16; j++)
+    if (mask [j] & 0x80)
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      unsigned char c[NUM * 16];
+    } dst, src1, src2, mask;
+  int i;
+
+  init_pblendvb (src1.c, src2.c, mask.c);
+
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blendv_epi8 (src1.x[i], src2.x[i], mask.x[i]);
+      if (check_pblendvb (&dst.x[i], &src1.c[i * 16], &src2.c[i * 16],
+			  &mask.c[i * 16]))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c
new file mode 100644
index 000000000..eecc6edf6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendw-2.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+#undef MASK
+#define MASK 0xfe
+
+static void
+init_pblendw (short *src1, short *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 8; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_pblendw (__m128i *dst, short *src1, short *src2)
+{
+  short tmp[8];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 8; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+sse4_1_test (void)
+{
+  __m128i x, y;
+  union
+    {
+      __m128i x[NUM];
+      short s[NUM * 8];
+    } dst, src1, src2;
+  union
+    {
+      __m128i x;
+      short s[8];
+    } src3;
+  int i;
+
+  init_pblendw (src1.s, src2.s);
+
+  /* Check pblendw imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_epi16 (src1.x[i], src2.x[i], MASK); 
+      if (check_pblendw (&dst.x[i], &src1.s[i * 8], &src2.s[i * 8]))
+	abort ();
+    }
+    
+   /* Check pblendw imm8, xmm, xmm */
+  src3.x = _mm_setzero_si128 ();
+
+  x = _mm_blend_epi16 (dst.x[2], src3.x, MASK);
+  y = _mm_blend_epi16 (src3.x, dst.x[2], MASK);
+
+  if (check_pblendw (&x, &dst.s[16], &src3.s[0]))
+    abort ();
+
+  if (check_pblendw (&y, &src3.s[0], &dst.s[16]))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c
new file mode 100644
index 000000000..5f5a25353
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pblendw.c
@@ -0,0 +1,88 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define NUM 20
+
+#ifndef MASK
+#define MASK 0x0f
+#endif
+
+static void
+init_pblendw (short *src1, short *src2)
+{
+  int i, sign = 1;
+
+  for (i = 0; i < NUM * 8; i++)
+    {
+      src1[i] = i * i * sign;
+      src2[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+}
+
+static int
+check_pblendw (__m128i *dst, short *src1, short *src2)
+{
+  short tmp[8];
+  int j;
+
+  memcpy (&tmp[0], src1, sizeof (tmp));
+  for (j = 0; j < 8; j++)
+    if ((MASK & (1 << j)))
+      tmp[j] = src2[j];
+
+  return memcmp (dst, &tmp[0], sizeof (tmp));
+}
+
+static void
+TEST (void)
+{
+  __m128i x, y;
+  union
+    {
+      __m128i x[NUM];
+      short s[NUM * 8];
+    } dst, src1, src2;
+  union
+    {
+      __m128i x;
+      short s[8];
+    } src3;
+  int i;
+
+  init_pblendw (src1.s, src2.s);
+
+  /* Check pblendw imm8, m128, xmm */
+  for (i = 0; i < NUM; i++)
+    {
+      dst.x[i] = _mm_blend_epi16 (src1.x[i], src2.x[i], MASK); 
+      if (check_pblendw (&dst.x[i], &src1.s[i * 8], &src2.s[i * 8]))
+	abort ();
+    }
+    
+   /* Check pblendw imm8, xmm, xmm */
+  src3.x = _mm_setzero_si128 ();
+
+  x = _mm_blend_epi16 (dst.x[2], src3.x, MASK);
+  y = _mm_blend_epi16 (src3.x, dst.x[2], MASK);
+
+  if (check_pblendw (&x, &dst.s[16], &src3.s[0]))
+    abort ();
+
+  if (check_pblendw (&y, &src3.s[0], &dst.s[16]))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c
new file mode 100644
index 000000000..8611b8248
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pcmpeqq.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+    } dst, src1, src2;
+  int i, sign=1;
+  long long is_eq;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.ll[i] = i * i * sign;
+      src2.ll[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cmpeq_epi64(src1.x [i / 2], src2.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      is_eq = src1.ll[i] == src2.ll[i] ? 0xffffffffffffffffLL : 0LL;
+      if (is_eq != dst.ll[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c
new file mode 100644
index 000000000..bef4d2d16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrb.c
@@ -0,0 +1,87 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+#include <smmintrin.h>
+
+#define msk0   0
+#define msk1   1
+#define msk2   2
+#define msk3   3
+#define msk4   4
+#define msk5   5
+#define msk6   6
+#define msk7   7
+#define msk8   8
+#define msk9   9
+#define msk10 10
+#define msk11 11
+#define msk12 12
+#define msk13 13
+#define msk14 14
+#define msk15 15
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      int i[4];
+      char c[16];
+    } val1;
+  int res[16], masks[16];
+  int i;
+
+  val1.i[0] = 0x04030201;
+  val1.i[1] = 0x08070605;
+  val1.i[2] = 0x0C0B0A09;
+  val1.i[3] = 0x100F0E0D;
+
+  res[0] = _mm_extract_epi8 (val1.x, msk0);
+  res[1] = _mm_extract_epi8 (val1.x, msk1);
+  res[2] = _mm_extract_epi8 (val1.x, msk2);
+  res[3] = _mm_extract_epi8 (val1.x, msk3);
+  res[4] = _mm_extract_epi8 (val1.x, msk4);
+  res[5] = _mm_extract_epi8 (val1.x, msk5);
+  res[6] = _mm_extract_epi8 (val1.x, msk6);
+  res[7] = _mm_extract_epi8 (val1.x, msk7);
+  res[8] = _mm_extract_epi8 (val1.x, msk8);
+  res[9] = _mm_extract_epi8 (val1.x, msk9);
+  res[10] = _mm_extract_epi8 (val1.x, msk10);
+  res[11] = _mm_extract_epi8 (val1.x, msk11);
+  res[12] = _mm_extract_epi8 (val1.x, msk12);
+  res[13] = _mm_extract_epi8 (val1.x, msk13);
+  res[14] = _mm_extract_epi8 (val1.x, msk14);
+  res[15] = _mm_extract_epi8 (val1.x, msk15);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+  masks[8] = msk8;
+  masks[9] = msk9;
+  masks[10] = msk10;
+  masks[11] = msk11;
+  masks[12] = msk12;
+  masks[13] = msk13;
+  masks[14] = msk14;
+  masks[15] = msk15;
+
+  for (i = 0; i < 16; i++)
+    if (res[i] != val1.c [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c
new file mode 100644
index 000000000..3091e5a05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrd.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+#include <smmintrin.h>
+
+
+#define msk0   0
+#define msk1   1
+#define msk2   2
+#define msk3   3
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      int i[4];
+    } val1;
+  int res[4], masks[4];
+  int i;
+
+  val1.i[0] = 0x04030201;
+  val1.i[1] = 0x08070605;
+  val1.i[2] = 0x0C0B0A09;
+  val1.i[3] = 0x100F0E0D;
+
+  res[0] = _mm_extract_epi32 (val1.x, msk0);
+  res[1] = _mm_extract_epi32 (val1.x, msk1);
+  res[2] = _mm_extract_epi32 (val1.x, msk2);
+  res[3] = _mm_extract_epi32 (val1.x, msk3);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for (i = 0; i < 4; i++)
+    if (res[i] != val1.i [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c
new file mode 100644
index 000000000..112dd37fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrq.c
@@ -0,0 +1,45 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define msk0   0
+#define msk1   1
+
+static void
+__attribute__((noinline))
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      long long ll[2];
+    } val1;
+  long long res[2];
+  int masks[2];
+  int i;
+
+  val1.ll[0] = 0x0807060504030201LL;
+  val1.ll[1] = 0x100F0E0D0C0B0A09LL;
+
+  res[0] = _mm_extract_epi64 (val1.x, msk0);
+  res[1] = _mm_extract_epi64 (val1.x, msk1);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+
+  for (i = 0; i < 2; i++)
+    if (res[i] != val1.ll [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c
new file mode 100644
index 000000000..2a0f03c07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pextrw.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define msk0   0
+#define msk1   1
+#define msk2   2
+#define msk3   3
+#define msk4   4
+#define msk5   5
+#define msk6   6
+#define msk7   7
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      int i[4];
+      short s[8];
+    } val1;
+  int res[8], masks[8];
+  int i;
+
+  val1.i[0] = 0x04030201;
+  val1.i[1] = 0x08070605;
+  val1.i[2] = 0x0C0B0A09;
+  val1.i[3] = 0x100F0E0D;
+
+  res[0] = _mm_extract_epi16 (val1.x, msk0);
+  res[1] = _mm_extract_epi16 (val1.x, msk1);
+  res[2] = _mm_extract_epi16 (val1.x, msk2);
+  res[3] = _mm_extract_epi16 (val1.x, msk3);
+  res[4] = _mm_extract_epi16 (val1.x, msk4);
+  res[5] = _mm_extract_epi16 (val1.x, msk5);
+  res[6] = _mm_extract_epi16 (val1.x, msk6);
+  res[7] = _mm_extract_epi16 (val1.x, msk7);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+
+  for (i = 0; i < 8; i++)
+    if (res[i] != val1.s [masks[i]])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c
new file mode 100644
index 000000000..c9f9c1cdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-2.c
@@ -0,0 +1,78 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O3 -msse4.1 -mno-avx2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+extern void abort (void);
+
+#define N 1024
+short a[N], c, e;
+unsigned short b[N], d, f;
+
+__attribute__((noinline)) short
+vecsmax (void)
+{
+  int i;
+  short r = -32768;
+  for (i = 0; i < N; ++i)
+    if (r < a[i]) r = a[i];
+  return r;
+}
+
+__attribute__((noinline)) unsigned short
+vecumax (void)
+{
+  int i;
+  unsigned short r = 0;
+  for (i = 0; i < N; ++i)
+    if (r < b[i]) r = b[i];
+  return r;
+}
+
+__attribute__((noinline)) short
+vecsmin (void)
+{
+  int i;
+  short r = 32767;
+  for (i = 0; i < N; ++i)
+    if (r > a[i]) r = a[i];
+  return r;
+}
+
+__attribute__((noinline)) unsigned short
+vecumin (void)
+{
+  int i;
+  unsigned short r = 65535;
+  for (i = 0; i < N; ++i)
+    if (r > b[i]) r = b[i];
+  return r;
+}
+
+static void
+TEST (void)
+{
+  int i;
+  for (i = 0; i < N; ++i)
+    {
+      a[i] = i - N / 2;
+      b[i] = i + 32768 - N / 2;
+    }
+  a[N / 3] = N;
+  a[2 * N / 3] = -N;
+  b[N / 5] = 32768 + N;
+  b[4 * N / 5] = 32768 - N;
+  if (vecsmax () != N || vecsmin () != -N)
+    abort ();
+  if (vecumax () != 32768 + N || vecumin () != 32768 - N)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c
new file mode 100644
index 000000000..95c5f059d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -msse4.1 -mno-avx2" } */
+
+#include "sse4_1-phminposuw-2.c"
+
+/* { dg-final { scan-assembler "phminposuw\[^\n\r\]*xmm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c
new file mode 100644
index 000000000..ab4683401
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-phminposuw.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM/8];
+      unsigned short s[NUM];
+    } src;
+  unsigned short minVal[NUM/8];
+  int minInd[NUM/8];
+  unsigned short minValScalar, minIndScalar;
+  int i, j, res;
+
+  for (i = 0; i < NUM; i++)
+    src.s[i] = i * i / (i + i / 3.14 + 1.0);
+
+  for (i = 0, j = 0; i < NUM; i += 8, j++)
+    {
+      res = _mm_cvtsi128_si32 (_mm_minpos_epu16 (src.x [i/8]));
+      minVal[j] = res & 0xffff;
+      minInd[j] = (res >> 16) & 0x3;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    {
+      minValScalar = src.s[i];
+      minIndScalar = 0;
+
+      for (j = i + 1; j < i + 8; j++)
+	if (minValScalar > src.s[j])
+	  {
+	    minValScalar = src.s[j];
+	    minIndScalar = j - i;
+	  }
+
+      if (minValScalar != minVal[i/8] && minIndScalar != minInd[i/8])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c
new file mode 100644
index 000000000..18427360f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrb.c
@@ -0,0 +1,110 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+#define msk4 0x04
+#define msk5 0x05
+#define msk6 0x06
+#define msk7 0x07
+#define msk8 0x08
+#define msk9 0x09
+#define mskA 0x0A
+#define mskB 0x0B
+#define mskC 0x0C
+#define mskD 0x0D
+#define mskE 0x0E
+#define mskF 0x0F
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+      unsigned char c[16];
+    } res [16], val, tmp;
+  int masks[16];
+  unsigned char ins[4] = { 3, 4, 5, 6 };
+  int i;
+
+  val.i[0] = 0x35251505;
+  val.i[1] = 0x75655545;
+  val.i[2] = 0xB5A59585;
+  val.i[3] = 0xF5E5D5C5;
+
+  /* Check pinsrb imm8, r32, xmm.  */
+  res[0].x = _mm_insert_epi8 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi8 (val.x, ins[0], msk1);
+  res[2].x = _mm_insert_epi8 (val.x, ins[0], msk2);
+  res[3].x = _mm_insert_epi8 (val.x, ins[0], msk3);
+  res[4].x = _mm_insert_epi8 (val.x, ins[0], msk4);
+  res[5].x = _mm_insert_epi8 (val.x, ins[0], msk5);
+  res[6].x = _mm_insert_epi8 (val.x, ins[0], msk6);
+  res[7].x = _mm_insert_epi8 (val.x, ins[0], msk7);
+  res[8].x = _mm_insert_epi8 (val.x, ins[0], msk8);
+  res[9].x = _mm_insert_epi8 (val.x, ins[0], msk9);
+  res[10].x = _mm_insert_epi8 (val.x, ins[0], mskA);
+  res[11].x = _mm_insert_epi8 (val.x, ins[0], mskB);
+  res[12].x = _mm_insert_epi8 (val.x, ins[0], mskC);
+  res[13].x = _mm_insert_epi8 (val.x, ins[0], mskD);
+  res[14].x = _mm_insert_epi8 (val.x, ins[0], mskE);
+  res[15].x = _mm_insert_epi8 (val.x, ins[0], mskF);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+  masks[4] = msk4;
+  masks[5] = msk5;
+  masks[6] = msk6;
+  masks[7] = msk7;
+  masks[8] = msk8;
+  masks[9] = msk9;
+  masks[10] = mskA;
+  masks[11] = mskB;
+  masks[12] = mskC;
+  masks[13] = mskD;
+  masks[14] = mskE;
+  masks[15] = mskF;
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp.x = val.x;
+      tmp.c[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrb imm8, m8, xmm.  */
+  for (i = 0; i < 16; i++)
+    {
+      res[i].x = _mm_insert_epi8 (val.x, ins[i % 4], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 16; i++)
+    {
+      tmp.x = val.x;
+      tmp.c[masks[i]] = ins[i % 4];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c
new file mode 100644
index 000000000..7a5d5fbc9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrd.c
@@ -0,0 +1,73 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+#define msk2 0x02
+#define msk3 0x03
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } res [4], val, tmp;
+  static unsigned int ins[4] = { 3, 4, 5, 6 };
+  int masks[4];
+  int i;
+
+  val.i[0] = 55;
+  val.i[1] = 55;
+  val.i[2] = 55;
+  val.i[3] = 55;
+
+  /* Check pinsrd imm8, r32, xmm.  */
+  res[0].x = _mm_insert_epi32 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi32 (val.x, ins[0], msk1);
+  res[2].x = _mm_insert_epi32 (val.x, ins[0], msk2);
+  res[3].x = _mm_insert_epi32 (val.x, ins[0], msk3);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+  masks[2] = msk2;
+  masks[3] = msk3;
+
+  for (i = 0; i < 4; i++)
+    {
+      tmp.x = val.x;
+      tmp.i[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrd imm8, m32, xmm.  */
+  for (i = 0; i < 4; i++)
+    {
+      res[i].x = _mm_insert_epi32 (val.x, ins[i], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 4; i++)
+    {
+      tmp.x = val.x;
+      tmp.i[masks[i]] = ins[i];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c
new file mode 100644
index 000000000..1ed0987bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pinsrq.c
@@ -0,0 +1,67 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+#include <string.h>
+
+#define msk0 0x00
+#define msk1 0x01
+
+static void
+__attribute__((noinline))
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long ll[2];
+    } res [4], val, tmp;
+  int masks[4];
+  static unsigned long long ins[2] =
+    { 0xAABBAABBAABBAABBLL, 0xCCDDCCDDCCDDCCDDLL };
+  int i;
+
+  val.ll[0] = 0x0807060504030201LL;
+  val.ll[1] = 0x100F0E0D0C0B0A09LL;
+
+  /* Check pinsrq imm8, r64, xmm.  */
+  res[0].x = _mm_insert_epi64 (val.x, ins[0], msk0);
+  res[1].x = _mm_insert_epi64 (val.x, ins[0], msk1);
+
+  masks[0] = msk0;
+  masks[1] = msk1;
+
+  for (i = 0; i < 2; i++)
+    {
+      tmp.x = val.x;
+      tmp.ll[masks[i]] = ins[0];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+    
+  /* Check pinsrq imm8, m64, xmm.  */
+  for (i = 0; i < 2; i++)
+    {
+      res[i].x = _mm_insert_epi64 (val.x, ins[i], msk0);
+      masks[i] = msk0;
+    }
+
+  for (i = 0; i < 2; i++)
+    {
+      tmp.x = val.x;
+      tmp.ll[masks[i]] = ins[i];
+      if (memcmp (&tmp, &res[i], sizeof (tmp)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c
new file mode 100644
index 000000000..ab445eefd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsb.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 1024
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 16];
+      char i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  char max;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 16)
+    dst.x[i / 16] = _mm_max_epi8 (src1.x[i / 16], src2.x[i / 16]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (max != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c
new file mode 100644
index 000000000..37c77aef5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxsd.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  int max;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_max_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (max != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c
new file mode 100644
index 000000000..693c078fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxud.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned int i[NUM];
+    } dst, src1, src2;
+  int i;
+  unsigned int max;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i;
+      src2.i[i] = i + 20;
+      if ((i % 4))
+	src2.i[i] |= 0x80000000;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_max_epu32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (max != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c
new file mode 100644
index 000000000..7b5cfcd8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmaxuw.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 8];
+      unsigned short i[NUM];
+    } dst, src1, src2;
+  int i;
+  unsigned short max;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i;
+      src2.i[i] = i + 20;
+      if ((i % 8))
+	src2.i[i] |= 0x8000;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    dst.x[i / 8] = _mm_max_epu16 (src1.x[i / 8], src2.x[i / 8]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (max != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c
new file mode 100644
index 000000000..6f32d8b83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminsb.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 1024
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 16];
+      char i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  char min;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 16)
+    dst.x[i / 16] = _mm_min_epi8 (src1.x[i / 16], src2.x[i / 16]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (min != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c
new file mode 100644
index 000000000..a3de148a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminsd.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  int min;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_min_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (min != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c
new file mode 100644
index 000000000..9daffc070
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminud.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned int i[NUM];
+    } dst, src1, src2;
+  int i;
+  unsigned int min;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i;
+      src2.i[i] = i + 20;
+      if ((i % 4))
+	src2.i[i] |= 0x80000000;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_min_epu32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (min != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c
new file mode 100644
index 000000000..6ed5d9e2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pminuw.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 8];
+      unsigned short i[NUM];
+    } dst, src1, src2;
+  int i;
+  unsigned short min;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i;
+      src2.i[i] = i + 20;
+      if ((i % 8))
+	src2.i[i] |= 0x8000;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    dst.x[i / 8] = _mm_min_epu16 (src1.x[i / 8], src2.x[i / 8]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      min = src1.i[i] >= src2.i[i] ? src2.i[i] : src1.i[i];
+      if (min != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c
new file mode 100644
index 000000000..00ce3ef77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbd.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+      char c[NUM * 4];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 4) + (i / 4) * 16] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x [i / 4] = _mm_cvtepi8_epi32 (src.x [i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c
new file mode 100644
index 000000000..0df6a61c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+      char c[NUM * 8];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 2) + (i / 2) * 16] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepi8_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c
new file mode 100644
index 000000000..36accff4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxbw.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 8];
+      short s[NUM];
+      char c[NUM * 2];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 8) + (i / 8) * 16] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    dst.x [i / 8] = _mm_cvtepi8_epi16 (src.x [i / 8]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c
new file mode 100644
index 000000000..e46ba1961
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxdq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+      int i[NUM * 2];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.i[(i % 2) + (i / 2) * 4] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepi32_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c
new file mode 100644
index 000000000..61d9d3c2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwd.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+      short s[NUM * 2];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.s[(i % 4) + (i / 4) * 8] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x [i / 4] = _mm_cvtepi16_epi32 (src.x [i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c
new file mode 100644
index 000000000..160d6467d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovsxwq.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+      short s[NUM * 4];
+    } dst, src;
+  int i, sign = 1;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.s[(i % 2) + (i / 2) * 8] = i * i * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepi16_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c
new file mode 100644
index 000000000..6ebd6cf4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbd.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned int i[NUM];
+      unsigned char c[NUM * 4];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 4) + (i / 4) * 16] = i * i;
+      if ((i % 4))
+	src.c[(i % 4) + (i / 4) * 16] |= 0x80;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x [i / 4] = _mm_cvtepu8_epi32 (src.x [i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 4) + (i / 4) * 16] != dst.i[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c
new file mode 100644
index 000000000..8b2f18a22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      unsigned long long ll[NUM];
+      unsigned char c[NUM * 8];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 2) + (i / 2) * 16] = i * i;
+      if ((i % 2))
+	src.c[(i % 2) + (i / 2) * 16] |= 0x80;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepu8_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 2) + (i / 2) * 16] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c
new file mode 100644
index 000000000..8e1452bf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxbw.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 8];
+      unsigned short s[NUM];
+      unsigned char c[NUM * 2];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.c[(i % 8) + (i / 8) * 16] = i * i;
+      if ((i % 4))
+	src.c[(i % 8) + (i / 8) * 16] |= 0x80;
+    }
+
+  for (i = 0; i < NUM; i += 8)
+    dst.x [i / 8] = _mm_cvtepu8_epi16 (src.x [i / 8]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.c[(i % 8) + (i / 8) * 16] != dst.s[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c
new file mode 100644
index 000000000..cb2a4383e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxdq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      unsigned long long ll[NUM];
+      unsigned int i[NUM * 2];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.i[(i % 2) + (i / 2) * 4] = i * i;
+      if ((i % 2))
+        src.i[(i % 2) + (i / 2) * 4] |= 0x80000000;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepu32_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.i[(i % 2) + (i / 2) * 4] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c
new file mode 100644
index 000000000..b525f4c6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwd.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      unsigned int i[NUM];
+      unsigned short s[NUM * 2];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.s[(i % 4) + (i / 4) * 8] = i * i;
+      if ((i % 4))
+	src.s[(i % 4) + (i / 4) * 8] |= 0x8000;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x [i / 4] = _mm_cvtepu16_epi32 (src.x [i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.s[(i % 4) + (i / 4) * 8] != dst.i[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c
new file mode 100644
index 000000000..98f552aac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmovzxwq.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 128
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      unsigned long long ll[NUM];
+      unsigned short s[NUM * 4];
+    } dst, src;
+  int i;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src.s[(i % 2) + (i / 2) * 8] = i * i;
+      if ((i % 2))
+	src.s[(i % 2) + (i / 2) * 8] |= 0x8000;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x [i / 2] = _mm_cvtepu16_epi64 (src.x [i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    if (src.s[(i % 2) + (i / 2) * 8] != dst.ll[i])
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c
new file mode 100644
index 000000000..fc3830a45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmuldq.c
@@ -0,0 +1,51 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+    } dst;
+  union
+    {
+      __m128i x[NUM / 2];
+      int i[NUM * 2];
+    } src1, src2;
+  int i, sign = 1;
+  long long value;
+
+  for (i = 0; i < NUM * 2; i += 2)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x[i / 2] = _mm_mul_epi32 (src1.x[i / 2], src2.x[i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      value = (long long) src1.i[i * 2] * (long long) src2.i[i * 2];
+      if (value != dst.ll[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c
new file mode 100644
index 000000000..9fb77d0ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-pmulld.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 4];
+      int i[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  int value;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.i[i] = i * i * sign;
+      src2.i[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 4)
+    dst.x[i / 4] = _mm_mullo_epi32 (src1.x[i / 4], src2.x[i / 4]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      value = src1.i[i] * src2.i[i];
+      if (value != dst.i[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c
new file mode 100644
index 000000000..8b57a2111
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-1.c
@@ -0,0 +1,117 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static int
+make_ptestz (__m128i m, __m128i v)
+{
+  union
+    {
+      __m128i x;
+      unsigned char c[16];
+    } val, mask;
+  int i, z;
+
+  mask.x = m;
+  val.x = v;
+
+  z = 1;
+  for (i = 0; i < 16; i++)
+    if ((mask.c[i] & val.c[i]))
+      {
+	z = 0;
+	break;
+      }
+  return z;
+}
+
+static int
+make_ptestc (__m128i m, __m128i v)
+{
+  union
+    {
+      __m128i x;
+      unsigned char c[16];
+    } val, mask;
+  int i, c;
+
+  mask.x = m;
+  val.x = v;
+
+  c = 1;
+  for (i = 0; i < 16; i++)
+    if ((val.c[i] & ~mask.c[i]))
+      {
+	c = 0;
+	break;
+      }
+  return c;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } val[4];
+  int i, j, l;
+  int res[32];
+
+  val[0].i[0] = 0x11111111;
+  val[0].i[1] = 0x00000000;
+  val[0].i[2] = 0x00000000;
+  val[0].i[3] = 0x11111111;
+    
+  val[1].i[0] = 0x00000000;
+  val[1].i[1] = 0x11111111;
+  val[1].i[2] = 0x11111111;
+  val[1].i[3] = 0x00000000;
+
+  val[2].i[0] = 0;
+  val[2].i[1] = 0;
+  val[2].i[2] = 0;
+  val[2].i[3] = 0;
+
+  val[3].i[0] = 0xffffffff;
+  val[3].i[1] = 0xffffffff;
+  val[3].i[2] = 0xffffffff;
+  val[3].i[3] = 0xffffffff;
+
+  l = 0;
+  for(i = 0; i < 4; i++)
+    for(j = 0; j < 4; j++)
+      {
+	res[l++] = _mm_testz_si128 (val[j].x, val[i].x);
+	res[l++] = _mm_testc_si128 (val[j].x, val[i].x);
+      }
+
+  l = 0;
+  for(i = 0; i < 4; i++)
+    for(j = 0; j < 4; j++)
+      {
+	if (res[l++] != make_ptestz (val[j].x, val[i].x))
+	  abort ();
+	if (res[l++] != make_ptestc (val[j].x, val[i].x))
+	  abort ();
+      }
+
+  if (res[2] != _mm_testz_si128 (val[1].x, val[0].x))
+    abort ();
+
+  if (res[3] != _mm_testc_si128 (val[1].x, val[0].x))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c
new file mode 100644
index 000000000..2e6df9538
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-2.c
@@ -0,0 +1,96 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static int
+make_ptestnzc (__m128i m, __m128i v)
+{
+  union
+    {
+      __m128i x;
+      unsigned char c[16];
+    } val, mask;
+  int i, z, c;
+
+  mask.x = m;
+  val.x = v;
+
+  z = c = 1;
+  for (i = 0; i < 16; i++)
+    {
+      if ((mask.c[i] & val.c[i]))
+	z = 0;
+      if ((~mask.c[i] & val.c[i]))
+	c = 0;
+    }
+
+  return (z == 0 && c == 0) ? 1 : 0;
+}
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } val[4];
+  int i, j, l;
+  int res[32];
+
+  val[0].i[0] = 0x11111111;
+  val[0].i[1] = 0x00000000;
+  val[0].i[2] = 0x00000000;
+  val[0].i[3] = 0x11111111;
+    
+  val[1].i[0] = 0x00000000;
+  val[1].i[1] = 0x11111111;
+  val[1].i[2] = 0x11111111;
+  val[1].i[3] = 0x00000000;
+
+  val[2].i[0] = 0;
+  val[2].i[1] = 0;
+  val[2].i[2] = 0;
+  val[2].i[3] = 0;
+
+  val[3].i[0] = 0xffffffff;
+  val[3].i[1] = 0xffffffff;
+  val[3].i[2] = 0xffffffff;
+  val[3].i[3] = 0xffffffff;
+
+  l = 0;
+  for(i = 0; i < 4; i++)
+    for(j = 0; j < 4; j++)
+      {
+	res[l++] = _mm_testnzc_si128 (val[j].x, val[i].x);
+	res[l++] = _mm_testnzc_si128 (val[j].x, val[i].x);
+      }
+
+  l = 0;
+  for(i = 0; i < 4; i++)
+    for(j = 0; j < 4; j++)
+      {
+	if (res[l++] != make_ptestnzc (val[j].x, val[i].x))
+	  abort ();
+	if (res[l++] != make_ptestnzc (val[j].x, val[i].x))
+	  abort ();
+      }
+
+  if (res[2] != _mm_testnzc_si128 (val[1].x, val[0].x))
+    abort ();
+
+  if (res[3] != _mm_testnzc_si128 (val[1].x, val[0].x))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c
new file mode 100644
index 000000000..bf2df320e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-ptest-3.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } val[4];
+  int correct_zeros[4];
+  int correct_ones[4];
+  int correct_mixed[4];
+  int zeros[4];
+  int ones[4];
+  int mixed[4];
+  int i;
+  __m128i v;
+
+  val[0].i[0] = 0x11111111;
+  val[0].i[1] = 0x00000000;
+  val[0].i[2] = 0x00000000;
+  val[0].i[3] = 0x11111111;
+  correct_zeros[0] = 0;
+  correct_ones[0] = 0;
+  correct_mixed[0] = 1;
+    
+  val[1].i[0] = 0x00000000;
+  val[1].i[1] = 0x11111111;
+  val[1].i[2] = 0x11111111;
+  val[1].i[3] = 0x00000000;
+  correct_zeros[1] = 0;
+  correct_ones[1] = 0;
+  correct_mixed[1] = 1;
+
+  val[2].i[0] = 0;
+  val[2].i[1] = 0;
+  val[2].i[2] = 0;
+  val[2].i[3] = 0;
+  correct_zeros[2] = 1;
+  correct_ones[2] = 0;
+  correct_mixed[2] = 0;
+
+  val[3].i[0] = 0xffffffff;
+  val[3].i[1] = 0xffffffff;
+  val[3].i[2] = 0xffffffff;
+  val[3].i[3] = 0xffffffff;
+  correct_zeros[3] = 0;
+  correct_ones[3] = 1;
+  correct_mixed[3] = 0;
+
+  for (i=0; i < 4; i++)
+    zeros[i] = _mm_test_all_zeros (val[i].x, val[i].x);
+
+  for( i=0; i < 4; i++ )
+    ones[i] = _mm_test_all_ones (val[i].x);
+
+  v = _mm_cmpeq_epi32 (val[0].x, val[0].x);
+  for( i=0; i < 4; i++ )
+    mixed[i] = _mm_test_mix_ones_zeros (val[i].x, v);
+
+  for( i=0; i < 4; i++ )
+    {
+      if (zeros[i] != correct_zeros[i])
+	abort ();
+      if (ones[i] != correct_ones[i])
+	abort ();
+      if (mixed[i] != correct_mixed[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c
new file mode 100644
index 000000000..d9c2fbf2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rint-sfix-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double rint (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) rint (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) rint (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c
new file mode 100644
index 000000000..f20359a1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rint-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double rint (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  double r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = rint (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != rint (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c
new file mode 100644
index 000000000..1d25f7669
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rintf-sfix-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern float rintf (float);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) rintf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) rintf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c
new file mode 100644
index 000000000..716cad1e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-rintf-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern float rintf (float);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  float r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = rintf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != rintf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c
new file mode 100644
index 000000000..9abbe55b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round-sfix-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double round (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) round (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) round (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c
new file mode 100644
index 000000000..bb912cef9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double round (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  double r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = round (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != round (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round.h
new file mode 100644
index 000000000..0210ac130
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-round.h
@@ -0,0 +1,95 @@
+#include <smmintrin.h>
+#include <math.h>
+
+#define NUM 64
+
+static void
+init_round (FP_T *src)
+{
+  int i, sign = 1;
+  FP_T f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1)* f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI *sign);
+      sign = -sign;
+    }
+}
+
+static FP_T
+do_round (FP_T f, int type)
+{
+  short saved_cw, new_cw, clr_mask;
+  FP_T ret;
+
+  if ((type & 4))
+    {
+      type = 0;
+      clr_mask = 0xFFFF;
+    }
+  else
+    {
+      type = 0x003F | ((type & 3) << 10);
+      clr_mask = ~0x0C3F;
+    }
+
+  __asm__ ("fld" ASM_SUFFIX " %0" : : "m" (*&f));
+
+  __asm__ ("fstcw %0" : "=m" (*&saved_cw));
+  new_cw = saved_cw & clr_mask;
+  new_cw |= type;
+  __asm__ ("fldcw %0" : : "m" (*&new_cw));
+
+  __asm__ ("frndint\n"
+	   "fstp" ASM_SUFFIX " %0\n" : "=m" (*&ret));
+  __asm__ ("fldcw %0" : : "m" (*&saved_cw));
+  return ret;
+}
+
+static void
+sse4_1_test (void)
+{
+  int i;
+  FP_T f;
+  union
+    {
+      VEC_T x[NUM / LOOP_INCREMENT];
+      FP_T f[NUM];
+    } dst, src;
+
+  init_round (src.f);
+
+  for (i = 0; i < NUM / LOOP_INCREMENT; i++)
+    dst.x[i] =  ROUND_INTRIN (src.x[i], ROUND_MODE);
+
+  for (i = 0; i < NUM; i += CHECK_LOOP_INCREMENT)
+    {
+      f = do_round (src.f[i], CHECK_ROUND_MODE);
+     if (f != dst.f[i])
+       abort ();
+    }
+
+  if (_MM_FROUND_TO_NEAREST_INT != 0x00
+      || _MM_FROUND_TO_NEG_INF != 0x01
+      || _MM_FROUND_TO_POS_INF != 0x02
+      || _MM_FROUND_TO_ZERO != 0x03
+      || _MM_FROUND_CUR_DIRECTION != 0x04
+      || _MM_FROUND_RAISE_EXC != 0x00
+      || _MM_FROUND_NO_EXC != 0x08
+      || _MM_FROUND_NINT != 0x00
+      || _MM_FROUND_FLOOR != 0x01
+      || _MM_FROUND_CEIL != 0x02
+      || _MM_FROUND_TRUNC != 0x03
+      || _MM_FROUND_RINT != 0x04
+      || _MM_FROUND_NEARBYINT != 0x0C)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c
new file mode 100644
index 000000000..5384e5c62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundf-sfix-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern float roundf (float);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  int r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = (int) roundf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != (int) roundf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c
new file mode 100644
index 000000000..d254aa66b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundf-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern float roundf (float);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  float r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = roundf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != roundf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c
new file mode 100644
index 000000000..8baee3390
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-1.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+#define iRoundMode 0x2
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  double e[2] = {0.0};
+  int i;
+
+  s.x = _mm_set_pd (1.1234, -2.3478);
+  u.x = _mm_round_pd (s.x, iRoundMode);
+
+  for (i = 0; i < 2; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s.a[i]);
+      tmp = _mm_round_sd (tmp, tmp, iRoundMode);
+      _mm_store_sd (&e[i], tmp);
+    }
+  
+  if (check_union128d (u, e))
+    abort ();
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c
new file mode 100644
index 000000000..86b78ed75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-2.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  double e[2] = {0.0};
+  int i;
+
+  s.x = _mm_set_pd (1.1234, -2.3478);
+  u.x = _mm_floor_pd (s.x);
+
+  for (i = 0; i < 2; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s.a[i]);
+      tmp = _mm_floor_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+  
+  if (check_union128d (u, e))
+    abort ();
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c
new file mode 100644
index 000000000..6e6a05c59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundpd-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <smmintrin.h>
+
+static void
+TEST (void)
+{
+  union128d u, s;
+  double e[2] = {0.0};
+  int i;
+
+  s.x = _mm_set_pd (1.1234, -2.3478);
+  u.x = _mm_ceil_pd (s.x);
+
+  for (i = 0; i < 2; i++)
+    {
+      __m128d tmp = _mm_load_sd (&s.a[i]);
+      tmp = _mm_ceil_sd (tmp, tmp);
+      _mm_store_sd (&e[i], tmp);
+    }
+  
+  if (check_union128d (u, e))
+    abort ();
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c
new file mode 100644
index 000000000..71bc51be2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-1.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_ceil_ps(x)
+#define ROUND_MODE _MM_FROUND_CEIL
+#define CHECK_ROUND_MODE 0x02
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 1
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c
new file mode 100644
index 000000000..672e92067
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-2.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN _mm_round_ps
+#define ROUND_MODE _MM_FROUND_NINT
+#define CHECK_ROUND_MODE 0x00
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 1
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c
new file mode 100644
index 000000000..4bfc1cacc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundps-3.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_floor_ps(x)
+#define ROUND_MODE _MM_FROUND_FLOOR
+#define CHECK_ROUND_MODE 0x01
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 1
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c
new file mode 100644
index 000000000..ae8881cf0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-1.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128d
+#define FP_T double
+#define ASM_SUFFIX "l"
+
+#define ROUND_INTRIN(x, mode) _mm_ceil_sd(x, x)
+#define ROUND_MODE _MM_FROUND_CEIL
+#define CHECK_ROUND_MODE 0x02
+
+#define LOOP_INCREMENT 2
+#define CHECK_LOOP_INCREMENT 2
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c
new file mode 100644
index 000000000..70679bb07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-2.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128d
+#define FP_T double
+#define ASM_SUFFIX "l"
+
+#define ROUND_INTRIN(x, mode) _mm_round_sd(x, x, mode)
+#define ROUND_MODE _MM_FROUND_NINT
+#define CHECK_ROUND_MODE 0x00
+
+#define LOOP_INCREMENT 2
+#define CHECK_LOOP_INCREMENT 2
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c
new file mode 100644
index 000000000..81a3f7606
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-3.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128d
+#define FP_T double
+#define ASM_SUFFIX "l"
+
+#define ROUND_INTRIN(x, mode) _mm_floor_sd(x, x)
+#define ROUND_MODE _MM_FROUND_FLOOR
+#define CHECK_ROUND_MODE 0x01
+
+#define LOOP_INCREMENT 2
+#define CHECK_LOOP_INCREMENT 2
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c
new file mode 100644
index 000000000..124f82502
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundsd-4.c
@@ -0,0 +1,92 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <math.h>
+#include <string.h>
+
+#define NUM 64
+
+static void
+init_round (double *src)
+{
+  int i, sign = 1;
+  double d = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1)* d * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    d = d * src[i];
+        }
+      else if (i == (NUM / 2))
+	d = rand ();
+      else if ((i % 6) == 0)
+	d = 1 / (d * (i + 1) * src[i] * M_PI *sign);
+      sign = -sign;
+    }
+}
+
+static double
+do_round (double f, int type)
+{
+  short saved_cw, new_cw, clr_mask;
+  double ret;
+
+  if ((type & 4))
+    {
+      type = 0;
+      clr_mask = 0xFFFF;
+    }
+  else
+    {
+      type = 0x003F | ((type & 3) << 10);
+      clr_mask = ~0x0C3F;
+    }
+
+  __asm__ ("fldl %0" : : "m" (*&f));
+
+  __asm__ ("fstcw %0" : "=m" (*&saved_cw));
+  new_cw = saved_cw & clr_mask;
+  new_cw |= type;
+  __asm__ ("fldcw %0" : : "m" (*&new_cw));
+
+  __asm__ ("frndint\n"
+	   "fstpl %0\n" : "=m" (*&ret));
+  __asm__ ("fldcw %0" : : "m" (*&saved_cw));
+  return ret;
+}
+
+static void
+sse4_1_test (void)
+{
+  int i;
+  double f;
+  union
+    {
+      __m128d x[NUM / 2];
+      double d[NUM];
+    } dst, src;
+
+  init_round (src.d);
+  memset (&dst, 0, NUM * sizeof(double));
+
+  for (i = 0; i < NUM / 2 ; i++)
+    dst.x[i] =  _mm_round_sd (dst.x[i], src.x[i], _MM_FROUND_TRUNC);
+
+  for (i = 0; i < NUM; i += 2)
+    {
+      if (dst.d[i + 1] != 0.0)
+	abort ();
+
+      f = do_round (src.d[i], 0x03);
+      if (f != dst.d[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c
new file mode 100644
index 000000000..96dd8a6a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-1.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_ceil_ss(x, x)
+#define ROUND_MODE _MM_FROUND_CEIL
+#define CHECK_ROUND_MODE 0x02
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 4
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c
new file mode 100644
index 000000000..f052c029f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-2.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_round_ss(x, x, mode)
+#define ROUND_MODE _MM_FROUND_NINT
+#define CHECK_ROUND_MODE 0x00
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 4
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c
new file mode 100644
index 000000000..0a696b1cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-3.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#define VEC_T __m128
+#define FP_T float
+#define ASM_SUFFIX "s"
+
+#define ROUND_INTRIN(x, mode) _mm_floor_ss(x, x)
+#define ROUND_MODE _MM_FROUND_FLOOR
+#define CHECK_ROUND_MODE 0x01
+
+#define LOOP_INCREMENT 4
+#define CHECK_LOOP_INCREMENT 4
+
+#include "sse4_1-round.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c
new file mode 100644
index 000000000..71042d1b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-roundss-4.c
@@ -0,0 +1,107 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#include "sse4_1-check.h"
+
+#include <smmintrin.h>
+#include <math.h>
+#include <string.h>
+
+#define NUM 64
+
+static void
+init_round (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1)* f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI *sign);
+      sign = -sign;
+    }
+}
+
+static float
+do_round (float f, int type)
+{
+  short saved_cw, new_cw, clr_mask;
+  float ret;
+
+  if ((type & 4))
+    {
+      type = 0;
+      clr_mask = 0xFFFF;
+    }
+  else
+    {
+      type = 0x003F | ((type & 3) << 10);
+      clr_mask = ~0x0C3F;
+    }
+
+  __asm__ ("flds %0" : : "m" (*&f));
+
+  __asm__ ("fstcw %0" : "=m" (*&saved_cw));
+  new_cw = saved_cw & clr_mask;
+  new_cw |= type;
+  __asm__ ("fldcw %0" : : "m" (*&new_cw));
+
+  __asm__ ("frndint\n"
+	   "fstps %0\n" : "=m" (*&ret));
+  __asm__ ("fldcw %0" : : "m" (*&saved_cw));
+  return ret;
+}
+
+static void
+sse4_1_test (void)
+{
+  int i, j;
+  float f;
+  union
+    {
+      __m128 x[NUM / 4];
+      float f[NUM];
+    } dst, src;
+
+  init_round (src.f);
+  memset (&dst, 0, NUM * sizeof(float));
+
+  for (i = 0; i < NUM / 4 ; i++)
+    dst.x[i] =  _mm_round_ss (dst.x[i], src.x[i], _MM_FROUND_RINT);
+
+  for (i = 0; i < NUM; i += 4)
+    {
+      for (j = 0; j < 3; j++)
+	if (dst.f[i + j + 1] != 0.0)
+	  abort ();
+
+      f = do_round (src.f[i], 0x04);
+      if (f != dst.f[i])
+	abort ();
+    }
+
+  for (i = 0; i < NUM / 4 ; i++)
+    dst.x[i] =  _mm_round_ss (dst.x[i], src.x[i], _MM_FROUND_NEARBYINT);
+
+  for (i = 0; i < NUM; i += 4)
+    {
+      for (j = 0; j < 3; j++)
+	if (dst.f[i + j + 1] != 0.0)
+	  abort ();
+
+      f = do_round (src.f[i], 0x0c);
+      if (f != dst.f[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c
new file mode 100644
index 000000000..989e4f708
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-epi32-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+test (unsigned int *v)
+{
+  union
+    {
+      __m128i x;
+      unsigned int i[4];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_epi32 (v[3], v[2], v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.i[i])
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%x != 0x%x\n", i, v[i], u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned int v[4]
+    = { 0x7B5B5465, 0x73745665, 0x63746F72, 0x5D53475D };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c
new file mode 100644
index 000000000..8679f5286
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-epi64x-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <emmintrin.h>
+
+static void
+__attribute__((noinline))
+test (unsigned long long *v)
+{
+  union
+    {
+      __m128i x;
+      unsigned long long i[2];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_epi64x (v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.i[i])
+      {
+#ifdef DEBUG
+	printf ("%i: 0x%llx != 0x%llx\n", i, v[i], u.i[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse4_1_test (void)
+{
+  unsigned long long v[2]
+    = { 0x7B5B546573745665LL, 0x63746F725D53475DLL };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c
new file mode 100644
index 000000000..fe77d94ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-ps-1.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#include "sse4_1-check.h"
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+#include <xmmintrin.h>
+
+static void
+__attribute__((noinline))
+test (float *v)
+{
+  union
+    {
+      __m128 x;
+      float f[4];
+    } u;
+  unsigned int i;
+  
+  u.x = _mm_set_ps (v[3], v[2], v[1], v[0]);
+
+  for (i = 0; i < sizeof (v) / sizeof (v[0]); i++)
+    if (v[i] != u.f[i])
+      {
+#ifdef DEBUG
+	printf ("%i: %f != %f\n", i, v[i], u.f[i]);
+#endif
+	abort ();
+      }
+}
+
+static void
+sse4_1_test (void)
+{
+  float v[4] = { -3, 2, 1, 9 };
+  test (v);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c
new file mode 100644
index 000000000..23c090330
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c
new file mode 100644
index 000000000..b8612962d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-1a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-1.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c
new file mode 100644
index 000000000..524587082
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c
new file mode 100644
index 000000000..21f1692cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-2a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c
new file mode 100644
index 000000000..99f563ab1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-3.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c
new file mode 100644
index 000000000..1065a843a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-set-v16qi-3a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -mtune=core2 -msse4.1" } */
+
+#define CHECK_H "sse4_1-check.h"
+#define TEST sse4_1_test
+
+#include "set-v16qi-3.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c
new file mode 100644
index 000000000..9cbcd9b39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-trunc-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern double trunc (double);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (double *src)
+{
+  int i, sign = 1;
+  double f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  double a[NUM];
+  double r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = trunc (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != trunc (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c
new file mode 100644
index 000000000..815b50814
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_1-truncf-vec.c
@@ -0,0 +1,62 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse4.1" } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-skip-if "no M_PI" { vxworks_kernel } } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_1-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_1_test
+#endif
+
+#include CHECK_H
+
+#include <math.h>
+
+extern float truncf (float);
+
+#define NUM 64
+
+static void
+__attribute__((__target__("fpmath=sse")))
+init_src (float *src)
+{
+  int i, sign = 1;
+  float f = rand ();
+
+  for (i = 0; i < NUM; i++)
+    {
+      src[i] = (i + 1) * f * M_PI * sign;
+      if (i < (NUM / 2))
+	{
+          if ((i % 6) == 0)
+	    f = f * src[i];
+        }
+      else if (i == (NUM / 2))
+	f = rand ();
+      else if ((i % 6) == 0)
+	f = 1 / (f * (i + 1) * src[i] * M_PI * sign);
+      sign = -sign;
+    }
+}
+
+static void
+__attribute__((__target__("fpmath=387")))
+TEST (void)
+{
+  float a[NUM];
+  float r[NUM];
+  int i;
+
+  init_src (a);
+
+  for (i = 0; i < NUM; i++)
+    r[i] = truncf (a[i]);
+
+  /* check results:  */
+  for (i = 0; i < NUM; i++)
+    if (r[i] != truncf (a[i]))
+      abort();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-check.h
new file mode 100644
index 000000000..d10e6c7d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-check.h
@@ -0,0 +1,28 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void sse4_2_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  sse4_2_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE4.2 test only if host has SSE4.2 support.  */
+  if (ecx & bit_SSE4_2)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h
new file mode 100644
index 000000000..c0bcd16cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32.h
@@ -0,0 +1,163 @@
+#include "sse4_2-check.h"
+
+#include <nmmintrin.h>
+#include <string.h>
+
+#define POLYNOMIAL 0x11EDC6F41LL
+
+#define MAX_BUF 16
+
+static void
+shift_mem_by1 (unsigned char* buf, int len)
+{
+  int i;
+
+  for (i = len - 1; i >= 0; i--)
+    {
+      buf[i] = buf[i] << 1;
+      if (i > 0 && (buf[i-1] & 0x80))
+	buf[i] |= 1;
+   }
+}
+
+static void
+do_div (unsigned char* buf, unsigned char* div) 
+{
+  int i;
+  for (i = 0; i < 5; i++)
+    buf[i] ^= div[i];
+}
+
+static unsigned int
+calc_rem (unsigned char* buf, int len)
+{
+  union
+    {
+      unsigned long long ll;
+      unsigned char c[8];
+    } divisor;
+  union
+    {
+      unsigned int i;
+      unsigned char c[4];
+    } ret;
+  unsigned char *div_buf;
+  unsigned char divident[MAX_BUF];
+  int disp = len / 8;
+  int i;
+
+  divisor.ll = POLYNOMIAL << 7LL;
+
+  memcpy (divident, buf, disp);
+
+  div_buf = divident + disp - 5;
+
+  for (i = 0; i < len - 32; i++)
+    {
+      if ((div_buf[4] & 0x80)) 
+	do_div (div_buf, divisor.c);
+      shift_mem_by1 (divident, disp);
+   }
+
+  memcpy (ret.c, div_buf + 1, sizeof (ret));
+  return ret.i;
+}
+
+static void 
+reverse_bits (unsigned char *src, int len)
+{
+  unsigned char buf[MAX_BUF];
+  unsigned char *tmp = buf + len - 1;
+  unsigned char ch;
+  int i, j;
+
+  for (i = 0; i < len; i++)
+    {
+      ch = 0;
+      for (j = 0; j < 8; j++)
+	if ((src[i] & (1 << j)))
+	  ch |= 1 << (7 - j);
+      *tmp-- = ch;
+    }
+
+  for (i = 0; i < len; i++)
+    src[i] = buf[i];
+}
+
+static void 
+shift_mem ( unsigned char *src, unsigned char *dst, int len, int shft)
+{
+  int disp = shft / 8;
+  int i;
+   
+  memset (dst, 0, len + disp);
+  for (i = 0; i < len; i++)
+    dst[i + disp] = src[i];
+}
+
+static void 
+xor_mem (unsigned char *src, unsigned char *dst, int len)
+{
+  int disp = len / 8;
+  int i;
+   
+  for (i = 0; i < disp; i++)
+    dst[i] ^= src[i];
+}
+
+static DST_T
+compute_crc32 (DST_T crc, SRC_T inp)
+{
+  unsigned char crcbuf[sizeof (DST_T)];
+  unsigned char inbuf[sizeof (SRC_T)];
+  unsigned char tmp1[MAX_BUF], tmp2[MAX_BUF];
+  int crc_sh, xor_sz;
+  union
+    {
+      unsigned int i;
+      unsigned char c[4];
+    } ret;
+
+  crc_sh = sizeof (SRC_T) * 8;
+  xor_sz = 32 + crc_sh;
+  memcpy (crcbuf, &crc, sizeof (DST_T));
+  memcpy (inbuf, &inp, sizeof (SRC_T));
+   
+  reverse_bits (crcbuf, 4);
+  reverse_bits (inbuf, sizeof (SRC_T));
+
+  shift_mem (inbuf, tmp1, sizeof (SRC_T), 32);
+  shift_mem (crcbuf, tmp2, 4, crc_sh);
+
+  xor_mem (tmp1, tmp2, xor_sz);
+
+  ret.i = calc_rem (tmp2, xor_sz);
+  
+  reverse_bits (ret.c, 4);
+
+  return (DST_T)ret.i;
+}
+
+#define NUM 1024
+
+static void
+sse4_2_test (void)
+{
+  DST_T dst[NUM]; 
+  SRC_T src[NUM];
+  int i;
+
+ for (i = 0; i < NUM; i++)
+   {
+     dst[i] = rand ();
+     if (sizeof (DST_T) > 4)
+       dst[i] |= (DST_T)rand () << (DST_T)(sizeof (DST_T) * 4);
+     src[i] = rand ();
+     if (sizeof (SRC_T) > 4)
+       src[i] |= (SRC_T)rand () << (SRC_T)(sizeof (DST_T) * 4);
+   }
+
+  for (i = 0; i < NUM; i++)
+    if (CRC32 (dst[i], src[i]) != compute_crc32 (dst[i], src[i]))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c
new file mode 100644
index 000000000..05a609cd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32b.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define CRC32 _mm_crc32_u8
+#define DST_T unsigned int
+#define SRC_T unsigned char
+
+#include "sse4_2-crc32.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c
new file mode 100644
index 000000000..00cdf6ad3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32l.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define CRC32 _mm_crc32_u32
+#define DST_T unsigned int
+#define SRC_T unsigned int
+
+#include "sse4_2-crc32.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c
new file mode 100644
index 000000000..f1f75d916
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32q.c
@@ -0,0 +1,9 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define CRC32 _mm_crc32_u64
+#define DST_T unsigned long long
+#define SRC_T unsigned long long
+
+#include "sse4_2-crc32.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c
new file mode 100644
index 000000000..03991e553
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-crc32w.c
@@ -0,0 +1,9 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define CRC32 _mm_crc32_u16
+#define DST_T unsigned int
+#define SRC_T unsigned short
+
+#include "sse4_2-crc32.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c
new file mode 100644
index 000000000..5b7f3ad77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-1.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+ (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+  | _SIDD_MOST_SIGNIFICANT)
+#define IMM_VAL2 \
+ (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_LEAST_SIGNIFICANT)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  int res, correct, l1, l2;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      l1 = rand () % 18;
+      l2 = rand () % 18;
+
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0,
+			    NULL);
+	  break;
+
+	case 1:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1,
+			    NULL);
+	  break;
+
+	case 2:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2,
+			    NULL);
+	  break;
+
+	default:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3,
+			    NULL);
+	  break;
+        }
+
+      if (correct != res)
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c
new file mode 100644
index 000000000..800084ff6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestri-2.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+ (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+  | _SIDD_MOST_SIGNIFICANT)
+#define IMM_VAL2 \
+ (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_LEAST_SIGNIFICANT)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  int res, correct, correct_flags, l1, l2;
+  int flags, cf, zf, sf, of, af;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      l1 = rand () % 18;
+      l2 = rand () % 18;
+
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0,
+			    &correct_flags);
+	  break;
+
+	case 1:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1,
+			    &correct_flags);
+	  break;
+
+	case 2:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2,
+			    &correct_flags);
+	  break;
+
+	default:
+	  res = _mm_cmpestri (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  correct = cmp_ei (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3,
+			    &correct_flags);
+	  break;
+	}
+      
+      if (correct != res)
+	abort ();
+
+      flags = 0;
+      if (cf)
+	flags |= CFLAG;
+      if (zf)
+	flags |= ZFLAG;
+      if (sf)
+	flags |= SFLAG;
+      if (of)
+	flags |= OFLAG;
+      
+      if (flags != correct_flags
+	  || (af && (cf || zf))
+	  || (!af && !(cf || zf)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c
new file mode 100644
index 000000000..f02bb7e69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-1.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+  (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+   | _SIDD_BIT_MASK)
+#define IMM_VAL2 \
+  (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  __m128i res, correct;
+  int l1, l2;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      l1 = rand () % 18;
+      l2 = rand () % 18;
+
+      switch((rand() % 4))
+	{
+	case 0:
+	  res  = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0,
+			    NULL);
+	  break;
+
+	case 1:
+	  res  = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1,
+			    NULL);
+	  break;
+
+	case 2:
+	  res  = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2,
+			    NULL);
+	  break;
+
+	default:
+	  res  = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3,
+			    NULL);
+	  break;
+        }
+
+      if (memcmp (&correct, &res, sizeof (res)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c
new file mode 100644
index 000000000..845471f0b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpestrm-2.c
@@ -0,0 +1,119 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+  (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+   | _SIDD_BIT_MASK)
+#define IMM_VAL2 \
+  (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK)
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  __m128i res, correct;
+  int correct_flags, l1, l2;
+  int flags, cf, zf, sf, of, af;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      l1 = rand () % 18;
+      l2 = rand () % 18;
+
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL0);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL0,
+			    &correct_flags);
+	  break;
+
+	case 1:
+	  res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL1);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL1,
+			    &correct_flags);
+	  break;
+
+	case 2:
+	  res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL2);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL2,
+			    &correct_flags);
+	  break;
+
+	default:	
+	  res = _mm_cmpestrm (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  cf = _mm_cmpestrc (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  zf = _mm_cmpestrz (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  sf = _mm_cmpestrs (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  of = _mm_cmpestro (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  af = _mm_cmpestra (src1.x[i], l1, src2.x[i], l2, IMM_VAL3);
+	  correct = cmp_em (&src1.x[i], l1, &src2.x[i], l2, IMM_VAL3,
+			    &correct_flags);
+	  break;
+	}
+      
+      if (memcmp (&correct, &res, sizeof (res)))
+	abort ();
+
+      flags = 0;
+      if (cf)
+	flags |= CFLAG;
+      if (zf)
+	flags |= ZFLAG;
+      if (sf)
+	flags |= SFLAG;
+      if (of)
+	flags |= OFLAG;
+      
+      if (flags != correct_flags
+	  || (af && (cf || zf))
+	  || (!af && !(cf || zf)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c
new file mode 100644
index 000000000..e2ef66f2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpgtq.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include <nmmintrin.h>
+
+#define NUM 64
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM / 2];
+      long long ll[NUM];
+    } dst, src1, src2;
+  int i, sign = 1;
+  long long is_eq;
+
+  for (i = 0; i < NUM; i++)
+    {
+      src1.ll[i] = i * i * sign;
+      src2.ll[i] = (i + 20) * sign;
+      sign = -sign;
+    }
+
+  for (i = 0; i < NUM; i += 2)
+    dst.x[i / 2] = _mm_cmpgt_epi64 (src1.x[i / 2], src2.x[i / 2]);
+
+  for (i = 0; i < NUM; i++)
+    {
+      is_eq = src1.ll[i] > src2.ll[i] ? 0xFFFFFFFFFFFFFFFFLL : 0LL;
+      if (is_eq != dst.ll[i])
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c
new file mode 100644
index 000000000..b74df024d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-1.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+ (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+  | _SIDD_MOST_SIGNIFICANT)
+#define IMM_VAL2 \
+ (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_MOST_SIGNIFICANT)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  int res, correct;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL0);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL0, NULL);
+	  break;
+
+	case 1:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL1);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL1, NULL);
+	  break;
+
+	case 2:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL2);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL2, NULL);
+	  break;
+
+	default:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL3);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL3, NULL);
+	  break;
+        }
+
+      if (correct != res)
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c
new file mode 100644
index 000000000..5aea655ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistri-2.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+ (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+  | _SIDD_MOST_SIGNIFICANT)
+#define IMM_VAL2 \
+ (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_MOST_SIGNIFICANT)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  int res, correct, correct_flags;
+  int flags, cf, zf, sf, of, af;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL0);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL0);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL0);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL0);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL0);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL0);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL0,
+			    &correct_flags);
+	  break;
+
+	case 1:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL1);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL1);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL1);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL1);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL1);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL1);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL1,
+			    &correct_flags);
+	  break;
+
+	case 2:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL2);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL2);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL2);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL2);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL2);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL2);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL2,
+			    &correct_flags);
+	  break;
+
+	default:
+	  res = _mm_cmpistri (src1.x[i], src2.x[i], IMM_VAL3);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL3);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL3);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL3);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL3);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL3);
+	  correct = cmp_ii (&src1.x[i], &src2.x[i], IMM_VAL3,
+			    &correct_flags);
+	  break;
+	}
+      
+      if (correct != res)
+	abort ();
+
+      flags = 0;
+      if (cf)
+	flags |= CFLAG;
+      if (zf)
+	flags |= ZFLAG;
+      if (sf)
+	flags |= SFLAG;
+      if (of)
+	flags |= OFLAG;
+      
+      if (flags != correct_flags
+	  || (af && (cf || zf))
+	  || (!af && !(cf || zf)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c
new file mode 100644
index 000000000..b8ec890cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-1.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+  (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+   | _SIDD_BIT_MASK)
+#define IMM_VAL2 \
+  (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_MASKED_NEGATIVE_POLARITY | _SIDD_UNIT_MASK)
+
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  __m128i res, correct;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      switch((rand() % 4))
+	{
+	case 0:
+	  res  = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL0);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL0, NULL);
+	  break;
+
+	case 1:
+	  res  = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL1);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL1, NULL);
+	  break;
+
+	case 2:
+	  res  = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL2);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL2, NULL);
+	  break;
+
+	default:
+	  res  = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL3);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL3, NULL);
+	  break;
+        }
+
+      if (memcmp (&correct, &res, sizeof (res)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c
new file mode 100644
index 000000000..c6896ee61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpistrm-2.c
@@ -0,0 +1,116 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#ifndef CHECK_H
+#define CHECK_H "sse4_2-check.h"
+#endif
+
+#ifndef TEST
+#define TEST sse4_2_test
+#endif
+
+#include CHECK_H
+
+#include "sse4_2-pcmpstr.h"
+
+#define NUM 1024
+
+#define IMM_VAL0 \
+  (_SIDD_SBYTE_OPS | _SIDD_CMP_RANGES | _SIDD_MASKED_POSITIVE_POLARITY)
+#define IMM_VAL1 \
+  (_SIDD_UBYTE_OPS | _SIDD_CMP_EQUAL_EACH | _SIDD_NEGATIVE_POLARITY \
+   | _SIDD_BIT_MASK)
+#define IMM_VAL2 \
+  (_SIDD_UWORD_OPS | _SIDD_CMP_EQUAL_ANY | _SIDD_MASKED_NEGATIVE_POLARITY)
+#define IMM_VAL3 \
+  (_SIDD_SWORD_OPS | _SIDD_CMP_EQUAL_ORDERED \
+   | _SIDD_POSITIVE_POLARITY | _SIDD_UNIT_MASK)
+
+static void
+TEST (void)
+{
+  union
+    {
+      __m128i x[NUM];
+      char c[NUM *16];
+    } src1, src2;
+  __m128i res, correct;
+  int correct_flags;
+  int flags, cf, zf, sf, of, af;
+  int i;
+
+  for (i = 0; i < NUM *16; i++)
+    {
+      src1.c[i] = rand ();
+      src2.c[i] = rand ();
+    }
+
+  for (i = 0; i < NUM; i++)
+    {
+      switch ((rand () % 4))
+	{
+	case 0:
+	  res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL0);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL0);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL0);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL0);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL0);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL0);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL0,
+			    &correct_flags);
+	  break;
+
+	case 1:
+	  res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL1);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL1);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL1);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL1);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL1);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL1);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL1,
+			    &correct_flags);
+	  break;
+
+	case 2:
+	  res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL2);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL2);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL2);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL2);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL2);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL2);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL2,
+			    &correct_flags);
+	  break;
+
+	default:	
+	  res = _mm_cmpistrm (src1.x[i], src2.x[i], IMM_VAL3);
+	  cf = _mm_cmpistrc (src1.x[i], src2.x[i], IMM_VAL3);
+	  zf = _mm_cmpistrz (src1.x[i], src2.x[i], IMM_VAL3);
+	  sf = _mm_cmpistrs (src1.x[i], src2.x[i], IMM_VAL3);
+	  of = _mm_cmpistro (src1.x[i], src2.x[i], IMM_VAL3);
+	  af = _mm_cmpistra (src1.x[i], src2.x[i], IMM_VAL3);
+	  correct = cmp_im (&src1.x[i], &src2.x[i], IMM_VAL3,
+			    &correct_flags);
+	  break;
+	}
+      
+      if (memcmp (&correct, &res, sizeof (res)))
+	abort ();
+
+      flags = 0;
+      if (cf)
+	flags |= CFLAG;
+      if (zf)
+	flags |= ZFLAG;
+      if (sf)
+	flags |= SFLAG;
+      if (of)
+	flags |= OFLAG;
+      
+      if (flags != correct_flags
+	  || (af && (cf || zf))
+	  || (!af && !(cf || zf)))
+	abort ();
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h
new file mode 100644
index 000000000..999b5c8ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-pcmpstr.h
@@ -0,0 +1,447 @@
+#include <nmmintrin.h>
+#include <string.h>
+
+#define CFLAG 0x00000001
+#define ZFLAG 0x00000002
+#define SFLAG 0x00000004
+#define OFLAG 0x00000008
+#define AFLAG 0x00000010
+#define PFLAG 0x00000020
+
+#define PCMPSTR_EQ(X, Y, RES) \
+  {							\
+    int __size = (sizeof (*X) ^ 3) * 8;			\
+    int __i, __j;					\
+    for (__i = 0; __i < __size; __i++)			\
+      for (__j = 0; __j < __size; __j++)		\
+        RES[__j][__i] = (X[__i] == Y[__j]);		\
+  }
+
+#define PCMPSTR_RNG(X, Y, RES) \
+  {							\
+    int __size = (sizeof (*X) ^ 3) * 8;			\
+    int __i, __j;					\
+    for (__j = 0; __j < __size; __j++)			\
+      for (__i = 0; __i < __size - 1; __i += 2)		\
+	{						\
+	  RES[__j][__i] = (Y[__j] >= X[__i]);		\
+	  RES[__j][__i+1] = (Y[__j] <= X[__i + 1]);	\
+	}						\
+  }
+
+static void
+override_invalid (unsigned char res[16][16], int la, int lb,
+		  const int mode, int dim)
+{
+  int i, j;
+
+  for (j = 0; j < dim; j++)
+    for (i = 0; i < dim; i++)
+      if (i < la && j >= lb)
+	res[j][i] = 0;
+      else if (i >= la)
+	switch ((mode & 0x0C))
+	  {
+	  case _SIDD_CMP_EQUAL_ANY:
+	  case _SIDD_CMP_RANGES:
+	    res[j][i] = 0;
+	    break;
+	  case _SIDD_CMP_EQUAL_EACH:
+	    res[j][i] = (j >= lb) ? 1: 0;
+	    break;
+	  case _SIDD_CMP_EQUAL_ORDERED:
+	    res[j][i] = 1;
+	    break;
+          }
+}
+
+static void  
+calc_matrix (__m128i a, int la, __m128i b, int lb, const int mode,
+	     unsigned char res[16][16])
+{
+  union
+    {
+      __m128i x;
+      signed char sc[16];
+      unsigned char uc[16];
+      signed short ss[8];
+      unsigned short us[8];
+    } d, s;
+
+  d.x = a;
+  s.x = b;
+
+  switch ((mode & 3))
+    {
+    case _SIDD_UBYTE_OPS:
+      if ((mode & 0x0C) == _SIDD_CMP_RANGES)
+	{
+	  PCMPSTR_RNG (d.uc, s.uc, res);
+	}
+      else
+	{
+	  PCMPSTR_EQ (d.uc, s.uc, res);
+	}
+      break;
+    case _SIDD_UWORD_OPS:
+      if ((mode & 0x0C) == _SIDD_CMP_RANGES)
+	{
+	  PCMPSTR_RNG (d.us, s.us, res);
+	}
+      else
+	{
+	  PCMPSTR_EQ (d.us, s.us, res);
+	}
+      break;
+    case _SIDD_SBYTE_OPS:
+      if ((mode & 0x0C) == _SIDD_CMP_RANGES)
+	{
+	  PCMPSTR_RNG (d.sc, s.sc, res);
+	}
+      else
+	{
+	  PCMPSTR_EQ (d.sc, s.sc, res);
+	}
+      break;
+    case _SIDD_SWORD_OPS:
+      if ((mode & 0x0C) == _SIDD_CMP_RANGES)
+	{
+	  PCMPSTR_RNG (d.ss, s.ss, res);
+	}
+      else
+	{
+	  PCMPSTR_EQ (d.ss, s.ss, res);
+	}
+      break;
+    }
+
+  override_invalid (res, la, lb, mode, (mode & 1) == 0 ? 16 : 8);
+}
+
+static int 
+calc_res (__m128i a, int la, __m128i b, int lb, const int mode)
+{
+  unsigned char mtx[16][16];
+  int i, j, k, dim, res = 0;
+
+  memset (mtx, 0, sizeof (mtx));
+
+  dim = (mode & 1) == 0 ? 16 : 8;
+
+  if (la < 0)
+    la = -la;
+
+  if (lb < 0)
+    lb = -lb;
+
+  if (la > dim)
+    la = dim;
+ 
+  if (lb > dim)
+    lb = dim;
+
+  calc_matrix (a, la, b, lb, mode, mtx);
+
+  switch ((mode & 0x0C))
+    {
+    case _SIDD_CMP_EQUAL_ANY:
+      for (i = 0; i < dim; i++)
+	for (j = 0; j < dim; j++)
+	  if (mtx[i][j])
+	    res |= (1 << i);
+      break;
+
+     case _SIDD_CMP_RANGES:
+      for (i = 0; i < dim; i += 2)
+	for(j = 0; j < dim; j++)
+	  if (mtx[j][i] && mtx[j][i+1])
+	    res |= (1 << j);
+      break;
+
+     case _SIDD_CMP_EQUAL_EACH:
+      for(i = 0; i < dim; i++)
+	if (mtx[i][i])
+	  res |= (1 << i);
+      break;
+
+     case _SIDD_CMP_EQUAL_ORDERED:
+      for(i = 0; i < dim; i++)
+	{
+	  unsigned char val = 1;
+
+	  for (j = 0, k = i; j < dim - i && k < dim; j++, k++)
+	    val &= mtx[k][j];
+	  
+	  if (val)
+	    res |= (1 << i);
+	  else
+	    res &= ~(1 << i);
+	}
+      break;
+    }
+
+  switch ((mode & 0x30))
+    {
+    case _SIDD_POSITIVE_POLARITY:
+    case _SIDD_MASKED_POSITIVE_POLARITY:
+      break;
+
+    case _SIDD_NEGATIVE_POLARITY:
+      res ^= -1;
+      break;
+
+    case _SIDD_MASKED_NEGATIVE_POLARITY:
+      for (i = 0; i < lb; i++)
+	if (res & (1 << i))
+	  res &= ~(1 << i);
+	else
+	  res |= (1 << i);
+      break;
+    }
+
+  return res & ((dim == 8) ? 0xFF : 0xFFFF);
+}
+
+static int
+cmp_flags (__m128i a, int la, __m128i b, int lb,
+	   int mode, int res2, int is_implicit)
+{
+  int i;
+  int flags = 0;
+  int is_bytes_mode = (mode & 1) == 0;
+  union
+    {
+      __m128i x;
+      unsigned char uc[16];
+      unsigned short us[8];
+    } d, s;
+
+  d.x = a;
+  s.x = b;
+
+  /* CF: reset if (RES2 == 0), set otherwise.  */
+  if (res2 != 0)
+    flags |= CFLAG;
+
+  if (is_implicit)
+    {
+      /* ZF: set if any byte/word of src xmm operand is null, reset
+	 otherwise.
+	 SF: set if any byte/word of dst xmm operand is null, reset
+	 otherwise.  */
+
+      if (is_bytes_mode)
+	{
+	  for (i = 0; i < 16; i++)
+	    {
+	      if (s.uc[i] == 0)
+		flags |= ZFLAG;
+	      if (d.uc[i] == 0)
+		flags |= SFLAG;
+            }
+	}
+      else
+	{
+	  for (i = 0; i < 8; i++)
+	    {
+	      if (s.us[i] == 0)
+		flags |= ZFLAG;
+	      if (d.us[i] == 0)
+		flags |= SFLAG;
+            }
+        }
+    }
+  else
+    {
+      /* ZF: set if abs value of EDX/RDX < 16 (8), reset otherwise.
+	 SF: set if abs value of EAX/RAX < 16 (8), reset otherwise.  */
+      int max_ind = is_bytes_mode ? 16 : 8;
+
+      if (la < 0)
+	la = -la;
+      if (lb < 0)
+	lb = -lb;
+
+      if (lb < max_ind)
+	flags |= ZFLAG;
+      if (la < max_ind)
+	flags |= SFLAG;
+    }
+
+  /* OF: equal to RES2[0].  */
+  if ((res2 & 0x1))
+    flags |= OFLAG;
+
+  /* AF: Reset.
+     PF: Reset.  */
+  return flags;
+}
+
+static int
+cmp_indexed (__m128i a, int la, __m128i b, int lb,
+	     const int mode, int *res2)
+{
+  int i, ndx;
+  int dim = (mode & 1) == 0 ? 16 : 8;
+  int r2;
+  
+  r2 = calc_res (a, la, b, lb, mode);
+
+  ndx = dim;
+  if ((mode & 0x40))
+    {
+      for (i = dim - 1; i >= 0; i--)
+	if (r2 & (1 << i))
+	  {
+	    ndx = i;
+	    break;
+	  }
+    }
+  else
+    {
+      for (i = 0; i < dim; i++)
+	if ((r2 & (1 << i)))
+	  {
+	    ndx = i;
+	    break;
+	  }
+    }
+
+   *res2 = r2;
+   return ndx;
+}
+
+static __m128i 
+cmp_masked (__m128i a, int la, __m128i b, int lb,
+	    const int mode, int *res2)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+    } ret;
+  int i;
+  int dim = (mode & 1) == 0 ? 16 : 8;
+  union
+    {
+      int i;
+      char c[4];
+      short s[2];
+    } r2;
+
+  r2.i = calc_res (a, la, b, lb, mode);
+
+  memset (&ret, 0, sizeof (ret));
+
+  if (mode & 0x40)
+    {
+      for (i = 0; i < dim; i++)
+	if (dim == 8)
+	  ret.s [i] = (r2.i & (1 << i)) ? -1 : 0;
+	else
+	  ret.c [i] = (r2.i & (1 << i)) ? -1 : 0;
+    }
+  else
+    {
+      if (dim == 16)
+	ret.s[0] = r2.s[0];
+      else
+	ret.c[0] = r2.c[0];
+    }
+
+   *res2 = r2.i;
+
+   return ret.x;
+}
+
+static int 
+calc_str_len (__m128i a, const int mode)
+{
+  union
+    {
+      __m128i x;
+      char c[16];
+      short s[8];
+    } s;
+  int i;
+  int dim  = (mode & 1) == 0 ? 16 : 8;
+
+  s.x = a;
+
+  if ((mode & 1))
+    {
+      for (i = 0; i < dim; i++)
+	if (s.s[i] == 0)
+	  break;
+    }
+  else
+    {
+      for (i = 0; i < dim; i++)
+       if (s.c[i] == 0)
+	 break;
+    }
+
+  return i;
+}
+
+static inline int
+cmp_ei (__m128i *a, int la, __m128i *b, int lb,
+	const int mode, int *flags)
+{
+  int res2;
+  int index = cmp_indexed (*a, la, *b, lb, mode, &res2);
+
+  if (flags != NULL)
+    *flags = cmp_flags (*a, la, *b, lb, mode, res2, 0);
+
+  return index;
+}
+
+static inline int
+cmp_ii (__m128i *a, __m128i *b, const int mode, int *flags)
+{
+  int la, lb;
+  int res2;
+  int index;
+
+  la = calc_str_len (*a, mode);
+  lb = calc_str_len (*b, mode);
+
+  index = cmp_indexed (*a, la, *b, lb, mode, &res2);
+
+  if (flags != NULL) 
+    *flags = cmp_flags (*a, la, *b, lb, mode, res2, 1);
+
+  return index;
+}
+
+static inline __m128i
+cmp_em (__m128i *a, int la, __m128i *b, int lb,
+	const int mode, int *flags )
+{
+  int res2;
+  __m128i mask = cmp_masked (*a, la, *b, lb, mode, &res2);
+
+  if (flags != NULL)
+    *flags = cmp_flags (*a, la, *b, lb, mode, res2, 0);
+
+  return mask;
+}
+
+static inline __m128i
+cmp_im (__m128i *a, __m128i *b, const int mode, int *flags)
+{
+  int la, lb;
+  int res2;
+  __m128i mask;
+
+  la = calc_str_len (*a, mode);
+  lb = calc_str_len (*b, mode);
+
+  mask = cmp_masked (*a, la, *b, lb, mode, &res2);
+  if (flags != NULL)
+    *flags = cmp_flags (*a, la, *b, lb, mode, res2, 1);
+
+  return mask;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h
new file mode 100644
index 000000000..ce06ba1b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcnt.h
@@ -0,0 +1,41 @@
+#include "sse4_2-check.h"
+
+#include <nmmintrin.h>
+
+#define NUM 1024
+
+static int
+compute_popcnt (TYPE v)
+{
+  int ret;
+  int i;
+
+ ret = 0;
+ for (i = 0; i < sizeof(v) * 8; i++)
+   if ((v & ((TYPE)1 << (TYPE) i)))
+     ret++;
+
+ return ret;
+}
+
+static void
+sse4_2_test (void)
+{
+  int i;
+  TYPE vals[NUM];
+  TYPE res;
+
+ for (i = 0; i < NUM; i++)
+   {
+     vals[i] = rand ();
+     if (sizeof (TYPE) > 4)
+       vals[i] |= (TYPE)rand() << (TYPE)(sizeof (TYPE) * 4);
+   }
+
+ for (i=0; i < NUM; i++)
+   { 
+     res = POPCNT (vals[i]);
+     if (res != compute_popcnt (vals[i]))
+       abort ();
+   }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c
new file mode 100644
index 000000000..30da548d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcntl.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define TYPE unsigned int
+#define POPCNT _mm_popcnt_u32
+
+#include "sse4_2-popcnt.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c
new file mode 100644
index 000000000..47cdf3562
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4_2-popcntq.c
@@ -0,0 +1,8 @@
+/* { dg-do run { target { ! { ia32 } } } } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O2 -msse4.2" } */
+
+#define TYPE unsigned long long
+#define POPCNT _mm_popcnt_u64
+
+#include "sse4_2-popcnt.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-check.h
new file mode 100644
index 000000000..d43b4b222
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-check.h
@@ -0,0 +1,28 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void sse4a_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  sse4a_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSE4a test only if host has SSE4a support.  */
+  if (ecx & bit_SSE4a)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-extract.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-extract.c
new file mode 100644
index 000000000..5fb190e44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-extract.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4a } */
+/* { dg-options "-O2 -msse4a" } */
+
+#include "sse4a-check.h"
+
+#include <ammintrin.h>
+
+typedef union
+{
+  long long i[2];
+  __m128i vec;
+} LI;
+
+static long long 
+sse4a_test_extrq (long long in)
+{
+  __m128i v1, v2;
+  long long index_length, pad;
+  LI v_out;
+  index_length = 0x0000000000000810LL; 
+  pad = 0x0;
+  v1 = _mm_set_epi64x (pad, in);
+  v2 = _mm_set_epi64x (pad, index_length); 
+  v_out.vec = _mm_extract_si64 (v1, v2);
+  return (v_out.i[0]); 
+}
+
+static long long 
+sse4a_test_extrqi (long long in)
+{
+  __m128i v1;
+  long long pad =0x0;
+  LI v_out;
+  v1 = _mm_set_epi64x (pad, in);
+  v_out.vec = _mm_extracti_si64 (v1, (unsigned int) 0x10,(unsigned int) 0x08);
+  return (v_out.i[0]);
+}
+
+static chk (long long i1, long long i2)
+{
+  int n_fails =0;
+  if (i1 != i2) 
+    n_fails +=1;
+  return n_fails;
+}
+
+long long vals_in[5] =
+  {
+    0x1234567887654321LL,
+    0x1456782093002490LL,
+    0x2340909123990390LL,
+    0x9595959599595999LL,
+    0x9099038798000029LL
+  };
+
+long long vals_out[5] =
+  {
+    0x0000000000006543LL,
+    0x0000000000000024LL,
+    0x0000000000009903LL,
+    0x0000000000005959LL,
+    0x0000000000000000LL
+  };
+
+static void
+sse4a_test (void)
+{
+  int i;
+  int fail = 0;
+  long long out;
+
+  for (i = 0; i < 5; i += 1)
+    {
+      out = sse4a_test_extrq (vals_in[i]);
+      fail += chk(out, vals_out[i]);
+
+      out = sse4a_test_extrqi (vals_in[i]);
+      fail += chk(out, vals_out[i]);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-insert.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-insert.c
new file mode 100644
index 000000000..c1bd1006d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-insert.c
@@ -0,0 +1,94 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4a } */
+/* { dg-options "-O2 -msse4a" } */
+
+#include "sse4a-check.h"
+
+#include <ammintrin.h>
+
+typedef union
+{
+  long long i[2];
+  __m128i vec;
+} LI;
+
+static long long
+sse4a_test_insert (long long in1, long long in2)
+{
+  __m128i v1,v2;
+  long long index_length, pad;
+  LI v_out;
+  index_length = 0x0000000000000810LL;
+  pad = 0x0;
+  v1 = _mm_set_epi64x (pad, in1);
+  v2 = _mm_set_epi64x (index_length, in2); 
+  v_out.vec = _mm_insert_si64 (v1, v2);
+  return (v_out.i[0]);
+}
+
+static long long
+sse4a_test_inserti (long long in1, long long in2)
+{
+  __m128i v1,v2;
+  long long pad = 0x0;
+  LI v_out;
+  v1 = _mm_set_epi64x (pad, in1);
+  v2 = _mm_set_epi64x (pad, in2); 
+  v_out.vec = _mm_inserti_si64 (v1, v2, (unsigned int) 0x10, (unsigned int) 0x08);
+  return (v_out.i[0]);  
+}
+
+static chk (long long i1, long long i2)
+{
+  int n_fails =0;
+  if (i1 != i2) 
+    n_fails +=1;
+  return n_fails;
+}
+
+long long vals_in1[5] =
+  {
+    0x1234567887654321LL,
+    0x1456782093002490LL,
+    0x2340909123990390LL,
+    0x9595959599595999LL,
+    0x9099038798000029LL
+  };
+
+long long vals_in2[5] =
+  {
+    0x9ABCDEF00FEDCBA9LL,
+    0x234567097289672ALL,
+    0x45476453097BD342LL,
+    0x23569012AE586FF0LL,
+    0x432567ABCDEF765DLL
+  };
+
+long long vals_out[5] =
+  {
+    0x1234567887CBA921LL,
+    0x1456782093672A90LL,
+    0x2340909123D34290LL,
+    0x95959595996FF099LL,
+    0x9099038798765D29LL
+  };
+
+static void
+sse4a_test (void)
+{
+  int i;
+  int fail = 0;
+  long long out;
+
+  for (i = 0; i < 5; i += 1)
+    {
+      out = sse4a_test_insert (vals_in1[i], vals_in2[i]);
+      fail += chk(out, vals_out[i]);
+
+      out = sse4a_test_inserti (vals_in1[i], vals_in2[i]);
+      fail += chk(out, vals_out[i]);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-montsd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-montsd.c
new file mode 100644
index 000000000..1cc067db6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-montsd.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4a } */
+/* { dg-options "-O2 -msse4a" } */
+
+#include "sse4a-check.h"
+
+#include <ammintrin.h>
+
+static void 
+sse4a_test_movntsd (double *out, double *in)
+{
+  __m128d in_v2df = _mm_load_sd (in);
+  _mm_stream_sd (out, in_v2df);
+}
+
+static int 
+chk_sd (double *v1, double *v2)
+{
+  int n_fails = 0;
+  if (v1[0] != v2[0])
+    n_fails += 1;
+  return n_fails;
+}
+
+double vals[10] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, 
+    -1.0, .345, -21.5, 9.32,  8.41
+  };
+
+static void
+sse4a_test (void)
+{
+  int i;
+  int fail = 0;
+  double *out;
+
+  out = (double *) malloc (sizeof (double));
+  for (i = 0; i < 10; i += 1)
+    {
+      sse4a_test_movntsd (out, &vals[i]);
+      
+      fail += chk_sd (out, &vals[i]);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-montss.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-montss.c
new file mode 100644
index 000000000..41e80e83d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sse4a-montss.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4a } */
+/* { dg-options "-O2 -msse4a" } */
+
+#include "sse4a-check.h"
+
+#include <ammintrin.h>
+
+static void 
+sse4a_test_movntss (float *out, float *in)
+{
+  __m128 in_v4sf = _mm_load_ss (in);
+  _mm_stream_ss (out, in_v4sf);
+}
+
+static int 
+chk_ss (float *v1, float *v2)
+{
+  int n_fails = 0;
+  if (v1[0] != v2[0])
+    n_fails += 1;
+  return n_fails;
+}
+
+float vals[10] =
+  {
+    100.0,  200.0, 300.0, 400.0, 5.0, 
+    -1.0, .345, -21.5, 9.32,  8.41
+  };
+
+static void
+sse4a_test (void)
+{
+  int i;
+  int fail = 0;
+  float *out;
+
+  out = (float *) malloc (sizeof (float));
+  for (i = 0; i < 10; i += 1)
+    {
+      sse4a_test_movntss (out, &vals[i]);
+      
+      fail += chk_ss (out, &vals[i]);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-1.c
new file mode 100644
index 000000000..4c72fa4d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-1.c
@@ -0,0 +1,31 @@
+/* Test argument passing with SSE and local functions
+   Written by Paolo Bonzini, 25 January 2005 */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-final { scan-assembler "movss" } } */
+/* { dg-final { scan-assembler "mulss" } } */
+/* { dg-final { scan-assembler-not "movsd" } } */
+/* { dg-final { scan-assembler-not "mulsd" } } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
+/* { dg-options "-O2 -march=i386 -msse -mno-sse2 -mfpmath=sse -fno-inline" } */
+
+static float xs (void)
+{
+  return 3.14159265;
+}
+
+float ys (float a)
+{
+  return xs () * a;
+}
+
+static double xd (void)
+{
+  return 3.1415926535;
+}
+
+double yd (double a)
+{
+  return xd () * a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-2.c
new file mode 100644
index 000000000..2549855cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-2.c
@@ -0,0 +1,31 @@
+/* Test argument passing with SSE2 and local functions
+   Written by Paolo Bonzini, 25 January 2005 */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-final { scan-assembler "movss" } } */
+/* { dg-final { scan-assembler "mulss" } } */
+/* { dg-final { scan-assembler "movsd" } } */
+/* { dg-final { scan-assembler "mulsd" } } */
+/* { dg-options "-O2 -msse2 -mfpmath=sse -fno-inline" } */
+
+static float xs (void)
+{
+  return 3.14159265;
+}
+
+float ys (float a)
+{
+  return xs () * a;
+}
+
+static double xd (void)
+{
+  return 3.1415926535;
+}
+
+double yd (double a)
+{
+  return xd () * a;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-3.c
new file mode 100644
index 000000000..b96b21179
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-3.c
@@ -0,0 +1,39 @@
+/* Execution test for argument passing with SSE and local functions
+   Written by Paolo Bonzini, 25 January 2005 */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -msse -mfpmath=sse" } */
+/* { dg-require-effective-target sse } */
+
+#include "sse-check.h"
+
+#include <assert.h>
+
+static float xs (void)
+{
+  return 3.14159265;
+}
+
+float ys (float a)
+{
+  return xs () * a;
+}
+
+static double xd (void)
+{
+  return 3.1415926535;
+}
+
+double yd (double a)
+{
+  return xd () * a;
+}
+
+static void
+sse_test (void)
+{
+  assert (ys (1) == xs ());
+  assert (ys (2) == xs () * 2);
+  assert (yd (1) == xd ());
+  assert (yd (2) == xd () * 2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-4.c
new file mode 100644
index 000000000..2d7407eae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefn-4.c
@@ -0,0 +1,39 @@
+/* Execution test for argument passing with SSE2 and local functions
+   Written by Paolo Bonzini, 25 January 2005 */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2 -mfpmath=sse" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+
+#include <assert.h>
+
+static float xs (void)
+{
+  return 3.14159265;
+}
+
+float ys (float a)
+{
+  return xs () * a;
+}
+
+static double xd (void)
+{
+  return 3.1415926535;
+}
+
+double yd (double a)
+{
+  return xd () * a;
+}
+
+static void
+sse2_test (void)
+{
+  assert (ys (1) == xs ());
+  assert (ys (2) == xs () * 2);
+  assert (yd (1) == xd ());
+  assert (yd (2) == xd () * 2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefp-1.c
new file mode 100644
index 000000000..621e362f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefp-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */
+/* { dg-final { scan-assembler "maxsd" } } */
+/* { dg-final { scan-assembler "minsd" } } */
+double x;
+t()
+{
+  x=x>5?x:5;
+}
+
+double x;
+q()
+{
+  x=x<5?x:5;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefp-2.c
new file mode 100644
index 000000000..a6caee398
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssefp-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */
+/* { dg-final { scan-assembler "maxsd" } } */
+/* { dg-final { scan-assembler "minsd" } } */
+double x;
+q()
+{
+  x=x<5?5:x;
+}
+
+double x;
+q1()
+{
+  x=x>5?5:x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-1.c
new file mode 100644
index 000000000..63bad7e47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse" } */
+/* { dg-require-effective-target ia32 } */
+
+float essef(float) __attribute__((sseregparm));
+double essed(double) __attribute__((sseregparm));
+float __attribute__((sseregparm, noinline)) ssef(float f) { return f; }
+double __attribute__((sseregparm, noinline)) ssed(double d) { return d; }
+extern double d;
+extern float f;
+void test(void)
+{
+  f = essef(f);
+  d = essed(d);
+  f = ssef(f);
+  d = ssed(d);
+}
+
+/* { dg-final { scan-assembler-not "fldl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-2.c
new file mode 100644
index 000000000..b5e521a11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-sse" } */
+/* { dg-require-effective-target ia32 } */
+
+float essef(float) __attribute__((sseregparm));
+double essed(double) __attribute__((sseregparm));
+float __attribute__((sseregparm, noinline)) ssef(float f) { return f; } /* { dg-error "SSE" } */
+double __attribute__((sseregparm, noinline)) ssed(double d) { return d; } /* { dg-error "SSE" } */
+extern double d;
+extern float f;
+void test(void)
+{
+  f = essef(f);
+  d = essed(d);
+  f = ssef(f);
+  d = ssed(d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-3.c
new file mode 100644
index 000000000..5c16f4354
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ia32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(double x);
+double __attribute__((sseregparm)) (*mysinfp)(double) = mysin;
+double bar(double x)
+{
+  return 1.0+mysinfp(x);
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-4.c
new file mode 100644
index 000000000..47d66e3ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ia32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(double x);
+double __attribute__((sseregparm)) (*mysinfp)(double) = mysin;
+double bar(double x)
+{
+  return mysinfp(x);
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-5.c
new file mode 100644
index 000000000..d0f4757b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ia32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(void);
+double __attribute__((sseregparm)) (*mysinfp)(void) = mysin;
+double bar(double x)
+{
+  return mysinfp();
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-6.c
new file mode 100644
index 000000000..a4a836386
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-6.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ia32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(double x);
+double bar(double x)
+{
+  return mysin(x);
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-7.c
new file mode 100644
index 000000000..54b2573cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-7.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-require-effective-target ia32 } */
+
+/* Make sure we know that mysinfp returns in %xmm0.  */
+
+double __attribute__((sseregparm)) mysin(void);
+double bar(double x)
+{
+  return mysin();
+}
+
+/* { dg-final { scan-assembler "fldl" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-8.c
new file mode 100644
index 000000000..a7068dfe0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sseregparm-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-sse" } */
+/* { dg-require-effective-target ia32 } */
+
+float essef(float) __attribute__((sseregparm));
+double essed(double) __attribute__((sseregparm));
+float __attribute__((sseregparm)) ssef(float f);
+double __attribute__((sseregparm)) ssed(double d);
+extern double d;
+extern float f;
+void test(void)
+{
+  f = essef(f); /* { dg-error "SSE" } */
+  d = essed(d); /* { dg-error "SSE" } */
+  f = ssef(f); /* { dg-error "SSE" } */
+  d = ssed(d); /* { dg-error "SSE" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-1.c
new file mode 100644
index 000000000..ef89059b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-1.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andpd\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "andnpd\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "xorpd\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "orpd\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler-not "movdqa" } } */
+/* { dg-final { scan-assembler "movapd\[^\\n\]*magic" } } */
+
+/* Verify that we generate proper instruction with memory operand.  */
+
+#include <xmmintrin.h>
+
+static __m128d magic_a, magic_b;
+
+__m128d
+t1(void)
+{
+return _mm_and_pd (magic_a,magic_b);
+}
+__m128d
+t2(void)
+{
+return _mm_andnot_pd (magic_a,magic_b);
+}
+__m128d
+t3(void)
+{
+return _mm_or_pd (magic_a,magic_b);
+}
+__m128d
+t4(void)
+{
+return _mm_xor_pd (magic_a,magic_b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-2.c
new file mode 100644
index 000000000..b68a63923
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-2.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andpd" } } */
+/* { dg-final { scan-assembler "andnpd" } } */
+/* { dg-final { scan-assembler "xorpd" } } */
+/* { dg-final { scan-assembler "orpd" } } */
+/* { dg-final { scan-assembler-not "movdqa" } } */
+
+/* Verify that we generate proper instruction without memory operand.  */
+
+#include <xmmintrin.h>
+__m128d
+t1(__m128d a, __m128d b)
+{
+a=_mm_sqrt_pd(a);
+b=_mm_sqrt_pd(b);
+return _mm_and_pd (a,b);
+}
+__m128d
+t2(__m128d a, __m128d b)
+{
+a=_mm_sqrt_pd(a);
+b=_mm_sqrt_pd(b);
+return _mm_andnot_pd (a,b);
+}
+__m128d
+t3(__m128d a, __m128d b)
+{
+a=_mm_sqrt_pd(a);
+b=_mm_sqrt_pd(b);
+return _mm_or_pd (a,b);
+}
+__m128d
+t4(__m128d a, __m128d b)
+{
+a=_mm_sqrt_pd(a);
+b=_mm_sqrt_pd(b);
+return _mm_xor_pd (a,b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-3.c
new file mode 100644
index 000000000..d6887d5cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andps\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "andnps\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "xorps\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "orps\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler-not "movdqa" } } */
+/* { dg-final { scan-assembler "movaps\[^\\n\]*magic" } } */
+
+/* Verify that we generate proper instruction with memory operand.  */
+
+#include <xmmintrin.h>
+
+static __m128 magic_a, magic_b;
+__m128
+t1(void)
+{
+return _mm_and_ps (magic_a,magic_b);
+}
+__m128
+t2(void)
+{
+return _mm_andnot_ps (magic_a,magic_b);
+}
+__m128
+t3(void)
+{
+return _mm_or_ps (magic_a,magic_b);
+}
+__m128
+t4(void)
+{
+return _mm_xor_ps (magic_a,magic_b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-4.c
new file mode 100644
index 000000000..9994b07f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-4.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andps" } } */
+/* { dg-final { scan-assembler "andnps" } } */
+/* { dg-final { scan-assembler "xorps" } } */
+/* { dg-final { scan-assembler "orps" } } */
+
+/* Verify that we generate proper instruction without memory operand.  */
+
+#include <xmmintrin.h>
+__m128
+t1(__m128 a, __m128 b)
+{
+a=_mm_sqrt_ps(a);
+b=_mm_sqrt_ps(b);
+return _mm_and_ps (a,b);
+}
+__m128
+t2(__m128 a, __m128 b)
+{
+a=_mm_sqrt_ps(a);
+b=_mm_sqrt_ps(b);
+return _mm_andnot_ps (a,b);
+}
+__m128
+t3(__m128 a, __m128 b)
+{
+a=_mm_sqrt_ps(a);
+b=_mm_sqrt_ps(b);
+return _mm_or_ps (a,b);
+}
+__m128
+t4(__m128 a, __m128 b)
+{
+a=_mm_sqrt_ps(a);
+b=_mm_sqrt_ps(b);
+return _mm_xor_ps (a,b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-5.c
new file mode 100644
index 000000000..75133e9fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssetype-5.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* This test checks for absolute memory operands.  */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "pand\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "pandn\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "pxor\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "por\[^\\n\]*magic" } } */
+/* { dg-final { scan-assembler "movdqa" } } */
+/* { dg-final { scan-assembler-not "movaps\[^\\n\]*magic" } } */
+
+/* Verify that we generate proper instruction with memory operand.  */
+
+#include <xmmintrin.h>
+static __m128i magic_a, magic_b;
+__m128i
+t1(void)
+{
+return _mm_and_si128 (magic_a,magic_b);
+}
+__m128i
+t2(void)
+{
+return _mm_andnot_si128 (magic_a,magic_b);
+}
+__m128i
+t3(void)
+{
+return _mm_or_si128 (magic_a,magic_b);
+}
+__m128i
+t4(void)
+{
+return _mm_xor_si128 (magic_a,magic_b);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-check.h
new file mode 100644
index 000000000..3ca79333c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-check.h
@@ -0,0 +1,28 @@
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "cpuid.h"
+
+static void ssse3_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  ssse3_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run SSSE3 test only if host has SSSE3 support.  */
+  if (ecx & bit_SSSE3)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
new file mode 100644
index 000000000..7caa1b6c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsb.c
@@ -0,0 +1,80 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pabsb (int *i1, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  *(__m64 *) r = _mm_abs_pi8 (t1);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pabsb128 (int *i1, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  *(__m128i *) r = _mm_abs_epi8 (t1);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *r)
+{
+  char *b1 = (char *) i1;
+  char *bout = (char *) r;
+  int i;
+
+  for (i = 0; i < 16; i++)
+    if (b1[i] < 0)
+      bout[i] = -b1[i];
+    else
+      bout[i] = b1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 4)
+    {
+      /* Manually compute the result */
+      compute_correct_result(&vals[i + 0], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pabsb (&vals[i + 0], &r[0]);
+      ssse3_test_pabsb (&vals[i + 2], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pabsb128 (&vals[i + 0], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c
new file mode 100644
index 000000000..3a73cf011
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsd.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pabsd (int *i1, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  *(__m64 *) r = _mm_abs_pi32 (t1);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pabsd128 (int *i1, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  *(__m128i *) r = _mm_abs_epi32 (t1);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    if (i1[i] < 0)
+      r[i] = -i1[i];
+    else
+      r[i] = i1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 4)
+    {
+      /* Manually compute the result */
+      compute_correct_result(&vals[i + 0], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pabsd (&vals[i + 0], &r[0]);
+      ssse3_test_pabsd (&vals[i + 2], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pabsd128 (&vals[i + 0], r);
+      fail += chk_128(ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c
new file mode 100644
index 000000000..67e4721b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pabsw.c
@@ -0,0 +1,81 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pabsw (int *i1, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  *(__m64 *) r = _mm_abs_pi16 (t1);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pabsw128 (int *i1, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  *(__m128i *) r = _mm_abs_epi16 (t1);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *r)
+{
+  short *s1 = (short *) i1;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    if (s1[i] < 0)
+      sout[i] = -s1[i];
+    else
+      sout[i] = s1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 4)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pabsw (&vals[i + 0], &r[0]);
+      ssse3_test_pabsw (&vals[i + 2], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pabsw128 (&vals[i + 0], r);
+      fail += chk_128 (ck, r);
+    }
+  
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-palignr.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-palignr.c
new file mode 100644
index 000000000..dbee9bee4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-palignr.c
@@ -0,0 +1,279 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+#include <string.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_palignr (int *i1, int *i2, unsigned int imm, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+
+  switch (imm)
+    {
+    case 0:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 0);
+      break;
+    case 1:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 1);
+      break;
+    case 2:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 2);
+      break;
+    case 3:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 3);
+      break;
+    case 4:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 4);
+      break;
+    case 5:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 5);
+      break;
+    case 6:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 6);
+      break;
+    case 7:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 7);
+      break;
+    case 8:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 8);
+      break;
+    case 9:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 9);
+      break;
+    case 10:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 10);
+      break;
+    case 11:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 11);
+      break;
+    case 12:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 12);
+      break;
+    case 13:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 13);
+      break;
+    case 14:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 14);
+      break;
+    case 15:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 15);
+      break;
+    default:
+      *(__m64 *) r = _mm_alignr_pi8 (t1, t2, 16);
+      break;
+    }
+
+   _mm_empty();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_palignr128 (int *i1, int *i2, unsigned int imm, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+
+  switch (imm)
+    {
+    case 0:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 0);
+      break;
+    case 1:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 1);
+      break;
+    case 2:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 2);
+      break;
+    case 3:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 3);
+      break;
+    case 4:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 4);
+      break;
+    case 5:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 5);
+      break;
+    case 6:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 6);
+      break;
+    case 7:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 7);
+      break;
+    case 8:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 8);
+      break;
+    case 9:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 9);
+      break;
+    case 10:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 10);
+      break;
+    case 11:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 11);
+      break;
+    case 12:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 12);
+      break;
+    case 13:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 13);
+      break;
+    case 14:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 14);
+      break;
+    case 15:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 15);
+      break;
+    case 16:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 16);
+      break;
+    case 17:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 17);
+      break;
+    case 18:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 18);
+      break;
+    case 19:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 19);
+      break;
+    case 20:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 20);
+      break;
+    case 21:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 21);
+      break;
+    case 22:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 22);
+      break;
+    case 23:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 23);
+      break;
+    case 24:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 24);
+      break;
+    case 25:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 25);
+      break;
+    case 26:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 26);
+      break;
+    case 27:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 27);
+      break;
+    case 28:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 28);
+      break;
+    case 29:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 29);
+      break;
+    case 30:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 30);
+      break;
+    case 31:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 31);
+      break;
+    default:
+      *(__m128i *) r = _mm_alignr_epi8 (t1, t2, 32);
+      break;
+    }
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result_128 (int *i1, int *i2, unsigned int imm, int *r)
+{
+  char buf [32];
+  char *bout = (char *) r;
+  int i;
+
+  memcpy (&buf[0], i2, 16);
+  memcpy (&buf[16], i1, 16);
+
+  for (i = 0; i < 16; i++)
+    if (imm >= 32 || imm + i >= 32)
+      bout[i] = 0;
+    else
+      bout[i] = buf[imm + i];
+}
+
+#ifndef __AVX__
+static void
+compute_correct_result_64 (int *i1, int *i2, unsigned int imm, int *r)
+{
+  char buf [16];
+  char *bout = (char *)r;
+  int i;
+
+  /* Handle the first half */
+  memcpy (&buf[0], i2, 8);
+  memcpy (&buf[8], i1, 8);
+
+  for (i = 0; i < 8; i++)
+    if (imm >= 16 || imm + i >= 16)
+      bout[i] = 0;
+    else
+      bout[i] = buf[imm + i];
+
+  /* Handle the second half */
+  memcpy (&buf[0], &i2[2], 8);
+  memcpy (&buf[8], &i1[2], 8);
+
+  for (i = 0; i < 8; i++)
+    if (imm >= 16 || imm + i >= 16)
+      bout[i + 8] = 0;
+    else
+      bout[i + 8] = buf[imm + i];
+}
+#endif
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  unsigned int imm;
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    for (imm = 0; imm < 100; imm++)
+      {
+#ifndef __AVX__
+	/* Manually compute the result */
+	compute_correct_result_64 (&vals[i + 0], &vals[i + 4], imm, ck);
+
+	/* Run the 64-bit tests */
+	ssse3_test_palignr (&vals[i + 0], &vals[i + 4], imm, &r[0]);
+	ssse3_test_palignr (&vals[i + 2], &vals[i + 6], imm, &r[2]);
+	fail += chk_128 (ck, r);
+#endif
+
+	/* Recompute the results for 128-bits */
+	compute_correct_result_128 (&vals[i + 0], &vals[i + 4], imm, ck);
+
+	/* Run the 128-bit tests */
+	ssse3_test_palignr128 (&vals[i + 0], &vals[i + 4], imm, r);
+	fail += chk_128 (ck, r);
+      }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c
new file mode 100644
index 000000000..bef781686
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddd.c
@@ -0,0 +1,81 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phaddd (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hadd_pi32 (t1, t2);
+  _mm_empty();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phaddd128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_hadd_epi32 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result(int *i1, int *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    r[i] = i1[2 * i] + i1[2 * i + 1];
+  for (i = 0; i < 2; i++)
+    r[i + 2] = i2[2 * i] + i2[2 * i + 1];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phaddd (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phaddd (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phaddd128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c
new file mode 100644
index 000000000..ff31fe5a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddsw.c
@@ -0,0 +1,95 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phaddsw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hadds_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phaddsw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+ *(__m128i *) r = _mm_hadds_epi16 (t1, t2);
+}
+
+static short
+signed_saturate_to_word (int x)
+{
+  if (x > (int) 0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short) x;
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    sout[i] = signed_saturate_to_word(s1[2 * i] + s1[2 * i + 1]);
+  for (i = 0; i < 4; i++)
+    sout[i + 4] = signed_saturate_to_word(s2[2 * i] + s2[2 * i + 1]);
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phaddsw (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phaddsw (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phaddsw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c
new file mode 100644
index 000000000..05c0afd4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phaddw.c
@@ -0,0 +1,84 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phaddw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hadd_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phaddw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_hadd_epi16 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result(int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    sout[i] = s1[2 * i] + s1[2 * i + 1];
+
+  for (i = 0; i < 4; i++)
+    sout[i + 4] = s2[2 * i] + s2[2 * i + 1];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phaddw (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phaddw (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phaddw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c
new file mode 100644
index 000000000..5884e5c12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubd.c
@@ -0,0 +1,80 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phsubd (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hsub_pi32(t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phsubd128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_hsub_epi32 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 2; i++)
+    r[i] = i1[2 * i] - i1[2 * i + 1];
+  for (i = 0; i < 2; i++)
+    r[i + 2] = i2[2 * i] - i2[2 * i + 1];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phsubd (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phsubd (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phsubd128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c
new file mode 100644
index 000000000..371c8d112
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubsw.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phsubsw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+
+  *(__m64 *) r = _mm_hsubs_pi16 (t1, t2);
+
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phsubsw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_hsubs_epi16 (t1, t2);
+}
+
+static short
+signed_saturate_to_word (int x)
+{
+  if (x > (int )0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short)x;
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    sout[i] = signed_saturate_to_word (s1[2 * i] - s1[2 * i + 1]);
+
+  for (i = 0; i < 4; i++)
+    sout[i + 4] = signed_saturate_to_word (s2[2 * i] - s2[2 * i + 1]);
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phsubsw (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phsubsw (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phsubsw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c
new file mode 100644
index 000000000..f3dbf9c98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-phsubw.c
@@ -0,0 +1,83 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_phsubw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_hsub_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_phsubw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+
+  *(__m128i *) r = _mm_hsub_epi16 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    sout[i] = s1[2 * i] - s1[2 * i + 1];
+  for (i = 0; i < 4; i++)
+    sout[i + 4] = s2[2 * i] - s2[2 * i + 1];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_phsubw (&vals[i + 0], &vals[i + 2], &r[0]);
+      ssse3_test_phsubw (&vals[i + 4], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_phsubw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c
new file mode 100644
index 000000000..00bfc844f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pmaddubsw.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pmaddubsw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_maddubs_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pmaddubsw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_maddubs_epi16 (t1, t2);
+}
+
+static short
+signed_saturate_to_word(int x)
+{
+  if (x > (int) 0x7fff)
+    return 0x7fff;
+
+  if (x < (int) 0xffff8000)
+    return 0x8000;
+
+  return (short) x;
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  unsigned char *ub1 = (unsigned char *) i1;
+  char *sb2 = (char *) i2;
+  short *sout = (short *) r;
+  int t0;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    { 
+      t0 = ((int) ub1[2 * i] * (int) sb2[2 * i] +
+	    (int) ub1[2 * i + 1] * (int) sb2[2 * i + 1]);
+      sout[i] = signed_saturate_to_word (t0);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pmaddubsw (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_pmaddubsw (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pmaddubsw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c
new file mode 100644
index 000000000..24570b3bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pmulhrsw.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pmulhrsw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_mulhrs_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pmulhrsw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_mulhrs_epi16 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int t0;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    {
+      t0 = (((int) s1[i] * (int) s2[i]) >> 14) + 1;
+      sout[i] = (short) (t0 >> 1);
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_pmulhrsw (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_pmulhrsw (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_pmulhrsw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c
new file mode 100644
index 000000000..b995456b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-pshufb.c
@@ -0,0 +1,114 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_pshufb (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *)r = _mm_shuffle_pi8 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_pshufb128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *)r = _mm_shuffle_epi8 (t1, t2);
+}
+
+#ifndef __AVX__
+/* Routine to manually compute the results */
+static void
+compute_correct_result_64 (int *i1, int *i2, int *r)
+{
+  char *b1 = (char *) i1;
+  char *b2 = (char *) i2;
+  char *bout = (char *) r;
+  int i;
+  char select;
+
+  for (i = 0; i < 16; i++)
+    {
+      select = b2[i];
+      if (select & 0x80)
+	bout[i] = 0;
+      else if (i < 8)
+	bout[i] = b1[select & 0x7];
+      else
+	bout[i] = b1[8 + (select & 0x7)];
+    }
+}
+#endif
+
+static void
+compute_correct_result_128 (int *i1, int *i2, int *r)
+{
+  char *b1 = (char *) i1;
+  char *b2 = (char *) i2;
+  char *bout = (char *) r;
+  int i;
+  char select;
+
+  for (i = 0; i < 16; i++)
+    {
+      select = b2[i];
+      if (select & 0x80)
+	bout[i] = 0;
+      else
+	bout[i] = b1[select & 0xf];
+    }
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+#ifndef __AVX__
+      /* Manually compute the result */
+      compute_correct_result_64 (&vals[i + 0], &vals[i + 4], ck);
+
+      /* Run the 64-bit tests */
+      ssse3_test_pshufb (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_pshufb (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Recompute the result for 128-bits */
+      compute_correct_result_128 (&vals[i + 0], &vals[i + 4], ck);
+
+      /* Run the 128-bit tests */
+      ssse3_test_pshufb128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignb.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignb.c
new file mode 100644
index 000000000..7462929aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignb.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_psignb (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_sign_pi8 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_psignb128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *) r = _mm_sign_epi8 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  char *b1 = (char *) i1;
+  char *b2 = (char *) i2;
+  char *bout = (char *) r;
+  int i;
+
+  for (i = 0; i < 16; i++)
+    if (b2[i] < 0)
+      bout[i] = -b1[i];
+    else if (b2[i] == 0)
+      bout[i] = 0;
+    else
+      bout[i] = b1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_psignb (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_psignb (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_psignb128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignd.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignd.c
new file mode 100644
index 000000000..eca0489f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignd.c
@@ -0,0 +1,82 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_psignd (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_sign_pi32 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_psignd128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+  *(__m128i *)r = _mm_sign_epi32 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    if (i2[i] < 0)
+      r[i] = -i1[i];
+    else if (i2[i] == 0)
+      r[i] = 0;
+    else
+      r[i] = i1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_psignd (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_psignd (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_psignd128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignw.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignw.c
new file mode 100644
index 000000000..00a506fd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-psignw.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O2 -fno-strict-aliasing -mssse3" } */
+
+#ifndef CHECK_H
+#define CHECK_H "ssse3-check.h"
+#endif
+
+#ifndef TEST
+#define TEST ssse3_test
+#endif
+
+#include CHECK_H
+#include "ssse3-vals.h"
+
+#include <tmmintrin.h>
+
+#ifndef __AVX__
+/* Test the 64-bit form */
+static void
+ssse3_test_psignw (int *i1, int *i2, int *r)
+{
+  __m64 t1 = *(__m64 *) i1;
+  __m64 t2 = *(__m64 *) i2;
+  *(__m64 *) r = _mm_sign_pi16 (t1, t2);
+  _mm_empty ();
+}
+#endif
+
+/* Test the 128-bit form */
+static void
+ssse3_test_psignw128 (int *i1, int *i2, int *r)
+{
+  /* Assumes incoming pointers are 16-byte aligned */
+  __m128i t1 = *(__m128i *) i1;
+  __m128i t2 = *(__m128i *) i2;
+ *(__m128i *) r = _mm_sign_epi16 (t1, t2);
+}
+
+/* Routine to manually compute the results */
+static void
+compute_correct_result (int *i1, int *i2, int *r)
+{
+  short *s1 = (short *) i1;
+  short *s2 = (short *) i2;
+  short *sout = (short *) r;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    if (s2[i] < 0)
+      sout[i] = -s1[i];
+    else if (s2[i] == 0)
+      sout[i] = 0;
+    else
+      sout[i] = s1[i];
+}
+
+static void
+TEST (void)
+{
+  int i;
+  int r [4] __attribute__ ((aligned(16)));
+  int ck [4];
+  int fail = 0;
+
+  for (i = 0; i < 256; i += 8)
+    {
+      /* Manually compute the result */
+      compute_correct_result (&vals[i + 0], &vals[i + 4], ck);
+
+#ifndef __AVX__
+      /* Run the 64-bit tests */
+      ssse3_test_psignw (&vals[i + 0], &vals[i + 4], &r[0]);
+      ssse3_test_psignw (&vals[i + 2], &vals[i + 6], &r[2]);
+      fail += chk_128 (ck, r);
+#endif
+
+      /* Run the 128-bit tests */
+      ssse3_test_psignw128 (&vals[i + 0], &vals[i + 4], r);
+      fail += chk_128 (ck, r);
+    }
+
+  if (fail != 0)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-vals.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-vals.h
new file mode 100644
index 000000000..048ca911c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/ssse3-vals.h
@@ -0,0 +1,60 @@
+/* Routine to check correctness of the results */
+static int
+chk_128 (int *v1, int *v2)
+{
+  int i;
+  int n_fails = 0;
+
+  for (i = 0; i < 4; i++)
+    if (v1[i] != v2[i])
+      n_fails += 1;
+
+  return n_fails;
+}
+
+static int vals [256] __attribute__ ((aligned(16))) =
+{
+  0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x5be800ee, 0x4f2d7b15,
+  0x409d9291, 0xdd95f27f, 0x423986e3, 0x21a4d2cd, 0xa7056d84, 0x4f4e5a3b,
+  0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+  0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+  0x73ef0244, 0xcd836329, 0x847f634f, 0xa7e3abcf, 0xb4c14764, 0x1ef42c06,
+  0x504f29ac, 0x4ae7ca73, 0xaddde3c9, 0xf63ded2e, 0xa5d3553d, 0xa52ae05f,
+  0x6fd3c83a, 0x7dc2b300, 0x76b05de7, 0xea8ebae5, 0x549568dd, 0x172f0358,
+  0x917eadf0, 0x796fb0a7, 0xb39381af, 0xd0591d61, 0x731d2f17, 0xbc4b6f5d,
+  0x8ec664c2, 0x3c199c19, 0x9c81db12, 0x6d85913b, 0x486107a9, 0xab6f4b26,
+  0x5630d37c, 0x20836e85, 0x40d4e746, 0xdfbaba36, 0xbeacaa69, 0xb3c84083,
+  0x8a688eb4, 0x08cde481, 0x66e7a190, 0x74ee1639, 0xb3942a19, 0xe0c40471,
+  0x9b789489, 0x9751207a, 0x543a1524, 0x41da7ad6, 0x614bb563, 0xf86f57b1,
+  0x69e62199, 0x2150cb12, 0x9ed74062, 0x429471f4, 0xad28502b, 0xf2e2d4d5,
+  0x45b6ce09, 0xaaa5e649, 0xb46da484, 0x0a637515, 0xae7a3212, 0x5afc784c,
+  0x776cfbbe, 0x9c542bb2, 0x64193aa8, 0x16e8a655, 0x4e3d2f92, 0xe05d7b72,
+  0x89854ebc, 0x8c318814, 0xb81e76e0, 0x3f2625f5, 0x61b44852, 0x5209d7ad,
+  0x842fe317, 0xd3cfcca1, 0x8d287cc7, 0x80f0c9a8, 0x4215f4e5, 0x563993d6,
+  0x5d627433, 0xc4449e35, 0x5b4fe009, 0x3ef92286, 0xacbc8927, 0x549ab870,
+  0x9ac5b959, 0xed8f1c91, 0x7ecf02cd, 0x989c0e8b, 0xa31d6918, 0x1dc2bcc1,
+  0x99d3f3cc, 0x6857acc8, 0x45d7324a, 0xaebdf2e6, 0x7af2f2ae, 0x09716f73,
+  0x7816e694, 0xc65493c0, 0x9f7e87bc, 0xaa96cd40, 0xbfb5bfc6, 0x01a2cce7,
+  0x5f1d8c46, 0x45303efb, 0xb24607c3, 0xef2009a7, 0xba873753, 0xbefb14bc,
+  0x74e53cd3, 0x70124708, 0x6eb4bdbd, 0xf3ba5e43, 0x4c94085f, 0x0c03e7e0,
+  0x9a084931, 0x62735424, 0xaeee77c5, 0xdb34f90f, 0x6860cbdd, 0xaf77cf9f,
+  0x95b28158, 0x23bd70d7, 0x9fbc3d88, 0x742e659e, 0x53bcfb48, 0xb8a63f6c,
+  0x4dcf3373, 0x2b168627, 0x4fe20745, 0xd0af5e94, 0x22514e6a, 0xb8ef25c2,
+  0x89ec781a, 0x13d9002b, 0x6d724500, 0x7fdbf63f, 0xb0e9ced5, 0xf919e0f3,
+  0x00fef203, 0x8905d47a, 0x434e7517, 0x4aef8e2c, 0x689f51e8, 0xe513b7c3,
+  0x72bbc5d2, 0x3a222f74, 0x05c3a0f9, 0xd5489d82, 0xb41fbe83, 0xec5d305f,
+  0x5ea02b0b, 0xb176065b, 0xa8eb404e, 0x80349117, 0x210fd49e, 0x43898d0e,
+  0x6c151b9c, 0x8742df18, 0x7b64de73, 0x1dbf52b2, 0x55c9cb19, 0xeb841f10,
+  0x10b8ae76, 0x0764ecb6, 0xb7479018, 0x2672cb3f, 0x7ac9ac90, 0x4be5332c,
+  0x8f1a0615, 0x4efb7a77, 0x16551a85, 0xdb2c3d66, 0x49179c07, 0x5dc4657e,
+  0x5e76907e, 0xd7486a9c, 0x445204a4, 0x65cdc426, 0x33f86ded, 0xcba95dda,
+  0x83351f16, 0xfedefad9, 0x639b620f, 0x86896a64, 0xba4099ba, 0x965f4a21,
+  0x1247154f, 0x25604c42, 0x5862d692, 0xb1e9149e, 0x612516a5, 0x02c49bf8,
+  0x631212bf, 0x9f69f54e, 0x168b63b0, 0x310a25ba, 0xa42a59cd, 0x084f0af9,
+  0x44a06cec, 0x5c0cda40, 0xb932d721, 0x7c42bb0d, 0x213cd3f0, 0xedc7f5a4,
+  0x7fb85859, 0x6b3da5ea, 0x61cd591e, 0xe8e9aa08, 0x4361fc34, 0x53d40d2a,
+  0x0511ad1b, 0xf996b44c, 0xb5ead756, 0xc022138d, 0x6172adf1, 0xa4a0a3b4,
+  0x8c2977b8, 0xa8e482ed, 0x04fcdd6b, 0x3f7b85d4, 0x4fca1e46, 0xa392ddca,
+  0x569fc791, 0x346a706c, 0x543bf3eb, 0x895b3cde, 0x2146bb80, 0x26b3c168,
+  0x929998db, 0x1ea472c9, 0x7207b36b, 0x6a8f10d4 
+};
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c
new file mode 100644
index 000000000..4a93e333c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-prot-kernel.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2 -fstack-protector-all -mcmodel=kernel" } */
+
+void test1 (int x)
+{
+  char p[40];
+  int i;
+  for (i=0; i<40; i++)
+	p[i] = x;
+}
+
+/* { dg-final { scan-assembler-not "%fs" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-realign.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-realign.c
new file mode 100644
index 000000000..a45441845
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-realign.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mstackrealign -O2" } */
+
+extern void abort (void);
+
+__attribute__((noinline)) static void foo (int i1, int i2, int i3)
+{
+  if (i3 != 3)
+    abort ();
+}
+
+int main (int argc, char **argv)
+{
+  foo (1, 2, 3);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-usage-realign.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-usage-realign.c
new file mode 100644
index 000000000..c899606d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stack-usage-realign.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-skip-if "no stack realignment" { *-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-fstack-usage -msse2 -mforce-drap" } */
+
+typedef int __attribute__((vector_size(16))) vec;
+
+vec foo (vec v)
+{
+  return v;
+}
+
+int main (void)
+{
+  vec V;
+  V = foo (V);
+  return 0;
+}
+
+/* { dg-final { scan-stack-usage "main\t48\tdynamic,bounded" } } */
+/* { dg-final { cleanup-stack-usage } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c
new file mode 100644
index 000000000..dfe3968f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/asm-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mpreferred-stack-boundary=2" } */
+
+/* This case is to detect a compile time regression introduced in stack
+   branch development. */
+f(){asm("%0"::"r"(1.5F));}g(){asm("%0"::"r"(1.5));}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c
new file mode 100644
index 000000000..161d2292d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/longlong-1.c
@@ -0,0 +1,15 @@
+/* PR target/39137 */
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=2" } */
+/* Make sure dynamic stack realignment isn't performed just because there
+   are long long variables.  */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-8,\[^\\n\]*sp" } } */
+
+void fn (void *);
+
+void f1 (void)
+{
+  unsigned long long a;
+  fn (&a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c
new file mode 100644
index 000000000..6ea83f98f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/longlong-2.c
@@ -0,0 +1,33 @@
+/* { dg-do compile  { target { ! *-*-darwin* } } } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-O2 -mpreferred-stack-boundary=2" } */
+/* { dg-final { scan-assembler-times "and\[lq\]?\[^\\n\]*-8,\[^\\n\]*sp" 2 } } */ 
+/* { dg-final { scan-assembler-times "and\[lq\]?\[^\\n\]*-16,\[^\\n\]*sp" 2 } } */ 
+
+void fn (void *);
+
+void f2 (void)
+{
+  unsigned long long a __attribute__((aligned (8)));
+  fn (&a);
+}
+
+void f3 (void)
+{
+  typedef unsigned long long L __attribute__((aligned (8)));
+  L a;
+  fn (&a);
+}
+
+void f4 (void)
+{
+  unsigned long long a __attribute__((aligned (16)));
+  fn (&a);
+}
+
+void f5 (void)
+{
+  typedef unsigned long long L __attribute__((aligned (16)));
+  L a;
+  fn (&a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/pr39146.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/pr39146.c
new file mode 100644
index 000000000..9ae5f0345
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/pr39146.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O2 -mavx" } */
+
+typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__));
+
+
+__m256i
+bar (__m256i x)
+{
+  return x;
+}
+
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-32,\[^\\n\]*sp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-1.c
new file mode 100644
index 000000000..c9fcc1213
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mpreferred-stack-boundary=2" } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+
+double
+foo (void)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-2.c
new file mode 100644
index 000000000..d393913ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mpreferred-stack-boundary=2" } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+void baz (void);
+                       
+double foo (void)
+{
+  baz ();
+  return;
+}
+
+double bar (void)
+{
+  baz ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-3.c
new file mode 100644
index 000000000..e32547e01
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { ia32 && dfp } } { "*" } { "" } } */
+/* { dg-options "-msse -std=gnu99 -mpreferred-stack-boundary=2" } */
+/* { dg-require-effective-target sse } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+_Decimal128 test (void)
+{
+  return 1234123412341234.123412341234dl;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-4.c
new file mode 100644
index 000000000..a1e35dcc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mpreferred-stack-boundary=4" } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+typedef int aligned __attribute__((aligned(64)));
+
+aligned
+foo (void) { }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-5.c
new file mode 100644
index 000000000..208bc0d8a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mpreferred-stack-boundary=4" } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+struct bar
+{
+  int x;
+} __attribute__((aligned(64)));
+
+
+struct bar
+foo (void) { }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-6.c
new file mode 100644
index 000000000..b1aa1eac8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/return-6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mpreferred-stack-boundary=4" } */
+/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-64,\[^\\n\]*sp" } } */
+
+/* This compile only test is to detect an assertion failure in stack branch
+   development.  */
+struct bar
+{
+  int x __attribute__((aligned(64)));
+};
+
+
+struct bar
+foo (void) { }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp
new file mode 100644
index 000000000..0e0d55bf7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/stackalign/stackalign.exp
@@ -0,0 +1,46 @@
+# Copyright (C) 2008-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# Exit immediately if this isn't a x86 target.
+if { ![istarget i?86*-*-*] && ![istarget x86_64-*-*] } then {
+  return
+}
+
+load_lib gcc-dg.exp
+
+# Only run on targets which support automatic stack alignment.
+if { ![check_effective_target_automatic_stack_alignment] } then {
+    return
+}
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS "-w"
+}
+
+# Initialize `dg'.
+dg-init
+
+set additional_flags "-mstackrealign"
+
+dg-runtest [lsort [glob $srcdir/$subdir/*.c]] $additional_flags $DEFAULT_CFLAGS
+
+set additional_flags "-mno-stackrealign"
+
+dg-runtest [lsort [glob $srcdir/$subdir/*.c]] $additional_flags $DEFAULT_CFLAGS
+
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/strinline.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/strinline.c
new file mode 100644
index 000000000..2fe671416
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/strinline.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -fPIC" } */
+typedef unsigned int size_t;
+ char *
+__mempcpy_by2 (char *__dest, __const char *__src, size_t __srclen)
+{
+  register char *__tmp = __dest;
+  register unsigned long int __d0, __d1;
+  __asm__ __volatile__
+    ("shrl      $1,%3\n\t"
+     "jz        2f\n"
+     "1:\n\t"
+     "movl      (%2),%0\n\t"
+     "leal      4(%2),%2\n\t"
+     "movl      %0,(%1)\n\t"
+     "leal      4(%1),%1\n\t"
+     "decl      %3\n\t"
+     "jnz       1b\n"
+     "2:\n\t"
+     "movw      (%2),%w0\n\t"
+     "movw      %w0,(%1)"
+     : "=&q" (__d0), "=r" (__tmp), "=&r" (__src), "=&r" (__d1),
+       "=m" ( *(struct { __extension__ char __x[__srclen]; } *)__dest)
+     : "1" (__tmp), "2" (__src), "3" (__srclen / 2),
+       "m" ( *(struct { __extension__ char __x[__srclen]; } *)__src)
+     : "cc");
+  return __tmp + 2;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/sw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/sw-1.c
new file mode 100644
index 000000000..d07ac9cf5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/sw-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=generic -fshrink-wrap -fdump-rtl-pro_and_epilogue" } */
+/* { dg-skip-if "No shrink-wrapping preformed" { x86_64-*-mingw* } { "*" } { "" } } */
+
+#include <string.h>
+
+int c;
+int x[2000];
+__attribute__((regparm(1))) void foo (int a, int b)
+ {
+   int t[200];
+   if (a == 0 || c == 0)
+     return;
+   memcpy (t, x + b, sizeof t);
+   c = t[a];
+ }
+
+/* { dg-final { scan-rtl-dump "Performing shrink-wrapping" "pro_and_epilogue" } } */
+/* { dg-final { cleanup-rtl-dump "pro_and_epilogue" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/tailcall-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/tailcall-1.c
new file mode 100644
index 000000000..9aae9d45e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/tailcall-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2" } */
+
+typedef unsigned int Cardinal;
+typedef char *String;
+typedef struct _WidgetRec *Widget;
+
+typedef union _XEvent {
+        int type;
+ long pad[24];
+} XEvent;
+
+
+extern int SendMousePosition (Widget w, XEvent* event);
+
+
+void
+HandleIgnore(Widget w,
+      XEvent * event,
+      String * params ,
+      Cardinal *param_count )
+{
+
+    (void) SendMousePosition(w, event);
+}
+
+/* { dg-final { scan-assembler "jmp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/tbm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/tbm-1.c
new file mode 100644
index 000000000..2c16d74db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/tbm-1.c
@@ -0,0 +1,74 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtbm" } */
+/* { dg-final { scan-assembler "bextr\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "blcfill\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "blci\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "blcic\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "blcmsk\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "blcs\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "blsfill\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "blsic\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "t1mskc\[^\\n]*(%|)eax" } } */
+/* { dg-final { scan-assembler "tzmsk\[^\\n]*(%|)eax" } } */
+
+#include <x86intrin.h>
+
+unsigned int
+func_bextri32 (unsigned int X)
+{
+  return __bextri_u32 (X, 0x101);
+}
+
+unsigned int
+func_blcfill32 (unsigned int X)
+{
+  return __blcfill_u32 (X);
+}
+
+unsigned int
+func_blci32 (unsigned int X)
+{
+  return __blci_u32 (X);
+}
+
+unsigned int
+func_blcic32 (unsigned int X)
+{
+  return __blcic_u32 (X);
+}
+
+unsigned int
+func_blcmsk32 (unsigned int X)
+{
+  return __blcmsk_u32 (X);
+}
+
+unsigned int
+func_blcs32 (unsigned int X)
+{
+  return __blcs_u32 (X);
+}
+
+unsigned int
+func_blsfill32 (unsigned int X)
+{
+  return __blsfill_u32 (X);
+}
+
+unsigned int
+func_blsic32 (unsigned int X)
+{
+  return __blsic_u32 (X);
+}
+
+unsigned int
+func_t1mskc32 (unsigned int X)
+{
+  return __t1mskc_u32 (X);
+}
+
+unsigned int
+func_tzmsk32 (unsigned int X)
+{
+  return __tzmsk_u32 (X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/tbm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/tbm-2.c
new file mode 100644
index 000000000..fa3870a5e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/tbm-2.c
@@ -0,0 +1,74 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mtbm" } */
+/* { dg-final { scan-assembler "bextr\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "blcfill\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "blci\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "blcic\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "blcmsk\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "blcs\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "blsfill\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "blsic\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "t1mskc\[^\\n]*(%|)rax" } } */
+/* { dg-final { scan-assembler "tzmsk\[^\\n]*(%|)rax" } } */
+
+#include <x86intrin.h>
+
+unsigned long long
+func_bextri64 (unsigned long long X)
+{
+  return __bextri_u64 (X, 0x101);
+}
+
+unsigned long long
+func_blcfill64 (unsigned long long X)
+{
+  return __blcfill_u64 (X);
+}
+
+unsigned long long
+func_blci64 (unsigned long long X)
+{
+  return __blci_u64 (X);
+}
+
+unsigned long long
+func_blcic64 (unsigned long long X)
+{
+  return __blcic_u64 (X);
+}
+
+unsigned long long
+func_blcmsk64 (unsigned long long X)
+{
+  return __blcmsk_u64 (X);
+}
+
+unsigned long long
+func_blcs64 (unsigned long long X)
+{
+  return __blcs_u64 (X);
+}
+
+unsigned long long
+func_blsfill64 (unsigned long long X)
+{
+  return __blsfill_u64 (X);
+}
+
+unsigned long long
+func_blsic64 (unsigned long long X)
+{
+  return __blsic_u64 (X);
+}
+
+unsigned long long
+func_t1mskc64 (unsigned long long X)
+{
+  return __t1mskc_u64 (X);
+}
+
+unsigned long long
+func_tzmsk64 (unsigned long long X)
+{
+  return __tzmsk_u64 (X);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-1.c
new file mode 100644
index 000000000..57276192e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-1.c
@@ -0,0 +1,94 @@
+/* PR target/49411 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -mf16c -maes -mpclmul" } */
+
+#include <x86intrin.h>
+
+__m128i i1, i2, i3, i4;
+__m128 a1, a2, a3, a4;
+__m128d d1, d2, d3, d4;
+__m256i l1, l2, l3, l4;
+__m256 b1, b2, b3, b4;
+__m256d e1, e2, e3, e4;
+__m64 m1, m2, m3, m4;
+int k1, k2, k3, k4;
+float f1, f2, f3, f4;
+
+void
+test8bit (void)
+{
+  i1 = _mm_cmpistrm (i2, i3, 256);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistri (i2, i3, 256);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistra (i2, i3, 256);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrc (i2, i3, 256);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistro (i2, i3, 256);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrs (i2, i3, 256);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrz (i2, i3, 256);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  i1 = _mm_cmpestrm (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestri (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestra (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrc (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestro (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrs (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrz (i2, k2, i3, k3, 256);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  b1 = _mm256_blend_ps (b2, b3, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  k1 = _cvtss_sh (f1, 256);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm256_cvtps_ph (b2, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_dp_ps (b2, b3, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  e1 = _mm256_permute2f128_pd (e2, e3, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_permute2f128_ps (b2, b3, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_permute2f128_si256 (l2, l3, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_permute_ps (b2, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_aeskeygenassist_si128 (i2, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_blend_epi16 (i2, i3, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_clmulepi64_si128 (i2, i3, 256);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_cvtps_ph (a1, 256);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  d1 = _mm_dp_pd (d2, d3, 256);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_dp_ps (a2, a3, 256);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_insert_ps (a2, a3, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_mpsadbw_epu8 (i2, i3, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_permute_ps (a2, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_slli_si128 (i2, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_srli_si128 (i2, 256);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+}
+
+void
+test5bit (void)
+{
+  d1 = _mm_cmp_sd (d2, d3, 32);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  a1 = _mm_cmp_ss (a2, a3, 32);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  d1 = _mm_cmp_pd (d2, d3, 32);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  a1 = _mm_cmp_ps (a2, a3, 32);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  e1 = _mm256_cmp_pd (e2, e3, 32);	  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  b1 = _mm256_cmp_ps (b2, b3, 32);	  /* { dg-error "the last argument must be a 5-bit immediate" } */
+}
+
+void
+test4bit (void)
+{
+  d1 = _mm_round_pd (d2, 16);		  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  d1 = _mm_round_sd (d2, d3, 16);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_round_ps (a2, 16);		  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_round_ss (a2, a2, 16);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_blend_ps (a2, a3, 16);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  e1 = _mm256_blend_pd (e2, e3, 16);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  e1 = _mm256_round_pd (e2, 16);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  b1 = _mm256_round_ps (b2, 16);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+}
+
+void
+test2bit (void)
+{
+  d1 = _mm_blend_pd (d2, d3, 4);	  /* { dg-error "the last argument must be a 2-bit immediate" } */
+}
+
+void
+test1bit (void)
+{
+  d1 = _mm256_extractf128_pd (e2, 2);	  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  a1 = _mm256_extractf128_ps (b2, 2);	  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  i1 = _mm256_extractf128_si256 (l2, 2);  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  e1 = _mm256_insertf128_pd (e2, d1, 2);  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  b1 = _mm256_insertf128_ps (b2, a1, 2);  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  l1 = _mm256_insertf128_si256 (l2, i1, 2);/* { dg-error "the last argument must be a 1-bit immediate" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-10.c
new file mode 100644
index 000000000..d744e1c08
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-10.c
@@ -0,0 +1,192 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx512f" } */
+
+#include <x86intrin.h>
+
+__m512i m512i;
+__m512d m512d;
+__m512  m512;
+__m256i m256i;
+__m256d m256d;
+__m256  m256;
+__m128i m128i;
+__m128d m128d;
+__m128  m128;
+__mmask8 mmask8;
+__mmask16 mmask16;
+
+void
+test8bit (void)
+{
+  m512i = _mm512_permutex_epi64 (m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_permutex_epi64 (m512i, mmask8, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_permutex_epi64 (mmask8, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_ternarylogic_epi64 (m512i, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_ternarylogic_epi64 (m512i, mmask8, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_ternarylogic_epi64 (mmask8, m512i, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_ternarylogic_epi32 (m512i, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_ternarylogic_epi32 (m512i, mmask16, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_ternarylogic_epi32 (mmask16, m512i, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_shuffle_epi32 (m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_shuffle_epi32 (m512i, mmask16, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_shuffle_epi32 (mmask16, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_shuffle_i64x2 (m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_shuffle_i64x2 (m512i, mmask8, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_shuffle_i64x2 (mmask8, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_shuffle_i32x4 (m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_shuffle_i32x4 (m512i, mmask16, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_shuffle_i32x4 (mmask16, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512d = _mm512_shuffle_f64x2 (m512d, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512d = _mm512_mask_shuffle_f64x2 (m512d, mmask8, m512d, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512d = _mm512_maskz_shuffle_f64x2 (mmask8, m512d, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512  = _mm512_shuffle_f32x4 (m512, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512  = _mm512_mask_shuffle_f32x4 (m512, mmask16, m512, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512  = _mm512_maskz_shuffle_f32x4 (mmask16, m512, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512d = _mm512_permutex_pd (m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512d = _mm512_mask_permutex_pd (m512d, mmask8, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512d = _mm512_maskz_permutex_pd (mmask8, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512d = _mm512_permute_pd (m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512d = _mm512_mask_permute_pd (m512d, mmask8, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512d = _mm512_maskz_permute_pd (mmask8, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512  = _mm512_permute_ps (m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512  = _mm512_mask_permute_ps (m512, mmask16, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512  = _mm512_maskz_permute_ps (mmask16, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512d = _mm512_shuffle_pd (m512d, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512d = _mm512_mask_shuffle_pd (m512d, mmask8, m512d, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512d = _mm512_maskz_shuffle_pd (mmask8, m512d, m512d, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512  = _mm512_shuffle_ps (m512, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512  = _mm512_mask_shuffle_ps (m512, mmask16, m512, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512  = _mm512_maskz_shuffle_ps (mmask16, m512, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512d = _mm512_fixupimm_pd (m512d, m512d, m512i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m512d = _mm512_mask_fixupimm_pd (m512d, mmask8, m512d, m512i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m512d = _mm512_maskz_fixupimm_pd (mmask8, m512d, m512d, m512i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+
+  m512  = _mm512_fixupimm_ps (m512, m512, m512i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m512  = _mm512_mask_fixupimm_ps (m512, mmask16, m512, m512i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m512  = _mm512_maskz_fixupimm_ps (mmask16, m512, m512, m512i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+
+  m128d = _mm_fixupimm_sd (m128d, m128d, m128i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m128d = _mm_mask_fixupimm_sd (m128d, mmask8, m128d, m128i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m128d = _mm_maskz_fixupimm_sd (mmask8, m128d, m128d, m128i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+
+  m128  = _mm_fixupimm_ss (m128, m128, m128i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m128  = _mm_mask_fixupimm_ss (m128, mmask8, m128, m128i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m128  = _mm_maskz_fixupimm_ss (mmask8, m128, m128, m128i, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_rol_epi32 (m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_rol_epi32 (m512i, mmask16, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_rol_epi32 (mmask16, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_ror_epi32 (m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_ror_epi32 (m512i, mmask16, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_ror_epi32 (mmask16, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_rol_epi64 (m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_rol_epi64 (m512i, mmask8, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_rol_epi64 (mmask8, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_ror_epi64 (m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_ror_epi64 (m512i, mmask8, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_ror_epi64 (mmask8, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m256i = _mm512_cvtps_ph (m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m256i = _mm512_mask_cvtps_ph (m256i, mmask16, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m256i = _mm512_maskz_cvtps_ph (mmask16, m512, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  m512d = _mm512_roundscale_pd (m512d, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m512d = _mm512_mask_roundscale_pd (m512d, mmask8, m512d, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m512d = _mm512_maskz_roundscale_pd (mmask8, m512d, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+
+  m512  = _mm512_roundscale_ps (m512, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m512  = _mm512_mask_roundscale_ps (m512, mmask16, m512, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m512  = _mm512_maskz_roundscale_ps (mmask16, m512, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+
+  m128d = _mm_roundscale_sd (m128d, m128d, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+  m128  = _mm_roundscale_ss (m128, m128, 256); /* { dg-error "the immediate argument must be an 8-bit immediate" } */
+
+  m512i = _mm512_alignr_epi32 (m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_alignr_epi32 (m512i, mmask16, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_alignr_epi32 (mmask16, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_alignr_epi64 (m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_mask_alignr_epi64 (m512i, mmask8, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  m512i = _mm512_maskz_alignr_epi64 (mmask8, m512i, m512i, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+
+  mmask8 = _mm512_cmp_epi64_mask (m512i, m512i, 256); /* { dg-error "the last argument must be a 3-bit immediate" } */
+  mmask8 = _mm512_cmp_epi32_mask (m512i, m512i, 256); /* { dg-error "the last argument must be a 3-bit immediate" } */
+  mmask8 = _mm512_cmp_epu64_mask (m512i, m512i, 256); /* { dg-error "the last argument must be a 3-bit immediate" } */
+  mmask8 = _mm512_cmp_epu32_mask (m512i, m512i, 256); /* { dg-error "the last argument must be a 3-bit immediate" } */
+  mmask8 = _mm512_cmp_pd_mask (m512d, m512d, 256); /* { dg-error "the immediate argument must be a 5-bit immediate" } */
+  mmask8 = _mm512_cmp_ps_mask (m512, m512, 256); /* { dg-error "the immediate argument must be a 5-bit immediate" } */
+  mmask8 = _mm512_mask_cmp_epi64_mask (2, m512i, m512i, 256); /* { dg-error "the last argument must be a 3-bit immediate" } */
+  mmask8 = _mm512_mask_cmp_epi32_mask (2, m512i, m512i, 256); /* { dg-error "the last argument must be a 3-bit immediate" } */
+  mmask8 = _mm512_mask_cmp_epu64_mask (2, m512i, m512i, 256); /* { dg-error "the last argument must be a 3-bit immediate" } */
+  mmask8 = _mm512_mask_cmp_epu32_mask (2, m512i, m512i, 256); /* { dg-error "the last argument must be a 3-bit immediate" } */
+  mmask8 = _mm512_mask_cmp_pd_mask (2, m512d, m512d, 256); /* { dg-error "the immediate argument must be a 5-bit immediate" } */
+  mmask8 = _mm512_mask_cmp_ps_mask (2, m512, m512, 256); /* { dg-error "the immediate argument must be a 5-bit immediate" } */
+  mmask8 = _mm_cmp_sd_mask (m128d, m128d, 256); /* { dg-error "the immediate argument must be a 5-bit immediate" } */
+  mmask8 = _mm_cmp_ss_mask (m128, m128, 256); /* { dg-error "the immediate argument must be a 5-bit immediate" } */
+  mmask8 = _mm_mask_cmp_sd_mask (1, m128d, m128d, 256); /* { dg-error "the immediate argument must be a 5-bit immediate" } */
+  mmask8 = _mm_mask_cmp_ss_mask (1, m128, m128, 256); /* { dg-error "the immediate argument must be a 5-bit immediate" } */
+
+}
+
+test1bit (void) {
+  m256d = _mm512_extractf64x4_pd (m512d, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  m256d = _mm512_mask_extractf64x4_pd (m256d, mmask8, m512d, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  m256d = _mm512_maskz_extractf64x4_pd (mmask8, m512d, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+
+  m256i = _mm512_extracti64x4_epi64 (m512i, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  m256i = _mm512_mask_extracti64x4_epi64 (m256i, mmask8, m512i, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  m256i = _mm512_maskz_extracti64x4_epi64 (mmask8, m512i, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+
+  m512d = _mm512_insertf64x4 (m512d, m256d, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  m512d = _mm512_mask_insertf64x4 (m512d, mmask8, m512d, m256d, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  m512d = _mm512_maskz_insertf64x4 (mmask8, m512d, m256d, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+
+  m512i = _mm512_inserti64x4 (m512i, m256i, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  m512i = _mm512_mask_inserti64x4 (m512i, mmask8, m512i, m256i, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  m512i = _mm512_maskz_inserti64x4 (mmask8, m512i, m256i, 256); /* { dg-error "the last argument must be a 1-bit immediate" } */
+}
+
+test2bit (void) {
+  m128  = _mm512_extractf32x4_ps(m512, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+  m128  = _mm512_mask_extractf32x4_ps(m128, mmask8, m512, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+  m128  = _mm512_maskz_extractf32x4_ps(mmask8, m512, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+
+  m128i = _mm512_extracti32x4_epi32 (m512i, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+  m128i = _mm512_mask_extracti32x4_epi32 (m128i, mmask8, m512i, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+  m128i = _mm512_maskz_extracti32x4_epi32 (mmask8, m512i, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+
+  m512  = _mm512_insertf32x4 (m512, m128, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+  m512  = _mm512_mask_insertf32x4 (m512, mmask16, m512, m128, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+  m512  = _mm512_maskz_insertf32x4 (mmask16, m512, m128, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+
+  m512i = _mm512_inserti32x4 (m512i, m128i, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+  m512i = _mm512_mask_inserti32x4 (m512i, mmask16, m512i, m128i, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+  m512i = _mm512_maskz_inserti32x4 (mmask16, m512i, m128i, 256); /* { dg-error "the last argument must be a 2-bit immediate" } */
+}
+
+test4bit (void) {
+  m512d = _mm512_getmant_pd (m512d, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */
+  m512d = _mm512_mask_getmant_pd (m512d, mmask8, m512d, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */
+  m512d = _mm512_maskz_getmant_pd (mmask8, m512d, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */
+
+  m512  = _mm512_getmant_ps (m512, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */
+  m512  = _mm512_mask_getmant_ps (m512, mmask16, m512, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */
+  m512  = _mm512_maskz_getmant_ps (mmask16, m512, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */
+
+  m128d = _mm_getmant_sd (m128d, m128d, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */
+  m128  = _mm_getmant_ss (m128, m128, 1, 64); /* { dg-error "the immediate argument must be a 4-bit immediate" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-2.c
new file mode 100644
index 000000000..3d5080920
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-2.c
@@ -0,0 +1,94 @@
+/* PR target/49411 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -mf16c -maes -mpclmul" } */
+
+#include <x86intrin.h>
+
+__m128i i1, i2, i3, i4;
+__m128 a1, a2, a3, a4;
+__m128d d1, d2, d3, d4;
+__m256i l1, l2, l3, l4;
+__m256 b1, b2, b3, b4;
+__m256d e1, e2, e3, e4;
+__m64 m1, m2, m3, m4;
+int k1, k2, k3, k4;
+float f1, f2, f3, f4;
+
+void
+test8bit (void)
+{
+  i1 = _mm_cmpistrm (i2, i3, -10);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistri (i2, i3, -10);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistra (i2, i3, -10);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrc (i2, i3, -10);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistro (i2, i3, -10);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrs (i2, i3, -10);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrz (i2, i3, -10);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  i1 = _mm_cmpestrm (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestri (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestra (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrc (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestro (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrs (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrz (i2, k2, i3, k3, -10);/* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  b1 = _mm256_blend_ps (b2, b3, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  k1 = _cvtss_sh (f1, -10);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm256_cvtps_ph (b2, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_dp_ps (b2, b3, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  e1 = _mm256_permute2f128_pd (e2, e3, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_permute2f128_ps (b2, b3, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_permute2f128_si256 (l2, l3, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_permute_ps (b2, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_aeskeygenassist_si128 (i2, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_blend_epi16 (i2, i3, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_clmulepi64_si128 (i2, i3, -10);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_cvtps_ph (a1, -10);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  d1 = _mm_dp_pd (d2, d3, -10);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_dp_ps (a2, a3, -10);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_insert_ps (a2, a3, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_mpsadbw_epu8 (i2, i3, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_permute_ps (a2, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_slli_si128 (i2, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_srli_si128 (i2, -10);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+}
+
+void
+test5bit (void)
+{
+  d1 = _mm_cmp_sd (d2, d3, -7);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  a1 = _mm_cmp_ss (a2, a3, -7);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  d1 = _mm_cmp_pd (d2, d3, -7);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  a1 = _mm_cmp_ps (a2, a3, -7);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  e1 = _mm256_cmp_pd (e2, e3, -7);	  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  b1 = _mm256_cmp_ps (b2, b3, -7);	  /* { dg-error "the last argument must be a 5-bit immediate" } */
+}
+
+void
+test4bit (void)
+{
+  d1 = _mm_round_pd (d2, -7);		  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  d1 = _mm_round_sd (d2, d3, -7);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_round_ps (a2, -7);		  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_round_ss (a2, a2, -7);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_blend_ps (a2, a3, -7);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  e1 = _mm256_blend_pd (e2, e3, -7);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  e1 = _mm256_round_pd (e2, -7);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  b1 = _mm256_round_ps (b2, -7);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+}
+
+void
+test2bit (void)
+{
+  d1 = _mm_blend_pd (d2, d3, -1);	  /* { dg-error "the last argument must be a 2-bit immediate" } */
+}
+
+void
+test1bit (void)
+{
+  d1 = _mm256_extractf128_pd (e2, -1);	  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  a1 = _mm256_extractf128_ps (b2, -1);	  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  i1 = _mm256_extractf128_si256 (l2, -1); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  e1 = _mm256_insertf128_pd (e2, d1, -1); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  b1 = _mm256_insertf128_ps (b2, a1, -1); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  l1 = _mm256_insertf128_si256 (l2, i1, -1);/* { dg-error "the last argument must be a 1-bit immediate" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-3.c
new file mode 100644
index 000000000..3e4fea7fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-3.c
@@ -0,0 +1,94 @@
+/* PR target/49411 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -mf16c -maes -mpclmul" } */
+
+#include <x86intrin.h>
+
+__m128i i1, i2, i3, i4;
+__m128 a1, a2, a3, a4;
+__m128d d1, d2, d3, d4;
+__m256i l1, l2, l3, l4;
+__m256 b1, b2, b3, b4;
+__m256d e1, e2, e3, e4;
+__m64 m1, m2, m3, m4;
+int k1, k2, k3, k4;
+float f1, f2, f3, f4;
+
+void
+test8bit (void)
+{
+  i1 = _mm_cmpistrm (i2, i3, k4);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistri (i2, i3, k4);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistra (i2, i3, k4);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrc (i2, i3, k4);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistro (i2, i3, k4);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrs (i2, i3, k4);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpistrz (i2, i3, k4);	  /* { dg-error "the third argument must be an 8-bit immediate" } */
+  i1 = _mm_cmpestrm (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestri (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestra (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrc (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestro (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrs (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  k1 = _mm_cmpestrz (i2, k2, i3, k3, k4); /* { dg-error "the fifth argument must be an 8-bit immediate" } */
+  b1 = _mm256_blend_ps (b2, b3, k4);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  k1 = _cvtss_sh (f1, k4);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm256_cvtps_ph (b2, k4);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_dp_ps (b2, b3, k4);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  e1 = _mm256_permute2f128_pd (e2, e3, k4);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_permute2f128_ps (b2, b3, k4);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_permute2f128_si256 (l2, l3, k4);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  b1 = _mm256_permute_ps (b2, k4);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_aeskeygenassist_si128 (i2, k4);/* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_blend_epi16 (i2, i3, k4);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_clmulepi64_si128 (i2, i3, k4); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_cvtps_ph (a1, k4);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  d1 = _mm_dp_pd (d2, d3, k4);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_dp_ps (a2, a3, k4);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_insert_ps (a2, a3, k4);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_mpsadbw_epu8 (i2, i3, k4);	  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  a1 = _mm_permute_ps (a2, k4);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_slli_si128 (i2, k4);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_srli_si128 (i2, k4);		  /* { dg-error "the last argument must be an 8-bit immediate" } */
+}
+
+void
+test5bit (void)
+{
+  d1 = _mm_cmp_sd (d2, d3, k4);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  a1 = _mm_cmp_ss (a2, a3, k4);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  d1 = _mm_cmp_pd (d2, d3, k4);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  a1 = _mm_cmp_ps (a2, a3, k4);		  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  e1 = _mm256_cmp_pd (e2, e3, k4);	  /* { dg-error "the last argument must be a 5-bit immediate" } */
+  b1 = _mm256_cmp_ps (b2, b3, k4);	  /* { dg-error "the last argument must be a 5-bit immediate" } */
+}
+
+void
+test4bit (void)
+{
+  d1 = _mm_round_pd (d2, k4);		  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  d1 = _mm_round_sd (d2, d3, k4);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_round_ps (a2, k4);		  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_round_ss (a2, a2, k4);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  a1 = _mm_blend_ps (a2, a3, k4);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  e1 = _mm256_blend_pd (e2, e3, k4);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  e1 = _mm256_round_pd (e2, k4);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+  b1 = _mm256_round_ps (b2, k4);	  /* { dg-error "the last argument must be a 4-bit immediate" } */
+}
+
+void
+test2bit (void)
+{
+  d1 = _mm_blend_pd (d2, d3, k4);	  /* { dg-error "the last argument must be a 2-bit immediate" } */
+}
+
+void
+test1bit (void)
+{
+  d1 = _mm256_extractf128_pd (e2, k4);	  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  a1 = _mm256_extractf128_ps (b2, k4);	  /* { dg-error "the last argument must be a 1-bit immediate" } */
+  i1 = _mm256_extractf128_si256 (l2, k4); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  e1 = _mm256_insertf128_pd (e2, d1, k4); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  b1 = _mm256_insertf128_ps (b2, a1, k4); /* { dg-error "the last argument must be a 1-bit immediate" } */
+  l1 = _mm256_insertf128_si256 (l2, i1, k4);/* { dg-error "the last argument must be a 1-bit immediate" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-4.c
new file mode 100644
index 000000000..2eaf41338
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-4.c
@@ -0,0 +1,97 @@
+/* PR target/49411 */
+/* { dg-do assemble } */
+/* { dg-options "-O0 -mf16c -maes -mpclmul" } */
+/* { dg-require-effective-target f16c } */
+/* { dg-require-effective-target vaes } */
+/* { dg-require-effective-target vpclmul } */
+
+#include <x86intrin.h>
+
+__m128i i1, i2, i3, i4;
+__m128 a1, a2, a3, a4;
+__m128d d1, d2, d3, d4;
+__m256i l1, l2, l3, l4;
+__m256 b1, b2, b3, b4;
+__m256d e1, e2, e3, e4;
+__m64 m1, m2, m3, m4;
+int k1, k2, k3, k4;
+float f1, f2, f3, f4;
+
+void
+test8bit (void)
+{
+  i1 = _mm_cmpistrm (i2, i3, 255);
+  k1 = _mm_cmpistri (i2, i3, 255);
+  k1 = _mm_cmpistra (i2, i3, 255);
+  k1 = _mm_cmpistrc (i2, i3, 255);
+  k1 = _mm_cmpistro (i2, i3, 255);
+  k1 = _mm_cmpistrs (i2, i3, 255);
+  k1 = _mm_cmpistrz (i2, i3, 255);
+  i1 = _mm_cmpestrm (i2, k2, i3, k3, 255);
+  k1 = _mm_cmpestri (i2, k2, i3, k3, 255);
+  k1 = _mm_cmpestra (i2, k2, i3, k3, 255);
+  k1 = _mm_cmpestrc (i2, k2, i3, k3, 255);
+  k1 = _mm_cmpestro (i2, k2, i3, k3, 255);
+  k1 = _mm_cmpestrs (i2, k2, i3, k3, 255);
+  k1 = _mm_cmpestrz (i2, k2, i3, k3, 255);
+  b1 = _mm256_blend_ps (b2, b3, 255);
+  k1 = _cvtss_sh (f1, 255);
+  i1 = _mm256_cvtps_ph (b2, 255);
+  b1 = _mm256_dp_ps (b2, b3, 255);
+  e1 = _mm256_permute2f128_pd (e2, e3, 255);
+  b1 = _mm256_permute2f128_ps (b2, b3, 255);
+  l1 = _mm256_permute2f128_si256 (l2, l3, 255);
+  b1 = _mm256_permute_ps (b2, 255);
+  i1 = _mm_aeskeygenassist_si128 (i2, 255);
+  i1 = _mm_blend_epi16 (i2, i3, 255);
+  i1 = _mm_clmulepi64_si128 (i2, i3, 255);
+  i1 = _mm_cvtps_ph (a1, 255);
+  d1 = _mm_dp_pd (d2, d3, 255);
+  a1 = _mm_dp_ps (a2, a3, 255);
+  a1 = _mm_insert_ps (a2, a3, 255);
+  i1 = _mm_mpsadbw_epu8 (i2, i3, 255);
+  a1 = _mm_permute_ps (a2, 255);
+  i1 = _mm_slli_si128 (i2, 255);
+  i1 = _mm_srli_si128 (i2, 255);
+}
+
+void
+test5bit (void)
+{
+  d1 = _mm_cmp_sd (d2, d3, 31);
+  a1 = _mm_cmp_ss (a2, a3, 31);
+  d1 = _mm_cmp_pd (d2, d3, 31);
+  a1 = _mm_cmp_ps (a2, a3, 31);
+  e1 = _mm256_cmp_pd (e2, e3, 31);
+  b1 = _mm256_cmp_ps (b2, b3, 31);
+}
+
+void
+test4bit (void)
+{
+  d1 = _mm_round_pd (d2, 15);
+  d1 = _mm_round_sd (d2, d3, 15);
+  a1 = _mm_round_ps (a2, 15);
+  a1 = _mm_round_ss (a2, a2, 15);
+  a1 = _mm_blend_ps (a2, a3, 15);
+  e1 = _mm256_blend_pd (e2, e3, 15);
+  e1 = _mm256_round_pd (e2, 15);
+  b1 = _mm256_round_ps (b2, 15);
+}
+
+void
+test2bit (void)
+{
+  d1 = _mm_blend_pd (d2, d3, 3);
+}
+
+void
+test1bit (void)
+{
+  d1 = _mm256_extractf128_pd (e2, 1);
+  a1 = _mm256_extractf128_ps (b2, 1);
+  i1 = _mm256_extractf128_si256 (l2, 1);
+  e1 = _mm256_insertf128_pd (e2, d1, 1);
+  b1 = _mm256_insertf128_ps (b2, a1, 1);
+  l1 = _mm256_insertf128_si256 (l2, i1, 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-5.c
new file mode 100644
index 000000000..67c152834
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-5.c
@@ -0,0 +1,8 @@
+/* PR target/49411 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mf16c -maes -mpclmul" } */
+/* { dg-require-effective-target f16c } */
+/* { dg-require-effective-target vaes } */
+/* { dg-require-effective-target vpclmul } */
+
+#include "testimm-4.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-6.c
new file mode 100644
index 000000000..087a6ffa5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-6.c
@@ -0,0 +1,41 @@
+/* PR target/49411 */
+/* { dg-do compile } */
+/* { dg-options "-O0 -mxop" } */
+
+#include <x86intrin.h>
+
+__m128i i1, i2, i3, i4;
+__m128 a1, a2, a3, a4;
+__m128d d1, d2, d3, d4;
+__m256i l1, l2, l3, l4;
+__m256 b1, b2, b3, b4;
+__m256d e1, e2, e3, e4;
+__m64 m1, m2, m3, m4;
+int k1, k2, k3, k4;
+float f1, f2, f3, f4;
+
+void
+test2bit (void)
+{
+  d1 = _mm_permute2_pd (d2, d3, i1, 17);	/* { dg-error "the last argument must be a 2-bit immediate" } */
+  e1 = _mm256_permute2_pd (e2, e3, l1, 17);	/* { dg-error "the last argument must be a 2-bit immediate" } */
+  a1 = _mm_permute2_ps (a2, a3, i1, 17);	/* { dg-error "the last argument must be a 2-bit immediate" } */
+  b1 = _mm256_permute2_ps (b2, b3, l1, 17);	/* { dg-error "the last argument must be a 2-bit immediate" } */
+  d1 = _mm_permute2_pd (d2, d3, i1, k4);	/* { dg-error "the last argument must be a 2-bit immediate" } */
+  e1 = _mm256_permute2_pd (e2, e3, l1, k4);	/* { dg-error "the last argument must be a 2-bit immediate" } */
+  a1 = _mm_permute2_ps (a2, a3, i1, k4);	/* { dg-error "the last argument must be a 2-bit immediate" } */
+  b1 = _mm256_permute2_ps (b2, b3, l1, k4);	/* { dg-error "the last argument must be a 2-bit immediate" } */
+}
+
+void
+test2args (void)
+{
+  i1 = _mm_extracti_si64 (i2, 256, 0);		/* { dg-error "the next to last argument must be an 8-bit immediate" } */
+  i1 = _mm_extracti_si64 (i2, 0, 256);		/* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_inserti_si64 (i2, i3, 256, 0);	/* { dg-error "the next to last argument must be an 8-bit immediate" } */
+  i2 = _mm_inserti_si64 (i2, i3, 0, 256);	/* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_extracti_si64 (i2, k4, 0);		/* { dg-error "the next to last argument must be an 8-bit immediate" } */
+  i1 = _mm_extracti_si64 (i2, 0, k4);		/* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_inserti_si64 (i2, i3, k4, 0);	/* { dg-error "the next to last argument must be an 8-bit immediate" } */
+  i2 = _mm_inserti_si64 (i2, i3, 0, k4);	/* { dg-error "the last argument must be an 8-bit immediate" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-7.c
new file mode 100644
index 000000000..9b16fc7f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-7.c
@@ -0,0 +1,46 @@
+/* PR target/49411 */
+/* { dg-do assemble } */
+/* { dg-options "-O0 -mxop" } */
+/* { dg-require-effective-target xop } */
+
+#include <x86intrin.h>
+
+__m128i i1, i2, i3, i4;
+__m128 a1, a2, a3, a4;
+__m128d d1, d2, d3, d4;
+__m256i l1, l2, l3, l4;
+__m256 b1, b2, b3, b4;
+__m256d e1, e2, e3, e4;
+__m64 m1, m2, m3, m4;
+int k1, k2, k3, k4;
+float f1, f2, f3, f4;
+
+void
+test2bit (void)
+{
+  d1 = _mm_permute2_pd (d2, d3, i1, 3);
+  e1 = _mm256_permute2_pd (e2, e3, l1, 3);
+  a1 = _mm_permute2_ps (a2, a3, i1, 3);
+  b1 = _mm256_permute2_ps (b2, b3, l1, 3);
+  d1 = _mm_permute2_pd (d2, d3, i1, 0);
+  e1 = _mm256_permute2_pd (e2, e3, l1, 0);
+  a1 = _mm_permute2_ps (a2, a3, i1, 0);
+  b1 = _mm256_permute2_ps (b2, b3, l1, 0);
+}
+
+void
+test2args (void)
+{
+  i1 = _mm_extracti_si64 (i2, 255, 0);
+  i1 = _mm_extracti_si64 (i2, 0, 255);
+  i1 = _mm_inserti_si64 (i2, i3, 255, 0);
+  i2 = _mm_inserti_si64 (i2, i3, 0, 255);
+  i1 = _mm_extracti_si64 (i2, 255, 255);
+  i1 = _mm_extracti_si64 (i2, 255, 255);
+  i1 = _mm_inserti_si64 (i2, i3, 255, 255);
+  i2 = _mm_inserti_si64 (i2, i3, 255, 255);
+  i1 = _mm_extracti_si64 (i2, 0, 0);
+  i1 = _mm_extracti_si64 (i2, 0, 0);
+  i1 = _mm_inserti_si64 (i2, i3, 0, 0);
+  i2 = _mm_inserti_si64 (i2, i3, 0, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-8.c
new file mode 100644
index 000000000..5169763fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-8.c
@@ -0,0 +1,6 @@
+/* PR target/49411 */
+/* { dg-do assemble } */
+/* { dg-options "-O2 -mxop" } */
+/* { dg-require-effective-target xop } */
+
+#include "testimm-7.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-9.c
new file mode 100644
index 000000000..a9b4fe9e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testimm-9.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx2" } */
+
+#include <x86intrin.h>
+
+__m128i i1, i2, i3, i4;
+__m256i l1, l2, l3, l4;
+__m256d e1, e2, e3, e4;
+
+void
+test8bit (void)
+{
+  l1 = _mm256_mpsadbw_epu8 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_alignr_epi8 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  i1 = _mm_blend_epi32 (i1, i1, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_blend_epi32 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_blend_epi16(l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_permute2x128_si256 (l2, l3, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  e1 = _mm256_permute4x64_pd (e2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_permute4x64_epi64 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_shuffle_epi32 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_shufflehi_epi16 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_shufflelo_epi16 (l2, 256);  /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_slli_si256 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+  l1 = _mm256_srli_si256 (l2, 256); /* { dg-error "the last argument must be an 8-bit immediate" } */
+}
+
+void
+test1bit (void)
+{
+  i1 = _mm256_extracti128_si256 (l1, 2);  /* { dg-error "the last argument must be an 1-bit immediate" } */
+  l1 = _mm256_inserti128_si256 (l1, i2, 2);  /* { dg-error "the last argument must be an 1-bit immediate" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testround-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testround-1.c
new file mode 100644
index 000000000..20c039ab0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testround-1.c
@@ -0,0 +1,507 @@
+/* { dg-do compile } */
+/* { dg-options "-O0 -mavx512f" } */
+
+#include <x86intrin.h>
+
+int i;
+unsigned int ui;
+__m512i m512i;
+__m512d m512d;
+__m512  m512;
+__m256i m256i;
+__m256  m256;
+__m128i m128i;
+__m128d m128d;
+__m128  m128;
+__mmask8 mmask8;
+__mmask16 mmask16;
+
+void
+test_round (void)
+{
+  m128d = _mm_add_round_sd (m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_add_round_ss (m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_sub_round_sd (m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_sub_round_ss (m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_sqrt_round_pd (m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_sqrt_round_pd (m512d, mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_sqrt_round_pd (mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_sqrt_round_ps (m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_sqrt_round_ps (m512, mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_sqrt_round_ps (mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_sqrt_round_sd (m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_sqrt_round_ss (m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_add_round_pd (m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_add_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_add_round_pd (mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_add_round_ps (m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_add_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_add_round_ps (mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_sub_round_pd (m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_sub_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_sub_round_pd (mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_sub_round_ps (m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_sub_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_sub_round_ps (mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_mul_round_pd (m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_mul_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_mul_round_pd (mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mul_round_ps (m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_mul_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_mul_round_ps (mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_div_round_pd (m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_div_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_div_round_pd (mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_div_round_ps (m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_div_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_div_round_ps (mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_mul_round_sd (m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_mul_round_ss (m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_div_round_sd (m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_div_round_ss (m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_scalef_round_pd(m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_scalef_round_pd(m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_scalef_round_pd(mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_scalef_round_ps(m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_scalef_round_ps(m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_scalef_round_ps(mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_scalef_round_sd (m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_scalef_round_ss (m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_fmadd_round_pd (m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fmadd_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fmadd_round_pd (m512d, m512d, m512d, mmask8, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fmadd_round_pd (mmask8, m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fmadd_round_ps (m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fmadd_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fmadd_round_ps (m512, m512, m512, mmask16, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fmadd_round_ps (mmask16, m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fmsub_round_pd (m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fmsub_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fmsub_round_pd (m512d, m512d, m512d, mmask8, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fmsub_round_pd (mmask8, m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fmsub_round_ps (m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fmsub_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fmsub_round_ps (m512, m512, m512, mmask16, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fmsub_round_ps (mmask16, m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fmaddsub_round_pd (m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fmaddsub_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fmaddsub_round_pd (m512d, m512d, m512d, mmask8, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fmaddsub_round_pd (mmask8, m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fmaddsub_round_ps (m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fmaddsub_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fmaddsub_round_ps (m512, m512, m512, mmask16, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fmaddsub_round_ps (mmask16, m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fmsubadd_round_pd (m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fmsubadd_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fmsubadd_round_pd (m512d, m512d, m512d, mmask8, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fmsubadd_round_pd (mmask8, m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fmsubadd_round_ps (m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fmsubadd_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fmsubadd_round_ps (m512, m512, m512, mmask16, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fmsubadd_round_ps (mmask16, m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fnmadd_round_pd (m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fnmadd_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fnmadd_round_pd (m512d, m512d, m512d, mmask8, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fnmadd_round_pd (mmask8, m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fnmadd_round_ps (m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fnmadd_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fnmadd_round_ps (m512, m512, m512, mmask16, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fnmadd_round_ps (mmask16, m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fnmsub_round_pd (m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fnmsub_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fnmsub_round_pd (m512d, m512d, m512d, mmask8, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fnmsub_round_pd (mmask8, m512d, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fnmsub_round_ps (m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fnmsub_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fnmsub_round_ps (m512, m512, m512, mmask16, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fnmsub_round_ps (mmask16, m512, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m256i = _mm512_cvt_roundpd_epi32 (m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_mask_cvt_roundpd_epi32 (m256i, mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_maskz_cvt_roundpd_epi32 (mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_cvt_roundpd_epu32 (m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_mask_cvt_roundpd_epu32 (m256i, mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_maskz_cvt_roundpd_epu32 (mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512i = _mm512_cvt_roundps_epi32 (m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_mask_cvt_roundps_epi32 (m512i, mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_maskz_cvt_roundps_epi32 (mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_cvt_roundps_epu32 (m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_mask_cvt_roundps_epu32 (m512i, mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_maskz_cvt_roundps_epu32 (mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m128 = _mm_cvt_roundu32_ss (m128, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_cvt_roundi32_ss (m128, 4, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512 = _mm512_cvt_roundepi32_ps (m512i, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_cvt_roundepi32_ps (m512, mmask16, m512i, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_cvt_roundepi32_ps (mmask16, m512i, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_cvt_roundepu32_ps (m512i, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_cvt_roundepu32_ps (m512, mmask16, m512i, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_cvt_roundepu32_ps (mmask16, m512i, 7); /* { dg-error "incorrect rounding operand" } */
+
+  ui = _mm_cvt_roundss_u32 (m128, 7); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_cvt_roundss_i32 (m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  ui = _mm_cvt_roundsd_u32 (m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_cvt_roundsd_i32 (m128d, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m256 = _mm512_cvt_roundpd_ps (m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256 = _mm512_mask_cvt_roundpd_ps (m256, mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256 = _mm512_maskz_cvt_roundpd_ps (mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_cvt_roundsd_ss (m128, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m128d = _mm_fmadd_round_sd (m128d, m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fmadd_round_ss (m128, m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_fmsub_round_sd (m128d, m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fmsub_round_ss (m128, m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_fnmadd_round_sd (m128d, m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fnmadd_round_ss (m128, m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_fnmsub_round_sd (m128d, m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fnmsub_round_ss (m128, m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_max_round_pd (m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_max_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_max_round_pd (mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_max_round_ps (m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_max_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_max_round_ps (mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_min_round_pd (m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_min_round_pd (m512d, mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_min_round_pd (mmask8, m512d, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_min_round_ps (m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_min_round_ps (m512, mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_min_round_ps (mmask16, m512, m512, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m256i = _mm512_cvtt_roundpd_epi32 (m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_mask_cvtt_roundpd_epi32 (m256i, mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_maskz_cvtt_roundpd_epi32 (mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_cvtt_roundpd_epu32 (m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_mask_cvtt_roundpd_epu32 (m256i, mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_maskz_cvtt_roundpd_epu32 (mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512i = _mm512_cvtt_roundps_epi32 (m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_mask_cvtt_roundps_epi32 (m512i, mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_maskz_cvtt_roundps_epi32 (mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_cvtt_roundps_epu32 (m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_mask_cvtt_roundps_epu32 (m512i, mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_maskz_cvtt_roundps_epu32 (mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_fixupimm_round_pd (m512d, m512d, m512i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fixupimm_round_pd (m512d, mmask8, m512d, m512i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fixupimm_round_pd (mmask8, m512d, m512d, m512i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fixupimm_round_ps (m512, m512, m512i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fixupimm_round_ps (m512, mmask16, m512, m512i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fixupimm_round_ps (mmask16, m512, m512, m512i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_fixupimm_round_sd (m128d, m128d, m128i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_mask_fixupimm_round_sd (m128d, mmask8, m128d, m128i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_maskz_fixupimm_round_sd (mmask8, m128d, m128d, m128i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fixupimm_round_ss (m128, m128, m128i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_mask_fixupimm_round_ss (m128, mmask8, m128, m128i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_maskz_fixupimm_round_ss (mmask8, m128, m128, m128i, 4, 7); /* { dg-error "incorrect rounding operand" } */
+
+  ui = _mm_cvtt_roundss_u32 (m128, 7); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_cvtt_roundss_i32 (m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  ui = _mm_cvtt_roundsd_u32 (m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_cvtt_roundsd_i32 (m128d, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_cvt_roundps_pd (m256, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_cvt_roundps_pd (m512d, mmask8, m256, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_cvt_roundps_pd (mmask8, m256, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_cvt_roundph_ps (m256i, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_cvt_roundph_ps (m512, mmask16, m256i, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_cvt_roundph_ps (mmask16, m256i, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m128d = _mm_cvt_roundss_sd (m128d, m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m128 = _mm_getexp_round_ss (m128, m128, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_getexp_round_sd (m128d, m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_getexp_round_ps (m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_getexp_round_ps (m512, mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_getexp_round_ps (mmask16, m512, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_getexp_round_pd (m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_getexp_round_pd (m512d, mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_getexp_round_pd (mmask8, m512d, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_getmant_round_pd (m512d, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_getmant_round_pd (m512d, mmask8, m512d, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_getmant_round_pd (mmask8, m512d, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_getmant_round_ps (m512, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_getmant_round_ps (m512, mmask16, m512, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_getmant_round_ps (mmask16, m512, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_getmant_round_sd (m128d, m128d, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_getmant_round_ss (m128, m128, 0, 0, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m512 = _mm512_roundscale_round_ps (m512, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_roundscale_round_ps (m512, mmask16, m512, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_roundscale_round_ps (mmask16, m512, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_roundscale_round_pd (m512d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_roundscale_round_pd (m512d, mmask8, m512d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_roundscale_round_pd (mmask8, m512d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_roundscale_round_ss (m128, m128, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_roundscale_round_sd (m128d, m128d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+
+  mmask8 = _mm512_cmp_round_pd_mask (m512d, m512d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  mmask16 = _mm512_cmp_round_ps_mask (m512, m512, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  mmask8 = _mm512_mask_cmp_round_pd_mask (mmask8, m512d, m512d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  mmask16 = _mm512_mask_cmp_round_ps_mask (mmask16, m512, m512, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  mmask8 = _mm_cmp_round_sd_mask (m128d, m128d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  mmask8 = _mm_mask_cmp_round_sd_mask (mmask8, m128d, m128d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  mmask16 = _mm_cmp_round_ss_mask (m128, m128, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  mmask16 = _mm_mask_cmp_round_ss_mask (mmask8, m128, m128, 4, 7); /* { dg-error "incorrect rounding operand" } */
+
+  i = _mm_comi_round_ss (m128, m128, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_comi_round_sd (m128d, m128d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+}
+
+void
+test_round_sae (void)
+{
+  m128d = _mm_add_round_sd (m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_add_round_ss (m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_sub_round_sd (m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_sub_round_ss (m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_sqrt_round_pd (m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_sqrt_round_pd (m512d, mmask8, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_sqrt_round_pd (mmask8, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_sqrt_round_ps (m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_sqrt_round_ps (m512, mmask16, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_sqrt_round_ps (mmask16, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_sqrt_round_sd (m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_sqrt_round_ss (m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_add_round_pd (m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_add_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_add_round_pd (mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_add_round_ps (m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_add_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_add_round_ps (mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_sub_round_pd (m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_sub_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_sub_round_pd (mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_sub_round_ps (m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_sub_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_sub_round_ps (mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_mul_round_pd (m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_mul_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_mul_round_pd (mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mul_round_ps (m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_mul_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_mul_round_ps (mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_div_round_pd (m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_div_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_div_round_pd (mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_div_round_ps (m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_div_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_div_round_ps (mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_mul_round_sd (m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_mul_round_ss (m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_div_round_sd (m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_div_round_ss (m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_scalef_round_pd(m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_scalef_round_pd(m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_scalef_round_pd(mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_scalef_round_ps(m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_scalef_round_ps(m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_scalef_round_ps(mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_scalef_round_sd (m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_scalef_round_ss (m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_fmadd_round_pd (m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fmadd_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fmadd_round_pd (m512d, m512d, m512d, mmask8, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fmadd_round_pd (mmask8, m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fmadd_round_ps (m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fmadd_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fmadd_round_ps (m512, m512, m512, mmask16, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fmadd_round_ps (mmask16, m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fmsub_round_pd (m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fmsub_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fmsub_round_pd (m512d, m512d, m512d, mmask8, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fmsub_round_pd (mmask8, m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fmsub_round_ps (m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fmsub_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fmsub_round_ps (m512, m512, m512, mmask16, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fmsub_round_ps (mmask16, m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fmaddsub_round_pd (m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fmaddsub_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fmaddsub_round_pd (m512d, m512d, m512d, mmask8, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fmaddsub_round_pd (mmask8, m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fmaddsub_round_ps (m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fmaddsub_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fmaddsub_round_ps (m512, m512, m512, mmask16, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fmaddsub_round_ps (mmask16, m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fmsubadd_round_pd (m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fmsubadd_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fmsubadd_round_pd (m512d, m512d, m512d, mmask8, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fmsubadd_round_pd (mmask8, m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fmsubadd_round_ps (m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fmsubadd_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fmsubadd_round_ps (m512, m512, m512, mmask16, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fmsubadd_round_ps (mmask16, m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fnmadd_round_pd (m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fnmadd_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fnmadd_round_pd (m512d, m512d, m512d, mmask8, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fnmadd_round_pd (mmask8, m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fnmadd_round_ps (m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fnmadd_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fnmadd_round_ps (m512, m512, m512, mmask16, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fnmadd_round_ps (mmask16, m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_fnmsub_round_pd (m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fnmsub_round_pd (m512d, mmask8, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask3_fnmsub_round_pd (m512d, m512d, m512d, mmask8, 5); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fnmsub_round_pd (mmask8, m512d, m512d, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fnmsub_round_ps (m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fnmsub_round_ps (m512, mmask16, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask3_fnmsub_round_ps (m512, m512, m512, mmask16, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fnmsub_round_ps (mmask16, m512, m512, m512, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m256i = _mm512_cvt_roundpd_epi32 (m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_mask_cvt_roundpd_epi32 (m256i, mmask8, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_maskz_cvt_roundpd_epi32 (mmask8, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_cvt_roundpd_epu32 (m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_mask_cvt_roundpd_epu32 (m256i, mmask8, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_maskz_cvt_roundpd_epu32 (mmask8, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m512i = _mm512_cvt_roundps_epi32 (m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_mask_cvt_roundps_epi32 (m512i, mmask16, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_maskz_cvt_roundps_epi32 (mmask16, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_cvt_roundps_epu32 (m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_mask_cvt_roundps_epu32 (m512i, mmask16, m512, 5); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_maskz_cvt_roundps_epu32 (mmask16, m512, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m128 = _mm_cvt_roundu32_ss (m128, 4, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_cvt_roundi32_ss (m128, 4, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m512 = _mm512_cvt_roundepi32_ps (m512i, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_cvt_roundepi32_ps (m512, mmask16, m512i, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_cvt_roundepi32_ps (mmask16, m512i, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_cvt_roundepu32_ps (m512i, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_cvt_roundepu32_ps (m512, mmask16, m512i, 5); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_cvt_roundepu32_ps (mmask16, m512i, 5); /* { dg-error "incorrect rounding operand" } */
+
+  ui = _mm_cvt_roundss_u32 (m128, 5); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_cvt_roundss_i32 (m128, 5); /* { dg-error "incorrect rounding operand" } */
+
+  ui = _mm_cvt_roundsd_u32 (m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_cvt_roundsd_i32 (m128d, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m256 = _mm512_cvt_roundpd_ps (m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m256 = _mm512_mask_cvt_roundpd_ps (m256, mmask8, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m256 = _mm512_maskz_cvt_roundpd_ps (mmask8, m512d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_cvt_roundsd_ss (m128, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m128d = _mm_fmadd_round_sd (m128d, m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fmadd_round_ss (m128, m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_fmsub_round_sd (m128d, m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fmsub_round_ss (m128, m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_fnmadd_round_sd (m128d, m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fnmadd_round_ss (m128, m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_fnmsub_round_sd (m128d, m128d, m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fnmsub_round_ss (m128, m128, m128, 5); /* { dg-error "incorrect rounding operand" } */
+}
+
+void
+test_sae_only (void)
+{
+  m512d = _mm512_max_round_pd (m512d, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_max_round_pd (m512d, mmask8, m512d, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_max_round_pd (mmask8, m512d, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_max_round_ps (m512, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_max_round_ps (m512, mmask16, m512, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_max_round_ps (mmask16, m512, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_min_round_pd (m512d, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_min_round_pd (m512d, mmask8, m512d, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_min_round_pd (mmask8, m512d, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_min_round_ps (m512, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_min_round_ps (m512, mmask16, m512, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_min_round_ps (mmask16, m512, m512, 3); /* { dg-error "incorrect rounding operand" } */
+
+  m256i = _mm512_cvtt_roundpd_epi32 (m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_mask_cvtt_roundpd_epi32 (m256i, mmask8, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_maskz_cvtt_roundpd_epi32 (mmask8, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_cvtt_roundpd_epu32 (m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_mask_cvtt_roundpd_epu32 (m256i, mmask8, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m256i = _mm512_maskz_cvtt_roundpd_epu32 (mmask8, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+
+  m512i = _mm512_cvtt_roundps_epi32 (m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_mask_cvtt_roundps_epi32 (m512i, mmask16, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_maskz_cvtt_roundps_epi32 (mmask16, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_cvtt_roundps_epu32 (m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_mask_cvtt_roundps_epu32 (m512i, mmask16, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512i = _mm512_maskz_cvtt_roundps_epu32 (mmask16, m512, 3); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_fixupimm_round_pd (m512d, m512d, m512i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_fixupimm_round_pd (m512d, mmask8, m512d, m512i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_fixupimm_round_pd (mmask8, m512d, m512d, m512i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_fixupimm_round_ps (m512, m512, m512i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_fixupimm_round_ps (m512, mmask16, m512, m512i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_fixupimm_round_ps (mmask16, m512, m512, m512i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_fixupimm_round_sd (m128d, m128d, m128i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_mask_fixupimm_round_sd (m128d, mmask8, m128d, m128i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_maskz_fixupimm_round_sd (mmask8, m128d, m128d, m128i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_fixupimm_round_ss (m128, m128, m128i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_mask_fixupimm_round_ss (m128, mmask8, m128, m128i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_maskz_fixupimm_round_ss (mmask8, m128, m128, m128i, 4, 3); /* { dg-error "incorrect rounding operand" } */
+
+  ui = _mm_cvtt_roundss_u32 (m128, 3); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_cvtt_roundss_i32 (m128, 3); /* { dg-error "incorrect rounding operand" } */
+
+  ui = _mm_cvtt_roundsd_u32 (m128d, 3); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_cvtt_roundsd_i32 (m128d, 3); /* { dg-error "incorrect rounding operand" } */
+
+  m512d = _mm512_cvt_roundps_pd (m256, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_cvt_roundps_pd (m512d, mmask8, m256, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_cvt_roundps_pd (mmask8, m256, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_cvt_roundph_ps (m256i, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_cvt_roundph_ps (m512, mmask16, m256i, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_cvt_roundph_ps (mmask16, m256i, 3); /* { dg-error "incorrect rounding operand" } */
+
+  m128d = _mm_cvt_roundss_sd (m128d, m128, 3); /* { dg-error "incorrect rounding operand" } */
+
+  m128 = _mm_getexp_round_ss (m128, m128, 3); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_getexp_round_sd (m128d, m128d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_getexp_round_ps (m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_getexp_round_ps (m512, mmask16, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_getexp_round_ps (mmask16, m512, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_getexp_round_pd (m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_getexp_round_pd (m512d, mmask8, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_getexp_round_pd (mmask8, m512d, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_getmant_round_pd (m512d, 0, 0, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_getmant_round_pd (m512d, mmask8, m512d, 0, 0, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_getmant_round_pd (mmask8, m512d, 0, 0, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_getmant_round_ps (m512, 0, 0, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_getmant_round_ps (m512, mmask16, m512, 0, 0, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_getmant_round_ps (mmask16, m512, 0, 0, 3); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_getmant_round_sd (m128d, m128d, 0, 0, 3); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_getmant_round_ss (m128, m128, 0, 0, 3); /* { dg-error "incorrect rounding operand" } */
+
+  m512 = _mm512_roundscale_round_ps (m512, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_mask_roundscale_round_ps (m512, mmask16, m512, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512 = _mm512_maskz_roundscale_round_ps (mmask16, m512, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_roundscale_round_pd (m512d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_mask_roundscale_round_pd (m512d, mmask8, m512d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m512d = _mm512_maskz_roundscale_round_pd (mmask8, m512d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_roundscale_round_ss (m128, m128, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_roundscale_round_sd (m128d, m128d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+
+  mmask8 = _mm512_cmp_round_pd_mask (m512d, m512d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  mmask16 = _mm512_cmp_round_ps_mask (m512, m512, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  mmask8 = _mm512_mask_cmp_round_pd_mask (mmask8, m512d, m512d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  mmask16 = _mm512_mask_cmp_round_ps_mask (mmask16, m512, m512, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  mmask8 = _mm_cmp_round_sd_mask (m128d, m128d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  mmask8 = _mm_mask_cmp_round_sd_mask (mmask8, m128d, m128d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  mmask16 = _mm_cmp_round_ss_mask (m128, m128, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  mmask16 = _mm_mask_cmp_round_ss_mask (mmask8, m128, m128, 4, 3); /* { dg-error "incorrect rounding operand" } */
+
+  i = _mm_comi_round_ss (m128, m128, 4, 3); /* { dg-error "incorrect rounding operand" } */
+  i = _mm_comi_round_sd (m128d, m128d, 4, 3); /* { dg-error "incorrect rounding operand" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/testround-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/testround-2.c
new file mode 100644
index 000000000..7236bfb9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/testround-2.c
@@ -0,0 +1,57 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O0 -mavx512f" } */
+
+#include <x86intrin.h>
+
+long long l;
+unsigned long long ul;
+__m128d m128d;
+__m128  m128;
+
+void
+test_round_64 (void)
+{
+  m128d = _mm_cvt_roundu64_sd (m128d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_cvt_roundi64_sd (m128d, 4, 7); /* { dg-error "incorrect rounding operand" } */
+
+  m128 = _mm_cvt_roundu64_ss (m128, 4, 7); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_cvt_roundi64_ss (m128, 4, 7); /* { dg-error "incorrect rounding operand" } */
+
+  ul = _mm_cvt_roundss_u64 (m128, 7); /* { dg-error "incorrect rounding operand" } */
+  l = _mm_cvt_roundss_i64 (m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  ul = _mm_cvt_roundsd_u64 (m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  l = _mm_cvt_roundsd_i64 (m128d, 7); /* { dg-error "incorrect rounding operand" } */
+
+  ul = _mm_cvtt_roundss_u64 (m128, 7); /* { dg-error "incorrect rounding operand" } */
+  l = _mm_cvtt_roundss_i64 (m128, 7); /* { dg-error "incorrect rounding operand" } */
+
+  ul = _mm_cvtt_roundsd_u64 (m128d, 7); /* { dg-error "incorrect rounding operand" } */
+  l = _mm_cvtt_roundsd_i64 (m128d, 7); /* { dg-error "incorrect rounding operand" } */
+}
+
+void
+test_round_sae_64 (void)
+{
+  m128d = _mm_cvt_roundu64_sd (m128d, 4, 5); /* { dg-error "incorrect rounding operand" } */
+  m128d = _mm_cvt_roundi64_sd (m128d, 4, 5); /* { dg-error "incorrect rounding operand" } */
+
+  m128 = _mm_cvt_roundu64_ss (m128, 4, 5); /* { dg-error "incorrect rounding operand" } */
+  m128 = _mm_cvt_roundi64_ss (m128, 4, 5); /* { dg-error "incorrect rounding operand" } */
+
+  ul = _mm_cvt_roundss_u64 (m128, 5); /* { dg-error "incorrect rounding operand" } */
+  l = _mm_cvt_roundss_i64 (m128, 5); /* { dg-error "incorrect rounding operand" } */
+
+  ul = _mm_cvt_roundsd_u64 (m128d, 5); /* { dg-error "incorrect rounding operand" } */
+  l = _mm_cvt_roundsd_i64 (m128d, 5); /* { dg-error "incorrect rounding operand" } */
+}
+
+void
+test_sae_only_64 (void)
+{
+  ul = _mm_cvtt_roundss_u64 (m128, 3); /* { dg-error "incorrect rounding operand" } */
+  l = _mm_cvtt_roundss_i64 (m128, 3); /* { dg-error "incorrect rounding operand" } */
+
+  ul = _mm_cvtt_roundsd_u64 (m128d, 3); /* { dg-error "incorrect rounding operand" } */
+  l = _mm_cvtt_roundsd_i64 (m128d, 3); /* { dg-error "incorrect rounding operand" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-1.c
new file mode 100644
index 000000000..eebd84362
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+__attribute__((noinline))
+test (unsigned int x, unsigned int y, unsigned int q, unsigned int r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+int
+main ()
+{
+  test (7, 6, 1, 1);
+  test (255, 254, 1, 1);
+  test (256, 254, 1, 2);
+  test (256, 256, 1, 0);
+  test (254, 256, 0, 254);
+  test (254, 255, 0, 254);
+  test (254, 1, 254, 0);
+  test (255, 2, 127, 1);
+  test (1, 256, 0, 1);
+  test (0x80000000, 0x7fffffff, 1, 1);
+  test (0x7fffffff, 0x80000000, 0, 0x7fffffff);
+  test (0x80000000, 0x80000003, 0, 0x80000000);
+  test (0xfffffffd, 0xfffffffe, 0, 0xfffffffd);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-2.c
new file mode 100644
index 000000000..2bba8f3c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+unsigned int
+foo (unsigned int x, unsigned int y)
+{
+   return x / y;
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "divl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-3.c
new file mode 100644
index 000000000..f2ac4e5da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+unsigned int
+foo (unsigned int x, unsigned int y)
+{
+   return x % y;
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "divl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-4.c
new file mode 100644
index 000000000..14dd87c17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+test (unsigned int x, unsigned int y, unsigned int q, unsigned int r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "divl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-4a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-4a.c
new file mode 100644
index 000000000..f1ff38909
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-4a.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+test (unsigned int x, unsigned int y, unsigned int q, unsigned int r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+/* { dg-final { scan-assembler-not "divb" } } */
+/* { dg-final { scan-assembler-times "divl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-5.c
new file mode 100644
index 000000000..7c31a0a9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void foo (unsigned int, unsigned int, unsigned int,
+		 unsigned int, unsigned int, unsigned int);
+
+void
+bar (unsigned int x, unsigned int y)
+{
+  foo (0, 0, 0, 0, x / y, x % y);
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "divl" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-6.c
new file mode 100644
index 000000000..d77417178
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-6.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+__attribute__((noinline))
+test (unsigned long long x, unsigned long long y,
+      unsigned long long q, unsigned long long r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+int
+main ()
+{
+  test (7, 6, 1, 1);
+  test (255, 254, 1, 1);
+  test (256, 254, 1, 2);
+  test (256, 256, 1, 0);
+  test (254, 256, 0, 254);
+  test (254, 255, 0, 254);
+  test (254, 1, 254, 0);
+  test (255, 2, 127, 1);
+  test (1, 256, 0, 1);
+  test (0x80000000, 0x7fffffff, 1, 1);
+  test (0x7fffffff, 0x80000000, 0, 0x7fffffff);
+  test (0x80000000, 0x80000003, 0, 0x80000000);
+  test (0xfffffffd, 0xfffffffe, 0, 0xfffffffd);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-7.c
new file mode 100644
index 000000000..4a68a75f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-7.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void abort (void);
+
+void
+test (unsigned long long x, unsigned long long y,
+      unsigned long long q, unsigned long long r)
+{
+  if ((x / y) != q || (x % y) != r)
+    abort ();
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "divq" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-8.c
new file mode 100644
index 000000000..bef496490
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/udivmod-8.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -m8bit-idiv" } */
+
+extern void foo (unsigned long long, unsigned long long,
+		 unsigned long long, unsigned long long,
+		 unsigned long long, unsigned long long);
+
+void
+bar (unsigned long long x, unsigned long long y)
+{
+  foo (0, 0, 0, 0, x / y, x % y);
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-times "divq" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-1.c
new file mode 100644
index 000000000..54edf139d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=atom" } */
+
+unsigned char
+foo (unsigned char x, unsigned char y)
+{
+  return x % y;
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-not "divw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-2.c
new file mode 100644
index 000000000..6fe738468
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=atom" } */
+
+extern unsigned char z;
+
+unsigned char
+foo (unsigned char x, unsigned char y)
+{
+  z = x/y;
+  return x % y;
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-not "divw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-3.c
new file mode 100644
index 000000000..7123bc9f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/umod-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=atom" } */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned char cx = 7;
+
+int
+main ()
+{
+  unsigned char cy;
+  
+  cy = cx / 6; if (cy != 1) abort ();
+  cy = cx % 6; if (cy != 1) abort ();
+
+  exit(0);
+}
+
+/* { dg-final { scan-assembler-times "divb" 1 } } */
+/* { dg-final { scan-assembler-not "divw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/unordcmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/unordcmp-1.c
new file mode 100644
index 000000000..49d4b8e07
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/unordcmp-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-final { scan-assembler "cmpunordss" } } */
+/* { dg-final { scan-assembler "cmpunordps" } } */
+/* { dg-final { scan-assembler "cmpunordsd" } } */
+/* { dg-final { scan-assembler "cmpunordpd" } } */
+/* { dg-final { scan-assembler-not "cmpordss" } } */
+/* { dg-final { scan-assembler-not "cmpordps" } } */
+/* { dg-final { scan-assembler-not "cmpordsd" } } */
+/* { dg-final { scan-assembler-not "cmpordpd" } } */
+
+#include <emmintrin.h>
+
+__m128
+f1 (__m128 x, __m128 y)
+{
+  return _mm_cmpunord_ss (x, y);
+}
+
+__m128
+f2 (__m128 x, __m128 y)
+{
+  return _mm_cmpunord_ps (x, y);
+}
+
+__m128d
+f3 (__m128d x, __m128d y)
+{
+  return _mm_cmpunord_sd (x, y);
+}
+
+__m128d
+f4 (__m128d x, __m128d y)
+{
+  return _mm_cmpunord_pd (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/unroll-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/unroll-1.c
new file mode 100644
index 000000000..cc8132e20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/unroll-1.c
@@ -0,0 +1,18 @@
+/* PR optimization/8599 */
+/* { dg-do run } */
+/* { dg-require-effective-target ia32 } */
+/* { dg-options "-mtune=k6 -O2 -funroll-loops" } */
+
+extern void exit (int);
+
+void *array[4];
+
+int main ()
+{
+  int i;
+ 
+  for (i = 0; i < 4; i++)
+    array[i] = 0;
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-1.c
new file mode 100644
index 000000000..a2db4b9f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-1.c
@@ -0,0 +1,34 @@
+/* PR middle-end/36858 */
+/* { dg-do run } */
+/* { dg-options "-w" { target { ! { ia32 } } } } */
+/* { dg-options "-w" { target { llp64 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ia32 } } } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+#include <stdarg.h>
+#include <emmintrin.h>
+
+int
+__attribute__((noinline))
+test (int a, ...)
+{
+  return a;
+}
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+
+int
+__attribute__((noinline))
+foo (void)
+{
+  return test (1, n1);
+}
+
+static void
+__attribute__((noinline))
+sse2_test (void)
+{
+  if (foo () != 1)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-10.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-10.c
new file mode 100644
index 000000000..053649877
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-10.c
@@ -0,0 +1,112 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "avx-check.h"
+
+struct m256d
+{
+  __m256d  v;
+};
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+struct m256d n2 = { { -93.83, 893.318, 3994.3, -39484.0 } };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+struct m256d n8 = { { -123.3, 2.3, 3.4, -10.03 } };
+__m128 n9 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n10 = { 1233, -100 };
+int n11 = 407;
+double n12 = 304.9;
+__m128i n13 = { 233, -110 };
+__m256i n14 = { -1233, 23, 34, -1003 };
+__m128i n15 = { -393, -180 };
+__m128d n16 = { 73.0, 63.18 };
+__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 };
+__m128 n18 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+struct m256d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+struct m256d e8;
+__m128 e9;
+__m128i e10;
+int e11;
+double e12;
+__m128i e13;
+__m256i e14;
+__m128i e15;
+__m128d e16;
+__m256 e17;
+__m128 e18;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, struct m256d);
+  e9 = va_arg (va_arglist, __m128);
+  e10 = va_arg (va_arglist, __m128i);
+  e11 = va_arg (va_arglist, int);
+  e12 = va_arg (va_arglist, double);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m256i);
+  e15 = va_arg (va_arglist, __m128i);
+  e16 = va_arg (va_arglist, __m128d);
+  e17 = va_arg (va_arglist, __m256);
+  e18 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+__attribute__((noinline))
+test (__m128 a1, struct m256d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+static void
+avx_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	n13, n14, n15, n16, n17, n18);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0);
+  assert (n11 == e11);
+  assert (n12 == e12);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+  assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0);
+  assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0);
+  assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-2.c
new file mode 100644
index 000000000..bd5ad5446
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-2.c
@@ -0,0 +1,42 @@
+/* PR middle-end/36859 */
+/* { dg-do run } */
+/* { dg-options "-w" { target { ! { ia32 } } } } */
+/* { dg-options "-w" { target { llp64 } } } */
+/* { dg-options "-w -msse2 -mpreferred-stack-boundary=2" { target { ia32 } } } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-check.h"
+#include <stdarg.h>
+#include <emmintrin.h>
+
+__m128
+__attribute__((noinline))
+test (int a, ...)
+{
+  __m128 x;
+  va_list va_arglist;
+
+  va_start (va_arglist, a);
+  x = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+  return x;
+}
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+
+int
+__attribute__((noinline))
+foo (void)
+{
+  __m128 x = test (1, n1);
+  if (__builtin_memcmp (&x, &n1, sizeof (x)) != 0)
+    abort ();
+  return 0;
+}
+
+static void
+__attribute__((noinline))
+sse2_test (void)
+{
+  foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-3.c
new file mode 100644
index 000000000..3bfc3f14c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-3.c
@@ -0,0 +1,86 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "sse2-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m128d n2 = { -93.83, 893.318 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+__m128 n8 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n9 = { 1233, -100 };
+int n10 = 407;
+double n11 = 304.9;
+__m128i n12 = { 233, -110 };
+__m128i n13 = { -393, -180 };
+__m128d n14 = { 73.0, 63.18 };
+__m128 n15 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+__m128d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+__m128 e8;
+__m128i e9;
+int e10;
+double e11;
+__m128i e12;
+__m128i e13;
+__m128d e14;
+__m128 e15;
+
+static void
+__attribute__((noinline))
+test (__m128 a1, __m128d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, __m128);
+  e9 = va_arg (va_arglist, __m128i);
+  e10 = va_arg (va_arglist, int);
+  e11 = va_arg (va_arglist, double);
+  e12 = va_arg (va_arglist, __m128i);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m128d);
+  e15 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+sse2_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (n10 == e10);
+  assert (n11 == e11);
+  assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-4.c
new file mode 100644
index 000000000..8034dcadb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-4.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "sse2-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m128d n2 = { -93.83, 893.318 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+__m128 n8 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n9 = { 1233, -100 };
+int n10 = 407;
+double n11 = 304.9;
+__m128i n12 = { 233, -110 };
+__m128i n13 = { -393, -180 };
+__m128d n14 = { 73.0, 63.18 };
+__m128 n15 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+__m128d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+__m128 e8;
+__m128i e9;
+int e10;
+double e11;
+__m128i e12;
+__m128i e13;
+__m128d e14;
+__m128 e15;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, __m128);
+  e9 = va_arg (va_arglist, __m128i);
+  e10 = va_arg (va_arglist, int);
+  e11 = va_arg (va_arglist, double);
+  e12 = va_arg (va_arglist, __m128i);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m128d);
+  e15 = va_arg (va_arglist, __m128);
+}
+
+static void
+__attribute__((noinline))
+test (__m128 a1, __m128d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+static void
+sse2_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (n10 == e10);
+  assert (n11 == e11);
+  assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-5.c
new file mode 100644
index 000000000..03ff60cd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-5.c
@@ -0,0 +1,99 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "avx-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m256d n2 = { -93.83, 893.318, 3994.3, -39484.0 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+__m256d n8 = { -123.3, 2.3, 3.4, -10.03 };
+__m128 n9 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n10 = { 1233, -100 };
+int n11 = 407;
+double n12 = 304.9;
+__m128i n13 = { 233, -110 };
+__m256i n14 = { -1233, 23, 34, -1003 };
+__m128i n15 = { -393, -180 };
+__m128d n16 = { 73.0, 63.18 };
+__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 };
+__m128 n18 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+__m256d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+__m256d e8;
+__m128 e9;
+__m128i e10;
+int e11;
+double e12;
+__m128i e13;
+__m256i e14;
+__m128i e15;
+__m128d e16;
+__m256 e17;
+__m128 e18;
+
+static void
+__attribute__((noinline))
+test (__m128 a1, __m256d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, __m256d);
+  e9 = va_arg (va_arglist, __m128);
+  e10 = va_arg (va_arglist, __m128i);
+  e11 = va_arg (va_arglist, int);
+  e12 = va_arg (va_arglist, double);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m256i);
+  e15 = va_arg (va_arglist, __m128i);
+  e16 = va_arg (va_arglist, __m128d);
+  e17 = va_arg (va_arglist, __m256);
+  e18 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+avx_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	n13, n14, n15, n16, n17, n18);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0);
+  assert (n11 == e11);
+  assert (n12 == e12);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+  assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0);
+  assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0);
+  assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-6.c
new file mode 100644
index 000000000..5c645c41d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-6.c
@@ -0,0 +1,107 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "avx-check.h"
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+__m256d n2 = { -93.83, 893.318, 3994.3, -39484.0 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+__m256d n8 = { -123.3, 2.3, 3.4, -10.03 };
+__m128 n9 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n10 = { 1233, -100 };
+int n11 = 407;
+double n12 = 304.9;
+__m128i n13 = { 233, -110 };
+__m256i n14 = { -1233, 23, 34, -1003 };
+__m128i n15 = { -393, -180 };
+__m128d n16 = { 73.0, 63.18 };
+__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 };
+__m128 n18 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+__m256d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+__m256d e8;
+__m128 e9;
+__m128i e10;
+int e11;
+double e12;
+__m128i e13;
+__m256i e14;
+__m128i e15;
+__m128d e16;
+__m256 e17;
+__m128 e18;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, __m256d);
+  e9 = va_arg (va_arglist, __m128);
+  e10 = va_arg (va_arglist, __m128i);
+  e11 = va_arg (va_arglist, int);
+  e12 = va_arg (va_arglist, double);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m256i);
+  e15 = va_arg (va_arglist, __m128i);
+  e16 = va_arg (va_arglist, __m128d);
+  e17 = va_arg (va_arglist, __m256);
+  e18 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+__attribute__((noinline))
+test (__m128 a1, __m256d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+static void
+avx_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	n13, n14, n15, n16, n17, n18);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0);
+  assert (n11 == e11);
+  assert (n12 == e12);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+  assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0);
+  assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0);
+  assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-7.c
new file mode 100644
index 000000000..0f10d6784
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-7.c
@@ -0,0 +1,91 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "sse2-check.h"
+
+struct m128
+{
+  __m128 v;
+};
+
+struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } };
+__m128d n2 = { -93.83, 893.318 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+struct m128 n8 = { { -123.3, 2.3, 3.4, -10.03 } };
+__m128i n9 = { 1233, -100 };
+int n10 = 407;
+double n11 = 304.9;
+__m128i n12 = { 233, -110 };
+__m128i n13 = { -393, -180 };
+__m128d n14 = { 73.0, 63.18 };
+struct m128 n15 = { { -183.3, 22.3, 13.4, -19.03 } };
+
+struct m128 e1;
+__m128d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+struct m128 e8;
+__m128i e9;
+int e10;
+double e11;
+__m128i e12;
+__m128i e13;
+__m128d e14;
+struct m128 e15;
+
+static void
+__attribute__((noinline))
+test (struct m128 a1, __m128d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, struct m128);
+  e9 = va_arg (va_arglist, __m128i);
+  e10 = va_arg (va_arglist, int);
+  e11 = va_arg (va_arglist, double);
+  e12 = va_arg (va_arglist, __m128i);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m128d);
+  e15 = va_arg (va_arglist, struct m128);
+  va_end (va_arglist);
+}
+
+static void
+sse2_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (n10 == e10);
+  assert (n11 == e11);
+  assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-8.c
new file mode 100644
index 000000000..5c5a0b4a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-8.c
@@ -0,0 +1,98 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "sse2-check.h"
+
+struct m128
+{
+  __m128 v;
+};
+
+struct m128 n1 = { { -283.3, -23.3, 213.4, 1119.03 } };
+__m128d n2 = { -93.83, 893.318 };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+struct m128 n8 = { { -123.3, 2.3, 3.4, -10.03 } };
+__m128i n9 = { 1233, -100 };
+int n10 = 407;
+double n11 = 304.9;
+__m128i n12 = { 233, -110 };
+__m128i n13 = { -393, -180 };
+__m128d n14 = { 73.0, 63.18 };
+struct m128 n15 = { { -183.3, 22.3, 13.4, -19.03 } };
+
+struct m128 e1;
+__m128d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+struct m128 e8;
+__m128i e9;
+int e10;
+double e11;
+__m128i e12;
+__m128i e13;
+__m128d e14;
+struct m128 e15;
+
+static void
+__attribute__((noinline))
+foo (va_list va_arglist)
+{
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, struct m128);
+  e9 = va_arg (va_arglist, __m128i);
+  e10 = va_arg (va_arglist, int);
+  e11 = va_arg (va_arglist, double);
+  e12 = va_arg (va_arglist, __m128i);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m128d);
+  e15 = va_arg (va_arglist, struct m128);
+}
+
+static void
+__attribute__((noinline))
+test (struct m128 a1, __m128d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  foo (va_arglist);
+  va_end (va_arglist);
+}
+
+static void
+sse2_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (n10 == e10);
+  assert (n11 == e11);
+  assert (__builtin_memcmp (&e12, &n12, sizeof (e12)) == 0);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-9.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-9.c
new file mode 100644
index 000000000..581abb178
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vararg-9.c
@@ -0,0 +1,104 @@
+/* { dg-do run } */
+/* { dg-require-effective-target avx } */
+/* { dg-options "-mavx" } */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include "avx-check.h"
+
+struct m256d
+{
+  __m256d  v;
+};
+
+__m128 n1 = { -283.3, -23.3, 213.4, 1119.03 };
+struct m256d n2 = { { -93.83, 893.318, 3994.3, -39484.0 } };
+__m128i n3 = { 893, -3180 } ;
+int n4 = 324;
+double n5 = 103.3;
+__m128i n6 = { -123, 2 };
+__m128d n7 = { -91.387, -8193.518 };
+struct m256d n8 = { { -123.3, 2.3, 3.4, -10.03 } };
+__m128 n9 = { -123.3, 2.3, 3.4, -10.03 };
+__m128i n10 = { 1233, -100 };
+int n11 = 407;
+double n12 = 304.9;
+__m128i n13 = { 233, -110 };
+__m256i n14 = { -1233, 23, 34, -1003 };
+__m128i n15 = { -393, -180 };
+__m128d n16 = { 73.0, 63.18 };
+__m256 n17 = { -183.3, -22.3, 13.9, -119.3, 483.1, 122.3, -33.4, -9.37 };
+__m128 n18 = { -183.3, 22.3, 13.4, -19.03 };
+
+__m128 e1;
+struct m256d e2;
+__m128i e3;
+int e4;
+double e5;
+__m128i e6;
+__m128d e7;
+struct m256d e8;
+__m128 e9;
+__m128i e10;
+int e11;
+double e12;
+__m128i e13;
+__m256i e14;
+__m128i e15;
+__m128d e16;
+__m256 e17;
+__m128 e18;
+
+static void
+__attribute__((noinline))
+test (__m128 a1, struct m256d a2, __m128i a3, ...)
+{
+  va_list va_arglist;
+
+  e1 = a1;
+  e2 = a2;
+  e3 = a3;
+  va_start (va_arglist, a3);
+  e4 = va_arg (va_arglist, int);
+  e5 = va_arg (va_arglist, double);
+  e6 = va_arg (va_arglist, __m128i);
+  e7 = va_arg (va_arglist, __m128d);
+  e8 = va_arg (va_arglist, struct m256d);
+  e9 = va_arg (va_arglist, __m128);
+  e10 = va_arg (va_arglist, __m128i);
+  e11 = va_arg (va_arglist, int);
+  e12 = va_arg (va_arglist, double);
+  e13 = va_arg (va_arglist, __m128i);
+  e14 = va_arg (va_arglist, __m256i);
+  e15 = va_arg (va_arglist, __m128i);
+  e16 = va_arg (va_arglist, __m128d);
+  e17 = va_arg (va_arglist, __m256);
+  e18 = va_arg (va_arglist, __m128);
+  va_end (va_arglist);
+}
+
+static void
+avx_test (void)
+{
+  test (n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,
+	n13, n14, n15, n16, n17, n18);
+  assert (__builtin_memcmp (&e1, &n1, sizeof (e1)) == 0);
+  assert (__builtin_memcmp (&e2, &n2, sizeof (e2)) == 0);
+  assert (__builtin_memcmp (&e3, &n3, sizeof (e3)) == 0);
+  assert (n4 == e4);
+  assert (n5 == e5);
+  assert (__builtin_memcmp (&e6, &n6, sizeof (e6)) == 0);
+  assert (__builtin_memcmp (&e7, &n7, sizeof (e7)) == 0);
+  assert (__builtin_memcmp (&e8, &n8, sizeof (e8)) == 0);
+  assert (__builtin_memcmp (&e9, &n9, sizeof (e9)) == 0);
+  assert (__builtin_memcmp (&e10, &n10, sizeof (e10)) == 0);
+  assert (n11 == e11);
+  assert (n12 == e12);
+  assert (__builtin_memcmp (&e13, &n13, sizeof (e13)) == 0);
+  assert (__builtin_memcmp (&e14, &n14, sizeof (e14)) == 0);
+  assert (__builtin_memcmp (&e15, &n15, sizeof (e15)) == 0);
+  assert (__builtin_memcmp (&e16, &n16, sizeof (e16)) == 0);
+  assert (__builtin_memcmp (&e17, &n17, sizeof (e17)) == 0);
+  assert (__builtin_memcmp (&e18, &n18, sizeof (e18)) == 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c
new file mode 100644
index 000000000..3b46671f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-require-effective-target f16c } */
+/* { dg-options "-O2 -mf16c" } */
+
+#include "f16c-check.h"
+
+static void
+f16c_test (void)
+{
+  union128i_w val; 
+  union128 res;
+  float exp[4];
+
+  exp[0] = 1;
+  exp[1] = -2;
+  exp[2] = -1;
+  exp[3] = 2;
+
+  val.a[0] = 0x3c00;
+  val.a[1] = 0xc000;
+  val.a[2] = 0xbc00;
+  val.a[3] = 0x4000;
+
+  res.x = _mm_cvtph_ps (val.x);
+
+  if (check_union128 (res, exp))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c
new file mode 100644
index 000000000..1523deaa1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target f16c } */
+/* { dg-options "-O2 -mf16c" } */
+
+#include "f16c-check.h"
+
+static void
+f16c_test (void)
+{
+  union256 res;
+  union128i_w val; 
+  float exp[8];
+
+  exp[0] = 1;
+  exp[1] = 2;
+  exp[2] = 4;
+  exp[3] = 8;
+  exp[4] = -1;
+  exp[5] = -2;
+  exp[6] = -4;
+  exp[7] = -8;
+
+  val.a[0] = 0x3c00;
+  val.a[1] = 0x4000;
+  val.a[2] = 0x4400;
+  val.a[3] = 0x4800;
+  val.a[4] = 0xbc00;
+  val.a[5] = 0xc000;
+  val.a[6] = 0xc400;
+  val.a[7] = 0xc800;
+
+  res.x = _mm256_cvtph_ps (val.x);
+
+  if (check_union256 (res, exp))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c
new file mode 100644
index 000000000..49b61f678
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtph2ps-3.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target f16c } */
+/* { dg-options "-O2 -mf16c" } */
+
+#include "f16c-check.h"
+
+static void
+f16c_test (void)
+{
+  unsigned short val = 0xc000;
+  float exp = -2;
+  float res;
+
+  res = _cvtsh_ss (val);
+
+  if (res != exp)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c
new file mode 100644
index 000000000..c114c98ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-require-effective-target f16c } */
+/* { dg-options "-O2 -mf16c" } */
+
+#include "f16c-check.h"
+
+static void
+f16c_test (void)
+{
+  union128 val;
+  union128i_w res; 
+  short exp[8];
+
+  val.a[0] = 1;
+  val.a[1] = -2;
+  val.a[2] = -1;
+  val.a[3] = 2;
+
+  exp[0] = 0x3c00;
+  exp[1] = 0xc000;
+  exp[2] = 0xbc00;
+  exp[3] = 0x4000;
+  exp[4] = 0;
+  exp[5] = 0;
+  exp[6] = 0;
+  exp[7] = 0;
+
+  res.x = _mm_cvtps_ph (val.x, 0);
+
+  if (check_union128i_w (res, exp))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c
new file mode 100644
index 000000000..57436ae86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-2.c
@@ -0,0 +1,36 @@
+/* { dg-do run } */
+/* { dg-require-effective-target f16c } */
+/* { dg-options "-O2 -mf16c" } */
+
+#include "f16c-check.h"
+
+static void
+f16c_test (void)
+{
+  union256 val;
+  union128i_w res; 
+  short exp[8];
+
+  val.a[0] = 1;
+  val.a[1] = 2;
+  val.a[2] = 4;
+  val.a[3] = 8;
+  val.a[4] = -1;
+  val.a[5] = -2;
+  val.a[6] = -4;
+  val.a[7] = -8;
+
+  exp[0] = 0x3c00;
+  exp[1] = 0x4000;
+  exp[2] = 0x4400;
+  exp[3] = 0x4800;
+  exp[4] = 0xbc00;
+  exp[5] = 0xc000;
+  exp[6] = 0xc400;
+  exp[7] = 0xc800;
+
+  res.x = _mm256_cvtps_ph (val.x, 0);
+
+  if (check_union128i_w (res, exp))
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c
new file mode 100644
index 000000000..3b7cb5c5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vcvtps2ph-3.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-require-effective-target f16c } */
+/* { dg-options "-O2 -mf16c" } */
+
+#include "f16c-check.h"
+
+static void
+f16c_test (void)
+{
+  float val = -2;
+  unsigned short exp = 0xc000;
+  unsigned short res;
+
+  res = _cvtss_sh (val, 0);
+
+  if (res != exp)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-1.c
new file mode 100644
index 000000000..17e295985
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -msse2 -mno-sse4" } */
+
+#define vector __attribute__((vector_size(16)))
+
+float a;
+vector float f1(void) { return (vector float){ a, 0.0, 0.0, 0.0}; }
+vector float f2(void) { return (vector float){ 0.0, a, 0.0, 0.0}; }
+vector float f3(void) { return (vector float){ 0.0, 0.0, a, 0.0}; }
+vector float f4(void) { return (vector float){ 0.0, 0.0, 0.0, a}; }
+/* { dg-final { scan-assembler-not "movaps" } } */
+/* { dg-final { scan-assembler-not "xor" } } */
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-2.c
new file mode 100644
index 000000000..d7b910062
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8 -msse2 -mno-sse4" } */
+
+#define vector __attribute__((vector_size(16)))
+
+int a;
+vector int f1(void) { return (vector int){ a, 0, 0, 0}; }
+vector int f2(void) { return (vector int){ 0, a, 0, 0}; }
+vector int f3(void) { return (vector int){ 0, 0, a, 0}; }
+vector int f4(void) { return (vector int){ 0, 0, 0, a}; }
+/* { dg-final { scan-assembler-not "movaps" } } */
+/* { dg-final { scan-assembler-not "xor" } } */
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-3.c
new file mode 100644
index 000000000..062fb1ed1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#define vector __attribute__((vector_size(16)))
+
+char a;
+vector char f(void) { return (vector char){ a, a, a, a, a, a, a, a,
+					    a, a, a, a, a, a, a, a }; }
+/* { dg-final { scan-assembler-not "sall" } } */
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-4.c
new file mode 100644
index 000000000..2dfa29c49
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-4.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#define vector __attribute__((vector_size(16)))
+
+short a;
+vector short f(void) { return (vector short){ a, a, a, a, a, a, a, a }; }
+/* { dg-final { scan-assembler-not "sall" } } */
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-5.c
new file mode 100644
index 000000000..dcf8b9206
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-5.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#define vector __attribute__((vector_size(16)))
+
+float a, b;
+vector float f1(void) { return (vector float){ 0.0, 0.0, a, a}; }
+vector float f2(void) { return (vector float){ a, a, 0.0, 0.0}; }
+vector float f3(void) { return (vector float){ 0.0, a, 0.0, a}; }
+vector float f4(void) { return (vector float){ a, 0.0, a, 0.0}; }
+
+vector float f5(void) { return (vector float){ 1.0, 1.0, a, a}; }
+vector float f6(void) { return (vector float){ a, a, 1.0, 1.0}; }
+vector float f7(void) { return (vector float){ 1.0, a, 1.0, a}; }
+vector float f8(void) { return (vector float){ a, 1.0, a, 1.0}; }
+
+vector float fa(void) { return (vector float){ 1.0, 1.0, 0.0, 0.0}; }
+vector float fb(void) { return (vector float){ 1.0, 0.0, 1.0, 0.0}; }
+vector float fc(void) { return (vector float){ 0.0, 1.0, 0.0, 1.0}; }
+
+vector float fA(void) { return (vector float){ a, a, b, b}; }
+vector float fB(void) { return (vector float){ a, b, a, b}; }
+vector float fC(void) { return (vector float){ a, a, a, a}; }
+
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-6.c
new file mode 100644
index 000000000..6817922d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vecinit-6.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2" } */
+
+#define vector __attribute__((vector_size(16)))
+
+int a, b;
+vector int f1(void) { return (vector int){ 0, 0, a, a}; }
+vector int f2(void) { return (vector int){ a, a, 0, 0}; }
+vector int f3(void) { return (vector int){ 0, a, 0, a}; }
+vector int f4(void) { return (vector int){ a, 0, a, 0}; }
+
+vector int f5(void) { return (vector int){ 1, 1, a, a}; }
+vector int f6(void) { return (vector int){ a, a, 1, 1}; }
+vector int f7(void) { return (vector int){ 1, a, 1, a}; }
+vector int f8(void) { return (vector int){ a, 1, a, 1}; }
+
+vector int fa(void) { return (vector int){ 1, 1, 0, 0}; }
+vector int fb(void) { return (vector int){ 1, 0, 1, 0}; }
+vector int fc(void) { return (vector int){ 0, 1, 0, 1}; }
+
+vector int fA(void) { return (vector int){ a, a, b, b}; }
+vector int fB(void) { return (vector int){ a, b, a, b}; }
+vector int fC(void) { return (vector int){ a, a, a, a}; }
+
+/* { dg-final { scan-assembler-not "%mm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s16.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s16.c
new file mode 100644
index 000000000..191ae3434
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s16.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2 -mno-sse3 -fdump-tree-vect-details" } */
+
+
+void test (short* a, short* b)
+{
+  int i;
+  for (i = 0; i < 10000; ++i)
+    a[i] = abs (b[i]);
+}
+
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s32.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s32.c
new file mode 100644
index 000000000..575e8efe0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s32.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2 -mno-sse3 -fdump-tree-vect-details" } */
+
+
+void test (int* a, int* b)
+{
+  int i;
+  for (i = 0; i < 10000; ++i)
+    a[i] = abs (b[i]);
+}
+
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s8.c
new file mode 100644
index 000000000..3f3f3facb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-abs-s8.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2 -mno-sse3 -fdump-tree-vect-details" } */
+
+
+void test (char* a, char* b)
+{
+  int i;
+  for (i = 0; i < 10000; ++i)
+    a[i] = abs (b[i]);
+}
+
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-args.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-args.c
new file mode 100644
index 000000000..fc458896e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-args.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-w -Wno-psabi" } */
+
+/* SSE1 and SSE2 modes.  */
+typedef unsigned char V16QImode __attribute__((vector_size(16)));
+typedef unsigned short V8HImode __attribute__((vector_size(16)));
+typedef unsigned int V4SImode __attribute__((vector_size(16)));
+typedef unsigned long long V2DImode __attribute__((vector_size(16)));
+typedef float V4SFmode __attribute__((vector_size(16)));
+typedef double V2DFmode __attribute__((vector_size(16)));
+
+/* MMX and 3DNOW modes.  */
+typedef unsigned char V8QImode __attribute__((vector_size(8)));
+typedef unsigned short V4HImode __attribute__((vector_size(8)));
+typedef unsigned int V2SImode __attribute__((vector_size(8)));
+typedef float V2SFmode __attribute__((vector_size(8)));
+
+/* Test argument loading and unloading of each.  */
+#define TEST(TYPE)					\
+extern TYPE data_##TYPE;				\
+void r_##TYPE (TYPE x) { data_##TYPE = x; }		\
+void s_##TYPE (void) { r_##TYPE (data_##TYPE); }
+
+TEST(V16QImode)
+TEST(V8HImode)
+TEST(V4SImode)
+TEST(V2DImode)
+TEST(V4SFmode)
+TEST(V2DFmode)
+TEST(V8QImode)
+TEST(V4HImode)
+TEST(V2SImode)
+TEST(V2SFmode)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-cond-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-cond-1.c
new file mode 100644
index 000000000..12ae77103
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-cond-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -mavx2" { target avx2 } } */
+
+int a[1024];
+
+int
+foo (int *p)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    {
+      int t;
+      if (a[i] < 30)
+	t = *p;
+      else
+	t = a[i] + 12;
+      a[i] = t;
+    }
+}
+
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-div-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-div-1.c
new file mode 100644
index 000000000..b3eed19c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-div-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile { target sse2 } } */
+/* { dg-options "-O2 -ftree-vectorize -fno-common -msse2" } */
+
+unsigned short b[1024] = { 0 };
+int a[1024] = { 0 };
+
+int
+f1 (int x)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    a[i] = (b[i] + 7) / 15;
+}
+
+int
+f2 (int x)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    a[i] = (b[i] + 7) % 15;
+}
+
+int
+f3 (int x)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    a[i] = (b[i] - 66000) / 15;
+}
+
+int
+f4 (int x)
+{
+  int i;
+  for (i = 0; i < 1024; i++)
+    a[i] = (b[i] - 66000) % 15;
+}
+
+/* In f1 and f2, VRP can prove the first operand of division or modulo
+   is always non-negative, so there is no need to do >> 31 shift
+   etc. to check if it is.  And in f3 and f4, VRP can prove it is always
+   negative.  */
+/* { dg-final { scan-assembler-not "psrad\[^\n\r\]*\\\$31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-1.c
new file mode 100644
index 000000000..d96d6399c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=core2" } } */
+/* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -march=core2 -fdump-tree-vect-stats" } */
+
+extern void abort (void);
+
+#ifndef STATIC
+#define STATIC
+#endif
+
+#define N 16
+ 
+double cb[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+double ca[N];
+
+STATIC void
+__attribute__ ((noinline))
+sse2_test (void)
+{  
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      ca[i] = cb[i];
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (ca[i] != cb[i])
+        abort ();
+    }
+}
+
+/* { dg-final { scan-tree-dump-times "Vectorized loops: 1" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-1a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-1a.c
new file mode 100644
index 000000000..a62c93903
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-1a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -msse2 -mtune=core2" } */
+
+#define STATIC static
+
+#include "vect-double-1.c"
+#include "sse2-check.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-2.c
new file mode 100644
index 000000000..a76dcb46c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -msse2 -mtune=atom -fdump-tree-vect-stats" } */
+
+extern void abort (void);
+
+#ifndef STATIC
+#define STATIC
+#endif
+
+#define N 16
+ 
+double cb[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+double ca[N];
+
+STATIC void
+__attribute__ ((noinline))
+sse2_test (void)
+{  
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      ca[i] = cb[i];
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (ca[i] != cb[i])
+        abort ();
+    }
+}
+
+/* { dg-final { scan-tree-dump-not "vectorized 1 loops" "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-2a.c
new file mode 100644
index 000000000..94f806275
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-double-2a.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse2 } */
+/* { dg-options "-O2 -ftree-vectorize -mfpmath=sse -msse2 -mtune=atom" } */
+
+#define STATIC static
+
+#include "vect-double-2.c"
+#include "sse2-check.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-rebuild.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-rebuild.c
new file mode 100644
index 000000000..570967f6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-rebuild.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mavx -fno-tree-forwprop" } */
+
+typedef double v2df __attribute__ ((__vector_size__ (16)));
+typedef double v4df __attribute__ ((__vector_size__ (32)));
+
+v2df f1 (v2df x)
+{
+  v2df xx = { x[0], x[1] };
+  return xx;
+}
+
+v4df f2 (v4df x)
+{
+  v4df xx = { x[0], x[1], x[2], x[3] };
+  return xx;
+}
+
+v2df g (v2df x)
+{
+  v2df xx = { x[1], x[0] };
+  return xx;
+}
+
+v2df h (v4df x)
+{
+  v2df xx = { x[2], x[3] };
+  return xx;
+}
+
+/* { dg-final { scan-assembler-not "unpck" } } */
+/* { dg-final { scan-assembler-times "\tv?permilpd\[ \t\]" 1 } } */
+/* { dg-final { scan-assembler-times "\tv?extractf128\[ \t\]" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-sizes-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-sizes-1.c
new file mode 100644
index 000000000..6ca38d2fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect-sizes-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -ffast-math -mavx -mtune=generic -fno-common" } */
+
+double a[1024];
+
+void dependence_distance_4 (void)
+{
+  int i;
+  for (i = 0; i < 1020; ++i)
+    a[i + 4] = a[i] + a[i + 4];
+}
+
+/* { dg-final { scan-assembler "vmovapd\[ \\t\]+\[^\n\]*%ymm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vect8-ret.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect8-ret.c
new file mode 100644
index 000000000..513369d0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vect8-ret.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mmmx" { target i?86-*-solaris2.9 *-*-vxworks* } } */
+/* { dg-options "-mmmx -mvect8-ret-in-mem" } */
+
+#include <mmintrin.h>
+
+__m64
+vecret (__m64 vect)
+{
+  return vect;
+}
+
+/* { dg-final { scan-assembler-times "movq" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize1.c
new file mode 100644
index 000000000..f673e44c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize1.c
@@ -0,0 +1,20 @@
+/* PR middle-end/28915 */
+/* { dg-options "-msse -O2 -ftree-vectorize -fdump-tree-vect" } */
+/* { dg-require-effective-target sse } */
+
+extern char lanip[3][40];
+typedef struct
+{
+  char *t[8];
+}tx_typ;
+
+int set_names (void)
+{
+  static tx_typ tt1;
+  int ln;
+  for (ln = 0; ln < 8; ln++)
+      tt1.t[ln] = lanip[1];
+}
+
+/* { dg-final { scan-tree-dump "vect_cst" "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize2.c
new file mode 100644
index 000000000..427e2d401
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mfpmath=sse -mtune=generic" } */
+
+double a[256];
+int b[256];
+unsigned short c[256];
+
+extern long lrint (double);
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    b[i] = lrint (a[i]);
+}
+
+void bar(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    {
+      b[i] = lrint (a[i]);
+      c[i] += c[i];
+    }
+}
+
+/* { dg-final { scan-assembler "cvtpd2dq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize3.c
new file mode 100644
index 000000000..2947acbaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize3.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mfpmath=sse" } */
+
+float a[256];
+int b[256];
+unsigned short c[256];
+
+extern long lrintf (float);
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    b[i] = lrintf (a[i]);
+}
+
+void bar(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    {
+      b[i] = lrintf (a[i]);
+      c[i] += c[i];
+    }
+}
+
+/* { dg-final { scan-assembler "cvtps2dq" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize4-avx.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize4-avx.c
new file mode 100644
index 000000000..33e991893
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize4-avx.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -mavx -mtune=generic" } */
+
+
+extern double sqrt (double __x);
+calc_freq (int *dest)
+{
+  float tmp_out[257];
+  int i;
+  for (i = 0; i < 256; i++)
+    dest[i] = sqrt (tmp_out[i]);
+}
+
+/* { dg-final { scan-assembler "vsqrtpd\[ \\t\]+\[^\n\]*%ymm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize4.c
new file mode 100644
index 000000000..557d0a26e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize4.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -ffast-math -ftree-vectorize -msse2 -mtune=generic --param ggc-min-expand=0 --param ggc-min-heapsize=0" } */
+/* This test, tests two thing, we vectorize square root and also we don't crash due to a GC issue.  */
+
+
+extern double sqrt (double __x);
+calc_freq (int *dest)
+{
+  float tmp_out[257];
+  int i;
+  for (i = 0; i < 256; i++)
+    dest[i] = sqrt (tmp_out[i]);
+}
+
+/* { dg-final { scan-assembler "sqrtpd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize5.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize5.c
new file mode 100644
index 000000000..2065e5d15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize5.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -ftree-vectorize -mveclibabi=acml -ffast-math -mtune=generic" } */
+
+double x[256];
+
+extern double sin(double);
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    x[i] = sin(x[i]);
+}
+
+/* { dg-final { scan-assembler "__vrd2_sin" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize6.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize6.c
new file mode 100644
index 000000000..d299a1551
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize6.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -ftree-vectorize -mveclibabi=svml -ffast-math -mtune=generic" } */
+
+double x[256];
+
+extern double sin(double);
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    x[i] = sin(x[i]);
+}
+
+/* { dg-final { scan-assembler "vmldSin2" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize7.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize7.c
new file mode 100644
index 000000000..10b7ba278
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize7.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2" } */
+
+unsigned int a[256];
+float b[256];
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    b[i] = a[i];
+}
+
+/* { dg-final { scan-assembler "cvtdq2ps" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize8.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize8.c
new file mode 100644
index 000000000..a194bb088
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vectorize8.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-vectorize -msse2 -mtune=generic" } */
+
+unsigned int a[256];
+double b[256];
+
+void foo(void)
+{
+  int i;
+
+  for (i=0; i<256; ++i)
+    b[i] = a[i];
+}
+
+/* { dg-final { scan-assembler "cvtdq2pd" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-1.c
new file mode 100644
index 000000000..714314cee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-1.c
@@ -0,0 +1,14 @@
+/* PR optimization/11381 */
+/* Originator: <tobias@ringstrom.mine.nu> */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+/* Verify that the comparison is not optimized away. */
+
+void foo(volatile unsigned int *vaddr)
+{
+  while (*vaddr != *vaddr)
+    ;
+}
+
+/* { dg-final { scan-assembler "cmp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-2.c
new file mode 100644
index 000000000..f4e6fb124
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-2.c
@@ -0,0 +1,93 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-options "-O2" } */
+
+/* Check volatiles are written, read or not re-read consistently */
+
+
+/* simple assignments */
+
+extern int volatile obj_0;
+void test_0 (int data)
+{
+  /* should not reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_0(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_0(\\(%rip\\))?," } } */
+  obj_0 = data;
+}
+
+extern int volatile obj_1;
+int test_1 (int data)
+{
+  /* should not reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_1(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_1(\\(%rip\\))?," } } */
+  return obj_1 = data;
+}
+
+extern int volatile obj_2;
+int test_2 (void)
+{
+  /* should not reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_2(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_2(\\(%rip\\))?," } } */
+  return obj_2 = 0;
+}
+
+
+/* Assignments in compound exprs */
+
+extern int volatile obj_3;
+int test_3 (int data)
+{
+  /* should not reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_3(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_3(\\(%rip\\))?," } } */
+  return (obj_3 = data, 0);
+}
+
+extern int volatile obj_4;
+int test_4 (void)
+{
+  /* should not reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_4(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_4(\\(%rip\\))?," } } */
+  return (obj_4 = 0, 0);
+}
+extern int volatile obj_5;
+int test_5 (void)
+{
+  /* should reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_5(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler "movl\[ \t\]_?obj_5(\\(%rip\\))?," } } */
+  return (obj_5 = 0, obj_5);
+}
+
+/* Assignments in conditional exprs */
+
+extern int volatile obj_6;
+void test_6 (int data, int cond)
+{
+  /* should not reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_6(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_6(\\(%rip\\))?," } } */
+  cond ? obj_6 = data : 0;
+}
+
+extern int volatile obj_7;
+int test_7 (int data, int cond)
+{
+  /* should not reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_7(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_7(\\(%rip\\))?," } } */
+  return cond ? obj_7 = data : 0;
+}
+
+extern int volatile obj_8;
+int test_8 (int cond)
+{
+  /* should not reread obj */
+  /* { dg-final { scan-assembler "movl\[ \t\]\[^,\]+, _?obj_8(\\(%rip\\))?" } } */
+  /* { dg-final { scan-assembler-not "movl\[ \t\]_?obj_8(\\(%rip\\))?," } } */
+  return cond ? obj_8 = 0 : 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c
new file mode 100644
index 000000000..f11a8aff5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-bitfields-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fstrict-volatile-bitfields" } */
+
+typedef struct {
+  char a:1;
+  char b:7;
+  int c;
+} BitStruct;
+
+volatile BitStruct bits;
+
+int foo ()
+{
+  return bits.b;
+}
+
+/* { dg-final { scan-assembler "mov(b|zbl).*bits" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c
new file mode 100644
index 000000000..302625a19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/volatile-bitfields-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-strict-volatile-bitfields" } */
+
+typedef struct {
+  char a:1;
+  char b:7;
+  int c;
+} BitStruct;
+
+volatile BitStruct bits;
+
+int foo ()
+{
+  return bits.b;
+}
+
+/* { dg-final { scan-assembler "movl.*bits" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-2-2.inc b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-2-2.inc
new file mode 100644
index 000000000..ef66f6808
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-2-2.inc
@@ -0,0 +1,27 @@
+/* This file auto-generated with ./vperm.pl 2 2.  */
+
+void check0(void)
+{
+  TEST (0, 0)
+  TEST (1, 0)
+  TEST (2, 0)
+  TEST (3, 0)
+  TEST (0, 1)
+  TEST (1, 1)
+  TEST (2, 1)
+  TEST (3, 1)
+  TEST (0, 2)
+  TEST (1, 2)
+  TEST (2, 2)
+  TEST (3, 2)
+  TEST (0, 3)
+  TEST (1, 3)
+  TEST (2, 3)
+  TEST (3, 3)
+}
+
+void check(void)
+{
+  check0 ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-4-1.inc b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-4-1.inc
new file mode 100644
index 000000000..c04f1856f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-4-1.inc
@@ -0,0 +1,272 @@
+/* This file auto-generated with ./vperm.pl 4 1.  */
+
+void check0(void)
+{
+  TEST (0, 0, 0, 0)
+  TEST (1, 0, 0, 0)
+  TEST (2, 0, 0, 0)
+  TEST (3, 0, 0, 0)
+  TEST (0, 1, 0, 0)
+  TEST (1, 1, 0, 0)
+  TEST (2, 1, 0, 0)
+  TEST (3, 1, 0, 0)
+  TEST (0, 2, 0, 0)
+  TEST (1, 2, 0, 0)
+  TEST (2, 2, 0, 0)
+  TEST (3, 2, 0, 0)
+  TEST (0, 3, 0, 0)
+  TEST (1, 3, 0, 0)
+  TEST (2, 3, 0, 0)
+  TEST (3, 3, 0, 0)
+  TEST (0, 0, 1, 0)
+  TEST (1, 0, 1, 0)
+  TEST (2, 0, 1, 0)
+  TEST (3, 0, 1, 0)
+  TEST (0, 1, 1, 0)
+  TEST (1, 1, 1, 0)
+  TEST (2, 1, 1, 0)
+  TEST (3, 1, 1, 0)
+  TEST (0, 2, 1, 0)
+  TEST (1, 2, 1, 0)
+  TEST (2, 2, 1, 0)
+  TEST (3, 2, 1, 0)
+  TEST (0, 3, 1, 0)
+  TEST (1, 3, 1, 0)
+  TEST (2, 3, 1, 0)
+  TEST (3, 3, 1, 0)
+  TEST (0, 0, 2, 0)
+  TEST (1, 0, 2, 0)
+  TEST (2, 0, 2, 0)
+  TEST (3, 0, 2, 0)
+  TEST (0, 1, 2, 0)
+  TEST (1, 1, 2, 0)
+  TEST (2, 1, 2, 0)
+  TEST (3, 1, 2, 0)
+  TEST (0, 2, 2, 0)
+  TEST (1, 2, 2, 0)
+  TEST (2, 2, 2, 0)
+  TEST (3, 2, 2, 0)
+  TEST (0, 3, 2, 0)
+  TEST (1, 3, 2, 0)
+  TEST (2, 3, 2, 0)
+  TEST (3, 3, 2, 0)
+  TEST (0, 0, 3, 0)
+  TEST (1, 0, 3, 0)
+  TEST (2, 0, 3, 0)
+  TEST (3, 0, 3, 0)
+  TEST (0, 1, 3, 0)
+  TEST (1, 1, 3, 0)
+  TEST (2, 1, 3, 0)
+  TEST (3, 1, 3, 0)
+  TEST (0, 2, 3, 0)
+  TEST (1, 2, 3, 0)
+  TEST (2, 2, 3, 0)
+  TEST (3, 2, 3, 0)
+  TEST (0, 3, 3, 0)
+  TEST (1, 3, 3, 0)
+  TEST (2, 3, 3, 0)
+  TEST (3, 3, 3, 0)
+  TEST (0, 0, 0, 1)
+  TEST (1, 0, 0, 1)
+  TEST (2, 0, 0, 1)
+  TEST (3, 0, 0, 1)
+  TEST (0, 1, 0, 1)
+  TEST (1, 1, 0, 1)
+  TEST (2, 1, 0, 1)
+  TEST (3, 1, 0, 1)
+  TEST (0, 2, 0, 1)
+  TEST (1, 2, 0, 1)
+  TEST (2, 2, 0, 1)
+  TEST (3, 2, 0, 1)
+  TEST (0, 3, 0, 1)
+  TEST (1, 3, 0, 1)
+  TEST (2, 3, 0, 1)
+  TEST (3, 3, 0, 1)
+  TEST (0, 0, 1, 1)
+  TEST (1, 0, 1, 1)
+  TEST (2, 0, 1, 1)
+  TEST (3, 0, 1, 1)
+  TEST (0, 1, 1, 1)
+  TEST (1, 1, 1, 1)
+  TEST (2, 1, 1, 1)
+  TEST (3, 1, 1, 1)
+  TEST (0, 2, 1, 1)
+  TEST (1, 2, 1, 1)
+  TEST (2, 2, 1, 1)
+  TEST (3, 2, 1, 1)
+  TEST (0, 3, 1, 1)
+  TEST (1, 3, 1, 1)
+  TEST (2, 3, 1, 1)
+  TEST (3, 3, 1, 1)
+  TEST (0, 0, 2, 1)
+  TEST (1, 0, 2, 1)
+  TEST (2, 0, 2, 1)
+  TEST (3, 0, 2, 1)
+  TEST (0, 1, 2, 1)
+  TEST (1, 1, 2, 1)
+  TEST (2, 1, 2, 1)
+  TEST (3, 1, 2, 1)
+  TEST (0, 2, 2, 1)
+  TEST (1, 2, 2, 1)
+  TEST (2, 2, 2, 1)
+  TEST (3, 2, 2, 1)
+  TEST (0, 3, 2, 1)
+  TEST (1, 3, 2, 1)
+  TEST (2, 3, 2, 1)
+  TEST (3, 3, 2, 1)
+  TEST (0, 0, 3, 1)
+  TEST (1, 0, 3, 1)
+  TEST (2, 0, 3, 1)
+  TEST (3, 0, 3, 1)
+  TEST (0, 1, 3, 1)
+  TEST (1, 1, 3, 1)
+  TEST (2, 1, 3, 1)
+  TEST (3, 1, 3, 1)
+  TEST (0, 2, 3, 1)
+  TEST (1, 2, 3, 1)
+  TEST (2, 2, 3, 1)
+  TEST (3, 2, 3, 1)
+  TEST (0, 3, 3, 1)
+  TEST (1, 3, 3, 1)
+  TEST (2, 3, 3, 1)
+  TEST (3, 3, 3, 1)
+}
+
+void check1(void)
+{
+  TEST (0, 0, 0, 2)
+  TEST (1, 0, 0, 2)
+  TEST (2, 0, 0, 2)
+  TEST (3, 0, 0, 2)
+  TEST (0, 1, 0, 2)
+  TEST (1, 1, 0, 2)
+  TEST (2, 1, 0, 2)
+  TEST (3, 1, 0, 2)
+  TEST (0, 2, 0, 2)
+  TEST (1, 2, 0, 2)
+  TEST (2, 2, 0, 2)
+  TEST (3, 2, 0, 2)
+  TEST (0, 3, 0, 2)
+  TEST (1, 3, 0, 2)
+  TEST (2, 3, 0, 2)
+  TEST (3, 3, 0, 2)
+  TEST (0, 0, 1, 2)
+  TEST (1, 0, 1, 2)
+  TEST (2, 0, 1, 2)
+  TEST (3, 0, 1, 2)
+  TEST (0, 1, 1, 2)
+  TEST (1, 1, 1, 2)
+  TEST (2, 1, 1, 2)
+  TEST (3, 1, 1, 2)
+  TEST (0, 2, 1, 2)
+  TEST (1, 2, 1, 2)
+  TEST (2, 2, 1, 2)
+  TEST (3, 2, 1, 2)
+  TEST (0, 3, 1, 2)
+  TEST (1, 3, 1, 2)
+  TEST (2, 3, 1, 2)
+  TEST (3, 3, 1, 2)
+  TEST (0, 0, 2, 2)
+  TEST (1, 0, 2, 2)
+  TEST (2, 0, 2, 2)
+  TEST (3, 0, 2, 2)
+  TEST (0, 1, 2, 2)
+  TEST (1, 1, 2, 2)
+  TEST (2, 1, 2, 2)
+  TEST (3, 1, 2, 2)
+  TEST (0, 2, 2, 2)
+  TEST (1, 2, 2, 2)
+  TEST (2, 2, 2, 2)
+  TEST (3, 2, 2, 2)
+  TEST (0, 3, 2, 2)
+  TEST (1, 3, 2, 2)
+  TEST (2, 3, 2, 2)
+  TEST (3, 3, 2, 2)
+  TEST (0, 0, 3, 2)
+  TEST (1, 0, 3, 2)
+  TEST (2, 0, 3, 2)
+  TEST (3, 0, 3, 2)
+  TEST (0, 1, 3, 2)
+  TEST (1, 1, 3, 2)
+  TEST (2, 1, 3, 2)
+  TEST (3, 1, 3, 2)
+  TEST (0, 2, 3, 2)
+  TEST (1, 2, 3, 2)
+  TEST (2, 2, 3, 2)
+  TEST (3, 2, 3, 2)
+  TEST (0, 3, 3, 2)
+  TEST (1, 3, 3, 2)
+  TEST (2, 3, 3, 2)
+  TEST (3, 3, 3, 2)
+  TEST (0, 0, 0, 3)
+  TEST (1, 0, 0, 3)
+  TEST (2, 0, 0, 3)
+  TEST (3, 0, 0, 3)
+  TEST (0, 1, 0, 3)
+  TEST (1, 1, 0, 3)
+  TEST (2, 1, 0, 3)
+  TEST (3, 1, 0, 3)
+  TEST (0, 2, 0, 3)
+  TEST (1, 2, 0, 3)
+  TEST (2, 2, 0, 3)
+  TEST (3, 2, 0, 3)
+  TEST (0, 3, 0, 3)
+  TEST (1, 3, 0, 3)
+  TEST (2, 3, 0, 3)
+  TEST (3, 3, 0, 3)
+  TEST (0, 0, 1, 3)
+  TEST (1, 0, 1, 3)
+  TEST (2, 0, 1, 3)
+  TEST (3, 0, 1, 3)
+  TEST (0, 1, 1, 3)
+  TEST (1, 1, 1, 3)
+  TEST (2, 1, 1, 3)
+  TEST (3, 1, 1, 3)
+  TEST (0, 2, 1, 3)
+  TEST (1, 2, 1, 3)
+  TEST (2, 2, 1, 3)
+  TEST (3, 2, 1, 3)
+  TEST (0, 3, 1, 3)
+  TEST (1, 3, 1, 3)
+  TEST (2, 3, 1, 3)
+  TEST (3, 3, 1, 3)
+  TEST (0, 0, 2, 3)
+  TEST (1, 0, 2, 3)
+  TEST (2, 0, 2, 3)
+  TEST (3, 0, 2, 3)
+  TEST (0, 1, 2, 3)
+  TEST (1, 1, 2, 3)
+  TEST (2, 1, 2, 3)
+  TEST (3, 1, 2, 3)
+  TEST (0, 2, 2, 3)
+  TEST (1, 2, 2, 3)
+  TEST (2, 2, 2, 3)
+  TEST (3, 2, 2, 3)
+  TEST (0, 3, 2, 3)
+  TEST (1, 3, 2, 3)
+  TEST (2, 3, 2, 3)
+  TEST (3, 3, 2, 3)
+  TEST (0, 0, 3, 3)
+  TEST (1, 0, 3, 3)
+  TEST (2, 0, 3, 3)
+  TEST (3, 0, 3, 3)
+  TEST (0, 1, 3, 3)
+  TEST (1, 1, 3, 3)
+  TEST (2, 1, 3, 3)
+  TEST (3, 1, 3, 3)
+  TEST (0, 2, 3, 3)
+  TEST (1, 2, 3, 3)
+  TEST (2, 2, 3, 3)
+  TEST (3, 2, 3, 3)
+  TEST (0, 3, 3, 3)
+  TEST (1, 3, 3, 3)
+  TEST (2, 3, 3, 3)
+  TEST (3, 3, 3, 3)
+}
+
+void check(void)
+{
+  check0 ();
+  check1 ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-4-2.inc b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-4-2.inc
new file mode 100644
index 000000000..2f7baa0ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-4-2.inc
@@ -0,0 +1,4262 @@
+/* This file auto-generated with ./vperm.pl 4 2.  */
+
+void check0(void)
+{
+  TEST (0, 0, 0, 0)
+  TEST (1, 0, 0, 0)
+  TEST (2, 0, 0, 0)
+  TEST (3, 0, 0, 0)
+  TEST (4, 0, 0, 0)
+  TEST (5, 0, 0, 0)
+  TEST (6, 0, 0, 0)
+  TEST (7, 0, 0, 0)
+  TEST (0, 1, 0, 0)
+  TEST (1, 1, 0, 0)
+  TEST (2, 1, 0, 0)
+  TEST (3, 1, 0, 0)
+  TEST (4, 1, 0, 0)
+  TEST (5, 1, 0, 0)
+  TEST (6, 1, 0, 0)
+  TEST (7, 1, 0, 0)
+  TEST (0, 2, 0, 0)
+  TEST (1, 2, 0, 0)
+  TEST (2, 2, 0, 0)
+  TEST (3, 2, 0, 0)
+  TEST (4, 2, 0, 0)
+  TEST (5, 2, 0, 0)
+  TEST (6, 2, 0, 0)
+  TEST (7, 2, 0, 0)
+  TEST (0, 3, 0, 0)
+  TEST (1, 3, 0, 0)
+  TEST (2, 3, 0, 0)
+  TEST (3, 3, 0, 0)
+  TEST (4, 3, 0, 0)
+  TEST (5, 3, 0, 0)
+  TEST (6, 3, 0, 0)
+  TEST (7, 3, 0, 0)
+  TEST (0, 4, 0, 0)
+  TEST (1, 4, 0, 0)
+  TEST (2, 4, 0, 0)
+  TEST (3, 4, 0, 0)
+  TEST (4, 4, 0, 0)
+  TEST (5, 4, 0, 0)
+  TEST (6, 4, 0, 0)
+  TEST (7, 4, 0, 0)
+  TEST (0, 5, 0, 0)
+  TEST (1, 5, 0, 0)
+  TEST (2, 5, 0, 0)
+  TEST (3, 5, 0, 0)
+  TEST (4, 5, 0, 0)
+  TEST (5, 5, 0, 0)
+  TEST (6, 5, 0, 0)
+  TEST (7, 5, 0, 0)
+  TEST (0, 6, 0, 0)
+  TEST (1, 6, 0, 0)
+  TEST (2, 6, 0, 0)
+  TEST (3, 6, 0, 0)
+  TEST (4, 6, 0, 0)
+  TEST (5, 6, 0, 0)
+  TEST (6, 6, 0, 0)
+  TEST (7, 6, 0, 0)
+  TEST (0, 7, 0, 0)
+  TEST (1, 7, 0, 0)
+  TEST (2, 7, 0, 0)
+  TEST (3, 7, 0, 0)
+  TEST (4, 7, 0, 0)
+  TEST (5, 7, 0, 0)
+  TEST (6, 7, 0, 0)
+  TEST (7, 7, 0, 0)
+  TEST (0, 0, 1, 0)
+  TEST (1, 0, 1, 0)
+  TEST (2, 0, 1, 0)
+  TEST (3, 0, 1, 0)
+  TEST (4, 0, 1, 0)
+  TEST (5, 0, 1, 0)
+  TEST (6, 0, 1, 0)
+  TEST (7, 0, 1, 0)
+  TEST (0, 1, 1, 0)
+  TEST (1, 1, 1, 0)
+  TEST (2, 1, 1, 0)
+  TEST (3, 1, 1, 0)
+  TEST (4, 1, 1, 0)
+  TEST (5, 1, 1, 0)
+  TEST (6, 1, 1, 0)
+  TEST (7, 1, 1, 0)
+  TEST (0, 2, 1, 0)
+  TEST (1, 2, 1, 0)
+  TEST (2, 2, 1, 0)
+  TEST (3, 2, 1, 0)
+  TEST (4, 2, 1, 0)
+  TEST (5, 2, 1, 0)
+  TEST (6, 2, 1, 0)
+  TEST (7, 2, 1, 0)
+  TEST (0, 3, 1, 0)
+  TEST (1, 3, 1, 0)
+  TEST (2, 3, 1, 0)
+  TEST (3, 3, 1, 0)
+  TEST (4, 3, 1, 0)
+  TEST (5, 3, 1, 0)
+  TEST (6, 3, 1, 0)
+  TEST (7, 3, 1, 0)
+  TEST (0, 4, 1, 0)
+  TEST (1, 4, 1, 0)
+  TEST (2, 4, 1, 0)
+  TEST (3, 4, 1, 0)
+  TEST (4, 4, 1, 0)
+  TEST (5, 4, 1, 0)
+  TEST (6, 4, 1, 0)
+  TEST (7, 4, 1, 0)
+  TEST (0, 5, 1, 0)
+  TEST (1, 5, 1, 0)
+  TEST (2, 5, 1, 0)
+  TEST (3, 5, 1, 0)
+  TEST (4, 5, 1, 0)
+  TEST (5, 5, 1, 0)
+  TEST (6, 5, 1, 0)
+  TEST (7, 5, 1, 0)
+  TEST (0, 6, 1, 0)
+  TEST (1, 6, 1, 0)
+  TEST (2, 6, 1, 0)
+  TEST (3, 6, 1, 0)
+  TEST (4, 6, 1, 0)
+  TEST (5, 6, 1, 0)
+  TEST (6, 6, 1, 0)
+  TEST (7, 6, 1, 0)
+  TEST (0, 7, 1, 0)
+  TEST (1, 7, 1, 0)
+  TEST (2, 7, 1, 0)
+  TEST (3, 7, 1, 0)
+  TEST (4, 7, 1, 0)
+  TEST (5, 7, 1, 0)
+  TEST (6, 7, 1, 0)
+  TEST (7, 7, 1, 0)
+}
+
+void check1(void)
+{
+  TEST (0, 0, 2, 0)
+  TEST (1, 0, 2, 0)
+  TEST (2, 0, 2, 0)
+  TEST (3, 0, 2, 0)
+  TEST (4, 0, 2, 0)
+  TEST (5, 0, 2, 0)
+  TEST (6, 0, 2, 0)
+  TEST (7, 0, 2, 0)
+  TEST (0, 1, 2, 0)
+  TEST (1, 1, 2, 0)
+  TEST (2, 1, 2, 0)
+  TEST (3, 1, 2, 0)
+  TEST (4, 1, 2, 0)
+  TEST (5, 1, 2, 0)
+  TEST (6, 1, 2, 0)
+  TEST (7, 1, 2, 0)
+  TEST (0, 2, 2, 0)
+  TEST (1, 2, 2, 0)
+  TEST (2, 2, 2, 0)
+  TEST (3, 2, 2, 0)
+  TEST (4, 2, 2, 0)
+  TEST (5, 2, 2, 0)
+  TEST (6, 2, 2, 0)
+  TEST (7, 2, 2, 0)
+  TEST (0, 3, 2, 0)
+  TEST (1, 3, 2, 0)
+  TEST (2, 3, 2, 0)
+  TEST (3, 3, 2, 0)
+  TEST (4, 3, 2, 0)
+  TEST (5, 3, 2, 0)
+  TEST (6, 3, 2, 0)
+  TEST (7, 3, 2, 0)
+  TEST (0, 4, 2, 0)
+  TEST (1, 4, 2, 0)
+  TEST (2, 4, 2, 0)
+  TEST (3, 4, 2, 0)
+  TEST (4, 4, 2, 0)
+  TEST (5, 4, 2, 0)
+  TEST (6, 4, 2, 0)
+  TEST (7, 4, 2, 0)
+  TEST (0, 5, 2, 0)
+  TEST (1, 5, 2, 0)
+  TEST (2, 5, 2, 0)
+  TEST (3, 5, 2, 0)
+  TEST (4, 5, 2, 0)
+  TEST (5, 5, 2, 0)
+  TEST (6, 5, 2, 0)
+  TEST (7, 5, 2, 0)
+  TEST (0, 6, 2, 0)
+  TEST (1, 6, 2, 0)
+  TEST (2, 6, 2, 0)
+  TEST (3, 6, 2, 0)
+  TEST (4, 6, 2, 0)
+  TEST (5, 6, 2, 0)
+  TEST (6, 6, 2, 0)
+  TEST (7, 6, 2, 0)
+  TEST (0, 7, 2, 0)
+  TEST (1, 7, 2, 0)
+  TEST (2, 7, 2, 0)
+  TEST (3, 7, 2, 0)
+  TEST (4, 7, 2, 0)
+  TEST (5, 7, 2, 0)
+  TEST (6, 7, 2, 0)
+  TEST (7, 7, 2, 0)
+  TEST (0, 0, 3, 0)
+  TEST (1, 0, 3, 0)
+  TEST (2, 0, 3, 0)
+  TEST (3, 0, 3, 0)
+  TEST (4, 0, 3, 0)
+  TEST (5, 0, 3, 0)
+  TEST (6, 0, 3, 0)
+  TEST (7, 0, 3, 0)
+  TEST (0, 1, 3, 0)
+  TEST (1, 1, 3, 0)
+  TEST (2, 1, 3, 0)
+  TEST (3, 1, 3, 0)
+  TEST (4, 1, 3, 0)
+  TEST (5, 1, 3, 0)
+  TEST (6, 1, 3, 0)
+  TEST (7, 1, 3, 0)
+  TEST (0, 2, 3, 0)
+  TEST (1, 2, 3, 0)
+  TEST (2, 2, 3, 0)
+  TEST (3, 2, 3, 0)
+  TEST (4, 2, 3, 0)
+  TEST (5, 2, 3, 0)
+  TEST (6, 2, 3, 0)
+  TEST (7, 2, 3, 0)
+  TEST (0, 3, 3, 0)
+  TEST (1, 3, 3, 0)
+  TEST (2, 3, 3, 0)
+  TEST (3, 3, 3, 0)
+  TEST (4, 3, 3, 0)
+  TEST (5, 3, 3, 0)
+  TEST (6, 3, 3, 0)
+  TEST (7, 3, 3, 0)
+  TEST (0, 4, 3, 0)
+  TEST (1, 4, 3, 0)
+  TEST (2, 4, 3, 0)
+  TEST (3, 4, 3, 0)
+  TEST (4, 4, 3, 0)
+  TEST (5, 4, 3, 0)
+  TEST (6, 4, 3, 0)
+  TEST (7, 4, 3, 0)
+  TEST (0, 5, 3, 0)
+  TEST (1, 5, 3, 0)
+  TEST (2, 5, 3, 0)
+  TEST (3, 5, 3, 0)
+  TEST (4, 5, 3, 0)
+  TEST (5, 5, 3, 0)
+  TEST (6, 5, 3, 0)
+  TEST (7, 5, 3, 0)
+  TEST (0, 6, 3, 0)
+  TEST (1, 6, 3, 0)
+  TEST (2, 6, 3, 0)
+  TEST (3, 6, 3, 0)
+  TEST (4, 6, 3, 0)
+  TEST (5, 6, 3, 0)
+  TEST (6, 6, 3, 0)
+  TEST (7, 6, 3, 0)
+  TEST (0, 7, 3, 0)
+  TEST (1, 7, 3, 0)
+  TEST (2, 7, 3, 0)
+  TEST (3, 7, 3, 0)
+  TEST (4, 7, 3, 0)
+  TEST (5, 7, 3, 0)
+  TEST (6, 7, 3, 0)
+  TEST (7, 7, 3, 0)
+}
+
+void check2(void)
+{
+  TEST (0, 0, 4, 0)
+  TEST (1, 0, 4, 0)
+  TEST (2, 0, 4, 0)
+  TEST (3, 0, 4, 0)
+  TEST (4, 0, 4, 0)
+  TEST (5, 0, 4, 0)
+  TEST (6, 0, 4, 0)
+  TEST (7, 0, 4, 0)
+  TEST (0, 1, 4, 0)
+  TEST (1, 1, 4, 0)
+  TEST (2, 1, 4, 0)
+  TEST (3, 1, 4, 0)
+  TEST (4, 1, 4, 0)
+  TEST (5, 1, 4, 0)
+  TEST (6, 1, 4, 0)
+  TEST (7, 1, 4, 0)
+  TEST (0, 2, 4, 0)
+  TEST (1, 2, 4, 0)
+  TEST (2, 2, 4, 0)
+  TEST (3, 2, 4, 0)
+  TEST (4, 2, 4, 0)
+  TEST (5, 2, 4, 0)
+  TEST (6, 2, 4, 0)
+  TEST (7, 2, 4, 0)
+  TEST (0, 3, 4, 0)
+  TEST (1, 3, 4, 0)
+  TEST (2, 3, 4, 0)
+  TEST (3, 3, 4, 0)
+  TEST (4, 3, 4, 0)
+  TEST (5, 3, 4, 0)
+  TEST (6, 3, 4, 0)
+  TEST (7, 3, 4, 0)
+  TEST (0, 4, 4, 0)
+  TEST (1, 4, 4, 0)
+  TEST (2, 4, 4, 0)
+  TEST (3, 4, 4, 0)
+  TEST (4, 4, 4, 0)
+  TEST (5, 4, 4, 0)
+  TEST (6, 4, 4, 0)
+  TEST (7, 4, 4, 0)
+  TEST (0, 5, 4, 0)
+  TEST (1, 5, 4, 0)
+  TEST (2, 5, 4, 0)
+  TEST (3, 5, 4, 0)
+  TEST (4, 5, 4, 0)
+  TEST (5, 5, 4, 0)
+  TEST (6, 5, 4, 0)
+  TEST (7, 5, 4, 0)
+  TEST (0, 6, 4, 0)
+  TEST (1, 6, 4, 0)
+  TEST (2, 6, 4, 0)
+  TEST (3, 6, 4, 0)
+  TEST (4, 6, 4, 0)
+  TEST (5, 6, 4, 0)
+  TEST (6, 6, 4, 0)
+  TEST (7, 6, 4, 0)
+  TEST (0, 7, 4, 0)
+  TEST (1, 7, 4, 0)
+  TEST (2, 7, 4, 0)
+  TEST (3, 7, 4, 0)
+  TEST (4, 7, 4, 0)
+  TEST (5, 7, 4, 0)
+  TEST (6, 7, 4, 0)
+  TEST (7, 7, 4, 0)
+  TEST (0, 0, 5, 0)
+  TEST (1, 0, 5, 0)
+  TEST (2, 0, 5, 0)
+  TEST (3, 0, 5, 0)
+  TEST (4, 0, 5, 0)
+  TEST (5, 0, 5, 0)
+  TEST (6, 0, 5, 0)
+  TEST (7, 0, 5, 0)
+  TEST (0, 1, 5, 0)
+  TEST (1, 1, 5, 0)
+  TEST (2, 1, 5, 0)
+  TEST (3, 1, 5, 0)
+  TEST (4, 1, 5, 0)
+  TEST (5, 1, 5, 0)
+  TEST (6, 1, 5, 0)
+  TEST (7, 1, 5, 0)
+  TEST (0, 2, 5, 0)
+  TEST (1, 2, 5, 0)
+  TEST (2, 2, 5, 0)
+  TEST (3, 2, 5, 0)
+  TEST (4, 2, 5, 0)
+  TEST (5, 2, 5, 0)
+  TEST (6, 2, 5, 0)
+  TEST (7, 2, 5, 0)
+  TEST (0, 3, 5, 0)
+  TEST (1, 3, 5, 0)
+  TEST (2, 3, 5, 0)
+  TEST (3, 3, 5, 0)
+  TEST (4, 3, 5, 0)
+  TEST (5, 3, 5, 0)
+  TEST (6, 3, 5, 0)
+  TEST (7, 3, 5, 0)
+  TEST (0, 4, 5, 0)
+  TEST (1, 4, 5, 0)
+  TEST (2, 4, 5, 0)
+  TEST (3, 4, 5, 0)
+  TEST (4, 4, 5, 0)
+  TEST (5, 4, 5, 0)
+  TEST (6, 4, 5, 0)
+  TEST (7, 4, 5, 0)
+  TEST (0, 5, 5, 0)
+  TEST (1, 5, 5, 0)
+  TEST (2, 5, 5, 0)
+  TEST (3, 5, 5, 0)
+  TEST (4, 5, 5, 0)
+  TEST (5, 5, 5, 0)
+  TEST (6, 5, 5, 0)
+  TEST (7, 5, 5, 0)
+  TEST (0, 6, 5, 0)
+  TEST (1, 6, 5, 0)
+  TEST (2, 6, 5, 0)
+  TEST (3, 6, 5, 0)
+  TEST (4, 6, 5, 0)
+  TEST (5, 6, 5, 0)
+  TEST (6, 6, 5, 0)
+  TEST (7, 6, 5, 0)
+  TEST (0, 7, 5, 0)
+  TEST (1, 7, 5, 0)
+  TEST (2, 7, 5, 0)
+  TEST (3, 7, 5, 0)
+  TEST (4, 7, 5, 0)
+  TEST (5, 7, 5, 0)
+  TEST (6, 7, 5, 0)
+  TEST (7, 7, 5, 0)
+}
+
+void check3(void)
+{
+  TEST (0, 0, 6, 0)
+  TEST (1, 0, 6, 0)
+  TEST (2, 0, 6, 0)
+  TEST (3, 0, 6, 0)
+  TEST (4, 0, 6, 0)
+  TEST (5, 0, 6, 0)
+  TEST (6, 0, 6, 0)
+  TEST (7, 0, 6, 0)
+  TEST (0, 1, 6, 0)
+  TEST (1, 1, 6, 0)
+  TEST (2, 1, 6, 0)
+  TEST (3, 1, 6, 0)
+  TEST (4, 1, 6, 0)
+  TEST (5, 1, 6, 0)
+  TEST (6, 1, 6, 0)
+  TEST (7, 1, 6, 0)
+  TEST (0, 2, 6, 0)
+  TEST (1, 2, 6, 0)
+  TEST (2, 2, 6, 0)
+  TEST (3, 2, 6, 0)
+  TEST (4, 2, 6, 0)
+  TEST (5, 2, 6, 0)
+  TEST (6, 2, 6, 0)
+  TEST (7, 2, 6, 0)
+  TEST (0, 3, 6, 0)
+  TEST (1, 3, 6, 0)
+  TEST (2, 3, 6, 0)
+  TEST (3, 3, 6, 0)
+  TEST (4, 3, 6, 0)
+  TEST (5, 3, 6, 0)
+  TEST (6, 3, 6, 0)
+  TEST (7, 3, 6, 0)
+  TEST (0, 4, 6, 0)
+  TEST (1, 4, 6, 0)
+  TEST (2, 4, 6, 0)
+  TEST (3, 4, 6, 0)
+  TEST (4, 4, 6, 0)
+  TEST (5, 4, 6, 0)
+  TEST (6, 4, 6, 0)
+  TEST (7, 4, 6, 0)
+  TEST (0, 5, 6, 0)
+  TEST (1, 5, 6, 0)
+  TEST (2, 5, 6, 0)
+  TEST (3, 5, 6, 0)
+  TEST (4, 5, 6, 0)
+  TEST (5, 5, 6, 0)
+  TEST (6, 5, 6, 0)
+  TEST (7, 5, 6, 0)
+  TEST (0, 6, 6, 0)
+  TEST (1, 6, 6, 0)
+  TEST (2, 6, 6, 0)
+  TEST (3, 6, 6, 0)
+  TEST (4, 6, 6, 0)
+  TEST (5, 6, 6, 0)
+  TEST (6, 6, 6, 0)
+  TEST (7, 6, 6, 0)
+  TEST (0, 7, 6, 0)
+  TEST (1, 7, 6, 0)
+  TEST (2, 7, 6, 0)
+  TEST (3, 7, 6, 0)
+  TEST (4, 7, 6, 0)
+  TEST (5, 7, 6, 0)
+  TEST (6, 7, 6, 0)
+  TEST (7, 7, 6, 0)
+  TEST (0, 0, 7, 0)
+  TEST (1, 0, 7, 0)
+  TEST (2, 0, 7, 0)
+  TEST (3, 0, 7, 0)
+  TEST (4, 0, 7, 0)
+  TEST (5, 0, 7, 0)
+  TEST (6, 0, 7, 0)
+  TEST (7, 0, 7, 0)
+  TEST (0, 1, 7, 0)
+  TEST (1, 1, 7, 0)
+  TEST (2, 1, 7, 0)
+  TEST (3, 1, 7, 0)
+  TEST (4, 1, 7, 0)
+  TEST (5, 1, 7, 0)
+  TEST (6, 1, 7, 0)
+  TEST (7, 1, 7, 0)
+  TEST (0, 2, 7, 0)
+  TEST (1, 2, 7, 0)
+  TEST (2, 2, 7, 0)
+  TEST (3, 2, 7, 0)
+  TEST (4, 2, 7, 0)
+  TEST (5, 2, 7, 0)
+  TEST (6, 2, 7, 0)
+  TEST (7, 2, 7, 0)
+  TEST (0, 3, 7, 0)
+  TEST (1, 3, 7, 0)
+  TEST (2, 3, 7, 0)
+  TEST (3, 3, 7, 0)
+  TEST (4, 3, 7, 0)
+  TEST (5, 3, 7, 0)
+  TEST (6, 3, 7, 0)
+  TEST (7, 3, 7, 0)
+  TEST (0, 4, 7, 0)
+  TEST (1, 4, 7, 0)
+  TEST (2, 4, 7, 0)
+  TEST (3, 4, 7, 0)
+  TEST (4, 4, 7, 0)
+  TEST (5, 4, 7, 0)
+  TEST (6, 4, 7, 0)
+  TEST (7, 4, 7, 0)
+  TEST (0, 5, 7, 0)
+  TEST (1, 5, 7, 0)
+  TEST (2, 5, 7, 0)
+  TEST (3, 5, 7, 0)
+  TEST (4, 5, 7, 0)
+  TEST (5, 5, 7, 0)
+  TEST (6, 5, 7, 0)
+  TEST (7, 5, 7, 0)
+  TEST (0, 6, 7, 0)
+  TEST (1, 6, 7, 0)
+  TEST (2, 6, 7, 0)
+  TEST (3, 6, 7, 0)
+  TEST (4, 6, 7, 0)
+  TEST (5, 6, 7, 0)
+  TEST (6, 6, 7, 0)
+  TEST (7, 6, 7, 0)
+  TEST (0, 7, 7, 0)
+  TEST (1, 7, 7, 0)
+  TEST (2, 7, 7, 0)
+  TEST (3, 7, 7, 0)
+  TEST (4, 7, 7, 0)
+  TEST (5, 7, 7, 0)
+  TEST (6, 7, 7, 0)
+  TEST (7, 7, 7, 0)
+}
+
+void check4(void)
+{
+  TEST (0, 0, 0, 1)
+  TEST (1, 0, 0, 1)
+  TEST (2, 0, 0, 1)
+  TEST (3, 0, 0, 1)
+  TEST (4, 0, 0, 1)
+  TEST (5, 0, 0, 1)
+  TEST (6, 0, 0, 1)
+  TEST (7, 0, 0, 1)
+  TEST (0, 1, 0, 1)
+  TEST (1, 1, 0, 1)
+  TEST (2, 1, 0, 1)
+  TEST (3, 1, 0, 1)
+  TEST (4, 1, 0, 1)
+  TEST (5, 1, 0, 1)
+  TEST (6, 1, 0, 1)
+  TEST (7, 1, 0, 1)
+  TEST (0, 2, 0, 1)
+  TEST (1, 2, 0, 1)
+  TEST (2, 2, 0, 1)
+  TEST (3, 2, 0, 1)
+  TEST (4, 2, 0, 1)
+  TEST (5, 2, 0, 1)
+  TEST (6, 2, 0, 1)
+  TEST (7, 2, 0, 1)
+  TEST (0, 3, 0, 1)
+  TEST (1, 3, 0, 1)
+  TEST (2, 3, 0, 1)
+  TEST (3, 3, 0, 1)
+  TEST (4, 3, 0, 1)
+  TEST (5, 3, 0, 1)
+  TEST (6, 3, 0, 1)
+  TEST (7, 3, 0, 1)
+  TEST (0, 4, 0, 1)
+  TEST (1, 4, 0, 1)
+  TEST (2, 4, 0, 1)
+  TEST (3, 4, 0, 1)
+  TEST (4, 4, 0, 1)
+  TEST (5, 4, 0, 1)
+  TEST (6, 4, 0, 1)
+  TEST (7, 4, 0, 1)
+  TEST (0, 5, 0, 1)
+  TEST (1, 5, 0, 1)
+  TEST (2, 5, 0, 1)
+  TEST (3, 5, 0, 1)
+  TEST (4, 5, 0, 1)
+  TEST (5, 5, 0, 1)
+  TEST (6, 5, 0, 1)
+  TEST (7, 5, 0, 1)
+  TEST (0, 6, 0, 1)
+  TEST (1, 6, 0, 1)
+  TEST (2, 6, 0, 1)
+  TEST (3, 6, 0, 1)
+  TEST (4, 6, 0, 1)
+  TEST (5, 6, 0, 1)
+  TEST (6, 6, 0, 1)
+  TEST (7, 6, 0, 1)
+  TEST (0, 7, 0, 1)
+  TEST (1, 7, 0, 1)
+  TEST (2, 7, 0, 1)
+  TEST (3, 7, 0, 1)
+  TEST (4, 7, 0, 1)
+  TEST (5, 7, 0, 1)
+  TEST (6, 7, 0, 1)
+  TEST (7, 7, 0, 1)
+  TEST (0, 0, 1, 1)
+  TEST (1, 0, 1, 1)
+  TEST (2, 0, 1, 1)
+  TEST (3, 0, 1, 1)
+  TEST (4, 0, 1, 1)
+  TEST (5, 0, 1, 1)
+  TEST (6, 0, 1, 1)
+  TEST (7, 0, 1, 1)
+  TEST (0, 1, 1, 1)
+  TEST (1, 1, 1, 1)
+  TEST (2, 1, 1, 1)
+  TEST (3, 1, 1, 1)
+  TEST (4, 1, 1, 1)
+  TEST (5, 1, 1, 1)
+  TEST (6, 1, 1, 1)
+  TEST (7, 1, 1, 1)
+  TEST (0, 2, 1, 1)
+  TEST (1, 2, 1, 1)
+  TEST (2, 2, 1, 1)
+  TEST (3, 2, 1, 1)
+  TEST (4, 2, 1, 1)
+  TEST (5, 2, 1, 1)
+  TEST (6, 2, 1, 1)
+  TEST (7, 2, 1, 1)
+  TEST (0, 3, 1, 1)
+  TEST (1, 3, 1, 1)
+  TEST (2, 3, 1, 1)
+  TEST (3, 3, 1, 1)
+  TEST (4, 3, 1, 1)
+  TEST (5, 3, 1, 1)
+  TEST (6, 3, 1, 1)
+  TEST (7, 3, 1, 1)
+  TEST (0, 4, 1, 1)
+  TEST (1, 4, 1, 1)
+  TEST (2, 4, 1, 1)
+  TEST (3, 4, 1, 1)
+  TEST (4, 4, 1, 1)
+  TEST (5, 4, 1, 1)
+  TEST (6, 4, 1, 1)
+  TEST (7, 4, 1, 1)
+  TEST (0, 5, 1, 1)
+  TEST (1, 5, 1, 1)
+  TEST (2, 5, 1, 1)
+  TEST (3, 5, 1, 1)
+  TEST (4, 5, 1, 1)
+  TEST (5, 5, 1, 1)
+  TEST (6, 5, 1, 1)
+  TEST (7, 5, 1, 1)
+  TEST (0, 6, 1, 1)
+  TEST (1, 6, 1, 1)
+  TEST (2, 6, 1, 1)
+  TEST (3, 6, 1, 1)
+  TEST (4, 6, 1, 1)
+  TEST (5, 6, 1, 1)
+  TEST (6, 6, 1, 1)
+  TEST (7, 6, 1, 1)
+  TEST (0, 7, 1, 1)
+  TEST (1, 7, 1, 1)
+  TEST (2, 7, 1, 1)
+  TEST (3, 7, 1, 1)
+  TEST (4, 7, 1, 1)
+  TEST (5, 7, 1, 1)
+  TEST (6, 7, 1, 1)
+  TEST (7, 7, 1, 1)
+}
+
+void check5(void)
+{
+  TEST (0, 0, 2, 1)
+  TEST (1, 0, 2, 1)
+  TEST (2, 0, 2, 1)
+  TEST (3, 0, 2, 1)
+  TEST (4, 0, 2, 1)
+  TEST (5, 0, 2, 1)
+  TEST (6, 0, 2, 1)
+  TEST (7, 0, 2, 1)
+  TEST (0, 1, 2, 1)
+  TEST (1, 1, 2, 1)
+  TEST (2, 1, 2, 1)
+  TEST (3, 1, 2, 1)
+  TEST (4, 1, 2, 1)
+  TEST (5, 1, 2, 1)
+  TEST (6, 1, 2, 1)
+  TEST (7, 1, 2, 1)
+  TEST (0, 2, 2, 1)
+  TEST (1, 2, 2, 1)
+  TEST (2, 2, 2, 1)
+  TEST (3, 2, 2, 1)
+  TEST (4, 2, 2, 1)
+  TEST (5, 2, 2, 1)
+  TEST (6, 2, 2, 1)
+  TEST (7, 2, 2, 1)
+  TEST (0, 3, 2, 1)
+  TEST (1, 3, 2, 1)
+  TEST (2, 3, 2, 1)
+  TEST (3, 3, 2, 1)
+  TEST (4, 3, 2, 1)
+  TEST (5, 3, 2, 1)
+  TEST (6, 3, 2, 1)
+  TEST (7, 3, 2, 1)
+  TEST (0, 4, 2, 1)
+  TEST (1, 4, 2, 1)
+  TEST (2, 4, 2, 1)
+  TEST (3, 4, 2, 1)
+  TEST (4, 4, 2, 1)
+  TEST (5, 4, 2, 1)
+  TEST (6, 4, 2, 1)
+  TEST (7, 4, 2, 1)
+  TEST (0, 5, 2, 1)
+  TEST (1, 5, 2, 1)
+  TEST (2, 5, 2, 1)
+  TEST (3, 5, 2, 1)
+  TEST (4, 5, 2, 1)
+  TEST (5, 5, 2, 1)
+  TEST (6, 5, 2, 1)
+  TEST (7, 5, 2, 1)
+  TEST (0, 6, 2, 1)
+  TEST (1, 6, 2, 1)
+  TEST (2, 6, 2, 1)
+  TEST (3, 6, 2, 1)
+  TEST (4, 6, 2, 1)
+  TEST (5, 6, 2, 1)
+  TEST (6, 6, 2, 1)
+  TEST (7, 6, 2, 1)
+  TEST (0, 7, 2, 1)
+  TEST (1, 7, 2, 1)
+  TEST (2, 7, 2, 1)
+  TEST (3, 7, 2, 1)
+  TEST (4, 7, 2, 1)
+  TEST (5, 7, 2, 1)
+  TEST (6, 7, 2, 1)
+  TEST (7, 7, 2, 1)
+  TEST (0, 0, 3, 1)
+  TEST (1, 0, 3, 1)
+  TEST (2, 0, 3, 1)
+  TEST (3, 0, 3, 1)
+  TEST (4, 0, 3, 1)
+  TEST (5, 0, 3, 1)
+  TEST (6, 0, 3, 1)
+  TEST (7, 0, 3, 1)
+  TEST (0, 1, 3, 1)
+  TEST (1, 1, 3, 1)
+  TEST (2, 1, 3, 1)
+  TEST (3, 1, 3, 1)
+  TEST (4, 1, 3, 1)
+  TEST (5, 1, 3, 1)
+  TEST (6, 1, 3, 1)
+  TEST (7, 1, 3, 1)
+  TEST (0, 2, 3, 1)
+  TEST (1, 2, 3, 1)
+  TEST (2, 2, 3, 1)
+  TEST (3, 2, 3, 1)
+  TEST (4, 2, 3, 1)
+  TEST (5, 2, 3, 1)
+  TEST (6, 2, 3, 1)
+  TEST (7, 2, 3, 1)
+  TEST (0, 3, 3, 1)
+  TEST (1, 3, 3, 1)
+  TEST (2, 3, 3, 1)
+  TEST (3, 3, 3, 1)
+  TEST (4, 3, 3, 1)
+  TEST (5, 3, 3, 1)
+  TEST (6, 3, 3, 1)
+  TEST (7, 3, 3, 1)
+  TEST (0, 4, 3, 1)
+  TEST (1, 4, 3, 1)
+  TEST (2, 4, 3, 1)
+  TEST (3, 4, 3, 1)
+  TEST (4, 4, 3, 1)
+  TEST (5, 4, 3, 1)
+  TEST (6, 4, 3, 1)
+  TEST (7, 4, 3, 1)
+  TEST (0, 5, 3, 1)
+  TEST (1, 5, 3, 1)
+  TEST (2, 5, 3, 1)
+  TEST (3, 5, 3, 1)
+  TEST (4, 5, 3, 1)
+  TEST (5, 5, 3, 1)
+  TEST (6, 5, 3, 1)
+  TEST (7, 5, 3, 1)
+  TEST (0, 6, 3, 1)
+  TEST (1, 6, 3, 1)
+  TEST (2, 6, 3, 1)
+  TEST (3, 6, 3, 1)
+  TEST (4, 6, 3, 1)
+  TEST (5, 6, 3, 1)
+  TEST (6, 6, 3, 1)
+  TEST (7, 6, 3, 1)
+  TEST (0, 7, 3, 1)
+  TEST (1, 7, 3, 1)
+  TEST (2, 7, 3, 1)
+  TEST (3, 7, 3, 1)
+  TEST (4, 7, 3, 1)
+  TEST (5, 7, 3, 1)
+  TEST (6, 7, 3, 1)
+  TEST (7, 7, 3, 1)
+}
+
+void check6(void)
+{
+  TEST (0, 0, 4, 1)
+  TEST (1, 0, 4, 1)
+  TEST (2, 0, 4, 1)
+  TEST (3, 0, 4, 1)
+  TEST (4, 0, 4, 1)
+  TEST (5, 0, 4, 1)
+  TEST (6, 0, 4, 1)
+  TEST (7, 0, 4, 1)
+  TEST (0, 1, 4, 1)
+  TEST (1, 1, 4, 1)
+  TEST (2, 1, 4, 1)
+  TEST (3, 1, 4, 1)
+  TEST (4, 1, 4, 1)
+  TEST (5, 1, 4, 1)
+  TEST (6, 1, 4, 1)
+  TEST (7, 1, 4, 1)
+  TEST (0, 2, 4, 1)
+  TEST (1, 2, 4, 1)
+  TEST (2, 2, 4, 1)
+  TEST (3, 2, 4, 1)
+  TEST (4, 2, 4, 1)
+  TEST (5, 2, 4, 1)
+  TEST (6, 2, 4, 1)
+  TEST (7, 2, 4, 1)
+  TEST (0, 3, 4, 1)
+  TEST (1, 3, 4, 1)
+  TEST (2, 3, 4, 1)
+  TEST (3, 3, 4, 1)
+  TEST (4, 3, 4, 1)
+  TEST (5, 3, 4, 1)
+  TEST (6, 3, 4, 1)
+  TEST (7, 3, 4, 1)
+  TEST (0, 4, 4, 1)
+  TEST (1, 4, 4, 1)
+  TEST (2, 4, 4, 1)
+  TEST (3, 4, 4, 1)
+  TEST (4, 4, 4, 1)
+  TEST (5, 4, 4, 1)
+  TEST (6, 4, 4, 1)
+  TEST (7, 4, 4, 1)
+  TEST (0, 5, 4, 1)
+  TEST (1, 5, 4, 1)
+  TEST (2, 5, 4, 1)
+  TEST (3, 5, 4, 1)
+  TEST (4, 5, 4, 1)
+  TEST (5, 5, 4, 1)
+  TEST (6, 5, 4, 1)
+  TEST (7, 5, 4, 1)
+  TEST (0, 6, 4, 1)
+  TEST (1, 6, 4, 1)
+  TEST (2, 6, 4, 1)
+  TEST (3, 6, 4, 1)
+  TEST (4, 6, 4, 1)
+  TEST (5, 6, 4, 1)
+  TEST (6, 6, 4, 1)
+  TEST (7, 6, 4, 1)
+  TEST (0, 7, 4, 1)
+  TEST (1, 7, 4, 1)
+  TEST (2, 7, 4, 1)
+  TEST (3, 7, 4, 1)
+  TEST (4, 7, 4, 1)
+  TEST (5, 7, 4, 1)
+  TEST (6, 7, 4, 1)
+  TEST (7, 7, 4, 1)
+  TEST (0, 0, 5, 1)
+  TEST (1, 0, 5, 1)
+  TEST (2, 0, 5, 1)
+  TEST (3, 0, 5, 1)
+  TEST (4, 0, 5, 1)
+  TEST (5, 0, 5, 1)
+  TEST (6, 0, 5, 1)
+  TEST (7, 0, 5, 1)
+  TEST (0, 1, 5, 1)
+  TEST (1, 1, 5, 1)
+  TEST (2, 1, 5, 1)
+  TEST (3, 1, 5, 1)
+  TEST (4, 1, 5, 1)
+  TEST (5, 1, 5, 1)
+  TEST (6, 1, 5, 1)
+  TEST (7, 1, 5, 1)
+  TEST (0, 2, 5, 1)
+  TEST (1, 2, 5, 1)
+  TEST (2, 2, 5, 1)
+  TEST (3, 2, 5, 1)
+  TEST (4, 2, 5, 1)
+  TEST (5, 2, 5, 1)
+  TEST (6, 2, 5, 1)
+  TEST (7, 2, 5, 1)
+  TEST (0, 3, 5, 1)
+  TEST (1, 3, 5, 1)
+  TEST (2, 3, 5, 1)
+  TEST (3, 3, 5, 1)
+  TEST (4, 3, 5, 1)
+  TEST (5, 3, 5, 1)
+  TEST (6, 3, 5, 1)
+  TEST (7, 3, 5, 1)
+  TEST (0, 4, 5, 1)
+  TEST (1, 4, 5, 1)
+  TEST (2, 4, 5, 1)
+  TEST (3, 4, 5, 1)
+  TEST (4, 4, 5, 1)
+  TEST (5, 4, 5, 1)
+  TEST (6, 4, 5, 1)
+  TEST (7, 4, 5, 1)
+  TEST (0, 5, 5, 1)
+  TEST (1, 5, 5, 1)
+  TEST (2, 5, 5, 1)
+  TEST (3, 5, 5, 1)
+  TEST (4, 5, 5, 1)
+  TEST (5, 5, 5, 1)
+  TEST (6, 5, 5, 1)
+  TEST (7, 5, 5, 1)
+  TEST (0, 6, 5, 1)
+  TEST (1, 6, 5, 1)
+  TEST (2, 6, 5, 1)
+  TEST (3, 6, 5, 1)
+  TEST (4, 6, 5, 1)
+  TEST (5, 6, 5, 1)
+  TEST (6, 6, 5, 1)
+  TEST (7, 6, 5, 1)
+  TEST (0, 7, 5, 1)
+  TEST (1, 7, 5, 1)
+  TEST (2, 7, 5, 1)
+  TEST (3, 7, 5, 1)
+  TEST (4, 7, 5, 1)
+  TEST (5, 7, 5, 1)
+  TEST (6, 7, 5, 1)
+  TEST (7, 7, 5, 1)
+}
+
+void check7(void)
+{
+  TEST (0, 0, 6, 1)
+  TEST (1, 0, 6, 1)
+  TEST (2, 0, 6, 1)
+  TEST (3, 0, 6, 1)
+  TEST (4, 0, 6, 1)
+  TEST (5, 0, 6, 1)
+  TEST (6, 0, 6, 1)
+  TEST (7, 0, 6, 1)
+  TEST (0, 1, 6, 1)
+  TEST (1, 1, 6, 1)
+  TEST (2, 1, 6, 1)
+  TEST (3, 1, 6, 1)
+  TEST (4, 1, 6, 1)
+  TEST (5, 1, 6, 1)
+  TEST (6, 1, 6, 1)
+  TEST (7, 1, 6, 1)
+  TEST (0, 2, 6, 1)
+  TEST (1, 2, 6, 1)
+  TEST (2, 2, 6, 1)
+  TEST (3, 2, 6, 1)
+  TEST (4, 2, 6, 1)
+  TEST (5, 2, 6, 1)
+  TEST (6, 2, 6, 1)
+  TEST (7, 2, 6, 1)
+  TEST (0, 3, 6, 1)
+  TEST (1, 3, 6, 1)
+  TEST (2, 3, 6, 1)
+  TEST (3, 3, 6, 1)
+  TEST (4, 3, 6, 1)
+  TEST (5, 3, 6, 1)
+  TEST (6, 3, 6, 1)
+  TEST (7, 3, 6, 1)
+  TEST (0, 4, 6, 1)
+  TEST (1, 4, 6, 1)
+  TEST (2, 4, 6, 1)
+  TEST (3, 4, 6, 1)
+  TEST (4, 4, 6, 1)
+  TEST (5, 4, 6, 1)
+  TEST (6, 4, 6, 1)
+  TEST (7, 4, 6, 1)
+  TEST (0, 5, 6, 1)
+  TEST (1, 5, 6, 1)
+  TEST (2, 5, 6, 1)
+  TEST (3, 5, 6, 1)
+  TEST (4, 5, 6, 1)
+  TEST (5, 5, 6, 1)
+  TEST (6, 5, 6, 1)
+  TEST (7, 5, 6, 1)
+  TEST (0, 6, 6, 1)
+  TEST (1, 6, 6, 1)
+  TEST (2, 6, 6, 1)
+  TEST (3, 6, 6, 1)
+  TEST (4, 6, 6, 1)
+  TEST (5, 6, 6, 1)
+  TEST (6, 6, 6, 1)
+  TEST (7, 6, 6, 1)
+  TEST (0, 7, 6, 1)
+  TEST (1, 7, 6, 1)
+  TEST (2, 7, 6, 1)
+  TEST (3, 7, 6, 1)
+  TEST (4, 7, 6, 1)
+  TEST (5, 7, 6, 1)
+  TEST (6, 7, 6, 1)
+  TEST (7, 7, 6, 1)
+  TEST (0, 0, 7, 1)
+  TEST (1, 0, 7, 1)
+  TEST (2, 0, 7, 1)
+  TEST (3, 0, 7, 1)
+  TEST (4, 0, 7, 1)
+  TEST (5, 0, 7, 1)
+  TEST (6, 0, 7, 1)
+  TEST (7, 0, 7, 1)
+  TEST (0, 1, 7, 1)
+  TEST (1, 1, 7, 1)
+  TEST (2, 1, 7, 1)
+  TEST (3, 1, 7, 1)
+  TEST (4, 1, 7, 1)
+  TEST (5, 1, 7, 1)
+  TEST (6, 1, 7, 1)
+  TEST (7, 1, 7, 1)
+  TEST (0, 2, 7, 1)
+  TEST (1, 2, 7, 1)
+  TEST (2, 2, 7, 1)
+  TEST (3, 2, 7, 1)
+  TEST (4, 2, 7, 1)
+  TEST (5, 2, 7, 1)
+  TEST (6, 2, 7, 1)
+  TEST (7, 2, 7, 1)
+  TEST (0, 3, 7, 1)
+  TEST (1, 3, 7, 1)
+  TEST (2, 3, 7, 1)
+  TEST (3, 3, 7, 1)
+  TEST (4, 3, 7, 1)
+  TEST (5, 3, 7, 1)
+  TEST (6, 3, 7, 1)
+  TEST (7, 3, 7, 1)
+  TEST (0, 4, 7, 1)
+  TEST (1, 4, 7, 1)
+  TEST (2, 4, 7, 1)
+  TEST (3, 4, 7, 1)
+  TEST (4, 4, 7, 1)
+  TEST (5, 4, 7, 1)
+  TEST (6, 4, 7, 1)
+  TEST (7, 4, 7, 1)
+  TEST (0, 5, 7, 1)
+  TEST (1, 5, 7, 1)
+  TEST (2, 5, 7, 1)
+  TEST (3, 5, 7, 1)
+  TEST (4, 5, 7, 1)
+  TEST (5, 5, 7, 1)
+  TEST (6, 5, 7, 1)
+  TEST (7, 5, 7, 1)
+  TEST (0, 6, 7, 1)
+  TEST (1, 6, 7, 1)
+  TEST (2, 6, 7, 1)
+  TEST (3, 6, 7, 1)
+  TEST (4, 6, 7, 1)
+  TEST (5, 6, 7, 1)
+  TEST (6, 6, 7, 1)
+  TEST (7, 6, 7, 1)
+  TEST (0, 7, 7, 1)
+  TEST (1, 7, 7, 1)
+  TEST (2, 7, 7, 1)
+  TEST (3, 7, 7, 1)
+  TEST (4, 7, 7, 1)
+  TEST (5, 7, 7, 1)
+  TEST (6, 7, 7, 1)
+  TEST (7, 7, 7, 1)
+}
+
+void check8(void)
+{
+  TEST (0, 0, 0, 2)
+  TEST (1, 0, 0, 2)
+  TEST (2, 0, 0, 2)
+  TEST (3, 0, 0, 2)
+  TEST (4, 0, 0, 2)
+  TEST (5, 0, 0, 2)
+  TEST (6, 0, 0, 2)
+  TEST (7, 0, 0, 2)
+  TEST (0, 1, 0, 2)
+  TEST (1, 1, 0, 2)
+  TEST (2, 1, 0, 2)
+  TEST (3, 1, 0, 2)
+  TEST (4, 1, 0, 2)
+  TEST (5, 1, 0, 2)
+  TEST (6, 1, 0, 2)
+  TEST (7, 1, 0, 2)
+  TEST (0, 2, 0, 2)
+  TEST (1, 2, 0, 2)
+  TEST (2, 2, 0, 2)
+  TEST (3, 2, 0, 2)
+  TEST (4, 2, 0, 2)
+  TEST (5, 2, 0, 2)
+  TEST (6, 2, 0, 2)
+  TEST (7, 2, 0, 2)
+  TEST (0, 3, 0, 2)
+  TEST (1, 3, 0, 2)
+  TEST (2, 3, 0, 2)
+  TEST (3, 3, 0, 2)
+  TEST (4, 3, 0, 2)
+  TEST (5, 3, 0, 2)
+  TEST (6, 3, 0, 2)
+  TEST (7, 3, 0, 2)
+  TEST (0, 4, 0, 2)
+  TEST (1, 4, 0, 2)
+  TEST (2, 4, 0, 2)
+  TEST (3, 4, 0, 2)
+  TEST (4, 4, 0, 2)
+  TEST (5, 4, 0, 2)
+  TEST (6, 4, 0, 2)
+  TEST (7, 4, 0, 2)
+  TEST (0, 5, 0, 2)
+  TEST (1, 5, 0, 2)
+  TEST (2, 5, 0, 2)
+  TEST (3, 5, 0, 2)
+  TEST (4, 5, 0, 2)
+  TEST (5, 5, 0, 2)
+  TEST (6, 5, 0, 2)
+  TEST (7, 5, 0, 2)
+  TEST (0, 6, 0, 2)
+  TEST (1, 6, 0, 2)
+  TEST (2, 6, 0, 2)
+  TEST (3, 6, 0, 2)
+  TEST (4, 6, 0, 2)
+  TEST (5, 6, 0, 2)
+  TEST (6, 6, 0, 2)
+  TEST (7, 6, 0, 2)
+  TEST (0, 7, 0, 2)
+  TEST (1, 7, 0, 2)
+  TEST (2, 7, 0, 2)
+  TEST (3, 7, 0, 2)
+  TEST (4, 7, 0, 2)
+  TEST (5, 7, 0, 2)
+  TEST (6, 7, 0, 2)
+  TEST (7, 7, 0, 2)
+  TEST (0, 0, 1, 2)
+  TEST (1, 0, 1, 2)
+  TEST (2, 0, 1, 2)
+  TEST (3, 0, 1, 2)
+  TEST (4, 0, 1, 2)
+  TEST (5, 0, 1, 2)
+  TEST (6, 0, 1, 2)
+  TEST (7, 0, 1, 2)
+  TEST (0, 1, 1, 2)
+  TEST (1, 1, 1, 2)
+  TEST (2, 1, 1, 2)
+  TEST (3, 1, 1, 2)
+  TEST (4, 1, 1, 2)
+  TEST (5, 1, 1, 2)
+  TEST (6, 1, 1, 2)
+  TEST (7, 1, 1, 2)
+  TEST (0, 2, 1, 2)
+  TEST (1, 2, 1, 2)
+  TEST (2, 2, 1, 2)
+  TEST (3, 2, 1, 2)
+  TEST (4, 2, 1, 2)
+  TEST (5, 2, 1, 2)
+  TEST (6, 2, 1, 2)
+  TEST (7, 2, 1, 2)
+  TEST (0, 3, 1, 2)
+  TEST (1, 3, 1, 2)
+  TEST (2, 3, 1, 2)
+  TEST (3, 3, 1, 2)
+  TEST (4, 3, 1, 2)
+  TEST (5, 3, 1, 2)
+  TEST (6, 3, 1, 2)
+  TEST (7, 3, 1, 2)
+  TEST (0, 4, 1, 2)
+  TEST (1, 4, 1, 2)
+  TEST (2, 4, 1, 2)
+  TEST (3, 4, 1, 2)
+  TEST (4, 4, 1, 2)
+  TEST (5, 4, 1, 2)
+  TEST (6, 4, 1, 2)
+  TEST (7, 4, 1, 2)
+  TEST (0, 5, 1, 2)
+  TEST (1, 5, 1, 2)
+  TEST (2, 5, 1, 2)
+  TEST (3, 5, 1, 2)
+  TEST (4, 5, 1, 2)
+  TEST (5, 5, 1, 2)
+  TEST (6, 5, 1, 2)
+  TEST (7, 5, 1, 2)
+  TEST (0, 6, 1, 2)
+  TEST (1, 6, 1, 2)
+  TEST (2, 6, 1, 2)
+  TEST (3, 6, 1, 2)
+  TEST (4, 6, 1, 2)
+  TEST (5, 6, 1, 2)
+  TEST (6, 6, 1, 2)
+  TEST (7, 6, 1, 2)
+  TEST (0, 7, 1, 2)
+  TEST (1, 7, 1, 2)
+  TEST (2, 7, 1, 2)
+  TEST (3, 7, 1, 2)
+  TEST (4, 7, 1, 2)
+  TEST (5, 7, 1, 2)
+  TEST (6, 7, 1, 2)
+  TEST (7, 7, 1, 2)
+}
+
+void check9(void)
+{
+  TEST (0, 0, 2, 2)
+  TEST (1, 0, 2, 2)
+  TEST (2, 0, 2, 2)
+  TEST (3, 0, 2, 2)
+  TEST (4, 0, 2, 2)
+  TEST (5, 0, 2, 2)
+  TEST (6, 0, 2, 2)
+  TEST (7, 0, 2, 2)
+  TEST (0, 1, 2, 2)
+  TEST (1, 1, 2, 2)
+  TEST (2, 1, 2, 2)
+  TEST (3, 1, 2, 2)
+  TEST (4, 1, 2, 2)
+  TEST (5, 1, 2, 2)
+  TEST (6, 1, 2, 2)
+  TEST (7, 1, 2, 2)
+  TEST (0, 2, 2, 2)
+  TEST (1, 2, 2, 2)
+  TEST (2, 2, 2, 2)
+  TEST (3, 2, 2, 2)
+  TEST (4, 2, 2, 2)
+  TEST (5, 2, 2, 2)
+  TEST (6, 2, 2, 2)
+  TEST (7, 2, 2, 2)
+  TEST (0, 3, 2, 2)
+  TEST (1, 3, 2, 2)
+  TEST (2, 3, 2, 2)
+  TEST (3, 3, 2, 2)
+  TEST (4, 3, 2, 2)
+  TEST (5, 3, 2, 2)
+  TEST (6, 3, 2, 2)
+  TEST (7, 3, 2, 2)
+  TEST (0, 4, 2, 2)
+  TEST (1, 4, 2, 2)
+  TEST (2, 4, 2, 2)
+  TEST (3, 4, 2, 2)
+  TEST (4, 4, 2, 2)
+  TEST (5, 4, 2, 2)
+  TEST (6, 4, 2, 2)
+  TEST (7, 4, 2, 2)
+  TEST (0, 5, 2, 2)
+  TEST (1, 5, 2, 2)
+  TEST (2, 5, 2, 2)
+  TEST (3, 5, 2, 2)
+  TEST (4, 5, 2, 2)
+  TEST (5, 5, 2, 2)
+  TEST (6, 5, 2, 2)
+  TEST (7, 5, 2, 2)
+  TEST (0, 6, 2, 2)
+  TEST (1, 6, 2, 2)
+  TEST (2, 6, 2, 2)
+  TEST (3, 6, 2, 2)
+  TEST (4, 6, 2, 2)
+  TEST (5, 6, 2, 2)
+  TEST (6, 6, 2, 2)
+  TEST (7, 6, 2, 2)
+  TEST (0, 7, 2, 2)
+  TEST (1, 7, 2, 2)
+  TEST (2, 7, 2, 2)
+  TEST (3, 7, 2, 2)
+  TEST (4, 7, 2, 2)
+  TEST (5, 7, 2, 2)
+  TEST (6, 7, 2, 2)
+  TEST (7, 7, 2, 2)
+  TEST (0, 0, 3, 2)
+  TEST (1, 0, 3, 2)
+  TEST (2, 0, 3, 2)
+  TEST (3, 0, 3, 2)
+  TEST (4, 0, 3, 2)
+  TEST (5, 0, 3, 2)
+  TEST (6, 0, 3, 2)
+  TEST (7, 0, 3, 2)
+  TEST (0, 1, 3, 2)
+  TEST (1, 1, 3, 2)
+  TEST (2, 1, 3, 2)
+  TEST (3, 1, 3, 2)
+  TEST (4, 1, 3, 2)
+  TEST (5, 1, 3, 2)
+  TEST (6, 1, 3, 2)
+  TEST (7, 1, 3, 2)
+  TEST (0, 2, 3, 2)
+  TEST (1, 2, 3, 2)
+  TEST (2, 2, 3, 2)
+  TEST (3, 2, 3, 2)
+  TEST (4, 2, 3, 2)
+  TEST (5, 2, 3, 2)
+  TEST (6, 2, 3, 2)
+  TEST (7, 2, 3, 2)
+  TEST (0, 3, 3, 2)
+  TEST (1, 3, 3, 2)
+  TEST (2, 3, 3, 2)
+  TEST (3, 3, 3, 2)
+  TEST (4, 3, 3, 2)
+  TEST (5, 3, 3, 2)
+  TEST (6, 3, 3, 2)
+  TEST (7, 3, 3, 2)
+  TEST (0, 4, 3, 2)
+  TEST (1, 4, 3, 2)
+  TEST (2, 4, 3, 2)
+  TEST (3, 4, 3, 2)
+  TEST (4, 4, 3, 2)
+  TEST (5, 4, 3, 2)
+  TEST (6, 4, 3, 2)
+  TEST (7, 4, 3, 2)
+  TEST (0, 5, 3, 2)
+  TEST (1, 5, 3, 2)
+  TEST (2, 5, 3, 2)
+  TEST (3, 5, 3, 2)
+  TEST (4, 5, 3, 2)
+  TEST (5, 5, 3, 2)
+  TEST (6, 5, 3, 2)
+  TEST (7, 5, 3, 2)
+  TEST (0, 6, 3, 2)
+  TEST (1, 6, 3, 2)
+  TEST (2, 6, 3, 2)
+  TEST (3, 6, 3, 2)
+  TEST (4, 6, 3, 2)
+  TEST (5, 6, 3, 2)
+  TEST (6, 6, 3, 2)
+  TEST (7, 6, 3, 2)
+  TEST (0, 7, 3, 2)
+  TEST (1, 7, 3, 2)
+  TEST (2, 7, 3, 2)
+  TEST (3, 7, 3, 2)
+  TEST (4, 7, 3, 2)
+  TEST (5, 7, 3, 2)
+  TEST (6, 7, 3, 2)
+  TEST (7, 7, 3, 2)
+}
+
+void check10(void)
+{
+  TEST (0, 0, 4, 2)
+  TEST (1, 0, 4, 2)
+  TEST (2, 0, 4, 2)
+  TEST (3, 0, 4, 2)
+  TEST (4, 0, 4, 2)
+  TEST (5, 0, 4, 2)
+  TEST (6, 0, 4, 2)
+  TEST (7, 0, 4, 2)
+  TEST (0, 1, 4, 2)
+  TEST (1, 1, 4, 2)
+  TEST (2, 1, 4, 2)
+  TEST (3, 1, 4, 2)
+  TEST (4, 1, 4, 2)
+  TEST (5, 1, 4, 2)
+  TEST (6, 1, 4, 2)
+  TEST (7, 1, 4, 2)
+  TEST (0, 2, 4, 2)
+  TEST (1, 2, 4, 2)
+  TEST (2, 2, 4, 2)
+  TEST (3, 2, 4, 2)
+  TEST (4, 2, 4, 2)
+  TEST (5, 2, 4, 2)
+  TEST (6, 2, 4, 2)
+  TEST (7, 2, 4, 2)
+  TEST (0, 3, 4, 2)
+  TEST (1, 3, 4, 2)
+  TEST (2, 3, 4, 2)
+  TEST (3, 3, 4, 2)
+  TEST (4, 3, 4, 2)
+  TEST (5, 3, 4, 2)
+  TEST (6, 3, 4, 2)
+  TEST (7, 3, 4, 2)
+  TEST (0, 4, 4, 2)
+  TEST (1, 4, 4, 2)
+  TEST (2, 4, 4, 2)
+  TEST (3, 4, 4, 2)
+  TEST (4, 4, 4, 2)
+  TEST (5, 4, 4, 2)
+  TEST (6, 4, 4, 2)
+  TEST (7, 4, 4, 2)
+  TEST (0, 5, 4, 2)
+  TEST (1, 5, 4, 2)
+  TEST (2, 5, 4, 2)
+  TEST (3, 5, 4, 2)
+  TEST (4, 5, 4, 2)
+  TEST (5, 5, 4, 2)
+  TEST (6, 5, 4, 2)
+  TEST (7, 5, 4, 2)
+  TEST (0, 6, 4, 2)
+  TEST (1, 6, 4, 2)
+  TEST (2, 6, 4, 2)
+  TEST (3, 6, 4, 2)
+  TEST (4, 6, 4, 2)
+  TEST (5, 6, 4, 2)
+  TEST (6, 6, 4, 2)
+  TEST (7, 6, 4, 2)
+  TEST (0, 7, 4, 2)
+  TEST (1, 7, 4, 2)
+  TEST (2, 7, 4, 2)
+  TEST (3, 7, 4, 2)
+  TEST (4, 7, 4, 2)
+  TEST (5, 7, 4, 2)
+  TEST (6, 7, 4, 2)
+  TEST (7, 7, 4, 2)
+  TEST (0, 0, 5, 2)
+  TEST (1, 0, 5, 2)
+  TEST (2, 0, 5, 2)
+  TEST (3, 0, 5, 2)
+  TEST (4, 0, 5, 2)
+  TEST (5, 0, 5, 2)
+  TEST (6, 0, 5, 2)
+  TEST (7, 0, 5, 2)
+  TEST (0, 1, 5, 2)
+  TEST (1, 1, 5, 2)
+  TEST (2, 1, 5, 2)
+  TEST (3, 1, 5, 2)
+  TEST (4, 1, 5, 2)
+  TEST (5, 1, 5, 2)
+  TEST (6, 1, 5, 2)
+  TEST (7, 1, 5, 2)
+  TEST (0, 2, 5, 2)
+  TEST (1, 2, 5, 2)
+  TEST (2, 2, 5, 2)
+  TEST (3, 2, 5, 2)
+  TEST (4, 2, 5, 2)
+  TEST (5, 2, 5, 2)
+  TEST (6, 2, 5, 2)
+  TEST (7, 2, 5, 2)
+  TEST (0, 3, 5, 2)
+  TEST (1, 3, 5, 2)
+  TEST (2, 3, 5, 2)
+  TEST (3, 3, 5, 2)
+  TEST (4, 3, 5, 2)
+  TEST (5, 3, 5, 2)
+  TEST (6, 3, 5, 2)
+  TEST (7, 3, 5, 2)
+  TEST (0, 4, 5, 2)
+  TEST (1, 4, 5, 2)
+  TEST (2, 4, 5, 2)
+  TEST (3, 4, 5, 2)
+  TEST (4, 4, 5, 2)
+  TEST (5, 4, 5, 2)
+  TEST (6, 4, 5, 2)
+  TEST (7, 4, 5, 2)
+  TEST (0, 5, 5, 2)
+  TEST (1, 5, 5, 2)
+  TEST (2, 5, 5, 2)
+  TEST (3, 5, 5, 2)
+  TEST (4, 5, 5, 2)
+  TEST (5, 5, 5, 2)
+  TEST (6, 5, 5, 2)
+  TEST (7, 5, 5, 2)
+  TEST (0, 6, 5, 2)
+  TEST (1, 6, 5, 2)
+  TEST (2, 6, 5, 2)
+  TEST (3, 6, 5, 2)
+  TEST (4, 6, 5, 2)
+  TEST (5, 6, 5, 2)
+  TEST (6, 6, 5, 2)
+  TEST (7, 6, 5, 2)
+  TEST (0, 7, 5, 2)
+  TEST (1, 7, 5, 2)
+  TEST (2, 7, 5, 2)
+  TEST (3, 7, 5, 2)
+  TEST (4, 7, 5, 2)
+  TEST (5, 7, 5, 2)
+  TEST (6, 7, 5, 2)
+  TEST (7, 7, 5, 2)
+}
+
+void check11(void)
+{
+  TEST (0, 0, 6, 2)
+  TEST (1, 0, 6, 2)
+  TEST (2, 0, 6, 2)
+  TEST (3, 0, 6, 2)
+  TEST (4, 0, 6, 2)
+  TEST (5, 0, 6, 2)
+  TEST (6, 0, 6, 2)
+  TEST (7, 0, 6, 2)
+  TEST (0, 1, 6, 2)
+  TEST (1, 1, 6, 2)
+  TEST (2, 1, 6, 2)
+  TEST (3, 1, 6, 2)
+  TEST (4, 1, 6, 2)
+  TEST (5, 1, 6, 2)
+  TEST (6, 1, 6, 2)
+  TEST (7, 1, 6, 2)
+  TEST (0, 2, 6, 2)
+  TEST (1, 2, 6, 2)
+  TEST (2, 2, 6, 2)
+  TEST (3, 2, 6, 2)
+  TEST (4, 2, 6, 2)
+  TEST (5, 2, 6, 2)
+  TEST (6, 2, 6, 2)
+  TEST (7, 2, 6, 2)
+  TEST (0, 3, 6, 2)
+  TEST (1, 3, 6, 2)
+  TEST (2, 3, 6, 2)
+  TEST (3, 3, 6, 2)
+  TEST (4, 3, 6, 2)
+  TEST (5, 3, 6, 2)
+  TEST (6, 3, 6, 2)
+  TEST (7, 3, 6, 2)
+  TEST (0, 4, 6, 2)
+  TEST (1, 4, 6, 2)
+  TEST (2, 4, 6, 2)
+  TEST (3, 4, 6, 2)
+  TEST (4, 4, 6, 2)
+  TEST (5, 4, 6, 2)
+  TEST (6, 4, 6, 2)
+  TEST (7, 4, 6, 2)
+  TEST (0, 5, 6, 2)
+  TEST (1, 5, 6, 2)
+  TEST (2, 5, 6, 2)
+  TEST (3, 5, 6, 2)
+  TEST (4, 5, 6, 2)
+  TEST (5, 5, 6, 2)
+  TEST (6, 5, 6, 2)
+  TEST (7, 5, 6, 2)
+  TEST (0, 6, 6, 2)
+  TEST (1, 6, 6, 2)
+  TEST (2, 6, 6, 2)
+  TEST (3, 6, 6, 2)
+  TEST (4, 6, 6, 2)
+  TEST (5, 6, 6, 2)
+  TEST (6, 6, 6, 2)
+  TEST (7, 6, 6, 2)
+  TEST (0, 7, 6, 2)
+  TEST (1, 7, 6, 2)
+  TEST (2, 7, 6, 2)
+  TEST (3, 7, 6, 2)
+  TEST (4, 7, 6, 2)
+  TEST (5, 7, 6, 2)
+  TEST (6, 7, 6, 2)
+  TEST (7, 7, 6, 2)
+  TEST (0, 0, 7, 2)
+  TEST (1, 0, 7, 2)
+  TEST (2, 0, 7, 2)
+  TEST (3, 0, 7, 2)
+  TEST (4, 0, 7, 2)
+  TEST (5, 0, 7, 2)
+  TEST (6, 0, 7, 2)
+  TEST (7, 0, 7, 2)
+  TEST (0, 1, 7, 2)
+  TEST (1, 1, 7, 2)
+  TEST (2, 1, 7, 2)
+  TEST (3, 1, 7, 2)
+  TEST (4, 1, 7, 2)
+  TEST (5, 1, 7, 2)
+  TEST (6, 1, 7, 2)
+  TEST (7, 1, 7, 2)
+  TEST (0, 2, 7, 2)
+  TEST (1, 2, 7, 2)
+  TEST (2, 2, 7, 2)
+  TEST (3, 2, 7, 2)
+  TEST (4, 2, 7, 2)
+  TEST (5, 2, 7, 2)
+  TEST (6, 2, 7, 2)
+  TEST (7, 2, 7, 2)
+  TEST (0, 3, 7, 2)
+  TEST (1, 3, 7, 2)
+  TEST (2, 3, 7, 2)
+  TEST (3, 3, 7, 2)
+  TEST (4, 3, 7, 2)
+  TEST (5, 3, 7, 2)
+  TEST (6, 3, 7, 2)
+  TEST (7, 3, 7, 2)
+  TEST (0, 4, 7, 2)
+  TEST (1, 4, 7, 2)
+  TEST (2, 4, 7, 2)
+  TEST (3, 4, 7, 2)
+  TEST (4, 4, 7, 2)
+  TEST (5, 4, 7, 2)
+  TEST (6, 4, 7, 2)
+  TEST (7, 4, 7, 2)
+  TEST (0, 5, 7, 2)
+  TEST (1, 5, 7, 2)
+  TEST (2, 5, 7, 2)
+  TEST (3, 5, 7, 2)
+  TEST (4, 5, 7, 2)
+  TEST (5, 5, 7, 2)
+  TEST (6, 5, 7, 2)
+  TEST (7, 5, 7, 2)
+  TEST (0, 6, 7, 2)
+  TEST (1, 6, 7, 2)
+  TEST (2, 6, 7, 2)
+  TEST (3, 6, 7, 2)
+  TEST (4, 6, 7, 2)
+  TEST (5, 6, 7, 2)
+  TEST (6, 6, 7, 2)
+  TEST (7, 6, 7, 2)
+  TEST (0, 7, 7, 2)
+  TEST (1, 7, 7, 2)
+  TEST (2, 7, 7, 2)
+  TEST (3, 7, 7, 2)
+  TEST (4, 7, 7, 2)
+  TEST (5, 7, 7, 2)
+  TEST (6, 7, 7, 2)
+  TEST (7, 7, 7, 2)
+}
+
+void check12(void)
+{
+  TEST (0, 0, 0, 3)
+  TEST (1, 0, 0, 3)
+  TEST (2, 0, 0, 3)
+  TEST (3, 0, 0, 3)
+  TEST (4, 0, 0, 3)
+  TEST (5, 0, 0, 3)
+  TEST (6, 0, 0, 3)
+  TEST (7, 0, 0, 3)
+  TEST (0, 1, 0, 3)
+  TEST (1, 1, 0, 3)
+  TEST (2, 1, 0, 3)
+  TEST (3, 1, 0, 3)
+  TEST (4, 1, 0, 3)
+  TEST (5, 1, 0, 3)
+  TEST (6, 1, 0, 3)
+  TEST (7, 1, 0, 3)
+  TEST (0, 2, 0, 3)
+  TEST (1, 2, 0, 3)
+  TEST (2, 2, 0, 3)
+  TEST (3, 2, 0, 3)
+  TEST (4, 2, 0, 3)
+  TEST (5, 2, 0, 3)
+  TEST (6, 2, 0, 3)
+  TEST (7, 2, 0, 3)
+  TEST (0, 3, 0, 3)
+  TEST (1, 3, 0, 3)
+  TEST (2, 3, 0, 3)
+  TEST (3, 3, 0, 3)
+  TEST (4, 3, 0, 3)
+  TEST (5, 3, 0, 3)
+  TEST (6, 3, 0, 3)
+  TEST (7, 3, 0, 3)
+  TEST (0, 4, 0, 3)
+  TEST (1, 4, 0, 3)
+  TEST (2, 4, 0, 3)
+  TEST (3, 4, 0, 3)
+  TEST (4, 4, 0, 3)
+  TEST (5, 4, 0, 3)
+  TEST (6, 4, 0, 3)
+  TEST (7, 4, 0, 3)
+  TEST (0, 5, 0, 3)
+  TEST (1, 5, 0, 3)
+  TEST (2, 5, 0, 3)
+  TEST (3, 5, 0, 3)
+  TEST (4, 5, 0, 3)
+  TEST (5, 5, 0, 3)
+  TEST (6, 5, 0, 3)
+  TEST (7, 5, 0, 3)
+  TEST (0, 6, 0, 3)
+  TEST (1, 6, 0, 3)
+  TEST (2, 6, 0, 3)
+  TEST (3, 6, 0, 3)
+  TEST (4, 6, 0, 3)
+  TEST (5, 6, 0, 3)
+  TEST (6, 6, 0, 3)
+  TEST (7, 6, 0, 3)
+  TEST (0, 7, 0, 3)
+  TEST (1, 7, 0, 3)
+  TEST (2, 7, 0, 3)
+  TEST (3, 7, 0, 3)
+  TEST (4, 7, 0, 3)
+  TEST (5, 7, 0, 3)
+  TEST (6, 7, 0, 3)
+  TEST (7, 7, 0, 3)
+  TEST (0, 0, 1, 3)
+  TEST (1, 0, 1, 3)
+  TEST (2, 0, 1, 3)
+  TEST (3, 0, 1, 3)
+  TEST (4, 0, 1, 3)
+  TEST (5, 0, 1, 3)
+  TEST (6, 0, 1, 3)
+  TEST (7, 0, 1, 3)
+  TEST (0, 1, 1, 3)
+  TEST (1, 1, 1, 3)
+  TEST (2, 1, 1, 3)
+  TEST (3, 1, 1, 3)
+  TEST (4, 1, 1, 3)
+  TEST (5, 1, 1, 3)
+  TEST (6, 1, 1, 3)
+  TEST (7, 1, 1, 3)
+  TEST (0, 2, 1, 3)
+  TEST (1, 2, 1, 3)
+  TEST (2, 2, 1, 3)
+  TEST (3, 2, 1, 3)
+  TEST (4, 2, 1, 3)
+  TEST (5, 2, 1, 3)
+  TEST (6, 2, 1, 3)
+  TEST (7, 2, 1, 3)
+  TEST (0, 3, 1, 3)
+  TEST (1, 3, 1, 3)
+  TEST (2, 3, 1, 3)
+  TEST (3, 3, 1, 3)
+  TEST (4, 3, 1, 3)
+  TEST (5, 3, 1, 3)
+  TEST (6, 3, 1, 3)
+  TEST (7, 3, 1, 3)
+  TEST (0, 4, 1, 3)
+  TEST (1, 4, 1, 3)
+  TEST (2, 4, 1, 3)
+  TEST (3, 4, 1, 3)
+  TEST (4, 4, 1, 3)
+  TEST (5, 4, 1, 3)
+  TEST (6, 4, 1, 3)
+  TEST (7, 4, 1, 3)
+  TEST (0, 5, 1, 3)
+  TEST (1, 5, 1, 3)
+  TEST (2, 5, 1, 3)
+  TEST (3, 5, 1, 3)
+  TEST (4, 5, 1, 3)
+  TEST (5, 5, 1, 3)
+  TEST (6, 5, 1, 3)
+  TEST (7, 5, 1, 3)
+  TEST (0, 6, 1, 3)
+  TEST (1, 6, 1, 3)
+  TEST (2, 6, 1, 3)
+  TEST (3, 6, 1, 3)
+  TEST (4, 6, 1, 3)
+  TEST (5, 6, 1, 3)
+  TEST (6, 6, 1, 3)
+  TEST (7, 6, 1, 3)
+  TEST (0, 7, 1, 3)
+  TEST (1, 7, 1, 3)
+  TEST (2, 7, 1, 3)
+  TEST (3, 7, 1, 3)
+  TEST (4, 7, 1, 3)
+  TEST (5, 7, 1, 3)
+  TEST (6, 7, 1, 3)
+  TEST (7, 7, 1, 3)
+}
+
+void check13(void)
+{
+  TEST (0, 0, 2, 3)
+  TEST (1, 0, 2, 3)
+  TEST (2, 0, 2, 3)
+  TEST (3, 0, 2, 3)
+  TEST (4, 0, 2, 3)
+  TEST (5, 0, 2, 3)
+  TEST (6, 0, 2, 3)
+  TEST (7, 0, 2, 3)
+  TEST (0, 1, 2, 3)
+  TEST (1, 1, 2, 3)
+  TEST (2, 1, 2, 3)
+  TEST (3, 1, 2, 3)
+  TEST (4, 1, 2, 3)
+  TEST (5, 1, 2, 3)
+  TEST (6, 1, 2, 3)
+  TEST (7, 1, 2, 3)
+  TEST (0, 2, 2, 3)
+  TEST (1, 2, 2, 3)
+  TEST (2, 2, 2, 3)
+  TEST (3, 2, 2, 3)
+  TEST (4, 2, 2, 3)
+  TEST (5, 2, 2, 3)
+  TEST (6, 2, 2, 3)
+  TEST (7, 2, 2, 3)
+  TEST (0, 3, 2, 3)
+  TEST (1, 3, 2, 3)
+  TEST (2, 3, 2, 3)
+  TEST (3, 3, 2, 3)
+  TEST (4, 3, 2, 3)
+  TEST (5, 3, 2, 3)
+  TEST (6, 3, 2, 3)
+  TEST (7, 3, 2, 3)
+  TEST (0, 4, 2, 3)
+  TEST (1, 4, 2, 3)
+  TEST (2, 4, 2, 3)
+  TEST (3, 4, 2, 3)
+  TEST (4, 4, 2, 3)
+  TEST (5, 4, 2, 3)
+  TEST (6, 4, 2, 3)
+  TEST (7, 4, 2, 3)
+  TEST (0, 5, 2, 3)
+  TEST (1, 5, 2, 3)
+  TEST (2, 5, 2, 3)
+  TEST (3, 5, 2, 3)
+  TEST (4, 5, 2, 3)
+  TEST (5, 5, 2, 3)
+  TEST (6, 5, 2, 3)
+  TEST (7, 5, 2, 3)
+  TEST (0, 6, 2, 3)
+  TEST (1, 6, 2, 3)
+  TEST (2, 6, 2, 3)
+  TEST (3, 6, 2, 3)
+  TEST (4, 6, 2, 3)
+  TEST (5, 6, 2, 3)
+  TEST (6, 6, 2, 3)
+  TEST (7, 6, 2, 3)
+  TEST (0, 7, 2, 3)
+  TEST (1, 7, 2, 3)
+  TEST (2, 7, 2, 3)
+  TEST (3, 7, 2, 3)
+  TEST (4, 7, 2, 3)
+  TEST (5, 7, 2, 3)
+  TEST (6, 7, 2, 3)
+  TEST (7, 7, 2, 3)
+  TEST (0, 0, 3, 3)
+  TEST (1, 0, 3, 3)
+  TEST (2, 0, 3, 3)
+  TEST (3, 0, 3, 3)
+  TEST (4, 0, 3, 3)
+  TEST (5, 0, 3, 3)
+  TEST (6, 0, 3, 3)
+  TEST (7, 0, 3, 3)
+  TEST (0, 1, 3, 3)
+  TEST (1, 1, 3, 3)
+  TEST (2, 1, 3, 3)
+  TEST (3, 1, 3, 3)
+  TEST (4, 1, 3, 3)
+  TEST (5, 1, 3, 3)
+  TEST (6, 1, 3, 3)
+  TEST (7, 1, 3, 3)
+  TEST (0, 2, 3, 3)
+  TEST (1, 2, 3, 3)
+  TEST (2, 2, 3, 3)
+  TEST (3, 2, 3, 3)
+  TEST (4, 2, 3, 3)
+  TEST (5, 2, 3, 3)
+  TEST (6, 2, 3, 3)
+  TEST (7, 2, 3, 3)
+  TEST (0, 3, 3, 3)
+  TEST (1, 3, 3, 3)
+  TEST (2, 3, 3, 3)
+  TEST (3, 3, 3, 3)
+  TEST (4, 3, 3, 3)
+  TEST (5, 3, 3, 3)
+  TEST (6, 3, 3, 3)
+  TEST (7, 3, 3, 3)
+  TEST (0, 4, 3, 3)
+  TEST (1, 4, 3, 3)
+  TEST (2, 4, 3, 3)
+  TEST (3, 4, 3, 3)
+  TEST (4, 4, 3, 3)
+  TEST (5, 4, 3, 3)
+  TEST (6, 4, 3, 3)
+  TEST (7, 4, 3, 3)
+  TEST (0, 5, 3, 3)
+  TEST (1, 5, 3, 3)
+  TEST (2, 5, 3, 3)
+  TEST (3, 5, 3, 3)
+  TEST (4, 5, 3, 3)
+  TEST (5, 5, 3, 3)
+  TEST (6, 5, 3, 3)
+  TEST (7, 5, 3, 3)
+  TEST (0, 6, 3, 3)
+  TEST (1, 6, 3, 3)
+  TEST (2, 6, 3, 3)
+  TEST (3, 6, 3, 3)
+  TEST (4, 6, 3, 3)
+  TEST (5, 6, 3, 3)
+  TEST (6, 6, 3, 3)
+  TEST (7, 6, 3, 3)
+  TEST (0, 7, 3, 3)
+  TEST (1, 7, 3, 3)
+  TEST (2, 7, 3, 3)
+  TEST (3, 7, 3, 3)
+  TEST (4, 7, 3, 3)
+  TEST (5, 7, 3, 3)
+  TEST (6, 7, 3, 3)
+  TEST (7, 7, 3, 3)
+}
+
+void check14(void)
+{
+  TEST (0, 0, 4, 3)
+  TEST (1, 0, 4, 3)
+  TEST (2, 0, 4, 3)
+  TEST (3, 0, 4, 3)
+  TEST (4, 0, 4, 3)
+  TEST (5, 0, 4, 3)
+  TEST (6, 0, 4, 3)
+  TEST (7, 0, 4, 3)
+  TEST (0, 1, 4, 3)
+  TEST (1, 1, 4, 3)
+  TEST (2, 1, 4, 3)
+  TEST (3, 1, 4, 3)
+  TEST (4, 1, 4, 3)
+  TEST (5, 1, 4, 3)
+  TEST (6, 1, 4, 3)
+  TEST (7, 1, 4, 3)
+  TEST (0, 2, 4, 3)
+  TEST (1, 2, 4, 3)
+  TEST (2, 2, 4, 3)
+  TEST (3, 2, 4, 3)
+  TEST (4, 2, 4, 3)
+  TEST (5, 2, 4, 3)
+  TEST (6, 2, 4, 3)
+  TEST (7, 2, 4, 3)
+  TEST (0, 3, 4, 3)
+  TEST (1, 3, 4, 3)
+  TEST (2, 3, 4, 3)
+  TEST (3, 3, 4, 3)
+  TEST (4, 3, 4, 3)
+  TEST (5, 3, 4, 3)
+  TEST (6, 3, 4, 3)
+  TEST (7, 3, 4, 3)
+  TEST (0, 4, 4, 3)
+  TEST (1, 4, 4, 3)
+  TEST (2, 4, 4, 3)
+  TEST (3, 4, 4, 3)
+  TEST (4, 4, 4, 3)
+  TEST (5, 4, 4, 3)
+  TEST (6, 4, 4, 3)
+  TEST (7, 4, 4, 3)
+  TEST (0, 5, 4, 3)
+  TEST (1, 5, 4, 3)
+  TEST (2, 5, 4, 3)
+  TEST (3, 5, 4, 3)
+  TEST (4, 5, 4, 3)
+  TEST (5, 5, 4, 3)
+  TEST (6, 5, 4, 3)
+  TEST (7, 5, 4, 3)
+  TEST (0, 6, 4, 3)
+  TEST (1, 6, 4, 3)
+  TEST (2, 6, 4, 3)
+  TEST (3, 6, 4, 3)
+  TEST (4, 6, 4, 3)
+  TEST (5, 6, 4, 3)
+  TEST (6, 6, 4, 3)
+  TEST (7, 6, 4, 3)
+  TEST (0, 7, 4, 3)
+  TEST (1, 7, 4, 3)
+  TEST (2, 7, 4, 3)
+  TEST (3, 7, 4, 3)
+  TEST (4, 7, 4, 3)
+  TEST (5, 7, 4, 3)
+  TEST (6, 7, 4, 3)
+  TEST (7, 7, 4, 3)
+  TEST (0, 0, 5, 3)
+  TEST (1, 0, 5, 3)
+  TEST (2, 0, 5, 3)
+  TEST (3, 0, 5, 3)
+  TEST (4, 0, 5, 3)
+  TEST (5, 0, 5, 3)
+  TEST (6, 0, 5, 3)
+  TEST (7, 0, 5, 3)
+  TEST (0, 1, 5, 3)
+  TEST (1, 1, 5, 3)
+  TEST (2, 1, 5, 3)
+  TEST (3, 1, 5, 3)
+  TEST (4, 1, 5, 3)
+  TEST (5, 1, 5, 3)
+  TEST (6, 1, 5, 3)
+  TEST (7, 1, 5, 3)
+  TEST (0, 2, 5, 3)
+  TEST (1, 2, 5, 3)
+  TEST (2, 2, 5, 3)
+  TEST (3, 2, 5, 3)
+  TEST (4, 2, 5, 3)
+  TEST (5, 2, 5, 3)
+  TEST (6, 2, 5, 3)
+  TEST (7, 2, 5, 3)
+  TEST (0, 3, 5, 3)
+  TEST (1, 3, 5, 3)
+  TEST (2, 3, 5, 3)
+  TEST (3, 3, 5, 3)
+  TEST (4, 3, 5, 3)
+  TEST (5, 3, 5, 3)
+  TEST (6, 3, 5, 3)
+  TEST (7, 3, 5, 3)
+  TEST (0, 4, 5, 3)
+  TEST (1, 4, 5, 3)
+  TEST (2, 4, 5, 3)
+  TEST (3, 4, 5, 3)
+  TEST (4, 4, 5, 3)
+  TEST (5, 4, 5, 3)
+  TEST (6, 4, 5, 3)
+  TEST (7, 4, 5, 3)
+  TEST (0, 5, 5, 3)
+  TEST (1, 5, 5, 3)
+  TEST (2, 5, 5, 3)
+  TEST (3, 5, 5, 3)
+  TEST (4, 5, 5, 3)
+  TEST (5, 5, 5, 3)
+  TEST (6, 5, 5, 3)
+  TEST (7, 5, 5, 3)
+  TEST (0, 6, 5, 3)
+  TEST (1, 6, 5, 3)
+  TEST (2, 6, 5, 3)
+  TEST (3, 6, 5, 3)
+  TEST (4, 6, 5, 3)
+  TEST (5, 6, 5, 3)
+  TEST (6, 6, 5, 3)
+  TEST (7, 6, 5, 3)
+  TEST (0, 7, 5, 3)
+  TEST (1, 7, 5, 3)
+  TEST (2, 7, 5, 3)
+  TEST (3, 7, 5, 3)
+  TEST (4, 7, 5, 3)
+  TEST (5, 7, 5, 3)
+  TEST (6, 7, 5, 3)
+  TEST (7, 7, 5, 3)
+}
+
+void check15(void)
+{
+  TEST (0, 0, 6, 3)
+  TEST (1, 0, 6, 3)
+  TEST (2, 0, 6, 3)
+  TEST (3, 0, 6, 3)
+  TEST (4, 0, 6, 3)
+  TEST (5, 0, 6, 3)
+  TEST (6, 0, 6, 3)
+  TEST (7, 0, 6, 3)
+  TEST (0, 1, 6, 3)
+  TEST (1, 1, 6, 3)
+  TEST (2, 1, 6, 3)
+  TEST (3, 1, 6, 3)
+  TEST (4, 1, 6, 3)
+  TEST (5, 1, 6, 3)
+  TEST (6, 1, 6, 3)
+  TEST (7, 1, 6, 3)
+  TEST (0, 2, 6, 3)
+  TEST (1, 2, 6, 3)
+  TEST (2, 2, 6, 3)
+  TEST (3, 2, 6, 3)
+  TEST (4, 2, 6, 3)
+  TEST (5, 2, 6, 3)
+  TEST (6, 2, 6, 3)
+  TEST (7, 2, 6, 3)
+  TEST (0, 3, 6, 3)
+  TEST (1, 3, 6, 3)
+  TEST (2, 3, 6, 3)
+  TEST (3, 3, 6, 3)
+  TEST (4, 3, 6, 3)
+  TEST (5, 3, 6, 3)
+  TEST (6, 3, 6, 3)
+  TEST (7, 3, 6, 3)
+  TEST (0, 4, 6, 3)
+  TEST (1, 4, 6, 3)
+  TEST (2, 4, 6, 3)
+  TEST (3, 4, 6, 3)
+  TEST (4, 4, 6, 3)
+  TEST (5, 4, 6, 3)
+  TEST (6, 4, 6, 3)
+  TEST (7, 4, 6, 3)
+  TEST (0, 5, 6, 3)
+  TEST (1, 5, 6, 3)
+  TEST (2, 5, 6, 3)
+  TEST (3, 5, 6, 3)
+  TEST (4, 5, 6, 3)
+  TEST (5, 5, 6, 3)
+  TEST (6, 5, 6, 3)
+  TEST (7, 5, 6, 3)
+  TEST (0, 6, 6, 3)
+  TEST (1, 6, 6, 3)
+  TEST (2, 6, 6, 3)
+  TEST (3, 6, 6, 3)
+  TEST (4, 6, 6, 3)
+  TEST (5, 6, 6, 3)
+  TEST (6, 6, 6, 3)
+  TEST (7, 6, 6, 3)
+  TEST (0, 7, 6, 3)
+  TEST (1, 7, 6, 3)
+  TEST (2, 7, 6, 3)
+  TEST (3, 7, 6, 3)
+  TEST (4, 7, 6, 3)
+  TEST (5, 7, 6, 3)
+  TEST (6, 7, 6, 3)
+  TEST (7, 7, 6, 3)
+  TEST (0, 0, 7, 3)
+  TEST (1, 0, 7, 3)
+  TEST (2, 0, 7, 3)
+  TEST (3, 0, 7, 3)
+  TEST (4, 0, 7, 3)
+  TEST (5, 0, 7, 3)
+  TEST (6, 0, 7, 3)
+  TEST (7, 0, 7, 3)
+  TEST (0, 1, 7, 3)
+  TEST (1, 1, 7, 3)
+  TEST (2, 1, 7, 3)
+  TEST (3, 1, 7, 3)
+  TEST (4, 1, 7, 3)
+  TEST (5, 1, 7, 3)
+  TEST (6, 1, 7, 3)
+  TEST (7, 1, 7, 3)
+  TEST (0, 2, 7, 3)
+  TEST (1, 2, 7, 3)
+  TEST (2, 2, 7, 3)
+  TEST (3, 2, 7, 3)
+  TEST (4, 2, 7, 3)
+  TEST (5, 2, 7, 3)
+  TEST (6, 2, 7, 3)
+  TEST (7, 2, 7, 3)
+  TEST (0, 3, 7, 3)
+  TEST (1, 3, 7, 3)
+  TEST (2, 3, 7, 3)
+  TEST (3, 3, 7, 3)
+  TEST (4, 3, 7, 3)
+  TEST (5, 3, 7, 3)
+  TEST (6, 3, 7, 3)
+  TEST (7, 3, 7, 3)
+  TEST (0, 4, 7, 3)
+  TEST (1, 4, 7, 3)
+  TEST (2, 4, 7, 3)
+  TEST (3, 4, 7, 3)
+  TEST (4, 4, 7, 3)
+  TEST (5, 4, 7, 3)
+  TEST (6, 4, 7, 3)
+  TEST (7, 4, 7, 3)
+  TEST (0, 5, 7, 3)
+  TEST (1, 5, 7, 3)
+  TEST (2, 5, 7, 3)
+  TEST (3, 5, 7, 3)
+  TEST (4, 5, 7, 3)
+  TEST (5, 5, 7, 3)
+  TEST (6, 5, 7, 3)
+  TEST (7, 5, 7, 3)
+  TEST (0, 6, 7, 3)
+  TEST (1, 6, 7, 3)
+  TEST (2, 6, 7, 3)
+  TEST (3, 6, 7, 3)
+  TEST (4, 6, 7, 3)
+  TEST (5, 6, 7, 3)
+  TEST (6, 6, 7, 3)
+  TEST (7, 6, 7, 3)
+  TEST (0, 7, 7, 3)
+  TEST (1, 7, 7, 3)
+  TEST (2, 7, 7, 3)
+  TEST (3, 7, 7, 3)
+  TEST (4, 7, 7, 3)
+  TEST (5, 7, 7, 3)
+  TEST (6, 7, 7, 3)
+  TEST (7, 7, 7, 3)
+}
+
+void check16(void)
+{
+  TEST (0, 0, 0, 4)
+  TEST (1, 0, 0, 4)
+  TEST (2, 0, 0, 4)
+  TEST (3, 0, 0, 4)
+  TEST (4, 0, 0, 4)
+  TEST (5, 0, 0, 4)
+  TEST (6, 0, 0, 4)
+  TEST (7, 0, 0, 4)
+  TEST (0, 1, 0, 4)
+  TEST (1, 1, 0, 4)
+  TEST (2, 1, 0, 4)
+  TEST (3, 1, 0, 4)
+  TEST (4, 1, 0, 4)
+  TEST (5, 1, 0, 4)
+  TEST (6, 1, 0, 4)
+  TEST (7, 1, 0, 4)
+  TEST (0, 2, 0, 4)
+  TEST (1, 2, 0, 4)
+  TEST (2, 2, 0, 4)
+  TEST (3, 2, 0, 4)
+  TEST (4, 2, 0, 4)
+  TEST (5, 2, 0, 4)
+  TEST (6, 2, 0, 4)
+  TEST (7, 2, 0, 4)
+  TEST (0, 3, 0, 4)
+  TEST (1, 3, 0, 4)
+  TEST (2, 3, 0, 4)
+  TEST (3, 3, 0, 4)
+  TEST (4, 3, 0, 4)
+  TEST (5, 3, 0, 4)
+  TEST (6, 3, 0, 4)
+  TEST (7, 3, 0, 4)
+  TEST (0, 4, 0, 4)
+  TEST (1, 4, 0, 4)
+  TEST (2, 4, 0, 4)
+  TEST (3, 4, 0, 4)
+  TEST (4, 4, 0, 4)
+  TEST (5, 4, 0, 4)
+  TEST (6, 4, 0, 4)
+  TEST (7, 4, 0, 4)
+  TEST (0, 5, 0, 4)
+  TEST (1, 5, 0, 4)
+  TEST (2, 5, 0, 4)
+  TEST (3, 5, 0, 4)
+  TEST (4, 5, 0, 4)
+  TEST (5, 5, 0, 4)
+  TEST (6, 5, 0, 4)
+  TEST (7, 5, 0, 4)
+  TEST (0, 6, 0, 4)
+  TEST (1, 6, 0, 4)
+  TEST (2, 6, 0, 4)
+  TEST (3, 6, 0, 4)
+  TEST (4, 6, 0, 4)
+  TEST (5, 6, 0, 4)
+  TEST (6, 6, 0, 4)
+  TEST (7, 6, 0, 4)
+  TEST (0, 7, 0, 4)
+  TEST (1, 7, 0, 4)
+  TEST (2, 7, 0, 4)
+  TEST (3, 7, 0, 4)
+  TEST (4, 7, 0, 4)
+  TEST (5, 7, 0, 4)
+  TEST (6, 7, 0, 4)
+  TEST (7, 7, 0, 4)
+  TEST (0, 0, 1, 4)
+  TEST (1, 0, 1, 4)
+  TEST (2, 0, 1, 4)
+  TEST (3, 0, 1, 4)
+  TEST (4, 0, 1, 4)
+  TEST (5, 0, 1, 4)
+  TEST (6, 0, 1, 4)
+  TEST (7, 0, 1, 4)
+  TEST (0, 1, 1, 4)
+  TEST (1, 1, 1, 4)
+  TEST (2, 1, 1, 4)
+  TEST (3, 1, 1, 4)
+  TEST (4, 1, 1, 4)
+  TEST (5, 1, 1, 4)
+  TEST (6, 1, 1, 4)
+  TEST (7, 1, 1, 4)
+  TEST (0, 2, 1, 4)
+  TEST (1, 2, 1, 4)
+  TEST (2, 2, 1, 4)
+  TEST (3, 2, 1, 4)
+  TEST (4, 2, 1, 4)
+  TEST (5, 2, 1, 4)
+  TEST (6, 2, 1, 4)
+  TEST (7, 2, 1, 4)
+  TEST (0, 3, 1, 4)
+  TEST (1, 3, 1, 4)
+  TEST (2, 3, 1, 4)
+  TEST (3, 3, 1, 4)
+  TEST (4, 3, 1, 4)
+  TEST (5, 3, 1, 4)
+  TEST (6, 3, 1, 4)
+  TEST (7, 3, 1, 4)
+  TEST (0, 4, 1, 4)
+  TEST (1, 4, 1, 4)
+  TEST (2, 4, 1, 4)
+  TEST (3, 4, 1, 4)
+  TEST (4, 4, 1, 4)
+  TEST (5, 4, 1, 4)
+  TEST (6, 4, 1, 4)
+  TEST (7, 4, 1, 4)
+  TEST (0, 5, 1, 4)
+  TEST (1, 5, 1, 4)
+  TEST (2, 5, 1, 4)
+  TEST (3, 5, 1, 4)
+  TEST (4, 5, 1, 4)
+  TEST (5, 5, 1, 4)
+  TEST (6, 5, 1, 4)
+  TEST (7, 5, 1, 4)
+  TEST (0, 6, 1, 4)
+  TEST (1, 6, 1, 4)
+  TEST (2, 6, 1, 4)
+  TEST (3, 6, 1, 4)
+  TEST (4, 6, 1, 4)
+  TEST (5, 6, 1, 4)
+  TEST (6, 6, 1, 4)
+  TEST (7, 6, 1, 4)
+  TEST (0, 7, 1, 4)
+  TEST (1, 7, 1, 4)
+  TEST (2, 7, 1, 4)
+  TEST (3, 7, 1, 4)
+  TEST (4, 7, 1, 4)
+  TEST (5, 7, 1, 4)
+  TEST (6, 7, 1, 4)
+  TEST (7, 7, 1, 4)
+}
+
+void check17(void)
+{
+  TEST (0, 0, 2, 4)
+  TEST (1, 0, 2, 4)
+  TEST (2, 0, 2, 4)
+  TEST (3, 0, 2, 4)
+  TEST (4, 0, 2, 4)
+  TEST (5, 0, 2, 4)
+  TEST (6, 0, 2, 4)
+  TEST (7, 0, 2, 4)
+  TEST (0, 1, 2, 4)
+  TEST (1, 1, 2, 4)
+  TEST (2, 1, 2, 4)
+  TEST (3, 1, 2, 4)
+  TEST (4, 1, 2, 4)
+  TEST (5, 1, 2, 4)
+  TEST (6, 1, 2, 4)
+  TEST (7, 1, 2, 4)
+  TEST (0, 2, 2, 4)
+  TEST (1, 2, 2, 4)
+  TEST (2, 2, 2, 4)
+  TEST (3, 2, 2, 4)
+  TEST (4, 2, 2, 4)
+  TEST (5, 2, 2, 4)
+  TEST (6, 2, 2, 4)
+  TEST (7, 2, 2, 4)
+  TEST (0, 3, 2, 4)
+  TEST (1, 3, 2, 4)
+  TEST (2, 3, 2, 4)
+  TEST (3, 3, 2, 4)
+  TEST (4, 3, 2, 4)
+  TEST (5, 3, 2, 4)
+  TEST (6, 3, 2, 4)
+  TEST (7, 3, 2, 4)
+  TEST (0, 4, 2, 4)
+  TEST (1, 4, 2, 4)
+  TEST (2, 4, 2, 4)
+  TEST (3, 4, 2, 4)
+  TEST (4, 4, 2, 4)
+  TEST (5, 4, 2, 4)
+  TEST (6, 4, 2, 4)
+  TEST (7, 4, 2, 4)
+  TEST (0, 5, 2, 4)
+  TEST (1, 5, 2, 4)
+  TEST (2, 5, 2, 4)
+  TEST (3, 5, 2, 4)
+  TEST (4, 5, 2, 4)
+  TEST (5, 5, 2, 4)
+  TEST (6, 5, 2, 4)
+  TEST (7, 5, 2, 4)
+  TEST (0, 6, 2, 4)
+  TEST (1, 6, 2, 4)
+  TEST (2, 6, 2, 4)
+  TEST (3, 6, 2, 4)
+  TEST (4, 6, 2, 4)
+  TEST (5, 6, 2, 4)
+  TEST (6, 6, 2, 4)
+  TEST (7, 6, 2, 4)
+  TEST (0, 7, 2, 4)
+  TEST (1, 7, 2, 4)
+  TEST (2, 7, 2, 4)
+  TEST (3, 7, 2, 4)
+  TEST (4, 7, 2, 4)
+  TEST (5, 7, 2, 4)
+  TEST (6, 7, 2, 4)
+  TEST (7, 7, 2, 4)
+  TEST (0, 0, 3, 4)
+  TEST (1, 0, 3, 4)
+  TEST (2, 0, 3, 4)
+  TEST (3, 0, 3, 4)
+  TEST (4, 0, 3, 4)
+  TEST (5, 0, 3, 4)
+  TEST (6, 0, 3, 4)
+  TEST (7, 0, 3, 4)
+  TEST (0, 1, 3, 4)
+  TEST (1, 1, 3, 4)
+  TEST (2, 1, 3, 4)
+  TEST (3, 1, 3, 4)
+  TEST (4, 1, 3, 4)
+  TEST (5, 1, 3, 4)
+  TEST (6, 1, 3, 4)
+  TEST (7, 1, 3, 4)
+  TEST (0, 2, 3, 4)
+  TEST (1, 2, 3, 4)
+  TEST (2, 2, 3, 4)
+  TEST (3, 2, 3, 4)
+  TEST (4, 2, 3, 4)
+  TEST (5, 2, 3, 4)
+  TEST (6, 2, 3, 4)
+  TEST (7, 2, 3, 4)
+  TEST (0, 3, 3, 4)
+  TEST (1, 3, 3, 4)
+  TEST (2, 3, 3, 4)
+  TEST (3, 3, 3, 4)
+  TEST (4, 3, 3, 4)
+  TEST (5, 3, 3, 4)
+  TEST (6, 3, 3, 4)
+  TEST (7, 3, 3, 4)
+  TEST (0, 4, 3, 4)
+  TEST (1, 4, 3, 4)
+  TEST (2, 4, 3, 4)
+  TEST (3, 4, 3, 4)
+  TEST (4, 4, 3, 4)
+  TEST (5, 4, 3, 4)
+  TEST (6, 4, 3, 4)
+  TEST (7, 4, 3, 4)
+  TEST (0, 5, 3, 4)
+  TEST (1, 5, 3, 4)
+  TEST (2, 5, 3, 4)
+  TEST (3, 5, 3, 4)
+  TEST (4, 5, 3, 4)
+  TEST (5, 5, 3, 4)
+  TEST (6, 5, 3, 4)
+  TEST (7, 5, 3, 4)
+  TEST (0, 6, 3, 4)
+  TEST (1, 6, 3, 4)
+  TEST (2, 6, 3, 4)
+  TEST (3, 6, 3, 4)
+  TEST (4, 6, 3, 4)
+  TEST (5, 6, 3, 4)
+  TEST (6, 6, 3, 4)
+  TEST (7, 6, 3, 4)
+  TEST (0, 7, 3, 4)
+  TEST (1, 7, 3, 4)
+  TEST (2, 7, 3, 4)
+  TEST (3, 7, 3, 4)
+  TEST (4, 7, 3, 4)
+  TEST (5, 7, 3, 4)
+  TEST (6, 7, 3, 4)
+  TEST (7, 7, 3, 4)
+}
+
+void check18(void)
+{
+  TEST (0, 0, 4, 4)
+  TEST (1, 0, 4, 4)
+  TEST (2, 0, 4, 4)
+  TEST (3, 0, 4, 4)
+  TEST (4, 0, 4, 4)
+  TEST (5, 0, 4, 4)
+  TEST (6, 0, 4, 4)
+  TEST (7, 0, 4, 4)
+  TEST (0, 1, 4, 4)
+  TEST (1, 1, 4, 4)
+  TEST (2, 1, 4, 4)
+  TEST (3, 1, 4, 4)
+  TEST (4, 1, 4, 4)
+  TEST (5, 1, 4, 4)
+  TEST (6, 1, 4, 4)
+  TEST (7, 1, 4, 4)
+  TEST (0, 2, 4, 4)
+  TEST (1, 2, 4, 4)
+  TEST (2, 2, 4, 4)
+  TEST (3, 2, 4, 4)
+  TEST (4, 2, 4, 4)
+  TEST (5, 2, 4, 4)
+  TEST (6, 2, 4, 4)
+  TEST (7, 2, 4, 4)
+  TEST (0, 3, 4, 4)
+  TEST (1, 3, 4, 4)
+  TEST (2, 3, 4, 4)
+  TEST (3, 3, 4, 4)
+  TEST (4, 3, 4, 4)
+  TEST (5, 3, 4, 4)
+  TEST (6, 3, 4, 4)
+  TEST (7, 3, 4, 4)
+  TEST (0, 4, 4, 4)
+  TEST (1, 4, 4, 4)
+  TEST (2, 4, 4, 4)
+  TEST (3, 4, 4, 4)
+  TEST (4, 4, 4, 4)
+  TEST (5, 4, 4, 4)
+  TEST (6, 4, 4, 4)
+  TEST (7, 4, 4, 4)
+  TEST (0, 5, 4, 4)
+  TEST (1, 5, 4, 4)
+  TEST (2, 5, 4, 4)
+  TEST (3, 5, 4, 4)
+  TEST (4, 5, 4, 4)
+  TEST (5, 5, 4, 4)
+  TEST (6, 5, 4, 4)
+  TEST (7, 5, 4, 4)
+  TEST (0, 6, 4, 4)
+  TEST (1, 6, 4, 4)
+  TEST (2, 6, 4, 4)
+  TEST (3, 6, 4, 4)
+  TEST (4, 6, 4, 4)
+  TEST (5, 6, 4, 4)
+  TEST (6, 6, 4, 4)
+  TEST (7, 6, 4, 4)
+  TEST (0, 7, 4, 4)
+  TEST (1, 7, 4, 4)
+  TEST (2, 7, 4, 4)
+  TEST (3, 7, 4, 4)
+  TEST (4, 7, 4, 4)
+  TEST (5, 7, 4, 4)
+  TEST (6, 7, 4, 4)
+  TEST (7, 7, 4, 4)
+  TEST (0, 0, 5, 4)
+  TEST (1, 0, 5, 4)
+  TEST (2, 0, 5, 4)
+  TEST (3, 0, 5, 4)
+  TEST (4, 0, 5, 4)
+  TEST (5, 0, 5, 4)
+  TEST (6, 0, 5, 4)
+  TEST (7, 0, 5, 4)
+  TEST (0, 1, 5, 4)
+  TEST (1, 1, 5, 4)
+  TEST (2, 1, 5, 4)
+  TEST (3, 1, 5, 4)
+  TEST (4, 1, 5, 4)
+  TEST (5, 1, 5, 4)
+  TEST (6, 1, 5, 4)
+  TEST (7, 1, 5, 4)
+  TEST (0, 2, 5, 4)
+  TEST (1, 2, 5, 4)
+  TEST (2, 2, 5, 4)
+  TEST (3, 2, 5, 4)
+  TEST (4, 2, 5, 4)
+  TEST (5, 2, 5, 4)
+  TEST (6, 2, 5, 4)
+  TEST (7, 2, 5, 4)
+  TEST (0, 3, 5, 4)
+  TEST (1, 3, 5, 4)
+  TEST (2, 3, 5, 4)
+  TEST (3, 3, 5, 4)
+  TEST (4, 3, 5, 4)
+  TEST (5, 3, 5, 4)
+  TEST (6, 3, 5, 4)
+  TEST (7, 3, 5, 4)
+  TEST (0, 4, 5, 4)
+  TEST (1, 4, 5, 4)
+  TEST (2, 4, 5, 4)
+  TEST (3, 4, 5, 4)
+  TEST (4, 4, 5, 4)
+  TEST (5, 4, 5, 4)
+  TEST (6, 4, 5, 4)
+  TEST (7, 4, 5, 4)
+  TEST (0, 5, 5, 4)
+  TEST (1, 5, 5, 4)
+  TEST (2, 5, 5, 4)
+  TEST (3, 5, 5, 4)
+  TEST (4, 5, 5, 4)
+  TEST (5, 5, 5, 4)
+  TEST (6, 5, 5, 4)
+  TEST (7, 5, 5, 4)
+  TEST (0, 6, 5, 4)
+  TEST (1, 6, 5, 4)
+  TEST (2, 6, 5, 4)
+  TEST (3, 6, 5, 4)
+  TEST (4, 6, 5, 4)
+  TEST (5, 6, 5, 4)
+  TEST (6, 6, 5, 4)
+  TEST (7, 6, 5, 4)
+  TEST (0, 7, 5, 4)
+  TEST (1, 7, 5, 4)
+  TEST (2, 7, 5, 4)
+  TEST (3, 7, 5, 4)
+  TEST (4, 7, 5, 4)
+  TEST (5, 7, 5, 4)
+  TEST (6, 7, 5, 4)
+  TEST (7, 7, 5, 4)
+}
+
+void check19(void)
+{
+  TEST (0, 0, 6, 4)
+  TEST (1, 0, 6, 4)
+  TEST (2, 0, 6, 4)
+  TEST (3, 0, 6, 4)
+  TEST (4, 0, 6, 4)
+  TEST (5, 0, 6, 4)
+  TEST (6, 0, 6, 4)
+  TEST (7, 0, 6, 4)
+  TEST (0, 1, 6, 4)
+  TEST (1, 1, 6, 4)
+  TEST (2, 1, 6, 4)
+  TEST (3, 1, 6, 4)
+  TEST (4, 1, 6, 4)
+  TEST (5, 1, 6, 4)
+  TEST (6, 1, 6, 4)
+  TEST (7, 1, 6, 4)
+  TEST (0, 2, 6, 4)
+  TEST (1, 2, 6, 4)
+  TEST (2, 2, 6, 4)
+  TEST (3, 2, 6, 4)
+  TEST (4, 2, 6, 4)
+  TEST (5, 2, 6, 4)
+  TEST (6, 2, 6, 4)
+  TEST (7, 2, 6, 4)
+  TEST (0, 3, 6, 4)
+  TEST (1, 3, 6, 4)
+  TEST (2, 3, 6, 4)
+  TEST (3, 3, 6, 4)
+  TEST (4, 3, 6, 4)
+  TEST (5, 3, 6, 4)
+  TEST (6, 3, 6, 4)
+  TEST (7, 3, 6, 4)
+  TEST (0, 4, 6, 4)
+  TEST (1, 4, 6, 4)
+  TEST (2, 4, 6, 4)
+  TEST (3, 4, 6, 4)
+  TEST (4, 4, 6, 4)
+  TEST (5, 4, 6, 4)
+  TEST (6, 4, 6, 4)
+  TEST (7, 4, 6, 4)
+  TEST (0, 5, 6, 4)
+  TEST (1, 5, 6, 4)
+  TEST (2, 5, 6, 4)
+  TEST (3, 5, 6, 4)
+  TEST (4, 5, 6, 4)
+  TEST (5, 5, 6, 4)
+  TEST (6, 5, 6, 4)
+  TEST (7, 5, 6, 4)
+  TEST (0, 6, 6, 4)
+  TEST (1, 6, 6, 4)
+  TEST (2, 6, 6, 4)
+  TEST (3, 6, 6, 4)
+  TEST (4, 6, 6, 4)
+  TEST (5, 6, 6, 4)
+  TEST (6, 6, 6, 4)
+  TEST (7, 6, 6, 4)
+  TEST (0, 7, 6, 4)
+  TEST (1, 7, 6, 4)
+  TEST (2, 7, 6, 4)
+  TEST (3, 7, 6, 4)
+  TEST (4, 7, 6, 4)
+  TEST (5, 7, 6, 4)
+  TEST (6, 7, 6, 4)
+  TEST (7, 7, 6, 4)
+  TEST (0, 0, 7, 4)
+  TEST (1, 0, 7, 4)
+  TEST (2, 0, 7, 4)
+  TEST (3, 0, 7, 4)
+  TEST (4, 0, 7, 4)
+  TEST (5, 0, 7, 4)
+  TEST (6, 0, 7, 4)
+  TEST (7, 0, 7, 4)
+  TEST (0, 1, 7, 4)
+  TEST (1, 1, 7, 4)
+  TEST (2, 1, 7, 4)
+  TEST (3, 1, 7, 4)
+  TEST (4, 1, 7, 4)
+  TEST (5, 1, 7, 4)
+  TEST (6, 1, 7, 4)
+  TEST (7, 1, 7, 4)
+  TEST (0, 2, 7, 4)
+  TEST (1, 2, 7, 4)
+  TEST (2, 2, 7, 4)
+  TEST (3, 2, 7, 4)
+  TEST (4, 2, 7, 4)
+  TEST (5, 2, 7, 4)
+  TEST (6, 2, 7, 4)
+  TEST (7, 2, 7, 4)
+  TEST (0, 3, 7, 4)
+  TEST (1, 3, 7, 4)
+  TEST (2, 3, 7, 4)
+  TEST (3, 3, 7, 4)
+  TEST (4, 3, 7, 4)
+  TEST (5, 3, 7, 4)
+  TEST (6, 3, 7, 4)
+  TEST (7, 3, 7, 4)
+  TEST (0, 4, 7, 4)
+  TEST (1, 4, 7, 4)
+  TEST (2, 4, 7, 4)
+  TEST (3, 4, 7, 4)
+  TEST (4, 4, 7, 4)
+  TEST (5, 4, 7, 4)
+  TEST (6, 4, 7, 4)
+  TEST (7, 4, 7, 4)
+  TEST (0, 5, 7, 4)
+  TEST (1, 5, 7, 4)
+  TEST (2, 5, 7, 4)
+  TEST (3, 5, 7, 4)
+  TEST (4, 5, 7, 4)
+  TEST (5, 5, 7, 4)
+  TEST (6, 5, 7, 4)
+  TEST (7, 5, 7, 4)
+  TEST (0, 6, 7, 4)
+  TEST (1, 6, 7, 4)
+  TEST (2, 6, 7, 4)
+  TEST (3, 6, 7, 4)
+  TEST (4, 6, 7, 4)
+  TEST (5, 6, 7, 4)
+  TEST (6, 6, 7, 4)
+  TEST (7, 6, 7, 4)
+  TEST (0, 7, 7, 4)
+  TEST (1, 7, 7, 4)
+  TEST (2, 7, 7, 4)
+  TEST (3, 7, 7, 4)
+  TEST (4, 7, 7, 4)
+  TEST (5, 7, 7, 4)
+  TEST (6, 7, 7, 4)
+  TEST (7, 7, 7, 4)
+}
+
+void check20(void)
+{
+  TEST (0, 0, 0, 5)
+  TEST (1, 0, 0, 5)
+  TEST (2, 0, 0, 5)
+  TEST (3, 0, 0, 5)
+  TEST (4, 0, 0, 5)
+  TEST (5, 0, 0, 5)
+  TEST (6, 0, 0, 5)
+  TEST (7, 0, 0, 5)
+  TEST (0, 1, 0, 5)
+  TEST (1, 1, 0, 5)
+  TEST (2, 1, 0, 5)
+  TEST (3, 1, 0, 5)
+  TEST (4, 1, 0, 5)
+  TEST (5, 1, 0, 5)
+  TEST (6, 1, 0, 5)
+  TEST (7, 1, 0, 5)
+  TEST (0, 2, 0, 5)
+  TEST (1, 2, 0, 5)
+  TEST (2, 2, 0, 5)
+  TEST (3, 2, 0, 5)
+  TEST (4, 2, 0, 5)
+  TEST (5, 2, 0, 5)
+  TEST (6, 2, 0, 5)
+  TEST (7, 2, 0, 5)
+  TEST (0, 3, 0, 5)
+  TEST (1, 3, 0, 5)
+  TEST (2, 3, 0, 5)
+  TEST (3, 3, 0, 5)
+  TEST (4, 3, 0, 5)
+  TEST (5, 3, 0, 5)
+  TEST (6, 3, 0, 5)
+  TEST (7, 3, 0, 5)
+  TEST (0, 4, 0, 5)
+  TEST (1, 4, 0, 5)
+  TEST (2, 4, 0, 5)
+  TEST (3, 4, 0, 5)
+  TEST (4, 4, 0, 5)
+  TEST (5, 4, 0, 5)
+  TEST (6, 4, 0, 5)
+  TEST (7, 4, 0, 5)
+  TEST (0, 5, 0, 5)
+  TEST (1, 5, 0, 5)
+  TEST (2, 5, 0, 5)
+  TEST (3, 5, 0, 5)
+  TEST (4, 5, 0, 5)
+  TEST (5, 5, 0, 5)
+  TEST (6, 5, 0, 5)
+  TEST (7, 5, 0, 5)
+  TEST (0, 6, 0, 5)
+  TEST (1, 6, 0, 5)
+  TEST (2, 6, 0, 5)
+  TEST (3, 6, 0, 5)
+  TEST (4, 6, 0, 5)
+  TEST (5, 6, 0, 5)
+  TEST (6, 6, 0, 5)
+  TEST (7, 6, 0, 5)
+  TEST (0, 7, 0, 5)
+  TEST (1, 7, 0, 5)
+  TEST (2, 7, 0, 5)
+  TEST (3, 7, 0, 5)
+  TEST (4, 7, 0, 5)
+  TEST (5, 7, 0, 5)
+  TEST (6, 7, 0, 5)
+  TEST (7, 7, 0, 5)
+  TEST (0, 0, 1, 5)
+  TEST (1, 0, 1, 5)
+  TEST (2, 0, 1, 5)
+  TEST (3, 0, 1, 5)
+  TEST (4, 0, 1, 5)
+  TEST (5, 0, 1, 5)
+  TEST (6, 0, 1, 5)
+  TEST (7, 0, 1, 5)
+  TEST (0, 1, 1, 5)
+  TEST (1, 1, 1, 5)
+  TEST (2, 1, 1, 5)
+  TEST (3, 1, 1, 5)
+  TEST (4, 1, 1, 5)
+  TEST (5, 1, 1, 5)
+  TEST (6, 1, 1, 5)
+  TEST (7, 1, 1, 5)
+  TEST (0, 2, 1, 5)
+  TEST (1, 2, 1, 5)
+  TEST (2, 2, 1, 5)
+  TEST (3, 2, 1, 5)
+  TEST (4, 2, 1, 5)
+  TEST (5, 2, 1, 5)
+  TEST (6, 2, 1, 5)
+  TEST (7, 2, 1, 5)
+  TEST (0, 3, 1, 5)
+  TEST (1, 3, 1, 5)
+  TEST (2, 3, 1, 5)
+  TEST (3, 3, 1, 5)
+  TEST (4, 3, 1, 5)
+  TEST (5, 3, 1, 5)
+  TEST (6, 3, 1, 5)
+  TEST (7, 3, 1, 5)
+  TEST (0, 4, 1, 5)
+  TEST (1, 4, 1, 5)
+  TEST (2, 4, 1, 5)
+  TEST (3, 4, 1, 5)
+  TEST (4, 4, 1, 5)
+  TEST (5, 4, 1, 5)
+  TEST (6, 4, 1, 5)
+  TEST (7, 4, 1, 5)
+  TEST (0, 5, 1, 5)
+  TEST (1, 5, 1, 5)
+  TEST (2, 5, 1, 5)
+  TEST (3, 5, 1, 5)
+  TEST (4, 5, 1, 5)
+  TEST (5, 5, 1, 5)
+  TEST (6, 5, 1, 5)
+  TEST (7, 5, 1, 5)
+  TEST (0, 6, 1, 5)
+  TEST (1, 6, 1, 5)
+  TEST (2, 6, 1, 5)
+  TEST (3, 6, 1, 5)
+  TEST (4, 6, 1, 5)
+  TEST (5, 6, 1, 5)
+  TEST (6, 6, 1, 5)
+  TEST (7, 6, 1, 5)
+  TEST (0, 7, 1, 5)
+  TEST (1, 7, 1, 5)
+  TEST (2, 7, 1, 5)
+  TEST (3, 7, 1, 5)
+  TEST (4, 7, 1, 5)
+  TEST (5, 7, 1, 5)
+  TEST (6, 7, 1, 5)
+  TEST (7, 7, 1, 5)
+}
+
+void check21(void)
+{
+  TEST (0, 0, 2, 5)
+  TEST (1, 0, 2, 5)
+  TEST (2, 0, 2, 5)
+  TEST (3, 0, 2, 5)
+  TEST (4, 0, 2, 5)
+  TEST (5, 0, 2, 5)
+  TEST (6, 0, 2, 5)
+  TEST (7, 0, 2, 5)
+  TEST (0, 1, 2, 5)
+  TEST (1, 1, 2, 5)
+  TEST (2, 1, 2, 5)
+  TEST (3, 1, 2, 5)
+  TEST (4, 1, 2, 5)
+  TEST (5, 1, 2, 5)
+  TEST (6, 1, 2, 5)
+  TEST (7, 1, 2, 5)
+  TEST (0, 2, 2, 5)
+  TEST (1, 2, 2, 5)
+  TEST (2, 2, 2, 5)
+  TEST (3, 2, 2, 5)
+  TEST (4, 2, 2, 5)
+  TEST (5, 2, 2, 5)
+  TEST (6, 2, 2, 5)
+  TEST (7, 2, 2, 5)
+  TEST (0, 3, 2, 5)
+  TEST (1, 3, 2, 5)
+  TEST (2, 3, 2, 5)
+  TEST (3, 3, 2, 5)
+  TEST (4, 3, 2, 5)
+  TEST (5, 3, 2, 5)
+  TEST (6, 3, 2, 5)
+  TEST (7, 3, 2, 5)
+  TEST (0, 4, 2, 5)
+  TEST (1, 4, 2, 5)
+  TEST (2, 4, 2, 5)
+  TEST (3, 4, 2, 5)
+  TEST (4, 4, 2, 5)
+  TEST (5, 4, 2, 5)
+  TEST (6, 4, 2, 5)
+  TEST (7, 4, 2, 5)
+  TEST (0, 5, 2, 5)
+  TEST (1, 5, 2, 5)
+  TEST (2, 5, 2, 5)
+  TEST (3, 5, 2, 5)
+  TEST (4, 5, 2, 5)
+  TEST (5, 5, 2, 5)
+  TEST (6, 5, 2, 5)
+  TEST (7, 5, 2, 5)
+  TEST (0, 6, 2, 5)
+  TEST (1, 6, 2, 5)
+  TEST (2, 6, 2, 5)
+  TEST (3, 6, 2, 5)
+  TEST (4, 6, 2, 5)
+  TEST (5, 6, 2, 5)
+  TEST (6, 6, 2, 5)
+  TEST (7, 6, 2, 5)
+  TEST (0, 7, 2, 5)
+  TEST (1, 7, 2, 5)
+  TEST (2, 7, 2, 5)
+  TEST (3, 7, 2, 5)
+  TEST (4, 7, 2, 5)
+  TEST (5, 7, 2, 5)
+  TEST (6, 7, 2, 5)
+  TEST (7, 7, 2, 5)
+  TEST (0, 0, 3, 5)
+  TEST (1, 0, 3, 5)
+  TEST (2, 0, 3, 5)
+  TEST (3, 0, 3, 5)
+  TEST (4, 0, 3, 5)
+  TEST (5, 0, 3, 5)
+  TEST (6, 0, 3, 5)
+  TEST (7, 0, 3, 5)
+  TEST (0, 1, 3, 5)
+  TEST (1, 1, 3, 5)
+  TEST (2, 1, 3, 5)
+  TEST (3, 1, 3, 5)
+  TEST (4, 1, 3, 5)
+  TEST (5, 1, 3, 5)
+  TEST (6, 1, 3, 5)
+  TEST (7, 1, 3, 5)
+  TEST (0, 2, 3, 5)
+  TEST (1, 2, 3, 5)
+  TEST (2, 2, 3, 5)
+  TEST (3, 2, 3, 5)
+  TEST (4, 2, 3, 5)
+  TEST (5, 2, 3, 5)
+  TEST (6, 2, 3, 5)
+  TEST (7, 2, 3, 5)
+  TEST (0, 3, 3, 5)
+  TEST (1, 3, 3, 5)
+  TEST (2, 3, 3, 5)
+  TEST (3, 3, 3, 5)
+  TEST (4, 3, 3, 5)
+  TEST (5, 3, 3, 5)
+  TEST (6, 3, 3, 5)
+  TEST (7, 3, 3, 5)
+  TEST (0, 4, 3, 5)
+  TEST (1, 4, 3, 5)
+  TEST (2, 4, 3, 5)
+  TEST (3, 4, 3, 5)
+  TEST (4, 4, 3, 5)
+  TEST (5, 4, 3, 5)
+  TEST (6, 4, 3, 5)
+  TEST (7, 4, 3, 5)
+  TEST (0, 5, 3, 5)
+  TEST (1, 5, 3, 5)
+  TEST (2, 5, 3, 5)
+  TEST (3, 5, 3, 5)
+  TEST (4, 5, 3, 5)
+  TEST (5, 5, 3, 5)
+  TEST (6, 5, 3, 5)
+  TEST (7, 5, 3, 5)
+  TEST (0, 6, 3, 5)
+  TEST (1, 6, 3, 5)
+  TEST (2, 6, 3, 5)
+  TEST (3, 6, 3, 5)
+  TEST (4, 6, 3, 5)
+  TEST (5, 6, 3, 5)
+  TEST (6, 6, 3, 5)
+  TEST (7, 6, 3, 5)
+  TEST (0, 7, 3, 5)
+  TEST (1, 7, 3, 5)
+  TEST (2, 7, 3, 5)
+  TEST (3, 7, 3, 5)
+  TEST (4, 7, 3, 5)
+  TEST (5, 7, 3, 5)
+  TEST (6, 7, 3, 5)
+  TEST (7, 7, 3, 5)
+}
+
+void check22(void)
+{
+  TEST (0, 0, 4, 5)
+  TEST (1, 0, 4, 5)
+  TEST (2, 0, 4, 5)
+  TEST (3, 0, 4, 5)
+  TEST (4, 0, 4, 5)
+  TEST (5, 0, 4, 5)
+  TEST (6, 0, 4, 5)
+  TEST (7, 0, 4, 5)
+  TEST (0, 1, 4, 5)
+  TEST (1, 1, 4, 5)
+  TEST (2, 1, 4, 5)
+  TEST (3, 1, 4, 5)
+  TEST (4, 1, 4, 5)
+  TEST (5, 1, 4, 5)
+  TEST (6, 1, 4, 5)
+  TEST (7, 1, 4, 5)
+  TEST (0, 2, 4, 5)
+  TEST (1, 2, 4, 5)
+  TEST (2, 2, 4, 5)
+  TEST (3, 2, 4, 5)
+  TEST (4, 2, 4, 5)
+  TEST (5, 2, 4, 5)
+  TEST (6, 2, 4, 5)
+  TEST (7, 2, 4, 5)
+  TEST (0, 3, 4, 5)
+  TEST (1, 3, 4, 5)
+  TEST (2, 3, 4, 5)
+  TEST (3, 3, 4, 5)
+  TEST (4, 3, 4, 5)
+  TEST (5, 3, 4, 5)
+  TEST (6, 3, 4, 5)
+  TEST (7, 3, 4, 5)
+  TEST (0, 4, 4, 5)
+  TEST (1, 4, 4, 5)
+  TEST (2, 4, 4, 5)
+  TEST (3, 4, 4, 5)
+  TEST (4, 4, 4, 5)
+  TEST (5, 4, 4, 5)
+  TEST (6, 4, 4, 5)
+  TEST (7, 4, 4, 5)
+  TEST (0, 5, 4, 5)
+  TEST (1, 5, 4, 5)
+  TEST (2, 5, 4, 5)
+  TEST (3, 5, 4, 5)
+  TEST (4, 5, 4, 5)
+  TEST (5, 5, 4, 5)
+  TEST (6, 5, 4, 5)
+  TEST (7, 5, 4, 5)
+  TEST (0, 6, 4, 5)
+  TEST (1, 6, 4, 5)
+  TEST (2, 6, 4, 5)
+  TEST (3, 6, 4, 5)
+  TEST (4, 6, 4, 5)
+  TEST (5, 6, 4, 5)
+  TEST (6, 6, 4, 5)
+  TEST (7, 6, 4, 5)
+  TEST (0, 7, 4, 5)
+  TEST (1, 7, 4, 5)
+  TEST (2, 7, 4, 5)
+  TEST (3, 7, 4, 5)
+  TEST (4, 7, 4, 5)
+  TEST (5, 7, 4, 5)
+  TEST (6, 7, 4, 5)
+  TEST (7, 7, 4, 5)
+  TEST (0, 0, 5, 5)
+  TEST (1, 0, 5, 5)
+  TEST (2, 0, 5, 5)
+  TEST (3, 0, 5, 5)
+  TEST (4, 0, 5, 5)
+  TEST (5, 0, 5, 5)
+  TEST (6, 0, 5, 5)
+  TEST (7, 0, 5, 5)
+  TEST (0, 1, 5, 5)
+  TEST (1, 1, 5, 5)
+  TEST (2, 1, 5, 5)
+  TEST (3, 1, 5, 5)
+  TEST (4, 1, 5, 5)
+  TEST (5, 1, 5, 5)
+  TEST (6, 1, 5, 5)
+  TEST (7, 1, 5, 5)
+  TEST (0, 2, 5, 5)
+  TEST (1, 2, 5, 5)
+  TEST (2, 2, 5, 5)
+  TEST (3, 2, 5, 5)
+  TEST (4, 2, 5, 5)
+  TEST (5, 2, 5, 5)
+  TEST (6, 2, 5, 5)
+  TEST (7, 2, 5, 5)
+  TEST (0, 3, 5, 5)
+  TEST (1, 3, 5, 5)
+  TEST (2, 3, 5, 5)
+  TEST (3, 3, 5, 5)
+  TEST (4, 3, 5, 5)
+  TEST (5, 3, 5, 5)
+  TEST (6, 3, 5, 5)
+  TEST (7, 3, 5, 5)
+  TEST (0, 4, 5, 5)
+  TEST (1, 4, 5, 5)
+  TEST (2, 4, 5, 5)
+  TEST (3, 4, 5, 5)
+  TEST (4, 4, 5, 5)
+  TEST (5, 4, 5, 5)
+  TEST (6, 4, 5, 5)
+  TEST (7, 4, 5, 5)
+  TEST (0, 5, 5, 5)
+  TEST (1, 5, 5, 5)
+  TEST (2, 5, 5, 5)
+  TEST (3, 5, 5, 5)
+  TEST (4, 5, 5, 5)
+  TEST (5, 5, 5, 5)
+  TEST (6, 5, 5, 5)
+  TEST (7, 5, 5, 5)
+  TEST (0, 6, 5, 5)
+  TEST (1, 6, 5, 5)
+  TEST (2, 6, 5, 5)
+  TEST (3, 6, 5, 5)
+  TEST (4, 6, 5, 5)
+  TEST (5, 6, 5, 5)
+  TEST (6, 6, 5, 5)
+  TEST (7, 6, 5, 5)
+  TEST (0, 7, 5, 5)
+  TEST (1, 7, 5, 5)
+  TEST (2, 7, 5, 5)
+  TEST (3, 7, 5, 5)
+  TEST (4, 7, 5, 5)
+  TEST (5, 7, 5, 5)
+  TEST (6, 7, 5, 5)
+  TEST (7, 7, 5, 5)
+}
+
+void check23(void)
+{
+  TEST (0, 0, 6, 5)
+  TEST (1, 0, 6, 5)
+  TEST (2, 0, 6, 5)
+  TEST (3, 0, 6, 5)
+  TEST (4, 0, 6, 5)
+  TEST (5, 0, 6, 5)
+  TEST (6, 0, 6, 5)
+  TEST (7, 0, 6, 5)
+  TEST (0, 1, 6, 5)
+  TEST (1, 1, 6, 5)
+  TEST (2, 1, 6, 5)
+  TEST (3, 1, 6, 5)
+  TEST (4, 1, 6, 5)
+  TEST (5, 1, 6, 5)
+  TEST (6, 1, 6, 5)
+  TEST (7, 1, 6, 5)
+  TEST (0, 2, 6, 5)
+  TEST (1, 2, 6, 5)
+  TEST (2, 2, 6, 5)
+  TEST (3, 2, 6, 5)
+  TEST (4, 2, 6, 5)
+  TEST (5, 2, 6, 5)
+  TEST (6, 2, 6, 5)
+  TEST (7, 2, 6, 5)
+  TEST (0, 3, 6, 5)
+  TEST (1, 3, 6, 5)
+  TEST (2, 3, 6, 5)
+  TEST (3, 3, 6, 5)
+  TEST (4, 3, 6, 5)
+  TEST (5, 3, 6, 5)
+  TEST (6, 3, 6, 5)
+  TEST (7, 3, 6, 5)
+  TEST (0, 4, 6, 5)
+  TEST (1, 4, 6, 5)
+  TEST (2, 4, 6, 5)
+  TEST (3, 4, 6, 5)
+  TEST (4, 4, 6, 5)
+  TEST (5, 4, 6, 5)
+  TEST (6, 4, 6, 5)
+  TEST (7, 4, 6, 5)
+  TEST (0, 5, 6, 5)
+  TEST (1, 5, 6, 5)
+  TEST (2, 5, 6, 5)
+  TEST (3, 5, 6, 5)
+  TEST (4, 5, 6, 5)
+  TEST (5, 5, 6, 5)
+  TEST (6, 5, 6, 5)
+  TEST (7, 5, 6, 5)
+  TEST (0, 6, 6, 5)
+  TEST (1, 6, 6, 5)
+  TEST (2, 6, 6, 5)
+  TEST (3, 6, 6, 5)
+  TEST (4, 6, 6, 5)
+  TEST (5, 6, 6, 5)
+  TEST (6, 6, 6, 5)
+  TEST (7, 6, 6, 5)
+  TEST (0, 7, 6, 5)
+  TEST (1, 7, 6, 5)
+  TEST (2, 7, 6, 5)
+  TEST (3, 7, 6, 5)
+  TEST (4, 7, 6, 5)
+  TEST (5, 7, 6, 5)
+  TEST (6, 7, 6, 5)
+  TEST (7, 7, 6, 5)
+  TEST (0, 0, 7, 5)
+  TEST (1, 0, 7, 5)
+  TEST (2, 0, 7, 5)
+  TEST (3, 0, 7, 5)
+  TEST (4, 0, 7, 5)
+  TEST (5, 0, 7, 5)
+  TEST (6, 0, 7, 5)
+  TEST (7, 0, 7, 5)
+  TEST (0, 1, 7, 5)
+  TEST (1, 1, 7, 5)
+  TEST (2, 1, 7, 5)
+  TEST (3, 1, 7, 5)
+  TEST (4, 1, 7, 5)
+  TEST (5, 1, 7, 5)
+  TEST (6, 1, 7, 5)
+  TEST (7, 1, 7, 5)
+  TEST (0, 2, 7, 5)
+  TEST (1, 2, 7, 5)
+  TEST (2, 2, 7, 5)
+  TEST (3, 2, 7, 5)
+  TEST (4, 2, 7, 5)
+  TEST (5, 2, 7, 5)
+  TEST (6, 2, 7, 5)
+  TEST (7, 2, 7, 5)
+  TEST (0, 3, 7, 5)
+  TEST (1, 3, 7, 5)
+  TEST (2, 3, 7, 5)
+  TEST (3, 3, 7, 5)
+  TEST (4, 3, 7, 5)
+  TEST (5, 3, 7, 5)
+  TEST (6, 3, 7, 5)
+  TEST (7, 3, 7, 5)
+  TEST (0, 4, 7, 5)
+  TEST (1, 4, 7, 5)
+  TEST (2, 4, 7, 5)
+  TEST (3, 4, 7, 5)
+  TEST (4, 4, 7, 5)
+  TEST (5, 4, 7, 5)
+  TEST (6, 4, 7, 5)
+  TEST (7, 4, 7, 5)
+  TEST (0, 5, 7, 5)
+  TEST (1, 5, 7, 5)
+  TEST (2, 5, 7, 5)
+  TEST (3, 5, 7, 5)
+  TEST (4, 5, 7, 5)
+  TEST (5, 5, 7, 5)
+  TEST (6, 5, 7, 5)
+  TEST (7, 5, 7, 5)
+  TEST (0, 6, 7, 5)
+  TEST (1, 6, 7, 5)
+  TEST (2, 6, 7, 5)
+  TEST (3, 6, 7, 5)
+  TEST (4, 6, 7, 5)
+  TEST (5, 6, 7, 5)
+  TEST (6, 6, 7, 5)
+  TEST (7, 6, 7, 5)
+  TEST (0, 7, 7, 5)
+  TEST (1, 7, 7, 5)
+  TEST (2, 7, 7, 5)
+  TEST (3, 7, 7, 5)
+  TEST (4, 7, 7, 5)
+  TEST (5, 7, 7, 5)
+  TEST (6, 7, 7, 5)
+  TEST (7, 7, 7, 5)
+}
+
+void check24(void)
+{
+  TEST (0, 0, 0, 6)
+  TEST (1, 0, 0, 6)
+  TEST (2, 0, 0, 6)
+  TEST (3, 0, 0, 6)
+  TEST (4, 0, 0, 6)
+  TEST (5, 0, 0, 6)
+  TEST (6, 0, 0, 6)
+  TEST (7, 0, 0, 6)
+  TEST (0, 1, 0, 6)
+  TEST (1, 1, 0, 6)
+  TEST (2, 1, 0, 6)
+  TEST (3, 1, 0, 6)
+  TEST (4, 1, 0, 6)
+  TEST (5, 1, 0, 6)
+  TEST (6, 1, 0, 6)
+  TEST (7, 1, 0, 6)
+  TEST (0, 2, 0, 6)
+  TEST (1, 2, 0, 6)
+  TEST (2, 2, 0, 6)
+  TEST (3, 2, 0, 6)
+  TEST (4, 2, 0, 6)
+  TEST (5, 2, 0, 6)
+  TEST (6, 2, 0, 6)
+  TEST (7, 2, 0, 6)
+  TEST (0, 3, 0, 6)
+  TEST (1, 3, 0, 6)
+  TEST (2, 3, 0, 6)
+  TEST (3, 3, 0, 6)
+  TEST (4, 3, 0, 6)
+  TEST (5, 3, 0, 6)
+  TEST (6, 3, 0, 6)
+  TEST (7, 3, 0, 6)
+  TEST (0, 4, 0, 6)
+  TEST (1, 4, 0, 6)
+  TEST (2, 4, 0, 6)
+  TEST (3, 4, 0, 6)
+  TEST (4, 4, 0, 6)
+  TEST (5, 4, 0, 6)
+  TEST (6, 4, 0, 6)
+  TEST (7, 4, 0, 6)
+  TEST (0, 5, 0, 6)
+  TEST (1, 5, 0, 6)
+  TEST (2, 5, 0, 6)
+  TEST (3, 5, 0, 6)
+  TEST (4, 5, 0, 6)
+  TEST (5, 5, 0, 6)
+  TEST (6, 5, 0, 6)
+  TEST (7, 5, 0, 6)
+  TEST (0, 6, 0, 6)
+  TEST (1, 6, 0, 6)
+  TEST (2, 6, 0, 6)
+  TEST (3, 6, 0, 6)
+  TEST (4, 6, 0, 6)
+  TEST (5, 6, 0, 6)
+  TEST (6, 6, 0, 6)
+  TEST (7, 6, 0, 6)
+  TEST (0, 7, 0, 6)
+  TEST (1, 7, 0, 6)
+  TEST (2, 7, 0, 6)
+  TEST (3, 7, 0, 6)
+  TEST (4, 7, 0, 6)
+  TEST (5, 7, 0, 6)
+  TEST (6, 7, 0, 6)
+  TEST (7, 7, 0, 6)
+  TEST (0, 0, 1, 6)
+  TEST (1, 0, 1, 6)
+  TEST (2, 0, 1, 6)
+  TEST (3, 0, 1, 6)
+  TEST (4, 0, 1, 6)
+  TEST (5, 0, 1, 6)
+  TEST (6, 0, 1, 6)
+  TEST (7, 0, 1, 6)
+  TEST (0, 1, 1, 6)
+  TEST (1, 1, 1, 6)
+  TEST (2, 1, 1, 6)
+  TEST (3, 1, 1, 6)
+  TEST (4, 1, 1, 6)
+  TEST (5, 1, 1, 6)
+  TEST (6, 1, 1, 6)
+  TEST (7, 1, 1, 6)
+  TEST (0, 2, 1, 6)
+  TEST (1, 2, 1, 6)
+  TEST (2, 2, 1, 6)
+  TEST (3, 2, 1, 6)
+  TEST (4, 2, 1, 6)
+  TEST (5, 2, 1, 6)
+  TEST (6, 2, 1, 6)
+  TEST (7, 2, 1, 6)
+  TEST (0, 3, 1, 6)
+  TEST (1, 3, 1, 6)
+  TEST (2, 3, 1, 6)
+  TEST (3, 3, 1, 6)
+  TEST (4, 3, 1, 6)
+  TEST (5, 3, 1, 6)
+  TEST (6, 3, 1, 6)
+  TEST (7, 3, 1, 6)
+  TEST (0, 4, 1, 6)
+  TEST (1, 4, 1, 6)
+  TEST (2, 4, 1, 6)
+  TEST (3, 4, 1, 6)
+  TEST (4, 4, 1, 6)
+  TEST (5, 4, 1, 6)
+  TEST (6, 4, 1, 6)
+  TEST (7, 4, 1, 6)
+  TEST (0, 5, 1, 6)
+  TEST (1, 5, 1, 6)
+  TEST (2, 5, 1, 6)
+  TEST (3, 5, 1, 6)
+  TEST (4, 5, 1, 6)
+  TEST (5, 5, 1, 6)
+  TEST (6, 5, 1, 6)
+  TEST (7, 5, 1, 6)
+  TEST (0, 6, 1, 6)
+  TEST (1, 6, 1, 6)
+  TEST (2, 6, 1, 6)
+  TEST (3, 6, 1, 6)
+  TEST (4, 6, 1, 6)
+  TEST (5, 6, 1, 6)
+  TEST (6, 6, 1, 6)
+  TEST (7, 6, 1, 6)
+  TEST (0, 7, 1, 6)
+  TEST (1, 7, 1, 6)
+  TEST (2, 7, 1, 6)
+  TEST (3, 7, 1, 6)
+  TEST (4, 7, 1, 6)
+  TEST (5, 7, 1, 6)
+  TEST (6, 7, 1, 6)
+  TEST (7, 7, 1, 6)
+}
+
+void check25(void)
+{
+  TEST (0, 0, 2, 6)
+  TEST (1, 0, 2, 6)
+  TEST (2, 0, 2, 6)
+  TEST (3, 0, 2, 6)
+  TEST (4, 0, 2, 6)
+  TEST (5, 0, 2, 6)
+  TEST (6, 0, 2, 6)
+  TEST (7, 0, 2, 6)
+  TEST (0, 1, 2, 6)
+  TEST (1, 1, 2, 6)
+  TEST (2, 1, 2, 6)
+  TEST (3, 1, 2, 6)
+  TEST (4, 1, 2, 6)
+  TEST (5, 1, 2, 6)
+  TEST (6, 1, 2, 6)
+  TEST (7, 1, 2, 6)
+  TEST (0, 2, 2, 6)
+  TEST (1, 2, 2, 6)
+  TEST (2, 2, 2, 6)
+  TEST (3, 2, 2, 6)
+  TEST (4, 2, 2, 6)
+  TEST (5, 2, 2, 6)
+  TEST (6, 2, 2, 6)
+  TEST (7, 2, 2, 6)
+  TEST (0, 3, 2, 6)
+  TEST (1, 3, 2, 6)
+  TEST (2, 3, 2, 6)
+  TEST (3, 3, 2, 6)
+  TEST (4, 3, 2, 6)
+  TEST (5, 3, 2, 6)
+  TEST (6, 3, 2, 6)
+  TEST (7, 3, 2, 6)
+  TEST (0, 4, 2, 6)
+  TEST (1, 4, 2, 6)
+  TEST (2, 4, 2, 6)
+  TEST (3, 4, 2, 6)
+  TEST (4, 4, 2, 6)
+  TEST (5, 4, 2, 6)
+  TEST (6, 4, 2, 6)
+  TEST (7, 4, 2, 6)
+  TEST (0, 5, 2, 6)
+  TEST (1, 5, 2, 6)
+  TEST (2, 5, 2, 6)
+  TEST (3, 5, 2, 6)
+  TEST (4, 5, 2, 6)
+  TEST (5, 5, 2, 6)
+  TEST (6, 5, 2, 6)
+  TEST (7, 5, 2, 6)
+  TEST (0, 6, 2, 6)
+  TEST (1, 6, 2, 6)
+  TEST (2, 6, 2, 6)
+  TEST (3, 6, 2, 6)
+  TEST (4, 6, 2, 6)
+  TEST (5, 6, 2, 6)
+  TEST (6, 6, 2, 6)
+  TEST (7, 6, 2, 6)
+  TEST (0, 7, 2, 6)
+  TEST (1, 7, 2, 6)
+  TEST (2, 7, 2, 6)
+  TEST (3, 7, 2, 6)
+  TEST (4, 7, 2, 6)
+  TEST (5, 7, 2, 6)
+  TEST (6, 7, 2, 6)
+  TEST (7, 7, 2, 6)
+  TEST (0, 0, 3, 6)
+  TEST (1, 0, 3, 6)
+  TEST (2, 0, 3, 6)
+  TEST (3, 0, 3, 6)
+  TEST (4, 0, 3, 6)
+  TEST (5, 0, 3, 6)
+  TEST (6, 0, 3, 6)
+  TEST (7, 0, 3, 6)
+  TEST (0, 1, 3, 6)
+  TEST (1, 1, 3, 6)
+  TEST (2, 1, 3, 6)
+  TEST (3, 1, 3, 6)
+  TEST (4, 1, 3, 6)
+  TEST (5, 1, 3, 6)
+  TEST (6, 1, 3, 6)
+  TEST (7, 1, 3, 6)
+  TEST (0, 2, 3, 6)
+  TEST (1, 2, 3, 6)
+  TEST (2, 2, 3, 6)
+  TEST (3, 2, 3, 6)
+  TEST (4, 2, 3, 6)
+  TEST (5, 2, 3, 6)
+  TEST (6, 2, 3, 6)
+  TEST (7, 2, 3, 6)
+  TEST (0, 3, 3, 6)
+  TEST (1, 3, 3, 6)
+  TEST (2, 3, 3, 6)
+  TEST (3, 3, 3, 6)
+  TEST (4, 3, 3, 6)
+  TEST (5, 3, 3, 6)
+  TEST (6, 3, 3, 6)
+  TEST (7, 3, 3, 6)
+  TEST (0, 4, 3, 6)
+  TEST (1, 4, 3, 6)
+  TEST (2, 4, 3, 6)
+  TEST (3, 4, 3, 6)
+  TEST (4, 4, 3, 6)
+  TEST (5, 4, 3, 6)
+  TEST (6, 4, 3, 6)
+  TEST (7, 4, 3, 6)
+  TEST (0, 5, 3, 6)
+  TEST (1, 5, 3, 6)
+  TEST (2, 5, 3, 6)
+  TEST (3, 5, 3, 6)
+  TEST (4, 5, 3, 6)
+  TEST (5, 5, 3, 6)
+  TEST (6, 5, 3, 6)
+  TEST (7, 5, 3, 6)
+  TEST (0, 6, 3, 6)
+  TEST (1, 6, 3, 6)
+  TEST (2, 6, 3, 6)
+  TEST (3, 6, 3, 6)
+  TEST (4, 6, 3, 6)
+  TEST (5, 6, 3, 6)
+  TEST (6, 6, 3, 6)
+  TEST (7, 6, 3, 6)
+  TEST (0, 7, 3, 6)
+  TEST (1, 7, 3, 6)
+  TEST (2, 7, 3, 6)
+  TEST (3, 7, 3, 6)
+  TEST (4, 7, 3, 6)
+  TEST (5, 7, 3, 6)
+  TEST (6, 7, 3, 6)
+  TEST (7, 7, 3, 6)
+}
+
+void check26(void)
+{
+  TEST (0, 0, 4, 6)
+  TEST (1, 0, 4, 6)
+  TEST (2, 0, 4, 6)
+  TEST (3, 0, 4, 6)
+  TEST (4, 0, 4, 6)
+  TEST (5, 0, 4, 6)
+  TEST (6, 0, 4, 6)
+  TEST (7, 0, 4, 6)
+  TEST (0, 1, 4, 6)
+  TEST (1, 1, 4, 6)
+  TEST (2, 1, 4, 6)
+  TEST (3, 1, 4, 6)
+  TEST (4, 1, 4, 6)
+  TEST (5, 1, 4, 6)
+  TEST (6, 1, 4, 6)
+  TEST (7, 1, 4, 6)
+  TEST (0, 2, 4, 6)
+  TEST (1, 2, 4, 6)
+  TEST (2, 2, 4, 6)
+  TEST (3, 2, 4, 6)
+  TEST (4, 2, 4, 6)
+  TEST (5, 2, 4, 6)
+  TEST (6, 2, 4, 6)
+  TEST (7, 2, 4, 6)
+  TEST (0, 3, 4, 6)
+  TEST (1, 3, 4, 6)
+  TEST (2, 3, 4, 6)
+  TEST (3, 3, 4, 6)
+  TEST (4, 3, 4, 6)
+  TEST (5, 3, 4, 6)
+  TEST (6, 3, 4, 6)
+  TEST (7, 3, 4, 6)
+  TEST (0, 4, 4, 6)
+  TEST (1, 4, 4, 6)
+  TEST (2, 4, 4, 6)
+  TEST (3, 4, 4, 6)
+  TEST (4, 4, 4, 6)
+  TEST (5, 4, 4, 6)
+  TEST (6, 4, 4, 6)
+  TEST (7, 4, 4, 6)
+  TEST (0, 5, 4, 6)
+  TEST (1, 5, 4, 6)
+  TEST (2, 5, 4, 6)
+  TEST (3, 5, 4, 6)
+  TEST (4, 5, 4, 6)
+  TEST (5, 5, 4, 6)
+  TEST (6, 5, 4, 6)
+  TEST (7, 5, 4, 6)
+  TEST (0, 6, 4, 6)
+  TEST (1, 6, 4, 6)
+  TEST (2, 6, 4, 6)
+  TEST (3, 6, 4, 6)
+  TEST (4, 6, 4, 6)
+  TEST (5, 6, 4, 6)
+  TEST (6, 6, 4, 6)
+  TEST (7, 6, 4, 6)
+  TEST (0, 7, 4, 6)
+  TEST (1, 7, 4, 6)
+  TEST (2, 7, 4, 6)
+  TEST (3, 7, 4, 6)
+  TEST (4, 7, 4, 6)
+  TEST (5, 7, 4, 6)
+  TEST (6, 7, 4, 6)
+  TEST (7, 7, 4, 6)
+  TEST (0, 0, 5, 6)
+  TEST (1, 0, 5, 6)
+  TEST (2, 0, 5, 6)
+  TEST (3, 0, 5, 6)
+  TEST (4, 0, 5, 6)
+  TEST (5, 0, 5, 6)
+  TEST (6, 0, 5, 6)
+  TEST (7, 0, 5, 6)
+  TEST (0, 1, 5, 6)
+  TEST (1, 1, 5, 6)
+  TEST (2, 1, 5, 6)
+  TEST (3, 1, 5, 6)
+  TEST (4, 1, 5, 6)
+  TEST (5, 1, 5, 6)
+  TEST (6, 1, 5, 6)
+  TEST (7, 1, 5, 6)
+  TEST (0, 2, 5, 6)
+  TEST (1, 2, 5, 6)
+  TEST (2, 2, 5, 6)
+  TEST (3, 2, 5, 6)
+  TEST (4, 2, 5, 6)
+  TEST (5, 2, 5, 6)
+  TEST (6, 2, 5, 6)
+  TEST (7, 2, 5, 6)
+  TEST (0, 3, 5, 6)
+  TEST (1, 3, 5, 6)
+  TEST (2, 3, 5, 6)
+  TEST (3, 3, 5, 6)
+  TEST (4, 3, 5, 6)
+  TEST (5, 3, 5, 6)
+  TEST (6, 3, 5, 6)
+  TEST (7, 3, 5, 6)
+  TEST (0, 4, 5, 6)
+  TEST (1, 4, 5, 6)
+  TEST (2, 4, 5, 6)
+  TEST (3, 4, 5, 6)
+  TEST (4, 4, 5, 6)
+  TEST (5, 4, 5, 6)
+  TEST (6, 4, 5, 6)
+  TEST (7, 4, 5, 6)
+  TEST (0, 5, 5, 6)
+  TEST (1, 5, 5, 6)
+  TEST (2, 5, 5, 6)
+  TEST (3, 5, 5, 6)
+  TEST (4, 5, 5, 6)
+  TEST (5, 5, 5, 6)
+  TEST (6, 5, 5, 6)
+  TEST (7, 5, 5, 6)
+  TEST (0, 6, 5, 6)
+  TEST (1, 6, 5, 6)
+  TEST (2, 6, 5, 6)
+  TEST (3, 6, 5, 6)
+  TEST (4, 6, 5, 6)
+  TEST (5, 6, 5, 6)
+  TEST (6, 6, 5, 6)
+  TEST (7, 6, 5, 6)
+  TEST (0, 7, 5, 6)
+  TEST (1, 7, 5, 6)
+  TEST (2, 7, 5, 6)
+  TEST (3, 7, 5, 6)
+  TEST (4, 7, 5, 6)
+  TEST (5, 7, 5, 6)
+  TEST (6, 7, 5, 6)
+  TEST (7, 7, 5, 6)
+}
+
+void check27(void)
+{
+  TEST (0, 0, 6, 6)
+  TEST (1, 0, 6, 6)
+  TEST (2, 0, 6, 6)
+  TEST (3, 0, 6, 6)
+  TEST (4, 0, 6, 6)
+  TEST (5, 0, 6, 6)
+  TEST (6, 0, 6, 6)
+  TEST (7, 0, 6, 6)
+  TEST (0, 1, 6, 6)
+  TEST (1, 1, 6, 6)
+  TEST (2, 1, 6, 6)
+  TEST (3, 1, 6, 6)
+  TEST (4, 1, 6, 6)
+  TEST (5, 1, 6, 6)
+  TEST (6, 1, 6, 6)
+  TEST (7, 1, 6, 6)
+  TEST (0, 2, 6, 6)
+  TEST (1, 2, 6, 6)
+  TEST (2, 2, 6, 6)
+  TEST (3, 2, 6, 6)
+  TEST (4, 2, 6, 6)
+  TEST (5, 2, 6, 6)
+  TEST (6, 2, 6, 6)
+  TEST (7, 2, 6, 6)
+  TEST (0, 3, 6, 6)
+  TEST (1, 3, 6, 6)
+  TEST (2, 3, 6, 6)
+  TEST (3, 3, 6, 6)
+  TEST (4, 3, 6, 6)
+  TEST (5, 3, 6, 6)
+  TEST (6, 3, 6, 6)
+  TEST (7, 3, 6, 6)
+  TEST (0, 4, 6, 6)
+  TEST (1, 4, 6, 6)
+  TEST (2, 4, 6, 6)
+  TEST (3, 4, 6, 6)
+  TEST (4, 4, 6, 6)
+  TEST (5, 4, 6, 6)
+  TEST (6, 4, 6, 6)
+  TEST (7, 4, 6, 6)
+  TEST (0, 5, 6, 6)
+  TEST (1, 5, 6, 6)
+  TEST (2, 5, 6, 6)
+  TEST (3, 5, 6, 6)
+  TEST (4, 5, 6, 6)
+  TEST (5, 5, 6, 6)
+  TEST (6, 5, 6, 6)
+  TEST (7, 5, 6, 6)
+  TEST (0, 6, 6, 6)
+  TEST (1, 6, 6, 6)
+  TEST (2, 6, 6, 6)
+  TEST (3, 6, 6, 6)
+  TEST (4, 6, 6, 6)
+  TEST (5, 6, 6, 6)
+  TEST (6, 6, 6, 6)
+  TEST (7, 6, 6, 6)
+  TEST (0, 7, 6, 6)
+  TEST (1, 7, 6, 6)
+  TEST (2, 7, 6, 6)
+  TEST (3, 7, 6, 6)
+  TEST (4, 7, 6, 6)
+  TEST (5, 7, 6, 6)
+  TEST (6, 7, 6, 6)
+  TEST (7, 7, 6, 6)
+  TEST (0, 0, 7, 6)
+  TEST (1, 0, 7, 6)
+  TEST (2, 0, 7, 6)
+  TEST (3, 0, 7, 6)
+  TEST (4, 0, 7, 6)
+  TEST (5, 0, 7, 6)
+  TEST (6, 0, 7, 6)
+  TEST (7, 0, 7, 6)
+  TEST (0, 1, 7, 6)
+  TEST (1, 1, 7, 6)
+  TEST (2, 1, 7, 6)
+  TEST (3, 1, 7, 6)
+  TEST (4, 1, 7, 6)
+  TEST (5, 1, 7, 6)
+  TEST (6, 1, 7, 6)
+  TEST (7, 1, 7, 6)
+  TEST (0, 2, 7, 6)
+  TEST (1, 2, 7, 6)
+  TEST (2, 2, 7, 6)
+  TEST (3, 2, 7, 6)
+  TEST (4, 2, 7, 6)
+  TEST (5, 2, 7, 6)
+  TEST (6, 2, 7, 6)
+  TEST (7, 2, 7, 6)
+  TEST (0, 3, 7, 6)
+  TEST (1, 3, 7, 6)
+  TEST (2, 3, 7, 6)
+  TEST (3, 3, 7, 6)
+  TEST (4, 3, 7, 6)
+  TEST (5, 3, 7, 6)
+  TEST (6, 3, 7, 6)
+  TEST (7, 3, 7, 6)
+  TEST (0, 4, 7, 6)
+  TEST (1, 4, 7, 6)
+  TEST (2, 4, 7, 6)
+  TEST (3, 4, 7, 6)
+  TEST (4, 4, 7, 6)
+  TEST (5, 4, 7, 6)
+  TEST (6, 4, 7, 6)
+  TEST (7, 4, 7, 6)
+  TEST (0, 5, 7, 6)
+  TEST (1, 5, 7, 6)
+  TEST (2, 5, 7, 6)
+  TEST (3, 5, 7, 6)
+  TEST (4, 5, 7, 6)
+  TEST (5, 5, 7, 6)
+  TEST (6, 5, 7, 6)
+  TEST (7, 5, 7, 6)
+  TEST (0, 6, 7, 6)
+  TEST (1, 6, 7, 6)
+  TEST (2, 6, 7, 6)
+  TEST (3, 6, 7, 6)
+  TEST (4, 6, 7, 6)
+  TEST (5, 6, 7, 6)
+  TEST (6, 6, 7, 6)
+  TEST (7, 6, 7, 6)
+  TEST (0, 7, 7, 6)
+  TEST (1, 7, 7, 6)
+  TEST (2, 7, 7, 6)
+  TEST (3, 7, 7, 6)
+  TEST (4, 7, 7, 6)
+  TEST (5, 7, 7, 6)
+  TEST (6, 7, 7, 6)
+  TEST (7, 7, 7, 6)
+}
+
+void check28(void)
+{
+  TEST (0, 0, 0, 7)
+  TEST (1, 0, 0, 7)
+  TEST (2, 0, 0, 7)
+  TEST (3, 0, 0, 7)
+  TEST (4, 0, 0, 7)
+  TEST (5, 0, 0, 7)
+  TEST (6, 0, 0, 7)
+  TEST (7, 0, 0, 7)
+  TEST (0, 1, 0, 7)
+  TEST (1, 1, 0, 7)
+  TEST (2, 1, 0, 7)
+  TEST (3, 1, 0, 7)
+  TEST (4, 1, 0, 7)
+  TEST (5, 1, 0, 7)
+  TEST (6, 1, 0, 7)
+  TEST (7, 1, 0, 7)
+  TEST (0, 2, 0, 7)
+  TEST (1, 2, 0, 7)
+  TEST (2, 2, 0, 7)
+  TEST (3, 2, 0, 7)
+  TEST (4, 2, 0, 7)
+  TEST (5, 2, 0, 7)
+  TEST (6, 2, 0, 7)
+  TEST (7, 2, 0, 7)
+  TEST (0, 3, 0, 7)
+  TEST (1, 3, 0, 7)
+  TEST (2, 3, 0, 7)
+  TEST (3, 3, 0, 7)
+  TEST (4, 3, 0, 7)
+  TEST (5, 3, 0, 7)
+  TEST (6, 3, 0, 7)
+  TEST (7, 3, 0, 7)
+  TEST (0, 4, 0, 7)
+  TEST (1, 4, 0, 7)
+  TEST (2, 4, 0, 7)
+  TEST (3, 4, 0, 7)
+  TEST (4, 4, 0, 7)
+  TEST (5, 4, 0, 7)
+  TEST (6, 4, 0, 7)
+  TEST (7, 4, 0, 7)
+  TEST (0, 5, 0, 7)
+  TEST (1, 5, 0, 7)
+  TEST (2, 5, 0, 7)
+  TEST (3, 5, 0, 7)
+  TEST (4, 5, 0, 7)
+  TEST (5, 5, 0, 7)
+  TEST (6, 5, 0, 7)
+  TEST (7, 5, 0, 7)
+  TEST (0, 6, 0, 7)
+  TEST (1, 6, 0, 7)
+  TEST (2, 6, 0, 7)
+  TEST (3, 6, 0, 7)
+  TEST (4, 6, 0, 7)
+  TEST (5, 6, 0, 7)
+  TEST (6, 6, 0, 7)
+  TEST (7, 6, 0, 7)
+  TEST (0, 7, 0, 7)
+  TEST (1, 7, 0, 7)
+  TEST (2, 7, 0, 7)
+  TEST (3, 7, 0, 7)
+  TEST (4, 7, 0, 7)
+  TEST (5, 7, 0, 7)
+  TEST (6, 7, 0, 7)
+  TEST (7, 7, 0, 7)
+  TEST (0, 0, 1, 7)
+  TEST (1, 0, 1, 7)
+  TEST (2, 0, 1, 7)
+  TEST (3, 0, 1, 7)
+  TEST (4, 0, 1, 7)
+  TEST (5, 0, 1, 7)
+  TEST (6, 0, 1, 7)
+  TEST (7, 0, 1, 7)
+  TEST (0, 1, 1, 7)
+  TEST (1, 1, 1, 7)
+  TEST (2, 1, 1, 7)
+  TEST (3, 1, 1, 7)
+  TEST (4, 1, 1, 7)
+  TEST (5, 1, 1, 7)
+  TEST (6, 1, 1, 7)
+  TEST (7, 1, 1, 7)
+  TEST (0, 2, 1, 7)
+  TEST (1, 2, 1, 7)
+  TEST (2, 2, 1, 7)
+  TEST (3, 2, 1, 7)
+  TEST (4, 2, 1, 7)
+  TEST (5, 2, 1, 7)
+  TEST (6, 2, 1, 7)
+  TEST (7, 2, 1, 7)
+  TEST (0, 3, 1, 7)
+  TEST (1, 3, 1, 7)
+  TEST (2, 3, 1, 7)
+  TEST (3, 3, 1, 7)
+  TEST (4, 3, 1, 7)
+  TEST (5, 3, 1, 7)
+  TEST (6, 3, 1, 7)
+  TEST (7, 3, 1, 7)
+  TEST (0, 4, 1, 7)
+  TEST (1, 4, 1, 7)
+  TEST (2, 4, 1, 7)
+  TEST (3, 4, 1, 7)
+  TEST (4, 4, 1, 7)
+  TEST (5, 4, 1, 7)
+  TEST (6, 4, 1, 7)
+  TEST (7, 4, 1, 7)
+  TEST (0, 5, 1, 7)
+  TEST (1, 5, 1, 7)
+  TEST (2, 5, 1, 7)
+  TEST (3, 5, 1, 7)
+  TEST (4, 5, 1, 7)
+  TEST (5, 5, 1, 7)
+  TEST (6, 5, 1, 7)
+  TEST (7, 5, 1, 7)
+  TEST (0, 6, 1, 7)
+  TEST (1, 6, 1, 7)
+  TEST (2, 6, 1, 7)
+  TEST (3, 6, 1, 7)
+  TEST (4, 6, 1, 7)
+  TEST (5, 6, 1, 7)
+  TEST (6, 6, 1, 7)
+  TEST (7, 6, 1, 7)
+  TEST (0, 7, 1, 7)
+  TEST (1, 7, 1, 7)
+  TEST (2, 7, 1, 7)
+  TEST (3, 7, 1, 7)
+  TEST (4, 7, 1, 7)
+  TEST (5, 7, 1, 7)
+  TEST (6, 7, 1, 7)
+  TEST (7, 7, 1, 7)
+}
+
+void check29(void)
+{
+  TEST (0, 0, 2, 7)
+  TEST (1, 0, 2, 7)
+  TEST (2, 0, 2, 7)
+  TEST (3, 0, 2, 7)
+  TEST (4, 0, 2, 7)
+  TEST (5, 0, 2, 7)
+  TEST (6, 0, 2, 7)
+  TEST (7, 0, 2, 7)
+  TEST (0, 1, 2, 7)
+  TEST (1, 1, 2, 7)
+  TEST (2, 1, 2, 7)
+  TEST (3, 1, 2, 7)
+  TEST (4, 1, 2, 7)
+  TEST (5, 1, 2, 7)
+  TEST (6, 1, 2, 7)
+  TEST (7, 1, 2, 7)
+  TEST (0, 2, 2, 7)
+  TEST (1, 2, 2, 7)
+  TEST (2, 2, 2, 7)
+  TEST (3, 2, 2, 7)
+  TEST (4, 2, 2, 7)
+  TEST (5, 2, 2, 7)
+  TEST (6, 2, 2, 7)
+  TEST (7, 2, 2, 7)
+  TEST (0, 3, 2, 7)
+  TEST (1, 3, 2, 7)
+  TEST (2, 3, 2, 7)
+  TEST (3, 3, 2, 7)
+  TEST (4, 3, 2, 7)
+  TEST (5, 3, 2, 7)
+  TEST (6, 3, 2, 7)
+  TEST (7, 3, 2, 7)
+  TEST (0, 4, 2, 7)
+  TEST (1, 4, 2, 7)
+  TEST (2, 4, 2, 7)
+  TEST (3, 4, 2, 7)
+  TEST (4, 4, 2, 7)
+  TEST (5, 4, 2, 7)
+  TEST (6, 4, 2, 7)
+  TEST (7, 4, 2, 7)
+  TEST (0, 5, 2, 7)
+  TEST (1, 5, 2, 7)
+  TEST (2, 5, 2, 7)
+  TEST (3, 5, 2, 7)
+  TEST (4, 5, 2, 7)
+  TEST (5, 5, 2, 7)
+  TEST (6, 5, 2, 7)
+  TEST (7, 5, 2, 7)
+  TEST (0, 6, 2, 7)
+  TEST (1, 6, 2, 7)
+  TEST (2, 6, 2, 7)
+  TEST (3, 6, 2, 7)
+  TEST (4, 6, 2, 7)
+  TEST (5, 6, 2, 7)
+  TEST (6, 6, 2, 7)
+  TEST (7, 6, 2, 7)
+  TEST (0, 7, 2, 7)
+  TEST (1, 7, 2, 7)
+  TEST (2, 7, 2, 7)
+  TEST (3, 7, 2, 7)
+  TEST (4, 7, 2, 7)
+  TEST (5, 7, 2, 7)
+  TEST (6, 7, 2, 7)
+  TEST (7, 7, 2, 7)
+  TEST (0, 0, 3, 7)
+  TEST (1, 0, 3, 7)
+  TEST (2, 0, 3, 7)
+  TEST (3, 0, 3, 7)
+  TEST (4, 0, 3, 7)
+  TEST (5, 0, 3, 7)
+  TEST (6, 0, 3, 7)
+  TEST (7, 0, 3, 7)
+  TEST (0, 1, 3, 7)
+  TEST (1, 1, 3, 7)
+  TEST (2, 1, 3, 7)
+  TEST (3, 1, 3, 7)
+  TEST (4, 1, 3, 7)
+  TEST (5, 1, 3, 7)
+  TEST (6, 1, 3, 7)
+  TEST (7, 1, 3, 7)
+  TEST (0, 2, 3, 7)
+  TEST (1, 2, 3, 7)
+  TEST (2, 2, 3, 7)
+  TEST (3, 2, 3, 7)
+  TEST (4, 2, 3, 7)
+  TEST (5, 2, 3, 7)
+  TEST (6, 2, 3, 7)
+  TEST (7, 2, 3, 7)
+  TEST (0, 3, 3, 7)
+  TEST (1, 3, 3, 7)
+  TEST (2, 3, 3, 7)
+  TEST (3, 3, 3, 7)
+  TEST (4, 3, 3, 7)
+  TEST (5, 3, 3, 7)
+  TEST (6, 3, 3, 7)
+  TEST (7, 3, 3, 7)
+  TEST (0, 4, 3, 7)
+  TEST (1, 4, 3, 7)
+  TEST (2, 4, 3, 7)
+  TEST (3, 4, 3, 7)
+  TEST (4, 4, 3, 7)
+  TEST (5, 4, 3, 7)
+  TEST (6, 4, 3, 7)
+  TEST (7, 4, 3, 7)
+  TEST (0, 5, 3, 7)
+  TEST (1, 5, 3, 7)
+  TEST (2, 5, 3, 7)
+  TEST (3, 5, 3, 7)
+  TEST (4, 5, 3, 7)
+  TEST (5, 5, 3, 7)
+  TEST (6, 5, 3, 7)
+  TEST (7, 5, 3, 7)
+  TEST (0, 6, 3, 7)
+  TEST (1, 6, 3, 7)
+  TEST (2, 6, 3, 7)
+  TEST (3, 6, 3, 7)
+  TEST (4, 6, 3, 7)
+  TEST (5, 6, 3, 7)
+  TEST (6, 6, 3, 7)
+  TEST (7, 6, 3, 7)
+  TEST (0, 7, 3, 7)
+  TEST (1, 7, 3, 7)
+  TEST (2, 7, 3, 7)
+  TEST (3, 7, 3, 7)
+  TEST (4, 7, 3, 7)
+  TEST (5, 7, 3, 7)
+  TEST (6, 7, 3, 7)
+  TEST (7, 7, 3, 7)
+}
+
+void check30(void)
+{
+  TEST (0, 0, 4, 7)
+  TEST (1, 0, 4, 7)
+  TEST (2, 0, 4, 7)
+  TEST (3, 0, 4, 7)
+  TEST (4, 0, 4, 7)
+  TEST (5, 0, 4, 7)
+  TEST (6, 0, 4, 7)
+  TEST (7, 0, 4, 7)
+  TEST (0, 1, 4, 7)
+  TEST (1, 1, 4, 7)
+  TEST (2, 1, 4, 7)
+  TEST (3, 1, 4, 7)
+  TEST (4, 1, 4, 7)
+  TEST (5, 1, 4, 7)
+  TEST (6, 1, 4, 7)
+  TEST (7, 1, 4, 7)
+  TEST (0, 2, 4, 7)
+  TEST (1, 2, 4, 7)
+  TEST (2, 2, 4, 7)
+  TEST (3, 2, 4, 7)
+  TEST (4, 2, 4, 7)
+  TEST (5, 2, 4, 7)
+  TEST (6, 2, 4, 7)
+  TEST (7, 2, 4, 7)
+  TEST (0, 3, 4, 7)
+  TEST (1, 3, 4, 7)
+  TEST (2, 3, 4, 7)
+  TEST (3, 3, 4, 7)
+  TEST (4, 3, 4, 7)
+  TEST (5, 3, 4, 7)
+  TEST (6, 3, 4, 7)
+  TEST (7, 3, 4, 7)
+  TEST (0, 4, 4, 7)
+  TEST (1, 4, 4, 7)
+  TEST (2, 4, 4, 7)
+  TEST (3, 4, 4, 7)
+  TEST (4, 4, 4, 7)
+  TEST (5, 4, 4, 7)
+  TEST (6, 4, 4, 7)
+  TEST (7, 4, 4, 7)
+  TEST (0, 5, 4, 7)
+  TEST (1, 5, 4, 7)
+  TEST (2, 5, 4, 7)
+  TEST (3, 5, 4, 7)
+  TEST (4, 5, 4, 7)
+  TEST (5, 5, 4, 7)
+  TEST (6, 5, 4, 7)
+  TEST (7, 5, 4, 7)
+  TEST (0, 6, 4, 7)
+  TEST (1, 6, 4, 7)
+  TEST (2, 6, 4, 7)
+  TEST (3, 6, 4, 7)
+  TEST (4, 6, 4, 7)
+  TEST (5, 6, 4, 7)
+  TEST (6, 6, 4, 7)
+  TEST (7, 6, 4, 7)
+  TEST (0, 7, 4, 7)
+  TEST (1, 7, 4, 7)
+  TEST (2, 7, 4, 7)
+  TEST (3, 7, 4, 7)
+  TEST (4, 7, 4, 7)
+  TEST (5, 7, 4, 7)
+  TEST (6, 7, 4, 7)
+  TEST (7, 7, 4, 7)
+  TEST (0, 0, 5, 7)
+  TEST (1, 0, 5, 7)
+  TEST (2, 0, 5, 7)
+  TEST (3, 0, 5, 7)
+  TEST (4, 0, 5, 7)
+  TEST (5, 0, 5, 7)
+  TEST (6, 0, 5, 7)
+  TEST (7, 0, 5, 7)
+  TEST (0, 1, 5, 7)
+  TEST (1, 1, 5, 7)
+  TEST (2, 1, 5, 7)
+  TEST (3, 1, 5, 7)
+  TEST (4, 1, 5, 7)
+  TEST (5, 1, 5, 7)
+  TEST (6, 1, 5, 7)
+  TEST (7, 1, 5, 7)
+  TEST (0, 2, 5, 7)
+  TEST (1, 2, 5, 7)
+  TEST (2, 2, 5, 7)
+  TEST (3, 2, 5, 7)
+  TEST (4, 2, 5, 7)
+  TEST (5, 2, 5, 7)
+  TEST (6, 2, 5, 7)
+  TEST (7, 2, 5, 7)
+  TEST (0, 3, 5, 7)
+  TEST (1, 3, 5, 7)
+  TEST (2, 3, 5, 7)
+  TEST (3, 3, 5, 7)
+  TEST (4, 3, 5, 7)
+  TEST (5, 3, 5, 7)
+  TEST (6, 3, 5, 7)
+  TEST (7, 3, 5, 7)
+  TEST (0, 4, 5, 7)
+  TEST (1, 4, 5, 7)
+  TEST (2, 4, 5, 7)
+  TEST (3, 4, 5, 7)
+  TEST (4, 4, 5, 7)
+  TEST (5, 4, 5, 7)
+  TEST (6, 4, 5, 7)
+  TEST (7, 4, 5, 7)
+  TEST (0, 5, 5, 7)
+  TEST (1, 5, 5, 7)
+  TEST (2, 5, 5, 7)
+  TEST (3, 5, 5, 7)
+  TEST (4, 5, 5, 7)
+  TEST (5, 5, 5, 7)
+  TEST (6, 5, 5, 7)
+  TEST (7, 5, 5, 7)
+  TEST (0, 6, 5, 7)
+  TEST (1, 6, 5, 7)
+  TEST (2, 6, 5, 7)
+  TEST (3, 6, 5, 7)
+  TEST (4, 6, 5, 7)
+  TEST (5, 6, 5, 7)
+  TEST (6, 6, 5, 7)
+  TEST (7, 6, 5, 7)
+  TEST (0, 7, 5, 7)
+  TEST (1, 7, 5, 7)
+  TEST (2, 7, 5, 7)
+  TEST (3, 7, 5, 7)
+  TEST (4, 7, 5, 7)
+  TEST (5, 7, 5, 7)
+  TEST (6, 7, 5, 7)
+  TEST (7, 7, 5, 7)
+}
+
+void check31(void)
+{
+  TEST (0, 0, 6, 7)
+  TEST (1, 0, 6, 7)
+  TEST (2, 0, 6, 7)
+  TEST (3, 0, 6, 7)
+  TEST (4, 0, 6, 7)
+  TEST (5, 0, 6, 7)
+  TEST (6, 0, 6, 7)
+  TEST (7, 0, 6, 7)
+  TEST (0, 1, 6, 7)
+  TEST (1, 1, 6, 7)
+  TEST (2, 1, 6, 7)
+  TEST (3, 1, 6, 7)
+  TEST (4, 1, 6, 7)
+  TEST (5, 1, 6, 7)
+  TEST (6, 1, 6, 7)
+  TEST (7, 1, 6, 7)
+  TEST (0, 2, 6, 7)
+  TEST (1, 2, 6, 7)
+  TEST (2, 2, 6, 7)
+  TEST (3, 2, 6, 7)
+  TEST (4, 2, 6, 7)
+  TEST (5, 2, 6, 7)
+  TEST (6, 2, 6, 7)
+  TEST (7, 2, 6, 7)
+  TEST (0, 3, 6, 7)
+  TEST (1, 3, 6, 7)
+  TEST (2, 3, 6, 7)
+  TEST (3, 3, 6, 7)
+  TEST (4, 3, 6, 7)
+  TEST (5, 3, 6, 7)
+  TEST (6, 3, 6, 7)
+  TEST (7, 3, 6, 7)
+  TEST (0, 4, 6, 7)
+  TEST (1, 4, 6, 7)
+  TEST (2, 4, 6, 7)
+  TEST (3, 4, 6, 7)
+  TEST (4, 4, 6, 7)
+  TEST (5, 4, 6, 7)
+  TEST (6, 4, 6, 7)
+  TEST (7, 4, 6, 7)
+  TEST (0, 5, 6, 7)
+  TEST (1, 5, 6, 7)
+  TEST (2, 5, 6, 7)
+  TEST (3, 5, 6, 7)
+  TEST (4, 5, 6, 7)
+  TEST (5, 5, 6, 7)
+  TEST (6, 5, 6, 7)
+  TEST (7, 5, 6, 7)
+  TEST (0, 6, 6, 7)
+  TEST (1, 6, 6, 7)
+  TEST (2, 6, 6, 7)
+  TEST (3, 6, 6, 7)
+  TEST (4, 6, 6, 7)
+  TEST (5, 6, 6, 7)
+  TEST (6, 6, 6, 7)
+  TEST (7, 6, 6, 7)
+  TEST (0, 7, 6, 7)
+  TEST (1, 7, 6, 7)
+  TEST (2, 7, 6, 7)
+  TEST (3, 7, 6, 7)
+  TEST (4, 7, 6, 7)
+  TEST (5, 7, 6, 7)
+  TEST (6, 7, 6, 7)
+  TEST (7, 7, 6, 7)
+  TEST (0, 0, 7, 7)
+  TEST (1, 0, 7, 7)
+  TEST (2, 0, 7, 7)
+  TEST (3, 0, 7, 7)
+  TEST (4, 0, 7, 7)
+  TEST (5, 0, 7, 7)
+  TEST (6, 0, 7, 7)
+  TEST (7, 0, 7, 7)
+  TEST (0, 1, 7, 7)
+  TEST (1, 1, 7, 7)
+  TEST (2, 1, 7, 7)
+  TEST (3, 1, 7, 7)
+  TEST (4, 1, 7, 7)
+  TEST (5, 1, 7, 7)
+  TEST (6, 1, 7, 7)
+  TEST (7, 1, 7, 7)
+  TEST (0, 2, 7, 7)
+  TEST (1, 2, 7, 7)
+  TEST (2, 2, 7, 7)
+  TEST (3, 2, 7, 7)
+  TEST (4, 2, 7, 7)
+  TEST (5, 2, 7, 7)
+  TEST (6, 2, 7, 7)
+  TEST (7, 2, 7, 7)
+  TEST (0, 3, 7, 7)
+  TEST (1, 3, 7, 7)
+  TEST (2, 3, 7, 7)
+  TEST (3, 3, 7, 7)
+  TEST (4, 3, 7, 7)
+  TEST (5, 3, 7, 7)
+  TEST (6, 3, 7, 7)
+  TEST (7, 3, 7, 7)
+  TEST (0, 4, 7, 7)
+  TEST (1, 4, 7, 7)
+  TEST (2, 4, 7, 7)
+  TEST (3, 4, 7, 7)
+  TEST (4, 4, 7, 7)
+  TEST (5, 4, 7, 7)
+  TEST (6, 4, 7, 7)
+  TEST (7, 4, 7, 7)
+  TEST (0, 5, 7, 7)
+  TEST (1, 5, 7, 7)
+  TEST (2, 5, 7, 7)
+  TEST (3, 5, 7, 7)
+  TEST (4, 5, 7, 7)
+  TEST (5, 5, 7, 7)
+  TEST (6, 5, 7, 7)
+  TEST (7, 5, 7, 7)
+  TEST (0, 6, 7, 7)
+  TEST (1, 6, 7, 7)
+  TEST (2, 6, 7, 7)
+  TEST (3, 6, 7, 7)
+  TEST (4, 6, 7, 7)
+  TEST (5, 6, 7, 7)
+  TEST (6, 6, 7, 7)
+  TEST (7, 6, 7, 7)
+  TEST (0, 7, 7, 7)
+  TEST (1, 7, 7, 7)
+  TEST (2, 7, 7, 7)
+  TEST (3, 7, 7, 7)
+  TEST (4, 7, 7, 7)
+  TEST (5, 7, 7, 7)
+  TEST (6, 7, 7, 7)
+  TEST (7, 7, 7, 7)
+}
+
+void check(void)
+{
+  check0 ();
+  check1 ();
+  check2 ();
+  check3 ();
+  check4 ();
+  check5 ();
+  check6 ();
+  check7 ();
+  check8 ();
+  check9 ();
+  check10 ();
+  check11 ();
+  check12 ();
+  check13 ();
+  check14 ();
+  check15 ();
+  check16 ();
+  check17 ();
+  check18 ();
+  check19 ();
+  check20 ();
+  check21 ();
+  check22 ();
+  check23 ();
+  check24 ();
+  check25 ();
+  check26 ();
+  check27 ();
+  check28 ();
+  check29 ();
+  check30 ();
+  check31 ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v2df.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v2df.c
new file mode 100644
index 000000000..5aefc05f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v2df.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "isa-check.h"
+#include "sse-os-support.h"
+
+typedef double S;
+typedef double V __attribute__((vector_size(16)));
+typedef long long IV __attribute__((vector_size(16)));
+typedef union { S s[2]; V v; } U;
+
+static U i[2], b, c;
+
+extern int memcmp (const void *, const void *, __SIZE_TYPE__);
+#define assert(T) ((T) || (__builtin_trap (), 0))
+
+#define TEST(E0, E1) \
+  b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1}); \
+  c.s[0] = i[0].s[E0]; \
+  c.s[1] = i[0].s[E1]; \
+  __asm__("" : : : "memory"); \
+  assert (memcmp (&b, &c, sizeof(c)) == 0);
+
+#include "vperm-2-2.inc"
+
+int main()
+{
+  check_isa ();
+
+  if (!sse_os_support ())
+    exit (0);
+
+  i[0].s[0] = 0;
+  i[0].s[1] = 1;
+  i[0].s[2] = 2;
+  i[0].s[3] = 3;
+
+  check();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v2di.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v2di.c
new file mode 100644
index 000000000..282cce6e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v2di.c
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "isa-check.h"
+#include "sse-os-support.h"
+
+typedef long long S;
+typedef long long V __attribute__((vector_size(16)));
+typedef long long IV __attribute__((vector_size(16)));
+typedef union { S s[2]; V v; } U;
+
+static U i[2], b, c;
+
+extern int memcmp (const void *, const void *, __SIZE_TYPE__);
+#define assert(T) ((T) || (__builtin_trap (), 0))
+
+#define TEST(E0, E1) \
+  b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1}); \
+  c.s[0] = i[0].s[E0]; \
+  c.s[1] = i[0].s[E1]; \
+  __asm__("" : : : "memory"); \
+  assert (memcmp (&b, &c, sizeof(c)) == 0);
+
+#include "vperm-2-2.inc"
+
+int main()
+{
+  check_isa ();
+
+  if (!sse_os_support ())
+    exit (0);
+
+  i[0].s[0] = 0;
+  i[0].s[1] = 1;
+  i[0].s[2] = 2;
+  i[0].s[3] = 3;
+
+  check();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c
new file mode 100644
index 000000000..f16c34bc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4sf-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O -msse" } */
+/* { dg-require-effective-target sse } */
+
+#include "isa-check.h"
+#include "sse-os-support.h"
+
+typedef float S;
+typedef float V __attribute__((vector_size(16)));
+typedef int IV __attribute__((vector_size(16)));
+typedef union { S s[4]; V v; } U;
+
+static U i[2], b, c;
+
+extern int memcmp (const void *, const void *, __SIZE_TYPE__);
+#define assert(T) ((T) || (__builtin_trap (), 0))
+
+#define TEST(E0, E1, E2, E3) \
+  b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \
+  c.s[0] = i[0].s[E0]; \
+  c.s[1] = i[0].s[E1]; \
+  c.s[2] = i[0].s[E2]; \
+  c.s[3] = i[0].s[E3]; \
+  __asm__("" : : : "memory"); \
+  assert (memcmp (&b, &c, sizeof(c)) == 0);
+
+#include "vperm-4-1.inc"
+
+int main()
+{
+  check_isa ();
+
+  if (!sse_os_support ())
+    exit (0);
+
+  i[0].s[0] = 0;
+  i[0].s[1] = 1;
+  i[0].s[2] = 2;
+  i[0].s[3] = 3;
+  i[0].s[4] = 4;
+  i[0].s[5] = 5;
+  i[0].s[6] = 6;
+  i[0].s[7] = 7;
+
+  check();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c
new file mode 100644
index 000000000..12a462370
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4sf-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O -mssse3" } */
+
+#include "isa-check.h"
+
+typedef float S;
+typedef float V __attribute__((vector_size(16)));
+typedef int IV __attribute__((vector_size(16)));
+typedef union { S s[4]; V v; } U;
+
+static U i[2], b, c;
+
+extern int memcmp (const void *, const void *, __SIZE_TYPE__);
+#define assert(T) ((T) || (__builtin_trap (), 0))
+
+#define TEST(E0, E1, E2, E3) \
+  b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \
+  c.s[0] = i[0].s[E0]; \
+  c.s[1] = i[0].s[E1]; \
+  c.s[2] = i[0].s[E2]; \
+  c.s[3] = i[0].s[E3]; \
+  __asm__("" : : : "memory"); \
+  assert (memcmp (&b, &c, sizeof(c)) == 0);
+
+#include "vperm-4-2.inc"
+
+int main()
+{
+  check_isa ();
+
+  i[0].s[0] = 0;
+  i[0].s[1] = 1;
+  i[0].s[2] = 2;
+  i[0].s[3] = 3;
+  i[0].s[4] = 4;
+  i[0].s[5] = 5;
+  i[0].s[6] = 6;
+  i[0].s[7] = 7;
+
+  check();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c
new file mode 100644
index 000000000..4667f9556
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-1.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O -msse2" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "isa-check.h"
+#include "sse-os-support.h"
+
+typedef int S;
+typedef int V __attribute__((vector_size(16)));
+typedef int IV __attribute__((vector_size(16)));
+typedef union { S s[4]; V v; } U;
+
+static U i[2], b, c;
+
+extern int memcmp (const void *, const void *, __SIZE_TYPE__);
+#define assert(T) ((T) || (__builtin_trap (), 0))
+
+#define TEST(E0, E1, E2, E3) \
+  b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \
+  c.s[0] = i[0].s[E0]; \
+  c.s[1] = i[0].s[E1]; \
+  c.s[2] = i[0].s[E2]; \
+  c.s[3] = i[0].s[E3]; \
+  __asm__("" : : : "memory"); \
+  assert (memcmp (&b, &c, sizeof(c)) == 0);
+
+#include "vperm-4-1.inc"
+
+int main()
+{
+  check_isa ();
+
+  if (!sse_os_support ())
+    exit (0);
+
+  i[0].s[0] = 0;
+  i[0].s[1] = 1;
+  i[0].s[2] = 2;
+  i[0].s[3] = 3;
+  i[0].s[4] = 4;
+  i[0].s[5] = 5;
+  i[0].s[6] = 6;
+  i[0].s[7] = 7;
+
+  check();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2-sse4.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2-sse4.c
new file mode 100644
index 000000000..1f35b825c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2-sse4.c
@@ -0,0 +1,4 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O -msse4" } */
+#include "vperm-v4si-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c
new file mode 100644
index 000000000..930434555
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ssse3 } */
+/* { dg-options "-O -mssse3" } */
+
+#include "isa-check.h"
+
+typedef int S;
+typedef int V __attribute__((vector_size(16)));
+typedef int IV __attribute__((vector_size(16)));
+typedef union { S s[4]; V v; } U;
+
+static U i[2], b, c;
+
+extern int memcmp (const void *, const void *, __SIZE_TYPE__);
+#define assert(T) ((T) || (__builtin_trap (), 0))
+
+#define TEST(E0, E1, E2, E3) \
+  b.v = __builtin_shuffle (i[0].v, i[1].v, (IV){E0, E1, E2, E3}); \
+  c.s[0] = i[0].s[E0]; \
+  c.s[1] = i[0].s[E1]; \
+  c.s[2] = i[0].s[E2]; \
+  c.s[3] = i[0].s[E3]; \
+  __asm__("" : : : "memory"); \
+  assert (memcmp (&b, &c, sizeof(c)) == 0);
+
+#include "vperm-4-2.inc"
+
+int main()
+{
+  check_isa ();
+
+  i[0].s[0] = 0;
+  i[0].s[1] = 1;
+  i[0].s[2] = 2;
+  i[0].s[3] = 3;
+  i[0].s[4] = 4;
+  i[0].s[5] = 5;
+  i[0].s[6] = 6;
+  i[0].s[7] = 7;
+
+  check();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2x.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2x.c
new file mode 100644
index 000000000..48d1424b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm-v4si-2x.c
@@ -0,0 +1,4 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O -mxop" } */
+#include "vperm-v4si-2.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm.pl b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm.pl
new file mode 100755
index 000000000..80fae9daa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/vperm.pl
@@ -0,0 +1,41 @@
+#!/usr/bin/perl
+
+$nelt = int($ARGV[0]);
+$leng = int($ARGV[1]);
+
+print "/* This file auto-generated with ./vperm.pl $nelt $leng.  */\n\n";
+
+for ($i = 0; $i < $nelt; ++$i) { $perm[$i] = 0; }
+$ncheck = 0;
+
+for ($i = 0; $i < ($leng * $nelt) ** $nelt; ++$i)
+{
+  if ($i % 128 == 0)
+  {
+    print "}\n\n" if $ncheck > 0;
+    print "void check$ncheck(void)\n{\n";
+    ++$ncheck;
+  }
+
+  print "  TEST (";
+  for ($j = 0; $j < $nelt; ++$j)
+  {
+    print $perm[$j];
+    print ", " if $j < $nelt - 1;
+  }
+  print ")\n";
+
+  INCR: for ($j = 0; $j < $nelt; ++$j)
+  {
+    last INCR if ++$perm[$j] < $leng * $nelt;
+    $perm[$j] = 0;
+  }
+}
+print "}\n\n";
+
+print "void check(void)\n{\n";
+for ($i = 0; $i < $ncheck; ++$i)
+{
+  print "  check$i ();\n";
+}
+print "}\n\n";
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c
new file mode 100644
index 000000000..6fecf9262
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { ! { ia32 } } } }  */
+/* { dg-options "-mno-sse -Wvector-operation-performance" }  */
+#define vector(elcount, type)  \
+__attribute__((vector_size((elcount)*sizeof(type)))) type
+
+int main (int argc, char *argv[])
+{
+  vector (4, int) v0 = {argc, 1, 15, 38};
+  vector (4, int) v1 = {-4, argc, 2, 11};
+  vector (4, int) res[] = 
+  {
+    v0 + v1,	  /* { dg-warning "expanded piecewise" }  */
+    v0 - v1,	  /* { dg-warning "expanded piecewise" }  */
+    v0 > v1,	  /* { dg-warning "expanded piecewise" }  */
+    v0 & v1,	  /* { dg-warning "expanded in parallel" }  */
+    __builtin_shuffle (v0, v1),	    /* { dg-warning "expanded piecewise" }  */
+    __builtin_shuffle (v0, v1, v1)  /* { dg-warning "expanded piecewise" }  */  
+  };
+
+  return res[argc][argc];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c
new file mode 100644
index 000000000..6e6311924
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target { ! { ia32 } } } }  */
+/* { dg-options "-mno-sse -Wvector-operation-performance" }  */
+#define vector(elcount, type)  \
+__attribute__((vector_size((elcount)*sizeof(type)))) type
+
+int main (int argc, char *argv[])
+{
+  vector (16, signed char) v0 = {argc, 1, 15, 38, 12, -1, argc, 2, 
+				 argc, 1, 15, 38, 12, -1, argc, 2};
+  vector (16, signed char) v1 = {-4, argc, 2, 11, 1, 17, -8, argc,
+				 argc, 1, 15, 38, 12, -1, argc, 2};
+  vector (16, signed char) res[] = 
+  {
+    v0 + v1,		  /* { dg-warning "expanded in parallel" }  */
+    v0 - v1,              /* { dg-warning "expanded in parallel" }  */
+    v0 > v1,              /* { dg-warning "expanded piecewise" }  */
+    v0 & v1,              /* { dg-warning "expanded in parallel" }  */
+    __builtin_shuffle (v0, v1),        /* { dg-warning "expanded piecewise" }  */
+    __builtin_shuffle (v0, v1, v1)     /* { dg-warning "expanded piecewise" }  */
+  };
+ 
+  return res[argc][argc];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c
new file mode 100644
index 000000000..bdbd8b520
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/warn-vect-op-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { ! { ia32 } } } }  */
+/* { dg-options "-mno-sse -Wvector-operation-performance" }  */
+#define vector(elcount, type)  \
+__attribute__((vector_size((elcount)*sizeof(type)))) type
+
+int main (int argc, char *argv[])
+{
+  vector (8, short) v0 = {argc, 1, 15, 38, 12, -1, argc, 2};
+  vector (8, short) v1 = {-4, argc, 2, 11, 1, 17, -8, argc};
+  vector (8, short) res[] = 
+  {
+    v0 + v1,	      /* { dg-warning "expanded in parallel" }  */
+    v0 - v1,          /* { dg-warning "expanded in parallel" }  */
+    v0 > v1,          /* { dg-warning "expanded piecewise" }  */
+    v0 & v1,          /* { dg-warning "expanded in parallel" }  */
+    __builtin_shuffle (v0, v1),	      /* { dg-warning "expanded piecewise" }  */
+    __builtin_shuffle (v0, v1, v1)    /* { dg-warning "expanded piecewise" }  */
+  };
+  
+  return res[argc][argc];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-1.c
new file mode 100644
index 000000000..4ef8385ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target ia32 } */
+
+long long mac(const int *a, const int *b, long long sqr, long long *sum)
+{
+  int i;
+  long long dotp = *sum;
+
+  for (i = 0; i < 150; i++) {
+    dotp += (long long)b[i] * a[i];
+    sqr += (long long)b[i] * b[i];
+  }
+
+  *sum = dotp;
+  return sqr;
+}
+
+/* { dg-final { scan-assembler-times "imull" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-2.c
new file mode 100644
index 000000000..0a8265445
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/wmul-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target ia32 } */
+
+void vec_mpy(int y[], const int x[], int scaler)
+{
+ int i;
+
+ for (i = 0; i < 150; i++)
+   y[i] += (((long long)scaler * x[i]) >> 31);
+}
+
+/* { dg-final { scan-assembler-times "imull" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/wrfsbase-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/wrfsbase-1.c
new file mode 100644
index 000000000..dc1503817
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/wrfsbase-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfsgsbase" } */
+/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)(edi|ecx)" } } */
+
+#include <immintrin.h>
+
+void
+write_fs_base32 (unsigned int base)
+{
+  _writefsbase_u32 (base);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/wrfsbase-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/wrfsbase-2.c
new file mode 100644
index 000000000..fc4a7b5ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/wrfsbase-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfsgsbase" } */
+/* { dg-final { scan-assembler "wrfsbase\[ \t]+(%|)(rdi|rcx)" } } */
+
+#include <immintrin.h>
+
+void
+write_fs_base64 (unsigned long long base)
+{
+  _writefsbase_u64 (base);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/wrgsbase-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/wrgsbase-1.c
new file mode 100644
index 000000000..5474288be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/wrgsbase-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfsgsbase" } */
+/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)(edi|ecx)" } } */
+
+#include <immintrin.h>
+
+void
+write_gs_base32 (unsigned int base)
+{
+  _writegsbase_u32 (base);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/wrgsbase-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/wrgsbase-2.c
new file mode 100644
index 000000000..cf9475084
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/wrgsbase-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mfsgsbase" } */
+/* { dg-final { scan-assembler "wrgsbase\[ \t]+(%|)(rdi|rcx)" } } */
+
+#include <immintrin.h>
+
+void
+write_gs_base64 (unsigned long long base)
+{
+  _writegsbase_u64 (base);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/writeeflags-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/writeeflags-1.c
new file mode 100644
index 000000000..446840cb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/writeeflags-1.c
@@ -0,0 +1,30 @@
+/* { dg-do run } */
+/* { dg-options "-O0" } */
+
+#include <x86intrin.h>
+
+#ifdef __x86_64__
+#define EFLAGS_TYPE unsigned long long int
+#else
+#define EFLAGS_TYPE unsigned int
+#endif
+
+int
+main ()
+{
+  EFLAGS_TYPE flags = 0xD7; /* 111010111b  */
+
+  __writeeflags (flags);
+
+  flags = __readeflags ();
+
+  if ((flags & 0xFF) != 0xD7)
+    abort ();
+
+#ifdef DEBUG
+    printf ("PASSED\n");
+#endif
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xchg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xchg-1.c
new file mode 100644
index 000000000..e81fe49cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xchg-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=k8" } */
+
+unsigned short good(unsigned short a)
+{
+       return (a >> 8 | a << 8);
+}
+
+/* { dg-final { scan-assembler "rol" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xchg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xchg-2.c
new file mode 100644
index 000000000..f00fb0f21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xchg-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+unsigned short good(unsigned short a)
+{
+       return (a >> 8 | a << 8);
+}
+
+/* { dg-final { scan-assembler "xchgb" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-check.h b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-check.h
new file mode 100644
index 000000000..395abe876
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-check.h
@@ -0,0 +1,28 @@
+#include <stdlib.h>
+
+#include "cpuid.h"
+#include "m256-check.h"
+
+static void xop_test (void);
+
+static void
+__attribute__ ((noinline))
+do_test (void)
+{
+  xop_test ();
+}
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run XOP test only if host has XOP support.  */
+  if (ecx & bit_XOP)
+    do_test ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-frczX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-frczX.c
new file mode 100644
index 000000000..931b5ce39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-frczX.c
@@ -0,0 +1,60 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+
+void
+check_mm_vmfrcz_sd (__m128d __A, __m128d __B)
+{
+  union128d a, b, c;
+  double d[2];
+
+  a.x = __A;
+  b.x = __B;
+  c.x = _mm_frcz_sd (__A, __B);
+  d[0] = b.a[0] - (int)b.a[0] ;
+  d[1] = a.a[1];
+  if (check_union128d (c, d))
+    abort ();
+}
+
+void
+check_mm_vmfrcz_ss (__m128 __A, __m128 __B)
+{
+  union128 a, b, c;
+  float f[4];
+
+  a.x = __A;
+  b.x = __B;
+  c.x = _mm_frcz_ss (__A, __B);
+  f[0] = b.a[0] - (int)b.a[0] ;
+  f[1] = a.a[1];
+  f[2] = a.a[2];
+  f[3] = a.a[3];
+  if (check_union128 (c, f))
+    abort ();
+}
+
+static void
+xop_test (void)
+{
+  union128 a, b;
+  union128d c,d;
+  int i;
+
+  for (i = 0; i < 4; i++)
+    {
+       a.a[i] = i + 3.5;
+       b.a[i] = i + 7.9;
+    }
+  for (i = 0; i < 2; i++)
+    {
+       c.a[i] = i + 3.5;
+       d.a[i] = i + 7.987654321;
+    }
+  check_mm_vmfrcz_ss (a.x, b.x);
+  check_mm_vmfrcz_sd (c.x, d.x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-haddX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-haddX.c
new file mode 100644
index 000000000..7d3220baf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-haddX.c
@@ -0,0 +1,206 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 10
+
+union
+{
+  __m128i x[NUM];
+  signed char ssi[NUM * 16];
+  short si[NUM * 8];
+  int li[NUM * 4];
+  long long lli[NUM * 2];
+} dst, res, src1;
+
+static void
+init_sbyte ()
+{
+  int i;
+  for (i=0; i < NUM * 16; i++)
+    src1.ssi[i] = i;
+}
+
+static void
+init_sword ()
+{
+  int i;
+  for (i=0; i < NUM * 8; i++)
+    src1.si[i] = i;
+}
+
+
+static void
+init_sdword ()
+{
+  int i;
+  for (i=0; i < NUM * 4; i++)
+    src1.li[i] = i;
+}
+
+static int 
+check_sbyte2word ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ;
+	  if (res.si[s] != dst.si[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int 
+check_sbyte2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (4 * j);
+	  s = (i / 4) + j;
+	  res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2]
+	              + src1.ssi[t + 3]); 
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_sbyte2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (8 * j);
+	  s = (i / 8) + j;
+	  res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] 
+		       + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5])
+	               + (src1.ssi[t + 6] + src1.ssi[t + 7])); 
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_sword2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 8); i = i + 8)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.li[s] = src1.si[t] + src1.si[t + 1] ;
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int 
+check_sword2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 8; i = i + 8)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (4 * j);
+	  s = (i / 4) + j;
+	  res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2]
+	               + src1.si[t + 3]); 
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_dword2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 4); i = i + 4)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.lli[s] = src1.li[t] + src1.li[t + 1] ;
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static void
+xop_test (void)
+{
+  int i;
+
+  init_sbyte ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddw_epi8 (src1.x[i]);
+  
+  if (check_sbyte2word())
+  abort ();
+  
+
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_haddd_epi8 (src1.x[i]);
+  
+  if (check_sbyte2dword())
+    abort (); 
+  
+
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epi8 (src1.x[i]);
+  
+  if (check_sbyte2qword())
+    abort ();
+
+
+  init_sword ();
+
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_haddd_epi16 (src1.x[i]);
+  
+  if (check_sword2dword())
+    abort (); 
+
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epi16 (src1.x[i]);
+  
+  if (check_sword2qword())
+    abort ();
+ 
+
+  init_sdword ();
+
+    for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epi32 (src1.x[i]);
+  
+  if (check_dword2qword())
+    abort ();
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-hadduX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-hadduX.c
new file mode 100644
index 000000000..9c7ea9a2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-hadduX.c
@@ -0,0 +1,207 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 10
+
+union
+{
+  __m128i x[NUM];
+  unsigned char  ssi[NUM * 16];
+  unsigned short si[NUM * 8];
+  unsigned int li[NUM * 4];
+  unsigned long long  lli[NUM * 2];
+} dst, res, src1;
+
+static void
+init_byte ()
+{
+  int i;
+  for (i=0; i < NUM * 16; i++)
+    src1.ssi[i] = i;
+}
+
+static void
+init_word ()
+{
+  int i;
+  for (i=0; i < NUM * 8; i++)
+    src1.si[i] = i;
+}
+
+
+static void
+init_dword ()
+{
+  int i;
+  for (i=0; i < NUM * 4; i++)
+    src1.li[i] = i;
+}
+
+static int 
+check_byte2word ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ;
+	  if (res.si[s] != dst.si[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int 
+check_byte2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (4 * j);
+	  s = (i / 4) + j;
+	  res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2]
+	              + src1.ssi[t + 3]); 
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_byte2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (8 * j);
+	  s = (i / 8) + j;
+	  res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] 
+		       + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5])
+	               + (src1.ssi[t + 6] + src1.ssi[t + 7])); 
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_word2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 8); i = i + 8)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.li[s] = src1.si[t] + src1.si[t + 1] ;
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int 
+check_word2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 8; i = i + 8)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (4 * j);
+	  s = (i / 4) + j;
+	  res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2]
+	               + src1.si[t + 3]); 
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;
+	}
+    }
+  return check_fails++;
+}
+
+static int
+check_dword2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 4); i = i + 4)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.lli[s] = src1.li[t] + src1.li[t + 1] ;
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static void
+xop_test (void)
+{
+  int i;
+  
+  /* Check haddubw */
+  init_byte ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddw_epu8 (src1.x[i]);
+  
+  if (check_byte2word())
+  abort ();
+  
+  /* Check haddubd */
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_haddd_epu8 (src1.x[i]);
+  
+  if (check_byte2dword())
+    abort (); 
+  
+  /* Check haddubq */
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epu8 (src1.x[i]);
+  
+  if (check_byte2qword())
+    abort ();
+
+  /* Check hadduwd */
+  init_word ();
+
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_haddd_epu16 (src1.x[i]);
+  
+  if (check_word2dword())
+    abort (); 
+   
+  /* Check haddbuwq */
+ 
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epu16 (src1.x[i]);
+  
+  if (check_word2qword())
+    abort ();
+ 
+  /* Check hadudq */
+  init_dword ();
+    for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_haddq_epu32 (src1.x[i]);
+  
+  if (check_dword2qword())
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-hsubX.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-hsubX.c
new file mode 100644
index 000000000..f0fa9b312
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-hsubX.c
@@ -0,0 +1,128 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+#include <string.h>
+
+#define NUM 10
+
+union
+{
+  __m128i x[NUM];
+  signed char ssi[NUM * 16];
+  short si[NUM * 8];
+  int li[NUM * 4];
+  long long lli[NUM * 2];
+} dst, res, src1;
+
+static void
+init_sbyte ()
+{
+  int i;
+  for (i=0; i < NUM * 16; i++)
+    src1.ssi[i] = i;
+}
+
+static void
+init_sword ()
+{
+  int i;
+  for (i=0; i < NUM * 8; i++)
+    src1.si[i] = i;
+}
+
+
+static void
+init_sdword ()
+{
+  int i;
+  for (i=0; i < NUM * 4; i++)
+    src1.li[i] = i;
+}
+
+static int 
+check_sbyte2word ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < NUM * 16; i = i + 16)
+    {
+      for (j = 0; j < 8; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.si[s] = src1.ssi[t] - src1.ssi[t + 1] ;
+	  if (res.si[s] != dst.si[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int
+check_sword2dword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 8); i = i + 8)
+    {
+      for (j = 0; j < 4; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.li[s] = src1.si[t] - src1.si[t + 1] ;
+	  if (res.li[s] != dst.li[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static int
+check_dword2qword ()
+{
+  int i, j, s, t, check_fails = 0;
+  for (i = 0; i < (NUM * 4); i = i + 4)
+    {
+      for (j = 0; j < 2; j++)
+	{
+	  t = i + (2 * j);
+	  s = (i / 2) + j;
+	  res.lli[s] = src1.li[t] - src1.li[t + 1] ;
+	  if (res.lli[s] != dst.lli[s]) 
+	    check_fails++;	
+	}
+    }
+}
+
+static void
+xop_test (void)
+{
+  int i;
+  
+  /* Check hsubbw */
+  init_sbyte ();
+  
+  for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_hsubw_epi8 (src1.x[i]);
+  
+  if (check_sbyte2word())
+  abort ();
+  
+
+  /* Check hsubwd */
+  init_sword ();
+
+  for (i = 0; i < (NUM ); i++)
+    dst.x[i] = _mm_hsubd_epi16 (src1.x[i]);
+  
+  if (check_sword2dword())
+    abort (); 
+   
+   /* Check hsubdq */
+  init_sdword ();
+    for (i = 0; i < NUM; i++)
+    dst.x[i] = _mm_hsubq_epi32 (src1.x[i]);
+  
+  if (check_dword2qword())
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c
new file mode 100644
index 000000000..0730987e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c
@@ -0,0 +1,36 @@
+/* Test that the compiler properly optimizes floating point multiply and add
+   instructions vector into pmacsdd/etc. on XOP systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mxop -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  int i32[SIZE];
+  long i64[SIZE];
+} a, b, c, d;
+
+void
+imul32_to_64 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i64[i] = ((long)b.i32[i]) * ((long)c.i32[i]);
+}
+
+int main ()
+{
+  imul32_to_64 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vpmuldq" } } */
+/* { dg-final { scan-assembler "vpmacsdqh" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c
new file mode 100644
index 000000000..382677e60
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c
@@ -0,0 +1,36 @@
+/* Test that the compiler properly optimizes floating point multiply and add
+   instructions vector into pmacsdd/etc. on XOP systems.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mxop -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  long i64[SIZE];
+} a, b, c, d;
+
+void
+imul64 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i64[i] = b.i64[i] * c.i64[i];
+}
+
+int main ()
+{
+  imul64 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vpmulld" } } */
+/* { dg-final { scan-assembler "vphadddq" } } */
+/* { dg-final { scan-assembler "vpmacsdql" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-mul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-mul-1.c
new file mode 100644
index 000000000..47ef1bc02
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-mul-1.c
@@ -0,0 +1,13 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O3 -mxop" } */
+
+#ifndef CHECK_H
+#define CHECK_H "xop-check.h"
+#endif
+
+#ifndef TEST
+#define TEST xop_test
+#endif
+
+#include "sse2-mul-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pcmov.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pcmov.c
new file mode 100644
index 000000000..75ed433cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pcmov.c
@@ -0,0 +1,22 @@
+/* Test that the compiler properly optimizes conditional floating point moves
+   into the pcmov instruction on XOP systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mxop" } */
+
+extern void exit (int);
+
+double dbl_test (double a, double b, double c, double d)
+{
+  return (a > b) ? c : d;
+}
+
+double dbl_a = 1, dbl_b = 2, dbl_c = 3, dbl_d = 4, dbl_e;
+
+int main()
+{
+  dbl_e = dbl_test (dbl_a, dbl_b, dbl_c, dbl_d);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vpcmov" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pcmov2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pcmov2.c
new file mode 100644
index 000000000..6b6bd2169
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-pcmov2.c
@@ -0,0 +1,22 @@
+/* Test that the compiler properly optimizes conditional floating point moves
+   into the pcmov instruction on XOP systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mxop" } */
+
+extern void exit (int);
+
+float flt_test (float a, float b, float c, float d)
+{
+  return (a > b) ? c : d;
+}
+
+float flt_a = 1, flt_b = 2, flt_c = 3, flt_d = 4, flt_e;
+
+int main()
+{
+  flt_e = flt_test (flt_a, flt_b, flt_c, flt_d);
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vpcmov" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate1-int.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate1-int.c
new file mode 100644
index 000000000..a58cd726b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate1-int.c
@@ -0,0 +1,63 @@
+/* PR target/49411 */
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+
+extern void abort (void);
+
+union
+{
+  __m128i v;
+  unsigned char c[16];
+  unsigned short s[8];
+  unsigned int i[4];
+  unsigned long long l[2];
+} a, b, c, d;
+
+#define TEST1(F, N, S, SS) \
+do {							\
+  for (i = 0; i < sizeof (a.F) / sizeof (a.F[0]); i++)	\
+    a.F[i] = i * 17;					\
+  s = _mm_set1_epi##SS (N);				\
+  b.v = _mm_roti_epi##S (a.v, N);			\
+  c.v = _mm_rot_epi##S (a.v, s);			\
+  for (i = 0; i < sizeof (a.F) / sizeof (a.F[0]); i++)	\
+    {							\
+      int mask = __CHAR_BIT__ * sizeof (a.F[i]) - 1;	\
+      d.F[i] = a.F[i] << (N & mask);			\
+      if (N & mask)					\
+	d.F[i] |= a.F[i] >> (mask + 1 - (N & mask));	\
+      if (b.F[i] != c.F[i] || b.F[i] != d.F[i])		\
+	abort ();					\
+    }							\
+} while (0)
+#define TEST(N) \
+  TEST1 (c, N, 8, 8);					\
+  TEST1 (s, N, 16, 16);					\
+  TEST1 (i, N, 32, 32);					\
+  TEST1 (l, N, 64, 64x)
+
+volatile int n;
+
+static void
+xop_test (void)
+{
+  unsigned int i;
+  __m128i s;
+
+#ifndef NON_CONST
+  TEST (5);
+  TEST (-5);
+  TEST (0);
+  TEST (31);
+#else
+  n = 5; TEST (n);
+  n = -5; TEST (n);
+  n = 0; TEST (n);
+  n = 31; TEST (n);
+#endif
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c
new file mode 100644
index 000000000..f2b9eb845
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c
@@ -0,0 +1,34 @@
+/* Test that the compiler properly optimizes vector rotate instructions vector
+   into prot on XOP systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mxop -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+left_rotate32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.u32[i] = (b.u32[i] << ((sizeof (int) * 8) - 4)) | (b.u32[i] >> 4);
+}
+
+int
+main ()
+{
+  left_rotate32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vprotd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate2-int.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate2-int.c
new file mode 100644
index 000000000..634a51a84
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate2-int.c
@@ -0,0 +1,7 @@
+/* PR target/49411 */
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#define NON_CONST 1
+#include "xop-rotate1-int.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c
new file mode 100644
index 000000000..11d40023f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c
@@ -0,0 +1,34 @@
+/* Test that the compiler properly optimizes vector rotate instructions vector
+   into prot on XOP systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mxop -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+right_rotate32_b (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - 4)) | (b.u32[i] << 4);
+}
+
+int
+main ()
+{
+  right_rotate ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vprot" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c
new file mode 100644
index 000000000..eb3c61431
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c
@@ -0,0 +1,33 @@
+/* Test that the compiler properly optimizes vector rotate instructions vector
+   into prot on XOP systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mxop -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+vector_rotate32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - c.u32[i])) | (b.u32[i] << c.u32[i]);
+}
+
+int main ()
+{
+  vector_rotate32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vprotd" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c
new file mode 100644
index 000000000..16b3a6b75
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c
@@ -0,0 +1,34 @@
+/* Test that the compiler properly optimizes vector shift instructions into
+   psha/pshl on XOP systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mxop -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  int i32[SIZE];
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+left_shift32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i32[i] = b.i32[i] << c.i32[i];
+}
+
+int main ()
+{
+  left_shfit32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vpshad" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c
new file mode 100644
index 000000000..1f1ed630e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c
@@ -0,0 +1,34 @@
+/* Test that the compiler properly optimizes vector shift instructions into
+   psha/pshl on XOP systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mxop -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  int i32[SIZE];
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+right_sign_shift32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.i32[i] = b.i32[i] >> c.i32[i];
+}
+
+int main ()
+{
+  right_sign_shfit32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vpshad" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c
new file mode 100644
index 000000000..de6417876
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c
@@ -0,0 +1,34 @@
+/* Test that the compiler properly optimizes vector shift instructions into
+   psha/pshl on XOP systems.  */
+
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mxop -ftree-vectorize" } */
+
+extern void exit (int);
+
+typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
+
+#define SIZE 10240
+
+union {
+  __m128i i_align;
+  int i32[SIZE];
+  unsigned u32[SIZE];
+} a, b, c;
+
+void
+right_uns_shift32 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a.u32[i] = b.u32[i] >> c.i32[i];
+}
+
+int main ()
+{
+  right_uns_shfit32 ();
+  exit (0);
+}
+
+/* { dg-final { scan-assembler "vpshld" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-1.c
new file mode 100644
index 000000000..83cb5163d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-1.c
@@ -0,0 +1,57 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+
+#ifndef ZERO_MATCH
+#define ZERO_MATCH  2
+#endif
+
+static double
+select2dp(double *src1, double *src2, long long  sel)
+{
+    double tmp = 0.0;
+
+    if ((sel & 0x3) == 0) tmp = src1[0];
+    if ((sel & 0x3) == 1) tmp = src1[1];
+    if ((sel & 0x3) == 2) tmp = src2[0];
+    if ((sel & 0x3) == 3) tmp = src2[1];
+
+    return tmp;
+}
+
+static double
+sel_and_condzerodp(double *src1, double *src2, long long  sel, int imm8)
+{
+    double tmp;
+
+    tmp = select2dp(src1, src2, sel & 0x3);
+
+    if (((imm8 & 0x3) == 2) && ((sel & 0x4) == 0x4)) tmp = 0;
+    if (((imm8 & 0x3) == 3) && ((sel & 0x4) == 0x0)) tmp = 0;
+
+    return tmp;
+}
+
+void static
+xop_test ()
+{
+    union128d s1, s2, u;
+    union128i_q s3;
+    double e[2];
+
+    s1.x = _mm_set_pd (1, 2);
+    s2.x = _mm_set_pd (3, 4);
+    s3.x = _mm_set_epi64x (1, 2);
+    u.x = _mm_permute2_pd(s1.x, s2.x, s3.x, ZERO_MATCH);
+
+    e[0] = sel_and_condzerodp (s1.a, s2.a, (s3.a[0] & 0xe)>>1, ZERO_MATCH);
+    e[1] = sel_and_condzerodp (s1.a, s2.a, (s3.a[1] & 0xe)>>1, ZERO_MATCH);
+
+    if (check_union128d (u, e))
+      abort ();
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-256-1.c
new file mode 100644
index 000000000..ab2079afa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2pd-256-1.c
@@ -0,0 +1,58 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+
+#ifndef ZERO_MATCH
+#define ZERO_MATCH 1
+#endif
+
+static double
+select2dp(double *src1, double *src2, long long  sel)
+{
+    double tmp = 3.414;
+
+    if ((sel & 0x3) == 0) tmp = src1[0];
+    if ((sel & 0x3) == 1) tmp = src1[1];
+    if ((sel & 0x3) == 2) tmp = src2[0];
+    if ((sel & 0x3) == 3) tmp = src2[1];
+
+    return tmp;
+}
+
+static double
+sel_and_condzerodp(double *src1, double *src2, long long  sel, int imm8)
+{
+    double tmp;
+
+    tmp = select2dp(src1, src2, sel);
+
+    if (((imm8 & 0x3) == 2) && ((sel & 0x4) == 0x4)) tmp = 0;
+    if (((imm8 & 0x3) == 3) && ((sel & 0x4) == 0x0)) tmp = 0;
+
+    return tmp;
+}
+
+void static
+xop_test ()
+{
+    union256d u, s1, s2;
+    double   e[4] = {0.0};
+    union256i_q s3;
+
+    s1.x = _mm256_set_pd (1, 2, 3, 4);
+    s2.x = _mm256_set_pd (5, 6, 7, 8);
+    s3.x = _mm256_set_epi64x (0, 1, 2, 3);
+    u.x = _mm256_permute2_pd(s1.x, s2.x, s3.x, ZERO_MATCH);
+
+    e[0] = sel_and_condzerodp (s1.a, s2.a, (s3.a[0] & 0xe)>>1, ZERO_MATCH);
+    e[1] = sel_and_condzerodp (s1.a, s2.a, (s3.a[1] & 0xe)>>1, ZERO_MATCH);
+    e[2] = sel_and_condzerodp (s1.a + 2, s2.a + 2, (s3.a[2] & 0xe)>>1, ZERO_MATCH);
+    e[3] = sel_and_condzerodp (s1.a + 2, s2.a + 2, (s3.a[3] & 0xe)>>1, ZERO_MATCH);
+
+    if (check_union256d (u, e))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-1.c
new file mode 100644
index 000000000..90e59ae92
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-1.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+
+#ifndef ZERO_MATCH
+#define ZERO_MATCH  1
+#endif
+
+static float
+select2sp(float *src1, float *src2, int sel)
+{
+    float tmp;
+
+    if ((sel & 0x7) == 0) tmp = src1[0];
+    if ((sel & 0x7) == 1) tmp = src1[1];
+    if ((sel & 0x7) == 2) tmp = src1[2];
+    if ((sel & 0x7) == 3) tmp = src1[3];
+    if ((sel & 0x7) == 4) tmp = src2[0];
+    if ((sel & 0x7) == 5) tmp = src2[1];
+    if ((sel & 0x7) == 6) tmp = src2[2];
+    if ((sel & 0x7) == 7) tmp = src2[3];
+
+    return tmp;
+}
+static float
+sel_and_condzerosp(float *src1, float *src2, int sel, int imm8)
+{
+    float tmp;
+
+    tmp = select2sp(src1, src2, sel & 0x7);
+
+    if (((imm8 & 0x3) == 2) && ((sel & 0x8) == 0x8)) tmp = 0;
+    if (((imm8 & 0x3) == 3) && ((sel & 0x8) == 0x0)) tmp = 0;
+
+    return tmp;
+}
+
+void static
+xop_test ()
+{
+    int i;
+    union128  source1, source2, u;
+    union128i_d source3;
+    float s1[4] = {1, 2, 3, 4};
+    float s2[4] = {5, 6, 7, 8};
+    int   s3[4] = {0, 1, 0, 1};
+    float e[4];
+
+    source1.x = _mm_loadu_ps(s1);
+    source2.x = _mm_loadu_ps(s2);
+    source3.x = _mm_loadu_si128((__m128i*) s3);
+    u.x = _mm_permute2_ps(source1.x, source2.x, source3.x, ZERO_MATCH);
+
+    for (i = 0; i < 4; ++i) {
+        e[i] = sel_and_condzerosp(&s1[i & 0x4], &s2[i & 0x4], s3[i] & 0xf, ZERO_MATCH & 0x3);
+    }
+
+    if (check_union128 (u, e))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-256-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-256-1.c
new file mode 100644
index 000000000..d458d3e49
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vpermil2ps-256-1.c
@@ -0,0 +1,64 @@
+/* { dg-do run } */
+/* { dg-require-effective-target xop } */
+/* { dg-options "-O2 -mxop" } */
+
+#include "xop-check.h"
+
+#include <x86intrin.h>
+
+#ifndef ZERO_MATCH
+#define ZERO_MATCH  3
+#endif
+
+static float
+select2sp(float *src1, float *src2, int sel)
+{
+    float tmp;
+
+    if ((sel & 0x7) == 0) tmp = src1[0];
+    if ((sel & 0x7) == 1) tmp = src1[1];
+    if ((sel & 0x7) == 2) tmp = src1[2];
+    if ((sel & 0x7) == 3) tmp = src1[3];
+    if ((sel & 0x7) == 4) tmp = src2[0];
+    if ((sel & 0x7) == 5) tmp = src2[1];
+    if ((sel & 0x7) == 6) tmp = src2[2];
+    if ((sel & 0x7) == 7) tmp = src2[3];
+
+    return tmp;
+}
+static float
+sel_and_condzerosp(float *src1, float *src2, int sel, int imm8)
+{
+    float tmp;
+
+    tmp = select2sp(src1, src2, sel & 0x7);
+
+    if (((imm8 & 0x3) == 2) && ((sel & 0x8) == 0x8)) tmp = 0;
+    if (((imm8 & 0x3) == 3) && ((sel & 0x8) == 0x0)) tmp = 0;
+
+    return tmp;
+}
+
+void static
+xop_test ()
+{
+    int i;
+    union256  source1, source2, u;
+    union256i_d source3;
+    float s1[8]={1, 2, 3, 4, 5, 6, 7, 8};
+    float s2[8]={9, 10, 11, 12, 13, 14, 15, 16};
+    int   s3[8]={11, 2, 3, 15, 5, 12, 7, 8};
+    float  e[8];
+
+    source1.x = _mm256_loadu_ps(s1);
+    source2.x = _mm256_loadu_ps(s2);
+    source3.x = _mm256_loadu_si256((__m256i*) s3);
+    u.x = _mm256_permute2_ps(source1.x, source2.x, source3.x, ZERO_MATCH);
+
+    for (i = 0; i < 8; ++i) {
+        e[i] = sel_and_condzerosp(&s1[i & 0x4], &s2[i & 0x4], s3[i] & 0xf, ZERO_MATCH & 0x3);
+    }
+
+   if (check_union256(u, e))
+     abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vshift-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vshift-1.c
new file mode 100644
index 000000000..ee3d29903
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vshift-1.c
@@ -0,0 +1,145 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mxop" } */
+/* { dg-require-effective-target xop } */
+
+#ifndef CHECK_H
+#define CHECK_H "xop-check.h"
+#endif
+
+#ifndef TEST
+#define TEST xop_test
+#endif
+
+#include CHECK_H
+
+#define N 64
+
+#ifndef TYPE1
+#define TYPE1 int
+#define TYPE2 long long
+#endif
+
+/* mingw runtime don't provide random().  */
+#ifdef __MINGW32__
+#define random rand
+#endif
+
+signed TYPE1 a[N], b[N], g[N];
+unsigned TYPE1 c[N], h[N];
+signed TYPE2 d[N], e[N], j[N];
+unsigned TYPE2 f[N], k[N];
+
+__attribute__((noinline)) void
+f1 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    g[i] = a[i] << b[i];
+}
+
+__attribute__((noinline)) void
+f2 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    g[i] = a[i] >> b[i];
+}
+
+__attribute__((noinline)) void
+f3 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    h[i] = c[i] >> b[i];
+}
+
+__attribute__((noinline)) void
+f4 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    j[i] = d[i] << e[i];
+}
+
+__attribute__((noinline)) void
+f5 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    j[i] = d[i] >> e[i];
+}
+
+__attribute__((noinline)) void
+f6 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    k[i] = f[i] >> e[i];
+}
+
+__attribute__((noinline)) void
+f7 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    j[i] = d[i] << b[i];
+}
+
+__attribute__((noinline)) void
+f8 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    j[i] = d[i] >> b[i];
+}
+
+__attribute__((noinline)) void
+f9 (void)
+{
+  int i;
+  for (i = 0; i < N; i++)
+    k[i] = f[i] >> b[i];
+}
+
+static void
+TEST ()
+{
+  int i;
+  for (i = 0; i < N; i++)
+    {
+      asm ("");
+      c[i] = (random () << 1) | (random () & 1);
+      b[i] = (i * 85) & (sizeof (TYPE1) * __CHAR_BIT__ - 1);
+      a[i] = c[i];
+      d[i] = (random () << 1) | (random () & 1);
+      d[i] |= (unsigned long long) c[i] << 32;
+      e[i] = (i * 85) & (sizeof (TYPE2) * __CHAR_BIT__ - 1);
+      f[i] = d[i];
+    }
+  f1 ();
+  f3 ();
+  f4 ();
+  f6 ();
+  for (i = 0; i < N; i++)
+    if (g[i] != (signed TYPE1) (a[i] << b[i])
+	|| h[i] != (unsigned TYPE1) (c[i] >> b[i])
+	|| j[i] != (signed TYPE2) (d[i] << e[i])
+	|| k[i] != (unsigned TYPE2) (f[i] >> e[i]))
+      abort ();
+  f2 ();
+  f5 ();
+  f9 ();
+  for (i = 0; i < N; i++)
+    if (g[i] != (signed TYPE1) (a[i] >> b[i])
+	|| j[i] != (signed TYPE2) (d[i] >> e[i])
+	|| k[i] != (unsigned TYPE2) (f[i] >> b[i]))
+      abort ();
+  f7 ();
+  for (i = 0; i < N; i++)
+    if (j[i] != (signed TYPE2) (d[i] << b[i]))
+      abort ();
+  f8 ();
+  for (i = 0; i < N; i++)
+    if (j[i] != (signed TYPE2) (d[i] >> b[i]))
+      abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vshift-2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vshift-2.c
new file mode 100644
index 000000000..81e86d098
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xop-vshift-2.c
@@ -0,0 +1,8 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mxop" } */
+/* { dg-require-effective-target xop } */
+
+#define TYPE1 char
+#define TYPE2 short
+
+#include "xop-vshift-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps-sse.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps-sse.c
new file mode 100644
index 000000000..e9c0a2e73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps-sse.c
@@ -0,0 +1,14 @@
+/* Test that we generate xorps instruction when pxor is not available.  */
+/* { dg-do compile } */
+/* { dg-options "-O -msse -mno-sse2" } */
+/* { dg-final { scan-assembler "xorps\[ \t\]" } } */
+
+#define vector __attribute__ ((vector_size (16)))
+
+vector int i(vector int f)
+{
+  vector int g = { 0x80000000, 0, 0x80000000, 0 };
+  vector int f_int = (vector int) f;
+  return (f_int ^ g);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps-sse2.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps-sse2.c
new file mode 100644
index 000000000..b9576d970
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps-sse2.c
@@ -0,0 +1,15 @@
+/* Test that we generate xorps when the result is used in FP math.  */
+/* { dg-do compile } */
+/* { dg-options "-O -msse2 -mno-sse3" } */
+/* { dg-final { scan-assembler "xorps\[ \t\]" } } */
+/* { dg-final { scan-assembler-not "pxor" } } */
+
+#define vector __attribute__ ((vector_size (16)))
+
+vector float i(vector float f, vector float h)
+{
+  vector int g = { 0x80000000, 0, 0x80000000, 0 };
+  vector int f_int = (vector int) f;
+  return ((vector float) (f_int ^ g)) + h;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps.c
new file mode 100644
index 000000000..6803a4d89
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xorps.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -msse2" } */
+
+typedef float __m128 __attribute__ ((vector_size (16)));
+
+static __inline __m128
+_mm_mul_ps (__m128 __A, __m128 __B)
+{
+  return __builtin_ia32_mulps (__A, __B);
+}
+
+static __inline __m128
+_mm_sub_ps (__m128 __A, __m128 __B)
+{
+  return  __builtin_ia32_subps (__A, __B);
+}
+
+__m128 POW_FUNC (__m128 x, __m128 y)
+{
+    __m128 xmm0 = x, xmm1 = y, xmm2;
+
+    xmm0 = __builtin_ia32_xorps (xmm1, xmm1);
+
+    xmm0 = _mm_mul_ps (xmm0, xmm1);
+
+    xmm0 = _mm_sub_ps (xmm0, xmm1);
+
+    xmm0 = _mm_mul_ps (xmm0, xmm1);
+
+    return xmm0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xrstor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xrstor-1.c
new file mode 100644
index 000000000..3e7013948
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xrstor-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx -O2" } */
+/* { dg-final { scan-assembler "xrstor\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+xsave_test (void)
+{
+  char xsave_region [512] __attribute__((aligned(64)));
+  _xrstor (xsave_region, ((long long) 0xA0000000F));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xrstor64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xrstor64-1.c
new file mode 100644
index 000000000..3cf2a66cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xrstor64-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mxsave -O2" } */
+/* { dg-final { scan-assembler "xrstor64\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+xsave_test (void)
+{
+  char xsave_region [512] __attribute__((aligned(64)));
+  _xrstor64 (xsave_region, ((long long) 0xA0000000F));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xsave-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xsave-1.c
new file mode 100644
index 000000000..9eee59739
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xsave-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mxsave -O2" } */
+/* { dg-final { scan-assembler "xsave\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+xsave_test (void)
+{
+  char xsave_region [512] __attribute__((aligned(64)));
+  _xsave (xsave_region, ((long long) 0xA0000000F));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xsave64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xsave64-1.c
new file mode 100644
index 000000000..661da9171
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xsave64-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mxsave -O2" } */
+/* { dg-final { scan-assembler "xsave64\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+xsave_test (void)
+{
+  char xsave_region [512] __attribute__((aligned(64)));
+  _xsave64 (xsave_region, ((long long) 0xA0000000F));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xsaveopt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xsaveopt-1.c
new file mode 100644
index 000000000..b08a50a23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xsaveopt-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mxsaveopt -O2" } */
+/* { dg-final { scan-assembler "xsaveopt\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+xsave_test (void)
+{
+  char xsaveopt_region [512] __attribute__((aligned(64)));
+  _xsaveopt (xsaveopt_region, ((long long) 0xA0000000F));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/xsaveopt64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/xsaveopt64-1.c
new file mode 100644
index 000000000..f7864fe39
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/xsaveopt64-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mxsaveopt -O2" } */
+/* { dg-final { scan-assembler "xsaveopt64\[ \\t\]" } } */
+
+#include <x86intrin.h>
+
+void extern
+xsave_test (void)
+{
+  char xsaveopt_region [512] __attribute__((aligned(64)));
+  _xsaveopt64 (xsaveopt_region, ((long long) 0xA0000000F));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/i386/zee.c b/gcc-4.9/gcc/testsuite/gcc.target/i386/zee.c
new file mode 100644
index 000000000..1975b02b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/i386/zee.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -fzee" } */
+/* { dg-final { scan-assembler-not "mov\[\\t \]+\(%\[\^,\]+\),\[\\t \]*\\1" } } */
+int mask[100];
+int foo(unsigned x)
+{
+  if (x < 10)
+    x = x * 45;
+  else
+    x = x * 78;
+  return mask[x];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20010423-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20010423-1.c
new file mode 100644
index 000000000..4cec79370
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20010423-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int __sync_fetch_and_add_si (int *, int);
+
+inline unsigned int
+bar (volatile unsigned int *mem, unsigned int val)
+{
+  return __sync_fetch_and_add_si((int *)mem, (int)val);
+}
+
+volatile unsigned int x;
+
+void foo (unsigned short *a)
+{
+  *a = bar (&x, 1) + 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20020313-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20020313-1.c
new file mode 100644
index 000000000..bc134febf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20020313-1.c
@@ -0,0 +1,72 @@
+/* PR 5312 
+   The problem here is that the ia64 scheduler saw a sequence of L L M type
+   insns, and messed up its internal state on which slot it was issuing
+   to, and aborted.  */
+
+/* { dg-do compile } */
+/* In ILP32 mode, we get warnings about large integer constants.
+   Those cause spurious FAILs.  */
+/* { dg-options "-w -O2 -mconstant-gp" } */
+
+typedef unsigned long __u64;
+typedef unsigned int __u32;
+typedef struct { } spinlock_t;
+struct cpuinfo_ia64 {
+        union {
+                struct {
+                        __u32 irq_count;
+                        __u32 bh_count;
+                } f;
+                __u64 irq_and_bh_counts;
+        } irq_stat;
+        __u32 softirq_pending;
+} __attribute__ ((aligned ((1UL << 14)))) ;
+enum
+{
+        TCA_UNSPEC,
+        TCA_KIND,
+        TCA_OPTIONS,
+        TCA_STATS,
+        TCA_XSTATS,
+        TCA_RATE,
+};
+struct tc_stats
+{
+        __u64 bytes;
+        __u32 packets;
+        __u32 drops;
+        __u32 overlimits;
+        __u32 bps;
+        __u32 pps;
+        __u32 qlen;
+        __u32 backlog;
+        spinlock_t *lock;
+};
+struct sk_buff {
+        unsigned int data_len;
+        unsigned char *tail;
+        unsigned char *end;
+};
+static inline int skb_is_nonlinear(const struct sk_buff *skb)
+{
+        return skb->data_len;
+}
+static inline int skb_tailroom(const struct sk_buff *skb)
+{
+        return skb_is_nonlinear(skb) ? 0 : skb->end-skb->tail;
+}
+struct rtattr
+{
+        unsigned short rta_len;
+        unsigned short rta_type;
+};
+int qdisc_copy_stats(struct sk_buff *skb, struct tc_stats *st)
+{
+        do { do { (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count)++; __asm__ __volatile__("": : :"memory"); } while (0); (void)(st->lock); } while (0);
+        ({ if (skb_tailroom(skb) < (int)( (((( ((sizeof(struct rtattr))+4 -1) & ~(4 -1) ) + ((char*)&st->lock - (char*)st)))+4 -1) & ~(4 -1) )) goto rtattr_failure; __rta_fill(skb, TCA_STATS, (char*)&st->lock - (char*)st, st); });
+        do { do { } while(0); do { do { __asm__ __volatile__("": : :"memory"); (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count)--; } while (0); if (__builtin_expect((((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->softirq_pending), 0) && (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count) == 0) do_softirq(); } while (0); } while (0);
+        return 0;
+rtattr_failure:
+        do { do { } while(0); do { do { __asm__ __volatile__("": : :"memory"); (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count)--; } while (0); if (__builtin_expect((((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->softirq_pending), 0) && (((struct cpuinfo_ia64 *) (0xa000000000000000 + 2*(1UL << 14)))->irq_stat.f.bh_count) == 0) do_softirq(); } while (0); } while (0);
+        return -1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20020326-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20020326-1.c
new file mode 100644
index 000000000..16da750ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20020326-1.c
@@ -0,0 +1,11 @@
+/* PR target/6054 */
+/* { dg-do compile } */
+/* { dg-options "-O -mconstant-gp" } */
+/* { dg-final { scan-assembler "mov r1 =" } } */
+
+extern void direct (void);
+void foo(void (*indirect) (void))
+{
+  indirect ();
+  direct ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030225-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030225-2.c
new file mode 100644
index 000000000..278180777
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030225-2.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int __attribute__((noinline, const))
+ret4 (float value)
+{
+  return 4;
+}
+
+int __attribute__((noinline, const))
+ret0 (float value)
+{
+  return 0;
+}
+
+float __attribute__((noinline))
+test (float x, float y)
+{
+  int clsx = ret4 (x);
+  int clsy = ret0 (y);
+
+  if (clsx == 0 || clsy == 0
+      || (y < 0 && clsx == 1 && clsy == 1))
+    return x - y;
+
+  return x < y ? 0 : x - y;
+}
+
+float a = 0.0, b;
+
+int main (void)
+{
+  unsigned long e;
+  b = a / a;
+  __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (e));
+  e &= ~0x7e000UL;
+  __asm__ __volatile__ ("mov.m ar.fpsr=%0" :: "r" (e) : "memory");
+  a = test (0, b);
+  __asm__ __volatile__ ("mov.m %0=ar.fpsr" : "=r" (e));
+  if (e & 0x2000)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030405-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030405-1.c
new file mode 100644
index 000000000..510638ce5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030405-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+foo (int x, int y)
+{
+  if (y == 0)
+    {
+      register long r8 asm ("r8");
+      register long r15 asm ("r15") = 1;
+      long retval;
+      __asm __volatile ("foo" : "=r" (r8), "=r" (r15) : "1" (r15));
+      retval = r8;
+      y = retval;
+    }
+
+  {
+    register long r8 asm ("r8");
+    register long r15 asm ("r15") = 2;
+    long retval;
+    register long _out1 asm ("out1") = x;
+    register long _out0 asm ("out0") = y;
+    __asm __volatile ("foo"
+		      : "=r" (r8), "=r" (r15) , "=r" (_out0), "=r" (_out1)
+		      : "1" (r15) , "2" (_out0), "3" (_out1));
+    retval = r8;
+    return retval;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030811-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030811-1.c
new file mode 100644
index 000000000..45f78b361
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20030811-1.c
@@ -0,0 +1,59 @@
+/* Origin: PR target/11693 from Andreas Schwab <schwab@suse.de> */
+/* { dg-do compile } */
+/* { dg-options "-O2 -frename-registers" } */
+
+static inline unsigned long long
+foo (void)
+{
+  unsigned long long x;
+  __asm__ __volatile__ ("" : "=r" (x) :: "memory");
+  return x;
+}
+
+static inline void
+bar (unsigned long long x, unsigned long long y)
+{
+  __asm__ __volatile__ ("" :: "r"(x), "r"(y) : "memory");
+}
+
+static inline void
+baz (unsigned long long x, unsigned long long y, unsigned long long z,
+     unsigned long long p, unsigned long long q)
+{
+  __asm__ __volatile__ ("" :: "r" (q << 2) : "memory");
+  __asm__ __volatile__ ("" :: "r" (z) : "memory");
+  if (x & 0x1)
+    __asm__ __volatile__ ("" :: "r" (y), "r" (p) : "memory");
+  if (x & 0x2)
+    __asm__ __volatile__ ("" :: "r" (y), "r" (p) : "memory");
+}
+
+static inline unsigned long long
+ffz (unsigned long long x)
+{
+  unsigned long long r;
+  __asm__ ("" : "=r" (r) : "r" (x & (~x - 1)));
+  return r;
+}
+
+void die (const char *, ...) __attribute__ ((noreturn));
+
+void
+test (void *x)
+{
+  unsigned long long a, c;
+
+  a = foo ();
+  bar (0xc000000000000000LL, 0x660);
+  bar (0xa00000000000c000LL, 0x539);
+  baz (2, 1, 0xa000000000008000LL,
+       ({ unsigned long long b;
+	  b = ({ unsigned long long d; __asm__ ("" : "=r" (d) : "r" (x)); d; })
+	      + 0x10000000000661LL;
+	  b;
+	}),
+       14);
+  c = ffz (0x1fffffffffffffffLL);
+  if (c < 51 || c > 61)
+    die ("die", c - 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20040303-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20040303-1.c
new file mode 100644
index 000000000..60b5c528f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20040303-1.c
@@ -0,0 +1,20 @@
+/* Test floating point division on ia64.  There was a bug in the
+   max-throughput version of the inline division code.  Expecting an
+   exact value from a floating point expression is unwise but GCC
+   depends on it in allocno_compare.  */
+
+/* { dg-do run } */
+/* { dg-options "-minline-float-divide-max-throughput" } */
+
+extern void abort (void);
+
+volatile int i = 24;
+volatile int j = 30;
+volatile int k = 1;
+
+int main()
+{
+        int pri2 = (((double) i / j) * (10000 / 1000) * k);
+        if (pri2 != 8) abort();
+	return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20040709-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20040709-2.c
new file mode 100644
index 000000000..585ab06f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20040709-2.c
@@ -0,0 +1,151 @@
+/* Check for ia64 data speculation failure with '-O2 -funroll-loops'.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -funroll-loops -Wno-overflow" } */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned int
+myrnd (void)
+{
+  static unsigned int s = 1388815473;
+  s *= 1103515245;
+  s += 12345;
+  return (s / 65536) % 2048;
+}
+
+#define T(S)					\
+struct S s##S;					\
+struct S retme##S (struct S x)			\
+{						\
+  return x;					\
+}						\
+						\
+unsigned int fn1##S (unsigned int x)		\
+{						\
+  struct S y = s##S;				\
+  y.k += x;					\
+  y = retme##S (y);				\
+  return y.k;					\
+}						\
+						\
+unsigned int fn2##S (unsigned int x)		\
+{						\
+  struct S y = s##S;				\
+  y.k += x;					\
+  y.k %= 15;					\
+  return y.k;					\
+}						\
+						\
+unsigned int retit##S (void)			\
+{						\
+  return s##S.k;				\
+}						\
+						\
+unsigned int fn3##S (unsigned int x)		\
+{						\
+  s##S.k += x;					\
+  return retit##S ();				\
+}						\
+						\
+void test##S (void)				\
+{						\
+  int i;					\
+  unsigned int mask, v, a, r;			\
+  struct S x;					\
+  char *p = (char *) &s##S;			\
+  for (i = 0; i < sizeof (s##S); ++i)		\
+    *p++ = myrnd ();				\
+  if (__builtin_classify_type (s##S.l) == 8)	\
+    s##S.l = 5.25;				\
+  s##S.k = -1;					\
+  mask = s##S.k;				\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn1##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || x.k != s##S.k || x.l != s##S.l		\
+      || ((v + a) & mask) != r)			\
+    abort ();					\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn2##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || x.k != s##S.k || x.l != s##S.l		\
+      || ((((v + a) & mask) % 15) & mask) != r)	\
+    abort ();					\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn3##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || s##S.k != r || x.l != s##S.l		\
+      || ((v + a) & mask) != r)			\
+    abort ();					\
+}
+
+#define pck __attribute__((packed))
+struct pck A { unsigned short i : 1, l : 1, j : 3, k : 11; }; T(A)
+struct pck B { unsigned short i : 4, j : 1, k : 11; unsigned int l; }; T(B)
+struct pck C { unsigned int l; unsigned short i : 4, j : 1, k : 11; }; T(C)
+struct pck D { unsigned long long l : 6, i : 6, j : 23, k : 29; }; T(D)
+struct pck E { unsigned long long l, i : 12, j : 23, k : 29; }; T(E)
+struct pck F { unsigned long long i : 12, j : 23, k : 29, l; }; T(F)
+struct pck G { unsigned short i : 1, j : 1, k : 6; unsigned long long l; }; T(G)
+struct pck H { unsigned short i : 6, j : 2, k : 8; unsigned long long l; }; T(H)
+struct pck I { unsigned short i : 1, j : 6, k : 1; unsigned long long l; }; T(I)
+struct pck J { unsigned short i : 1, j : 8, k : 7; unsigned short l; }; T(J)
+struct pck K { unsigned int k : 6, l : 1, j : 10, i : 15; }; T(K)
+struct pck L { unsigned int k : 6, j : 11, i : 15; unsigned int l; }; T(L)
+struct pck M { unsigned int l; unsigned short k : 6, j : 11, i : 15; }; T(M)
+struct pck N { unsigned long long l : 6, k : 6, j : 23, i : 29; }; T(N)
+struct pck O { unsigned long long l, k : 12, j : 23, i : 29; }; T(O)
+struct pck P { unsigned long long k : 12, j : 23, i : 29, l; }; T(P)
+struct pck Q { unsigned short k : 12, j : 1, i : 3; unsigned long long l; }; T(Q)
+struct pck R { unsigned short k : 2, j : 11, i : 3; unsigned long long l; }; T(R)
+struct pck S { unsigned short k : 1, j : 6, i : 9; unsigned long long l; }; T(S)
+struct pck T { unsigned short k : 1, j : 8, i : 7; unsigned short l; }; T(T)
+struct pck U { unsigned short j : 6, k : 1, i : 9; unsigned long long l; }; T(U)
+struct pck V { unsigned short j : 8, k : 1, i : 7; unsigned short l; }; T(V)
+struct pck W { long double l; unsigned int k : 12, j : 13, i : 7; }; T(W)
+struct pck X { unsigned int k : 12, j : 13, i : 7; long double l; }; T(X)
+struct pck Y { unsigned int k : 12, j : 11, i : 9; long double l; }; T(Y)
+struct pck Z { long double l; unsigned int j : 13, i : 7, k : 12; }; T(Z)
+
+int
+main (void)
+{
+  testA ();
+  testB ();
+  testC ();
+  testD ();
+  testE ();
+  testF ();
+  testG ();
+  testH ();
+  testI ();
+  testJ ();
+  testK ();
+  testL ();
+  testM ();
+  testN ();
+  testO ();
+  testP ();
+  testQ ();
+  testR ();
+  testS ();
+  testT ();
+  testU ();
+  testV ();
+  testW ();
+  testX ();
+  testY ();
+  testZ ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20071210-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20071210-2.c
new file mode 100644
index 000000000..96a20a73f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20071210-2.c
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fselective-scheduling2" } */
+
+extern void abort (void);
+
+struct S
+{
+  int n1, n2, n3, n4;
+};
+
+__attribute__((noinline)) struct S
+foo (int x, int y, int z)
+{
+  if (x != 10 || y != 9 || z != 8)
+    abort ();
+  struct S s = { 1, 2, 3, 4 };
+  return s;
+}
+
+__attribute__((noinline)) void **
+bar (void **u, int *v)
+{
+  void **w = u;
+  int *s = v, x, y, z;
+  void **p, **q;
+  static void *l[] = { &&lab1, &&lab1, &&lab2, &&lab3, &&lab4 };
+
+  if (!u)
+    return l;
+
+  q = *w++;
+  goto *q;
+lab2:
+  p = q;
+  q = *w++;
+  x = s[2];
+  y = s[1];
+  z = s[0];
+  s -= 1;
+  struct S r = foo (x, y, z);
+  s[3] = r.n1;
+  s[2] = r.n2;
+  s[1] = r.n3;
+  s[0] = r.n4;
+  goto *q;
+lab3:
+  p = q;
+  q = *w++;
+  s += 1;
+  s[0] = 23;
+lab1:
+  goto *q;
+lab4:
+  return 0;
+}
+
+int
+main (void)
+{
+  void **u = bar ((void **) 0, (int *) 0);
+  void *t[] = { u[2], u[4] };
+  int s[] = { 7, 8, 9, 10, 11, 12 };
+  if (bar (t, &s[1]) != (void **) 0
+      || s[0] != 4 || s[1] != 3 || s[2] != 2 || s[3] != 1
+      || s[4] != 11 || s[5] != 12)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20080802-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20080802-1.c
new file mode 100644
index 000000000..b689a5d8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20080802-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msched-control-spec" } */
+
+struct cpp_reader;
+
+extern const char * parse_include (struct cpp_reader *, int *m, void *);
+extern int _cpp_compare_file_date (struct cpp_reader *, const char *, int);
+
+void
+_cpp_init_internal_pragmas (struct cpp_reader *pfile)
+{
+  const char *fname;
+  int angle_brackets, ordering;
+
+  fname = parse_include (pfile, &angle_brackets, (void *) 0);
+  if (!fname)
+    return;
+  ordering = _cpp_compare_file_date (pfile, fname, angle_brackets);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20090324-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20090324-1.c
new file mode 100644
index 000000000..d9aff6a18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20090324-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -fmodulo-sched" } */
+
+static char *place_region_bounds_x, *place_region_bounds_y;
+static void read_place () {
+  char msg[300];
+  update_screen (msg);
+}
+static void alloc_and_load_placement_structs () {
+  int i, j;
+  for (j=0;
+      j<100;
+      j++) {
+    place_region_bounds_x[i] = place_region_bounds_x[i-1];
+    place_region_bounds_y[i] = place_region_bounds_y[i-1];
+  }
+}
+void place_and_route () {
+  read_place ();
+  alloc_and_load_placement_structs ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/20101014.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20101014.c
new file mode 100644
index 000000000..c3e3e9f35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/20101014.c
@@ -0,0 +1,66 @@
+/* { dg-do compile } */
+/* { dg-options "-w -O2 -g -fselective-scheduling2" } */
+
+typedef long unsigned int size_t;
+struct fileloc
+{
+  const char *file;
+};
+typedef struct type *type_p;
+typedef const struct type *const_type_p;
+enum typekind
+{
+  TYPE_STRUCT,
+  TYPE_UNION,
+  TYPE_POINTER,
+  TYPE_LANG_STRUCT,
+  TYPE_PARAM_STRUCT
+};
+struct type
+{
+  enum typekind kind;
+  union
+  {
+    struct
+    {
+      struct fileloc line;
+    } s;
+    struct
+    {
+      struct fileloc line;
+    } param_struct;
+  } u;
+};
+struct outf
+{
+  size_t bufused;
+  char *buf;
+};
+typedef struct outf *outf_p;
+oprintf (outf_p o, const char *format, ...)
+{
+  char *s;
+  size_t slength;
+  memcpy (o->buf + o->bufused, s, slength);
+}
+output_mangled_typename (outf_p of, const_type_p t)
+{
+    switch (t->kind)
+      {
+      case TYPE_POINTER: (fancy_abort ("/gcc/gengtype.c", 1988, __FUNCTION__));
+    }
+}
+output_type_enum (outf_p of, type_p s)
+{
+  if (s->kind == TYPE_PARAM_STRUCT && s->u.param_struct.line.file != ((void *)0))
+    {
+      oprintf (of, ", gt_e_");
+    }
+  else if (((s)->kind == TYPE_UNION || (s)->kind == TYPE_STRUCT || (s)->kind == TYPE_LANG_STRUCT) && s->u.s.line.file != ((void *)0))
+    {
+      oprintf (of, ", gt_ggc_e_");
+      output_mangled_typename (of, s);
+    }
+  else
+    oprintf (of, ", gt_types_enum_last");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/asm-1.c
new file mode 100644
index 000000000..0acfee589
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/asm-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-options } */
+
+extern void abort (void);
+
+/* Test that "=S" properly avoids the post-increment on the memory address.  */
+
+static void foo(int *x)
+{
+  long i;
+  for (i = 0; i < 100; ++i)
+    __asm__("st4 %0 = r0" : "=S"(x[i]));
+}
+
+int main()
+{
+  int array[100];
+  long i;
+
+  for (i = 0; i < 100; ++i)
+    array[i] = -1;
+
+  foo(array);
+
+  for (i = 0; i < 100; ++i)
+    if (array[i])
+      abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-bswap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-bswap-1.c
new file mode 100644
index 000000000..381e3fe22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-bswap-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "mux1" } } */
+
+long foo (long x)
+{
+  return __builtin_bswap64 (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-bswap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-bswap-2.c
new file mode 100644
index 000000000..96f32c702
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-bswap-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "mux1" } } */
+
+int foo (int x)
+{
+  return __builtin_bswap32 (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-fma-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-fma-1.c
new file mode 100644
index 000000000..a4b2e063c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-fma-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+/* Don't confuse the fma insn with the fma in the filename.  */
+/* { dg-final { scan-assembler-times "fma\\." 4 } } */
+/* { dg-final { scan-assembler-times "fms" 2 } } */
+/* { dg-final { scan-assembler-times "fnma" 4 } } */
+
+#ifndef __FP_FAST_FMAF
+# error "__FP_FAST_FMAF should be defined"
+#endif
+#ifndef __FP_FAST_FMA
+# error "__FP_FAST_FMA should be defined"
+#endif
+
+float f0(float x, float y, float z) { return __builtin_fmaf(x,y,z); }
+float f1(float x, float y, float z) { return __builtin_fmaf(x,y,-z); }
+float f2(float x, float y, float z) { return __builtin_fmaf(-x,y,z); }
+float f3(float x, float y, float z) { return __builtin_fmaf(x,-y,z); }
+float f4(float x, float y, float z) { return __builtin_fmaf(-x,-y,z); }
+
+double d0(double x, double y, double z) { return __builtin_fma(x,y,z); }
+double d1(double x, double y, double z) { return __builtin_fma(x,y,-z); }
+double d2(double x, double y, double z) { return __builtin_fma(-x,y,z); }
+double d3(double x, double y, double z) { return __builtin_fma(x,-y,z); }
+double d4(double x, double y, double z) { return __builtin_fma(-x,-y,z); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-fma-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-fma-2.c
new file mode 100644
index 000000000..16d95b70c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-fma-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-skip-if "128-bit long double" { *-*-hpux* } { "*" } { "" } } */
+/* { dg-options "-O" } */
+/* Don't confuse the fma insn with the fma in the filename.  */
+/* { dg-final { scan-assembler-times "fma\[ 	\]" 2 } } */
+/* { dg-final { scan-assembler-times "fms" 1 } } */
+/* { dg-final { scan-assembler-times "fnma" 2 } } */
+
+#ifndef __FP_FAST_FMAL
+# error "__FP_FAST_FMAL should be defined"
+#endif
+
+typedef long double LD;
+
+LD L0(LD x, LD y, LD z) { return __builtin_fmal(x,y,z); }
+LD L1(LD x, LD y, LD z) { return __builtin_fmal(x,y,-z); }
+LD L2(LD x, LD y, LD z) { return __builtin_fmal(-x,y,z); }
+LD L3(LD x, LD y, LD z) { return __builtin_fmal(x,-y,z); }
+LD L4(LD x, LD y, LD z) { return __builtin_fmal(-x,-y,z); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-popcount-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-popcount-1.c
new file mode 100644
index 000000000..c9641d0e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-popcount-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "popcnt" } } */
+
+int foo (int x)
+{
+  return __builtin_popcount (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-popcount-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-popcount-2.c
new file mode 100644
index 000000000..50ced72e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/builtin-popcount-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "popcnt" } } */
+
+int foo (int x)
+{
+  return __builtin_popcount (x) == 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-1.c
new file mode 100644
index 000000000..38e9c870f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-1.c
@@ -0,0 +1,12 @@
+/* Bug 14610 */
+/* { dg-do run } */
+
+extern void abort(void);
+volatile __float80 x = 30.0;
+
+int main(void)
+{
+  double d = x;
+  if (d != 30.0) abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-2.c
new file mode 100644
index 000000000..346daa7ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-2.c
@@ -0,0 +1,13 @@
+/* Bug 14610 */
+/* { dg-do run } */
+/* { dg-options "-minline-int-divide-max-throughput" } */
+
+extern void abort(void);
+volatile int j = 30;
+
+int main(void)
+{
+  if (29 % j != 29) abort();
+  if (30 % j != 0)  abort();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-varargs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-varargs-1.c
new file mode 100644
index 000000000..96524be6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/float80-varargs-1.c
@@ -0,0 +1,33 @@
+/* Test for a bug with passing __float80 in varargs.  The __float80
+   value was wrongly passed, leading to an abort.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do run } */
+/* { dg-options "" } */
+
+#include <stdarg.h>
+
+extern void abort (void);
+extern void exit (int);
+
+__float80 s = 1.234L;
+__float80 d;
+
+void vf (int a0, ...);
+
+int
+main (void)
+{
+  vf (0, s);
+  if (d != s)
+    abort ();
+  exit (0);
+}
+
+void
+vf (int a0, ...)
+{
+  va_list ap;
+  va_start (ap, a0);
+  d = va_arg (ap, __float80);
+  va_end (ap);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/fpreg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/fpreg-1.c
new file mode 100644
index 000000000..8c9e21d7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/fpreg-1.c
@@ -0,0 +1,82 @@
+/* Test permitted and invalid uses of __fpreg.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+__float80 f80;
+double d;
+/* Default initialized __fpreg is OK.  */
+__fpreg fpreg, fpreg2;
+/* But explicitly zero-initialized is an invalid conversion.  */
+__fpreg fi = 0; /* { dg-error "invalid conversion to '__fpreg'" } */
+
+__fpreg f0 (__fpreg);
+int f1 (__float80);
+
+/* __fpreg in a structure is OK.  */
+struct s {
+  __float80 b;
+  __fpreg a;
+} x;
+
+void
+f (void)
+{
+  __fpreg *p;
+  /* Valid operations.  */
+  fpreg = fpreg2;
+  fpreg2 = (__fpreg) fpreg;
+  fpreg = f0 (fpreg2);
+  fpreg = +fpreg2;
+  p = &fpreg;
+  (void) fpreg;
+  fpreg = x.a;
+  fpreg2 = (struct s) { 0 }.a;
+  fpreg = (d ? fpreg : fpreg2);
+  d = sizeof (fpreg);
+  (void)(fpreg, fpreg);
+  /* Invalid operations.  */
+  ++fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  --fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg++; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg--; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = -fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = ~fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = !fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = *fpreg; /* { dg-error "invalid type argument" } */
+  if (fpreg) /* { dg-error "invalid operation on '__fpreg'" } */
+    return;
+  d = fpreg; /* { dg-error "invalid conversion from '__fpreg'" } */
+  d = (double) fpreg; /* { dg-error "invalid conversion from '__fpreg'" } */
+  fpreg = (__fpreg) d; /* { dg-error "invalid conversion to '__fpreg'" } */
+  fpreg = fpreg * fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg / fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg % fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg + fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg - fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg << fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = fpreg >> fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg < fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg > fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg <= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg >= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg == fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg != fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg & fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg ^ fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg | fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg && fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = fpreg || fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  d = (fpreg ? 1 : 2); /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg = (d ? fpreg : d); /* { dg-error "invalid conversion to '__fpreg'" } */
+  fpreg *= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg /= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg %= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg += fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg -= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg <<= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg >>= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg &= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg ^= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+  fpreg |= fpreg; /* { dg-error "invalid operation on '__fpreg'" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/fpreg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/fpreg-2.c
new file mode 100644
index 000000000..a21bd0fb2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/fpreg-2.c
@@ -0,0 +1,21 @@
+/* Test __fpreg ABI.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-options "" } */
+/* { dg-final { scan-assembler "ldf.fill" } } */
+/* { dg-final { scan-assembler "stf.spill" } } */
+
+__fpreg x;
+
+void f (void);
+
+void
+g (void)
+{
+  __fpreg b = x;
+  f ();
+  x = b;
+}
+
+char t1[(sizeof (__fpreg) == sizeof (__float80) ? 1 : -1)];
+char t2[(__alignof (__fpreg) == __alignof (__float80) ? 1 : -1)];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/fptr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/fptr-1.c
new file mode 100644
index 000000000..b3d4536bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/fptr-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target ia64-*-linux* } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "@ltoffx\\(os_boot_rendez#\\)" } } */
+/* { dg-final { scan-assembler "@ltoff\\(@fptr\\(os_boot_rendez#\\)\\)" } } */
+
+/* Test function descriptor access.  */
+
+struct ia64_fdesc
+{
+  unsigned long func;
+  unsigned long gp;
+};
+
+void
+os_boot_rendez (void)
+{
+}
+
+extern int check (unsigned long);
+
+int
+main (int argc, char **argv)
+{
+  int i;
+  int res = 0;
+
+  for (i = 0; i < 1; i++)
+    res += check (((struct ia64_fdesc *) os_boot_rendez)->gp);
+  return res;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/got-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/got-1.c
new file mode 100644
index 000000000..7a12ebd02
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/got-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC" } */
+
+/* { dg-final { scan-assembler "@ltoffx\\(object#\\)" } } */
+/* { dg-final { scan-assembler "@ltoffx\\(object#\[-+\]16384\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]1\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]8191\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]8192\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]8193\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]16383\\)" } } */
+/* { dg-final { scan-assembler-not "@ltoffx\\(object#\[-+\]16385\\)" } } */
+
+/* must not be in sdata */
+extern char object[];
+
+#define r(n) char *r_##n (void) { return &object[n]; }
+#define R(n) char *R_##n (void) { return &object[-n]; }
+
+#define t(n) r(n) R(n)
+
+t(0) t(1)
+t(8191) t(8192) t(8193)
+t(16383) t(16384) t(16385)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/ia64.exp b/gcc-4.9/gcc/testsuite/gcc.target/ia64/ia64.exp
new file mode 100644
index 000000000..d70e990c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/ia64.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 1997-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an IA-64 target.
+if ![istarget ia64*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/mfused-madd-vect.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/mfused-madd-vect.c
new file mode 100644
index 000000000..e166e85da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/mfused-madd-vect.c
@@ -0,0 +1,33 @@
+/* { dg-do compile */
+/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-final { scan-assembler-not "fpmpy" } } */
+
+/* fpma and fpms will show in either way because there are no
+   specific vector add/sub instructions.  So we just check for fpmpy.  */
+
+#define N 16
+extern bar(float *, float *, float *, float *);
+void foo()
+{
+	int i;
+	float a[N], b[N], c[N], d[N];
+	bar(a,b,c,d);
+	for (i = 0; i < N; i++) {
+		a[i] = b[i] + c[i] * d[i];
+	}
+	bar(a,b,c,d);
+#if 0
+	for (i = 0; i < N; i++) {
+		a[i] = b[i] - c[i] * d[i];
+	}
+	bar(a,b,c,d);
+#endif
+	for (i = 0; i < N; i++) {
+		a[i] = b[i] * c[i] + d[i];
+	}
+	bar(a,b,c,d);
+	for (i = 0; i < N; i++) {
+		a[i] = b[i] * c[i] - d[i];
+	}
+	bar(a,b,c,d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/mfused-madd.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/mfused-madd.c
new file mode 100644
index 000000000..8ecb31f0d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/mfused-madd.c
@@ -0,0 +1,64 @@
+/* { dg-do compile */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "fmpy" } } */
+/* { dg-final { scan-assembler-not "fadd" } } */
+/* { dg-final { scan-assembler-not "fsub" } } */
+/* { dg-final { scan-assembler "fma" } } */
+/* { dg-final { scan-assembler "fms" } } */
+/* { dg-final { scan-assembler "fnma" } } */
+
+float foo01(float a, float b, float c) {return (a + b * c);}
+float foo02(float a, float b, float c) {return (a - b * c);}
+float foo03(float a, float b, float c) {return (a * b + c);}
+float foo04(float a, float b, float c) {return (a * b - c);}
+
+double foo05(double a, double b, double c) {return (a + b * c);}
+double foo06(double a, double b, double c) {return (a - b * c);}
+double foo07(double a, double b, double c) {return (a * b + c);}
+double foo08(double a, double b, double c) {return (a * b - c);}
+
+__float80 foo09(__float80 a, __float80 b, __float80 c) {return (a + b * c);}
+__float80 foo10(__float80 a, __float80 b, __float80 c) {return (a - b * c);}
+__float80 foo11(__float80 a, __float80 b, __float80 c) {return (a * b + c);}
+__float80 foo12(__float80 a, __float80 b, __float80 c) {return (a * b - c);}
+
+
+
+float foo20(double a, double b, double c) {return (float) (a + b * c);}
+float foo21(double a, double b, double c) {return (float) (a - b * c);}
+float foo22(double a, double b, double c) {return (float) (a * b + c);}
+float foo23(double a, double b, double c) {return (float) (a * b - c);}
+
+float foo24(__float80 a, __float80 b, __float80 c) {return (float) (a + b * c);}
+float foo25(__float80 a, __float80 b, __float80 c) {return (float) (a - b * c);}
+float foo26(__float80 a, __float80 b, __float80 c) {return (float) (a * b + c);}
+float foo27(__float80 a, __float80 b, __float80 c) {return (float) (a * b - c);}
+
+double foo28(__float80 a, __float80 b, __float80 c) {return (double) (a + b * c);}
+double foo29(__float80 a, __float80 b, __float80 c) {return (double) (a - b * c);}
+double foo30(__float80 a, __float80 b, __float80 c) {return (double) (a * b + c);}
+double foo31(__float80 a, __float80 b, __float80 c) {return (double) (a * b - c);}
+
+
+float foo001(float a, float b, double c) { return (a + b * c); }
+float foo002(float a, float b, double c) { return (a - b * c); }
+
+float foo005(float a, double b, double c) { return (a + b * c); }
+float foo006(float a, double b, double c) { return (a - b * c); }
+float foo007(float a, double b, double c) { return (a * b + c); }
+float foo008(float a, double b, double c) { return (a * b - c); }
+
+double foo009(double a, float b, double c) { return (a + b * c); }
+double foo010(double a, float b, double c) { return (a - b * c); }
+double foo011(double a, float b, double c) { return (a * b + c); }
+double foo012(double a, float b, double c) { return (a * b - c); }
+
+float foo013(float a, double b, __float80 c) { return (a + b * c); }
+float foo014(float a, double b, __float80 c) { return (a - b * c); }
+float foo017(double a, float b, __float80 c) { return (a + b * c); }
+float foo018(double a, float b, __float80 c) { return (a - b * c); }
+
+float foo021(float a, __float80 b, double c) { return (a + b * c); }
+float foo022(float a, __float80 b, double c) { return (a - b * c); }
+float foo023(float a, __float80 b, double c) { return (a * b + c); }
+float foo024(float a, __float80 b, double c) { return (a * b - c); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/mno-fused-madd-vect.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/mno-fused-madd-vect.c
new file mode 100644
index 000000000..fd80d061a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/mno-fused-madd-vect.c
@@ -0,0 +1,31 @@
+/* { dg-do compile */
+/* { dg-options "-O2 -ffp-contract=off -ftree-vectorize" } */
+/* { dg-final { scan-assembler "fpmpy" } } */
+
+/* fpma and fpms will show in either way because there are no
+   specific vector add/sub instructions.  So we just check for fpmpy.  */
+
+#define N 16
+extern bar(float *, float *, float *, float *);
+void foo()
+{
+	int i;
+	float a[N], b[N], c[N], d[N];
+	bar(a,b,c,d);
+	for (i = 0; i < N; i++) {
+		a[i] = b[i] + c[i] * d[i];
+	}
+	bar(a,b,c,d);
+	for (i = 0; i < N; i++) {
+		a[i] = b[i] - c[i] * d[i];
+	}
+	bar(a,b,c,d);
+	for (i = 0; i < N; i++) {
+		a[i] = b[i] * c[i] + d[i];
+	}
+	bar(a,b,c,d);
+	for (i = 0; i < N; i++) {
+		a[i] = b[i] * c[i] - d[i];
+	}
+	bar(a,b,c,d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/mno-fused-madd.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/mno-fused-madd.c
new file mode 100644
index 000000000..487519add
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/mno-fused-madd.c
@@ -0,0 +1,64 @@
+/* { dg-do compile */
+/* { dg-options "-O2 -ffp-contract=off" } */
+/* { dg-final { scan-assembler-not "fma" } } */
+/* { dg-final { scan-assembler-not "fms" } } */
+/* { dg-final { scan-assembler-not "fnma" } } */
+/* { dg-final { scan-assembler "fmpy" } } */
+/* { dg-final { scan-assembler "fadd" } } */
+/* { dg-final { scan-assembler "fsub" } } */
+
+float foo01(float a, float b, float c) {return (a + b * c);}
+float foo02(float a, float b, float c) {return (a - b * c);}
+float foo03(float a, float b, float c) {return (a * b + c);}
+float foo04(float a, float b, float c) {return (a * b - c);}
+
+double foo05(double a, double b, double c) {return (a + b * c);}
+double foo06(double a, double b, double c) {return (a - b * c);}
+double foo07(double a, double b, double c) {return (a * b + c);}
+double foo08(double a, double b, double c) {return (a * b - c);}
+
+__float80 foo09(__float80 a, __float80 b, __float80 c) {return (a + b * c);}
+__float80 foo10(__float80 a, __float80 b, __float80 c) {return (a - b * c);}
+__float80 foo11(__float80 a, __float80 b, __float80 c) {return (a * b + c);}
+__float80 foo12(__float80 a, __float80 b, __float80 c) {return (a * b - c);}
+
+
+
+float foo20(double a, double b, double c) {return (float) (a + b * c);}
+float foo21(double a, double b, double c) {return (float) (a - b * c);}
+float foo22(double a, double b, double c) {return (float) (a * b + c);}
+float foo23(double a, double b, double c) {return (float) (a * b - c);}
+
+float foo24(__float80 a, __float80 b, __float80 c) {return (float) (a + b * c);}
+float foo25(__float80 a, __float80 b, __float80 c) {return (float) (a - b * c);}
+float foo26(__float80 a, __float80 b, __float80 c) {return (float) (a * b + c);}
+float foo27(__float80 a, __float80 b, __float80 c) {return (float) (a * b - c);}
+
+double foo28(__float80 a, __float80 b, __float80 c) {return (double) (a + b * c);}
+double foo29(__float80 a, __float80 b, __float80 c) {return (double) (a - b * c);}
+double foo30(__float80 a, __float80 b, __float80 c) {return (double) (a * b + c);}
+double foo31(__float80 a, __float80 b, __float80 c) {return (double) (a * b - c);}
+
+
+float foo001(float a, float b, double c) { return (a + b * c); }
+float foo002(float a, float b, double c) { return (a - b * c); }
+
+float foo005(float a, double b, double c) { return (a + b * c); }
+float foo006(float a, double b, double c) { return (a - b * c); }
+float foo007(float a, double b, double c) { return (a * b + c); }
+float foo008(float a, double b, double c) { return (a * b - c); }
+
+double foo009(double a, float b, double c) { return (a + b * c); }
+double foo010(double a, float b, double c) { return (a - b * c); }
+double foo011(double a, float b, double c) { return (a * b + c); }
+double foo012(double a, float b, double c) { return (a * b - c); }
+
+float foo013(float a, double b, __float80 c) { return (a + b * c); }
+float foo014(float a, double b, __float80 c) { return (a - b * c); }
+float foo017(double a, float b, __float80 c) { return (a + b * c); }
+float foo018(double a, float b, __float80 c) { return (a - b * c); }
+
+float foo021(float a, __float80 b, double c) { return (a + b * c); }
+float foo022(float a, __float80 b, double c) { return (a - b * c); }
+float foo023(float a, __float80 b, double c) { return (a * b + c); }
+float foo024(float a, __float80 b, double c) { return (a * b - c); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/postinc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/postinc-1.c
new file mode 100644
index 000000000..93c30d872
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/postinc-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-options "-O2 -mlp64" { target ia64-*-hpux* } } */
+
+void copy_loop_ldouble (void *xdest,
+                        const void *xsrc,
+                        long roff,
+                        long soff,
+                        long len,
+                        long shift)
+{ __float128 *dest = xdest;
+  const long double *src;
+  long i;
+  roff /= sizeof (__float128);
+  soff /= sizeof (__float128);
+  src = xsrc;
+  src += shift * soff;
+  for (i = 0; i < len - shift; ++i) {
+        *dest = *src;
+        dest += roff;
+        src += soff;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr29682.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr29682.c
new file mode 100644
index 000000000..ecca32392
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr29682.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target ia64-*-* } } */
+/* { dg-options "-O3 -msched-control-spec" } */
+typedef long unsigned int size_t;
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+typedef uint8_t byte;
+typedef enum pgpArmor_e
+{
+  PGPARMOR_ERR_CRC_CHECK = -7, PGPARMOR_ERR_BODY_DECODE =
+    -3, PGPARMOR_ERR_UNKNOWN_ARMOR_TYPE = -2, PGPARMOR_ERR_NO_BEGIN_PGP =
+    -1, PGPARMOR_NONE = 0, PGPARMOR_MESSAGE = 1, PGPARMOR_PUBKEY =
+    5, PGPARMOR_PRIVKEY = 6, PGPARMOR_SECKEY = 7
+}
+pgpArmor;
+pgpCRC (const byte * octets, size_t len)
+{
+  unsigned int crc = 0xb704ce;
+  int i;
+  while (len--)
+    {
+      for (i = 0; i < 8; i++)
+	{
+	  crc <<= 1;
+	  if (crc & 0x1000000)
+	    crc ^= 0x1864cfb;
+	}
+    }
+}
+pgpReadPkts (const char *fn, const byte ** pkt, size_t * pktlen)
+{
+  const byte *b = ((void *) 0);
+  const char *enc = ((void *) 0);
+  byte *dec;
+  size_t declen;
+  uint32_t crcpkt, crc;
+  int pstate = 0;
+  pgpArmor ec = PGPARMOR_ERR_NO_BEGIN_PGP;
+    {
+      switch (pstate)
+	{
+	case 0:
+	  if (b64decode (enc, (void **) &dec, &declen) != 0)
+	    {
+	      goto exit;
+	    }
+	  crc = pgpCRC (dec, declen);
+	}
+    }
+exit:if (ec > PGPARMOR_NONE && pkt)
+    *pkt = b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-1.c
new file mode 100644
index 000000000..9ce66f494
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-1.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -ftree-vectorize" } */
+
+unsigned int v1[] __attribute__ ((aligned(16))) =
+{
+  0x80000000, 1, 0xa0000000, 2,
+  3, 0xd0000000, 0xf0000000, 0xe0000000
+};
+unsigned int v2[] __attribute__ ((aligned(16))) =
+{
+  4, 0xb0000000, 5, 0xc0000000,
+  0xd0000000, 6, 7, 8
+};
+
+unsigned int max[] =
+{
+  0x80000000, 0xb0000000, 0xa0000000, 0xc0000000,
+  0xd0000000, 0xd0000000, 0xf0000000, 0xe0000000
+};
+
+unsigned int min[] =
+{
+  4, 1, 5, 2,
+  3, 6, 7, 8
+};
+
+unsigned int res[8] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 8; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+int main (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 8; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 8; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-2.c
new file mode 100644
index 000000000..d41eef383
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-2.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -ftree-vectorize" } */
+
+unsigned short v1[] __attribute__ ((aligned(16))) =
+{
+  0x8000, 0x9000, 1, 10, 0xa000, 0xb000, 2, 20,
+  3, 30, 0xd000, 0xe000, 0xf000, 0xe000, 25, 30
+};
+unsigned short v2[] __attribute__ ((aligned(16))) =
+{
+  4, 40, 0xb000, 0x8000, 5, 50, 0xc000, 0xf000,
+  0xd000, 0xa000, 6, 65, 7, 75, 0xe000, 0xc000
+};
+
+unsigned short max[] =
+{
+  0x8000, 0x9000, 0xb000, 0x8000, 0xa000, 0xb000, 0xc000, 0xf000,
+  0xd000, 0xa000, 0xd000, 0xe000, 0xf000, 0xe000, 0xe000, 0xc000
+};
+
+unsigned short min[] =
+{
+  4, 40, 1, 10, 5, 50, 2, 20,
+  3, 30, 6, 65, 7, 75, 25, 30
+};
+
+unsigned short res[16] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 16; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+int main (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 16; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 16; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-3.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-3.c
new file mode 100644
index 000000000..29e090883
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr42542-3.c
@@ -0,0 +1,76 @@
+/* { dg-do run } */
+/* { dg-options "-O1 -ftree-vectorize" } */
+
+unsigned char v1[] __attribute__ ((aligned(16))) =
+{
+  0x80, 0xd0, 0x90, 0xa0, 1, 15, 10, 15,
+  0xa0, 0xc0, 0xb0, 0xf0, 2, 25, 20, 35,
+  3, 34, 30, 36, 0xd0, 0x80, 0xe0, 0xb0,
+  0xf0, 0xe0, 0xe0, 0x80, 25, 34, 30, 40
+};
+unsigned char v2[] __attribute__ ((aligned(16))) =
+{
+  4, 44, 40, 48, 0xb0, 0x80, 0x80, 0x90,
+  5, 55, 50, 51, 0xc0, 0xb0, 0xf0, 0xd0,
+  0xd0, 0x80, 0xa0, 0xf0, 6, 61, 65, 68,
+  7, 76, 75, 81, 0xe0, 0xf0, 0xc0, 0x90
+};
+
+unsigned char max[] =
+{
+  0x80, 0xd0, 0x90, 0xa0, 0xb0, 0x80, 0x80, 0x90,
+  0xa0, 0xc0, 0xb0, 0xf0, 0xc0, 0xb0, 0xf0, 0xd0,
+  0xd0, 0x80, 0xa0, 0xf0, 0xd0, 0x80, 0xe0, 0xb0,
+  0xf0, 0xe0, 0xe0, 0x80, 0xe0, 0xf0, 0xc0, 0x90
+};
+
+unsigned char min[] =
+{
+  4, 44, 40, 48, 1, 15, 10, 15,
+  5, 55, 50, 51, 2, 25, 20, 35,
+  3, 34, 30, 36, 6, 61, 65, 68,
+  7, 76, 75, 81, 25, 34, 30, 40
+};
+
+unsigned char res[32] __attribute__ ((aligned(16)));
+
+extern void abort (void);
+
+void
+find_max (void)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    res[i] = v1[i] < v2[i] ? v2[i] : v1[i];
+}
+
+void
+find_min (void)
+{
+  int i;
+
+  for (i = 0; i < 32; i++)
+    res[i] = v1[i] > v2[i] ? v2[i] : v1[i];
+}
+
+int main (void)
+{
+  int i;
+  int err = 0;
+
+  find_max ();
+  for (i = 0; i < 32; i++)
+    if (res[i] != max[i])
+      err++;
+
+  find_min ();
+  for (i = 0; i < 32; i++)
+    if (res[i] != min[i])
+      err++;
+
+  if (err)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr43603.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr43603.c
new file mode 100644
index 000000000..ad3a5b114
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr43603.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+int 
+foo( long * np, int * dp, int qn)
+{
+  int i;
+  int n0;
+  int d0;
+  int a;
+  int b;
+  int c;
+  int d;
+
+  a = 1;
+  b = 0;
+  c = 1;
+  d = 1;
+
+  d0 = dp[0];
+
+  for (i = qn; i >= 0; i--) {
+    if (bar((c == 0)) && (np[1] == d0)) {
+      car(np - 3, dp, 3);
+    } else { 
+      __asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" : "=&f" ((a)), 
+"=f" (b) : "f" ((c)), "f" ((d))); 
+      n0 = np[0]; 
+      if (n0 < d0) 
+        c = 1; 
+      else 
+        c = 0; 
+
+    }
+    *--np = a;
+  }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr43897.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr43897.c
new file mode 100644
index 000000000..fb73e8692
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr43897.c
@@ -0,0 +1,12 @@
+/* PR target/43897 */
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+int
+sub (int i)
+{
+  float tmp;
+  if (i)
+    __asm__ __volatile__ ("frcpa.s0 %0,p1=f0,f0":"=f" (tmp)::"p1");
+  return i + 10;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr48496.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr48496.c
new file mode 100644
index 000000000..6e604336a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr48496.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef unsigned int UINT64 __attribute__((__mode__(__DI__)));
+
+typedef struct
+{
+  UINT64 x[2] __attribute__((aligned(16)));
+} fpreg;
+
+struct ia64_args
+{
+  fpreg fp_regs[8];
+  UINT64 gp_regs[8];
+};
+
+ffi_call(long i, long gpcount, long fpcount, void **avalue)
+{
+  struct ia64_args *stack;
+  stack = __builtin_alloca (64);
+  asm ("stf.spill %0 = %1%P0" : "=m" (*&stack->fp_regs[fpcount++])
+                              : "f"(*(double *)avalue[i]));
+  stack->gp_regs[gpcount++] = *(UINT64 *)avalue[i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr49303.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr49303.c
new file mode 100644
index 000000000..2d88304f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr49303.c
@@ -0,0 +1,185 @@
+/* { dg-do compile } */
+/* { dg-options "-w -O2 -fselective-scheduling2 -fsel-sched-pipelining" } */
+
+typedef struct rtx_def *rtx;
+typedef const struct rtx_def *const_rtx;
+typedef struct basic_block_def *basic_block;
+enum machine_mode {
+  VOIDmode, BLKmode, CCmode, CCImode, BImode, QImode, HImode, SImode, DImode, TImode, OImode, QQmode, HQmode, SQmode, DQmode, TQmode, UQQmode, UHQmode, USQmode, UDQmode, UTQmode, HAmode, SAmode, DAmode, TAmode, UHAmode, USAmode, UDAmode, UTAmode, SFmode, DFmode, XFmode, RFmode, TFmode, SDmode, DDmode, TDmode, CQImode, CHImode, CSImode, CDImode, CTImode, COImode, SCmode, DCmode, XCmode, RCmode, TCmode, V4QImode, V2HImode, V8QImode, V4HImode, V2SImode, V16QImode, V8HImode, V4SImode, V2SFmode, V4SFmode, MAX_MACHINE_MODE, MIN_MODE_RANDOM = VOIDmode, MAX_MODE_RANDOM = BLKmode, MIN_MODE_CC = CCmode, MAX_MODE_CC = CCImode, MIN_MODE_INT = QImode, MAX_MODE_INT = OImode, MIN_MODE_PARTIAL_INT = VOIDmode, MAX_MODE_PARTIAL_INT = VOIDmode, MIN_MODE_FRACT = QQmode, MAX_MODE_FRACT = TQmode, MIN_MODE_UFRACT = UQQmode, MAX_MODE_UFRACT = UTQmode, MIN_MODE_ACCUM = HAmode, MAX_MODE_ACCUM = TAmode, MIN_MODE_UACCUM = UHAmode, MAX_MODE_UACCUM = UTAmode, MIN_MODE_FLOAT = SFmode, MAX_MODE_FLOAT = TFmode, MIN_MODE_DECIMAL_FLOAT = SDmode, MAX_MODE_DECIMAL_FLOAT = TDmode, MIN_MODE_COMPLEX_INT = CQImode, MAX_MODE_COMPLEX_INT = COImode, MIN_MODE_COMPLEX_FLOAT = SCmode, MAX_MODE_COMPLEX_FLOAT = TCmode, MIN_MODE_VECTOR_INT = V4QImode, MAX_MODE_VECTOR_INT = V4SImode, MIN_MODE_VECTOR_FRACT = VOIDmode, MAX_MODE_VECTOR_FRACT = VOIDmode, MIN_MODE_VECTOR_UFRACT = VOIDmode, MAX_MODE_VECTOR_UFRACT = VOIDmode, MIN_MODE_VECTOR_ACCUM = VOIDmode, MAX_MODE_VECTOR_ACCUM = VOIDmode, MIN_MODE_VECTOR_UACCUM = VOIDmode, MAX_MODE_VECTOR_UACCUM = VOIDmode, MIN_MODE_VECTOR_FLOAT = V2SFmode, MAX_MODE_VECTOR_FLOAT = V4SFmode, NUM_MACHINE_MODES = MAX_MACHINE_MODE };
+struct real_value {
+};
+extern void vec_assert_fail (const char *, const char * ,const char *file_,unsigned line_,const char *function_) __attribute__ ((__noreturn__));
+typedef struct vec_prefix {
+  unsigned num;
+};
+enum rtx_code {
+  UNKNOWN , VALUE , DEBUG_EXPR , EXPR_LIST , INSN_LIST , SEQUENCE , ADDRESS , DEBUG_INSN , INSN , JUMP_INSN , CALL_INSN , BARRIER , CODE_LABEL , NOTE , COND_EXEC , PARALLEL , ASM_INPUT , ASM_OPERANDS , UNSPEC , UNSPEC_VOLATILE , ADDR_VEC , ADDR_DIFF_VEC , PREFETCH , SET , USE , CLOBBER , CALL , RETURN , EH_RETURN , TRAP_IF , CONST_INT , CONST_FIXED , CONST_DOUBLE , CONST_VECTOR , CONST_STRING , CONST , PC , REG , SCRATCH , SUBREG , STRICT_LOW_PART , CONCAT , CONCATN , MEM , LABEL_REF , SYMBOL_REF , CC0 , IF_THEN_ELSE , COMPARE , PLUS , MINUS , NEG , MULT , SS_MULT , US_MULT , DIV , SS_DIV , US_DIV , MOD , UDIV , UMOD , AND , IOR , XOR , NOT , ASHIFT , ROTATE , ASHIFTRT , LSHIFTRT , ROTATERT , SMIN , SMAX , UMIN , UMAX , PRE_DEC , PRE_INC , POST_DEC , POST_INC , PRE_MODIFY , POST_MODIFY , NE , EQ , GE , GT , LE , LT , GEU , GTU , LEU , LTU , UNORDERED , ORDERED , UNEQ , UNGE , UNGT , UNLE , UNLT , LTGT , SIGN_EXTEND , ZERO_EXTEND , TRUNCATE , FLOAT_EXTEND , FLOAT_TRUNCATE , FLOAT , FIX , UNSIGNED_FLOAT , UNSIGNED_FIX , FRACT_CONVERT , UNSIGNED_FRACT_CONVERT , SAT_FRACT , UNSIGNED_SAT_FRACT , ABS , SQRT , BSWAP , FFS , CLZ , CTZ , POPCOUNT , PARITY , SIGN_EXTRACT , ZERO_EXTRACT , HIGH , LO_SUM , VEC_MERGE , VEC_SELECT , VEC_CONCAT , VEC_DUPLICATE , SS_PLUS , US_PLUS , SS_MINUS , SS_NEG , US_NEG , SS_ABS , SS_ASHIFT , US_ASHIFT , US_MINUS , SS_TRUNCATE , US_TRUNCATE , FMA , VAR_LOCATION , DEBUG_IMPLICIT_PTR , ENTRY_VALUE , LAST_AND_UNUSED_RTX_CODE};
+enum rtx_class {
+  RTX_COMPARE, RTX_COMM_COMPARE, RTX_BIN_ARITH, RTX_COMM_ARITH, RTX_UNARY, RTX_EXTRA, RTX_MATCH, RTX_INSN, RTX_OBJ, RTX_CONST_OBJ, RTX_TERNARY, RTX_BITFIELD_OPS, RTX_AUTOINC };
+extern const enum rtx_class rtx_class[((int) LAST_AND_UNUSED_RTX_CODE)];
+union rtunion_def {
+  int rt_int;
+  unsigned int rt_uint;
+  rtx rt_rtx;
+};
+typedef union rtunion_def rtunion;
+struct rtx_def {
+  __extension__ enum rtx_code code: 16;
+  __extension__ enum machine_mode mode : 8;
+  unsigned int unchanging : 1;
+  union u {
+    rtunion fld[1];
+  }
+  u;
+};
+static __inline__ unsigned int rhs_regno (const_rtx x) {
+  return (((x)->u.fld[0]).rt_uint);
+}
+struct regstat_n_sets_and_refs_t {
+  int sets;
+};
+extern struct regstat_n_sets_and_refs_t *regstat_n_sets_and_refs;
+static __inline__ int REG_N_SETS (int regno) {
+  return regstat_n_sets_and_refs[regno].sets;
+}
+struct target_regs {
+  unsigned char x_hard_regno_nregs[334][MAX_MACHINE_MODE];
+};
+extern struct target_regs default_target_regs;
+static __inline__ unsigned int end_hard_regno (enum machine_mode mode, unsigned int regno) {
+  return regno + ((&default_target_regs)->x_hard_regno_nregs)[regno][(int) mode];
+}
+struct function {
+  struct eh_status *eh;
+  struct control_flow_graph *cfg;
+};
+extern struct function *cfun;
+typedef struct VEC_edge_gc {
+}
+VEC_edge_gc;
+struct basic_block_def {
+  VEC_edge_gc *preds;
+  struct basic_block_def *next_bb;
+  int index;
+}
+VEC_basic_block_gc;
+struct control_flow_graph {
+  basic_block x_entry_block_ptr;
+}
+bitmap_obstack;
+typedef struct bitmap_element_def {
+}
+bitmap_element;
+typedef struct bitmap_head_def {
+  bitmap_element *first;
+  bitmap_element *current;
+}
+bitmap_head;
+struct dataflow {
+  struct df_problem *problem;
+  void *block_info;
+  unsigned int block_info_size;
+};
+struct df_insn_info {
+  int luid;
+};
+struct df_d {
+  struct dataflow *problems_by_index[(7 + 1)];
+  struct df_insn_info **insns;
+};
+struct df_lr_bb_info {
+  bitmap_head def;
+  bitmap_head in;
+};
+extern struct df_d *df;
+static __inline__ struct df_lr_bb_info * df_lr_get_bb_info (unsigned int index) {
+  if (index < (df->problems_by_index[1])->block_info_size) return &((struct df_lr_bb_info *) (df->problems_by_index[1])->block_info)[index];
+  else return ((void *)0);
+}
+typedef struct reg_stat_struct {
+  int last_set_label;
+  unsigned long last_set_nonzero_bits;
+  char last_set_invalid;
+}
+reg_stat_type;
+typedef struct VEC_reg_stat_type_base {
+  struct vec_prefix prefix;
+  reg_stat_type vec[1];
+}
+VEC_reg_stat_type_base;
+static __inline__ reg_stat_type *VEC_reg_stat_type_base_index (VEC_reg_stat_type_base *vec_, unsigned ix_ ,const char *file_,unsigned line_,const char *function_) {
+  (void)((vec_ && ix_ < vec_->prefix.num) ? 0 : (vec_assert_fail ("index","VEC(reg_stat_type,base)" ,file_,line_,function_), 0));
+  return &vec_->vec[ix_];
+}
+typedef struct VEC_reg_stat_type_heap {
+  VEC_reg_stat_type_base base;
+}
+VEC_reg_stat_type_heap;
+static VEC_reg_stat_type_heap *reg_stat;
+static int mem_last_set;
+static int label_tick;
+int get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
+{
+  rtx x = *loc;
+  int i, j;
+  if ((((enum rtx_code) (x)->code) == REG))
+    {
+      unsigned int regno = (rhs_regno(x));
+      unsigned int endregno = (((((rhs_regno(x))) < 334)) ? end_hard_regno (((enum machine_mode) (x)->mode), (rhs_regno(x))) : (rhs_regno(x)) + 1);
+      for (j = regno;
+	   j < endregno;
+	   j++)
+	{
+	  reg_stat_type *rsp = (VEC_reg_stat_type_base_index(((reg_stat) ? &(reg_stat)->base : 0),j ,"/gcc/combine.c",12640,__FUNCTION__));
+	  if (
+	      rsp->last_set_invalid
+	      ||
+	      (
+	       (
+		regno >= 334
+		&& REG_N_SETS (regno) == 1
+		&& (!bitmap_bit_p ((&(df_lr_get_bb_info((((cfun + 0)->cfg->x_entry_block_ptr)->next_bb)->index))->in), regno) )
+	       )
+	       && rsp->last_set_label > tick
+	      )
+	     )
+	    {
+	      return replace;
+	    }
+	}
+    }
+  else if ((((enum rtx_code) (x)->code) == MEM)
+	   &&
+	   (
+	    (
+	     {
+	     __typeof ((x)) const _rtx = ((x));
+	     _rtx;
+	     }
+	    )->unchanging
+	   )
+	   &&
+	   (
+	    tick != label_tick
+	    || ((((df->insns[((((insn)->u.fld[0]).rt_int))]))->luid)) <= mem_last_set
+	   )
+	  )
+    {
+	{
+	  if (
+	      i == 1
+	     )
+	    {
+	      rtx x0 = (((x)->u.fld[0]).rt_rtx);
+	      rtx x1 = (((x)->u.fld[1]).rt_rtx);
+	      if ((((rtx_class[(int) (((enum rtx_code) (x1)->code))]) & (~1)) == (RTX_COMM_ARITH & (~1)))
+		  &&
+		  (
+		   x0 == (((x1)->u.fld[0]).rt_rtx)
+		  )
+		 )
+		return get_last_value_validate (&(((x1)->u.fld[x0 == (((x1)->u.fld[0]).rt_rtx) ? 1 : 0]).rt_rtx) , insn, tick, replace);
+	    }
+	}
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr52657.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr52657.c
new file mode 100644
index 000000000..8db588198
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr52657.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+typedef unsigned long int mp_limb_t;
+
+typedef struct
+{
+  int _mp_alloc;
+  int _mp_size;
+  mp_limb_t *_mp_d;
+} __mpz_struct;
+
+typedef __mpz_struct mpz_t[1];
+typedef mp_limb_t * mp_ptr;
+typedef const mp_limb_t * mp_srcptr;
+typedef long int mp_size_t;
+
+extern mp_limb_t __gmpn_addmul_2 (mp_ptr, mp_srcptr, mp_size_t, mp_srcptr);
+
+void
+__gmpn_redc_2 (mp_ptr rp, mp_ptr up, mp_srcptr mp, mp_size_t n, mp_srcptr mip)
+{
+  mp_limb_t q[2];
+  mp_size_t j;
+  mp_limb_t upn;
+
+  for (j = n - 2; j >= 0; j -= 2)
+    {
+      mp_limb_t _ph, _pl;
+      __asm__ ("xma.hu %0 = %3, %5, f0\n\t"
+               "xma.l %1 = %3, %5, f0\n\t"
+               ";;\n\t"
+               "xma.l %0 = %3, %4, %0\n\t"
+               ";;\n\t"
+               "xma.l %0 = %2, %5, %0"
+               : "=&f" (q[1]), "=&f" (q[0])
+               : "f" (mip[1]), "f" (mip[0]), "f" (up[1]), "f" (up[0]));
+      upn = up[n];
+      up[1] = __gmpn_addmul_2 (up, mp, n, q);
+      up[0] = up[n];
+      up[n] = upn;
+      up += 2;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr52731.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr52731.c
new file mode 100644
index 000000000..50ef1d78d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/pr52731.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target ia64-*-* } } */
+/* { dg-options "-O2" } */
+
+char* area;
+long int area_size;
+char* base;
+
+void fun(unsigned long int addr)
+{
+  unsigned long int size32 = (addr + 4096 - 1) & ~(4096 - 1);
+  unsigned long int size = size32 * sizeof(unsigned int);
+
+  if (size > 0) {
+    size = (size + 1) & ~(1);
+  }
+
+  area_size = size;
+  area = base + size;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-opt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-opt-1.c
new file mode 100644
index 000000000..6e8d1a2fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-opt-1.c
@@ -0,0 +1,12 @@
+/* PR target/38056.  Do not do sibcall optimization across object file
+   boundery when -mconstant-gp is not used.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "br.call.*bar" } } */
+
+int bar(int x);
+
+int foo(int x)
+{
+  return (bar(x + 1));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-opt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-opt-2.c
new file mode 100644
index 000000000..d802b792d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-opt-2.c
@@ -0,0 +1,12 @@
+/* PR target/38056.  Do sibcall optimization across object file
+   boundery when -mconstant-gp is used.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mconstant-gp" } */
+/* { dg-final { scan-assembler-not "br.call.*bar" } } */
+
+int bar(int x);
+
+int foo(int x)
+{
+  return (bar(x + 1));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-unwind-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-unwind-1.c
new file mode 100644
index 000000000..471179119
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-unwind-1.c
@@ -0,0 +1,10 @@
+/* PR 13158.  Emit ".restore sp" for a sibcall.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "\\.restore sp" 1 } } */
+
+static void do_date (char *);  
+void rfc822_date (char *date)  
+{  
+  do_date (date);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-unwind-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-unwind-2.c
new file mode 100644
index 000000000..0ae31ae5b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sibcall-unwind-2.c
@@ -0,0 +1,11 @@
+/* PR 18987.  This caused an assembler error because we emitted ".restore sp"
+   twice.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -w" } */
+/* { dg-final { scan-assembler-times "\\.restore sp" 1 } } */
+
+static void do_date (char *);  
+void rfc822_date (char *date)  
+{  
+  do_date (date);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/small-addr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/small-addr-1.c
new file mode 100644
index 000000000..846218623
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/small-addr-1.c
@@ -0,0 +1,23 @@
+/* PR target/21632 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct S
+{
+  void *s[256];
+};
+
+struct T
+{
+  long t[23];
+  struct S *u;
+};
+
+extern struct T __attribute__((model (small))) v;
+
+void *
+foo (void)
+{
+  return v.u->s[0];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/sync-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sync-1.c
new file mode 100644
index 000000000..2de04e57e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/sync-1.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "xchg4 .*, r0" } } */
+/* { dg-final { scan-assembler "cmpxchg4.*, r0, .*" } } */
+/* { dg-final { scan-assembler "cmpxchg8.*, r0, .*" { target lp64 } } } */
+
+int
+foo1 (int *p)
+{
+  return __sync_lock_test_and_set (p, 0);
+}
+
+int
+foo2 (int *p, int v)
+{
+  return __sync_bool_compare_and_swap (p, v, 0);
+}
+
+long
+foo3 (long *p, long v)
+{
+  return __sync_bool_compare_and_swap (p, v, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/types-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/types-1.c
new file mode 100644
index 000000000..ace49ebb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/types-1.c
@@ -0,0 +1,41 @@
+/* { dg-do compile { target ia64*-hp-hpux* } } */
+
+/* Test that __fpreg is distinct from any other builtin type.  */
+
+extern float fr1; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr1; /* { dg-error "" } */
+extern double fr2; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr2; /* { dg-error "" } */
+extern long double fr3; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr3; /* { dg-error "" } */
+extern __float80 fr4; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr4; /* { dg-error "" } */
+extern __float128 fr5; /* { dg-message "note: previous declaration of " } */
+extern __fpreg fr5; /* { dg-error "" } */
+
+/* Test that __float80 is distinct from any other builtin type.  */
+
+extern float f801; /* { dg-message "note: previous declaration of " } */
+extern __float80 f801; /* { dg-error "" } */
+extern double f802; /* { dg-message "note: previous declaration of " } */
+extern __float80 f802; /* { dg-error "" } */
+extern long double f803; /* { dg-message "note: previous declaration of " } */
+extern __float80 f803; /* { dg-error "" } */
+extern __fpreg f804;  /* { dg-message "note: previous declaration of " } */
+extern __float80 f804; /* { dg-error "" } */
+extern __float128 f805; /* { dg-message "note: previous declaration of " } */
+extern __float80 f805; /* { dg-error "" } */
+
+/* Test that __float128 is distinct from any other builtin type --
+   except "long double", for which it is a synonym.  */
+
+extern float f1281; /* { dg-message "note: previous declaration of " } */
+extern __float128 f1281; /* { dg-error "" } */
+extern double f1282; /* { dg-message "note: previous declaration of " } */
+extern __float128 f1282; /* { dg-error "" } */
+extern long double f1283;
+extern __float128 f1283;
+extern __fpreg f1284; /* { dg-message "note: previous declaration of " } */
+extern __float128 f1284; /* { dg-error "" } */
+extern __float80 f1285; /* { dg-message "note: previous declaration of " } */
+extern __float128 f1285; /* { dg-error "" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/types-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/types-2.c
new file mode 100644
index 000000000..30e4ddbf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/types-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run { target ia64*-hp-hpux* } } */
+/* { dg-options } */
+
+/* Test that the sizes and alignments of the extra floating-point
+   types are correct.  */
+
+int main () {
+  if (sizeof (__fpreg) != 16)
+    return 1;
+  if (__alignof__ (__fpreg) != 16)
+    return 2;
+
+  if (sizeof (__float80) != 16)
+    return 3;
+  if (__alignof__ (__float80) != 16)
+    return 4;
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/versionid-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/versionid-1.c
new file mode 100644
index 000000000..4ee8224a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/versionid-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target ia64-*-hpux* } } */
+
+extern int foo () __attribute__((version_id ("20040821")));
+
+int bar(int i)
+{
+	return (foo() + 1);
+}
+
+/* { dg-final { scan-assembler "alias.*foo.*foo\\\{20040821\\\}" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/versionid-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/versionid-2.c
new file mode 100644
index 000000000..258de0911
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/versionid-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target ia64-*-hpux* } } */
+
+extern int foo () __attribute__((version_id ("20040821")));
+
+int foo(int i)
+{
+	return (1);
+}
+
+/* { dg-final { scan-assembler "alias.*foo.*foo\\\{20040821\\\}" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/visibility-1.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/visibility-1.c
new file mode 100644
index 000000000..fdccab3c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/visibility-1.c
@@ -0,0 +1,38 @@
+/* Test visibility attribute.  */
+/* { dg-do compile { target ia64*-*-linux* } } */
+/* { dg-options "-O2 -fpic" } */
+/* { dg-final { scan-assembler "\\.hidden.*variable_j" } } */
+/* { dg-final { scan-assembler "\\.hidden.*variable_m" } } */
+/* { dg-final { scan-assembler "\\.protected.*baz" } } */
+/* { dg-final { scan-assembler "gprel.*variable_i" } } */
+/* { dg-final { scan-assembler "gprel.*variable_j" } } */
+/* { dg-final { scan-assembler "ltoff.*variable_k" } } */
+/* { dg-final { scan-assembler "gprel.*variable_l" } } */
+/* { dg-final { scan-assembler "gprel.*variable_m" } } */
+/* { dg-final { scan-assembler "ltoff.*variable_n" } } */
+
+static int variable_i;
+int variable_j __attribute__((visibility ("hidden")));
+int variable_k;
+struct A { char a[64]; };
+static struct A variable_l __attribute__((section (".sbss")));
+struct A variable_m __attribute__((visibility ("hidden"), section(".sbss")));
+struct A variable_n __attribute__((section (".sbss")));
+
+void foo (void)
+{
+  variable_i = 0;
+  variable_j = 0;
+  variable_k = 0;
+}
+
+void bar (void)
+{
+  variable_l.a[10] = 0;
+  variable_m.a[10] = 0;
+  variable_n.a[10] = 0;
+}
+
+void __attribute__((visibility ("protected"))) baz (void)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/ia64/visibility-2.c b/gcc-4.9/gcc/testsuite/gcc.target/ia64/visibility-2.c
new file mode 100644
index 000000000..895ef6d91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/ia64/visibility-2.c
@@ -0,0 +1,15 @@
+/* Test visibility attribute.  */
+/* { dg-do link { target ia64*-*-linux* } } */
+/* { dg-options "-O2 -fpic" } */
+
+int foo (int x);
+int bar (int x) __asm__ ("foo") __attribute__ ((visibility ("hidden")));
+int bar (int x)
+{
+  return x;
+}
+
+int main ()
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/20090709-1.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/20090709-1.c
new file mode 100644
index 000000000..fda05b756
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/20090709-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* There should be 3 occurrences of .LC0 in the code:
+   one for the definition of "0",
+   one for use in test1() and
+   one for use in test2().
+   FIXME: At the moment m68k GCC does not optimize test1() to nop
+   for some reason.  */
+/* { dg-final { scan-assembler-times ".LC0" 3 } } */
+
+void dummy(char *arg);
+
+void test1(void)
+{
+  char tmp[2] = "0";
+}
+
+void test2(void)
+{
+  dummy("0");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/20100512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/20100512-1.c
new file mode 100644
index 000000000..d07bb519a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/20100512-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fstack-protector" } */
+/* { dg-require-effective-target fstack_protector } */
+/* There should be 2 references to __stack_chk_guard in every function.  */
+/* { dg-final { scan-assembler-times "__stack_chk_guard" 4 } } */
+
+#include <stdlib.h>
+#include <string.h>
+void doTest1(void) {
+  volatile char foo[10];
+  memset((void *)foo, 1, 100);
+}
+void doTest2(void) {
+  volatile char foo[10];
+  memset((void *)foo, 1, 100);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/crash1.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/crash1.c
new file mode 100644
index 000000000..fdd737ab2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/crash1.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fomit-frame-pointer" } */
+
+/* Caused an ICE because of forgotten auto increment.  */
+
+register void *current __asm__("%a2");
+
+struct kernel_stat
+{
+ long long user;
+ long long nice;
+ long long system;
+ long long idle;
+ long long steal;
+ unsigned irqs[256];
+};
+extern struct kernel_stat per_cpu__kstat;
+
+void show_stat(void)
+{
+  int i;
+  long long user, nice, system, idle, steal;
+  long long sum = 0;
+
+  user = nice = system = idle = steal = 0;
+  for (i = 0; i < 1; i++)
+    {
+      int j;
+      user = user + per_cpu__kstat.user;
+      nice = nice + per_cpu__kstat.nice;
+      system = system + per_cpu__kstat.system;
+      idle = idle + per_cpu__kstat.idle;
+      steal = steal + per_cpu__kstat.steal;
+
+      for (j = 0 ; j < 256 ; j++)
+	sum += per_cpu__kstat.irqs[j];
+    }
+  seq_printf(user, nice, system, idle, steal);
+  seq_printf(sum);
+  for (i = 0; i < 256; i++)
+    seq_printf (i);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt-1.c
new file mode 100644
index 000000000..443c13b46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "j(ra|mp)\[ \t\]*interrupt_sibcall" } } */
+/* { dg-final { scan-assembler "j(b|)sr\[ \t\]*interrupt_call" } } */
+/* { dg-final { scan-assembler "j(ra|mp)\[ \t\]*normal_sibcall" } } */
+
+void normal_sibcall (void);
+void interrupt_call (void);
+void __attribute ((interrupt)) interrupt_sibcall (void);
+
+void normal (void)
+{
+  normal_sibcall ();
+}
+
+void __attribute ((interrupt)) interrupt (void)
+{
+  interrupt_call ();
+}
+
+void __attribute ((interrupt)) interrupt_2 (void)
+{
+  interrupt_sibcall ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt-2.c
new file mode 100644
index 000000000..7d4cb68c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+int x;
+volatile unsigned int y;
+
+#define REPEAT10(X, Y)					\
+  X(Y##0); X(Y##1); X(Y##2); X(Y##3); X(Y##4);		\
+  X(Y##5); X(Y##6); X(Y##7); X(Y##8); X(Y##9)
+
+#define REPEAT30(X) REPEAT10 (X, 0); REPEAT10 (X, 1); REPEAT10 (X, 2)
+#define IN(X) unsigned int x##X = y
+#define OUT(X) y = x##X
+
+void __attribute__ ((interrupt_handler)) f1 (void)
+{
+  x = y + 11;
+}
+
+void __attribute__ ((interrupt_handler)) f2 (void)
+{
+  REPEAT30 (IN);
+  REPEAT30 (OUT);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-1.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-1.c
new file mode 100644
index 000000000..ee7179cd4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=fidoa -O2 -fomit-frame-pointer" } */
+
+/* Check that interrupt_thread attribute works.  */
+
+#ifdef __mfido__
+extern void foo (void) __attribute__ ((interrupt_thread));
+
+int a, b, c, d;
+
+void bar (void);
+
+void
+foo (void)
+{
+  int w, x, y, z;
+
+  w = a;
+  x = b;
+  y = c;
+  z = d;
+
+  bar ();
+
+  a = w;
+  b = x;
+  c = y;
+  d = z;
+}
+#else
+/* If the current mutilib is, say, -mcpu=5485, the compiler gets
+   -mcpu=fidoa -mcpu=5485, where -mcpu=fidoa is overridden.  In that
+   case, we just print out "sleep" in the assembly file and pretend
+   that everything is all right.  */
+asm ("sleep");
+#endif
+
+/* "sleep" should be generated in place of "rts".  */
+/* { dg-final { scan-assembler-times "sleep" 1 } } */
+/* { dg-final { scan-assembler-times "rts" 0 } } */
+
+/* There should be no stack adjustment.  */
+/* { dg-final { scan-assembler-times "sp" 0 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-2.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-2.c
new file mode 100644
index 000000000..1518bece5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=fidoa" } */
+
+/* Check that an error is issued for using more than one
+   interrupt_attribute at the same time.  */
+
+/* If the current mutilib is, say, -mcpu=5485, the compiler gets
+   -mcpu=fidoa -mcpu=5485, where -mcpu=fidoa is overridden.  In that
+   case, we just use two interrupt_handler attributes and expect the
+   same error.  */
+#ifdef __mfido___
+#define IH interrupt_thread
+#else
+#define IH interrupt_handler
+#endif
+
+extern void f1 (void) __attribute__((interrupt_handler, interrupt_handler)); /* { dg-error "multiple interrupt attributes not allowed" } */
+
+extern void f2 (void) __attribute__((interrupt_handler, IH)); /* { dg-error "multiple interrupt attributes not allowed" } */
+
+extern void f3 (void) __attribute__((IH, interrupt_handler)); /* { dg-error "multiple interrupt attributes not allowed" } */
+
+extern void f4 (void) __attribute__((IH, IH)); /* { dg-error "multiple interrupt attributes not allowed" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-3.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-3.c
new file mode 100644
index 000000000..be83edb5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/interrupt_thread-3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=cpu32" } */
+
+/* Check that interrupt_thread is rejected on CPUs other than
+   fido.  */
+
+extern void foo (void) __attribute__((interrupt_thread)); /* { dg-error "interrupt_thread is available only on fido" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/m68k.exp b/gcc-4.9/gcc/testsuite/gcc.target/m68k/m68k.exp
new file mode 100644
index 000000000..a917898ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/m68k.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an m68k target.
+if { ![istarget m68k*-*-*] && ![istarget fido*-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/pic-1.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pic-1.c
new file mode 100644
index 000000000..b8d3fe81a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pic-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target m68k-*-* fido-*-* } }  */
+/* { dg-options "-O2 -fpic" }  */
+
+extern void Foo (void *);
+
+char *ary[] = {"a", "b", "c", "d", "e"};
+
+void Bar (void)
+{
+  int cnt = 0;
+
+  for (cnt = 0; cnt < 4;  ++cnt)
+    {
+      char *ptr = ary[cnt];
+
+      Foo (&ptr);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr35018.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr35018.c
new file mode 100644
index 000000000..fadea8620
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr35018.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -mcpu=5249" } */
+
+static inline void vect_add(int *x, int *y, int n)
+{
+    asm volatile ("nop;"
+                : [n] "+d" (n), [x] "+a" (x), [y] "+a" (y)
+                : : "%d0", "%d1", "%d2", "%d3", "%a0", "%a1", "%a2", "%a3",
+                    "cc", "memory");
+}
+
+extern void vect_copy (int *, int *, int);
+
+void vorbis_synthesis_blockin(int *blocksizes)
+{
+    int j, *pcm, *p;
+
+    int n=blocksizes[*p]/2;
+    int n0=blocksizes[0]/2;
+    int n1=blocksizes[1]/2;
+
+    for(j=0;j<*p;j++)
+    {
+        vect_add(p, pcm, n1);
+        vect_add(pcm, p, n0);
+        vect_add(p, pcm, n0);
+        vect_add(p, pcm, n0);
+        vect_copy(pcm, p, n);
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr36133.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr36133.c
new file mode 100644
index 000000000..25237a860
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr36133.c
@@ -0,0 +1,16 @@
+/* pr36133.c
+
+   This test ensures that conditional branches can use the condition codes
+   written by shift instructions, without the need for an extra TST.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O2" }  */
+/* { dg-final { scan-assembler-not "tst" } } */
+
+void
+f (unsigned int a)
+{
+  if (a >> 4)
+    asm volatile ("nop");
+  asm volatile ("nop");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr36134.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr36134.c
new file mode 100644
index 000000000..c91956b5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr36134.c
@@ -0,0 +1,28 @@
+/* pr36134.c
+
+   This test ensures that the shorter LEA instruction is used in preference
+   to the longer ADD instruction.
+
+   This preference is applicable to ColdFire only.  On CPU32, we can
+   use a sequence of two ADDQ instructions, which is faster than the
+   LEA instruction.  */
+
+/* { dg-do compile }  */
+/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "-mcpu=5208" } } */
+/* { dg-options "-O2 -mcpu=5208" }  */
+/* { dg-final { scan-assembler "lea" } } */
+/* { dg-final { scan-assembler-not "add" } } */
+
+int *a, *b;
+
+void
+f ()
+{
+  while (a > b)
+    {
+      *a++ = *b++;
+      *a++ = *b++;
+      *a++ = *b++;
+      *a++ = *b++;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr41302.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr41302.c
new file mode 100644
index 000000000..c3679923e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr41302.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "move.l \%d0,\%a0" { target *-*-*linux* } } } */
+
+struct pts {
+  int c;
+};
+
+unsigned int bar (struct pts *a, int b);
+
+struct pts * foo (struct pts *a, int b)
+{
+  return (struct pts *) bar (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr45015.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr45015.c
new file mode 100644
index 000000000..fba9550e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr45015.c
@@ -0,0 +1,26 @@
+/* PR debug/45015 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -g" } */
+
+unsigned int
+foo (unsigned int *x, const unsigned int *y, int z, unsigned int w)
+{
+  unsigned int a, b, c, s;
+  int j;
+  j = -z;
+  x -= j;
+  y -= j;
+  a = 0;
+  do
+    {
+      __asm__ ("move.l %2, %0; move.l %3, %1" : "=d" (b), "=d" (c) : "g<>" (y[j]), "d" (w));
+      c += a;
+      a = (c < a) + b;
+      s = x[j];
+      c = s + c;
+      a += (c < s);
+      x[j] = c;
+    }
+  while (++j != 0);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr52573.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr52573.c
new file mode 100644
index 000000000..df4119b0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr52573.c
@@ -0,0 +1,157 @@
+
+/* { dg-options "-w -O3 -funroll-loops" } */
+/* { dg-final { scan-assembler-not "%d0:%d0" } } */
+/* { dg-final { scan-assembler-not "%d1:%d1" } } */
+/* { dg-final { scan-assembler-not "%d2:%d2" } } */
+/* { dg-final { scan-assembler-not "%d3:%d3" } } */
+/* { dg-final { scan-assembler-not "%d4:%d4" } } */
+/* { dg-final { scan-assembler-not "%d5:%d5" } } */
+/* { dg-final { scan-assembler-not "%d6:%d6" } } */
+/* { dg-final { scan-assembler-not "%d7:%d7" } } */
+/* Test arithmetics on bitfields.  */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned int
+myrnd (void)
+{
+  static unsigned int s = 1388815473;
+  s *= 1103515245;
+  s += 12345;
+  return (s / 65536) % 2048;
+}
+
+#define T(S)					\
+struct S s##S;					\
+struct S retme##S (struct S x)			\
+{						\
+  return x;					\
+}						\
+						\
+unsigned int fn1##S (unsigned int x)		\
+{						\
+  struct S y = s##S;				\
+  y.k += x;					\
+  y = retme##S (y);				\
+  return y.k;					\
+}						\
+						\
+unsigned int fn2##S (unsigned int x)		\
+{						\
+  struct S y = s##S;				\
+  y.k += x;					\
+  y.k %= 15;					\
+  return y.k;					\
+}						\
+						\
+unsigned int retit##S (void)			\
+{						\
+  return s##S.k;				\
+}						\
+						\
+unsigned int fn3##S (unsigned int x)		\
+{						\
+  s##S.k += x;					\
+  return retit##S ();				\
+}						\
+						\
+void test##S (void)				\
+{						\
+  int i;					\
+  unsigned int mask, v, a, r;			\
+  struct S x;					\
+  char *p = (char *) &s##S;			\
+  for (i = 0; i < sizeof (s##S); ++i)		\
+    *p++ = myrnd ();				\
+  if (__builtin_classify_type (s##S.l) == 8)	\
+    s##S.l = 5.25;				\
+  s##S.k = -1;					\
+  mask = s##S.k;				\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn1##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || x.k != s##S.k || x.l != s##S.l		\
+      || ((v + a) & mask) != r)			\
+    abort ();					\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn2##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || x.k != s##S.k || x.l != s##S.l		\
+      || ((((v + a) & mask) % 15) & mask) != r)	\
+    abort ();					\
+  v = myrnd ();					\
+  a = myrnd ();					\
+  s##S.k = v;					\
+  x = s##S;					\
+  r = fn3##S (a);				\
+  if (x.i != s##S.i || x.j != s##S.j		\
+      || s##S.k != r || x.l != s##S.l		\
+      || ((v + a) & mask) != r)			\
+    abort ();					\
+}
+
+struct A { unsigned int i : 6, l : 1, j : 10, k : 15; }; T(A)
+struct B { unsigned int i : 6, j : 11, k : 15; unsigned int l; }; T(B)
+struct C { unsigned int l; unsigned int i : 6, j : 11, k : 15; }; T(C)
+struct D { unsigned long long l : 6, i : 6, j : 23, k : 29; }; T(D)
+struct E { unsigned long long l, i : 12, j : 23, k : 29; }; T(E)
+struct F { unsigned long long i : 12, j : 23, k : 29, l; }; T(F)
+struct G { unsigned int i : 12, j : 13, k : 7; unsigned long long l; }; T(G)
+struct H { unsigned int i : 12, j : 11, k : 9; unsigned long long l; }; T(H)
+struct I { unsigned short i : 1, j : 6, k : 9; unsigned long long l; }; T(I)
+struct J { unsigned short i : 1, j : 8, k : 7; unsigned short l; }; T(J)
+struct K { unsigned int k : 6, l : 1, j : 10, i : 15; }; T(K)
+struct L { unsigned int k : 6, j : 11, i : 15; unsigned int l; }; T(L)
+struct M { unsigned int l; unsigned int k : 6, j : 11, i : 15; }; T(M)
+struct N { unsigned long long l : 6, k : 6, j : 23, i : 29; }; T(N)
+struct O { unsigned long long l, k : 12, j : 23, i : 29; }; T(O)
+struct P { unsigned long long k : 12, j : 23, i : 29, l; }; T(P)
+struct Q { unsigned int k : 12, j : 13, i : 7; unsigned long long l; }; T(Q)
+struct R { unsigned int k : 12, j : 11, i : 9; unsigned long long l; }; T(R)
+struct S { unsigned short k : 1, j : 6, i : 9; unsigned long long l; }; T(S)
+struct T { unsigned short k : 1, j : 8, i : 7; unsigned short l; }; T(T)
+struct U { unsigned short j : 6, k : 1, i : 9; unsigned long long l; }; T(U)
+struct V { unsigned short j : 8, k : 1, i : 7; unsigned short l; }; T(V)
+struct W { long double l; unsigned int k : 12, j : 13, i : 7; }; T(W)
+struct X { unsigned int k : 12, j : 13, i : 7; long double l; }; T(X)
+struct Y { unsigned int k : 12, j : 11, i : 9; long double l; }; T(Y)
+struct Z { long double l; unsigned int j : 13, i : 7, k : 12; }; T(Z)
+
+int
+main (void)
+{
+  testA ();
+  testB ();
+  testC ();
+  testD ();
+  testE ();
+  testF ();
+  testG ();
+  testH ();
+  testI ();
+  testJ ();
+  testK ();
+  testL ();
+  testM ();
+  testN ();
+  testO ();
+  testP ();
+  testQ ();
+  testR ();
+  testS ();
+  testT ();
+  testU ();
+  testV ();
+  testW ();
+  testX ();
+  testY ();
+  testZ ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr54041.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr54041.c
new file mode 100644
index 000000000..645cb6d23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/pr54041.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mshort" } */
+
+extern int r[];
+
+int *fn(int i)
+{
+	return &r[i];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/slp-ice.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/slp-ice.c
new file mode 100644
index 000000000..61c7f9df3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/slp-ice.c
@@ -0,0 +1,15 @@
+/* From PR 7872, test for optabs segfault when strict low part is present.  */
+/* { dg-do compile { target m68k-*-* } }  */
+/* { dg-options "-O0" }  */
+extern void (**table)(void);
+
+typedef unsigned short uw16;
+typedef unsigned int gshort;
+
+register uw16 *pc asm("%a4");
+register gshort code asm("%d6");
+
+void QMExecuteLoop(uw16 *oldPC)
+{
+  table[code=(*(uw16*)(pc++))]();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/stack-limit-1.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/stack-limit-1.c
new file mode 100644
index 000000000..b1e9b99b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/stack-limit-1.c
@@ -0,0 +1,6 @@
+/* -fstack-limit- should be ignored without an ICE if not supported.  */
+/* { dg-do compile } */
+/* { dg-options "-fstack-limit-symbol=_stack_limit -m68000" } */
+/* { dg-warning "not supported" "" { target *-*-* } 1 } */
+
+void dummy (void) { }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c
new file mode 100644
index 000000000..2a4900b5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2 -fpic -mxgot" } */
+/* { dg-final { scan-assembler "#foo@TLSGD,\%\[ad\]\[0-7\]" } } */
+/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
+
+extern int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-gd.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-gd.c
new file mode 100644
index 000000000..2b69fbdc1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-gd.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2 -fpic" } */
+/* { dg-final { scan-assembler "foo@TLSGD\\(\%a5\\)" } } */
+/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
+
+extern int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c
new file mode 100644
index 000000000..d3fbfdaa4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2 -mxgot" } */
+/* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */
+/* { dg-final { scan-assembler "#foo@TLSIE,\%\[ad\]\[0-7\]" } } */
+
+extern int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ie.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ie.c
new file mode 100644
index 000000000..2661f9fc0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ie.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */
+/* { dg-final { scan-assembler "foo@TLSIE\\(\%a5\\)" } } */
+
+extern int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c
new file mode 100644
index 000000000..4817de01d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2 -fpic -mxgot -mxtls" } */
+/* { dg-final { scan-assembler "#foo@TLSLDM,\%\[ad\]\[0-7\]" } } */
+/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
+/* { dg-final { scan-assembler "#foo@TLSLDO,\%\[ad\]\[0-7\]" } } */
+
+static int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c
new file mode 100644
index 000000000..f95f71928
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2 -fpic -mxgot" } */
+/* { dg-final { scan-assembler "#foo@TLSLDM,\%\[ad\]\[0-7\]" } } */
+/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
+/* { dg-final { scan-assembler "lea \\(foo@TLSLDO,\%a0\\)" } } */
+
+static int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c
new file mode 100644
index 000000000..1bc3eaf7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2 -fpic -mxtls" } */
+/* { dg-final { scan-assembler "foo@TLSLDM\\(\%a5\\)" } } */
+/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
+/* { dg-final { scan-assembler "#foo@TLSLDO,\%\[ad\]\[0-7\]" } } */
+
+static int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld.c
new file mode 100644
index 000000000..556a11718
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-ld.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2 -fpic" } */
+/* { dg-final { scan-assembler "foo@TLSLDM\\(\%a5\\)" } } */
+/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
+/* { dg-final { scan-assembler "lea \\(foo@TLSLDO,\%a0\\)" } } */
+
+static int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-le-xtls.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-le-xtls.c
new file mode 100644
index 000000000..90061153f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-le-xtls.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2 -mxtls" } */
+/* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */
+/* { dg-final { scan-assembler "#foo@TLSLE,\%\[ad\]\[0-7\]" } } */
+
+static int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-le.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-le.c
new file mode 100644
index 000000000..1c0eab238
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/tls-le.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */
+/* { dg-final { scan-assembler "lea \\(foo@TLSLE,\%a0\\)" } } */
+
+static int __thread foo;
+
+int *
+bar (void)
+{
+  return &foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/m68k/xgot-1.c b/gcc-4.9/gcc/testsuite/gcc.target/m68k/xgot-1.c
new file mode 100644
index 000000000..6794241a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/m68k/xgot-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fpic -mxgot -mcpu=5206" } */
+/* { dg-final { scan-assembler "foo@GOT,\%\[ad\]\[0-7\]" } } */
+
+extern int foo;
+
+int
+bar (void)
+{
+  return foo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/bshift.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/bshift.c
new file mode 100644
index 000000000..64cf1e2e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/bshift.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler-not "mul\tr" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler-not "muli" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/div.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/div.c
new file mode 100644
index 000000000..25ee42ce5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/div.c
@@ -0,0 +1,52 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-div" } */
+
+volatile int m1, m2, m3;
+volatile long l1, l2;
+volatile long long llp;
+volatile unsigned int u1, u2, u3;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler-not "mul\tr" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler-not "muli" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
new file mode 100644
index 000000000..4041a2413
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    if (f2 <= f3) 
+        print ("le");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
new file mode 100644
index 000000000..3902b839d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    if (f2 < f3) 
+        print ("lt");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
new file mode 100644
index 000000000..8555974dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    if (f2 == f3) 
+        print ("eq");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
new file mode 100644
index 000000000..79cc5f9dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
@@ -0,0 +1,9 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+void float_func(float f1, float f2, float f3)
+{
+  /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+  /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    if(f1==f2 && f1<=f3)
+        print ("f1 eq f2 && f1 le f3");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c
new file mode 100644
index 000000000..ee057c1b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fcvt.c
@@ -0,0 +1,21 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float -mxl-float-convert" } */
+
+int float_func (float f) 
+{
+  /* { dg-final { scan-assembler "flt\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+   return f;
+}
+
+
+float int_func (int i) 
+{
+  /* { dg-final { scan-assembler "fint\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+   return i;
+}
+
+
+float uint_func (unsigned int i) 
+{
+  /* { dg-final { scan-assembler "fint\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+   return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/float.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/float.c
new file mode 100644
index 000000000..f5ef3186c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/float.c
@@ -0,0 +1,18 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler "fmul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    f1 = f2 * f3;
+
+  /* { dg-final { scan-assembler "fadd\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    f1 = f2 + f3;
+
+  /* { dg-final { scan-assembler "frsub\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    f1 = f2 - f3;
+
+  /* { dg-final { scan-assembler "fdiv\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    f1 = f2 / f3;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c
new file mode 100644
index 000000000..4c2466e4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/fsqrt.c
@@ -0,0 +1,10 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float -mxl-float-sqrt" } */
+#include <math.h>
+
+float sqrt_func (float f) 
+{
+  /* { dg-final { scan-assembler "fsqrt\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    return sqrtf (f);
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c
new file mode 100644
index 000000000..ce186314e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift-pcmp.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler "pcmpne\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler "pcmpeq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c
new file mode 100644
index 000000000..76d174ec7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul-bshift.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul.c
new file mode 100644
index 000000000..d2a6bec61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mul.c
@@ -0,0 +1,52 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-mul" } */
+
+volatile int m1, m2, m3;
+volatile long l1, l2;
+volatile long long llp;
+volatile unsigned int u1, u2, u3;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c
new file mode 100644
index 000000000..a15983af1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mulh-bshift-pcmp.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare -mxl-multiply-high" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler "mulh\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    llp = (long long)l1 * l2;
+
+  /* { dg-final { scan-assembler "mulhu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    ullp = (unsigned long long)ul1 * ul2;
+
+  /* { dg-final { scan-assembler "mulhsu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    llp = (long long)l1 * ul2;        
+
+  /* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler "pcmpne\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler "pcmpeq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mulh.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mulh.c
new file mode 100644
index 000000000..6e0cc3ac4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/mulh.c
@@ -0,0 +1,53 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-mul -mxl-multiply-high" } */
+
+volatile int m1, m2, m3;
+volatile unsigned int u1, u2, u3;
+volatile long l1, l2;
+volatile long long llp;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler "mulh\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler "mulhu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler "mulhsu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
new file mode 100644
index 000000000..ebfb170ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
@@ -0,0 +1,21 @@
+/* { dg-options "-O3 -mcpu=v6.00.a " } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+    /* { dg-final { scan-assembler-not "fcmp" } } */
+    if (f2 <= f3) 
+        print ("le");
+    else if (f2 == f3) 
+        print ("eq");
+    else if (f2 < f3) 
+        print ("lt");
+    else if (f2 > f3) 
+        print ("gt");
+    else if (f2 >= f3) 
+        print ("ge");
+    else if (f2 != f3) 
+        print ("ne");
+    
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c
new file mode 100644
index 000000000..647da3cfe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/nofloat.c
@@ -0,0 +1,19 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -msoft-float" } */
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler-not "fmul" } } */
+    f1 = f2 * f3;
+
+  /* { dg-final { scan-assembler-not "fadd" } } */
+    f1 = f2 + f3;
+
+  /* { dg-final { scan-assembler-not "frsub" } } */
+    f1 = f2 - f3;
+
+  /* { dg-final { scan-assembler-not "fdiv" } } */
+    f1 = f2 / f3;
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c
new file mode 100644
index 000000000..aea795721
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/pcmp.c
@@ -0,0 +1,52 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mxl-pattern-compare" } */
+
+volatile int m1, m2, m3;
+volatile long l1, l2;
+volatile long long llp;
+volatile unsigned int u1, u2, u3;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler-not "mul\tr" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler-not "muli" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler "pcmpeq" } } */
+    return (m1 == m2);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
new file mode 100644
index 000000000..1d6ba807b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
@@ -0,0 +1,89 @@
+/* { dg-options "-O3 -mcpu=v6.00.a -mcpu=v6.00.a" } */
+
+volatile int m1, m2, m3;
+volatile long l1, l2;
+volatile long long llp;
+volatile unsigned int u1, u2, u3;
+
+volatile unsigned long ul1, ul2;
+volatile unsigned long long ullp;
+
+int test_mul () {
+
+  /* { dg-final { scan-assembler-not "mul\tr" } } */
+    m1 = m2 * m3 ;
+
+  /* { dg-final { scan-assembler-not "muli" } } */
+    m3 = m1 * 1234 ;    
+
+  /* { dg-final { scan-assembler-not "mulh" } } */
+    llp = ((long long)l1 * l2);
+
+  /* { dg-final { scan-assembler-not "mulhu" } } */
+    ullp = ((unsigned long long)ul1 * ul2);
+
+  /* { dg-final { scan-assembler-not "mulhsu" } } */
+    llp = ((long long)l1 * ul2);        
+
+  /* { dg-final { scan-assembler-not "bslli" } } */
+    m3 = m2 << 25;
+
+  /* { dg-final { scan-assembler-not "bsll" } } */
+    m2 = m1 << m3;
+
+  /* { dg-final { scan-assembler-not "bsrai" } } */
+    m3 = m2 >> 25;
+
+  /* { dg-final { scan-assembler-not "bsra" } } */
+    m2 = m1 >> m3;
+
+  /* { dg-final { scan-assembler-not "idiv" } } */
+    m1 = m2 / m1;
+
+  /* { dg-final { scan-assembler-not "idivu" } } */
+    u1 = u2 / u3;    
+
+  /* { dg-final { scan-assembler-not "pcmpne" } } */
+    m3 = (m3 != m1);
+
+  /* { dg-final { scan-assembler-not "pcmpeq" } } */
+    return (m1 == m2);
+}
+
+
+
+volatile float f1, f2, f3;
+
+void float_func () 
+{
+  /* { dg-final { scan-assembler-not "fmul" } } */
+    f1 = f2 * f3;
+
+  /* { dg-final { scan-assembler-not "fadd" } } */
+    f1 = f2 + f3;
+
+  /* { dg-final { scan-assembler-not "frsub" } } */
+    f1 = f2 - f3;
+
+  /* { dg-final { scan-assembler-not "fdiv" } } */
+    f1 = f2 / f3;
+
+}
+
+void float_cmp_func () 
+{
+    /* { dg-final { scan-assembler-not "fcmp" } } */
+    if (f2 <= f3) 
+        print ("le");
+    else if (f2 == f3) 
+        print ("eq");
+    else if (f2 < f3) 
+        print ("lt");
+    else if (f2 > f3) 
+        print ("gt");
+    else if (f2 >= f3) 
+        print ("ge");
+    else if (f2 != f3) 
+        print ("ne");
+    
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/microblaze.exp b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/microblaze.exp
new file mode 100644
index 000000000..f34318141
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/microblaze.exp
@@ -0,0 +1,56 @@
+#   Copyright (C) 2009-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+
+# MicroBlaze test driver that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a MicroBlaze target.
+if { ![istarget microblaze*-*-*] } then {
+  return
+}
+
+global TORTURE_OPTIONS
+set TORTURE_OPTIONS [list \
+                         { -O0 } \
+                         { -O1 } \
+                         { -O2 } \
+                         { -O3 } \
+                         { -Os } ]
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+set default_c_flags "" 
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/isa/*.\[cSi\]]] \
+${default_c_flags} ""
+
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/others/*.\[cSi\]]] \
+    "-mcpu=v6.00.a" 
+
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
new file mode 100644
index 000000000..fdcde1fa7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+
+void trap ()
+{
+  __builtin_trap ();
+}
+
+/* { dg-final { scan-assembler "brki\tr0,-1" } } */
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var1.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var1.c
new file mode 100644
index 000000000..15b85ca77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var1.c
@@ -0,0 +1,8 @@
+/* { dg-final { scan-assembler "\.bss*" } } */
+int global;
+
+int testfunc ()
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
+    return global;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var2.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var2.c
new file mode 100644
index 000000000..9fb7347ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var2.c
@@ -0,0 +1,8 @@
+/* { dg-final { scan-assembler "\.data*" } } */
+int global = 10;
+
+int testfunc ()
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
+    return global;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var3.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var3.c
new file mode 100644
index 000000000..2b3f06410
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/data_var3.c
@@ -0,0 +1,7 @@
+/* { dg-final { scan-assembler "\.rodata*" } } */
+const int global = 10;
+
+int testfunc ()
+{
+    return global;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/interrupt_handler_leaf.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/interrupt_handler_leaf.c
new file mode 100644
index 000000000..9d068d05e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/interrupt_handler_leaf.c
@@ -0,0 +1,10 @@
+int leaf_func () __attribute__ ((interrupt_handler));
+volatile int intr_occurred;
+
+int leaf_func ()
+{
+
+  /* { dg-final { scan-assembler "rtid\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),0" } } */
+  /* { dg-final { scan-assembler-not "rtsd" } } */    
+    intr_occurred += 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c
new file mode 100644
index 000000000..e285fb821
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c
@@ -0,0 +1,74 @@
+/* { dg-options "-O2 -fPIC" } */
+
+typedef struct test_struct
+{
+    unsigned long long h[8];
+    unsigned long long Nl,Nh;
+    union {
+        unsigned long long d[16];
+        unsigned char p[(16*8)];
+    } u;
+    unsigned int num,md_len;
+} TEST_STRUCT;
+
+static const unsigned long long K512[12] = {
+    0x428a2f98d728ae22,0x7137449123ef65cd,
+    0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc,
+    0x3956c25bf348b538,0x59f111f1b605d019,
+    0x923f82a4af194f9b,0xab1c5ed5da6d8118,
+    0xd807aa98a3030242,0x12835b0145706fbe,
+    0x243185be4ee4b28c,0x550c7dc3d5ffb4e2};
+
+#define ROTR(x,s)   (((x)>>s) | (x)<<(64-s))
+#define Sigma0(x)   (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
+#define Sigma1(x)   (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
+#define Ch(x,y,z)   (((x) & (y)) ^ ((~(x)) & (z)))
+#define Maj(x,y,z)  (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
+
+#define ROUND_00_15(i,a,b,c,d,e,f,g,h)  do {    \
+    T1 += h + Sigma1(e) + Ch(e,f,g) + K512[i];  \
+    h = Sigma0(a) + Maj(a,b,c);         \
+    d += T1;    h += T1;        } while (0)
+
+#define ROUND_16_80(i,a,b,c,d,e,f,g,h,X)    do {    \
+    T1 = X[(i)&0x0f] += s0 + s1 + X[(i+9)&0x0f];    \
+    ROUND_00_15(i,a,b,c,d,e,f,g,h);     } while (0)
+
+static void testfunc1 (TEST_STRUCT *ctx, const void *in, unsigned int num)
+{
+    const unsigned long long *W=in;
+    unsigned long long  a,b,c,d,e,f,g,h,s0,s1,T1;
+    unsigned long long  X[16];
+    int i;
+
+    while (num--) {
+
+        T1 = X[0] = W[0];   ROUND_00_15(0,a,b,c,d,e,f,g,h);
+        T1 = X[1] = W[1];   ROUND_00_15(1,h,a,b,c,d,e,f,g);
+        T1 = X[2] = W[2];   ROUND_00_15(2,g,h,a,b,c,d,e,f);
+        T1 = X[3] = W[3];   ROUND_00_15(3,f,g,h,a,b,c,d,e);
+        T1 = X[4] = W[4];   ROUND_00_15(4,e,f,g,h,a,b,c,d);
+        T1 = X[5] = W[5];   ROUND_00_15(5,d,e,f,g,h,a,b,c);
+        T1 = X[6] = W[6];   ROUND_00_15(6,c,d,e,f,g,h,a,b);
+        T1 = X[7] = W[7];   ROUND_00_15(7,b,c,d,e,f,g,h,a);
+        T1 = X[8] = W[8];   ROUND_00_15(8,a,b,c,d,e,f,g,h);
+        T1 = X[9] = W[9];   ROUND_00_15(9,h,a,b,c,d,e,f,g);
+
+        for (i=16;i<80;i+=8)
+        {
+            ROUND_16_80(i+0,a,b,c,d,e,f,g,h,X);
+        }
+
+        ctx->h[4] += e; ctx->h[5] += f; ctx->h[6] += g; ctx->h[7] += h;
+    }
+}
+
+int testfunc2 (TEST_STRUCT *c, const void *_data, unsigned int len)
+{
+    const unsigned char *data=(const unsigned char *)_data;
+
+    unsigned char *p=(unsigned char *)c->u.p;
+
+    testfunc1 (c,p,0);
+    testfunc1 (c,data,len/sizeof(c->u));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var1.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var1.c
new file mode 100644
index 000000000..2337f5a1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var1.c
@@ -0,0 +1,15 @@
+/* { dg-options "-mxl-gp-opt" } */
+
+/* { dg-final { scan-assembler "\.sbss\[^2]+" } } */
+typedef int Boolean;
+volatile Boolean global = 0;
+int testfunc ()
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
+    return global;
+}
+
+int main ()
+{
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var2.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var2.c
new file mode 100644
index 000000000..1c91d0043
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var2.c
@@ -0,0 +1,10 @@
+/* { dg-options "-mxl-gp-opt" } */
+
+/* { dg-final { scan-assembler "\.sdata\[^2]+" } } */
+int global = 10;
+
+int testfunc ()
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
+    return global;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var3.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var3.c
new file mode 100644
index 000000000..07c80041c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var3.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mxl-gp-opt" } */
+
+extern int a;
+
+/* { dg-final { scan-assembler "\.sdata2" } } */
+const int global1 = 10;
+extern const int global2;
+
+int testfunc ()
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r2" } } */
+    return global2 + global1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var4.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var4.c
new file mode 100644
index 000000000..4dfa337d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var4.c
@@ -0,0 +1,15 @@
+/* { dg-options "-mxl-gp-opt -G 16" } */
+
+/* { dg-final { scan-assembler "\.sbss\[^2]+" } } */
+struct test_s {
+    int a;
+    int b;
+    int c;
+    int d;
+} global; 
+
+int testfunc ()
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
+    return global.a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var5.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var5.c
new file mode 100644
index 000000000..5c61962bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var5.c
@@ -0,0 +1,15 @@
+/* { dg-options "-mxl-gp-opt -G 16" } */
+
+/* { dg-final { scan-assembler "\.sdata\[^2]+" } } */
+struct test_s {
+    int a;
+    int b;
+    int c;
+    int d;
+} global = { 1, 2, 3, 4 }; 
+
+int testfunc ()
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
+    return global.a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var6.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var6.c
new file mode 100644
index 000000000..0c8fe431f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/sdata_var6.c
@@ -0,0 +1,18 @@
+/* { dg-options "-mxl-gp-opt -G 16" } */
+
+struct test_s {
+    int a;
+    int b;
+    int c;
+    int d;
+};
+
+/* { dg-final { scan-assembler "\.sdata2" } } */
+const struct test_s global1 = { 1, 2, 3, 4};
+extern const struct test_s global2;
+
+int testfunc ()
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r2" } } */
+    return global2.a + global1.a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst1.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst1.c
new file mode 100644
index 000000000..2a74f4ce7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst1.c
@@ -0,0 +1,12 @@
+#include <string.h>
+
+/* { dg-final { scan-assembler "\.rodata*" } } */
+/* { dg-final { scan-assembler "\.data*" } } */
+
+char *string1 = "string1";
+
+int testfunc (char *cptr)
+{
+/* { dg-final { scan-assembler-not "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
+    strcpy (string1, cptr);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst1_gpopt.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst1_gpopt.c
new file mode 100644
index 000000000..5b5d3db18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst1_gpopt.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mxl-gp-opt" } */
+
+#include <string.h>
+
+/* { dg-final { scan-assembler "\.rodata*" } } */
+/* { dg-final { scan-assembler "\.sdata\[^2]+" } } */
+char *string1 = "string1";
+
+int testfunc (char *cptr)
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
+    strcpy (string1, cptr);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst2.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst2.c
new file mode 100644
index 000000000..c375339dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst2.c
@@ -0,0 +1,13 @@
+#include <string.h>
+
+/* { dg-final { scan-assembler "\.rodata*" } } */
+/* { dg-final { scan-assembler "\.data*" } } */
+const char *string1 = "string1";
+
+char* testfunc (char *cptr)
+{
+/* { dg-final { scan-assembler-not "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
+    strcpy (cptr, string1);
+
+    return cptr;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst2_gpopt.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst2_gpopt.c
new file mode 100644
index 000000000..057e8c447
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/string_cst2_gpopt.c
@@ -0,0 +1,15 @@
+/* { dg-options "-mxl-gp-opt" } */
+
+#include <string.h>
+
+/* { dg-final { scan-assembler "\.rodata*" } } */
+/* { dg-final { scan-assembler "\.sdata\[^2]+" } } */
+const char *string1 = "string1";
+
+char* testfunc (char *cptr)
+{
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
+    strcpy (cptr, string1);
+
+    return cptr;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/strings1.c
new file mode 100644
index 000000000..7a63faf79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/microblaze/others/strings1.c
@@ -0,0 +1,13 @@
+/* { dg-options "-O3" } */
+
+#include <string.h>
+
+/* { dg-final { scan-assembler "\.rodata*" } } */
+extern void somefunc (char *);
+int testfunc ()
+{
+    char string2[80];
+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */    
+    strcpy (string2, "hello");
+    somefunc (string2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/20020620-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/20020620-1.c
new file mode 100644
index 000000000..f3bed5963
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/20020620-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mlong64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+int foo (int *x, int i)
+{
+  return x[i] + i;
+}
+/* { dg-final { scan-assembler-not "\tmove" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c
new file mode 100644
index 000000000..75bd1b664
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long32.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=eabi -mgp32 -mlong32" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c
new file mode 100644
index 000000000..1649433e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi32-long64.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=eabi -mgp32 -mlong64" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c
new file mode 100644
index 000000000..03d7c2718
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long32.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=eabi -mgp64 -mlong32" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c
new file mode 100644
index 000000000..bb6fa17ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-eabi64-long64.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=eabi -mgp64 -mlong64" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-main.h b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-main.h
new file mode 100644
index 000000000..f47a2e304
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-main.h
@@ -0,0 +1,74 @@
+#define FOR_EACH_SCALAR(F)	\
+  F(sc, signed char)		\
+  F(uc, unsigned char)		\
+  F(ss, short)			\
+  F(us, unsigned short)		\
+  F(si, int)			\
+  F(ui, unsigned int)		\
+  F(sl, long)			\
+  F(ul, unsigned long)		\
+  F(sll, long long)		\
+  F(ull, unsigned long long)	\
+  F(f, float)			\
+  F(d, double)			\
+  F(ld, long double)		\
+  F(ptr, void *)
+
+#define EXTERN(SUFFIX, TYPE) extern TYPE x##SUFFIX;
+#define STATIC(SUFFIX, TYPE) static TYPE s##SUFFIX;
+#define COMMON(SUFFIX, TYPE) TYPE c##SUFFIX;
+
+#define GETADDR(SUFFIX, TYPE)			\
+  TYPE *get##SUFFIX (int which)			\
+  {						\
+    return (which == 0 ? &c##SUFFIX		\
+	    : which == 1 ? &s##SUFFIX		\
+	    : &x##SUFFIX);			\
+  }
+
+#define COPY(SUFFIX, TYPE) c##SUFFIX = s##SUFFIX; s##SUFFIX = x##SUFFIX;
+
+FOR_EACH_SCALAR (EXTERN)
+FOR_EACH_SCALAR (STATIC)
+FOR_EACH_SCALAR (COMMON)
+
+FOR_EACH_SCALAR (GETADDR)
+
+void
+copy (void)
+{
+  FOR_EACH_SCALAR (COPY);
+}
+
+extern void foo (int);
+
+void
+sibcall1 (void)
+{
+  foo (1);
+}
+
+void
+sibcall2 (void)
+{
+  foo (csi + ssi + xsi);
+}
+
+static void
+sibcall3 (void)
+{
+  foo (1);
+  foo (2);
+  foo (3);
+}
+
+extern void bar (void (*) (void));
+
+int
+nested (int x)
+{
+  void sub (void) { foo (x); }
+  bar (sub);
+  bar (sibcall3);
+  return 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c
new file mode 100644
index 000000000..11dfe2bc8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-no-shared.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=n32 -mlong32 -mabicalls -mno-shared -mno-plt" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c
new file mode 100644
index 000000000..ffbe62c48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32-pic.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=n32 -mlong32 -fpic" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32.c
new file mode 100644
index 000000000..f6fa20d12
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long32.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=n32 -mlong32 addressing=absolute" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c
new file mode 100644
index 000000000..a30b573cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-no-shared.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=n32 -mlong64 -mabicalls -mno-shared -mno-plt" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c
new file mode 100644
index 000000000..f9729a3dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64-pic.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=n32 -mlong64 -fpic" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64.c
new file mode 100644
index 000000000..b064bf5e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n32-long64.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=n32 -mlong64 addressing=absolute" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c
new file mode 100644
index 000000000..6a5240912
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-no-shared.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=64 -mlong32 -mabicalls -mno-shared -mno-plt" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c
new file mode 100644
index 000000000..6a5203e8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32-pic.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=64 -mlong32 -fpic" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32.c
new file mode 100644
index 000000000..d5f52d94c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long32.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=64 -mlong32 addressing=absolute" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c
new file mode 100644
index 000000000..113bbcc5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-no-shared.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=64 -mlong64 -mabicalls -mno-shared -mno-plt" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c
new file mode 100644
index 000000000..5f734687c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64-pic.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=64 -mlong64 -fpic" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64.c
new file mode 100644
index 000000000..19e6d91d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-n64-long64.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=64 -mlong64 addressing=absolute" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c
new file mode 100644
index 000000000..fb1b888d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-no-shared.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=32 -mlong32 -mabicalls -mno-shared -mno-plt" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c
new file mode 100644
index 000000000..64a7f5854
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32-pic.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=32 -mlong32 -fpic" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32.c
new file mode 100644
index 000000000..790122077
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long32.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=32 -mlong32 addressing=absolute" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c
new file mode 100644
index 000000000..2f28aeb61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-no-shared.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=32 -mlong64 -mabicalls -mno-shared -mno-plt" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c
new file mode 100644
index 000000000..89cd9a207
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64-pic.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=32 -mlong64 -fpic" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64.c
new file mode 100644
index 000000000..840e9aa13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o32-long64.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=32 -mlong64 addressing=absolute" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c
new file mode 100644
index 000000000..832550e45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-no-shared.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=o64 -mlong32 -mabicalls -mno-shared -mno-plt" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c
new file mode 100644
index 000000000..e06b88292
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32-pic.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=o64 -mlong32 -fpic" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32.c
new file mode 100644
index 000000000..54ac2d707
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long32.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=o64 -mlong32 addressing=absolute" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c
new file mode 100644
index 000000000..94848f4e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-no-shared.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=o64 -mlong64 -mabicalls -mno-shared -mno-plt" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c
new file mode 100644
index 000000000..8c2ca36d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64-pic.c
@@ -0,0 +1,3 @@
+/* { dg-options "-mabi=o64 -mlong64 -fpic" } */
+/* { dg-error "is incompatible with" "" { target *-*-* } 0 } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64.c
new file mode 100644
index 000000000..02633567c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/abi-o64-long64.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mabi=o64 -mlong64 -mno-abicalls" } */
+#include "abi-main.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c
new file mode 100644
index 000000000..3a132deaf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-1.c
@@ -0,0 +1,35 @@
+/* Check that certain preprocessor macros are defined, and do some
+   consistency checks.  */
+/* { dg-do compile } */
+
+const char *compiled_for = _MIPS_ARCH;
+const char *optimized_for = _MIPS_TUNE;
+
+#if __mips_fpr != 32 && __mips_fpr != 64
+#error Bad __mips_fpr
+#endif
+
+/* Test complementary macro pairs: exactly one of each pair
+   must be defined.  */
+
+#if defined (_R3000) == defined (_R4000)
+#error _R3000 / _R4000 mismatch
+#endif
+
+#if defined (__mips_hard_float) == defined (__mips_soft_float)
+#error __mips_hard_float / __mips_soft_float mismatch
+#endif
+
+#if defined (_MIPSEL) == defined (_MIPSEB)
+#error _MIPSEL / _MIPSEB mismatch
+#endif
+
+/* Check for __mips64 consistency.  */
+
+#if defined (__mips64) != defined (_R4000)
+#error __mips64 / _R4000 mismatch
+#endif
+
+#if defined (__mips64) && __mips != 3 && __mips != 4 && __mips != 64
+#error __mips64 / __mips mismatch
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-2.c
new file mode 100644
index 000000000..192756525
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-2.c
@@ -0,0 +1,18 @@
+/* Check the _MIPSEB and _MIPSEL macros are accurate.  */
+/* { dg-do run } */
+extern void abort (void);
+extern void exit (int);
+
+short foo = 1;
+int main ()
+{
+  char *p = (char *) &foo;
+
+#ifdef _MIPSEB
+  if (p[0] != 0 || p[1] != 1)
+#else
+  if (p[0] != 1 || p[1] != 0)
+#endif
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c
new file mode 100644
index 000000000..6a79ce674
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/args-3.c
@@ -0,0 +1,39 @@
+/* __mips, and related defines, guarantee that certain assembly
+   instructions can be used.  Check a few examples.  */
+/* { dg-do run } */
+/* { dg-skip-if "" { *-*-* } { "-mflip-mips16" } { "" } } */
+extern void abort (void);
+extern void exit (int);
+
+typedef int int32 __attribute__ ((mode (SI)));
+typedef int int64 __attribute__ ((mode (DI)));
+int foo (float inf, int64 in64, int32 in32)
+{
+  int64 res64;
+  int32 res32;
+
+#if __mips != 1 && defined (__mips_hard_float) && !defined (__mips16)
+  __asm__ ("trunc.w.s %0, %1" : "=f" (res32) : "f" (inf));
+  if (res32 != 11)
+    abort ();
+#endif
+
+#if defined (__mips64)
+  __asm__ ("daddu %0, %1, %1" : "=r" (res64) : "r" (in64));
+  if (res64 != 50)
+    abort ();
+#endif
+
+#if (__mips == 4 || __mips == 32 || __mips == 64) && !defined (__mips16)
+  __asm__ ("move %0,%.\n\tmovn %0,%1,%2"
+	   : "=&r" (res32) : "r" (in32), "r" (in64 != 0));
+  if (res32 != 60)
+    abort ();
+#endif
+}
+
+int main ()
+{
+  foo (11.4f, 25, 60);
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/asm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/asm-1.c
new file mode 100644
index 000000000..8df268946
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/asm-1.c
@@ -0,0 +1,14 @@
+/* PR target/17565.  GCC used to put the asm into the delay slot
+   of the call.  */
+/* { dg-do assemble } */
+
+NOMIPS16 int foo (int n)
+{
+  register int k asm ("$16") = n;
+  if (k > 0)
+    {
+      bar ();
+      asm ("li %0,0x12345678" : "=r" (k));
+    }
+  return k;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-1.c
new file mode 100644
index 000000000..839d75c2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-1.c
@@ -0,0 +1,44 @@
+/* { dg-do run } */
+
+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target mips_llsc } 0 } */
+
+extern void abort (void);
+extern void exit (int);
+
+NOMIPS16 int main ()
+{
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+  unsigned v = 0;
+  __sync_synchronize ();
+
+  if (!__sync_bool_compare_and_swap (&v, 0, 30000))
+    abort();
+  if (30000 != __sync_val_compare_and_swap (&v, 30000, 100001))
+    abort();
+  __sync_sub_and_fetch (&v, 0x8001);
+  __sync_sub_and_fetch (&v, 0x7fff);
+  if (v != 34465)
+    abort();
+  if (__sync_nand_and_fetch (&v, 0xff) != -162)
+    abort();
+  if (__sync_fetch_and_add (&v, 262) != -162)
+    abort();
+  if (v != 100)
+    abort();
+  if (__sync_or_and_fetch (&v, 0xf001) != 0xf065)
+    abort();
+  if (__sync_and_and_fetch (&v, 0x1000) != 0x1000)
+    abort();
+  if (__sync_xor_and_fetch (&v, 0xa51040) != 0xa50040)
+    abort();
+  __sync_and_and_fetch (&v, 7);
+  if (__sync_lock_test_and_set(&v, 1) != 0)
+    abort();
+  if (v != 1)
+    abort();
+  __sync_lock_release (&v);
+  if (v != 0)
+    abort();
+#endif
+  exit(0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-2.c
new file mode 100644
index 000000000..506295b61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/atomic-memory-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "isa>=2 -mabi=32" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\taddiu\t" } } */
+/* { dg-final { scan-assembler-not "\tsubu" } } */
+
+NOMIPS16 unsigned long
+f(unsigned long *p)
+{
+  return __sync_fetch_and_sub (p, 5);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-1.c
new file mode 100644
index 000000000..6ef50e8a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-1.c
@@ -0,0 +1,14 @@
+/* Octeon targets should use "bbit" instructions for these "if" statements,
+   but we test for "bbit" elsewhere.  On other targets, we should implement
+   the "if" statements using an "andi" instruction followed by a branch
+   on zero.  */
+/* { dg-options "forbid_cpu=octeon.*" } */
+
+void bar (void);
+NOMIPS16 void f1 (int x) { if (x & 4) bar (); }
+NOMIPS16 void f2 (int x) { if ((x >> 2) & 1) bar (); }
+NOMIPS16 void f3 (unsigned int x) { if (x & 0x10) bar (); }
+NOMIPS16 void f4 (unsigned int x) { if ((x >> 4) & 1) bar (); }
+/* { dg-final { scan-assembler "\tandi\t.*\tandi\t.*\tandi\t.*\tandi\t" } } */
+/* { dg-final { scan-assembler-not "\tsrl\t" } } */
+/* { dg-final { scan-assembler-not "\tsra\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-10.c
new file mode 100644
index 000000000..e2b1b5f6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-10.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mshared -mabi=n32" } */
+/* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */
+/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (int (*bar) (void), int *x)
+{
+  *x = bar ();
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fff8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-11.c
new file mode 100644
index 000000000..962eb1b5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-11.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mshared -mabi=n32" } */
+/* { dg-final { scan-assembler "\tsd\t\\\$28," } } */
+/* { dg-final { scan-assembler "\tld\t\\\$28," } } */
+/* { dg-final { scan-assembler "\taddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */
+/* { dg-final { scan-assembler "\tlw\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$28\\)\n" } } */
+/* { dg-final { scan-assembler "\taddiu\t\\\$1,\\\$1,%got_ofst\\(\[^)\]*\\)\n" } } */
+/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (int (*bar) (void), int *x)
+{
+  *x = bar ();
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fffc;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-12.c
new file mode 100644
index 000000000..4aef160ad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-12.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mshared -mabi=64" } */
+/* { dg-final { scan-assembler-not "(\\\$28|%gp_rel|%got)" } } */
+/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (int (*bar) (void), int *x)
+{
+  *x = bar ();
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fff8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-13.c
new file mode 100644
index 000000000..8a6fb049f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-13.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mshared -mabi=64" } */
+/* { dg-final { scan-assembler "\tsd\t\\\$28," } } */
+/* { dg-final { scan-assembler "\tld\t\\\$28," } } */
+/* { dg-final { scan-assembler "\tdaddiu\t\\\$28,\\\$28,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$28\\)\n" } } */
+/* { dg-final { scan-assembler "\tdaddiu\t\\\$1,\\\$1,%got_ofst\\(\[^)\]*\\)\n" } } */
+/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (int (*bar) (void), int *x)
+{
+  *x = bar ();
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fffc;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-14.c
new file mode 100644
index 000000000..026417e16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-14.c
@@ -0,0 +1,23 @@
+/* An executable version of branch-2.c.  */
+/* { dg-do run } */
+
+#include "branch-helper.h"
+
+void __attribute__((noinline))
+foo (volatile int *x)
+{
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fff8;
+}
+
+int
+main (void)
+{
+  int x = 0;
+  int y = 1;
+
+  foo (&x);
+  foo (&y);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-15.c
new file mode 100644
index 000000000..dee7a0504
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-15.c
@@ -0,0 +1,23 @@
+/* An executable version of branch-3.c.  */
+/* { dg-do run } */
+
+#include "branch-helper.h"
+
+void
+foo (volatile int *x)
+{
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fffc;
+}
+
+int
+main (void)
+{
+  int x = 0;
+  int y = 1;
+
+  foo (&x);
+  foo (&y);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-2.c
new file mode 100644
index 000000000..6409c4cc5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-2.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mshared -mabi=32" } */
+/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|cpload)" } } */
+/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */
+/* { dg-final { scan-assembler-not "\\.cprestore" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (volatile int *x)
+{
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fff8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-3.c
new file mode 100644
index 000000000..5fcfece3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-3.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mshared -mabi=32" } */
+/* { dg-final { scan-assembler "\t\\.cpload\t\\\$25\n" } } */
+/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */
+/* { dg-final { scan-assembler-not "\\.cprestore" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (volatile int *x)
+{
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fffc;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-4.c
new file mode 100644
index 000000000..31e4909e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-4.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mshared -mabi=n32" } */
+/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */
+/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (volatile int *x)
+{
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fff8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-5.c
new file mode 100644
index 000000000..1e9c120c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-5.c
@@ -0,0 +1,14 @@
+/* { dg-options "-mshared -mabi=n32" } */
+/* { dg-final { scan-assembler "\taddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */
+/* { dg-final { scan-assembler "\tlw\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */
+/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */
+/* { dg-final { scan-assembler-not "\\\$28" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (volatile int *x)
+{
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fffc;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-6.c
new file mode 100644
index 000000000..77e0340eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-6.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mshared -mabi=64" } */
+/* { dg-final { scan-assembler-not "(\\\$25|\\\$28|%gp_rel|%got)" } } */
+/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (volatile int *x)
+{
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fff8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-7.c
new file mode 100644
index 000000000..8ad6808c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-7.c
@@ -0,0 +1,14 @@
+/* { dg-options "-mshared -mabi=64" } */
+/* { dg-final { scan-assembler "\tdaddiu\t\\\$3,\\\$3,%lo\\(%neg\\(%gp_rel\\(foo\\)\\)\\)\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$1,%got_page\\(\[^)\]*\\)\\(\\\$3\\)\\n" } } */
+/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */
+/* { dg-final { scan-assembler-not "\\\$28" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (volatile int *x)
+{
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fffc;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-8.c
new file mode 100644
index 000000000..ba5f95437
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-8.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mshared -mabi=32" } */
+/* { dg-final { scan-assembler-not "(\\\$28|cpload|cprestore)" } } */
+/* { dg-final { scan-assembler-not "\tjr\t\\\$1\n" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (int (*bar) (void), int *x)
+{
+  *x = bar ();
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fff8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-9.c
new file mode 100644
index 000000000..cad1c003c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-9.c
@@ -0,0 +1,18 @@
+/* { dg-options "-mshared -mabi=32" } */
+/* { dg-final { scan-assembler "\t\\.cpload\t\\\$25\n" } } */
+/* { dg-final { scan-assembler "\t\\.cprestore\t16\n" } } */
+/* { dg-final { scan-assembler "\tlw\t\\\$1,16\\(\\\$(fp|sp)\\)\n" } } */
+/* { dg-final { scan-assembler "\tlw\t\\\$1,%got\\(\[^)\]*\\)\\(\\\$1\\)\n" } } */
+/* { dg-final { scan-assembler "\taddiu\t\\\$1,\\\$1,%lo\\(\[^)\]*\\)\n" } } */
+/* { dg-final { scan-assembler "\tjr\t\\\$1\n" } } */
+/* { dg-final { scan-assembler-not "\\\$28" } } */
+
+#include "branch-helper.h"
+
+NOMIPS16 void
+foo (int (*bar) (void), int *x)
+{
+  *x = bar ();
+  if (__builtin_expect (*x == 0, 1))
+    OCCUPY_0x1fffc;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-1.c
new file mode 100644
index 000000000..f72f2acfb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-1.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mbranch-cost=1 isa>=4" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+NOMIPS16 int
+foo (int x, int y, int z, int k)
+{
+  return x == k ? x + y : z - x;
+}
+/* { dg-final { scan-assembler-not "\t(movz|movn)\t" } } */
+/* { dg-final { scan-assembler "\t(bne|beq)\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c
new file mode 100644
index 000000000..3b2c4a13e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-cost-2.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mbranch-cost=10 isa>=4" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+NOMIPS16 int
+foo (int x, int y, int z, int k)
+{
+  return x == k ? x + y : z - x;
+}
+/* { dg-final { scan-assembler "\t(movz|movn)\t" } } */
+/* { dg-final { scan-assembler-not "\t(bne|beq)\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-helper.h b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-helper.h
new file mode 100644
index 000000000..85399be4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/branch-helper.h
@@ -0,0 +1,37 @@
+/* DN(X) generates 2**N copies of asm instruction X.  */
+#define D0(X) X
+#define D1(X) X "\n\t" X
+#define D2(X) D1 (D1 (X))
+#define D3(X) D2 (D1 (X))
+#define D4(X) D2 (D2 (X))
+#define D5(X) D4 (D1 (X))
+#define D6(X) D4 (D2 (X))
+#define D7(X) D4 (D2 (D1 (X)))
+#define D8(X) D4 (D4 (X))
+#define D9(X) D8 (D1 (X))
+#define D10(X) D8 (D2 (X))
+#define D11(X) D8 (D2 (D1 (X)))
+#define D12(X) D8 (D4 (X))
+#define D13(X) D8 (D4 (D1 (X)))
+#define D14(X) D8 (D4 (D2 (X)))
+
+/* Emit something that is 0x1fff8 bytes long, which is the largest
+   permissible range for non-MIPS16 forward branches.  */
+#define OCCUPY_0x1fff8 \
+  asm (D14 ("nop") "\n\t" \
+       D13 ("nop") "\n\t" \
+       D12 ("nop") "\n\t" \
+       D11 ("nop") "\n\t" \
+       D10 ("nop") "\n\t" \
+       D9 ("nop") "\n\t" \
+       D8 ("nop") "\n\t" \
+       D7 ("nop") "\n\t" \
+       D6 ("nop") "\n\t" \
+       D5 ("nop") "\n\t" \
+       D4 ("nop") "\n\t" \
+       D3 ("nop") "\n\t" \
+       D2 ("nop") "\n\t" \
+       D1 ("nop"))
+
+/* Likewise emit something that is 0x1fffc bytes long.  */
+#define OCCUPY_0x1fffc do { asm ("nop"); OCCUPY_0x1fff8; } while (0)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-1.c
new file mode 100644
index 000000000..24016f269
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-1.c
@@ -0,0 +1,10 @@
+/* { dg-options "isa_rev>=2" } */
+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
+
+NOMIPS16 unsigned short
+foo (unsigned short x)
+{
+  return ((x << 8) & 0xff00) | ((x >> 8) & 0xff);
+}
+
+/* { dg-final { scan-assembler "\twsbh\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-2.c
new file mode 100644
index 000000000..e0ca496b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-2.c
@@ -0,0 +1,9 @@
+/* { dg-options "isa_rev>=2" } */
+
+NOMIPS16 unsigned short
+foo (unsigned short x)
+{
+  return __builtin_bswap16 (x);
+}
+
+/* { dg-final { scan-assembler "\twsbh\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-3.c
new file mode 100644
index 000000000..5d2086fd3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-3.c
@@ -0,0 +1,14 @@
+/* { dg-options "isa_rev>=2" } */
+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
+
+NOMIPS16 unsigned int
+foo (unsigned int x)
+{
+  return (((x << 24) & 0xff000000)
+	  | ((x << 8) & 0xff0000)
+	  | ((x >> 8) & 0xff00)
+	  | ((x >> 24) & 0xff));
+}
+
+/* { dg-final { scan-assembler "\twsbh\t" } } */
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-4.c
new file mode 100644
index 000000000..ac37a0114
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-4.c
@@ -0,0 +1,10 @@
+/* { dg-options "isa_rev>=2" } */
+
+NOMIPS16 unsigned int
+foo (unsigned int x)
+{
+  return __builtin_bswap32 (x);
+}
+
+/* { dg-final { scan-assembler "\twsbh\t" } } */
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-5.c
new file mode 100644
index 000000000..45520e4ab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-5.c
@@ -0,0 +1,20 @@
+/* { dg-options "isa_rev>=2 -mgp64" } */
+/* { dg-skip-if "bswap recognition needs expensive optimizations" { *-*-* } { "-O0" "-O1" } { "" } } */
+
+typedef unsigned long long uint64_t;
+
+NOMIPS16 uint64_t
+foo (uint64_t x)
+{
+  return (((x << 56) & 0xff00000000000000ull)
+	  | ((x << 40) & 0xff000000000000ull)
+	  | ((x << 24) & 0xff0000000000ull)
+	  | ((x << 8) & 0xff00000000ull)
+	  | ((x >> 8) & 0xff000000)
+	  | ((x >> 24) & 0xff0000)
+	  | ((x >> 40) & 0xff00)
+	  | ((x >> 56) & 0xff));
+}
+
+/* { dg-final { scan-assembler "\tdsbh\t" } } */
+/* { dg-final { scan-assembler "\tdshd\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-6.c
new file mode 100644
index 000000000..1145357fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/bswap-6.c
@@ -0,0 +1,12 @@
+/* { dg-options "isa_rev>=2 -mgp64" } */
+
+typedef unsigned long long uint64_t;
+
+NOMIPS16 uint64_t
+foo (uint64_t x)
+{
+  return __builtin_bswap64 (x);
+}
+
+/* { dg-final { scan-assembler "\tdsbh\t" } } */
+/* { dg-final { scan-assembler "\tdshd\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/cache-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/cache-1.c
new file mode 100644
index 000000000..f5c3dd307
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/cache-1.c
@@ -0,0 +1,31 @@
+/* { dg-options "isa>=3" } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 void
+f1 (int *area)
+{
+  __builtin_mips_cache (20, area);
+}
+
+NOMIPS16 void
+f2 (const short *area)
+{
+  __builtin_mips_cache (24, area + 10);
+}
+
+NOMIPS16 void
+f3 (volatile unsigned int *area, int offset)
+{
+  __builtin_mips_cache (0, area + offset);
+}
+
+NOMIPS16 void
+f4 (const volatile unsigned char *area)
+{
+  __builtin_mips_cache (4, area - 80);
+}
+
+/* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-1.c
new file mode 100644
index 000000000..e4b7acefa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-1.c
@@ -0,0 +1,49 @@
+/* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=32" } */
+/* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalrs?\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalrs?\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalrs?\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjr\t" } } */
+
+__attribute__ ((noinline)) static void staticfunc () { asm (""); }
+int normal ();
+void normal2 ();
+
+NOMIPS16 f (int *p)
+{
+  *p = normal ();
+  normal2 ();
+  staticfunc ();
+  return 1;
+}
+
+int tail ();
+
+NOMIPS16 h ()
+{
+  return tail ();
+}
+
+void tail2 ();
+
+NOMIPS16 void g ()
+{
+  tail2 ();
+}
+
+__attribute__ ((visibility ("hidden"))) void tail3 ();
+
+NOMIPS16 void j ()
+{
+  tail3 ();
+}
+
+__attribute__ ((noinline)) static void tail4 () { asm (""); }
+
+NOMIPS16 void k ()
+{
+  tail4 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-2.c
new file mode 100644
index 000000000..c2fc8eaad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-2.c
@@ -0,0 +1,10 @@
+/* See through some simple data-flow.  */
+/* { dg-options "-mrelax-pic-calls" } */
+/* { dg-final { scan-assembler-times "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrs?\t" 2 } } */
+
+NOMIPS16 f ()
+{
+  g ();
+  g ();
+  return 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-3.c
new file mode 100644
index 000000000..37609088d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-3.c
@@ -0,0 +1,11 @@
+/* { dg-options "-mrelax-pic-calls -mno-shared" } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalrs?\t" } } */
+/* { dg-require-visibility "" } */
+
+__attribute__ ((visibility ("hidden"))) void g ();
+
+NOMIPS16 f ()
+{
+  g ();
+  return 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-4.c
new file mode 100644
index 000000000..049e33882
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-4.c
@@ -0,0 +1,9 @@
+/* See through some simple data-flow.  */
+/* { dg-options "-mrelax-pic-calls" } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,g\n1:\tjalr\t" } } */
+
+NOMIPS16 f (int i)
+{
+  while (i--)
+    g ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-5.c
new file mode 100644
index 000000000..2e58178ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-5.c
@@ -0,0 +1,51 @@
+/* Like call-1.c, but for n32.  We cannot use sibling calls for tail and tail2
+   in this case (PR target/57260).  */
+/* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=n32" } */
+/* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjr\t" } } */
+
+__attribute__ ((noinline)) static void staticfunc () { asm (""); }
+int normal ();
+void normal2 ();
+
+NOMIPS16 f (int *p)
+{
+  *p = normal ();
+  normal2 ();
+  staticfunc ();
+  return 1;
+}
+
+int tail ();
+
+NOMIPS16 h ()
+{
+  return tail ();
+}
+
+void tail2 ();
+
+NOMIPS16 void g ()
+{
+  tail2 ();
+}
+
+__attribute__ ((visibility ("hidden"))) void tail3 ();
+
+NOMIPS16 void j ()
+{
+  tail3 ();
+}
+
+__attribute__ ((noinline)) static void tail4 () { asm (""); }
+
+NOMIPS16 void k ()
+{
+  tail4 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-6.c
new file mode 100644
index 000000000..86f3dc4a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-6.c
@@ -0,0 +1,50 @@
+/* Like call-5.c, but for n64.  */
+/* { dg-options "-mrelax-pic-calls -mshared -foptimize-sibling-calls -mabi=64" } */
+/* { dg-skip-if "requires -foptimize-sibling-calls" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,normal2\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,staticfunc\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail2\n1:\tjalr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail3\n1:\tjr\t" } } */
+/* { dg-final { scan-assembler "\\.reloc\t1f,R_MIPS_JALR,tail4\n1:\tjr\t" } } */
+
+__attribute__ ((noinline)) static void staticfunc () { asm (""); }
+int normal ();
+void normal2 ();
+
+NOMIPS16 f (int *p)
+{
+  *p = normal ();
+  normal2 ();
+  staticfunc ();
+  return 1;
+}
+
+int tail ();
+
+NOMIPS16 h ()
+{
+  return tail ();
+}
+
+void tail2 ();
+
+NOMIPS16 void g ()
+{
+  tail2 ();
+}
+
+__attribute__ ((visibility ("hidden"))) void tail3 ();
+
+NOMIPS16 void j ()
+{
+  tail3 ();
+}
+
+__attribute__ ((noinline)) static void tail4 () { asm (""); }
+
+NOMIPS16 void k ()
+{
+  tail4 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-1.c
new file mode 100644
index 000000000..5c86b6c8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-1.c
@@ -0,0 +1,21 @@
+/* Check that we save all call-saved GPRs in a MIPS16 __builtin_eh_return
+   function.  */
+/* { dg-options "(-mips16) isa_rev=0" } */
+
+void bar (void);
+
+MIPS16 void
+foo (int x)
+{
+  __builtin_unwind_init ();
+  __builtin_eh_return (x, bar);
+}
+/* { dg-final { scan-assembler "\\\$16" } } */
+/* { dg-final { scan-assembler "\\\$17" } } */
+/* { dg-final { scan-assembler "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler "\\\$20" } } */
+/* { dg-final { scan-assembler "\\\$21" } } */
+/* { dg-final { scan-assembler "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-2.c
new file mode 100644
index 000000000..b55c30ab0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-2.c
@@ -0,0 +1,19 @@
+/* Check that we save non-MIPS16 GPRs if they are explicitly clobbered.  */
+/* { dg-options "(-mips16) isa_rev=0" } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+
+MIPS16 void
+foo (void)
+{
+  asm volatile ("" ::: "$19", "$23", "$24", "$30");
+}
+/* { dg-final { scan-assembler-not "\\\$16" } } */
+/* { dg-final { scan-assembler-not "\\\$17" } } */
+/* { dg-final { scan-assembler-not "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler-not "\\\$20" } } */
+/* { dg-final { scan-assembler-not "\\\$21" } } */
+/* { dg-final { scan-assembler-not "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler-not "\\\$24" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-3.c
new file mode 100644
index 000000000..84cdb3b88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/call-saved-3.c
@@ -0,0 +1,22 @@
+/* Check that we save all call-saved GPRs in a MIPS16 __builtin_setjmp
+   function.  */
+/* { dg-options "(-mips16) isa_rev=0" } */
+
+void bar (void);
+extern int buf[];
+
+MIPS16 void
+foo (int x)
+{
+  if (__builtin_setjmp (buf) == 0)
+    bar();
+}
+/* { dg-final { scan-assembler "\\\$16" } } */
+/* { dg-final { scan-assembler "\\\$17" } } */
+/* { dg-final { scan-assembler "\\\$18" } } */
+/* { dg-final { scan-assembler "\\\$19" } } */
+/* { dg-final { scan-assembler "\\\$20" } } */
+/* { dg-final { scan-assembler "\\\$21" } } */
+/* { dg-final { scan-assembler "\\\$22" } } */
+/* { dg-final { scan-assembler "\\\$23" } } */
+/* { dg-final { scan-assembler "\\\$(30|fp)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-1.c
new file mode 100644
index 000000000..f1554f593
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-msynci isa_rev>=2" } */
+/* { dg-final { scan-assembler "\tsynci\t" } } */
+/* { dg-final { scan-assembler "\tjr.hb\t" } } */
+/* { dg-final { scan-assembler-not "_flush_cache|mips_sync_icache|_cacheflush" } } */
+
+NOMIPS16 void f()
+{
+  int size = 40;
+  char *memory = __builtin_alloca(size);
+  __builtin___clear_cache(memory, memory + size);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-2.c
new file mode 100644
index 000000000..f1f7f8190
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/clear-cache-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mips32" } */
+/* { dg-final { scan-assembler-not "\tsynci" } } */
+/* { dg-final { scan-assembler-not "\tjr.hb" } } */
+/* { dg-final { scan-assembler "_flush_cache|mips_sync_icache|_cacheflush" } } */
+
+void f()
+{
+  int size = 40;
+  char *memory = __builtin_alloca(size);
+  __builtin___clear_cache(memory, memory + size);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-1.c
new file mode 100644
index 000000000..b3e864df6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-1.c
@@ -0,0 +1,51 @@
+/* { dg-options "(-mips16) -mcode-readable=yes -mgp32 addressing=absolute" } */
+/* { dg-skip-if ".half requires -O" { *-*-* } { "-O0" } { "" } } */
+
+volatile int x1;
+volatile int x2;
+volatile int x3;
+volatile int x4;
+volatile int x5;
+volatile int x6;
+volatile int x7;
+volatile int x8;
+volatile int x9;
+volatile int x10;
+volatile int x11;
+
+MIPS16 int
+foo (int i, volatile *x)
+{
+  switch (i)
+    {
+    case 1: return x1 + x[0];
+    case 2: return x2 + x[1];
+    case 3: return x3 + x[2];
+    case 4: return x4 + x[3];
+    case 5: return x5 + x[4];
+    case 6: return x6 + x[5];
+    case 7: return x7 + x[6];
+    case 8: return x8 + x[7];
+    case 9: return x9 + x[8];
+    case 10: return x10 + x[9];
+    case 11: return x11 + x[10];
+    default: return 0;
+    }
+}
+
+extern int k[];
+
+MIPS16 int *
+bar (void)
+{
+  return k;
+}
+
+/* { dg-final { scan-assembler "\tla\t" } } */
+/* { dg-final { scan-assembler "\t\\.half\t" } } */
+/* { dg-final { scan-assembler-not "%hi\\(\[^)\]*L" } } */
+/* { dg-final { scan-assembler-not "%lo\\(\[^)\]*L" } } */
+
+/* { dg-final { scan-assembler "\t\\.word\tk\n" } } */
+/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */
+/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-2.c
new file mode 100644
index 000000000..3d325049d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-2.c
@@ -0,0 +1,49 @@
+/* { dg-options "(-mips16) -mcode-readable=pcrel -mgp32 addressing=absolute" } */
+
+volatile int x1;
+volatile int x2;
+volatile int x3;
+volatile int x4;
+volatile int x5;
+volatile int x6;
+volatile int x7;
+volatile int x8;
+volatile int x9;
+volatile int x10;
+volatile int x11;
+
+MIPS16 int
+foo (int i, volatile *x)
+{
+  switch (i)
+    {
+    case 1: return x1 + x[0];
+    case 2: return x2 + x[1];
+    case 3: return x3 + x[2];
+    case 4: return x4 + x[3];
+    case 5: return x5 + x[4];
+    case 6: return x6 + x[5];
+    case 7: return x7 + x[6];
+    case 8: return x8 + x[7];
+    case 9: return x9 + x[8];
+    case 10: return x10 + x[9];
+    case 11: return x11 + x[10];
+    default: return 0;
+    }
+}
+
+extern int k[];
+
+MIPS16 int *
+bar (void)
+{
+  return k;
+}
+
+/* { dg-final { scan-assembler-not "\tla\t" } } */
+/* { dg-final { scan-assembler-not "\t\\.half\t" } } */
+/* { dg-final { scan-assembler "\t\\.word\t\[^\n\]*L" } } */
+
+/* { dg-final { scan-assembler "\t\\.word\tk\n" } } */
+/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */
+/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-3.c
new file mode 100644
index 000000000..aaf187493
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-3.c
@@ -0,0 +1,50 @@
+/* { dg-options "(-mips16) -mcode-readable=no -mgp32 addressing=absolute" } */
+
+volatile int x1;
+volatile int x2;
+volatile int x3;
+volatile int x4;
+volatile int x5;
+volatile int x6;
+volatile int x7;
+volatile int x8;
+volatile int x9;
+volatile int x10;
+volatile int x11;
+
+MIPS16 int
+foo (int i, volatile *x)
+{
+  switch (i)
+    {
+    case 1: return x1 + x[0];
+    case 2: return x2 + x[1];
+    case 3: return x3 + x[2];
+    case 4: return x4 + x[3];
+    case 5: return x5 + x[4];
+    case 6: return x6 + x[5];
+    case 7: return x7 + x[6];
+    case 8: return x8 + x[7];
+    case 9: return x9 + x[8];
+    case 10: return x10 + x[9];
+    case 11: return x11 + x[10];
+    default: return 0;
+    }
+}
+
+extern int k[];
+
+MIPS16 int *
+bar (void)
+{
+  return k;
+}
+
+/* { dg-final { scan-assembler-not "\tla\t" } } */
+/* { dg-final { scan-assembler-not "\t\\.half\t" } } */
+/* { dg-final { scan-assembler "%hi\\(\[^)\]*L" } } */
+/* { dg-final { scan-assembler "%lo\\(\[^)\]*L" } } */
+
+/* { dg-final { scan-assembler-not "\t\\.word\tk\n" } } */
+/* { dg-final { scan-assembler "%hi\\(k\\)" } } */
+/* { dg-final { scan-assembler "%lo\\(k\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-4.c
new file mode 100644
index 000000000..4db89f874
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/code-readable-4.c
@@ -0,0 +1,51 @@
+/* { dg-options "(-mips16) -mcode-readable=yes -mabi=eabi -mgp64" } */
+/* { dg-skip-if ".half requires -O" { *-*-* } { "-O0" } { "" } } */
+
+volatile int x1;
+volatile int x2;
+volatile int x3;
+volatile int x4;
+volatile int x5;
+volatile int x6;
+volatile int x7;
+volatile int x8;
+volatile int x9;
+volatile int x10;
+volatile int x11;
+
+MIPS16 int
+foo (int i, volatile *x)
+{
+  switch (i)
+    {
+    case 1: return x1 + x[0];
+    case 2: return x2 + x[1];
+    case 3: return x3 + x[2];
+    case 4: return x4 + x[3];
+    case 5: return x5 + x[4];
+    case 6: return x6 + x[5];
+    case 7: return x7 + x[6];
+    case 8: return x8 + x[7];
+    case 9: return x9 + x[8];
+    case 10: return x10 + x[9];
+    case 11: return x11 + x[10];
+    default: return 0;
+    }
+}
+
+extern int k[];
+
+MIPS16 int *
+bar (void)
+{
+  return k;
+}
+
+/* { dg-final { scan-assembler "\tla\t" } } */
+/* { dg-final { scan-assembler "\t\\.half\t" } } */
+/* { dg-final { scan-assembler-not "%hi\\(\[^)\]*L" } } */
+/* { dg-final { scan-assembler-not "%lo\\(\[^)\]*L" } } */
+
+/* { dg-final { scan-assembler "\t\\.dword\tk\n" } } */
+/* { dg-final { scan-assembler-not "%hi\\(k\\)" } } */
+/* { dg-final { scan-assembler-not "%lo\\(k\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-1.c
new file mode 100644
index 000000000..a5f01e4ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-1.c
@@ -0,0 +1,10 @@
+/* Derive a constant (0x1233ffff) from an intermediate value
+   (0x1234000) used to build another constant.  */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "0x12330000|305332224" } } */
+/* { dg-final { scan-assembler "\td?addiu\t\\\$5,\\\$\[0-9\]*,-1" } } */
+
+NOMIPS16 void f ()
+{
+  g (0x12340001, 0x1233ffff);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-2.c
new file mode 100644
index 000000000..8dad5a70b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/const-anchor-2.c
@@ -0,0 +1,9 @@
+/* Derive a constant (0x30001) from another constant.  */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "0x300000|196608" } } */
+/* { dg-final { scan-assembler "\td?addiu\t\\\$5,\\\$\[0-9\]*,32763" } } */
+
+NOMIPS16 void f ()
+{
+  g (0x28006, 0x30001);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-1.c
new file mode 100644
index 000000000..08234a6e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-1.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tddiv\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x / y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-10.c
new file mode 100644
index 000000000..fb8953def
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-10.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdivu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x / y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-11.c
new file mode 100644
index 000000000..ff129292a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-11.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdiv\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x % y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-12.c
new file mode 100644
index 000000000..57866ceb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-12.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdivu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x % y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-13.c
new file mode 100644
index 000000000..cf746a663
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-13.c
@@ -0,0 +1,17 @@
+/* { dg-options "(-mips16) -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+typedef int int32_t;
+typedef unsigned int uint32_t;
+typedef long long int64_t;
+typedef unsigned long long uint64_t;
+
+MIPS16 int32_t f1 (int32_t x, int32_t y) { return x / y + x % y; }
+MIPS16 uint32_t f2 (uint32_t x, uint32_t y) { return x / y + x % y; }
+MIPS16 int64_t f3 (int64_t x, int64_t y) { return x / y + x % y; }
+MIPS16 uint64_t f4 (uint64_t x, uint64_t y) { return x / y + x % y; }
+
+/* { dg-final { scan-assembler-times "\tdiv\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdivu\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tddiv\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tddivu\t" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-2.c
new file mode 100644
index 000000000..257ca923d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-2.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tddivu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x / y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-3.c
new file mode 100644
index 000000000..b9ae3684e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-3.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tddiv\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x % y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-4.c
new file mode 100644
index 000000000..5f05d8e78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-4.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tddivu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x % y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-5.c
new file mode 100644
index 000000000..294cc7f24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-5.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdiv\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x / y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-6.c
new file mode 100644
index 000000000..fb8953def
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-6.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdivu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x / y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-7.c
new file mode 100644
index 000000000..ff129292a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-7.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdiv\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x % y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-8.c
new file mode 100644
index 000000000..57866ceb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-8.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdivu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x % y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/div-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-9.c
new file mode 100644
index 000000000..294cc7f24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/div-9.c
@@ -0,0 +1,12 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-final { scan-assembler "\tdiv\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x / y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c
new file mode 100644
index 000000000..f8c0b8b44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dmult-1.c
@@ -0,0 +1,10 @@
+/* { dg-options "forbid_cpu=octeon.* -mgp64" } */
+/* { dg-final { scan-assembler "\tdmult\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tdmul\t" } } */
+
+long long
+f (long long a, long long b)
+{
+  return a * b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c
new file mode 100644
index 000000000..a48f561f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dpaq_sa_l_w.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target { fixed_point } } } */
+/* This test requires widening_mul */
+/* { dg-options "-mgp32 -mdsp -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tdpaq_sa.l.w\t\\\$ac" 3 } } */
+
+NOMIPS16 _Sat long long _Fract
+f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  return (_Sat long long _Fract) x * y + z;
+}
+
+NOMIPS16 _Sat long long _Fract
+f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  return z + (_Sat long long _Fract) y * x;
+}
+
+NOMIPS16 _Sat long long _Fract
+f3 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  _Sat long long _Fract t = (_Sat long long _Fract) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z = t + z; /* Need to put z at the end.  GCC does not swap operands to
+		  match the ssmadd pattern, because types are saturating.  */
+  return z;
+}
+
+long long _Fract
+f4 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  return (long long _Fract) x * y + z;
+}
+
+long long _Fract
+f5 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  return z + (long long _Fract) y * x;
+}
+
+long long _Fract
+f6 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  long long _Fract t = (long long _Fract) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z = t + z; /* Need to put z at the end.  GCC does not swap operands to
+		  match the ssmadd pattern, because types are saturating.  */
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c
new file mode 100644
index 000000000..fb63a1db8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dpsq_sa_l_w.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target { fixed_point } } } */
+/* This test requires widening_mul */
+/* { dg-options "-mgp32 -mdsp -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tdpsq_sa.l.w\t\\\$ac" 2 } } */
+
+NOMIPS16 _Sat long long _Fract
+f1 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  return z - (_Sat long long _Fract) x * y;
+}
+
+NOMIPS16 _Sat long long _Fract
+f2 (_Sat long _Fract x, _Sat long _Fract y, _Sat long long _Fract z)
+{
+  _Sat long long _Fract t = (_Sat long long _Fract) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
+
+long long _Fract
+f3 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  return z - (long long _Fract) x * y;
+}
+
+long long _Fract
+f4 (long _Fract x, long _Fract y, long long _Fract z)
+{
+  long long _Fract t = (long long _Fract) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dse-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dse-1.c
new file mode 100644
index 000000000..e53189cad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dse-1.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+#define TEST(ID, TYPE1, TYPE2)					\
+  union u##ID {							\
+    TYPE1 m1[sizeof (TYPE2) / sizeof (TYPE1)];			\
+    TYPE2 m2;							\
+  };								\
+								\
+  /* The MIPS16 versions of the shifts we need are too		\
+     expensive.  */						\
+  TYPE1 __attribute__((nomips16))				\
+  f##ID (TYPE2 x, union u##ID *u)				\
+  {								\
+    u->m2 = x;							\
+    return (u->m1[0]						\
+	    + u->m1[sizeof (TYPE2) / sizeof (TYPE1) - 1]);	\
+  }								\
+								\
+  TYPE1 __attribute__((nomips16))				\
+  g##ID (union u##ID *u)					\
+  {								\
+    u->m2 = 0;							\
+    return (u->m1[0] | u->m1[1]);				\
+  }
+
+TEST (1, unsigned int, unsigned long long);
+TEST (2, int, long long);
+TEST (3, unsigned short, unsigned long long);
+TEST (4, short, long long);
+TEST (5, unsigned char, unsigned long long);
+TEST (6, signed char, long long);
+
+TEST (7, unsigned short, unsigned int);
+TEST (8, short, int);
+TEST (9, unsigned char, unsigned int);
+TEST (10, signed char, int);
+
+TEST (11, unsigned char, unsigned short);
+TEST (12, signed char, short);
+
+/* { dg-final { scan-assembler-not "\tlh\t" } } */
+/* { dg-final { scan-assembler-not "\tlhu\t" } } */
+/* { dg-final { scan-assembler-not "\tlw\t" } } */
+/* { dg-final { scan-assembler-not "\tlwu\t" } } */
+/* { dg-final { scan-assembler-not "\tlb\t" } } */
+/* { dg-final { scan-assembler-not "\tlbu\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-ctrl.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-ctrl.c
new file mode 100644
index 000000000..4bf449b86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-ctrl.c
@@ -0,0 +1,69 @@
+/* { dg-do run } */
+/* { dg-options "-mdsp -mgp32" } */
+
+extern void abort (void);
+extern void exit (int);
+
+NOMIPS16 void __attribute__ ((noinline))
+test1 (int i)
+{
+  __builtin_mips_wrdsp (i, 63);
+}
+
+NOMIPS16 void __attribute__ ((noinline))
+test2 ()
+{
+  long long a = 0;
+  __builtin_mips_extpdp (a, 3);
+}
+
+NOMIPS16 void __attribute__ ((noinline))
+test3 (int i)
+{
+  long long a = 0;
+  __builtin_mips_extpdp (a, i);
+}
+
+NOMIPS16 void __attribute__ ((noinline))
+test4 ()
+{
+  long long a = 0;
+  int i = 0;
+  __builtin_mips_mthlip (a, i);
+}
+
+NOMIPS16 int
+main ()
+{
+  int cntl;
+
+  /* Test 1: wrdsp */
+  __builtin_mips_wrdsp (0,63);
+  test1 (63);
+  cntl = __builtin_mips_rddsp (63);
+  if (cntl != 63)
+    abort ();
+
+  /* Test 2: extpdp */
+  __builtin_mips_wrdsp (63,63);
+  test2 ();
+  cntl = __builtin_mips_rddsp (63);
+  if (cntl != 59)
+    abort ();
+
+  /* Test 3: extpdpv */
+  __builtin_mips_wrdsp (63,63);
+  test3 (10);
+  cntl = __builtin_mips_rddsp (63);
+  if (cntl != 52)
+    abort ();
+
+  /* Test 4: mthlip */
+  __builtin_mips_wrdsp (8,63);
+  test4 ();
+  cntl = __builtin_mips_rddsp (63);
+  if (cntl != 40)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-lhx.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-lhx.c
new file mode 100644
index 000000000..8fa20a090
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-lhx.c
@@ -0,0 +1,11 @@
+/* Test MIPS32 DSP LHX instruction */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdsp" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* { dg-final { scan-assembler "\tlhx\t" } } */
+
+NOMIPS16 signed short test (signed short *a, int index)
+{
+  return a[index];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c
new file mode 100644
index 000000000..42c4688cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dsp-no-lhx.c
@@ -0,0 +1,10 @@
+/* Test MIPS32 DSP LHX instruction */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdsp" } */
+
+/* { dg-final { scan-assembler-not "\tlhx\t" } } */
+
+NOMIPS16 unsigned short test (unsigned short *a, int index)
+{
+  return a[index];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULT.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULT.c
new file mode 100644
index 000000000..b668e0c6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULT.c
@@ -0,0 +1,19 @@
+/* Test MIPS32 DSP REV 2 MULT instruction.  Tune for a CPU that has
+   pipelined mult.  */
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-mgp32 -mdspr2 -mtune=74kc -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* See PR target/51729 for the reason behind the XFAILs.  */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\\\$ac1" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler "\\\$ac2" { xfail *-*-* } } } */
+
+typedef long long a64;
+
+NOMIPS16 a64 test (a64 *a, int *b, int *c)
+{
+  a[0] = (a64) b[0] * c[0];
+  a[1] = (a64) b[1] * c[1];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c
new file mode 100644
index 000000000..886e4ca88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/dspr2-MULTU.c
@@ -0,0 +1,18 @@
+/* Test MIPS32 DSP REV 2 MULTU instruction.  Tune for a CPU that has
+   pipelined multu.  */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdspr2 -mtune=74kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* See PR target/51729 for the reason behind the XFAILs.  */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler "\\\$ac1" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler "\\\$ac2" { xfail *-*-* } } } */
+
+typedef unsigned long long a64;
+
+NOMIPS16 a64 test (a64 *a, unsigned int *b, unsigned int *c)
+{
+  a[0] = (a64) b[0] * c[0];
+  a[1] = (a64) b[1] * c[1];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-1.c
new file mode 100644
index 000000000..177b5033b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2 -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdext\t" } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+
+struct
+{
+  unsigned long long a:9;
+  unsigned long long d:35;
+  unsigned long long e:10;
+  unsigned long long f:10;
+} t;
+
+NOMIPS16 unsigned long long
+f (void)
+{
+   return t.d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-2.c
new file mode 100644
index 000000000..320d42d2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-2.c
@@ -0,0 +1,15 @@
+/* Turn the truncate,zero_extend,lshiftrt sequence before the or into a
+   zero_extract.  The truncate is due to TARGET_PROMOTE_PROTOTYPES, the
+   zero_extend to PROMOTE_MODE.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2 -mgp64 -mlong64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdext\t" } } */
+/* { dg-final { scan-assembler-not "\tand" } } */
+/* { dg-final { scan-assembler-not "\td?srl" } } */
+
+NOMIPS16 void
+f (unsigned char x, unsigned char *r)
+{
+  *r = 0x50 | (x >> 4);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-3.c
new file mode 100644
index 000000000..66780551b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-3.c
@@ -0,0 +1,15 @@
+/* For MIPS64r2 use DEXT rather than DSLL/DSRL to zero-extend.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2 -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdext\t" } } */
+/* { dg-final { scan-assembler-not "\td?sll" } } */
+
+NOMIPS16 unsigned long long
+f (unsigned *i)
+{
+  unsigned j = *i;
+  j >>= 1;			/* enforce this is all done in SI mode */
+  j++;				/* don't merge the shift and the extension */
+  return j;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-4.c
new file mode 100644
index 000000000..16b848c35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-4.c
@@ -0,0 +1,12 @@
+/* For MIPS64r2 use DEXT rather than DSLL/DSRL for clear_upper32.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2 -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdext\t" } } */
+/* { dg-final { scan-assembler-not "\td?sll" } } */
+
+NOMIPS16 unsigned long long
+f (unsigned long long i)
+{
+  return i & 0xffffffffull;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-5.c
new file mode 100644
index 000000000..8bab2148f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-5.c
@@ -0,0 +1,12 @@
+/* For MIPS32r2 use EXT when ANDing with low-order bitmasks.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\text\t" } } */
+/* { dg-final { scan-assembler-not "\tandi?\t" } } */
+
+NOMIPS16 unsigned
+f (unsigned i)
+{
+  return i & 0x7ffffff;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-6.c
new file mode 100644
index 000000000..e12cbe6e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-6.c
@@ -0,0 +1,12 @@
+/* For MIPS64r2 use DEXT when ANDing with low-order bitmasks.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2 -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdext\t" } } */
+/* { dg-final { scan-assembler-not "\tandi?\t" } } */
+
+NOMIPS16 unsigned long long
+f (unsigned long long i)
+{
+  return i & 0x7ffffffffff;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-7.c
new file mode 100644
index 000000000..2e23dd652
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-7.c
@@ -0,0 +1,12 @@
+/* No need to use ext if we can use andi.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tandi\t" } } */
+/* { dg-final { scan-assembler-not "\td?ext\t" } } */
+
+NOMIPS16 unsigned
+f (unsigned i)
+{
+  return i & 0x7fff;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-8.c
new file mode 100644
index 000000000..9ceee7b9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext-8.c
@@ -0,0 +1,11 @@
+/* Also make sure we don't use ext for MIPS*r1.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev<=1" } */
+/* { dg-final { scan-assembler "\tand\t" } } */
+/* { dg-final { scan-assembler-not "\td?ext\t" } } */
+
+unsigned
+f (unsigned i)
+{
+  return i & 0x7fffff;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ext_ins.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext_ins.c
new file mode 100644
index 000000000..36f0f3fd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ext_ins.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2" } */
+/* { dg-final { scan-assembler "\td?ext\t" } } */
+/* { dg-final { scan-assembler "\td?ins\t" } } */
+
+struct A 
+{
+  unsigned int i : 2;
+  unsigned int j : 3;
+  unsigned int k : 4;
+  unsigned int l : 5;
+};
+
+void func (struct A);
+
+NOMIPS16 unsigned int f1 (struct A a)
+{
+  return a.j;
+}
+
+NOMIPS16 struct A f2 (struct A a, int i)
+{
+  a.j = i;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-1.c
new file mode 100644
index 000000000..9240ea558
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-1.c
@@ -0,0 +1,23 @@
+/* { dg-options "-mgp64 forbid_cpu=octeon.*" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tdsll\t" 5 } } */
+/* { dg-final { scan-assembler-times "\tdsra\t" 5 } } */
+/* { dg-final { scan-assembler-not "\tsll\t" } } */
+
+#define TEST_CHAR(T, N)				\
+  NOMIPS16 T					\
+  f##N (long long d, T *a, T *r)		\
+  {						\
+    T b = (signed char) d; *r = b + *a;		\
+  }
+#define TEST_SHORT(T, N)			\
+  NOMIPS16 T					\
+  g##N (long long d, T *a, T *r)		\
+  {						\
+    T b = (short) d; *r = b + *a;		\
+  }
+#define TEST(T, N) TEST_CHAR (T, N) TEST_SHORT (T, N)
+
+TEST (int, 1);
+TEST (long long, 2);
+TEST_CHAR (short, 3);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-2.c
new file mode 100644
index 000000000..a2036a899
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/extend-2.c
@@ -0,0 +1,12 @@
+/* Check the shift_shift alternative of the AND patterns.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev<=1 -mgp64" } */
+/* { dg-final { scan-assembler "\tdsrl\t" } } */
+/* { dg-final { scan-assembler "\tdsll\t" } } */
+/* { dg-final { scan-assembler-not "\td?ext\t" } } */
+
+unsigned long long
+f (unsigned long long i)
+{
+  return i & 0xffffffff;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-2008.c
new file mode 100644
index 000000000..211d561d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-2008.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mabs=2008" } */
+
+NOMIPS16 double
+fabs_2008 (double d)
+{
+  return __builtin_fabs (d);
+}
+
+/* { dg-final { scan-assembler "\tabs\\.d\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-legacy.c
new file mode 100644
index 000000000..dabc9d09c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabs-legacy.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mabs=legacy" } */
+
+NOMIPS16 double
+fabs_legacy (double d)
+{
+  return __builtin_fabs (d);
+}
+
+/* { dg-final { scan-assembler-not "\tabs\\.d\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-2008.c
new file mode 100644
index 000000000..2b0363abc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-2008.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mabs=2008" } */
+
+NOMIPS16 float
+fabsf_2008 (float f)
+{
+  return __builtin_fabsf (f);
+}
+
+/* { dg-final { scan-assembler "\tabs\\.s\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-legacy.c
new file mode 100644
index 000000000..7278f7d77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fabsf-legacy.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mabs=legacy" } */
+
+NOMIPS16 float
+fabsf_legacy (float f)
+{
+  return __builtin_fabsf (f);
+}
+
+/* { dg-final { scan-assembler-not "\tabs\\.s\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-1.c
new file mode 100644
index 000000000..edf4d70c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_add (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_add (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_add (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-10.c
new file mode 100644
index 000000000..ab353b6b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-10.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_and_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_and_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_and_and_fetch (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-11.c
new file mode 100644
index 000000000..30f6038b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-11.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_xor_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_xor_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_xor_and_fetch (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-12.c
new file mode 100644
index 000000000..855000df2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-12.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+/* { dg-message "note: '__sync_nand_and_fetch' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_nand_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_nand_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_nand_and_fetch (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-13.c
new file mode 100644
index 000000000..aa2d236f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-13.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_bool_compare_and_swap (z, 0, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_bool_compare_and_swap (z, 0, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_bool_compare_and_swap (z, 0, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-14.c
new file mode 100644
index 000000000..542e02f9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-14.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_val_compare_and_swap (z, 0, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_val_compare_and_swap (z, 0, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_val_compare_and_swap (z, 0, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-15.c
new file mode 100644
index 000000000..f44a725ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-15.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  int result;
+
+  result = __sync_lock_test_and_set (z, 42);
+  __sync_lock_release (z);
+  return result;
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  short result;
+
+  result = __sync_lock_test_and_set (z, 42);
+  __sync_lock_release (z);
+  return result;
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  char result;
+
+  result = __sync_lock_test_and_set (z, 42);
+  __sync_lock_release (z);
+  return result;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-2.c
new file mode 100644
index 000000000..88a591841
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z, int amt)
+{
+  return __sync_fetch_and_sub (z, amt);
+}
+
+NOMIPS16 short
+f2 (short *z, short amt)
+{
+  return __sync_fetch_and_sub (z, amt);
+}
+
+NOMIPS16 char
+f3 (char *z, char amt)
+{
+  return __sync_fetch_and_sub (z, amt);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-3.c
new file mode 100644
index 000000000..fbeeca10f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_or (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_or (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_or (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-4.c
new file mode 100644
index 000000000..344c6277b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_and (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_and (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_and (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-5.c
new file mode 100644
index 000000000..a775a6c0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-5.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_xor (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_xor (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_xor (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-6.c
new file mode 100644
index 000000000..62f8fdfb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-6.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+/* { dg-message "note: '__sync_fetch_and_nand' changed semantics in GCC 4.4" "" { target *-*-* } 0 } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_fetch_and_nand (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_fetch_and_nand (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_fetch_and_nand (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-7.c
new file mode 100644
index 000000000..635326c5c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-7.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_add_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_add_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_add_and_fetch (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-8.c
new file mode 100644
index 000000000..68978494d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-8.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z, int amt)
+{
+  return __sync_sub_and_fetch (z, amt);
+}
+
+NOMIPS16 short
+f2 (short *z, short amt)
+{
+  return __sync_sub_and_fetch (z, amt);
+}
+
+NOMIPS16 char
+f3 (char *z, char amt)
+{
+  return __sync_sub_and_fetch (z, amt);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-9.c
new file mode 100644
index 000000000..3d140b1bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r10000-9.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mfix-r10000" } */
+/* { dg-final { scan-assembler-times "\tbeql\t" 3 } } */
+
+NOMIPS16 int
+f1 (int *z)
+{
+  return __sync_or_and_fetch (z, 42);
+}
+
+NOMIPS16 short
+f2 (short *z)
+{
+  return __sync_or_and_fetch (z, 42);
+}
+
+NOMIPS16 char
+f3 (char *z)
+{
+  return __sync_or_and_fetch (z, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-1.c
new file mode 100644
index 000000000..5c812f256
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-1.c
@@ -0,0 +1,7 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -dp" } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef int int32_t;
+typedef int uint32_t;
+NOMIPS16 int32_t foo (int32_t x, int32_t y) { return x * y; }
+NOMIPS16 uint32_t bar (uint32_t x, uint32_t y) { return x * y; }
+/* { dg-final { scan-assembler-times "[concat {\tmult\t\$[45],\$[45][^\n]+mulsi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-10.c
new file mode 100644
index 000000000..7227bc8c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-10.c
@@ -0,0 +1,9 @@
+/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication
+   result to $2, which prevents the register allocators from storing the
+   multiplication result in $2.  */
+/* { dg-options "-mips3 -mfix-r4000 -mgp64 -EL -fno-split-wide-types -dp" } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef unsigned long long uint64_t;
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+NOMIPS16 uint128_t foo (uint64_t x, uint64_t y) { return (uint128_t) x * y; }
+/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-11.c
new file mode 100644
index 000000000..1ea7a7c40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-11.c
@@ -0,0 +1,6 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp" } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-skip-if "using DDIV gives a shorter sequence" { *-*-* } { "-Os" } { "" } } */
+typedef long long int64_t;
+NOMIPS16 int64_t foo (int64_t x) { return x / 11993; }
+/* { dg-final { scan-assembler "[concat {\tdmult\t\$4,\$[0-9]+[^\n]+smuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-12.c
new file mode 100644
index 000000000..a2afabbc7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-12.c
@@ -0,0 +1,6 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp" } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-skip-if "using DDIVU gives a shorter sequence" { *-*-* } { "-Os" } { "" } } */
+typedef unsigned long long uint64_t;
+NOMIPS16 uint64_t foo (uint64_t x) { return x / 11993; }
+/* { dg-final { scan-assembler "[concat {\tdmultu\t\$4,\$[0-9]+[^\n]+umuldi3_highpart[^\n]+\n\tmfhi\t\$[0-9]+\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-2.c
new file mode 100644
index 000000000..0261b16b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-2.c
@@ -0,0 +1,9 @@
+/* This test requires widening_mul */
+/* { dg-options "-mips1 -mfix-r4000 -dp -EB -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef int int32_t;
+typedef long long int64_t;
+NOMIPS16 int32_t foo (int32_t x, int32_t y) { return ((int64_t) x * y) >> 32; }
+/* ??? A highpart pattern would be a better choice, but we currently
+   don't use them.  */
+/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-3.c
new file mode 100644
index 000000000..195a9d10c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-3.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mips1 -mfix-r4000 -dp -EB" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+NOMIPS16 uint32_t foo (uint32_t x, uint32_t y) { return ((uint64_t) x * y) >> 32; }
+/* ??? A highpart pattern would be a better choice, but we currently
+   don't use them.  */
+/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-4.c
new file mode 100644
index 000000000..7a66182f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-4.c
@@ -0,0 +1,10 @@
+/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication
+   result to $2, which prevents the register allocators from storing the
+   multiplication result in $2.  */
+/* This test requires widening_mul */
+/* { dg-options "-mips1 -mfix-r4000 -fno-split-wide-types -dp -EL -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef int int32_t;
+typedef long long int64_t;
+NOMIPS16 int64_t foo (int32_t x, int32_t y) { return (int64_t) x * y; }
+/* { dg-final { scan-assembler "[concat {\tmult\t\$[45],\$[45][^\n]+mulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-5.c
new file mode 100644
index 000000000..0c0630800
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-5.c
@@ -0,0 +1,9 @@
+/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication
+   result to $2, which prevents the register allocators from storing the
+   multiplication result in $2.  */
+/* { dg-options "-mips1 -mfix-r4000 -fno-split-wide-types -dp -EL" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+NOMIPS16 uint64_t foo (uint32_t x, uint32_t y) { return (uint64_t) x * y; }
+/* { dg-final { scan-assembler "[concat {\tmultu\t\$[45],\$[45][^\n]+umulsidi3_32bit_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-6.c
new file mode 100644
index 000000000..9647a900c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-6.c
@@ -0,0 +1,7 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp" } */
+/* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef long long int64_t;
+typedef unsigned long long uint64_t;
+NOMIPS16 int64_t foo (int64_t x, int64_t y) { return x * y; }
+NOMIPS16 uint64_t bar (uint64_t x, uint64_t y) { return x * y; }
+/* { dg-final { scan-assembler-times "[concat {\tdmult\t\$[45],\$[45][^\n]+muldi3_r4000[^\n]+\n\tmflo\t\$2\n}]" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-7.c
new file mode 100644
index 000000000..ddba30383
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-7.c
@@ -0,0 +1,9 @@
+/* This test requires widening_mul */
+/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp -EB -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef long long int64_t;
+typedef int int128_t __attribute__((mode(TI)));
+NOMIPS16 int64_t foo (int64_t x, int64_t y) { return ((int128_t) x * y) >> 64; }
+/* ??? A highpart pattern would be a better choice, but we currently
+   don't use them.  */
+/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-8.c
new file mode 100644
index 000000000..4ae670622
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-8.c
@@ -0,0 +1,8 @@
+/* { dg-options "-march=r4000 -mfix-r4000 -mgp64 -dp -EB" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef unsigned long long uint64_t;
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+NOMIPS16 uint64_t foo (uint64_t x, uint64_t y) { return ((uint128_t) x * y) >> 64; }
+/* ??? A highpart pattern would be a better choice, but we currently
+   don't use them.  */
+/* { dg-final { scan-assembler "[concat {\tdmultu\t\$[45],\$[45][^\n]+umulditi3[^\n]+\n\tmflo\t\$3\n\tmfhi\t\$2\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-9.c
new file mode 100644
index 000000000..316715c59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-r4000-9.c
@@ -0,0 +1,10 @@
+/* ??? At the moment, lower-subreg.c decomposes the copy of the multiplication
+   result to $2, which prevents the register allocators from storing the
+   multiplication result in $2.  */
+/* This test requires widening_mul */
+/* { dg-options "-mips3 -mfix-r4000 -mgp64 -fno-split-wide-types -dp -EL -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+typedef long long int64_t;
+typedef int int128_t __attribute__((mode(TI)));
+NOMIPS16 int128_t foo (int64_t x, int64_t y) { return (int128_t) x * y; }
+/* { dg-final { scan-assembler "[concat {\tdmult\t\$[45],\$[45][^\n]+mulditi3_r4000[^\n]+\n\tmflo\t\$2\n\tmfhi\t\$3\n}]" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c
new file mode 100644
index 000000000..f4eb492e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=vr4130 -mfix-vr4130" } */
+NOMIPS16 unsigned int
+foo (unsigned int x, unsigned int y)
+{
+  return x % y;
+}
+/* { dg-final { scan-assembler "\tmacchi\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c
new file mode 100644
index 000000000..18708cb45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-2.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-march=vr4130 -mfix-vr4130" } */
+NOMIPS16 int foo (void) { int r; asm ("# foo" : "=l" (r)); return r; }
+/* { dg-final { scan-assembler "\tmacc\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c
new file mode 100644
index 000000000..d3399d10c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-3.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=vr4130 -mgp64 -mfix-vr4130" } */
+NOMIPS16 unsigned long long
+foo (unsigned long long x, unsigned long long y)
+{
+  return x % y;
+}
+/* { dg-final { scan-assembler "\tdmacchi\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c
new file mode 100644
index 000000000..8b307c6e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fix-vr4130-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=vr4130 -mgp64 -mfix-vr4130" } */
+NOMIPS16 long long
+foo (void)
+{
+  long long r;
+  asm ("# foo" : "=l" (r));
+  return r;
+}
+/* { dg-final { scan-assembler "\tdmacc\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c
new file mode 100644
index 000000000..810c82c2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-scalar-type.c
@@ -0,0 +1,218 @@
+/* Test scalar fixed-point instructions */
+/* { dg-do compile { target { fixed_point } } } */
+/* { dg-options "-mdspr2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\taddu\t" 10 } } */
+/* { dg-final { scan-assembler-times "\tsubu\t" 10 } } */
+/* { dg-final { scan-assembler "\taddu_s.qb\t" } } */
+/* { dg-final { scan-assembler-times "\taddu_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddq_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddq_s.w\t" 2 } } */
+/* { dg-final { scan-assembler "\tsubu_s.qb\t" } } */
+/* { dg-final { scan-assembler-times "\tsubu_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsubq_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsubq_s.w\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmulq_rs.ph\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmulq_rs.w\t" 1 } } */
+
+short _Fract non_sat_test1 (short _Fract a, short _Fract b)
+{
+  return a + b;
+}
+
+_Fract non_sat_test2 (_Fract a, _Fract b)
+{
+  return a + b;
+}
+
+long _Fract non_sat_test3 (long _Fract a, long _Fract b)
+{
+  return a + b;
+}
+
+unsigned short _Fract non_sat_test4 (unsigned short _Fract a,
+				     unsigned short _Fract b)
+{
+  return a + b;
+}
+
+unsigned _Fract non_sat_test5 (unsigned _Fract a, unsigned _Fract b)
+{
+  return a + b;
+}
+
+unsigned long _Fract non_sat_test6 (unsigned long _Fract a,
+				    unsigned long _Fract b)
+{
+  return a + b;
+}
+
+short _Accum non_sat_test7 (short _Accum a, short _Accum b)
+{
+  return a + b;
+}
+
+_Accum non_sat_test8 (_Accum a, _Accum b)
+{
+  return a + b;
+}
+
+unsigned short _Accum non_sat_test9 (unsigned short _Accum a,
+				     unsigned short _Accum b)
+{
+  return a + b;
+}
+
+unsigned _Accum non_sat_test10 (unsigned _Accum a, unsigned _Accum b)
+{
+  return a + b;
+}
+
+short _Fract non_sat_test11 (short _Fract a, short _Fract b)
+{
+  return a - b;
+}
+
+_Fract non_sat_test12 (_Fract a, _Fract b)
+{
+  return a - b;
+}
+
+long _Fract non_sat_test13 (long _Fract a, long _Fract b)
+{
+  return a - b;
+}
+
+unsigned short _Fract non_sat_test14 (unsigned short _Fract a,
+				      unsigned short _Fract b)
+{
+  return a - b;
+}
+
+unsigned _Fract non_sat_test15 (unsigned _Fract a, unsigned _Fract b)
+{
+  return a - b;
+}
+
+unsigned long _Fract non_sat_test16 (unsigned long _Fract a,
+				     unsigned long _Fract b)
+{
+  return a - b;
+}
+
+short _Accum non_sat_test17 (short _Accum a, short _Accum b)
+{
+  return a - b;
+}
+
+_Accum non_sat_test18 (_Accum a, _Accum b)
+{
+  return a - b;
+}
+
+unsigned short _Accum non_sat_test19 (unsigned short _Accum a,
+				      unsigned short _Accum b)
+{
+  return a - b;
+}
+
+unsigned _Accum non_sat_test20 (unsigned _Accum a, unsigned _Accum b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat unsigned short _Fract test1 (_Sat unsigned short _Fract a,
+					   _Sat unsigned short _Fract b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat unsigned _Fract test2 (_Sat unsigned  _Fract a,
+				     _Sat unsigned _Fract b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat unsigned short _Accum test3 (_Sat unsigned short _Accum a,
+					   _Sat unsigned short _Accum b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat _Fract test4 (_Sat _Fract a, _Sat _Fract b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat long _Fract test5 (_Sat long _Fract a, _Sat long _Fract b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat short _Accum test6 (_Sat short _Accum a, _Sat short _Accum b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat _Accum test7 (_Sat _Accum a, _Sat _Accum b)
+{
+  return a + b;
+}
+
+NOMIPS16 _Sat unsigned short _Fract test8 (_Sat unsigned short _Fract a,
+					   _Sat unsigned short _Fract b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat unsigned _Fract test9 (_Sat unsigned  _Fract a,
+				     _Sat unsigned _Fract b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat unsigned short _Accum test10 (_Sat unsigned short _Accum a,
+					    _Sat unsigned short _Accum b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat _Fract test11 (_Sat _Fract a, _Sat _Fract b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat long _Fract test12 (_Sat long _Fract a, _Sat long _Fract b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat short _Accum test13 (_Sat short _Accum a, _Sat short _Accum b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat _Accum test14 (_Sat _Accum a, _Sat _Accum b)
+{
+  return a - b;
+}
+
+NOMIPS16 _Sat _Fract test15 (_Sat _Fract a, _Sat _Fract b)
+{
+  return a * b;
+}
+
+NOMIPS16 _Sat long _Fract test16 (_Sat long _Fract a, _Sat long _Fract b)
+{
+  return a * b;
+}
+
+NOMIPS16 _Fract test17 (_Fract a, _Fract b)
+{
+  return a * b;
+}
+
+NOMIPS16 long _Fract test18 (long _Fract a, long _Fract b)
+{
+  return a * b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-vector-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-vector-type.c
new file mode 100644
index 000000000..ddd9660f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fixed-vector-type.c
@@ -0,0 +1,133 @@
+/* Test vector fixed-point instructions */
+/* { dg-do compile { target { fixed_point } } } */
+/* { dg-options "-mdspr2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\taddq_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsubq_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\taddu_s.qb\t" 1 } } */
+/* { dg-final { scan-assembler-times "\taddu_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tsubu_s.qb\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsubu_s.ph\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tmulq_rs.ph\t" 1 } } */
+
+typedef _Sat unsigned short _Fract sat_v4uqq __attribute__ ((vector_size(4)));
+typedef _Sat unsigned _Fract sat_v2uhq __attribute__ ((vector_size(4)));
+typedef _Sat unsigned short _Accum sat_v2uha __attribute__ ((vector_size(4)));
+typedef _Sat _Fract sat_v2hq __attribute__ ((vector_size(4)));
+typedef _Sat short _Accum sat_v2ha __attribute__ ((vector_size(4)));
+
+typedef unsigned short _Fract v4uqq __attribute__ ((vector_size(4)));
+typedef unsigned _Fract v2uhq __attribute__ ((vector_size(4)));
+typedef unsigned short _Accum v2uha __attribute__ ((vector_size(4)));
+typedef _Fract v2hq __attribute__ ((vector_size(4)));
+typedef short _Accum v2ha __attribute__ ((vector_size(4)));
+
+NOMIPS16 sat_v2hq test1 (sat_v2hq a, sat_v2hq b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v2ha test2 (sat_v2ha a, sat_v2ha b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v2hq test3 (sat_v2hq a, sat_v2hq b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v2ha test4 (sat_v2ha a, sat_v2ha b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v4uqq test5 (sat_v4uqq a, sat_v4uqq b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v2uhq test6 (sat_v2uhq a, sat_v2uhq b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v2uha test7 (sat_v2uha a, sat_v2uha b)
+{
+  return a + b;
+}
+
+NOMIPS16 sat_v4uqq test8 (sat_v4uqq a, sat_v4uqq b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v2uhq test9 (sat_v2uhq a, sat_v2uhq b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v2uha test10 (sat_v2uha a, sat_v2uha b)
+{
+  return a - b;
+}
+
+NOMIPS16 sat_v2hq test11 (sat_v2hq a, sat_v2hq b)
+{
+  return a * b;
+}
+
+NOMIPS16 v2hq test12 (v2hq a, v2hq b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2hq test13 (v2hq a, v2hq b)
+{
+  return a - b;
+}
+
+NOMIPS16 v2hq test14 (v2hq a, v2hq b)
+{
+  return a * b;
+}
+
+NOMIPS16 v2ha test15 (v2ha a, v2ha b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2ha test16 (v2ha a, v2ha b)
+{
+  return a - b;
+}
+
+NOMIPS16 v4uqq test17 (v4uqq a, v4uqq b)
+{
+  return a + b;
+}
+
+NOMIPS16 v4uqq test18 (v4uqq a, v4uqq b)
+{
+  return a - b;
+}
+
+NOMIPS16 v2uhq test19 (v2uhq a, v2uhq b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2uhq test20 (v2uhq a, v2uhq b)
+{
+  return a - b;
+}
+
+NOMIPS16 v2uha test21 (v2uha a, v2uha b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2uha test22 (v2uha a, v2uha b)
+{
+  return a - b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-2008.c
new file mode 100644
index 000000000..899268af7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-2008.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mabs=2008" } */
+
+NOMIPS16 double
+fneg_2008 (double d)
+{
+  return -d;
+}
+
+/* { dg-final { scan-assembler "\tneg\\.d\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-legacy.c
new file mode 100644
index 000000000..38f810cf9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fneg-legacy.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mabs=legacy" } */
+
+NOMIPS16 double
+fneg_legacy (double d)
+{
+  return -d;
+}
+
+/* { dg-final { scan-assembler-not "\tneg\\.d\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-2008.c
new file mode 100644
index 000000000..a64a6e693
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-2008.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mabs=2008" } */
+
+NOMIPS16 float
+fnegf_2008 (float f)
+{
+  return -f;
+}
+
+/* { dg-final { scan-assembler "\tneg\\.s\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-legacy.c
new file mode 100644
index 000000000..e628c2bd0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fnegf-legacy.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mabs=legacy" } */
+
+NOMIPS16 float
+fnegf_legacy (float f)
+{
+  return -f;
+}
+
+/* { dg-final { scan-assembler-not "\tneg\\.s\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c
new file mode 100644
index 000000000..c0594ff35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-1.c
@@ -0,0 +1,6 @@
+/* We used to use c.lt.fmt instead of c.ule.fmt here.  */
+/* { dg-options "-mhard-float" } */
+NOMIPS16 int f1 (float x, float y) { return __builtin_isless (x, y); }
+NOMIPS16 int f2 (double x, double y) { return __builtin_isless (x, y); }
+/* { dg-final { scan-assembler "\tc\\.ule\\.s\t" } } */
+/* { dg-final { scan-assembler "\tc\\.ule\\.d\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c
new file mode 100644
index 000000000..23d5cb0c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpcmp-2.c
@@ -0,0 +1,6 @@
+/* We used to use c.le.fmt instead of c.ult.fmt here.  */
+/* { dg-options "-mhard-float" } */
+NOMIPS16 int f1 (float x, float y) { return __builtin_islessequal (x, y); }
+NOMIPS16 int f2 (double x, double y) { return __builtin_islessequal (x, y); }
+/* { dg-final { scan-assembler "\tc\\.ult\\.s\t" } } */
+/* { dg-final { scan-assembler "\tc\\.ult\\.d\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-1.c
new file mode 100644
index 000000000..51a5f1723
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-1.c
@@ -0,0 +1,27 @@
+/* { dg-options "-mabi=32 -mhard-float -mips1 -EL" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 void
+foo (double d, double *x)
+{
+  *x = d;
+}
+
+NOMIPS16 double
+bar (double d)
+{
+  register double l1 asm ("$8") = d;
+  register double l2 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm volatile ("#foo" :: "f" (l2));
+  return l1;
+}
+
+/* { dg-final { scan-assembler "\tswc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tswc1\t\\\$f13,4\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f13\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f21\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f1\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-2.c
new file mode 100644
index 000000000..ffe614fcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-2.c
@@ -0,0 +1,27 @@
+/* { dg-options "-mabi=32 -mhard-float -mips1 -EB" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 void
+foo (double d, double *x)
+{
+  *x = d;
+}
+
+NOMIPS16 double
+bar (double d)
+{
+  register double l1 asm ("$8") = d;
+  register double l2 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm volatile ("#foo" :: "f" (l2));
+  return l1;
+}
+
+/* { dg-final { scan-assembler "\tswc1\t\\\$f12,4\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tswc1\t\\\$f13,0\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f13\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f21\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f1\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-3.c
new file mode 100644
index 000000000..80db0710c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-3.c
@@ -0,0 +1,19 @@
+/* { dg-options "-mabi=32 -mfp64 -EL" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 double
+foo (double d)
+{
+  register double l1 asm ("$8") = d;
+  register double l2 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm volatile ("#foo" :: "f" (l2));
+  return l1;
+}
+
+/* { dg-final { scan-assembler "\tmfc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmfhc1\t\\\$9,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmthc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$8,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tmthc1\t\\\$9,\\\$f0\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-4.c
new file mode 100644
index 000000000..d8f78586c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-4.c
@@ -0,0 +1,19 @@
+/* { dg-options "-mabi=32 -mfp64 -EB" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 double
+foo (double d)
+{
+  register double l1 asm ("$8") = d;
+  register double l2 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm volatile ("#foo" :: "f" (l2));
+  return l1;
+}
+
+/* { dg-final { scan-assembler "\tmfc1\t\\\$9,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmfhc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmthc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tmtc1\t\\\$9,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tmthc1\t\\\$8,\\\$f0\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-5.c
new file mode 100644
index 000000000..18d888049
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-5.c
@@ -0,0 +1,35 @@
+/* { dg-options "-mabi=64 -mhard-float -EL" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-require-effective-target mips_newabi_large_long_double } */
+
+NOMIPS16 void
+foo (long double d, long double *x)
+{
+  *x = d;
+}
+
+NOMIPS16 long double
+bar (long double d, long double *x)
+{
+  register long double l1 asm ("$8") = d;
+  register long double l2 asm ("$10") = x[1];
+  register long double l3 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm ("#foo" : "=d" (l2) : "d" (l2));
+  asm volatile ("#foo" :: "f" (l3));
+  x[1] = l1;
+  return l2;
+}
+
+/* { dg-final { scan-assembler "\tsdc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tsdc1\t\\\$f13,8\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmfc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tdmfc1\t\\\$9,\\\$f13\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$10,16\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$11,24\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f21\n" } } */
+/* { dg-final { scan-assembler "\tsd\t\\\$8,16\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tsd\t\\\$9,24\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$10,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$11,\\\$f2\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-6.c
new file mode 100644
index 000000000..30a83ec66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-6.c
@@ -0,0 +1,35 @@
+/* { dg-options "-mabi=64 -mhard-float -EB" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-require-effective-target mips_newabi_large_long_double } */
+
+NOMIPS16 void
+foo (long double d, long double *x)
+{
+  *x = d;
+}
+
+NOMIPS16 long double
+bar (long double d, long double *x)
+{
+  register long double l1 asm ("$8") = d;
+  register long double l2 asm ("$10") = x[1];
+  register long double l3 asm ("$f20") = 0.0;
+  asm ("#foo" : "=d" (l1) : "d" (l1));
+  asm ("#foo" : "=d" (l2) : "d" (l2));
+  asm volatile ("#foo" :: "f" (l3));
+  x[1] = l1;
+  return l2;
+}
+
+/* { dg-final { scan-assembler "\tsdc1\t\\\$f12,0\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tsdc1\t\\\$f13,8\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmfc1\t\\\$8,\\\$f12\n" } } */
+/* { dg-final { scan-assembler "\tdmfc1\t\\\$9,\\\$f13\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$10,16\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tld\t\\\$11,24\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f20\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$0,\\\$f21\n" } } */
+/* { dg-final { scan-assembler "\tsd\t\\\$8,16\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tsd\t\\\$9,24\\\(\\\$6\\\)\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$10,\\\$f0\n" } } */
+/* { dg-final { scan-assembler "\tdmtc1\t\\\$11,\\\$f2\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-7.c
new file mode 100644
index 000000000..56d7ccd63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-7.c
@@ -0,0 +1,36 @@
+/* { dg-options "(-mips16) -mabi=64 -EL" } */
+
+extern long double g[16];
+extern unsigned char gstuff[0x10000];
+
+NOMIPS16 long double
+foo (long double i1, long double i2, long double i3, long double i4,
+     long double *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = 1.0;
+  x[3] = g[4];
+  x[4] = *(long double *) (lstuff + 0x7fff);
+  return *(long double *) (gstuff + 0x7fff);
+}
+
+MIPS16 long double
+bar (long double i1, long double i2, long double i3, long double i4,
+     long double *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = 1.0;
+  x[3] = g[4];
+  x[4] = *(long double *) (lstuff + 0x7fff);
+  return *(long double *) (gstuff + 0x7fff);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-8.c
new file mode 100644
index 000000000..bf64193b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/fpr-moves-8.c
@@ -0,0 +1,36 @@
+/* { dg-options "(-mips16) -mabi=64 -EB" } */
+
+extern long double g[16];
+extern unsigned char gstuff[0x10000];
+
+NOMIPS16 long double
+foo (long double i1, long double i2, long double i3, long double i4,
+     long double *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = 1.0;
+  x[3] = g[4];
+  x[4] = *(long double *) (lstuff + 0x7fff);
+  return *(long double *) (gstuff + 0x7fff);
+}
+
+MIPS16 long double
+bar (long double i1, long double i2, long double i3, long double i4,
+     long double *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = 1.0;
+  x[3] = g[4];
+  x[4] = *(long double *) (lstuff + 0x7fff);
+  return *(long double *) (gstuff + 0x7fff);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c
new file mode 100644
index 000000000..74df7de14
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-1.c
@@ -0,0 +1,22 @@
+/* { dg-do preprocess } */
+/* { dg-options "isa>=2 -mgp32" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c
new file mode 100644
index 000000000..3a03ba349
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-2.c
@@ -0,0 +1,22 @@
+/* { dg-do preprocess } */
+/* { dg-options "-mgp64" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c
new file mode 100644
index 000000000..b47a2ceb2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-3.c
@@ -0,0 +1,21 @@
+/* { dg-options "isa>=2 -mgp32 -mips16" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c
new file mode 100644
index 000000000..78a12440a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/gcc-have-sync-compare-and-swap-4.c
@@ -0,0 +1,21 @@
+/* { dg-options "-mgp64 -mips16" } */
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
+#error nonono
+#endif
+
+#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+#error nonono
+#endif
+
+#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+#error nonono
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-1.c
new file mode 100644
index 000000000..46379b257
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-1.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mhard-float" } */
+
+NOMIPS16 unsigned int
+foo (void)
+{
+  return __builtin_mips_get_fcsr ();
+}
+
+/* { dg-final { scan-assembler "cfc1\t\\\$2,\\\$31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-2.c
new file mode 100644
index 000000000..29a97d309
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/get-fcsr-2.c
@@ -0,0 +1,10 @@
+/* { dg-options "-mhard-float (-mips16)" } */
+
+MIPS16 unsigned int
+foo (void)
+{
+  return __builtin_mips_get_fcsr ();
+}
+
+/* { dg-final { scan-assembler "__mips16_get_fcsr" } } */
+/* { dg-final { scan-assembler "cfc1\t\\\$2,\\\$31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-1.c
new file mode 100644
index 000000000..02bb8ae9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2 -mgp32" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tins\t" } } */
+
+struct
+{
+  unsigned int i : 2;
+  unsigned int j : 3;
+  unsigned int k : 4;
+} s;
+
+NOMIPS16 void
+foo (void)
+{
+  s.j = 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-2.c
new file mode 100644
index 000000000..916bc4b5e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/ins-2.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-meb isa_rev>=2 -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tins\t|\tdins\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsll\t|\tins\t" 1 } } */
+
+/* When inserting something into the top bit of a 32-bit structure,
+   we must make sure that the register remains properly sign-extended.
+   There are two ways of doing this:
+ 
+     - use purely 32-bit bit manipulations (a single INS, matched twice here).
+     - use a 64-bit bit manipulation (DINS), and sign-extend the result.  We
+     check for this extension using SLL.  */
+
+struct s
+{
+  int a:3;
+  int b:29;
+};
+
+NOMIPS16 void
+f (int a)
+{
+  struct s s;
+  asm volatile ("" : "=r"(s));
+  s.a = a;
+  asm volatile ("" :: "r"(s));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-1.c
new file mode 100644
index 000000000..77a554d21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-1.c
@@ -0,0 +1,38 @@
+/* { dg-options "(-mips16) -mgp64 -EL" } */
+
+typedef unsigned uint128_t __attribute__((mode(TI)));
+
+extern uint128_t g[16];
+extern unsigned char gstuff[0x10000];
+
+NOMIPS16 uint128_t
+foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4,
+     uint128_t *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL;
+  x[3] = g[4];
+  x[4] = *(uint128_t *) (lstuff + 0x7fff);
+  return *(uint128_t *) (gstuff + 0x7fff);
+}
+
+MIPS16 uint128_t
+bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4,
+     uint128_t *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL;
+  x[3] = g[4];
+  x[4] = *(uint128_t *) (lstuff + 0x7fff);
+  return *(uint128_t *) (gstuff + 0x7fff);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-2.c
new file mode 100644
index 000000000..930c36f9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/int-moves-2.c
@@ -0,0 +1,38 @@
+/* { dg-options "(-mips16) -mgp64 -EB" } */
+
+typedef unsigned uint128_t __attribute__((mode(TI)));
+
+extern uint128_t g[16];
+extern unsigned char gstuff[0x10000];
+
+NOMIPS16 uint128_t
+foo (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4,
+     uint128_t *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL;
+  x[3] = g[4];
+  x[4] = *(uint128_t *) (lstuff + 0x7fff);
+  return *(uint128_t *) (gstuff + 0x7fff);
+}
+
+MIPS16 uint128_t
+bar (uint128_t i1, uint128_t i2, uint128_t i3, uint128_t i4,
+     uint128_t *x, unsigned char *lstuff)
+{
+  g[0] = i1;
+  g[1] = i2;
+  g[2] = i3;
+  g[3] = i4;
+  x[0] = x[4];
+  x[1] = 0;
+  x[2] = ((uint128_t) 0x123456789abcdefULL << 64) | 0xaabbccddeeff1122ULL;
+  x[3] = g[4];
+  x[4] = *(uint128_t *) (lstuff + 0x7fff);
+  return *(uint128_t *) (gstuff + 0x7fff);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp
new file mode 100644
index 000000000..cfa64b192
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16-inter.exp
@@ -0,0 +1,72 @@
+# Copyright (C) 2007-2014 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# Run compatibility tests in which the "alt" compiler tries to force
+# MIPS16 mode.
+
+# We can only guarantee MIPS16 runtime support for certain targets.
+if { ![istarget mipsisa*-*-elf*] && ![istarget mips64vr*-*-elf*] } {
+    return
+}
+
+load_lib gcc-dg.exp
+
+# Check whether the flags are compatible with MIPS16 code generation.
+if { ![check_effective_target_mips16_attribute] } {
+    return
+}
+
+# Save the old value of CFLAGS_FOR_TARGET, if any.
+global saved_CFLAGS_FOR_TARGET
+if { [info exists CFLAGS_FOR_TARGET] } {
+    set saved_CFLAGS_FOR_TARGET $CFLAGS_FOR_TARGET
+} else {
+    unset -nocomplain saved_CFLAGS_FOR_TARGET
+}
+
+# The "alt" compiler is the normal compiler with an extra "-mips16" argument.
+proc compat-use-alt-compiler { } {
+    global saved_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET
+
+    if { [info exists saved_CFLAGS_FOR_TARGET] } {
+	set CFLAGS_FOR_TARGET [concat $saved_CFLAGS_FOR_TARGET "-mips16"]
+    } else {
+	set CFLAGS_FOR_TARGET "-mips16"
+    }
+}
+
+# Make the compiler under test the default.
+proc compat-use-tst-compiler { } {
+    global saved_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET
+
+    if { [info exists saved_CFLAGS_FOR_TARGET] } {
+	set CFLAGS_FOR_TARGET $saved_CFLAGS_FOR_TARGET
+    } else {
+	unset -nocomplain CFLAGS_FOR_TARGET
+    }
+}
+
+load_lib compat.exp
+
+gcc_init
+foreach src [lsort [find $srcdir/$subdir mips16_*_main.c]] {
+    if { [runtest_file_p $runtests $src] } {
+	compat-execute $src "mips16_inter" 1
+    }
+}
+compat-use-tst-compiler
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c
new file mode 100644
index 000000000..df18c7670
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_main.c
@@ -0,0 +1,10 @@
+extern void init (void);
+extern void test (void);
+
+int
+main (void)
+{
+  init ();
+  test ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c
new file mode 100644
index 000000000..38339cad8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_x.c
@@ -0,0 +1,176 @@
+#include <stdlib.h>
+
+/* All the function pointers are declared and initialized in
+   mips16-stubs-2.c.  */
+
+extern double the_result;
+
+extern void v0 (void);
+extern void v1 (float);
+extern void v5 (float, float);
+extern void v9 (float, double);
+extern void v2 (double);
+extern void v6 (double, float);
+extern void v10 (double, double);
+
+extern float f0 (void);
+extern float f1 (float);
+extern float f5 (float, float);
+extern float f9 (float, double);
+extern float f2 (double);
+extern float f6 (double, float);
+extern float f10 (double, double);
+
+extern double d0 (void);
+extern double d1 (float);
+extern double d5 (float, float);
+extern double d9 (float, double);
+extern double d2 (double);
+extern double d6 (double, float);
+extern double d10 (double, double);
+
+extern _Complex float cf0 (void);
+extern _Complex float cf1 (float);
+extern _Complex float cf5 (float, float);
+extern _Complex float cf9 (float, double);
+extern _Complex float cf2 (double);
+extern _Complex float cf6 (double, float);
+extern _Complex float cf10 (double, double);
+
+extern _Complex double cd0 (void);
+extern _Complex double cd1 (float);
+extern _Complex double cd5 (float, float);
+extern _Complex double cd9 (float, double);
+extern _Complex double cd2 (double);
+extern _Complex double cd6 (double, float);
+extern _Complex double cd10 (double, double);
+
+extern void (*pv0) (void);
+extern void (*pv1) (float);
+extern void (*pv5) (float, float);
+extern void (*pv9) (float, double);
+extern void (*pv2) (double);
+extern void (*pv6) (double, float);
+extern void (*pv10) (double, double);
+
+extern float (*pf0) (void);
+extern float (*pf1) (float);
+extern float (*pf5) (float, float);
+extern float (*pf9) (float, double);
+extern float (*pf2) (double);
+extern float (*pf6) (double, float);
+extern float (*pf10) (double, double);
+
+extern double (*pd0) (void);
+extern double (*pd1) (float);
+extern double (*pd5) (float, float);
+extern double (*pd9) (float, double);
+extern double (*pd2) (double);
+extern double (*pd6) (double, float);
+extern double (*pd10) (double, double);
+
+extern _Complex float (*pcf0) (void);
+extern _Complex float (*pcf1) (float);
+extern _Complex float (*pcf5) (float, float);
+extern _Complex float (*pcf9) (float, double);
+extern _Complex float (*pcf2) (double);
+extern _Complex float (*pcf6) (double, float);
+extern _Complex float (*pcf10) (double, double);
+
+extern _Complex double (*pcd0) (void);
+extern _Complex double (*pcd1) (float);
+extern _Complex double (*pcd5) (float, float);
+extern _Complex double (*pcd9) (float, double);
+extern _Complex double (*pcd2) (double);
+extern _Complex double (*pcd6) (double, float);
+extern _Complex double (*pcd10) (double, double);
+
+/* Macros for results checking.  */
+#define CHECK_RESULT(x, y) if ((x) != (y)) abort ()
+#define CHECK_VOID_RESULT(x, y)  CHECK_RESULT (((x), the_result), y)
+
+/* Call functions through pointers and check against expected results.  */
+void
+test (void)
+{
+
+  CHECK_VOID_RESULT (v0 (), 1.0);
+  CHECK_VOID_RESULT (v1 (1.0), 2.0);
+  CHECK_VOID_RESULT (v5 (5.0, 6.0), 12.0);
+  CHECK_VOID_RESULT (v9 (9.0, 10.0), 20.0);
+  CHECK_VOID_RESULT (v2 (2.0), 3.0);
+  CHECK_VOID_RESULT (v6 (6.0, 7.0), 14.0);
+  CHECK_VOID_RESULT (v10 (10.0, 11.0), 22.0);
+
+  CHECK_RESULT (f0 (), 1.0);
+  CHECK_RESULT (f1 (1.0), 2.0);
+  CHECK_RESULT (f5 (5.0, 6.0), 12.0);
+  CHECK_RESULT (f9 (9.0, 10.0), 20.0);
+  CHECK_RESULT (f2 (2.0), 3.0);
+  CHECK_RESULT (f6 (6.0, 7.0), 14.0);
+  CHECK_RESULT (f10 (10.0, 11.0), 22.0);
+
+  CHECK_RESULT (d0 (), 1.0);
+  CHECK_RESULT (d1 (1.0), 2.0);
+  CHECK_RESULT (d5 (5.0, 6.0), 12.0);
+  CHECK_RESULT (d9 (9.0, 10.0), 20.0);
+  CHECK_RESULT (d2 (2.0), 3.0);
+  CHECK_RESULT (d6 (6.0, 7.0), 14.0);
+  CHECK_RESULT (d10 (10.0, 11.0), 22.0);
+
+  CHECK_RESULT (cf0 (), 1.0 + 0.0i);
+  CHECK_RESULT (cf1 (1.0), 2.0 + 1.0i);
+  CHECK_RESULT (cf5 (5.0, 6.0), 12.0 + 5.0i);
+  CHECK_RESULT (cf9 (9.0, 10.0), 20.0 + 9.0i);
+  CHECK_RESULT (cf2 (2.0), 3.0 + 2.0i);
+  CHECK_RESULT (cf6 (6.0, 7.0), 14.0 + 6.0i);
+  CHECK_RESULT (cf10 (10.0, 11.0), 22.0 + 10.0i);
+
+  CHECK_RESULT (cd0 (), 1.0 + 0.0i);
+  CHECK_RESULT (cd1 (1.0), 2.0 + 1.0i);
+  CHECK_RESULT (cd5 (5.0, 6.0), 12.0 + 5.0i);
+  CHECK_RESULT (cd9 (9.0, 10.0), 20.0 + 9.0i);
+  CHECK_RESULT (cd2 (2.0), 3.0 + 2.0i);
+  CHECK_RESULT (cd6 (6.0, 7.0), 14.0 + 6.0i);
+  CHECK_RESULT (cd10 (10.0, 11.0), 22.0 + 10.0i);
+
+  CHECK_VOID_RESULT ((*pv0) (), 1.0);
+  CHECK_VOID_RESULT ((*pv1) (1.0), 2.0);
+  CHECK_VOID_RESULT ((*pv5) (5.0, 6.0), 12.0);
+  CHECK_VOID_RESULT ((*pv9) (9.0, 10.0), 20.0);
+  CHECK_VOID_RESULT ((*pv2) (2.0), 3.0);
+  CHECK_VOID_RESULT ((*pv6) (6.0, 7.0), 14.0);
+  CHECK_VOID_RESULT ((*pv10) (10.0, 11.0), 22.0);
+
+  CHECK_RESULT ((*pf0) (), 1.0);
+  CHECK_RESULT ((*pf1) (1.0), 2.0);
+  CHECK_RESULT ((*pf5) (5.0, 6.0), 12.0);
+  CHECK_RESULT ((*pf9) (9.0, 10.0), 20.0);
+  CHECK_RESULT ((*pf2) (2.0), 3.0);
+  CHECK_RESULT ((*pf6) (6.0, 7.0), 14.0);
+  CHECK_RESULT ((*pf10) (10.0, 11.0), 22.0);
+
+  CHECK_RESULT ((*pd0) (), 1.0);
+  CHECK_RESULT ((*pd1) (1.0), 2.0);
+  CHECK_RESULT ((*pd5) (5.0, 6.0), 12.0);
+  CHECK_RESULT ((*pd9) (9.0, 10.0), 20.0);
+  CHECK_RESULT ((*pd2) (2.0), 3.0);
+  CHECK_RESULT ((*pd6) (6.0, 7.0), 14.0);
+  CHECK_RESULT ((*pd10) (10.0, 11.0), 22.0);
+
+  CHECK_RESULT ((*pcf0) (), 1.0 + 0.0i);
+  CHECK_RESULT ((*pcf1) (1.0), 2.0 + 1.0i);
+  CHECK_RESULT ((*pcf5) (5.0, 6.0), 12.0 + 5.0i);
+  CHECK_RESULT ((*pcf9) (9.0, 10.0), 20.0 + 9.0i);
+  CHECK_RESULT ((*pcf2) (2.0), 3.0 + 2.0i);
+  CHECK_RESULT ((*pcf6) (6.0, 7.0), 14.0 + 6.0i);
+  CHECK_RESULT ((*pcf10) (10.0, 11.0), 22.0 + 10.0i);
+
+  CHECK_RESULT ((*pcd0) (), 1.0 + 0.0i);
+  CHECK_RESULT ((*pcd1) (1.0), 2.0 + 1.0i);
+  CHECK_RESULT ((*pcd5) (5.0, 6.0), 12.0 + 5.0i);
+  CHECK_RESULT ((*pcd9) (9.0, 10.0), 20.0 + 9.0i);
+  CHECK_RESULT ((*pcd2) (2.0), 3.0 + 2.0i);
+  CHECK_RESULT ((*pcd6) (6.0, 7.0), 14.0 + 6.0i);
+  CHECK_RESULT ((*pcd10) (10.0, 11.0), 22.0 + 10.0i);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c
new file mode 100644
index 000000000..b7a4d7f32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/inter/mips16_stubs_1_y.c
@@ -0,0 +1,133 @@
+/* All test functions return the sum of arguments, plus 1.
+   Void-returning functions put the result in the_result.
+   Complex-returning functions return their signature number as the
+   (constant) imaginary part of the result.  */
+
+double the_result;
+
+void v0 (void) 			{ the_result = 1.0; }
+void v1 (float x)		{ the_result = 1.0 + x; }
+void v5 (float x, float y) 	{ the_result = 1.0 + x + y; }
+void v9 (float x, double y) 	{ the_result = 1.0 + x + y; }
+void v2 (double x)		{ the_result = 1.0 + x; }
+void v6 (double x, float y)	{ the_result = 1.0 + x + y; }
+void v10 (double x, double y)  	{ the_result = 1.0 + x + y; }
+
+float f0 (void) 		{ return 1.0; }
+float f1 (float x)		{ return 1.0 + x; }
+float f5 (float x, float y) 	{ return 1.0 + x + y; }
+float f9 (float x, double y) 	{ return 1.0 + x + y; }
+float f2 (double x)		{ return 1.0 + x; }
+float f6 (double x, float y)	{ return 1.0 + x + y; }
+float f10 (double x, double y)	{ return 1.0 + x + y; }
+
+double d0 (void) 		{ return 1.0; }
+double d1 (float x)		{ return 1.0 + x; }
+double d5 (float x, float y) 	{ return 1.0 + x + y; }
+double d9 (float x, double y) 	{ return 1.0 + x + y; }
+double d2 (double x)		{ return 1.0 + x; }
+double d6 (double x, float y)	{ return 1.0 + x + y; }
+double d10 (double x, double y) { return 1.0 + x + y; }
+
+_Complex float cf0 (void) 			{ return 1.0 + 0.0i; }
+_Complex float cf1 (float x)			{ return 1.0 + x + 1.0i; }
+_Complex float cf5 (float x, float y) 		{ return 1.0 + x + y + 5.0i; }
+_Complex float cf9 (float x, double y) 		{ return 1.0 + x + y + 9.0i; }
+_Complex float cf2 (double x)			{ return 1.0 + x + 2.0i; }
+_Complex float cf6 (double x, float y)		{ return 1.0 + x + y + 6.0i; }
+_Complex float cf10 (double x, double y)	{ return 1.0 + x + y + 10.0i; }
+
+_Complex double cd0 (void) 			{ return 1.0 + 0.0i; }
+_Complex double cd1 (float x)			{ return 1.0 + x + 1.0i; }
+_Complex double cd5 (float x, float y) 		{ return 1.0 + x + y + 5.0i; }
+_Complex double cd9 (float x, double y) 	{ return 1.0 + x + y + 9.0i; }
+_Complex double cd2 (double x)			{ return 1.0 + x + 2.0i; }
+_Complex double cd6 (double x, float y)		{ return 1.0 + x + y + 6.0i; }
+_Complex double cd10 (double x, double y)	{ return 1.0 + x + y + 10.0i; }
+
+
+/* Declare and initialize all the pointer-to-function variables.  */
+
+void (*pv0) (void);
+void (*pv1) (float);
+void (*pv5) (float, float);
+void (*pv9) (float, double);
+void (*pv2) (double);
+void (*pv6) (double, float);
+void (*pv10) (double, double);
+
+float (*pf0) (void);
+float (*pf1) (float);
+float (*pf5) (float, float);
+float (*pf9) (float, double);
+float (*pf2) (double);
+float (*pf6) (double, float);
+float (*pf10) (double, double);
+
+double (*pd0) (void);
+double (*pd1) (float);
+double (*pd5) (float, float);
+double (*pd9) (float, double);
+double (*pd2) (double);
+double (*pd6) (double, float);
+double (*pd10) (double, double);
+
+_Complex float (*pcf0) (void);
+_Complex float (*pcf1) (float);
+_Complex float (*pcf5) (float, float);
+_Complex float (*pcf9) (float, double);
+_Complex float (*pcf2) (double);
+_Complex float (*pcf6) (double, float);
+_Complex float (*pcf10) (double, double);
+
+_Complex double (*pcd0) (void);
+_Complex double (*pcd1) (float);
+_Complex double (*pcd5) (float, float);
+_Complex double (*pcd9) (float, double);
+_Complex double (*pcd2) (double);
+_Complex double (*pcd6) (double, float);
+_Complex double (*pcd10) (double, double);
+
+void
+init (void)
+{
+  pv0 = v0;
+  pv1 = v1;
+  pv5 = v5;
+  pv9 = v9;
+  pv2 = v2;
+  pv6 = v6;
+  pv10 = v10;
+
+  pf0 = f0;
+  pf1 = f1;
+  pf5 = f5;
+  pf9 = f9;
+  pf2 = f2;
+  pf6 = f6;
+  pf10 = f10;
+
+  pd0 = d0;
+  pd1 = d1;
+  pd5 = d5;
+  pd9 = d9;
+  pd2 = d2;
+  pd6 = d6;
+  pd10 = d10;
+
+  pcf0 = cf0;
+  pcf1 = cf1;
+  pcf5 = cf5;
+  pcf9 = cf9;
+  pcf2 = cf2;
+  pcf6 = cf6;
+  pcf10 = cf10;
+
+  pcd0 = cd0;
+  pcd1 = cd1;
+  pcd5 = cd5;
+  pcd9 = cd9;
+  pcd2 = cd2;
+  pcd6 = cd6;
+  pcd10 = cd10;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c
new file mode 100644
index 000000000..9ab32bf5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-2.c
@@ -0,0 +1,15 @@
+/* Make sure that we emit .cfa_restore notes for LO and HI.  */
+/* { dg-options "-mips32r2 -msoft-float -g" } */
+/* { dg-skip-if "forbidding a frame pointer makes this a code quallity test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 64\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 65\n" } } */
+/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa( |\t)" } } */
+/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa_register( |\t)" } } */
+
+extern void f (void);
+
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set))
+v1 (void)
+{
+  f ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c
new file mode 100644
index 000000000..298e04677
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler-3.c
@@ -0,0 +1,34 @@
+/* Make sure that we emit .cfa_restore notes for LO, HI and GPRs.  */
+/* { dg-options "-mips32r2 -msoft-float -g" } */
+/* { dg-skip-if "forbidding a frame pointer makes this a code quallity test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 1\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 2\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 3\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 4\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 5\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 6\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 7\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 8\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 9\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 10\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 11\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 12\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 13\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 14\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 15\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 24\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 25\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 31\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 64\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_restore 65\n" } } */
+/* { dg-final { scan-assembler "\t\\\.cfi_def_cfa_offset 0\n" } } */
+/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa( |\t)" } } */
+/* { dg-final { scan-assembler-not "\\\.cfi_def_cfa_register( |\t)" } } */
+
+extern void f (void);
+
+NOMIPS16 void __attribute__ ((interrupt))
+v1 (void)
+{
+  f ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler.c
new file mode 100644
index 000000000..073c772ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/interrupt_handler.c
@@ -0,0 +1,23 @@
+/* Test attributes for interrupt handlers */
+/* { dg-do assemble } */
+/* { dg-options "-mips32r2 -msoft-float" } */
+
+void f () { }
+
+NOMIPS16 void __attribute__ ((interrupt)) v0 () { }
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set)) v1 () { }
+NOMIPS16 void __attribute__ ((interrupt, keep_interrupts_masked)) v2 () { }
+NOMIPS16 void __attribute__ ((interrupt, use_debug_exception_return)) v3 () { }
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, keep_interrupts_masked)) v4 () { }
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, use_debug_exception_return)) v5 () { }
+NOMIPS16 void __attribute__ ((interrupt, keep_interrupts_masked, use_debug_exception_return)) v6 () { }
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, keep_interrupts_masked, use_debug_exception_return)) v7 () { }
+
+NOMIPS16 void __attribute__ ((interrupt)) w0 () { t(); }
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set)) w1 () { t(); }
+NOMIPS16 void __attribute__ ((interrupt, keep_interrupts_masked)) w2 () { t(); }
+NOMIPS16 void __attribute__ ((interrupt, use_debug_exception_return)) w3 () { t(); }
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, keep_interrupts_masked)) w4 () { t(); }
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, use_debug_exception_return)) w5 () { t(); }
+NOMIPS16 void __attribute__ ((interrupt, keep_interrupts_masked, use_debug_exception_return)) w6 () { t(); }
+NOMIPS16 void __attribute__ ((interrupt, use_shadow_register_set, keep_interrupts_masked, use_debug_exception_return)) w7 () { t(); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/lazy-binding-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/lazy-binding-1.c
new file mode 100644
index 000000000..a30594840
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/lazy-binding-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-mshared -mexplicit-relocs -fno-delayed-branch -fno-unroll-loops" } */
+/* We can load into something other than $25 when not optimizing,
+   then immediately move into $25.  */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void bar (void);
+
+NOMIPS16 void
+foo (int n)
+{
+  while (n--)
+    {
+      bar ();
+      bar ();
+    }
+}
+
+/* There should be exactly five uses of $25: one to set up $gp, two to
+   load the address of bar (), and two to call it.  */
+/* { dg-final { scan-assembler-times "\tl.\t\\\$25,%call16\\\(bar\\\)" 2 } } */
+/* { dg-final { scan-assembler-times "\tjalrs?\t\\\$25" 2 } } */
+/* { dg-final { scan-assembler "(\\\$28,|\t.cpload\t)\\\$25" } } */
+/* { dg-final { scan-assembler-times "\\\$25" 5 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/long-calls-pg.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/long-calls-pg.c
new file mode 100644
index 000000000..5ccfe5149
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/long-calls-pg.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=32 -pg -mno-abicalls -mlong-calls" } */
+/* { dg-final { scan-assembler-not "\tjal\t_mcount" } } */
+NOMIPS16 void
+foo (void)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c
new file mode 100644
index 000000000..2efc3ef3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-1.c
@@ -0,0 +1,16 @@
+/* { dg-options "isa=loongson" } */
+
+typedef int st;
+typedef unsigned int ut;
+
+NOMIPS16 st smul (st x, st y) { return x * y; }
+NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; }
+
+NOMIPS16 ut umul (ut x, ut y) { return x * y; }
+NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; }
+
+/* { dg-final { scan-assembler-times "\tmultu.g\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tdivu.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmodu.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdiv.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tmod.g\t" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c
new file mode 100644
index 000000000..07523aa4a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-muldiv-2.c
@@ -0,0 +1,16 @@
+/* { dg-options "isa=loongson -mgp64" } */
+
+typedef long long st;
+typedef unsigned long long ut;
+
+NOMIPS16 st smul (st x, st y) { return x * y; }
+NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; }
+
+NOMIPS16 ut umul (ut x, ut y) { return x * y; }
+NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; }
+
+/* { dg-final { scan-assembler-times "\tdmultu.g\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tddivu.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdmodu.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tddiv.g\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tdmod.g\t" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c
new file mode 100644
index 000000000..778d73981
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c
@@ -0,0 +1,37 @@
+/* Test case for SHIFT_COUNT_TRUNCATED on Loongson.  */
+
+/* { dg-do run } */
+/* loongson.h does not handle or check for MIPS16ness.  There doesn't
+   seem any good reason for it to, given that the Loongson processors
+   do not support MIPS16.  */
+/* { dg-options "isa=loongson -mhard-float -mno-mips16" } */
+/* See PR 52155.  */
+/* { dg-options "isa=loongson -mhard-float -mno-mips16 -mlong64" { mips*-*-elf* && ilp32 } } */
+
+#include "loongson.h"
+#include <assert.h>
+
+typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t;
+
+void
+main1 (int shift)
+{
+  int32x2_encap_t s;
+  int32x2_encap_t r;
+
+  s.a[0] = 0xffffffff;
+  s.a[1] = 0xffffffff;
+  /* Loongson SIMD use low-order 7 bits to specify the shift amount.
+     Thus V2SI << 0x40 == 0.  The below expression 'shift & 0x3f' will be
+     mis-optimized as 'shift', if SHIFT_COUNT_TRUNCATED is nonzero.  */
+  r.v = psllw_s (s.v, (shift & 0x3f));
+  assert (r.a[0] == 0xffffffff);
+  assert (r.a[1] == 0xffffffff);
+}
+
+int
+main (void)
+{
+  main1 (0x40);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-simd.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-simd.c
new file mode 100644
index 000000000..ae3565f47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson-simd.c
@@ -0,0 +1,1966 @@
+/* Test cases for ST Microelectronics Loongson-2E/2F SIMD intrinsics.
+   Copyright (C) 2008 Free Software Foundation, Inc.
+   Contributed by CodeSourcery.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+/* loongson.h does not handle or check for MIPS16ness.  There doesn't
+   seem any good reason for it to, given that the Loongson processors
+   do not support MIPS16.  */
+/* { dg-options "isa=loongson -mhard-float -mno-mips16 -flax-vector-conversions" } */
+
+#include "loongson.h"
+#include <stdio.h>
+#include <stdint.h>
+#include <assert.h>
+#include <limits.h>
+
+typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t;
+typedef union { int16x4_t v; int16_t a[4]; } int16x4_encap_t;
+typedef union { int8x8_t v; int8_t a[8]; } int8x8_encap_t;
+typedef union { uint32x2_t v; uint32_t a[2]; } uint32x2_encap_t;
+typedef union { uint16x4_t v; uint16_t a[4]; } uint16x4_encap_t;
+typedef union { uint8x8_t v; uint8_t a[8]; } uint8x8_encap_t;
+
+#define UINT16x4_MAX USHRT_MAX
+#define UINT8x8_MAX UCHAR_MAX
+#define INT8x8_MAX SCHAR_MAX
+#define INT16x4_MAX SHRT_MAX
+#define INT32x2_MAX INT_MAX
+
+static void test_packsswh (void)
+{
+  int32x2_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = INT16x4_MAX - 2;
+  s.a[1] = INT16x4_MAX - 1;
+  t.a[0] = INT16x4_MAX;
+  t.a[1] = INT16x4_MAX + 1;
+  r.v = packsswh (s.v, t.v);
+  assert (r.a[0] == INT16x4_MAX - 2);
+  assert (r.a[1] == INT16x4_MAX - 1);
+  assert (r.a[2] == INT16x4_MAX);
+  assert (r.a[3] == INT16x4_MAX);
+}
+
+static void test_packsshb (void)
+{
+  int16x4_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = INT8x8_MAX - 6;
+  s.a[1] = INT8x8_MAX - 5;
+  s.a[2] = INT8x8_MAX - 4;
+  s.a[3] = INT8x8_MAX - 3;
+  t.a[0] = INT8x8_MAX - 2;
+  t.a[1] = INT8x8_MAX - 1;
+  t.a[2] = INT8x8_MAX;
+  t.a[3] = INT8x8_MAX + 1;
+  r.v = packsshb (s.v, t.v);
+  assert (r.a[0] == INT8x8_MAX - 6);
+  assert (r.a[1] == INT8x8_MAX - 5);
+  assert (r.a[2] == INT8x8_MAX - 4);
+  assert (r.a[3] == INT8x8_MAX - 3);
+  assert (r.a[4] == INT8x8_MAX - 2);
+  assert (r.a[5] == INT8x8_MAX - 1);
+  assert (r.a[6] == INT8x8_MAX);
+  assert (r.a[7] == INT8x8_MAX);
+}
+
+static void test_packushb (void)
+{
+  uint16x4_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = UINT8x8_MAX - 6;
+  s.a[1] = UINT8x8_MAX - 5;
+  s.a[2] = UINT8x8_MAX - 4;
+  s.a[3] = UINT8x8_MAX - 3;
+  t.a[0] = UINT8x8_MAX - 2;
+  t.a[1] = UINT8x8_MAX - 1;
+  t.a[2] = UINT8x8_MAX;
+  t.a[3] = UINT8x8_MAX + 1;
+  r.v = packushb (s.v, t.v);
+  assert (r.a[0] == UINT8x8_MAX - 6);
+  assert (r.a[1] == UINT8x8_MAX - 5);
+  assert (r.a[2] == UINT8x8_MAX - 4);
+  assert (r.a[3] == UINT8x8_MAX - 3);
+  assert (r.a[4] == UINT8x8_MAX - 2);
+  assert (r.a[5] == UINT8x8_MAX - 1);
+  assert (r.a[6] == UINT8x8_MAX);
+  assert (r.a[7] == UINT8x8_MAX);
+}
+
+static void test_paddw_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  t.a[0] = 3;
+  t.a[1] = 4;
+  r.v = paddw_u (s.v, t.v);
+  assert (r.a[0] == 4);
+  assert (r.a[1] == 6);
+}
+
+static void test_paddw_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = -2;
+  s.a[1] = -1;
+  t.a[0] = 3;
+  t.a[1] = 4;
+  r.v = paddw_s (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 3);
+}
+
+static void test_paddh_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  t.a[0] = 5;
+  t.a[1] = 6;
+  t.a[2] = 7;
+  t.a[3] = 8;
+  r.v = paddh_u (s.v, t.v);
+  assert (r.a[0] == 6);
+  assert (r.a[1] == 8);
+  assert (r.a[2] == 10);
+  assert (r.a[3] == 12);
+}
+
+static void test_paddh_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -10;
+  s.a[1] = -20;
+  s.a[2] = -30;
+  s.a[3] = -40;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  r.v = paddh_s (s.v, t.v);
+  assert (r.a[0] == -9);
+  assert (r.a[1] == -18);
+  assert (r.a[2] == -27);
+  assert (r.a[3] == -36);
+}
+
+static void test_paddb_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  s.a[4] = 5;
+  s.a[5] = 6;
+  s.a[6] = 7;
+  s.a[7] = 8;
+  t.a[0] = 9;
+  t.a[1] = 10;
+  t.a[2] = 11;
+  t.a[3] = 12;
+  t.a[4] = 13;
+  t.a[5] = 14;
+  t.a[6] = 15;
+  t.a[7] = 16;
+  r.v = paddb_u (s.v, t.v);
+  assert (r.a[0] == 10);
+  assert (r.a[1] == 12);
+  assert (r.a[2] == 14);
+  assert (r.a[3] == 16);
+  assert (r.a[4] == 18);
+  assert (r.a[5] == 20);
+  assert (r.a[6] == 22);
+  assert (r.a[7] == 24);
+}
+
+static void test_paddb_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -10;
+  s.a[1] = -20;
+  s.a[2] = -30;
+  s.a[3] = -40;
+  s.a[4] = -50;
+  s.a[5] = -60;
+  s.a[6] = -70;
+  s.a[7] = -80;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  t.a[4] = 5;
+  t.a[5] = 6;
+  t.a[6] = 7;
+  t.a[7] = 8;
+  r.v = paddb_s (s.v, t.v);
+  assert (r.a[0] == -9);
+  assert (r.a[1] == -18);
+  assert (r.a[2] == -27);
+  assert (r.a[3] == -36);
+  assert (r.a[4] == -45);
+  assert (r.a[5] == -54);
+  assert (r.a[6] == -63);
+  assert (r.a[7] == -72);
+}
+
+static void test_paddd_u (void)
+{
+  uint64_t d = 123456;
+  uint64_t e = 789012;
+  uint64_t r;
+  r = paddd_u (d, e);
+  assert (r == 912468);
+}
+
+static void test_paddd_s (void)
+{
+  int64_t d = 123456;
+  int64_t e = -789012;
+  int64_t r;
+  r = paddd_s (d, e);
+  assert (r == -665556);
+}
+
+static void test_paddsh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 0;
+  s.a[2] = 1;
+  s.a[3] = 2;
+  t.a[0] = INT16x4_MAX;
+  t.a[1] = INT16x4_MAX;
+  t.a[2] = INT16x4_MAX;
+  t.a[3] = INT16x4_MAX;
+  r.v = paddsh (s.v, t.v);
+  assert (r.a[0] == INT16x4_MAX - 1);
+  assert (r.a[1] == INT16x4_MAX);
+  assert (r.a[2] == INT16x4_MAX);
+  assert (r.a[3] == INT16x4_MAX);
+}
+
+static void test_paddsb (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -6;
+  s.a[1] = -5;
+  s.a[2] = -4;
+  s.a[3] = -3;
+  s.a[4] = -2;
+  s.a[5] = -1;
+  s.a[6] = 0;
+  s.a[7] = 1;
+  t.a[0] = INT8x8_MAX;
+  t.a[1] = INT8x8_MAX;
+  t.a[2] = INT8x8_MAX;
+  t.a[3] = INT8x8_MAX;
+  t.a[4] = INT8x8_MAX;
+  t.a[5] = INT8x8_MAX;
+  t.a[6] = INT8x8_MAX;
+  t.a[7] = INT8x8_MAX;
+  r.v = paddsb (s.v, t.v);
+  assert (r.a[0] == INT8x8_MAX - 6);
+  assert (r.a[1] == INT8x8_MAX - 5);
+  assert (r.a[2] == INT8x8_MAX - 4);
+  assert (r.a[3] == INT8x8_MAX - 3);
+  assert (r.a[4] == INT8x8_MAX - 2);
+  assert (r.a[5] == INT8x8_MAX - 1);
+  assert (r.a[6] == INT8x8_MAX);
+  assert (r.a[7] == INT8x8_MAX);
+}
+
+static void test_paddush (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 0;
+  s.a[1] = 1;
+  s.a[2] = 0;
+  s.a[3] = 1;
+  t.a[0] = UINT16x4_MAX;
+  t.a[1] = UINT16x4_MAX;
+  t.a[2] = UINT16x4_MAX;
+  t.a[3] = UINT16x4_MAX;
+  r.v = paddush (s.v, t.v);
+  assert (r.a[0] == UINT16x4_MAX);
+  assert (r.a[1] == UINT16x4_MAX);
+  assert (r.a[2] == UINT16x4_MAX);
+  assert (r.a[3] == UINT16x4_MAX);
+}
+
+static void test_paddusb (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 0;
+  s.a[1] = 1;
+  s.a[2] = 0;
+  s.a[3] = 1;
+  s.a[4] = 0;
+  s.a[5] = 1;
+  s.a[6] = 0;
+  s.a[7] = 1;
+  t.a[0] = UINT8x8_MAX;
+  t.a[1] = UINT8x8_MAX;
+  t.a[2] = UINT8x8_MAX;
+  t.a[3] = UINT8x8_MAX;
+  t.a[4] = UINT8x8_MAX;
+  t.a[5] = UINT8x8_MAX;
+  t.a[6] = UINT8x8_MAX;
+  t.a[7] = UINT8x8_MAX;
+  r.v = paddusb (s.v, t.v);
+  assert (r.a[0] == UINT8x8_MAX);
+  assert (r.a[1] == UINT8x8_MAX);
+  assert (r.a[2] == UINT8x8_MAX);
+  assert (r.a[3] == UINT8x8_MAX);
+  assert (r.a[4] == UINT8x8_MAX);
+  assert (r.a[5] == UINT8x8_MAX);
+  assert (r.a[6] == UINT8x8_MAX);
+  assert (r.a[7] == UINT8x8_MAX);
+}
+
+static void test_pandn_ud (void)
+{
+  uint64_t d1 = 0x0000ffff0000ffffull;
+  uint64_t d2 = 0x0000ffff0000ffffull;
+  uint64_t r;
+  r = pandn_ud (d1, d2);
+  assert (r == 0);
+}
+
+static void test_pandn_sd (void)
+{
+  int64_t d1 = (int64_t) 0x0000000000000000ull;
+  int64_t d2 = (int64_t) 0xfffffffffffffffeull;
+  int64_t r;
+  r = pandn_sd (d1, d2);
+  assert (r == -2);
+}
+
+static void test_pandn_uw (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 0xffffffff;
+  s.a[1] = 0x00000000;
+  t.a[0] = 0x00000000;
+  t.a[1] = 0xffffffff;
+  r.v = pandn_uw (s.v, t.v);
+  assert (r.a[0] == 0x00000000);
+  assert (r.a[1] == 0xffffffff);
+}
+
+static void test_pandn_sw (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = 0xffffffff;
+  s.a[1] = 0x00000000;
+  t.a[0] = 0xffffffff;
+  t.a[1] = 0xfffffffe;
+  r.v = pandn_sw (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -2);
+}
+
+static void test_pandn_uh (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 0xffff;
+  s.a[1] = 0x0000;
+  s.a[2] = 0xffff;
+  s.a[3] = 0x0000;
+  t.a[0] = 0x0000;
+  t.a[1] = 0xffff;
+  t.a[2] = 0x0000;
+  t.a[3] = 0xffff;
+  r.v = pandn_uh (s.v, t.v);
+  assert (r.a[0] == 0x0000);
+  assert (r.a[1] == 0xffff);
+  assert (r.a[2] == 0x0000);
+  assert (r.a[3] == 0xffff);
+}
+
+static void test_pandn_sh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = 0xffff;
+  s.a[1] = 0x0000;
+  s.a[2] = 0xffff;
+  s.a[3] = 0x0000;
+  t.a[0] = 0xffff;
+  t.a[1] = 0xfffe;
+  t.a[2] = 0xffff;
+  t.a[3] = 0xfffe;
+  r.v = pandn_sh (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -2);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -2);
+}
+
+static void test_pandn_ub (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 0xff;
+  s.a[1] = 0x00;
+  s.a[2] = 0xff;
+  s.a[3] = 0x00;
+  s.a[4] = 0xff;
+  s.a[5] = 0x00;
+  s.a[6] = 0xff;
+  s.a[7] = 0x00;
+  t.a[0] = 0x00;
+  t.a[1] = 0xff;
+  t.a[2] = 0x00;
+  t.a[3] = 0xff;
+  t.a[4] = 0x00;
+  t.a[5] = 0xff;
+  t.a[6] = 0x00;
+  t.a[7] = 0xff;
+  r.v = pandn_ub (s.v, t.v);
+  assert (r.a[0] == 0x00);
+  assert (r.a[1] == 0xff);
+  assert (r.a[2] == 0x00);
+  assert (r.a[3] == 0xff);
+  assert (r.a[4] == 0x00);
+  assert (r.a[5] == 0xff);
+  assert (r.a[6] == 0x00);
+  assert (r.a[7] == 0xff);
+}
+
+static void test_pandn_sb (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = 0xff;
+  s.a[1] = 0x00;
+  s.a[2] = 0xff;
+  s.a[3] = 0x00;
+  s.a[4] = 0xff;
+  s.a[5] = 0x00;
+  s.a[6] = 0xff;
+  s.a[7] = 0x00;
+  t.a[0] = 0xff;
+  t.a[1] = 0xfe;
+  t.a[2] = 0xff;
+  t.a[3] = 0xfe;
+  t.a[4] = 0xff;
+  t.a[5] = 0xfe;
+  t.a[6] = 0xff;
+  t.a[7] = 0xfe;
+  r.v = pandn_sb (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -2);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -2);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == -2);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == -2);
+}
+
+static void test_pavgh (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  t.a[0] = 5;
+  t.a[1] = 6;
+  t.a[2] = 7;
+  t.a[3] = 8;
+  r.v = pavgh (s.v, t.v);
+  assert (r.a[0] == 3);
+  assert (r.a[1] == 4);
+  assert (r.a[2] == 5);
+  assert (r.a[3] == 6);
+}
+
+static void test_pavgb (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  s.a[4] = 1;
+  s.a[5] = 2;
+  s.a[6] = 3;
+  s.a[7] = 4;
+  t.a[0] = 5;
+  t.a[1] = 6;
+  t.a[2] = 7;
+  t.a[3] = 8;
+  t.a[4] = 5;
+  t.a[5] = 6;
+  t.a[6] = 7;
+  t.a[7] = 8;
+  r.v = pavgb (s.v, t.v);
+  assert (r.a[0] == 3);
+  assert (r.a[1] == 4);
+  assert (r.a[2] == 5);
+  assert (r.a[3] == 6);
+  assert (r.a[4] == 3);
+  assert (r.a[5] == 4);
+  assert (r.a[6] == 5);
+  assert (r.a[7] == 6);
+}
+
+static void test_pcmpeqw_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 43;
+  t.a[0] = 43;
+  t.a[1] = 43;
+  r.v = pcmpeqw_u (s.v, t.v);
+  assert (r.a[0] == 0x00000000);
+  assert (r.a[1] == 0xffffffff);
+}
+
+static void test_pcmpeqh_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 43;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  t.a[0] = 43;
+  t.a[1] = 43;
+  t.a[2] = 43;
+  t.a[3] = 43;
+  r.v = pcmpeqh_u (s.v, t.v);
+  assert (r.a[0] == 0x0000);
+  assert (r.a[1] == 0xffff);
+  assert (r.a[2] == 0x0000);
+  assert (r.a[3] == 0xffff);
+}
+
+static void test_pcmpeqb_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 43;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  s.a[4] = 42;
+  s.a[5] = 43;
+  s.a[6] = 42;
+  s.a[7] = 43;
+  t.a[0] = 43;
+  t.a[1] = 43;
+  t.a[2] = 43;
+  t.a[3] = 43;
+  t.a[4] = 43;
+  t.a[5] = 43;
+  t.a[6] = 43;
+  t.a[7] = 43;
+  r.v = pcmpeqb_u (s.v, t.v);
+  assert (r.a[0] == 0x00);
+  assert (r.a[1] == 0xff);
+  assert (r.a[2] == 0x00);
+  assert (r.a[3] == 0xff);
+  assert (r.a[4] == 0x00);
+  assert (r.a[5] == 0xff);
+  assert (r.a[6] == 0x00);
+  assert (r.a[7] == 0xff);
+}
+
+static void test_pcmpeqw_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  t.a[0] = 42;
+  t.a[1] = -42;
+  r.v = pcmpeqw_s (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -1);
+}
+
+static void test_pcmpeqh_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  s.a[2] = -42;
+  s.a[3] = -42;
+  t.a[0] = 42;
+  t.a[1] = -42;
+  t.a[2] = 42;
+  t.a[3] = -42;
+  r.v = pcmpeqh_s (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -1);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -1);
+}
+
+static void test_pcmpeqb_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  s.a[2] = -42;
+  s.a[3] = -42;
+  s.a[4] = -42;
+  s.a[5] = -42;
+  s.a[6] = -42;
+  s.a[7] = -42;
+  t.a[0] = 42;
+  t.a[1] = -42;
+  t.a[2] = 42;
+  t.a[3] = -42;
+  t.a[4] = 42;
+  t.a[5] = -42;
+  t.a[6] = 42;
+  t.a[7] = -42;
+  r.v = pcmpeqb_s (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == -1);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -1);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == -1);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == -1);
+}
+
+static void test_pcmpgtw_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 43;
+  t.a[0] = 43;
+  t.a[1] = 42;
+  r.v = pcmpgtw_u (s.v, t.v);
+  assert (r.a[0] == 0x00000000);
+  assert (r.a[1] == 0xffffffff);
+}
+
+static void test_pcmpgth_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 40;
+  s.a[1] = 41;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  t.a[0] = 40;
+  t.a[1] = 41;
+  t.a[2] = 43;
+  t.a[3] = 42;
+  r.v = pcmpgth_u (s.v, t.v);
+  assert (r.a[0] == 0x0000);
+  assert (r.a[1] == 0x0000);
+  assert (r.a[2] == 0x0000);
+  assert (r.a[3] == 0xffff);
+}
+
+static void test_pcmpgtb_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 40;
+  s.a[1] = 41;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  s.a[4] = 44;
+  s.a[5] = 45;
+  s.a[6] = 46;
+  s.a[7] = 47;
+  t.a[0] = 48;
+  t.a[1] = 47;
+  t.a[2] = 46;
+  t.a[3] = 45;
+  t.a[4] = 44;
+  t.a[5] = 43;
+  t.a[6] = 42;
+  t.a[7] = 41;
+  r.v = pcmpgtb_u (s.v, t.v);
+  assert (r.a[0] == 0x00);
+  assert (r.a[1] == 0x00);
+  assert (r.a[2] == 0x00);
+  assert (r.a[3] == 0x00);
+  assert (r.a[4] == 0x00);
+  assert (r.a[5] == 0xff);
+  assert (r.a[6] == 0xff);
+  assert (r.a[7] == 0xff);
+}
+
+static void test_pcmpgtw_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = -42;
+  t.a[0] = -42;
+  t.a[1] = -42;
+  r.v = pcmpgtw_s (s.v, t.v);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == 0);
+}
+
+static void test_pcmpgth_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  s.a[2] = -42;
+  s.a[3] = -42;
+  t.a[0] = 42;
+  t.a[1] = 43;
+  t.a[2] = 44;
+  t.a[3] = -43;
+  r.v = pcmpgth_s (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == -1);
+}
+
+static void test_pcmpgtb_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = -42;
+  s.a[2] = -42;
+  s.a[3] = -42;
+  s.a[4] = 42;
+  s.a[5] = 42;
+  s.a[6] = 42;
+  s.a[7] = 42;
+  t.a[0] = -45;
+  t.a[1] = -44;
+  t.a[2] = -43;
+  t.a[3] = -42;
+  t.a[4] = 42;
+  t.a[5] = 43;
+  t.a[6] = 41;
+  t.a[7] = 40;
+  r.v = pcmpgtb_s (s.v, t.v);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == -1);
+  assert (r.a[2] == -1);
+  assert (r.a[3] == 0);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == 0);
+  assert (r.a[6] == -1);
+  assert (r.a[7] == -1);
+}
+
+static void test_pextrh_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 40;
+  s.a[1] = 41;
+  s.a[2] = 42;
+  s.a[3] = 43;
+  r.v = pextrh_u (s.v, 1);
+  assert (r.a[0] == 41);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_pextrh_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -40;
+  s.a[1] = -41;
+  s.a[2] = -42;
+  s.a[3] = -43;
+  r.v = pextrh_s (s.v, 2);
+  assert (r.a[0] == -42);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_pinsrh_0123_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 42;
+  s.a[1] = 0;
+  s.a[2] = 0;
+  s.a[3] = 0;
+  t.a[0] = 0;
+  t.a[1] = 0;
+  t.a[2] = 0;
+  t.a[3] = 0;
+  r.v = pinsrh_0_u (t.v, s.v);
+  r.v = pinsrh_1_u (r.v, s.v);
+  r.v = pinsrh_2_u (r.v, s.v);
+  r.v = pinsrh_3_u (r.v, s.v);
+  assert (r.a[0] == 42);
+  assert (r.a[1] == 42);
+  assert (r.a[2] == 42);
+  assert (r.a[3] == 42);
+}
+
+static void test_pinsrh_0123_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -42;
+  s.a[1] = 0;
+  s.a[2] = 0;
+  s.a[3] = 0;
+  t.a[0] = 0;
+  t.a[1] = 0;
+  t.a[2] = 0;
+  t.a[3] = 0;
+  r.v = pinsrh_0_s (t.v, s.v);
+  r.v = pinsrh_1_s (r.v, s.v);
+  r.v = pinsrh_2_s (r.v, s.v);
+  r.v = pinsrh_3_s (r.v, s.v);
+  assert (r.a[0] == -42);
+  assert (r.a[1] == -42);
+  assert (r.a[2] == -42);
+  assert (r.a[3] == -42);
+}
+
+static void test_pmaddhw (void)
+{
+  int16x4_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = -5;
+  s.a[1] = -4;
+  s.a[2] = -3;
+  s.a[3] = -2;
+  t.a[0] = 10;
+  t.a[1] = 11;
+  t.a[2] = 12;
+  t.a[3] = 13;
+  r.v = pmaddhw (s.v, t.v);
+  assert (r.a[0] == (-5*10 + -4*11));
+  assert (r.a[1] == (-3*12 + -2*13));
+}
+
+static void test_pmaxsh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -20;
+  s.a[1] = 40;
+  s.a[2] = -10;
+  s.a[3] = 50;
+  t.a[0] = 20;
+  t.a[1] = -40;
+  t.a[2] = 10;
+  t.a[3] = -50;
+  r.v = pmaxsh (s.v, t.v);
+  assert (r.a[0] == 20);
+  assert (r.a[1] == 40);
+  assert (r.a[2] == 10);
+  assert (r.a[3] == 50);
+}
+
+static void test_pmaxub (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  t.a[0] = 80;
+  t.a[1] = 70;
+  t.a[2] = 60;
+  t.a[3] = 50;
+  t.a[4] = 40;
+  t.a[5] = 30;
+  t.a[6] = 20;
+  t.a[7] = 10;
+  r.v = pmaxub (s.v, t.v);
+  assert (r.a[0] == 80);
+  assert (r.a[1] == 70);
+  assert (r.a[2] == 60);
+  assert (r.a[3] == 50);
+  assert (r.a[4] == 50);
+  assert (r.a[5] == 60);
+  assert (r.a[6] == 70);
+  assert (r.a[7] == 80);
+}
+
+static void test_pminsh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -20;
+  s.a[1] = 40;
+  s.a[2] = -10;
+  s.a[3] = 50;
+  t.a[0] = 20;
+  t.a[1] = -40;
+  t.a[2] = 10;
+  t.a[3] = -50;
+  r.v = pminsh (s.v, t.v);
+  assert (r.a[0] == -20);
+  assert (r.a[1] == -40);
+  assert (r.a[2] == -10);
+  assert (r.a[3] == -50);
+}
+
+static void test_pminub (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  t.a[0] = 80;
+  t.a[1] = 70;
+  t.a[2] = 60;
+  t.a[3] = 50;
+  t.a[4] = 40;
+  t.a[5] = 30;
+  t.a[6] = 20;
+  t.a[7] = 10;
+  r.v = pminub (s.v, t.v);
+  assert (r.a[0] == 10);
+  assert (r.a[1] == 20);
+  assert (r.a[2] == 30);
+  assert (r.a[3] == 40);
+  assert (r.a[4] == 40);
+  assert (r.a[5] == 30);
+  assert (r.a[6] == 20);
+  assert (r.a[7] == 10);
+}
+
+static void test_pmovmskb_u (void)
+{
+  uint8x8_encap_t s;
+  uint8x8_encap_t r;
+  s.a[0] = 0xf0;
+  s.a[1] = 0x40;
+  s.a[2] = 0xf0;
+  s.a[3] = 0x40;
+  s.a[4] = 0xf0;
+  s.a[5] = 0x40;
+  s.a[6] = 0xf0;
+  s.a[7] = 0x40;
+  r.v = pmovmskb_u (s.v);
+  assert (r.a[0] == 0x55);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == 0);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == 0);
+}
+
+static void test_pmovmskb_s (void)
+{
+  int8x8_encap_t s;
+  int8x8_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 1;
+  s.a[2] = -1;
+  s.a[3] = 1;
+  s.a[4] = -1;
+  s.a[5] = 1;
+  s.a[6] = -1;
+  s.a[7] = 1;
+  r.v = pmovmskb_s (s.v);
+  assert (r.a[0] == 0x55);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == 0);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == 0);
+}
+
+static void test_pmulhuh (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 0xff00;
+  s.a[1] = 0xff00;
+  s.a[2] = 0xff00;
+  s.a[3] = 0xff00;
+  t.a[0] = 16;
+  t.a[1] = 16;
+  t.a[2] = 16;
+  t.a[3] = 16;
+  r.v = pmulhuh (s.v, t.v);
+  assert (r.a[0] == 0x000f);
+  assert (r.a[1] == 0x000f);
+  assert (r.a[2] == 0x000f);
+  assert (r.a[3] == 0x000f);
+}
+
+static void test_pmulhh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = 0x0ff0;
+  s.a[1] = 0x0ff0;
+  s.a[2] = 0x0ff0;
+  s.a[3] = 0x0ff0;
+  t.a[0] = -16*16;
+  t.a[1] = -16*16;
+  t.a[2] = -16*16;
+  t.a[3] = -16*16;
+  r.v = pmulhh (s.v, t.v);
+  assert (r.a[0] == -16);
+  assert (r.a[1] == -16);
+  assert (r.a[2] == -16);
+  assert (r.a[3] == -16);
+}
+
+static void test_pmullh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = 0x0ff0;
+  s.a[1] = 0x0ff0;
+  s.a[2] = 0x0ff0;
+  s.a[3] = 0x0ff0;
+  t.a[0] = -16*16;
+  t.a[1] = -16*16;
+  t.a[2] = -16*16;
+  t.a[3] = -16*16;
+  r.v = pmullh (s.v, t.v);
+  assert (r.a[0] == 4096);
+  assert (r.a[1] == 4096);
+  assert (r.a[2] == 4096);
+  assert (r.a[3] == 4096);
+}
+
+static void test_pmuluw (void)
+{
+  uint32x2_encap_t s, t;
+  uint64_t r;
+  s.a[0] = 0xdeadbeef;
+  s.a[1] = 0;
+  t.a[0] = 0x0f00baaa;
+  t.a[1] = 0;
+  r = pmuluw (s.v, t.v);
+  assert (r == 0xd0cd08e1d1a70b6ull);
+}
+
+static void test_pasubub (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  t.a[0] = 80;
+  t.a[1] = 70;
+  t.a[2] = 60;
+  t.a[3] = 50;
+  t.a[4] = 40;
+  t.a[5] = 30;
+  t.a[6] = 20;
+  t.a[7] = 10;
+  r.v = pasubub (s.v, t.v);
+  assert (r.a[0] == 70);
+  assert (r.a[1] == 50);
+  assert (r.a[2] == 30);
+  assert (r.a[3] == 10);
+  assert (r.a[4] == 10);
+  assert (r.a[5] == 30);
+  assert (r.a[6] == 50);
+  assert (r.a[7] == 70);
+}
+
+static void test_biadd (void)
+{
+  uint8x8_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  r.v = biadd (s.v);
+  assert (r.a[0] == 360);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_psadbh (void)
+{
+  uint8x8_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 20;
+  s.a[2] = 30;
+  s.a[3] = 40;
+  s.a[4] = 50;
+  s.a[5] = 60;
+  s.a[6] = 70;
+  s.a[7] = 80;
+  t.a[0] = 80;
+  t.a[1] = 70;
+  t.a[2] = 60;
+  t.a[3] = 50;
+  t.a[4] = 40;
+  t.a[5] = 30;
+  t.a[6] = 20;
+  t.a[7] = 10;
+  r.v = psadbh (s.v, t.v);
+  assert (r.a[0] == 0x0140);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_pshufh_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 2;
+  s.a[2] = 3;
+  s.a[3] = 4;
+  r.a[0] = 0;
+  r.a[1] = 0;
+  r.a[2] = 0;
+  r.a[3] = 0;
+  r.v = pshufh_u (r.v, s.v, 0xe5);
+  assert (r.a[0] == 2);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == 3);
+  assert (r.a[3] == 4);
+}
+
+static void test_pshufh_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 2;
+  s.a[2] = -3;
+  s.a[3] = 4;
+  r.a[0] = 0;
+  r.a[1] = 0;
+  r.a[2] = 0;
+  r.a[3] = 0;
+  r.v = pshufh_s (r.v, s.v, 0xe5);
+  assert (r.a[0] == 2);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == -3);
+  assert (r.a[3] == 4);
+}
+
+static void test_psllh_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 0xffff;
+  s.a[1] = 0xffff;
+  s.a[2] = 0xffff;
+  s.a[3] = 0xffff;
+  r.v = psllh_u (s.v, 1);
+  assert (r.a[0] == 0xfffe);
+  assert (r.a[1] == 0xfffe);
+  assert (r.a[2] == 0xfffe);
+  assert (r.a[3] == 0xfffe);
+}
+
+static void test_psllw_u (void)
+{
+  uint32x2_encap_t s;
+  uint32x2_encap_t r;
+  s.a[0] = 0xffffffff;
+  s.a[1] = 0xffffffff;
+  r.v = psllw_u (s.v, 2);
+  assert (r.a[0] == 0xfffffffc);
+  assert (r.a[1] == 0xfffffffc);
+}
+
+static void test_psllh_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -1;
+  s.a[2] = -1;
+  s.a[3] = -1;
+  r.v = psllh_s (s.v, 1);
+  assert (r.a[0] == -2);
+  assert (r.a[1] == -2);
+  assert (r.a[2] == -2);
+  assert (r.a[3] == -2);
+}
+
+static void test_psllw_s (void)
+{
+  int32x2_encap_t s;
+  int32x2_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -1;
+  r.v = psllw_s (s.v, 2);
+  assert (r.a[0] == -4);
+  assert (r.a[1] == -4);
+}
+
+static void test_psrah_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 0xffef;
+  s.a[1] = 0xffef;
+  s.a[2] = 0xffef;
+  s.a[3] = 0xffef;
+  r.v = psrah_u (s.v, 1);
+  assert (r.a[0] == 0xfff7);
+  assert (r.a[1] == 0xfff7);
+  assert (r.a[2] == 0xfff7);
+  assert (r.a[3] == 0xfff7);
+}
+
+static void test_psraw_u (void)
+{
+  uint32x2_encap_t s;
+  uint32x2_encap_t r;
+  s.a[0] = 0xffffffef;
+  s.a[1] = 0xffffffef;
+  r.v = psraw_u (s.v, 1);
+  assert (r.a[0] == 0xfffffff7);
+  assert (r.a[1] == 0xfffffff7);
+}
+
+static void test_psrah_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -2;
+  s.a[1] = -2;
+  s.a[2] = -2;
+  s.a[3] = -2;
+  r.v = psrah_s (s.v, 1);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == -1);
+  assert (r.a[2] == -1);
+  assert (r.a[3] == -1);
+}
+
+static void test_psraw_s (void)
+{
+  int32x2_encap_t s;
+  int32x2_encap_t r;
+  s.a[0] = -2;
+  s.a[1] = -2;
+  r.v = psraw_s (s.v, 1);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == -1);
+}
+
+static void test_psrlh_u (void)
+{
+  uint16x4_encap_t s;
+  uint16x4_encap_t r;
+  s.a[0] = 0xffef;
+  s.a[1] = 0xffef;
+  s.a[2] = 0xffef;
+  s.a[3] = 0xffef;
+  r.v = psrlh_u (s.v, 1);
+  assert (r.a[0] == 0x7ff7);
+  assert (r.a[1] == 0x7ff7);
+  assert (r.a[2] == 0x7ff7);
+  assert (r.a[3] == 0x7ff7);
+}
+
+static void test_psrlw_u (void)
+{
+  uint32x2_encap_t s;
+  uint32x2_encap_t r;
+  s.a[0] = 0xffffffef;
+  s.a[1] = 0xffffffef;
+  r.v = psrlw_u (s.v, 1);
+  assert (r.a[0] == 0x7ffffff7);
+  assert (r.a[1] == 0x7ffffff7);
+}
+
+static void test_psrlh_s (void)
+{
+  int16x4_encap_t s;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -1;
+  s.a[2] = -1;
+  s.a[3] = -1;
+  r.v = psrlh_s (s.v, 1);
+  assert (r.a[0] == INT16x4_MAX);
+  assert (r.a[1] == INT16x4_MAX);
+  assert (r.a[2] == INT16x4_MAX);
+  assert (r.a[3] == INT16x4_MAX);
+}
+
+static void test_psrlw_s (void)
+{
+  int32x2_encap_t s;
+  int32x2_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -1;
+  r.v = psrlw_s (s.v, 1);
+  assert (r.a[0] == INT32x2_MAX);
+  assert (r.a[1] == INT32x2_MAX);
+}
+
+static void test_psubw_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 3;
+  s.a[1] = 4;
+  t.a[0] = 2;
+  t.a[1] = 1;
+  r.v = psubw_u (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 3);
+}
+
+static void test_psubw_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = -2;
+  s.a[1] = -1;
+  t.a[0] = 3;
+  t.a[1] = -4;
+  r.v = psubw_s (s.v, t.v);
+  assert (r.a[0] == -5);
+  assert (r.a[1] == 3);
+}
+
+static void test_psubh_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 5;
+  s.a[1] = 6;
+  s.a[2] = 7;
+  s.a[3] = 8;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  r.v = psubh_u (s.v, t.v);
+  assert (r.a[0] == 4);
+  assert (r.a[1] == 4);
+  assert (r.a[2] == 4);
+  assert (r.a[3] == 4);
+}
+
+static void test_psubh_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -10;
+  s.a[1] = -20;
+  s.a[2] = -30;
+  s.a[3] = -40;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  r.v = psubh_s (s.v, t.v);
+  assert (r.a[0] == -11);
+  assert (r.a[1] == -22);
+  assert (r.a[2] == -33);
+  assert (r.a[3] == -44);
+}
+
+static void test_psubb_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 10;
+  s.a[1] = 11;
+  s.a[2] = 12;
+  s.a[3] = 13;
+  s.a[4] = 14;
+  s.a[5] = 15;
+  s.a[6] = 16;
+  s.a[7] = 17;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  t.a[4] = 5;
+  t.a[5] = 6;
+  t.a[6] = 7;
+  t.a[7] = 8;
+  r.v = psubb_u (s.v, t.v);
+  assert (r.a[0] == 9);
+  assert (r.a[1] == 9);
+  assert (r.a[2] == 9);
+  assert (r.a[3] == 9);
+  assert (r.a[4] == 9);
+  assert (r.a[5] == 9);
+  assert (r.a[6] == 9);
+  assert (r.a[7] == 9);
+}
+
+static void test_psubb_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -10;
+  s.a[1] = -20;
+  s.a[2] = -30;
+  s.a[3] = -40;
+  s.a[4] = -50;
+  s.a[5] = -60;
+  s.a[6] = -70;
+  s.a[7] = -80;
+  t.a[0] = 1;
+  t.a[1] = 2;
+  t.a[2] = 3;
+  t.a[3] = 4;
+  t.a[4] = 5;
+  t.a[5] = 6;
+  t.a[6] = 7;
+  t.a[7] = 8;
+  r.v = psubb_s (s.v, t.v);
+  assert (r.a[0] == -11);
+  assert (r.a[1] == -22);
+  assert (r.a[2] == -33);
+  assert (r.a[3] == -44);
+  assert (r.a[4] == -55);
+  assert (r.a[5] == -66);
+  assert (r.a[6] == -77);
+  assert (r.a[7] == -88);
+}
+
+static void test_psubd_u (void)
+{
+  uint64_t d = 789012;
+  uint64_t e = 123456;
+  uint64_t r;
+  r = psubd_u (d, e);
+  assert (r == 665556);
+}
+
+static void test_psubd_s (void)
+{
+  int64_t d = 123456;
+  int64_t e = -789012;
+  int64_t r;
+  r = psubd_s (d, e);
+  assert (r == 912468);
+}
+
+static void test_psubsh (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 0;
+  s.a[2] = 1;
+  s.a[3] = 2;
+  t.a[0] = -INT16x4_MAX;
+  t.a[1] = -INT16x4_MAX;
+  t.a[2] = -INT16x4_MAX;
+  t.a[3] = -INT16x4_MAX;
+  r.v = psubsh (s.v, t.v);
+  assert (r.a[0] == INT16x4_MAX - 1);
+  assert (r.a[1] == INT16x4_MAX);
+  assert (r.a[2] == INT16x4_MAX);
+  assert (r.a[3] == INT16x4_MAX);
+}
+
+static void test_psubsb (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -6;
+  s.a[1] = -5;
+  s.a[2] = -4;
+  s.a[3] = -3;
+  s.a[4] = -2;
+  s.a[5] = -1;
+  s.a[6] = 0;
+  s.a[7] = 1;
+  t.a[0] = -INT8x8_MAX;
+  t.a[1] = -INT8x8_MAX;
+  t.a[2] = -INT8x8_MAX;
+  t.a[3] = -INT8x8_MAX;
+  t.a[4] = -INT8x8_MAX;
+  t.a[5] = -INT8x8_MAX;
+  t.a[6] = -INT8x8_MAX;
+  t.a[7] = -INT8x8_MAX;
+  r.v = psubsb (s.v, t.v);
+  assert (r.a[0] == INT8x8_MAX - 6);
+  assert (r.a[1] == INT8x8_MAX - 5);
+  assert (r.a[2] == INT8x8_MAX - 4);
+  assert (r.a[3] == INT8x8_MAX - 3);
+  assert (r.a[4] == INT8x8_MAX - 2);
+  assert (r.a[5] == INT8x8_MAX - 1);
+  assert (r.a[6] == INT8x8_MAX);
+  assert (r.a[7] == INT8x8_MAX);
+}
+
+static void test_psubush (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 0;
+  s.a[1] = 1;
+  s.a[2] = 2;
+  s.a[3] = 3;
+  t.a[0] = 1;
+  t.a[1] = 1;
+  t.a[2] = 3;
+  t.a[3] = 3;
+  r.v = psubush (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+}
+
+static void test_psubusb (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 0;
+  s.a[1] = 1;
+  s.a[2] = 2;
+  s.a[3] = 3;
+  s.a[4] = 4;
+  s.a[5] = 5;
+  s.a[6] = 6;
+  s.a[7] = 7;
+  t.a[0] = 1;
+  t.a[1] = 1;
+  t.a[2] = 3;
+  t.a[3] = 3;
+  t.a[4] = 5;
+  t.a[5] = 5;
+  t.a[6] = 7;
+  t.a[7] = 7;
+  r.v = psubusb (s.v, t.v);
+  assert (r.a[0] == 0);
+  assert (r.a[1] == 0);
+  assert (r.a[2] == 0);
+  assert (r.a[3] == 0);
+  assert (r.a[4] == 0);
+  assert (r.a[5] == 0);
+  assert (r.a[6] == 0);
+  assert (r.a[7] == 0);
+}
+
+static void test_punpckhbh_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -3;
+  s.a[2] = -5;
+  s.a[3] = -7;
+  s.a[4] = -9;
+  s.a[5] = -11;
+  s.a[6] = -13;
+  s.a[7] = -15;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  t.a[4] = 10;
+  t.a[5] = 12;
+  t.a[6] = 14;
+  t.a[7] = 16;
+  r.v = punpckhbh_s (s.v, t.v);
+  assert (r.a[0] == -9);
+  assert (r.a[1] == 10);
+  assert (r.a[2] == -11);
+  assert (r.a[3] == 12);
+  assert (r.a[4] == -13);
+  assert (r.a[5] == 14);
+  assert (r.a[6] == -15);
+  assert (r.a[7] == 16);
+}
+
+static void test_punpckhbh_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  s.a[2] = 5;
+  s.a[3] = 7;
+  s.a[4] = 9;
+  s.a[5] = 11;
+  s.a[6] = 13;
+  s.a[7] = 15;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  t.a[4] = 10;
+  t.a[5] = 12;
+  t.a[6] = 14;
+  t.a[7] = 16;
+  r.v = punpckhbh_u (s.v, t.v);
+  assert (r.a[0] == 9);
+  assert (r.a[1] == 10);
+  assert (r.a[2] == 11);
+  assert (r.a[3] == 12);
+  assert (r.a[4] == 13);
+  assert (r.a[5] == 14);
+  assert (r.a[6] == 15);
+  assert (r.a[7] == 16);
+}
+
+static void test_punpckhhw_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 3;
+  s.a[2] = -5;
+  s.a[3] = 7;
+  t.a[0] = -2;
+  t.a[1] = 4;
+  t.a[2] = -6;
+  t.a[3] = 8;
+  r.v = punpckhhw_s (s.v, t.v);
+  assert (r.a[0] == -5);
+  assert (r.a[1] == -6);
+  assert (r.a[2] == 7);
+  assert (r.a[3] == 8);
+}
+
+static void test_punpckhhw_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  s.a[2] = 5;
+  s.a[3] = 7;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  r.v = punpckhhw_u (s.v, t.v);
+  assert (r.a[0] == 5);
+  assert (r.a[1] == 6);
+  assert (r.a[2] == 7);
+  assert (r.a[3] == 8);
+}
+
+static void test_punpckhwd_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  t.a[0] = 2;
+  t.a[1] = -4;
+  r.v = punpckhwd_s (s.v, t.v);
+  assert (r.a[0] == 3);
+  assert (r.a[1] == -4);
+}
+
+static void test_punpckhwd_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  r.v = punpckhwd_u (s.v, t.v);
+  assert (r.a[0] == 3);
+  assert (r.a[1] == 4);
+}
+
+static void test_punpcklbh_s (void)
+{
+  int8x8_encap_t s, t;
+  int8x8_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = -3;
+  s.a[2] = -5;
+  s.a[3] = -7;
+  s.a[4] = -9;
+  s.a[5] = -11;
+  s.a[6] = -13;
+  s.a[7] = -15;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  t.a[4] = 10;
+  t.a[5] = 12;
+  t.a[6] = 14;
+  t.a[7] = 16;
+  r.v = punpcklbh_s (s.v, t.v);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == -3);
+  assert (r.a[3] == 4);
+  assert (r.a[4] == -5);
+  assert (r.a[5] == 6);
+  assert (r.a[6] == -7);
+  assert (r.a[7] == 8);
+}
+
+static void test_punpcklbh_u (void)
+{
+  uint8x8_encap_t s, t;
+  uint8x8_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  s.a[2] = 5;
+  s.a[3] = 7;
+  s.a[4] = 9;
+  s.a[5] = 11;
+  s.a[6] = 13;
+  s.a[7] = 15;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  t.a[4] = 10;
+  t.a[5] = 12;
+  t.a[6] = 14;
+  t.a[7] = 16;
+  r.v = punpcklbh_u (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == 3);
+  assert (r.a[3] == 4);
+  assert (r.a[4] == 5);
+  assert (r.a[5] == 6);
+  assert (r.a[6] == 7);
+  assert (r.a[7] == 8);
+}
+
+static void test_punpcklhw_s (void)
+{
+  int16x4_encap_t s, t;
+  int16x4_encap_t r;
+  s.a[0] = -1;
+  s.a[1] = 3;
+  s.a[2] = -5;
+  s.a[3] = 7;
+  t.a[0] = -2;
+  t.a[1] = 4;
+  t.a[2] = -6;
+  t.a[3] = 8;
+  r.v = punpcklhw_s (s.v, t.v);
+  assert (r.a[0] == -1);
+  assert (r.a[1] == -2);
+  assert (r.a[2] == 3);
+  assert (r.a[3] == 4);
+}
+
+static void test_punpcklhw_u (void)
+{
+  uint16x4_encap_t s, t;
+  uint16x4_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  s.a[2] = 5;
+  s.a[3] = 7;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  t.a[2] = 6;
+  t.a[3] = 8;
+  r.v = punpcklhw_u (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 2);
+  assert (r.a[2] == 3);
+  assert (r.a[3] == 4);
+}
+
+static void test_punpcklwd_s (void)
+{
+  int32x2_encap_t s, t;
+  int32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  t.a[0] = -2;
+  t.a[1] = 4;
+  r.v = punpcklwd_s (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == -2);
+}
+
+static void test_punpcklwd_u (void)
+{
+  uint32x2_encap_t s, t;
+  uint32x2_encap_t r;
+  s.a[0] = 1;
+  s.a[1] = 3;
+  t.a[0] = 2;
+  t.a[1] = 4;
+  r.v = punpcklwd_u (s.v, t.v);
+  assert (r.a[0] == 1);
+  assert (r.a[1] == 2);
+}
+
+int main (void)
+{
+  test_packsswh ();
+  test_packsshb ();
+  test_packushb ();
+  test_paddw_u ();
+  test_paddw_s ();
+  test_paddh_u ();
+  test_paddh_s ();
+  test_paddb_u ();
+  test_paddb_s ();
+  test_paddd_u ();
+  test_paddd_s ();
+  test_paddsh ();
+  test_paddsb ();
+  test_paddush ();
+  test_paddusb ();
+  test_pandn_ud ();
+  test_pandn_sd ();
+  test_pandn_uw ();
+  test_pandn_sw ();
+  test_pandn_uh ();
+  test_pandn_sh ();
+  test_pandn_ub ();
+  test_pandn_sb ();
+  test_pavgh ();
+  test_pavgb ();
+  test_pcmpeqw_u ();
+  test_pcmpeqh_u ();
+  test_pcmpeqb_u ();
+  test_pcmpeqw_s ();
+  test_pcmpeqh_s ();
+  test_pcmpeqb_s ();
+  test_pcmpgtw_u ();
+  test_pcmpgth_u ();
+  test_pcmpgtb_u ();
+  test_pcmpgtw_s ();
+  test_pcmpgth_s ();
+  test_pcmpgtb_s ();
+  test_pextrh_u ();
+  test_pextrh_s ();
+  test_pinsrh_0123_u ();
+  test_pinsrh_0123_s ();
+  test_pmaddhw ();
+  test_pmaxsh ();
+  test_pmaxub ();
+  test_pminsh ();
+  test_pminub ();
+  test_pmovmskb_u ();
+  test_pmovmskb_s ();
+  test_pmulhuh ();
+  test_pmulhh ();
+  test_pmullh ();
+  test_pmuluw ();
+  test_pasubub ();
+  test_biadd ();
+  test_psadbh ();
+  test_pshufh_u ();
+  test_pshufh_s ();
+  test_psllh_u ();
+  test_psllw_u ();
+  test_psllh_s ();
+  test_psllw_s ();
+  test_psrah_u ();
+  test_psraw_u ();
+  test_psrah_s ();
+  test_psraw_s ();
+  test_psrlh_u ();
+  test_psrlw_u ();
+  test_psrlh_s ();
+  test_psrlw_s ();
+  test_psubw_u ();
+  test_psubw_s ();
+  test_psubh_u ();
+  test_psubh_s ();
+  test_psubb_u ();
+  test_psubb_s ();
+  test_psubd_u ();
+  test_psubd_s ();
+  test_psubsh ();
+  test_psubsb ();
+  test_psubush ();
+  test_psubusb ();
+  test_punpckhbh_s ();
+  test_punpckhbh_u ();
+  test_punpckhhw_s ();
+  test_punpckhhw_u ();
+  test_punpckhwd_s ();
+  test_punpckhwd_u ();
+  test_punpcklbh_s ();
+  test_punpcklbh_u ();
+  test_punpcklhw_s ();
+  test_punpcklhw_u ();
+  test_punpcklwd_s ();
+  test_punpcklwd_u ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c
new file mode 100644
index 000000000..1c4d010b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-1.c
@@ -0,0 +1,16 @@
+/* { dg-options "-march=loongson3a" } */
+
+typedef int st;
+typedef unsigned int ut;
+
+NOMIPS16 st smul (st x, st y) { return x * y; }
+NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; }
+
+NOMIPS16 ut umul (ut x, ut y) { return x * y; }
+NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; }
+
+/* { dg-final { scan-assembler-times "\tgsmultu\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tgsdivu\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tgsmodu\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tgsdiv\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tgsmod\t" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c
new file mode 100644
index 000000000..9695b3f62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/loongson3a-muldiv-2.c
@@ -0,0 +1,16 @@
+/* { dg-options "-march=loongson3a -mgp64" } */
+
+typedef long long st;
+typedef unsigned long long ut;
+
+NOMIPS16 st smul (st x, st y) { return x * y; }
+NOMIPS16 st sdiv (st x, st y) { return x / y + x % y; }
+
+NOMIPS16 ut umul (ut x, ut y) { return x * y; }
+NOMIPS16 ut udiv (ut x, ut y) { return x / y + x % y; }
+
+/* { dg-final { scan-assembler-times "\tgsdmultu\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tgsddivu\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tgsdmodu\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tgsddiv\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tgsdmod\t" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-1.c
new file mode 100644
index 000000000..416673b46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-march=vr4130 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmacc\t\\\$1," 3 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return (long long) x * y + z;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  return z + (long long) y * x;
+}
+
+NOMIPS16 long long
+f3 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-2.c
new file mode 100644
index 000000000..ce0d9eb6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-march=vr5500 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return (long long) x * y + z;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  return z + (long long) y * x;
+}
+
+NOMIPS16 long long
+f3 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c
new file mode 100644
index 000000000..29f4c9b37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-3.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=1 -mgp32" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return (long long) x * y + z;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  return z + (long long) y * x;
+}
+
+NOMIPS16 long long
+f3 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-4.c
new file mode 100644
index 000000000..28c751b40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-4.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-mdspr2 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmadd\t\\\$ac" 3 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return (long long) x * y + z;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  return z + (long long) y * x;
+}
+
+NOMIPS16 long long
+f3 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-5.c
new file mode 100644
index 000000000..d1696a6a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-5.c
@@ -0,0 +1,9 @@
+/* { dg-options "-march=5kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmadd\t" 4 } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-times "\tmflo\t" 3 } } */
+
+NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3]; }
+NOMIPS16 void f2 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3] + a[4]; }
+NOMIPS16 void f3 (int *a) { a[0] = a[0] * a[1] + a[2] * a[3] + a[4] * a[5]; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-6.c
new file mode 100644
index 000000000..9323b8e10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-6.c
@@ -0,0 +1,7 @@
+/* { dg-options "-march=5kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tmadd\t" } } */
+/* { dg-final { scan-assembler "\tmul\t" } } */
+/* { dg-final { scan-assembler "\taddu\t" } } */
+
+NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] + a[2]; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-7.c
new file mode 100644
index 000000000..a639aa4f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-7.c
@@ -0,0 +1,16 @@
+/* { dg-options "-march=5kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-skip-if "requires -fira-region=all or =mixed" { *-*-* } { "-Os" } { "" } } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+/* { dg-final { scan-assembler "\tmadd\t" } } */
+
+NOMIPS16 int
+f1 (int *a, int *b, int n)
+{
+  int x, i;
+
+  x = 0;
+  for (i = 0; i < n; i++)
+    x += a[i] * b[i];
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-8.c
new file mode 100644
index 000000000..794a6ff17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-8.c
@@ -0,0 +1,16 @@
+/* { dg-options "-march=5kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmul\t" } } */
+/* { dg-final { scan-assembler-not "\tmadd\t" } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+NOMIPS16 int
+f2 (int x, int y, int z)
+{
+  asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9",
+		"$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17",
+		"$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25",
+		"$31");
+  return x * y + z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c
new file mode 100644
index 000000000..28681a910
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/madd-9.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=1 -mgp32 -mtune=4kc" } */
+/* References to X within the loop need to have a higher frequency than
+   references to X outside the loop, otherwise there is no reason
+   to prefer multiply/accumulator registers over GPRs.  */
+/* { dg-skip-if "requires register frequencies" { *-*-* } { "-O0" "-Os" } { "" } } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+/* { dg-final { scan-assembler-not "\tmthi" } } */
+/* { dg-final { scan-assembler-not "\tmtlo" } } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmadd\t" } } */
+
+NOMIPS16 long long
+f1 (int *a, int *b, int n)
+{
+  long long int x;
+  int i;
+
+  x = 0;
+  for (i = 0; i < n; i++)
+    x += (long long) a[i] * b[i];
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-1.c
new file mode 100644
index 000000000..af2b4181c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-march=vr4130 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmaccu\t\\\$1," 3 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return (ull) x * y + z;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  return z + (ull) y * x;
+}
+
+NOMIPS16 ull
+f3 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-2.c
new file mode 100644
index 000000000..ea091e4e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-march=vr5500 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return (ull) x * y + z;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  return z + (ull) y * x;
+}
+
+NOMIPS16 ull
+f3 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c
new file mode 100644
index 000000000..27a7350f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-3.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return (ull) x * y + z;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  return z + (ull) y * x;
+}
+
+NOMIPS16 ull
+f3 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-4.c
new file mode 100644
index 000000000..58c4a7ebe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/maddu-4.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-mdspr2 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmaddu\t\\\$ac" 3 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return (ull) x * y + z;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  return z + (ull) y * x;
+}
+
+NOMIPS16 ull
+f3 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z += t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/memcpy-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/memcpy-1.c
new file mode 100644
index 000000000..94786a737
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/memcpy-1.c
@@ -0,0 +1,19 @@
+/* { dg-options "-fno-common" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tlbu\t" } } */
+
+#include <string.h>
+
+char c[10];
+
+void
+f1 ()
+{
+  memcpy (c, "123456", 6);
+}
+
+void
+f2 ()
+{
+  memcpy (c, &"12345678"[2], 6);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-1.c
new file mode 100644
index 000000000..f11ffc5a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-1.c
@@ -0,0 +1,127 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Test MIPS-3D builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int main ()
+{
+  int little_endian;
+  v2sf a, b, c, d;
+  float f1, f2, f3, f4, f5, f6;
+  double d1, d2, d3, d4, d5, d6, d7, d8, d9;
+  v2sf ps1, ps2, ps3, ps4, ps5, ps6;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* addr.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {45, 67};
+  c = __builtin_mips_addr_ps (a, b);
+  if (little_endian)
+    d = (v2sf) {112, 46};
+  else
+    d = (v2sf) {46, 112};
+
+  if (!__builtin_mips_all_c_eq_ps(c, d))
+     abort ();
+
+  /* mulr.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {45, 67};
+  c = __builtin_mips_mulr_ps (a, b);
+  if (little_endian)
+    d = (v2sf) {3015, 408};
+  else
+    d = (v2sf) {408, 3015};
+
+  if (!__builtin_mips_all_c_eq_ps(c, d))
+     abort ();
+
+  /* cvt.pw.ps */
+  a = (v2sf) {12345.34, 67890.45};
+  b = __builtin_mips_cvt_pw_ps (a);
+
+  /* cvt.ps.pw */
+  c = __builtin_mips_cvt_ps_pw (b);
+  d = (v2sf) {12345.0, 67890.0};
+
+  if (!__builtin_mips_all_c_eq_ps(c, d))
+     abort ();
+
+  /* recip1.s recip2.s */
+  f1 = 40;
+  f2 = __builtin_mips_recip1_s (f1);
+  f3 = __builtin_mips_recip2_s (f2, f1);
+  f4 = f2 + f2 * f3;
+  f5 = 0.025;
+
+  if (f4 != f5)
+    abort ();
+
+  /* recip1.d recip2.d */
+  d1 = 80;
+  d2 = __builtin_mips_recip1_d (d1);
+  d3 = __builtin_mips_recip2_d (d2, d1);
+  d4 = d2 + d2 * d3;
+  d5 = __builtin_mips_recip2_d (d4, d1);
+  d6 = d4 + d4 * d5;
+  d7 = 0.0125;
+
+  if (d6 != d7)
+    abort ();
+
+  /* recip1.ps recip2.ps */
+  ps1 = (v2sf) {100, 200};
+  ps2 = __builtin_mips_recip1_ps (ps1);
+  ps3 = __builtin_mips_recip2_ps (ps2, ps1);
+  ps4 = ps2 + ps2 * ps3;
+  ps5 = (v2sf) {0.01, 0.005};
+
+  if (!__builtin_mips_all_c_eq_ps(ps4, ps5))
+    abort ();
+
+  /* rsqrt1.s rsqrt2.s */
+  f1 = 400;
+  f2 = __builtin_mips_rsqrt1_s (f1);
+  f3 = f2 * f1;
+  f4 = __builtin_mips_rsqrt2_s (f3, f2);
+  f5 = f2 + f2 * f4;
+  f6 = 0.05;
+
+  if (f5 != f6)
+    abort ();
+
+  /* rsqrt1.d rsqrt2.d */
+  d1 = 1600;
+  d2 = __builtin_mips_rsqrt1_d (d1);
+  d3 = d2 * d1;
+  d4 = __builtin_mips_rsqrt2_d (d3, d2);
+  d5 = d2 + d2 * d4;
+  d6 = d1 * d5;
+  d7 = __builtin_mips_rsqrt2_d (d6, d5);
+  d8 = d5 + d5 * d7;
+  d9 = 0.025;
+
+  if (d8 != d9)
+    abort ();
+
+  /* rsqrt1.ps rsqrt2.ps */
+  ps1 = (v2sf) {400, 100};
+  ps2 = __builtin_mips_rsqrt1_ps (ps1);
+  ps3 = ps2 * ps1;
+  ps4 = __builtin_mips_rsqrt2_ps (ps3, ps2);
+  ps5 = ps2 + ps2 * ps4;
+  ps6 = (v2sf) {0.05, 0.1};
+
+  if (!__builtin_mips_all_c_eq_ps(ps5, ps6))
+     abort ();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-2.c
new file mode 100644
index 000000000..b04c3bfb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-2.c
@@ -0,0 +1,554 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Test MIPS-3D branch-if-any-two builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  v2sf a, b, c, d;
+  int i, j;
+
+  /* c.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {56, 78};
+  i = 0;
+  j = 0;
+  if (__builtin_mips_any_c_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_all_c_eq_ps(a, b) != j)
+     abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {12, 78};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_all_c_eq_ps(a, b) != j)
+     abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {56, 34};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_all_c_eq_ps(a, b) != j)
+     abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {12, 34};
+  i = 1;
+  j = 1;
+  if (__builtin_mips_any_c_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_all_c_eq_ps(a, b) != j)
+     abort ();
+
+  /* Test with 16 operators */
+  a = (v2sf) {10.58, 1984.0};
+  b = (v2sf) {567.345, 1984.0};
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 0)
+    abort ();
+  i = test8 (a, b);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b);
+  if (i != 0)
+    abort ();
+  i = test24 (a, b);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b);
+  if (i != 1)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reverse arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a);
+  if (i != 1)
+    abort ();
+  i = test5 (b, a);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a);
+  if (i != 1)
+    abort ();
+  i = test7 (b, a);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a);
+  if (i != 0)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 0)
+    abort ();
+  i = test11 (b, a);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a);
+  if (i != 1)
+    abort ();
+  i = test13 (b, a);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a);
+  if (i != 0)
+    abort ();
+  i = test16 (b, a);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a);
+  if (i != 1)
+    abort ();
+  i = test21 (b, a);
+  if (i != 0)
+    abort ();
+  i = test22 (b, a);
+  if (i != 1)
+    abort ();
+  i = test23 (b, a);
+  if (i != 0)
+    abort ();
+  i = test24 (b, a);
+  if (i != 0)
+    abort ();
+  i = test25 (b, a);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a);
+  if (i != 0)
+    abort ();
+  i = test27 (b, a);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a);
+  if (i != 1)
+    abort ();
+  i = test29 (b, a);
+  if (i != 0)
+    abort ();
+  i = test30 (b, a);
+  if (i != 1)
+    abort ();
+  i = test31 (b, a);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test with 16 operators */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {567.345, 1984.0};
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 1)
+    abort ();
+  i = test19 (a, b);
+  if (i != 1)
+    abort ();
+  i = test20 (a, b);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b);
+  if (i != 0)
+    abort ();
+  i = test29 (a, b);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_f_ps (a, b);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_f_ps (a, b);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_un_ps (a, b);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_un_ps (a, b);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_eq_ps (a, b);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_eq_ps (a, b);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ueq_ps (a, b);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ueq_ps (a, b);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_olt_ps (a, b);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_olt_ps (a, b);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ult_ps (a, b);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ult_ps (a, b);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ole_ps (a, b);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ole_ps (a, b);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ule_ps (a, b);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ule_ps (a, b);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_sf_ps (a, b);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_sf_ps (a, b);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ngle_ps (a, b);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ngle_ps (a, b);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_seq_ps (a, b);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_seq_ps (a, b);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ngl_ps (a, b);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ngl_ps (a, b);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_lt_ps (a, b);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_lt_ps (a, b);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_nge_ps (a, b);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_nge_ps (a, b);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_le_ps (a, b);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_le_ps (a, b);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_c_ngt_ps (a, b);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_c_ngt_ps (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-3.c
new file mode 100644
index 000000000..e4de8fb19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-3.c
@@ -0,0 +1,1095 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Test MIPS-3D absolute compare builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
+NOMIPS16 int test32 (v2sf a, v2sf b);
+NOMIPS16 int test33 (v2sf a, v2sf b);
+NOMIPS16 int test34 (v2sf a, v2sf b);
+NOMIPS16 int test35 (v2sf a, v2sf b);
+NOMIPS16 int test36 (v2sf a, v2sf b);
+NOMIPS16 int test37 (v2sf a, v2sf b);
+NOMIPS16 int test38 (v2sf a, v2sf b);
+NOMIPS16 int test39 (v2sf a, v2sf b);
+NOMIPS16 int test40 (v2sf a, v2sf b);
+NOMIPS16 int test41 (v2sf a, v2sf b);
+NOMIPS16 int test42 (v2sf a, v2sf b);
+NOMIPS16 int test43 (v2sf a, v2sf b);
+NOMIPS16 int test44 (v2sf a, v2sf b);
+NOMIPS16 int test45 (v2sf a, v2sf b);
+NOMIPS16 int test46 (v2sf a, v2sf b);
+NOMIPS16 int test47 (v2sf a, v2sf b);
+NOMIPS16 int test48 (v2sf a, v2sf b);
+NOMIPS16 int test49 (v2sf a, v2sf b);
+NOMIPS16 int test50 (v2sf a, v2sf b);
+NOMIPS16 int test51 (v2sf a, v2sf b);
+NOMIPS16 int test52 (v2sf a, v2sf b);
+NOMIPS16 int test53 (v2sf a, v2sf b);
+NOMIPS16 int test54 (v2sf a, v2sf b);
+NOMIPS16 int test55 (v2sf a, v2sf b);
+NOMIPS16 int test56 (v2sf a, v2sf b);
+NOMIPS16 int test57 (v2sf a, v2sf b);
+NOMIPS16 int test58 (v2sf a, v2sf b);
+NOMIPS16 int test59 (v2sf a, v2sf b);
+NOMIPS16 int test60 (v2sf a, v2sf b);
+NOMIPS16 int test61 (v2sf a, v2sf b);
+NOMIPS16 int test62 (v2sf a, v2sf b);
+NOMIPS16 int test63 (v2sf a, v2sf b);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  int little_endian;
+  v2sf a, b, c, d;
+  int i, j, k, l;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* cabs.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {-56, -78};
+  i = 0;
+  j = 0;
+  k = 0;
+  l = 0;
+  if (__builtin_mips_any_cabs_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_upper_cabs_eq_ps(a, b) != j)
+     abort ();
+  if (__builtin_mips_lower_cabs_eq_ps(a, b) != k)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_ps(a, b) != l)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {-12, -78};
+  i = 1;
+  if (little_endian)
+    {
+      j = 0;
+      k = 1;
+    }
+  else
+    {
+      j = 1;
+      k = 0;
+    }
+  l = 0;
+  if (__builtin_mips_any_cabs_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_upper_cabs_eq_ps(a, b) != j)
+     abort ();
+  if (__builtin_mips_lower_cabs_eq_ps(a, b) != k)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_ps(a, b) != l)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {-56, -34};
+  i = 1;
+  if (little_endian)
+    {
+      j = 1;
+      k = 0;
+    }
+  else
+    {
+      j = 0;
+      k = 1;
+    }
+  l = 0;
+  if (__builtin_mips_any_cabs_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_upper_cabs_eq_ps(a, b) != j)
+     abort ();
+  if (__builtin_mips_lower_cabs_eq_ps(a, b) != k)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_ps(a, b) != l)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {12, 34};
+  b = (v2sf) {-12, -34};
+  i = 1;
+  j = 1;
+  k = 1;
+  l = 1;
+  if (__builtin_mips_any_cabs_eq_ps(a, b) != i)
+     abort ();
+  if (__builtin_mips_upper_cabs_eq_ps(a, b) != j)
+     abort ();
+  if (__builtin_mips_lower_cabs_eq_ps(a, b) != k)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_ps(a, b) != l)
+     abort ();
+
+  /* Test all comparisons */
+  if (little_endian)
+    {
+      a = (v2sf) {1984.0, 10.58};
+      b = (v2sf) {-1984.0, -567.345};
+    }
+  else
+    {
+      a = (v2sf) {10.58, 1984.0};
+      b = (v2sf) {-567.345, -1984.0};
+    }
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 0)
+    abort ();
+  i = test7 (a, b);
+  if (i != 0)
+    abort ();
+  i = test8 (a, b);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 0)
+    abort ();
+  i = test16 (a, b);
+  if (i != 1)
+    abort ();
+  i = test17 (a, b);
+  if (i != 1)
+    abort ();
+  i = test18 (a, b);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b);
+  if (i != 1)
+    abort ();
+  i = test22 (a, b);
+  if (i != 0)
+    abort ();
+  i = test23 (a, b);
+  if (i != 0)
+    abort ();
+  i = test24 (a, b);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b);
+  if (i != 1)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b);
+  if (i != 1)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+  i = test32 (a, b);
+  if (i != 0)
+    abort ();
+  i = test33 (a, b);
+  if (i != 0)
+    abort ();
+  i = test34 (a, b);
+  if (i != 0)
+    abort ();
+  i = test35 (a, b);
+  if (i != 0)
+    abort ();
+  i = test36 (a, b);
+  if (i != 0)
+    abort ();
+  i = test37 (a, b);
+  if (i != 0)
+    abort ();
+  i = test38 (a, b);
+  if (i != 0)
+    abort ();
+  i = test39 (a, b);
+  if (i != 0)
+    abort ();
+  i = test40 (a, b);
+  if (i != 1)
+    abort ();
+  i = test41 (a, b);
+  if (i != 0)
+    abort ();
+  i = test42 (a, b);
+  if (i != 1)
+    abort ();
+  i = test43 (a, b);
+  if (i != 0)
+    abort ();
+  i = test44 (a, b);
+  if (i != 1)
+    abort ();
+  i = test45 (a, b);
+  if (i != 0)
+    abort ();
+  i = test46 (a, b);
+  if (i != 1)
+    abort ();
+  i = test47 (a, b);
+  if (i != 0)
+    abort ();
+  i = test48 (a, b);
+  if (i != 1)
+    abort ();
+  i = test49 (a, b);
+  if (i != 1)
+    abort ();
+  i = test50 (a, b);
+  if (i != 0)
+    abort ();
+  i = test51 (a, b);
+  if (i != 0)
+    abort ();
+  i = test52 (a, b);
+  if (i != 1)
+    abort ();
+  i = test53 (a, b);
+  if (i != 1)
+    abort ();
+  i = test54 (a, b);
+  if (i != 0)
+    abort ();
+  i = test55 (a, b);
+  if (i != 0)
+    abort ();
+  i = test56 (a, b);
+  if (i != 1)
+    abort ();
+  i = test57 (a, b);
+  if (i != 1)
+    abort ();
+  i = test58 (a, b);
+  if (i != 1)
+    abort ();
+  i = test59 (a, b);
+  if (i != 1)
+    abort ();
+  i = test60 (a, b);
+  if (i != 1)
+    abort ();
+  i = test61 (a, b);
+  if (i != 1)
+    abort ();
+  i = test62 (a, b);
+  if (i != 1)
+    abort ();
+  i = test63 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reverse arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a);
+  if (i != 0)
+    abort ();
+  i = test5 (b, a);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a);
+  if (i != 0)
+    abort ();
+  i = test7 (b, a);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a);
+  if (i != 1)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 1)
+    abort ();
+  i = test11 (b, a);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a);
+  if (i != 1)
+    abort ();
+  i = test13 (b, a);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a);
+  if (i != 0)
+    abort ();
+  i = test16 (b, a);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a);
+  if (i != 0)
+    abort ();
+  i = test21 (b, a);
+  if (i != 0)
+    abort ();
+  i = test22 (b, a);
+  if (i != 0)
+    abort ();
+  i = test23 (b, a);
+  if (i != 0)
+    abort ();
+  i = test24 (b, a);
+  if (i != 1)
+    abort ();
+  i = test25 (b, a);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a);
+  if (i != 1)
+    abort ();
+  i = test27 (b, a);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a);
+  if (i != 1)
+    abort ();
+  i = test29 (b, a);
+  if (i != 0)
+    abort ();
+  i = test30 (b, a);
+  if (i != 1)
+    abort ();
+  i = test31 (b, a);
+  if (i != 0)
+    abort ();
+  i = test32 (b, a);
+  if (i != 0)
+    abort ();
+  i = test33 (b, a);
+  if (i != 0)
+    abort ();
+  i = test34 (b, a);
+  if (i != 0)
+    abort ();
+  i = test35 (b, a);
+  if (i != 0)
+    abort ();
+  i = test36 (b, a);
+  if (i != 0)
+    abort ();
+  i = test37 (b, a);
+  if (i != 0)
+    abort ();
+  i = test38 (b, a);
+  if (i != 0)
+    abort ();
+  i = test39 (b, a);
+  if (i != 0)
+    abort ();
+  i = test40 (b, a);
+  if (i != 1)
+    abort ();
+  i = test41 (b, a);
+  if (i != 0)
+    abort ();
+  i = test42 (b, a);
+  if (i != 1)
+    abort ();
+  i = test43 (b, a);
+  if (i != 0)
+    abort ();
+  i = test44 (b, a);
+  if (i != 1)
+    abort ();
+  i = test45 (b, a);
+  if (i != 0)
+    abort ();
+  i = test46 (b, a);
+  if (i != 1)
+    abort ();
+  i = test47 (b, a);
+  if (i != 0)
+    abort ();
+  i = test48 (b, a);
+  if (i != 0)
+    abort ();
+  i = test49 (b, a);
+  if (i != 0)
+    abort ();
+  i = test50 (b, a);
+  if (i != 0)
+    abort ();
+  i = test51 (b, a);
+  if (i != 0)
+    abort ();
+  i = test52 (b, a);
+  if (i != 0)
+    abort ();
+  i = test53 (b, a);
+  if (i != 0)
+    abort ();
+  i = test54 (b, a);
+  if (i != 0)
+    abort ();
+  i = test55 (b, a);
+  if (i != 0)
+    abort ();
+  i = test56 (b, a);
+  if (i != 1)
+    abort ();
+  i = test57 (b, a);
+  if (i != 0)
+    abort ();
+  i = test58 (b, a);
+  if (i != 1)
+    abort ();
+  i = test59 (b, a);
+  if (i != 0)
+    abort ();
+  i = test60 (b, a);
+  if (i != 1)
+    abort ();
+  i = test61 (b, a);
+  if (i != 0)
+    abort ();
+  i = test62 (b, a);
+  if (i != 1)
+    abort ();
+  i = test63 (b, a);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all comparisons */
+  if (little_endian)
+    {
+      a = (v2sf) {qnan, qnan};
+      b = (v2sf) {-1984.0, -567.345};
+    }
+  else
+    {
+      a = (v2sf) {qnan, qnan};
+      b = (v2sf) {-567.345, -1984.0};
+    }
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 0)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b);
+  if (i != 1)
+    abort ();
+  i = test22 (a, b);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 0)
+    abort ();
+  i = test27 (a, b);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b);
+  if (i != 1)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+  i = test32 (a, b);
+  if (i != 0)
+    abort ();
+  i = test33 (a, b);
+  if (i != 0)
+    abort ();
+  i = test34 (a, b);
+  if (i != 0)
+    abort ();
+  i = test35 (a, b);
+  if (i != 0)
+    abort ();
+  i = test36 (a, b);
+  if (i != 1)
+    abort ();
+  i = test37 (a, b);
+  if (i != 1)
+    abort ();
+  i = test38 (a, b);
+  if (i != 1)
+    abort ();
+  i = test39 (a, b);
+  if (i != 1)
+    abort ();
+  i = test40 (a, b);
+  if (i != 0)
+    abort ();
+  i = test41 (a, b);
+  if (i != 0)
+    abort ();
+  i = test42 (a, b);
+  if (i != 0)
+    abort ();
+  i = test43 (a, b);
+  if (i != 0)
+    abort ();
+  i = test44 (a, b);
+  if (i != 1)
+    abort ();
+  i = test45 (a, b);
+  if (i != 1)
+    abort ();
+  i = test46 (a, b);
+  if (i != 1)
+    abort ();
+  i = test47 (a, b);
+  if (i != 1)
+    abort ();
+  i = test48 (a, b);
+  if (i != 0)
+    abort ();
+  i = test49 (a, b);
+  if (i != 0)
+    abort ();
+  i = test50 (a, b);
+  if (i != 0)
+    abort ();
+  i = test51 (a, b);
+  if (i != 0)
+    abort ();
+  i = test52 (a, b);
+  if (i != 1)
+    abort ();
+  i = test53 (a, b);
+  if (i != 1)
+    abort ();
+  i = test54 (a, b);
+  if (i != 1)
+    abort ();
+  i = test55 (a, b);
+  if (i != 1)
+    abort ();
+  i = test56 (a, b);
+  if (i != 0)
+    abort ();
+  i = test57 (a, b);
+  if (i != 0)
+    abort ();
+  i = test58 (a, b);
+  if (i != 0)
+    abort ();
+  i = test59 (a, b);
+  if (i != 0)
+    abort ();
+  i = test60 (a, b);
+  if (i != 1)
+    abort ();
+  i = test61 (a, b);
+  if (i != 1)
+    abort ();
+  i = test62 (a, b);
+  if (i != 1)
+    abort ();
+  i = test63 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_f_ps (a, b);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_f_ps (a, b);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_f_ps (a, b);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_f_ps (a, b);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_un_ps (a, b);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_un_ps (a, b);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_un_ps (a, b);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_un_ps (a, b);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_eq_ps (a, b);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_eq_ps (a, b);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_eq_ps (a, b);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_eq_ps (a, b);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ueq_ps (a, b);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ueq_ps (a, b);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ueq_ps (a, b);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ueq_ps (a, b);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_olt_ps (a, b);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_olt_ps (a, b);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_olt_ps (a, b);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_olt_ps (a, b);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ult_ps (a, b);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ult_ps (a, b);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ult_ps (a, b);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ult_ps (a, b);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ole_ps (a, b);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ole_ps (a, b);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ole_ps (a, b);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ole_ps (a, b);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ule_ps (a, b);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ule_ps (a, b);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ule_ps (a, b);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ule_ps (a, b);
+}
+
+NOMIPS16 int test32 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_sf_ps (a, b);
+}
+
+NOMIPS16 int test33 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_sf_ps (a, b);
+}
+
+NOMIPS16 int test34 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_sf_ps (a, b);
+}
+
+NOMIPS16 int test35 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_sf_ps (a, b);
+}
+
+NOMIPS16 int test36 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ngle_ps (a, b);
+}
+
+NOMIPS16 int test37 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ngle_ps (a, b);
+}
+
+NOMIPS16 int test38 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ngle_ps (a, b);
+}
+
+NOMIPS16 int test39 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ngle_ps (a, b);
+}
+
+NOMIPS16 int test40 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_seq_ps (a, b);
+}
+
+NOMIPS16 int test41 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_seq_ps (a, b);
+}
+
+NOMIPS16 int test42 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_seq_ps (a, b);
+}
+
+NOMIPS16 int test43 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_seq_ps (a, b);
+}
+
+NOMIPS16 int test44 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ngl_ps (a, b);
+}
+
+NOMIPS16 int test45 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ngl_ps (a, b);
+}
+
+NOMIPS16 int test46 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ngl_ps (a, b);
+}
+
+NOMIPS16 int test47 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ngl_ps (a, b);
+}
+
+NOMIPS16 int test48 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_lt_ps (a, b);
+}
+
+NOMIPS16 int test49 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_lt_ps (a, b);
+}
+
+NOMIPS16 int test50 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_lt_ps (a, b);
+}
+
+NOMIPS16 int test51 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_lt_ps (a, b);
+}
+
+NOMIPS16 int test52 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_nge_ps (a, b);
+}
+
+NOMIPS16 int test53 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_nge_ps (a, b);
+}
+
+NOMIPS16 int test54 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_nge_ps (a, b);
+}
+
+NOMIPS16 int test55 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_nge_ps (a, b);
+}
+
+NOMIPS16 int test56 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_le_ps (a, b);
+}
+
+NOMIPS16 int test57 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_le_ps (a, b);
+}
+
+NOMIPS16 int test58 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_le_ps (a, b);
+}
+
+NOMIPS16 int test59 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_le_ps (a, b);
+}
+
+NOMIPS16 int test60 (v2sf a, v2sf b)
+{
+  return __builtin_mips_any_cabs_ngt_ps (a, b);
+}
+
+NOMIPS16 int test61 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_cabs_ngt_ps (a, b);
+}
+
+NOMIPS16 int test62 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_cabs_ngt_ps (a, b);
+}
+
+NOMIPS16 int test63 (v2sf a, v2sf b)
+{
+  return __builtin_mips_all_cabs_ngt_ps (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-4.c
new file mode 100644
index 000000000..3d28d7f2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-4.c
@@ -0,0 +1,590 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Test MIPS-3D branch-if-any-four builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  v2sf a, b, c, d;
+  int i, j;
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {33, 44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {77, 88};
+  i = 0;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {11, 44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {77, 88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {33, 22};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {77, 88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {33, 44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {55, 88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {33, 44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {77, 66};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* c.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {11, 22};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {55, 66};
+  i = 1;
+  j = 1;
+  if (__builtin_mips_any_c_eq_4s(a, b, c, d) != i)
+    abort ();
+  if (__builtin_mips_all_c_eq_4s(a, b, c, d) != j)
+    abort ();
+
+  /* Test all comparisons */
+  a = (v2sf) {11, 33};
+  b = (v2sf) {33, 11};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {55, 88};
+
+  i = test0 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test8 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test16 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test24 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b, c, d);
+  if (i != 0)
+    abort ();
+
+  /* Reversed arguments */
+  i = test0 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test5 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test7 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test9 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test11 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test13 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test16 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test21 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test22 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test23 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test24 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test25 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test27 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test29 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test30 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test31 (b, a, d, c);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all comparisons */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {33, 11};
+  c = (v2sf) {qnan, qnan};
+  d = (v2sf) {55, 88};
+
+  i = test0 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test19 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test20 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test29 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b, c, d);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_f_4s (a, b, c, d);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_f_4s (a, b, c, d);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_un_4s (a, b, c, d);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_un_4s (a, b, c, d);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_eq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_eq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ueq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ueq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_olt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_olt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ult_4s (a, b, c, d);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ult_4s (a, b, c, d);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ole_4s (a, b, c, d);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ole_4s (a, b, c, d);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ule_4s (a, b, c, d);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ule_4s (a, b, c, d);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_sf_4s (a, b, c, d);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_sf_4s (a, b, c, d);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ngle_4s (a, b, c, d);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ngle_4s (a, b, c, d);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_seq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_seq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ngl_4s (a, b, c, d);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ngl_4s (a, b, c, d);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_lt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_lt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_nge_4s (a, b, c, d);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_nge_4s (a, b, c, d);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_le_4s (a, b, c, d);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_le_4s (a, b, c, d);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_c_ngt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_c_ngt_4s (a, b, c, d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-5.c
new file mode 100644
index 000000000..a433675ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-5.c
@@ -0,0 +1,590 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Test MIPS-3D absolute-compare & branch-if-any-four builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  v2sf a, b, c, d;
+  int i, j;
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-33, -44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-77, -88};
+  i = 0;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-11, -44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-77, -88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-33, -22};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-77, -88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-33, -44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-55, -88};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-33, -44};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-77, -66};
+  i = 1;
+  j = 0;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* cabs.eq.ps */
+  a = (v2sf) {11, 22};
+  b = (v2sf) {-11, -22};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-55, -66};
+  i = 1;
+  j = 1;
+  if (__builtin_mips_any_cabs_eq_4s(a, b, c, d) != i)
+     abort ();
+  if (__builtin_mips_all_cabs_eq_4s(a, b, c, d) != j)
+     abort ();
+
+  /* Test all comparisons */
+  a = (v2sf) {11, 33};
+  b = (v2sf) {-33, -11};
+  c = (v2sf) {55, 66};
+  d = (v2sf) {-55, -88};
+
+  i = test0 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test8 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test16 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test21 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test24 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b, c, d);
+  if (i != 0)
+    abort ();
+
+  /* Reversed arguments */
+  i = test0 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test5 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test7 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test9 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test11 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test13 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test16 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test21 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test22 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test23 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test24 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test25 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test27 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test29 (b, a, d, c);
+  if (i != 0)
+    abort ();
+  i = test30 (b, a, d, c);
+  if (i != 1)
+    abort ();
+  i = test31 (b, a, d, c);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all comparisons */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {-33, -11};
+  c = (v2sf) {qnan, qnan};
+  d = (v2sf) {-55, -88};
+
+  i = test0 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test19 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test20 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test29 (a, b, c, d);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b, c, d);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b, c, d);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_f_4s (a, b, c, d);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_f_4s (a, b, c, d);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_un_4s (a, b, c, d);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_un_4s (a, b, c, d);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_eq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_eq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ueq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ueq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_olt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_olt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ult_4s (a, b, c, d);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ult_4s (a, b, c, d);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ole_4s (a, b, c, d);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ole_4s (a, b, c, d);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ule_4s (a, b, c, d);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ule_4s (a, b, c, d);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_sf_4s (a, b, c, d);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_sf_4s (a, b, c, d);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ngle_4s (a, b, c, d);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ngle_4s (a, b, c, d);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_seq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_seq_4s (a, b, c, d);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ngl_4s (a, b, c, d);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ngl_4s (a, b, c, d);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_lt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_lt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_nge_4s (a, b, c, d);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_nge_4s (a, b, c, d);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_le_4s (a, b, c, d);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_le_4s (a, b, c, d);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_any_cabs_ngt_4s (a, b, c, d);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_all_cabs_ngt_4s (a, b, c, d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-6.c
new file mode 100644
index 000000000..e6b44f075
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-6.c
@@ -0,0 +1,284 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Test MIPS-3D absolute compare (floats) builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+NOMIPS16 int test0 (float a, float b);
+NOMIPS16 int test1 (float a, float b);
+NOMIPS16 int test2 (float a, float b);
+NOMIPS16 int test3 (float a, float b);
+NOMIPS16 int test4 (float a, float b);
+NOMIPS16 int test5 (float a, float b);
+NOMIPS16 int test6 (float a, float b);
+NOMIPS16 int test7 (float a, float b);
+NOMIPS16 int test8 (float a, float b);
+NOMIPS16 int test9 (float a, float b);
+NOMIPS16 int test10 (float a, float b);
+NOMIPS16 int test11 (float a, float b);
+NOMIPS16 int test12 (float a, float b);
+NOMIPS16 int test13 (float a, float b);
+NOMIPS16 int test14 (float a, float b);
+NOMIPS16 int test15 (float a, float b);
+
+NOMIPS16 int main ()
+{
+  float a, b;
+  int i;
+
+  /* cabs.eq.s */
+  a = 12;
+  b = -56;
+  i = 0;
+  if (__builtin_mips_cabs_eq_s(a, b) != i)
+     abort ();
+
+  /* cabs.eq.s */
+  a = 12;
+  b = -12;
+  i = 1;
+  if (__builtin_mips_cabs_eq_s(a, b) != i)
+     abort ();
+
+  /* Test all comparisons */
+  a = 10.58;
+  b = 567.345;
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 1)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 0)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reversed arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a);
+  if (i != 0)
+    abort ();
+  i = test5 (b, a);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a);
+  if (i != 0)
+    abort ();
+  i = test7 (b, a);
+  if (i != 0)
+    abort ();
+  i = test8 (b, a);
+  if (i != 0)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 0)
+    abort ();
+  i = test11 (b, a);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a);
+  if (i != 0)
+    abort ();
+  i = test13 (b, a);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a);
+  if (i != 0)
+    abort ();
+  i = test15 (b, a);
+  if (i != 0)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all comparisons */
+  a = 1.0f/0.0f - 1.0f/0.0f; // QNaN
+  b = 567.345;
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 1)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 0)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 1)
+    abort ();
+  i = test10 (a, b);
+  if (i != 0)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 0)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (float a, float b)
+{
+  return __builtin_mips_cabs_f_s (a, b);
+}
+
+NOMIPS16 int test1 (float a, float b)
+{
+  return __builtin_mips_cabs_un_s (a, b);
+}
+
+NOMIPS16 int test2 (float a, float b)
+{
+  return __builtin_mips_cabs_eq_s (a, b);
+}
+
+NOMIPS16 int test3 (float a, float b)
+{
+  return __builtin_mips_cabs_ueq_s (a, b);
+}
+
+NOMIPS16 int test4 (float a, float b)
+{
+  return __builtin_mips_cabs_olt_s (a, b);
+}
+
+NOMIPS16 int test5 (float a, float b)
+{
+  return __builtin_mips_cabs_ult_s (a, b);
+}
+
+NOMIPS16 int test6 (float a, float b)
+{
+  return __builtin_mips_cabs_ole_s (a, b);
+}
+
+NOMIPS16 int test7 (float a, float b)
+{
+  return __builtin_mips_cabs_ule_s (a, b);
+}
+
+NOMIPS16 int test8 (float a, float b)
+{
+  return __builtin_mips_cabs_sf_s (a, b);
+}
+
+NOMIPS16 int test9 (float a, float b)
+{
+  return __builtin_mips_cabs_ngle_s (a, b);
+}
+
+NOMIPS16 int test10 (float a, float b)
+{
+  return __builtin_mips_cabs_seq_s (a, b);
+}
+
+NOMIPS16 int test11 (float a, float b)
+{
+  return __builtin_mips_cabs_ngl_s (a, b);
+}
+
+NOMIPS16 int test12 (float a, float b)
+{
+  return __builtin_mips_cabs_lt_s (a, b);
+}
+
+NOMIPS16 int test13 (float a, float b)
+{
+  return __builtin_mips_cabs_nge_s (a, b);
+}
+
+NOMIPS16 int test14 (float a, float b)
+{
+  return __builtin_mips_cabs_le_s (a, b);
+}
+
+NOMIPS16 int test15 (float a, float b)
+{
+  return __builtin_mips_cabs_ngt_s (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-7.c
new file mode 100644
index 000000000..2531ddf8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-7.c
@@ -0,0 +1,284 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Test MIPS-3D absolute compare (doubles) builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+NOMIPS16 int test0 (double a, double b);
+NOMIPS16 int test1 (double a, double b);
+NOMIPS16 int test2 (double a, double b);
+NOMIPS16 int test3 (double a, double b);
+NOMIPS16 int test4 (double a, double b);
+NOMIPS16 int test5 (double a, double b);
+NOMIPS16 int test6 (double a, double b);
+NOMIPS16 int test7 (double a, double b);
+NOMIPS16 int test8 (double a, double b);
+NOMIPS16 int test9 (double a, double b);
+NOMIPS16 int test10 (double a, double b);
+NOMIPS16 int test11 (double a, double b);
+NOMIPS16 int test12 (double a, double b);
+NOMIPS16 int test13 (double a, double b);
+NOMIPS16 int test14 (double a, double b);
+NOMIPS16 int test15 (double a, double b);
+
+NOMIPS16 int main ()
+{
+  double a, b;
+  int i;
+
+  /* cabs.eq.d */
+  a = 12;
+  b = -56;
+  i = 0;
+  if (__builtin_mips_cabs_eq_d(a, b) != i)
+     abort ();
+
+  /* cabs.eq.d */
+  a = 12;
+  b = -12;
+  i = 1;
+  if (__builtin_mips_cabs_eq_d(a, b) != i)
+     abort ();
+
+  /* Test all operators */
+  a = 1984.0;
+  b = 1984.0;
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reverse arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 1)
+    abort ();
+  i = test3 (b, a);
+  if (i != 1)
+    abort ();
+  i = test4 (b, a);
+  if (i != 0)
+    abort ();
+  i = test5 (b, a);
+  if (i != 0)
+    abort ();
+  i = test6 (b, a);
+  if (i != 1)
+    abort ();
+  i = test7 (b, a);
+  if (i != 1)
+    abort ();
+  i = test8 (b, a);
+  if (i != 0)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 1)
+    abort ();
+  i = test11 (b, a);
+  if (i != 1)
+    abort ();
+  i = test12 (b, a);
+  if (i != 0)
+    abort ();
+  i = test13 (b, a);
+  if (i != 0)
+    abort ();
+  i = test14 (b, a);
+  if (i != 1)
+    abort ();
+  i = test15 (b, a);
+  if (i != 1)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all operators */
+  a = 1.0/0.0 - 1.0/0.0; // QNaN
+  b = 1.0/0.0 - 1.0/0.0; // QNaN
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 1)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 0)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 1)
+    abort ();
+  i = test10 (a, b);
+  if (i != 0)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 0)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (double a, double b)
+{
+  return __builtin_mips_cabs_f_d (a, b);
+}
+
+NOMIPS16 int test1 (double a, double b)
+{
+  return __builtin_mips_cabs_un_d (a, b);
+}
+
+NOMIPS16 int test2 (double a, double b)
+{
+  return __builtin_mips_cabs_eq_d (a, b);
+}
+
+NOMIPS16 int test3 (double a, double b)
+{
+  return __builtin_mips_cabs_ueq_d (a, b);
+}
+
+NOMIPS16 int test4 (double a, double b)
+{
+  return __builtin_mips_cabs_olt_d (a, b);
+}
+
+NOMIPS16 int test5 (double a, double b)
+{
+  return __builtin_mips_cabs_ult_d (a, b);
+}
+
+NOMIPS16 int test6 (double a, double b)
+{
+  return __builtin_mips_cabs_ole_d (a, b);
+}
+
+NOMIPS16 int test7 (double a, double b)
+{
+  return __builtin_mips_cabs_ule_d (a, b);
+}
+
+NOMIPS16 int test8 (double a, double b)
+{
+  return __builtin_mips_cabs_sf_d (a, b);
+}
+
+NOMIPS16 int test9 (double a, double b)
+{
+  return __builtin_mips_cabs_ngle_d (a, b);
+}
+
+NOMIPS16 int test10 (double a, double b)
+{
+  return __builtin_mips_cabs_seq_d (a, b);
+}
+
+NOMIPS16 int test11 (double a, double b)
+{
+  return __builtin_mips_cabs_ngl_d (a, b);
+}
+
+NOMIPS16 int test12 (double a, double b)
+{
+  return __builtin_mips_cabs_lt_d (a, b);
+}
+
+NOMIPS16 int test13 (double a, double b)
+{
+  return __builtin_mips_cabs_nge_d (a, b);
+}
+
+NOMIPS16 int test14 (double a, double b)
+{
+  return __builtin_mips_cabs_le_d (a, b);
+}
+
+NOMIPS16 int test15 (double a, double b)
+{
+  return __builtin_mips_cabs_ngt_d (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-8.c
new file mode 100644
index 000000000..1d199d7d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-8.c
@@ -0,0 +1,630 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Test MIPS-3D absolute compare and conditional move builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__((vector_size(8)));
+
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  v2sf a, b, c, d, e, f;
+
+  /* Case 1 {diff, diff} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {-7, -6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 123};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 78};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 2 {same, diff} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {-5, -6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 3 {diff, same} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {-9, -12};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 4 {same, same} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {-5, -12};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 78};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 123};
+  if (!__builtin_mips_all_c_eq_ps (e, f))
+    abort ();
+
+  /* Test all 16 operators */
+  a = (v2sf) {-123, 123};
+  b = (v2sf) {1000, -1000};
+  c = (v2sf) {-33, 123};
+  d = (v2sf) {8, -78};
+
+  e = test0 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c))
+    abort ();
+  e = test1 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test3 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test4 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test5 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test6 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test7 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test8 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test9 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test10 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test11 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test12 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test13 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test14 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test15 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test16 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test17 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test18 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test19 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test20 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test21 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test22 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test23 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test24 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test25 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test26 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test27 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test28 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test29 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test30 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test31 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  /* Reversed arguments */
+  e = test0 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c))
+    abort ();
+  e = test1 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test3 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test4 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test5 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test6 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test7 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test8 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test9 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test10 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test11 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test12 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test13 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test14 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test15 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test16 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test17 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test18 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test19 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test20 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test21 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test22 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test23 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test24 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test25 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test26 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test27 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test28 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test29 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test30 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test31 (b, a, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test all 16 operators */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {1000, -1000};
+  c = (v2sf) {8, -78};
+  d = (v2sf) {-33, 123};
+
+  e = test0 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c))
+    abort ();
+  e = test1 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test3 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test4 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test5 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test6 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test7 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test8 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test9 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test10 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test11 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test12 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test13 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test14 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test15 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test16 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test17 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test18 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test19 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test20 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test21 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test22 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test23 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test24 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test25 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test26 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test27 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+
+  e = test28 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+  e = test29 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+
+  e = test30 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, d)) 
+    abort ();
+  e = test31 (a, b, c, d);
+  if (!__builtin_mips_all_c_eq_ps (e, c)) 
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_f_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_f_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_un_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_un_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_eq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_eq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ueq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ueq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_olt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_olt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ult_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ult_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ole_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ole_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ule_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ule_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_sf_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_sf_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ngle_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ngle_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_seq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_seq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ngl_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ngl_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_lt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_lt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_nge_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_nge_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_le_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_le_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movt_cabs_ngt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return  __builtin_mips_movf_cabs_ngt_ps (a, b, c, d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-9.c
new file mode 100644
index 000000000..d697efded
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-3d-9.c
@@ -0,0 +1,158 @@
+/* { dg-do run } */
+/* { dg-options "-mips3d" } */
+
+/* Matrix Multiplications */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__((vector_size(8)));
+
+float a[4] = {1.1, 2.2, 3.3, 4.4};
+float b[4][4] = {{1, 2, 3, 4},
+                 {5, 6, 7, 8},
+                 {9, 10, 11, 12},
+                 {13, 14, 15, 16}};
+
+float c[4]; /* Result for matrix_multiply1() */
+float d[4]; /* Result for matrix_multiply2() */
+float e[4]; /* Result for matrix_multiply3() */
+float f[4]; /* Result for matrix_multiply4() */
+
+void matrix_multiply1();
+NOMIPS16 void matrix_multiply2();
+NOMIPS16 void matrix_multiply3();
+NOMIPS16 void matrix_multiply4();
+
+int main ()
+{
+  int i;
+
+  /* Version 1. Use float calculations */
+  matrix_multiply1();
+
+  /* Version 2. Use paired-single instructions inside the inner loop*/
+  matrix_multiply2();
+  for (i = 0; i < 4; i++)
+    if (d[i] != c[i])
+      abort();
+
+  /* Version 3. Use paired-single instructions and unroll the inner loop */
+  matrix_multiply3();
+  for (i = 0; i < 4; i++)
+    if (e[i] != c[i])
+      abort();
+
+  /* Version 4. Use paired-single instructions and unroll all loops */
+  matrix_multiply4();
+  for (i = 0; i < 4; i++)
+    if (f[i] != c[i])
+      abort();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+void matrix_multiply1()
+{
+  int i, j;
+
+  for (i = 0; i < 4; i++)
+   {
+     c[i] = 0.0;
+
+     for (j = 0; j < 4; j ++)
+       c[i] += a[j] * b[j][i]; 
+   }
+}
+
+NOMIPS16 void matrix_multiply2()
+{
+  int i, j;
+  v2sf m1, m2;
+  v2sf result, temp;
+
+  for (i = 0; i < 4; i++)
+   {
+     result = (v2sf) {0.0, 0.0};
+
+     for (j = 0; j < 4; j+=2)
+     {
+       /* Load two float values into m1 */
+       m1 = (v2sf) {a[j], a[j+1]};
+       m2 = (v2sf) {b[j][i], b[j+1][i]};
+
+       /* Multiply and add */
+       result += m1 * m2;
+     }
+     
+     /* Reduction add at the end */
+     temp = __builtin_mips_addr_ps (result, result);
+     d[i] = __builtin_mips_cvt_s_pl (temp);
+   }
+}
+
+NOMIPS16 void matrix_multiply3()
+{
+  int i;
+  v2sf m1, m2, n1, n2;
+  v2sf result, temp;
+
+  m1 = (v2sf) {a[0], a[1]};
+  m2 = (v2sf) {a[2], a[3]};
+
+  for (i = 0; i < 4; i++)
+   {
+     n1 = (v2sf) {b[0][i], b[1][i]};
+     n2 = (v2sf) {b[2][i], b[3][i]};
+
+     /* Multiply and add */
+     result = m1 * n1 + m2 * n2;
+     
+     /* Reduction add at the end */
+     temp = __builtin_mips_addr_ps (result, result);
+     e[i] = __builtin_mips_cvt_s_pl (temp);
+   }
+}
+
+NOMIPS16 void matrix_multiply4()
+{
+  v2sf m1, m2;
+  v2sf n1, n2, n3, n4, n5, n6, n7, n8;
+  v2sf temp1, temp2, temp3, temp4;
+  v2sf result1, result2;
+
+  /* Load a[0] a[1] values into m1
+     Load a[2] a[3] values into m2 */
+  m1 = (v2sf) {a[0], a[1]};
+  m2 = (v2sf) {a[2], a[3]};
+
+  /* Load b[0][0] b[1][0] values into n1
+     Load b[2][0] b[3][0] values into n2
+     Load b[0][1] b[1][1] values into n3
+     Load b[2][1] b[3][1] values into n4
+     Load b[0][2] b[1][2] values into n5
+     Load b[2][2] b[3][2] values into n6
+     Load b[0][3] b[1][3] values into n7
+     Load b[2][3] b[3][3] values into n8 */
+  n1 = (v2sf) {b[0][0], b[1][0]};
+  n2 = (v2sf) {b[2][0], b[3][0]};
+  n3 = (v2sf) {b[0][1], b[1][1]};
+  n4 = (v2sf) {b[2][1], b[3][1]};
+  n5 = (v2sf) {b[0][2], b[1][2]};
+  n6 = (v2sf) {b[2][2], b[3][2]};
+  n7 = (v2sf) {b[0][3], b[1][3]};
+  n8 = (v2sf) {b[2][3], b[3][3]};
+
+  temp1 = m1 * n1 + m2 * n2;
+  temp2 = m1 * n3 + m2 * n4;
+  temp3 = m1 * n5 + m2 * n6;
+  temp4 = m1 * n7 + m2 * n8;
+
+  result1 = __builtin_mips_addr_ps (temp1, temp2);
+  result2 = __builtin_mips_addr_ps (temp3, temp4);
+  
+  f[0] = __builtin_mips_cvt_s_pu (result1);
+  f[1] = __builtin_mips_cvt_s_pl (result1);
+  f[2] = __builtin_mips_cvt_s_pu (result2);
+  f[3] = __builtin_mips_cvt_s_pl (result2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/README b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/README
new file mode 100644
index 000000000..b7a46e4b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/README
@@ -0,0 +1,27 @@
+These tests are meant to test the interoperability of PIC and nonpic objects for mips.
+This table shows the various combinations and each case is tested by one of the nonpic tests.
+Test Case	The PIC code        	The non-PIC code        The result (stub and/or PLT)
+
+main-1.c	nothing           	nothing              	Neither (trivial)
+main-2.c	nothing           	call only		PLT entry
+main-3.c	nothing           	address taken only	Neither (* But creating a PLT entry is valid)
+main-4.c	nothing           	address and call	PLT entry
+main-5.c	call only           	nothing			.MIPS.stubs entry
+main-6.c	call only           	call only		.MIPS.stubs and PLT
+main-7.c	call only           	address taken only	.MIPS.stubs (* Also creating a PLT entry is valid)
+main-8.c	call only           	address and call	.MIPS.stubs and PLT entry
+main-9.c	address taken only	nothing			Neither
+main-10.c	address taken only	call only		PLT entry
+main-11.c	address taken only	address taken only	Neither (* But creating a PLT entry is valid)
+main-12.c	address taken only	address and call	PLT entry
+main-13.c	address and call	nothing			Neither
+main-14.c	address and call	call only		PLT entry
+main-15.c	address and call	address taken only	Neither (* But creating a PLT entry is valid)
+main-16.c	address and call	address and call	PLT entry
+
+
+Copyright (C) 2008-2014 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c
new file mode 100644
index 000000000..2f428717a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-1.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-nothing.o nonpic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_nothing ();
+  pic_nothing ();
+
+  if (hit_nonpic_nothing != 1)
+    abort ();
+
+  if (hit_pic_nothing != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c
new file mode 100644
index 000000000..6c3601861
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-10.c
@@ -0,0 +1,18 @@
+/* { dg-options "nonpic-call.o pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_call ();
+  pic_addr ();
+
+  if (hit_nonpic_call != 1)
+    abort ();
+
+  if (hit_pic_addr != 2)
+    abort ();
+
+  exit (0);
+
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c
new file mode 100644
index 000000000..1d8a6d20c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-11.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr.o pic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr ();
+  pic_addr ();
+
+  if (hit_nonpic_addr != 1)
+    abort ();
+
+  if (hit_pic_addr != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c
new file mode 100644
index 000000000..f57b5ce17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-12.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr-call.o pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr_call ();
+  pic_addr ();
+
+  if (hit_nonpic_addr_call != 1)
+    abort ();
+
+  if (hit_pic_addr != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c
new file mode 100644
index 000000000..d2b88e1f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-13.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_nothing ();
+  pic_addr_call ();
+
+  if (hit_nonpic_nothing != 1)
+    abort ();
+
+  if (hit_pic_addr_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c
new file mode 100644
index 000000000..6318a2240
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-14.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-call.o pic-addr.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_call ();
+  pic_addr_call ();
+
+  if (hit_nonpic_call != 1)
+    abort ();
+
+  if (hit_pic_addr_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c
new file mode 100644
index 000000000..1c165043a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-15.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr ();
+  pic_addr_call ();
+
+  if (hit_nonpic_addr != 1)
+    abort ();
+
+  if (hit_pic_addr_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c
new file mode 100644
index 000000000..3119979d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-16.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr-call.o pic-receive-fn-addr.o pic-addr-call.o nonpic-receive-fn-addr.o pic-nothing.o nonpic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr_call ();
+  pic_addr_call ();
+
+  if (hit_nonpic_addr_call != 1)
+    abort ();
+
+  if (hit_pic_addr_call != 1)
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c
new file mode 100644
index 000000000..8a66e7a7a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-2.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-addr.o nonpic-call.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_call ();
+  pic_nothing ();
+
+  if (hit_nonpic_call != 1)
+    abort ();
+
+  if (hit_pic_nothing != 2)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c
new file mode 100644
index 000000000..c9c8dac70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-3.c
@@ -0,0 +1,17 @@
+/* { dg-options "nonpic-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr ();
+  pic_nothing ();
+
+  if (hit_nonpic_addr != 1)
+    abort ();
+
+  if (hit_pic_nothing != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c
new file mode 100644
index 000000000..c10c213ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-4.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-addr.o pic-receive-fn-addr.o nonpic-addr-call.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_addr_call ();
+  pic_nothing ();
+
+  if (hit_nonpic_addr_call != 1)
+    abort ();
+
+  if (hit_pic_nothing != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c
new file mode 100644
index 000000000..9b6dd8aff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-5.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-addr.o pic-call.o nonpic-addr.o pic-receive-fn-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  nonpic_nothing ();
+  pic_call ();
+
+  if (hit_nonpic_nothing != 2)
+    abort ();
+
+  if (hit_pic_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c
new file mode 100644
index 000000000..90b220f0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-6.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-call.o nonpic-call.o nonpic-addr.o pic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  pic_call ();
+  nonpic_call ();
+
+  if (hit_pic_call != 1)
+    abort ();
+
+  if (hit_nonpic_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c
new file mode 100644
index 000000000..8cef63f3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-7.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-call.o nonpic-addr.o nonpic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  pic_call ();
+  nonpic_addr ();
+
+  if (hit_pic_call != 1)
+    abort ();
+
+  if (hit_nonpic_addr != 2)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c
new file mode 100644
index 000000000..0200bf2dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-8.c
@@ -0,0 +1,17 @@
+/* { dg-options "pic-call.o nonpic-addr-call.o nonpic-addr.o nonpic-receive-fn-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  pic_call ();
+  nonpic_addr_call ();
+
+  if (hit_pic_call != 1)
+    abort ();
+
+  if (hit_nonpic_addr_call != 1)
+    abort ();
+
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c
new file mode 100644
index 000000000..4144172cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/main-9.c
@@ -0,0 +1,10 @@
+/* { dg-options "pic-addr.o pic-receive-fn-addr.o nonpic-nothing.o pic-nothing.o" } */
+
+#include "mips-nonpic.h"
+
+main ()
+{
+  pic_addr ();
+  nonpic_nothing ();
+  exit (0);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp
new file mode 100644
index 000000000..d99b3d183
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.exp
@@ -0,0 +1,54 @@
+#   Copyright (C) 2008-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+load_lib gcc-dg.exp
+load_lib target-supports.exp
+
+# Exit immediately if this isn't a MIPS target.
+if ![istarget mips*-*-*] {
+  return
+}
+
+# Pic and nonpic are not link-compatible for VXWorks targets.
+if [istarget mips*-*-vxworks] {
+  return
+}
+
+if { ![check_effective_target_fpic] } {
+  return
+}
+
+dg-init
+
+set old-dg-do-what-default "${dg-do-what-default}"
+set dg-do-what-default "assemble"
+
+foreach testcase [lsort [glob -nocomplain $srcdir/$subdir/pic-*.c]] {
+    verbose "Compiling [file tail [file dirname $testcase]]/[file tail $testcase]"
+    dg-test -keep-output $testcase "-fpic" ""
+}
+
+foreach testcase [lsort [glob -nocomplain $srcdir/$subdir/nonpic-*.c]] {
+    verbose "Compiling [file tail [file dirname $testcase]]/[file tail $testcase]"
+    dg-test -keep-output $testcase "-fno-pic" ""
+}
+
+set dg-do-what-default "run"
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/main-*.c]] "-fno-pic" ""
+
+set dg-do-what-default "${old-dg-do-what-default}"
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h
new file mode 100644
index 000000000..e9fe99218
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/mips-nonpic.h
@@ -0,0 +1,20 @@
+extern int hit_pic_addr;
+extern int hit_pic_addr_call;
+extern int hit_pic_nothing;
+extern int hit_pic_call;
+
+extern int hit_nonpic_addr;
+extern int hit_nonpic_addr_call;
+extern int hit_nonpic_call;
+extern int hit_nonpic_nothing;
+
+extern void nonpic_addr (void);
+extern void nonpic_nothing (void);
+extern void nonpic_receive_fn_addr (void *);
+
+extern void pic_addr (void);
+extern void pic_receive_fn_addr (void *);
+extern void pic_nothing (void);
+
+extern void abort (void);
+extern void exit (int);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c
new file mode 100644
index 000000000..19d0e4349
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr-call.c
@@ -0,0 +1,8 @@
+#include "mips-nonpic.h"
+int hit_nonpic_addr_call = 0;
+void
+nonpic_addr_call (void)
+{
+  hit_nonpic_addr_call++;
+  pic_receive_fn_addr (&pic_nothing);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c
new file mode 100644
index 000000000..c919e83b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-addr.c
@@ -0,0 +1,8 @@
+#include "mips-nonpic.h"
+int hit_nonpic_addr = 0;
+void
+nonpic_addr ()
+{
+  nonpic_receive_fn_addr (&nonpic_nothing);
+  hit_nonpic_addr++;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c
new file mode 100644
index 000000000..8d368b42e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-call.c
@@ -0,0 +1,9 @@
+#include "mips-nonpic.h"
+int hit_nonpic_call = 0;
+void
+nonpic_call ()
+{
+ pic_nothing ();
+ pic_addr ();
+ hit_nonpic_call++;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c
new file mode 100644
index 000000000..90356fb24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-nothing.c
@@ -0,0 +1,7 @@
+#include "mips-nonpic.h"
+int hit_nonpic_nothing = 0;
+void
+nonpic_nothing ()
+{
+  hit_nonpic_nothing++;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c
new file mode 100644
index 000000000..8b548c9ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/nonpic-receive-fn-addr.c
@@ -0,0 +1,7 @@
+#include "mips-nonpic.h"
+void
+nonpic_receive_fn_addr (void *x)
+{
+  if (x != &nonpic_nothing)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c
new file mode 100644
index 000000000..2db729392
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr-call.c
@@ -0,0 +1,8 @@
+#include "mips-nonpic.h"
+int hit_pic_addr_call = 0;
+void
+pic_addr_call (void)
+{
+  hit_pic_addr_call++;
+  nonpic_receive_fn_addr (&nonpic_nothing);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c
new file mode 100644
index 000000000..a90739235
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-addr.c
@@ -0,0 +1,8 @@
+#include "mips-nonpic.h"
+int hit_pic_addr = 0;
+void
+pic_addr ()
+{
+  pic_receive_fn_addr (&pic_nothing);
+  hit_pic_addr++;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c
new file mode 100644
index 000000000..0c73b9333
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-call.c
@@ -0,0 +1,9 @@
+#include "mips-nonpic.h"
+int hit_pic_call = 0;
+void
+pic_call ()
+{
+ nonpic_nothing ();
+ nonpic_addr ();
+ hit_pic_call++;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c
new file mode 100644
index 000000000..3e4539081
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-nothing.c
@@ -0,0 +1,7 @@
+#include "mips-nonpic.h"
+int hit_pic_nothing = 0;
+void
+pic_nothing ()
+{
+  hit_pic_nothing++;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c
new file mode 100644
index 000000000..4a40e0a18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-nonpic/pic-receive-fn-addr.c
@@ -0,0 +1,7 @@
+#include "mips-nonpic.h"
+void
+pic_receive_fn_addr (void *x)
+{
+  if (x != &pic_nothing)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-prepend-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-prepend-1.c
new file mode 100644
index 000000000..126dbebcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-prepend-1.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mdspr2" } */
+/* { dg-final { scan-assembler "prepend\[^\n\]*,10" } } */
+
+NOMIPS16 int
+foo (int x, int y)
+{
+  return __builtin_mips_prepend (x, y, 42);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-1.c
new file mode 100644
index 000000000..73598a840
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-1.c
@@ -0,0 +1,271 @@
+/* { dg-do run } */
+/* { dg-options "-mpaired-single" } */
+
+/* Test v2sf calculations */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size (8)));
+
+v2sf A = {100, 200};
+
+/* Init from float */
+v2sf init (float a, float b)
+{
+  return (v2sf) {a, b};
+}
+
+/* Move between registers */
+v2sf move (v2sf a)
+{
+  return a;
+}
+
+/* Load from memory */
+v2sf load ()
+{
+  return A;
+}
+
+/* Store to memory */ 
+void store (v2sf a)
+{
+  A = a;
+}
+
+/* Add */ 
+v2sf add (v2sf a, v2sf b)
+{
+  return a + b;
+}
+
+/* Subtract */ 
+v2sf sub (v2sf a, v2sf b)
+{
+  return a - b;
+}
+
+/* Negate */
+v2sf neg (v2sf a)
+{
+  return - a;
+}
+
+/* Multiply */ 
+v2sf mul (v2sf a, v2sf b)
+{
+  return a * b;
+}
+
+/* Multiply and add */ 
+v2sf madd (v2sf a, v2sf b, v2sf c)
+{
+  return a * b + c;
+}
+
+/* Multiply and subtract */ 
+v2sf msub (v2sf a, v2sf b, v2sf c)
+{
+  return a * b - c;
+}
+
+/* Negate Multiply and add */ 
+v2sf nmadd (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b + c);
+}
+
+/* Negate Multiply and subtract */ 
+v2sf nmsub (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b - c);
+}
+
+/* Conditional Move */ 
+v2sf cond_move1 (v2sf a, v2sf b, long i)
+{
+  if (i > 0)
+    return a;
+  else
+    return b;
+}
+
+/* Conditional Move */ 
+v2sf cond_move2 (v2sf a, v2sf b, int i)
+{
+  if (i > 0)
+    return a;
+  else
+    return b;
+}
+
+/* Conditional Move */ 
+v2sf cond_move3 (v2sf a, v2sf b, float i)
+{
+  if (i > 0.0)
+    return a;
+  else
+    return b;
+}
+
+/* Conditional Move */ 
+v2sf cond_move4 (v2sf a, v2sf b, double i)
+{
+  if (i > 0.0)
+    return a;
+  else
+    return b;
+}
+
+NOMIPS16 int main()
+{
+  v2sf a, b, c, d, e, f;
+  float f1, f2;
+
+  f1 = 1.2;
+  f2 = 3.4;
+  a = init (f1, f2);
+  b = (v2sf) {1.2, 3.4};
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  a = (v2sf) {1.2, 2.3};
+  b = (v2sf) {5.3, 6.1};
+  b = move (a);
+
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  a = (v2sf) {1.2, 2.3};
+  b = (v2sf) {5.3, 6.1};
+  c = add (a, b);
+  d = (v2sf) {6.5, 8.4};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = sub (a, b);
+  d = (v2sf) {-4, 6};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = mul (a, b);
+  d = (v2sf) {5, 72};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {5, 6};
+  d = madd (a, b, c);
+  e = (v2sf) {10, 78};
+  if (!__builtin_mips_upper_c_eq_ps (d, e) ||
+      !__builtin_mips_lower_c_eq_ps (d, e))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {5, 6};
+  d = msub (a, b, c);
+  e = (v2sf) {0, 66};
+  if (!__builtin_mips_upper_c_eq_ps (d, e) ||
+      !__builtin_mips_lower_c_eq_ps (d, e))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {5, 6};
+  d = nmadd (a, b, c);
+  e = (v2sf) {-10, -78};
+  if (!__builtin_mips_upper_c_eq_ps (d, e) ||
+      !__builtin_mips_lower_c_eq_ps (d, e))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {5, 6};
+  d = nmsub (a, b, c);
+  e = (v2sf) {0, -66};
+  if (!__builtin_mips_upper_c_eq_ps (d, e) ||
+      !__builtin_mips_lower_c_eq_ps (d, e))
+    abort ();
+
+  a = (v2sf) {98, 12};
+  b = neg (a);
+  c = (v2sf) {-98, -12};
+  if (!__builtin_mips_upper_c_eq_ps (b, c) ||
+      !__builtin_mips_lower_c_eq_ps (b, c))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = cond_move1 (a, b, 1000);
+  if (!__builtin_mips_upper_c_eq_ps (c, a) ||
+      !__builtin_mips_lower_c_eq_ps (c, a))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = cond_move2 (a, b, -1000);
+  if (!__builtin_mips_upper_c_eq_ps (c, b) ||
+      !__builtin_mips_lower_c_eq_ps (c, b))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = cond_move3 (a, b, 9.0);
+  if (!__builtin_mips_upper_c_eq_ps (c, a) ||
+      !__builtin_mips_lower_c_eq_ps (c, a))
+    abort ();
+
+  a = (v2sf) {1, 12};
+  b = (v2sf) {5, 6};
+  c = cond_move4 (a, b, -10.0);
+  if (!__builtin_mips_upper_c_eq_ps (c, b) ||
+      !__builtin_mips_lower_c_eq_ps (c, b))
+    abort ();
+
+  a = (v2sf) {5, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  a = (v2sf) {5, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  a = load();
+  b = (v2sf) {100, 200};
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  a = (v2sf) {123, 321};
+  store (a);
+  b = load();
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-2.c
new file mode 100644
index 000000000..526425586
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-2.c
@@ -0,0 +1,134 @@
+/* { dg-do run } */
+/* { dg-options "-mpaired-single" } */
+
+/* Test MIPS paired-single builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int main ()
+{
+  int little_endian;
+  v2sf a, b, c, d;
+  float e,f;
+  int i;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* pll.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_pll_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {3, 1};
+  else // big endian
+    d = (v2sf) {2, 4};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* pul.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_pul_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {3, 2};
+  else // big endian
+    d = (v2sf) {1, 4};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* plu.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_plu_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {4, 1};
+  else // big endian
+    d = (v2sf) {2, 3};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* puu.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_puu_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {4, 2};
+  else // big endian
+    d = (v2sf) {1, 3};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* cvt.ps.s */
+  e = 3.4;
+  f = 4.5; 
+  a = __builtin_mips_cvt_ps_s (e, f);
+  if (little_endian) // little endian
+    b = (v2sf) {4.5, 3.4};
+  else // big endian
+    b = (v2sf) {3.4, 4.5};
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  /* cvt.s.pl */
+  a = (v2sf) {35.1, 120.2};
+  e = __builtin_mips_cvt_s_pl (a);
+  if (little_endian) // little endian
+    f = 35.1; 
+  else // big endian
+    f = 120.2;
+  if (e != f)
+    abort ();
+
+  /* cvt.s.pu */
+  a = (v2sf) {30.0, 100.0};
+  e = __builtin_mips_cvt_s_pu (a);
+  if (little_endian) // little endian
+    f = 100.0;
+  else // big endian
+    f = 30.0; 
+  if (e != f)
+    abort ();
+
+  /* abs.ps */
+  a = (v2sf) {-3.4, -5.8};
+  b = __builtin_mips_abs_ps (a);
+  c = (v2sf) {3.4, 5.8};
+  if (!__builtin_mips_upper_c_eq_ps (b, c) ||
+      !__builtin_mips_lower_c_eq_ps (b, c))
+    abort ();
+
+  /* alnv.ps with rs = 4*/
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  i = 4;
+  c = __builtin_mips_alnv_ps (a, b, i);
+  d = (v2sf) {2, 3};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* alnv.ps with rs = 0 */
+  a = (v2sf) {5, 6};
+  b = (v2sf) {7, 8};
+  i = 0;
+  c = __builtin_mips_alnv_ps (a, b, i);
+  d = (v2sf) {5, 6};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-3.c
new file mode 100644
index 000000000..7e6ffd066
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-3.c
@@ -0,0 +1,737 @@
+/* { dg-do run } */
+/* { dg-options "-mpaired-single" } */
+
+/* Test MIPS paired-single conditional move */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__((vector_size(8)));
+
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d);
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main ()
+{
+  float f1;
+  v2sf a, b, c, d, e, f;
+
+  /* Case 1 {diff, diff} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {9, 6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 2 {same, diff} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {5, 6};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 3 {diff, same} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {9, 12};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* Case 4 {same, same} */
+  /* movt.ps */
+  a = (v2sf) {5, 12};
+  b = (v2sf) {5, 12};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = __builtin_mips_movt_c_eq_ps (a, b, c, d);
+  f = (v2sf) {8, 78};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* movf.ps */
+  e = __builtin_mips_movf_c_eq_ps (a, b, c, d);
+  f = (v2sf) {33, 123};
+  if (!__builtin_mips_upper_c_eq_ps (e, f) ||
+      !__builtin_mips_lower_c_eq_ps (e, f))
+    abort ();
+
+  /* Test all 16 operators */
+  a = (v2sf) {123, 123};
+  b = (v2sf) {1000, 1000};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = test0 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test1 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test3 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test4 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test5 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test6 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test7 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test8 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test9 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test10 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test11 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test12 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test13 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test14 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test15 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test16 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test17 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test18 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test19 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test20 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test21 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test22 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test23 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test24 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test25 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test26 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test27 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test28 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test29 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test30 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test31 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  /* Test all 16 operators with (b, a) */
+  a = (v2sf) {123, 123};
+  b = (v2sf) {1000, 1000};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = test0 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test1 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test3 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test4 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test5 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test6 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test7 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test8 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test9 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test10 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test11 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test12 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test13 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test14 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test15 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test16 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test17 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test18 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test19 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test20 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test21 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test22 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test23 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test24 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test25 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test26 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test27 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test28 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test29 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test30 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test31 (b, a, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test with NaN */
+  a = (v2sf) {qnan, qnan};
+  b = (v2sf) {1000, 1000};
+  c = (v2sf) {33, 123};
+  d = (v2sf) {8, 78};
+  e = test0 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test1 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test2 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test3 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test4 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test5 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test6 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test7 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test8 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test9 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test10 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test11 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test12 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test13 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test14 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test15 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test16 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test17 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test18 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test19 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test20 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test21 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test22 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test23 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test24 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test25 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test26 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test27 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+
+  e = test28 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+  e = test29 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+
+  e = test30 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, d) || 
+      !__builtin_mips_lower_c_eq_ps (e, d))
+    abort ();
+  e = test31 (a, b, c, d);
+  if (!__builtin_mips_upper_c_eq_ps (e, c) || 
+      !__builtin_mips_lower_c_eq_ps (e, c))
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 v2sf test0 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_f_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test1 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_f_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test2 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_un_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test3 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_un_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test4 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_eq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test5 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_eq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test6 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ueq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test7 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ueq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test8 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_olt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test9 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_olt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test10 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ult_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test11 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ult_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test12 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ole_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test13 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ole_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test14 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ule_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test15 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ule_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test16 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_sf_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test17 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_sf_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test18 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ngle_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test19 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ngle_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test20 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_seq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test21 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_seq_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test22 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ngl_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test23 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ngl_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test24 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_lt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test25 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_lt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test26 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_nge_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test27 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_nge_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test28 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_le_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test29 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_le_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test30 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movt_c_ngt_ps (a, b, c, d);
+}
+
+NOMIPS16 v2sf test31 (v2sf a, v2sf b, v2sf c, v2sf d)
+{
+  return __builtin_mips_movf_c_ngt_ps (a, b, c, d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-4.c
new file mode 100644
index 000000000..06850adb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-4.c
@@ -0,0 +1,583 @@
+/* { dg-do run } */
+/* { dg-options "-mpaired-single" } */
+
+/* Test MIPS paired-single comparisons */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__((vector_size(8)));
+
+NOMIPS16 int test0 (v2sf a, v2sf b);
+NOMIPS16 int test1 (v2sf a, v2sf b);
+NOMIPS16 int test2 (v2sf a, v2sf b);
+NOMIPS16 int test3 (v2sf a, v2sf b);
+NOMIPS16 int test4 (v2sf a, v2sf b);
+NOMIPS16 int test5 (v2sf a, v2sf b);
+NOMIPS16 int test6 (v2sf a, v2sf b);
+NOMIPS16 int test7 (v2sf a, v2sf b);
+NOMIPS16 int test8 (v2sf a, v2sf b);
+NOMIPS16 int test9 (v2sf a, v2sf b);
+NOMIPS16 int test10 (v2sf a, v2sf b);
+NOMIPS16 int test11 (v2sf a, v2sf b);
+NOMIPS16 int test12 (v2sf a, v2sf b);
+NOMIPS16 int test13 (v2sf a, v2sf b);
+NOMIPS16 int test14 (v2sf a, v2sf b);
+NOMIPS16 int test15 (v2sf a, v2sf b);
+NOMIPS16 int test16 (v2sf a, v2sf b);
+NOMIPS16 int test17 (v2sf a, v2sf b);
+NOMIPS16 int test18 (v2sf a, v2sf b);
+NOMIPS16 int test19 (v2sf a, v2sf b);
+NOMIPS16 int test20 (v2sf a, v2sf b);
+NOMIPS16 int test21 (v2sf a, v2sf b);
+NOMIPS16 int test22 (v2sf a, v2sf b);
+NOMIPS16 int test23 (v2sf a, v2sf b);
+NOMIPS16 int test24 (v2sf a, v2sf b);
+NOMIPS16 int test25 (v2sf a, v2sf b);
+NOMIPS16 int test26 (v2sf a, v2sf b);
+NOMIPS16 int test27 (v2sf a, v2sf b);
+NOMIPS16 int test28 (v2sf a, v2sf b);
+NOMIPS16 int test29 (v2sf a, v2sf b);
+NOMIPS16 int test30 (v2sf a, v2sf b);
+NOMIPS16 int test31 (v2sf a, v2sf b);
+
+float qnan = 1.0f/0.0f - 1.0f/0.0f;
+
+NOMIPS16 int main()
+{
+  union { long long ll; int i[2]; } endianness_test;
+  int little_endian;
+  v2sf a, b;
+  int i, j;
+
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* Case 1 {diff, diff} */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  i = __builtin_mips_upper_c_eq_ps (a, b);
+  j = __builtin_mips_lower_c_eq_ps (a, b);
+  if (i != 0 || j != 0)
+    abort ();
+
+  /* Case 2 {same, diff} */
+  a = (v2sf) {1.0, 2.0};
+  b = (v2sf) {1.0, 4.0};
+  i = __builtin_mips_upper_c_eq_ps (a, b);
+  j = __builtin_mips_lower_c_eq_ps (a, b);
+  if (little_endian)
+    {
+      if (i != 0 || j != 1)
+        abort ();
+    }
+  else
+    {
+      if (i != 1 || j != 0)
+        abort ();
+    }
+
+  /* Case 3 {diff, same} */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 2};
+  i = __builtin_mips_upper_c_eq_ps (a, b);
+  j = __builtin_mips_lower_c_eq_ps (a, b);
+  if (little_endian)
+    {
+      if (i != 1 || j != 0)
+        abort ();
+    }
+  else
+    {
+      if (i != 0 || j != 1)
+        abort ();
+    }
+
+  /* Case 4 {same, same} */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {1, 2};
+  i = __builtin_mips_upper_c_eq_ps (a, b);
+  j = __builtin_mips_lower_c_eq_ps (a, b);
+  if (i != 1 || j != 1)
+    abort ();
+
+  /* Test upper/lower with 16 operators */
+  if (little_endian)
+   {
+     a = (v2sf) {1984.0, 10.58};
+     b = (v2sf) {1984.0, 567.345};
+   }
+  else
+   {
+     a = (v2sf) {10.58, 1984.0};
+     b = (v2sf) {567.345, 1984.0};
+   }
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 0)
+    abort ();
+  i = test3 (a, b);
+  if (i != 0)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 1)
+    abort ();
+  i = test6 (a, b);
+  if (i != 0)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 1)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 0)
+    abort ();
+  i = test12 (a, b);
+  if (i != 1)
+    abort ();
+  i = test13 (a, b);
+  if (i != 1)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 0)
+    abort ();
+  i = test19 (a, b);
+  if (i != 0)
+    abort ();
+  i = test20 (a, b);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b);
+  if (i != 1)
+    abort ();
+  i = test22 (a, b);
+  if (i != 0)
+    abort ();
+  i = test23 (a, b);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b);
+  if (i != 1)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 0)
+    abort ();
+  i = test28 (a, b);
+  if (i != 1)
+    abort ();
+  i = test29 (a, b);
+  if (i != 1)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+
+  /* Reverse arguments */
+  i = test0 (b, a);
+  if (i != 0)
+    abort ();
+  i = test1 (b, a);
+  if (i != 0)
+    abort ();
+  i = test2 (b, a);
+  if (i != 0)
+    abort ();
+  i = test3 (b, a);
+  if (i != 0)
+    abort ();
+  i = test4 (b, a);
+  if (i != 0)
+    abort ();
+  i = test5 (b, a);
+  if (i != 1)
+    abort ();
+  i = test6 (b, a);
+  if (i != 0)
+    abort ();
+  i = test7 (b, a);
+  if (i != 1)
+    abort ();
+  i = test8 (b, a);
+  if (i != 0)
+    abort ();
+  i = test9 (b, a);
+  if (i != 0)
+    abort ();
+  i = test10 (b, a);
+  if (i != 0)
+    abort ();
+  i = test11 (b, a);
+  if (i != 0)
+    abort ();
+  i = test12 (b, a);
+  if (i != 0)
+    abort ();
+  i = test13 (b, a);
+  if (i != 1)
+    abort ();
+  i = test14 (b, a);
+  if (i != 0)
+    abort ();
+  i = test15 (b, a);
+  if (i != 1)
+    abort ();
+  i = test16 (b, a);
+  if (i != 0)
+    abort ();
+  i = test17 (b, a);
+  if (i != 0)
+    abort ();
+  i = test18 (b, a);
+  if (i != 0)
+    abort ();
+  i = test19 (b, a);
+  if (i != 0)
+    abort ();
+  i = test20 (b, a);
+  if (i != 0)
+    abort ();
+  i = test21 (b, a);
+  if (i != 1)
+    abort ();
+  i = test22 (b, a);
+  if (i != 0)
+    abort ();
+  i = test23 (b, a);
+  if (i != 1)
+    abort ();
+  i = test24 (b, a);
+  if (i != 0)
+    abort ();
+  i = test25 (b, a);
+  if (i != 0)
+    abort ();
+  i = test26 (b, a);
+  if (i != 0)
+    abort ();
+  i = test27 (b, a);
+  if (i != 0)
+    abort ();
+  i = test28 (b, a);
+  if (i != 0)
+    abort ();
+  i = test29 (b, a);
+  if (i != 1)
+    abort ();
+  i = test30 (b, a);
+  if (i != 0)
+    abort ();
+  i = test31 (b, a);
+  if (i != 1)
+    abort ();
+
+#ifndef __FAST_MATH__
+  /* Test upper/lower with 16 operators */
+  if (little_endian)
+   {
+     a = (v2sf) {qnan, qnan};
+     b = (v2sf) {1984.0, 567.345};
+   }
+  else
+   {
+     a = (v2sf) {qnan, qnan};
+     b = (v2sf) {567.345, 1984.0};
+   }
+
+  i = test0 (a, b);
+  if (i != 0)
+    abort ();
+  i = test1 (a, b);
+  if (i != 0)
+    abort ();
+  i = test2 (a, b);
+  if (i != 1)
+    abort ();
+  i = test3 (a, b);
+  if (i != 1)
+    abort ();
+  i = test4 (a, b);
+  if (i != 0)
+    abort ();
+  i = test5 (a, b);
+  if (i != 0)
+    abort ();
+  i = test6 (a, b);
+  if (i != 1)
+    abort ();
+  i = test7 (a, b);
+  if (i != 1)
+    abort ();
+  i = test8 (a, b);
+  if (i != 0)
+    abort ();
+  i = test9 (a, b);
+  if (i != 0)
+    abort ();
+  i = test10 (a, b);
+  if (i != 1)
+    abort ();
+  i = test11 (a, b);
+  if (i != 1)
+    abort ();
+  i = test12 (a, b);
+  if (i != 0)
+    abort ();
+  i = test13 (a, b);
+  if (i != 0)
+    abort ();
+  i = test14 (a, b);
+  if (i != 1)
+    abort ();
+  i = test15 (a, b);
+  if (i != 1)
+    abort ();
+  i = test16 (a, b);
+  if (i != 0)
+    abort ();
+  i = test17 (a, b);
+  if (i != 0)
+    abort ();
+  i = test18 (a, b);
+  if (i != 1)
+    abort ();
+  i = test19 (a, b);
+  if (i != 1)
+    abort ();
+  i = test20 (a, b);
+  if (i != 0)
+    abort ();
+  i = test21 (a, b);
+  if (i != 0)
+    abort ();
+  i = test22 (a, b);
+  if (i != 1)
+    abort ();
+  i = test23 (a, b);
+  if (i != 1)
+    abort ();
+  i = test24 (a, b);
+  if (i != 0)
+    abort ();
+  i = test25 (a, b);
+  if (i != 0)
+    abort ();
+  i = test26 (a, b);
+  if (i != 1)
+    abort ();
+  i = test27 (a, b);
+  if (i != 1)
+    abort ();
+  i = test28 (a, b);
+  if (i != 0)
+    abort ();
+  i = test29 (a, b);
+  if (i != 0)
+    abort ();
+  i = test30 (a, b);
+  if (i != 1)
+    abort ();
+  i = test31 (a, b);
+  if (i != 1)
+    abort ();
+#endif
+
+  printf ("Test Passes\n");
+  exit (0);
+}
+
+NOMIPS16 int test0 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_f_ps (a, b);
+}
+
+NOMIPS16 int test1 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_f_ps (a, b);
+}
+
+NOMIPS16 int test2 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_un_ps (a, b);
+}
+
+NOMIPS16 int test3 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_un_ps (a, b);
+}
+
+NOMIPS16 int test4 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_eq_ps (a, b);
+}
+
+NOMIPS16 int test5 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_eq_ps (a, b);
+}
+
+NOMIPS16 int test6 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ueq_ps (a, b);
+}
+
+NOMIPS16 int test7 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ueq_ps (a, b);
+}
+
+NOMIPS16 int test8 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_olt_ps (a, b);
+}
+
+NOMIPS16 int test9 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_olt_ps (a, b);
+}
+
+NOMIPS16 int test10 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ult_ps (a, b);
+}
+
+NOMIPS16 int test11 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ult_ps (a, b);
+}
+
+NOMIPS16 int test12 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ole_ps (a, b);
+}
+
+NOMIPS16 int test13 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ole_ps (a, b);
+}
+
+NOMIPS16 int test14 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ule_ps (a, b);
+}
+
+NOMIPS16 int test15 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ule_ps (a, b);
+}
+
+NOMIPS16 int test16 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_sf_ps (a, b);
+}
+
+NOMIPS16 int test17 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_sf_ps (a, b);
+}
+
+NOMIPS16 int test18 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ngle_ps (a, b);
+}
+
+NOMIPS16 int test19 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ngle_ps (a, b);
+}
+
+NOMIPS16 int test20 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_seq_ps (a, b);
+}
+
+NOMIPS16 int test21 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_seq_ps (a, b);
+}
+
+NOMIPS16 int test22 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ngl_ps (a, b);
+}
+
+NOMIPS16 int test23 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ngl_ps (a, b);
+}
+
+NOMIPS16 int test24 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_lt_ps (a, b);
+}
+
+NOMIPS16 int test25 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_lt_ps (a, b);
+}
+
+NOMIPS16 int test26 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_nge_ps (a, b);
+}
+
+NOMIPS16 int test27 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_nge_ps (a, b);
+}
+
+NOMIPS16 int test28 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_le_ps (a, b);
+}
+
+NOMIPS16 int test29 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_le_ps (a, b);
+}
+
+NOMIPS16 int test30 (v2sf a, v2sf b)
+{
+  return __builtin_mips_upper_c_ngt_ps (a, b);
+}
+
+NOMIPS16 int test31 (v2sf a, v2sf b)
+{
+  return __builtin_mips_lower_c_ngt_ps (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-5.c
new file mode 100644
index 000000000..077076f47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mpaired-single -mgp64 -ftree-vectorize" } */
+/* { dg-skip-if "requires vectorization" { *-*-* } { "-O0" "-Os" } { "" } } */
+
+extern float a[] __attribute__ ((aligned (8)));
+extern float b[] __attribute__ ((aligned (8)));
+extern float c[] __attribute__ ((aligned (8)));
+
+NOMIPS16 void
+foo (void)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = b[i] == c[i] + 1 ? b[i] : c[i];
+}
+
+/* { dg-final { scan-assembler "\tadd\\.ps\t" } } */
+/* { dg-final { scan-assembler "\tc\\.eq\\.ps\t" } } */
+/* { dg-final { scan-assembler "\tmov\[tf\]\\.ps\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-6.c
new file mode 100644
index 000000000..5bdfe436f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-6.c
@@ -0,0 +1,136 @@
+/* mips-ps-2.c with an extra -ffinite-math-only option.  This option
+   changes the way that abs.ps is handled.  */
+/* { dg-do run } */
+/* { dg-options "-mpaired-single -ffinite-math-only" } */
+
+/* Test MIPS paired-single builtin functions */
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+NOMIPS16 int main ()
+{
+  int little_endian;
+  v2sf a, b, c, d;
+  float e,f;
+  int i;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  /* pll.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_pll_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {3, 1};
+  else // big endian
+    d = (v2sf) {2, 4};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* pul.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_pul_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {3, 2};
+  else // big endian
+    d = (v2sf) {1, 4};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* plu.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_plu_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {4, 1};
+  else // big endian
+    d = (v2sf) {2, 3};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* puu.ps */
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  c = __builtin_mips_puu_ps (a, b);
+  if (little_endian) // little endian
+    d = (v2sf) {4, 2};
+  else // big endian
+    d = (v2sf) {1, 3};
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* cvt.ps.s */
+  e = 3.4;
+  f = 4.5; 
+  a = __builtin_mips_cvt_ps_s (e, f);
+  if (little_endian) // little endian
+    b = (v2sf) {4.5, 3.4};
+  else // big endian
+    b = (v2sf) {3.4, 4.5};
+  if (!__builtin_mips_upper_c_eq_ps (a, b) ||
+      !__builtin_mips_lower_c_eq_ps (a, b))
+    abort ();
+
+  /* cvt.s.pl */
+  a = (v2sf) {35.1, 120.2};
+  e = __builtin_mips_cvt_s_pl (a);
+  if (little_endian) // little endian
+    f = 35.1; 
+  else // big endian
+    f = 120.2;
+  if (e != f)
+    abort ();
+
+  /* cvt.s.pu */
+  a = (v2sf) {30.0, 100.0};
+  e = __builtin_mips_cvt_s_pu (a);
+  if (little_endian) // little endian
+    f = 100.0;
+  else // big endian
+    f = 30.0; 
+  if (e != f)
+    abort ();
+
+  /* abs.ps */
+  a = (v2sf) {-3.4, -5.8};
+  b = __builtin_mips_abs_ps (a);
+  c = (v2sf) {3.4, 5.8};
+  if (!__builtin_mips_upper_c_eq_ps (b, c) ||
+      !__builtin_mips_lower_c_eq_ps (b, c))
+    abort ();
+
+  /* alnv.ps with rs = 4*/
+  a = (v2sf) {1, 2};
+  b = (v2sf) {3, 4};
+  i = 4;
+  c = __builtin_mips_alnv_ps (a, b, i);
+  d = (v2sf) {2, 3};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  /* alnv.ps with rs = 0 */
+  a = (v2sf) {5, 6};
+  b = (v2sf) {7, 8};
+  i = 0;
+  c = __builtin_mips_alnv_ps (a, b, i);
+  d = (v2sf) {5, 6};
+
+  if (!__builtin_mips_upper_c_eq_ps (c, d) ||
+      !__builtin_mips_lower_c_eq_ps (c, d))
+    abort ();
+
+  printf ("Test Passes\n");
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-7.c
new file mode 100644
index 000000000..3b4e53085
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-7.c
@@ -0,0 +1,20 @@
+/* mips-ps-5.c with -mgp32 instead of -mgp64.  */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mpaired-single -ftree-vectorize" } */
+/* { dg-skip-if "requires vectorization" { *-*-* } { "-O0" "-Os" } { "" } } */
+
+extern float a[] __attribute__ ((aligned (8)));
+extern float b[] __attribute__ ((aligned (8)));
+extern float c[] __attribute__ ((aligned (8)));
+
+NOMIPS16 void
+foo (void)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    a[i] = b[i] == c[i] + 1 ? b[i] : c[i];
+}
+
+/* { dg-final { scan-assembler "\tadd\\.ps\t" } } */
+/* { dg-final { scan-assembler "\tc\\.eq\\.ps\t" } } */
+/* { dg-final { scan-assembler "\tmov\[tf\]\\.ps\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
new file mode 100644
index 000000000..f52cf91e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type-2.c
@@ -0,0 +1,112 @@
+/* Test v2sf calculations.  The nmadd and nmsub patterns need
+   -ffinite-math-only.  */
+/* { dg-do compile } */
+/* { dg-options "isa_rev>=2 -mgp32 -mpaired-single -ffinite-math-only" } */
+/* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */
+/* { dg-final { scan-assembler "\tmov.ps\t" } } */
+/* { dg-final { scan-assembler "\tldc1\t" } } */
+/* { dg-final { scan-assembler "\tsdc1\t" } } */
+/* { dg-final { scan-assembler "\tadd.ps\t" } } */
+/* { dg-final { scan-assembler "\tsub.ps\t" } } */
+/* { dg-final { scan-assembler "\tneg.ps\t" } } */
+/* { dg-final { scan-assembler "\tmul.ps\t" } } */
+/* { dg-final { scan-assembler "\tmadd.ps\t" } } */
+/* { dg-final { scan-assembler "\tmsub.ps\t" } } */
+/* { dg-final { scan-assembler "\tnmadd.ps\t" } } */
+/* { dg-final { scan-assembler "\tnmsub.ps\t" } } */
+/* { dg-final { scan-assembler "\tmovn.ps\t" } } */
+/* { dg-final { scan-assembler "\tmovz.ps\t" } } */
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+void gobble (v2sf);
+
+v2sf A = {100, 200};
+
+/* Init from  floats */
+NOMIPS16 v2sf init (float a, float b)
+{
+  return (v2sf) {a, b};
+}
+
+/* Move between registers */
+NOMIPS16 v2sf move (v2sf a)
+{
+  return a;
+}
+
+/* Load from memory */
+NOMIPS16 v2sf load ()
+{
+  return A;
+}
+
+/* Store to memory */
+NOMIPS16 void store (v2sf a)
+{
+  A = a;
+}
+
+/* Add */
+NOMIPS16 v2sf add (v2sf a, v2sf b)
+{
+  return a + b;
+}
+
+/* Subtract */
+NOMIPS16 v2sf sub (v2sf a, v2sf b)
+{
+  return a - b;
+}
+
+/* Negate */
+NOMIPS16 v2sf neg (v2sf a)
+{
+  return - a;
+}
+
+/* Multiply */
+NOMIPS16 v2sf mul (v2sf a, v2sf b)
+{
+  return a * b;
+}
+
+/* Multiply and add */
+NOMIPS16 v2sf madd (v2sf a, v2sf b, v2sf c)
+{
+  return a * b + c;
+}
+
+/* Multiply and subtract */
+NOMIPS16 v2sf msub (v2sf a, v2sf b, v2sf c)
+{
+  return a * b - c;
+}
+
+/* Negate Multiply and add */
+NOMIPS16 v2sf nmadd (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b + c);
+}
+
+/* Negate Multiply and subtract */
+NOMIPS16 v2sf nmsub (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b - c);
+}
+
+/* Conditional Move */
+NOMIPS16 v2sf cond_move1 (v2sf a, v2sf b, int i)
+{
+  if (i == 0)
+    a = b;
+  gobble (a);
+}
+
+/* Conditional Move */
+NOMIPS16 v2sf cond_move2 (v2sf a, v2sf b, int i)
+{
+  if (i != 0)
+    a = b;
+  gobble (a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type.c
new file mode 100644
index 000000000..c36dc25c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-ps-type.c
@@ -0,0 +1,112 @@
+/* Test v2sf calculations.  The nmadd and nmsub patterns need
+   -ffinite-math-only.  */
+/* { dg-do compile } */ 
+/* { dg-options "-mpaired-single -mgp64 -ffinite-math-only" } */
+/* { dg-skip-if "nmadd and nmsub need combine" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tcvt.ps.s\t" } } */
+/* { dg-final { scan-assembler "\tmov.ps\t" } } */
+/* { dg-final { scan-assembler "\tldc1\t" } } */
+/* { dg-final { scan-assembler "\tsdc1\t" } } */
+/* { dg-final { scan-assembler "\tadd.ps\t" } } */
+/* { dg-final { scan-assembler "\tsub.ps\t" } } */
+/* { dg-final { scan-assembler "\tneg.ps\t" } } */
+/* { dg-final { scan-assembler "\tmul.ps\t" } } */
+/* { dg-final { scan-assembler "\tmadd.ps\t" } } */
+/* { dg-final { scan-assembler "\tmsub.ps\t" } } */
+/* { dg-final { scan-assembler "\tnmadd.ps\t" } } */
+/* { dg-final { scan-assembler "\tnmsub.ps\t" } } */
+/* { dg-final { scan-assembler "\tmov(n|z).ps\t" } } */
+
+typedef float v2sf __attribute__ ((vector_size(8)));
+
+v2sf A = {100, 200};
+
+/* Init from  floats */
+NOMIPS16 v2sf init (float a, float b)
+{
+  return (v2sf) {a, b};
+}
+
+/* Move between registers */
+NOMIPS16 v2sf move (v2sf a)
+{
+  return a;
+}
+
+/* Load from memory */
+NOMIPS16 v2sf load ()
+{
+  return A;
+}
+
+/* Store to memory */ 
+NOMIPS16 void store (v2sf a)
+{
+  A = a;
+}
+
+/* Add */ 
+NOMIPS16 v2sf add (v2sf a, v2sf b)
+{
+  return a + b;
+}
+
+/* Subtract */ 
+NOMIPS16 v2sf sub (v2sf a, v2sf b)
+{
+  return a - b;
+}
+
+/* Negate */
+NOMIPS16 v2sf neg (v2sf a)
+{
+  return - a;
+}
+
+/* Multiply */ 
+NOMIPS16 v2sf mul (v2sf a, v2sf b)
+{
+  return a * b;
+}
+
+/* Multiply and add */ 
+NOMIPS16 v2sf madd (v2sf a, v2sf b, v2sf c)
+{
+  return a * b + c;
+}
+
+/* Multiply and subtract */ 
+NOMIPS16 v2sf msub (v2sf a, v2sf b, v2sf c)
+{
+  return a * b - c;
+}
+
+/* Negate Multiply and add */ 
+NOMIPS16 v2sf nmadd (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b + c);
+}
+
+/* Negate Multiply and subtract */ 
+NOMIPS16 v2sf nmsub (v2sf a, v2sf b, v2sf c)
+{
+  return - (a * b - c);
+}
+
+/* Conditional Move */ 
+NOMIPS16 v2sf cond_move1 (v2sf a, v2sf b, long i)
+{
+  if (i > 0)
+    return a;
+  else
+    return b;
+}
+
+/* Conditional Move */ 
+NOMIPS16 v2sf cond_move2 (v2sf a, v2sf b, int i)
+{
+  if (i > 0)
+    return a;
+  else
+    return b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-sched-madd.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-sched-madd.c
new file mode 100644
index 000000000..1db1550fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips-sched-madd.c
@@ -0,0 +1,20 @@
+/* Test for case where another independent multiply insn may interfere
+   with a macc chain.  */
+/* { dg-do compile } */
+/* { dg-options "-march=24kf" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 int foo (int a, int b, int c, int d, int e, int f, int g)
+{
+  int temp;
+  int acc;
+
+  acc = a * b;
+  temp = a * c;
+  acc = d * e + acc;
+  acc = f * g + acc;
+  return acc > temp ? acc : temp;
+}
+
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmadd\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp
new file mode 100644
index 000000000..8c72cff72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips.exp
@@ -0,0 +1,1308 @@
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# A MIPS version of the GCC dg.exp driver.
+#
+# There are many MIPS features that we want to test, and many of those
+# features are specific to certain architectures, certain ABIs and so on.
+# There are therefore many cases in which we want to test something that
+# is incompatible with the user's chosen test options.
+#
+# In most dg testsuites, the options added by dg-options have a lower
+# priority than the options chosen by the user.  For example, if a test
+# specifies:
+#
+#    { dg-options "-mips1" }
+#
+# and the user passes the following option to runtest:
+#
+#    --target_board unix/-mips3
+#
+# the test would be compiled as MIPS III rather than MIPS I.  If the
+# test really wouldn't work with -mips3, normal practice would be to
+# have something like:
+#
+#    { dg-do compile { target can_force_mips1 } }
+#
+# so that the test is skipped when an option like -mips3 is passed.
+#
+# Sticking to the same approach here would cause us to skip many tests,
+# even though the toolchain can generate the required code.  For example,
+# there are 6 MIPS ABIs, plus variants.  Some configurations support
+# more than one ABI, so it is natural to use something like:
+#
+#    --target_board unix{-mabi=n32,-mabi=32,-mabi=64}
+#
+# when testing them.  But these -mabi=* options would normally prevent any
+# EABI and o64 tests from running.
+#
+# This testsuite therefore defines a local version of dg-options that
+# overrides any user options that are incompatible with the test options.
+# It tries to keep the other user options intact.
+#
+#
+# Most of the tests in this testsuite are scan-assembler tests, but
+# sometimes we need a link test instead.  In these cases, we must not
+# try to link code with options that are incompatible with the current
+# multilib, because xgcc is passed -L and -B options that are specific
+# to that multilib.
+#
+# Normal GCC practice would be to skip incompatible link tests as
+# unsupported, but in this particular case, it seems better to downgrade
+# them to an assemble test instead.  At least that way we get some
+# test-for-ICE and code-sanity coverage.
+#
+# The same problem applies to run tests.  If a test requires runtime
+# support for a particular feature, and if the current target does not
+# provide that support, normal practice would be to skip the test.
+# But in this case it seems better to downgrade it to a link test instead.
+# (We might then have to downgrade it to an assembler test according to
+# the constraints just mentioned.)
+#
+# The local dg-options therefore checks whether the new options are
+# link-compatiable with the user's options.  If not, it automatically
+# downgrades link tests to assemble tests.  It does the same for run
+# tests, but in addition, it downgrades run tests to link tests if the
+# target does not provide runtime support for a required feature or ASE.
+#
+#
+# Another problem is that many of the options we want to test require
+# certain other features.  For example, -mips3d requires both 64-bit
+# FPRs and a MIPS32 or MIPS64 target; -mfix-r10000 requires branch-
+# likely instructions; and so on.  We could handle this by specifying
+# a set of options that are guaranteed to give us what we want, such as:
+#
+#   dg-options "-mips3d -mpaired-single -mhard-float -mgp64 -mfp64 -mabi=n32 -march=mips64 -mips64"
+#
+# With the new dg-options semantics, this would override any troublesome
+# user options like -mips3, -march=vr4100, -mfp32, -mgp32, -msoft-float,
+# -mno-paired-single and so on.  But there are three major problems with
+# this:
+#
+#   - It is easy to forget options.
+#
+#   - If a new option is added, all tests that are incompatible with that
+#     option must be updated.
+#
+#   - We want to be able to test MIPS-3D with things like -march=mips32,
+#     -march=mips64r2, -march=sb1, and so on.
+#
+# The local version of dg-options therefore works out the requirements
+# of each test option.  As with the test options themselves, the local
+# dg-options overrides any user options that incompatible with these
+# requirements, but it keeps the other user options the same.
+#
+# For example, if the user passes -mips3, a MIPS-3D test will choose
+# a different architecture like -mips64 instead.  But if the user
+# passes -march=sb1, MIPS-3D tests will be run with that option.
+#
+#
+# Sometimes it is useful to say "I want an environment that is compatible
+# with option X, but I don't want to pass option X itself".  The main example
+# of this is -mips16: we want to be able to test __attribute__((mips16))
+# without requiring the test itself to be compiled as -mips16.  The local
+# version of dg-options lets you do this by putting X in parentheses.
+# For example:
+#
+#   { dg-options "(-mips16)" }
+#
+# selects a MIPS16-compatible target without passing -mips16 itself.
+#
+# It is also useful to say "any architecture within this ISA range is fine".
+# This can be done using special pseudo-options of the form:
+#
+#   PROP=VALUE PROP<=VALUE PROP>=VALUE
+#
+# where PROP can be:
+#
+#   isa:
+#	the value of the __mips macro.
+#
+#   isa_rev:
+#	the value of the __mips_isa_rev macro, or 0 if it isn't defined.
+#
+# For example, "isa_rev>=1" selects a MIPS32 or MIPS64 processor,
+# "isa=4" selects a MIPS IV processor, and so on.
+#
+# There are also the following special pseudo-options:
+#
+#   isa=loongson
+#	select a Loongson processor
+#
+#   addressing=absolute
+#	force absolute addresses to be used
+#
+#   forbid_cpu=REGEXP
+#	forbid processors that match the given regexp; choose a
+#	generic ISA instead.
+#
+#
+# In summary:
+#
+#   (1) Try to avoid { target ... } requirements wherever possible.
+#       Specify the requirements as dg-options instead.
+#
+#   (2) Don't worry about the consequences of (1) for link and run tests.
+#       If the test uses { dg-do link } or { dg-do run }, and its
+#       dg-options are incompatible with the current target, the
+#       testsuite will downgrade them where necessary.
+#
+#   (3) Try to use the bare minimum of options and leave dg-options
+#       to work out the dependencies.  For example, if you want
+#       a MIPS-3D test, you should generally just specify -mips3d.
+#       Don't specify an architecture option like -mips64 unless
+#       the test really doesn't work with -mips32r2, -mips64r2,
+#       -march=sb1, etc.
+#
+#   (4) If you want something compatible with a particular option,
+#       but don't want to pass the option itself, wrap that option
+#       in parentheses.  In particular, pass '(-mips16)' if you
+#       want to use "mips16" attributes.
+#
+#   (5) When testing a feature of a generic ISA (as opposed to a
+#	processor-specific extension), try to use the "isa" and
+#	"isa_rev" pseudo-options instead of specific architecture
+#	options.  For example, if the feature is present on revision 2
+#	processors and above, try to use "isa_rev>=2" instead of
+#	"-mips32r2" or "-mips64r2".
+#
+#   (6) If you need to disable processor-specific extensions use
+#	forbid_cpu=REGEXP instead of forcing a generic ISA.
+#
+#
+# Terminology
+#
+#   Option group or just group:
+#      See comment before mips_option_groups.
+#
+#   Test options:
+#      The options specified in dg-options.
+#
+#   Explicit options:
+#      The options that were either passed to runtest as "multilib" options
+#      (e.g. -mips4 in --target_board=mips-sim-idt/-mips4) or specified as
+#      test options.  Note that options in parenthesis (i.e. (-mips16)) are
+#      not explicit and can be omitted depending on the base options.
+#
+#   Base options:
+#      Options that are on by default without being specified in dg-options,
+#      e.g. -march=mips64r2 for mipsisa64r2-elf or because they've been
+#      passed to runtest as "multilib" options.
+#
+#   Option array:
+#      Many functions in this file work with option arrays.  These are
+#      two-dimensional Tcl arrays where the first dimension can have three
+#      values: option, explicit_p or test_option_p.  The second dimension is
+#      the name of the option group.  "option" contains the name of the
+#      option that is in effect from this group.  If no option is active it
+#      contains the empty string.  The flags "explicit_p" and "test_option_p"
+#      are set for explicit and test options.
+
+# Exit immediately if this isn't a MIPS target.
+if ![istarget mips*-*-*] {
+    return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# A list of GROUP REGEXP pairs.  Each GROUP represents a logical group of
+# options from which only one option should be chosen.  REGEXP matches all
+# the options in that group; it is implicitly wrapped in "^(...)$".
+#
+# Note that -O* is deliberately omitted from this list.  Tests in this
+# directory are run at various optimisation levels and should use
+# dg-skip-if to skip any incompatible levels.
+set mips_option_groups {
+    abi "-mabi=.*"
+    addressing "addressing=.*"
+    arch "-mips([1-5]|32.*|64.*)|-march=.*|isa(|_rev)(=|<=|>=).*"
+    debug "-g.*"
+    dump_pattern "-dp"
+    endianness "-E(L|B)|-me(l|b)"
+    float "-m(hard|soft)-float"
+    forbid_cpu "forbid_cpu=.*"
+    fp "-mfp(32|64)"
+    gp "-mgp(32|64)"
+    long "-mlong(32|64)"
+    micromips "-mmicromips|-mno-micromips"
+    mips16 "-mips16|-mno-mips16|-mflip-mips16"
+    mips3d "-mips3d|-mno-mips3d"
+    pic "-f(no-|)(pic|PIC)"
+    profiling "-pg"
+    small-data "-G[0-9]+"
+    warnings "-w"
+    dump "-fdump-.*"
+}
+
+# Add -mfoo/-mno-foo options to mips_option_groups.
+foreach option {
+    abicalls
+    branch-likely
+    dsp
+    dspr2
+    explicit-relocs
+    extern-sdata
+    fix-r4000
+    fix-r10000
+    fix-vr4130
+    gpopt
+    local-sdata
+    long-calls
+    paired-single
+    plt
+    shared
+    smartmips
+    sym32
+    synci
+    relax-pic-calls
+    mcount-ra-address
+} {
+    lappend mips_option_groups $option "-m(no-|)$option"
+}
+
+# Add -mfoo= options to mips_option_groups.
+foreach option {
+    abs
+    branch-cost
+    code-readable
+    nan
+    r10k-cache-barrier
+    tune
+} {
+    lappend mips_option_groups $option "-m$option=.*"
+}
+
+# Add -ffoo/-fno-foo options to mips_option_groups.
+foreach option {
+    common
+    delayed-branch
+    expensive-optimizations
+    fast-math
+    fat-lto-objects
+    finite-math-only
+    fixed-hi
+    fixed-lo
+    lax-vector-conversions
+    omit-frame-pointer
+    optimize-sibling-calls
+    peephole2
+    schedule-insns2
+    split-wide-types
+    tree-vectorize
+    unroll-all-loops
+    unroll-loops
+} {
+    lappend mips_option_groups $option "-f(no-|)$option"
+}
+
+# A list of option groups that have an impact on the ABI.
+set mips_abi_groups {
+    abi
+    abicalls
+    arch
+    endianness
+    float
+    fp
+    gp
+    gpopt
+    long
+    pic
+    small-data
+}
+
+# mips_option_tests(OPTION) is some assembly code that will run to completion
+# on a target that supports OPTION.
+set mips_option_tests(-mips16) {
+    move $2,$31
+    bal 1f
+    .set mips16
+    jr $31
+    .set nomips16
+    .align 2
+1:
+    ori $3,$31,1
+    jalr $3
+    move $31,$2
+}
+set mips_option_tests(-mpaired-single) {
+    .set mips64
+    lui $2,0x3f80
+    mtc1 $2,$f0
+    cvt.ps.s $f2,$f0,$f0
+}
+set mips_option_tests(-mips3d) {
+    .set mips64
+    .set mips3d
+    lui $2,0x3f80
+    mtc1 $2,$f0
+    cvt.ps.s $f2,$f0,$f0
+    mulr.ps $f2,$f2,$f2
+    rsqrt1.s $f2,$f0
+    mul.s $f4,$f2,$f0
+    rsqrt2.s $f4,$f4,$f2
+    madd.s $f4,$f2,$f2,$f4
+}
+set mips_option_tests(-mdsp) {
+    .set mips64r2
+    .set dsp
+    addsc $2,$2,$2
+}
+set mips_option_tests(-mdspr2) {
+    .set mips64r2
+    .set dspr2
+    prepend $2,$3,11
+}
+
+# Canonicalize command-line option OPTION.
+proc mips_canonicalize_option { option } {
+    regsub {^-mips([1-5]|32*|64*)$} $option {-march=mips\1} option
+
+    regsub {^-mel$} $option {-EL} option
+    regsub {^-meb$} $option {-EB} option
+
+    regsub {^-O$} $option {-O1} option
+
+    # MIPS doesn't use -fpic and -fPIC to distinguish between code models.
+    regsub {^-f(no-|)PIC} $option {-f\1pic} option
+
+    return $option
+}
+
+# Return true if OPTION1 and OPTION2 represent the same command-line option.
+proc mips_same_option_p { option1 option2 } {
+    return [string equal \
+		[mips_canonicalize_option $option1] \
+		[mips_canonicalize_option $option2]]
+}
+
+# Preprocess CODE using target_compile options OPTIONS.  Return the
+# compiler output.
+proc mips_preprocess { options code } {
+    global tool
+
+    set src dummy[pid].c
+    set f [open $src "w"]
+    puts $f $code
+    close $f
+    set output [${tool}_target_compile $src "" preprocess $options]
+    file delete $src
+
+    return $output
+}
+
+# Set the target board's command-line options to NEW_OPTIONS, storing the
+# old values in UPVAR.
+proc mips_push_test_options { upvar new_options } {
+    upvar $upvar var
+    global board_info
+
+    array unset var
+    set var(name) board_info([target_info name],multilib_flags)
+    if { [info exists $var(name)] } {
+	set var(old_options) [set $var(name)]
+	set $var(name) [join $new_options " "]
+    }
+}
+
+# Undo the effects of [mips_push_test_options UPVAR ...]
+proc mips_pop_test_options { upvar } {
+    upvar $upvar var
+    global board_info
+
+    if { [info exists var(old_options)] } {
+	set $var(name) $var(old_options)
+    }
+}
+
+# Return property PROP for architecture option ARCH (which belongs to
+# the "arch" group in mips_option_groups).  See the comment at the
+# top of the file for the valid property names.
+#
+# Cache the results in mips_arch_info (which can be reused between test
+# variants).
+proc mips_arch_info { arch prop } {
+    global mips_arch_info
+    global board_info
+
+    set arch [mips_canonicalize_option $arch]
+    if { ![info exists mips_arch_info($arch,$prop)] } {
+	mips_push_test_options saved_options {}
+	set output [mips_preprocess [list "additional_flags=$arch -mabi=32"] {
+	    int isa = __mips;
+	    #ifdef __mips_isa_rev
+	    int isa_rev = __mips_isa_rev;
+	    #else
+	    int isa_rev = 0;
+	    #endif
+	}]
+	foreach lhs { isa isa_rev } {
+	    regsub ".*$lhs = (\[^;\]*).*" $output {\1} rhs
+	    verbose -log "Architecture $arch has $lhs $rhs"
+	    set mips_arch_info($arch,$lhs) $rhs
+	}
+	mips_pop_test_options saved_options
+    }
+    return $mips_arch_info($arch,$prop)
+}
+
+# Return the option group associated with OPTION, or "" if none.
+proc mips_option_maybe_group { option } {
+    global mips_option_groups
+
+    foreach { group regexp } $mips_option_groups {
+	if { [regexp -- "^($regexp)\$" $option] } {
+	    return $group
+	}
+    }
+    return ""
+}
+
+# Return the option group associated with OPTION.  Raise an error if
+# there is none.
+proc mips_option_group { option } {
+    set group [mips_option_maybe_group $option]
+    if { [string equal $group ""] } {
+	error "Unrecognised option: $option"
+    }
+    return $group
+}
+
+# Return the option for option group GROUP, or "" if no option in that
+# group has been chosen.  UPSTATUS describes the option status.
+proc mips_option { upstatus group } {
+    upvar $upstatus status
+
+    return $status(option,$group)
+}
+
+# If the base options for this test run include an option in group GROUP,
+# return that option, otherwise return "".
+proc mips_original_option { group } {
+    global mips_base_options
+
+    return [mips_option mips_base_options $group]
+}
+
+# Return true if the test described by UPSTATUS requires a specific
+# option in group GROUP.  UPSTATUS describes the option status.
+proc mips_test_option_p { upstatus group } {
+    upvar $upstatus status
+
+    return $status(test_option_p,$group)
+}
+
+# If the test described by UPSTATUS requires a particular option in group
+# GROUP, return that option, otherwise return "".
+proc mips_test_option { upstatus group } {
+    upvar $upstatus status
+
+    if { [mips_test_option_p status $group] } {
+	return [mips_option status $group]
+    } else {
+	return ""
+    }
+}
+
+# Return true if the options described by UPSTATUS include OPTION.
+proc mips_have_option_p { upstatus option } {
+    upvar $upstatus status
+
+    return [mips_same_option_p \
+		[mips_option status [mips_option_group $option]] \
+		$option]
+}
+
+# Return true if the options described by UPSTATUS require MIPS16 support.
+proc mips_using_mips16_p { upstatus } {
+    upvar $upstatus status
+
+    return [expr { [mips_have_option_p status "-mips16"]
+		   || [mips_have_option_p status "-mflip-mips16"] }]
+}
+
+# Return true if the test described by UPSTATUS requires option OPTION.
+proc mips_have_test_option_p { upstatus option } {
+    upvar $upstatus status
+
+    set group [mips_option_group $option]
+    return [mips_same_option_p [mips_test_option status $group] $option]
+}
+
+# If the test described by UPSTATUS does not specify an option in
+# OPTION's group, act as though it had specified OPTION.
+#
+# The first optional argument indicates whether the option should be
+# treated as though it were wrapped in parentheses; see the comment at
+# the top of the file for details about this convention.  The default is 0.
+proc mips_make_test_option { upstatus option args } {
+    upvar $upstatus status
+
+    set group [mips_option_group $option]
+    if { ![mips_test_option_p status $group] } {
+	set status(option,$group) $option
+	set status(test_option_p,$group) 1
+	if { [llength $args] == 0 || ![lindex $args 0] } {
+	    set status(explicit_p,$group) 1
+	}
+    }
+}
+
+# If the test described by UPSTATUS requires option FROM, assume that
+# it implicitly requires option TO.
+proc mips_option_dependency { upstatus from to } {
+    upvar $upstatus status
+
+    if { [mips_have_test_option_p status $from] } {
+	mips_make_test_option status $to
+    }
+}
+
+# Return true if the given arch-group option specifies a 32-bit ISA.
+proc mips_32bit_arch_p { option } {
+    set isa [mips_arch_info $option isa]
+    return [expr { $isa < 3 || $isa == 32 }]
+}
+
+# Return true if the given arch-group option specifies a 64-bit ISA.
+proc mips_64bit_arch_p { option } {
+    return [expr { ![mips_32bit_arch_p $option] }]
+}
+
+# Return true if the given abi-group option implicitly requires -mgp32.
+proc mips_32bit_abi_p { option } {
+    switch -glob -- $option {
+	-mabi=32 {
+	    return 1
+	}
+    }
+    return 0
+}
+
+# Return true if the given abi-group option implicitly requires -mgp64.
+proc mips_64bit_abi_p { option } {
+    switch -glob -- $option {
+	-mabi=o64 -
+	-mabi=n32 -
+	-mabi=64 {
+	    return 1
+	}
+    }
+    return 0
+}
+
+# Return true if the given abi-group option implicitly requires -mlong32.
+# o64 requires this for -mabicalls, but not otherwise; pick the conservative
+# case for simplicity.
+proc mips_long32_abi_p { option } {
+    switch -glob -- $option {
+	-mabi=o64 -
+	-mabi=n32 -
+	-mabi=32 {
+	    return 1
+	}
+    }
+    return 0
+}
+
+# Return true if the given abi-group option implicitly requires -mlong64.
+proc mips_long64_abi_p { option } {
+    switch -glob -- $option {
+	-mabi=64 {
+	    return 1
+	}
+    }
+    return 0
+}
+
+# Check whether the current target supports all the options that the
+# current test requires.  Return "" if so, otherwise return one of
+# the incompatible options.  UPSTATUS describes the option status.
+proc mips_first_unsupported_option { upstatus } {
+    global mips_option_tests
+    upvar $upstatus status
+
+    foreach { option code } [array get mips_option_tests] {
+	if { [mips_have_test_option_p status $option] } {
+	    regsub -all "\n" $code "\\n\\\n" asm
+	    # Use check_runtime from target-supports.exp, which caches
+	    # the result for us.
+	    if { ![check_runtime mips_option_$option [subst {
+		__attribute__((nomips16)) int
+		main (void)
+		{
+		    asm (".set push\
+		    $asm\
+		    .set pop");
+		    return 0;
+		}
+	    }]] } {
+		return $option
+	    }
+	}
+    }
+    return ""
+}
+
+# Initialize this testsuite for a new test variant.
+proc mips-dg-init {} {
+    # Invariant information.
+    global mips_option_groups
+
+    # Internally-generated information about this run.
+    global mips_base_options
+    global mips_extra_options
+
+    # Override dg-options with our mips-dg-options routine.
+    rename dg-options mips-old-dg-options
+    rename mips-dg-options dg-options
+
+    # Start with a fresh option status.
+    array unset mips_base_options
+    foreach { group regexp } $mips_option_groups {
+	set mips_base_options(option,$group) ""
+	set mips_base_options(explicit_p,$group) 0
+	set mips_base_options(test_option_p,$group) 0
+    }
+
+    # Use preprocessor macros to work out as many implicit options as we can.
+    set output [mips_preprocess "" {
+	const char *options[] = {
+	    #if !defined _MIPS_SIM
+	    "-mabi=eabi",
+	    #elif _MIPS_SIM==_ABIO32
+	    "-mabi=32",
+	    #elif _MIPS_SIM==_ABIO64
+	    "-mabi=o64",
+	    #elif _MIPS_SIM==_ABIN32
+	    "-mabi=n32",
+	    #else
+	    "-mabi=64",
+	    #endif
+
+	    "-march=" _MIPS_ARCH,
+
+	    #ifdef _MIPSEB
+	    "-EB",
+	    #else
+	    "-EL",
+	    #endif
+
+	    #ifdef __mips_hard_float
+	    "-mhard-float",
+	    #else
+	    "-msoft-float",
+	    #endif
+
+	    #ifdef __mips_abs2008
+	    "-mabs=2008",
+	    #else
+	    "-mabs=legacy",
+	    #endif
+
+	    #ifdef __mips_nan2008
+	    "-mnan=2008",
+	    #else
+	    "-mnan=legacy",
+	    #endif
+
+	    #if __mips_fpr == 64
+	    "-mfp64",
+	    #else
+	    "-mfp32",
+	    #endif
+
+	    #ifdef __mips64
+	    "-mgp64",
+	    #else
+	    "-mgp32",
+	    #endif
+
+	    #if _MIPS_SZLONG == 64
+	    "-mlong64",
+	    #else
+	    "-mlong32",
+	    #endif
+
+	    #ifdef __mips16
+	    "-mips16",
+	    #else
+	    "-mno-mips16",
+	    #endif
+
+	    #ifdef __mips3d
+	    "-mips3d",
+	    #else
+	    "-mno-mips3d",
+	    #endif
+
+	    #ifdef __mips_paired_single_float
+	    "-mpaired-single",
+	    #else
+	    "-mno-paired-single",
+	    #endif
+
+	    #if __mips_abicalls
+	    "-mabicalls",
+	    #else
+	    "-mno-abicalls",
+	    #endif
+
+	    #if __mips_dsp_rev >= 2
+	    "-mdspr2",
+	    #else
+	    "-mno-dspr2",
+	    #endif
+
+	    #if __mips_dsp_rev >= 1
+	    "-mdsp",
+	    #else
+	    "-mno-dsp",
+	    #endif
+
+	    #ifndef __PIC__
+	    "addressing=absolute",
+	    #endif
+
+	    #ifdef __mips_smartmips
+	    "-msmartmips",
+	    #else
+	    "-mno-smartmips",
+	    #endif
+
+	    #ifdef __mips_synci
+	    "-msynci",
+	    #else
+	    "-mno-synci",
+	    #endif
+
+	    0
+	};
+    }]
+    foreach line [split $output "\r\n"] {
+	# Poor man's string concatenation.
+	regsub -all {" "} $line "" line
+	if { [regexp {"(.*)",} $line dummy option] } {
+	    set group [mips_option_group $option]
+	    set mips_base_options(option,$group) $option
+	}
+    }
+
+    # Process the target's multilib options, saving any unrecognized
+    # ones in mips_extra_options.
+    set mips_extra_options {}
+    foreach option [split [board_info target multilib_flags]] {
+	set group [mips_option_maybe_group $option]
+	if { ![string equal $group ""] } {
+	    set mips_base_options(option,$group) $option
+	    set mips_base_options(explicit_p,$group) 1
+	} else {
+	    lappend mips_extra_options $option
+	}
+    }
+}
+
+# Finish a test run started by mips-dg-init.
+proc mips-dg-finish {} {
+    rename dg-options mips-dg-options
+    rename mips-old-dg-options dg-options
+}
+
+# Override dg-options so that we can do some MIPS-specific processing.
+# All options used in this testsuite must appear in mips_option_groups.
+#
+# Test options override multilib options.  Certain test options can
+# also imply other test options, which also override multilib options.
+# These dependencies are ordered as follows:
+#
+#          START                        END
+#            |                           |
+#         -mips16/-mflip-mips16       -mno-mips16
+#            |                           |
+#         -micromips                  -mno-micromips
+#            |                           |
+#         -mips3d                     -mno-mips3d
+#            |                           |
+#         -mpaired-single             -mno-paired-single
+#            |                           |
+#         -mfp64                      -mfp32
+#            |                           |
+#         -mabs=2008/-mabs=legacy     <no option>
+#            |                           |
+#         -mhard-float                -msoft-float
+#            |                           |
+#         -mno-sym32                  -msym32
+#            |                           |
+#         -mrelax-pic-calls           -mno-relax-pic-calls
+#            |                           |
+#         -fpic                       -fno-pic
+#            |                           |
+#         -mshared                    -mno-shared
+#            |                           |
+#         -mno-plt                    -mplt
+#            |                           |
+#         addressing=unknown          addressing=absolute
+#            |                           |
+#         -mabicalls                  -mno-abicalls
+#            |                           |
+#         -G0                         <other value>
+#            |                           |
+#         <other value>               -mr10k-cache-barrier=none
+#            |                           |
+#         -mfix-r10000                -mno-fix-r10000
+#            |                           |
+#         -mbranch-likely             -mno-branch-likely
+#            |                           |
+#         -msmartmips                 -mno-smartmips
+#            |                           |
+#         -mno-gpopt                  -mgpopt
+#            |                           |
+#         -mexplicit-relocs           -mno-explicit-relocs
+#            |                           |
+#         -mdspr2                     -mno-dspr2
+#            |                           |
+#         -mdsp                       -mno-dsp
+#            |                           |
+#         -msynci                     -mno-synci
+#            |                           |
+#            +-- gp, abi & arch ---------+
+#
+# For these purposes, the "gp", "abi" & "arch" option groups are treated
+# as a single node.
+proc mips-dg-options { args } {
+    # dg.exp variables.
+    upvar dg-extra-tool-flags extra_tool_flags
+    upvar dg-do-what do_what
+
+    # Invariant information.
+    global mips_option_groups
+    global mips_abi_groups
+
+    # Information about this run.
+    global mips_base_options
+
+    if { [llength $args] >= 3 } {
+        switch { [dg-process-target [lindex $args 2]] } {
+            "S" { }
+            "N" { return }
+            "F" { error "[lindex $args 0]: `xfail' not allowed here" }
+            "P" { error "[lindex $args 0]: `xfail' not allowed here" }
+        }
+    }
+
+    # Start out with the default option state.
+    array set options [array get mips_base_options]
+
+    # Record the options that this test explicitly needs.
+    foreach option [lindex $args 1] {
+	set all_but_p [regexp {^\((.*)\)$} $option dummy option]
+	set group [mips_option_group $option]
+	if { [mips_test_option_p options $group] } {
+	    set old [mips_option options $group]
+	    error "Inconsistent $group option: $old vs. $option"
+	} else {
+	    mips_make_test_option options $option $all_but_p
+	}
+    }
+
+    # Handle dependencies between the test options and the optimization ones.
+    mips_option_dependency options "-fno-unroll-loops" "-fno-unroll-all-loops"
+    mips_option_dependency options "-pg" "-fno-omit-frame-pointer"
+
+    # Handle dependencies between options on the left of the
+    # dependency diagram.
+    mips_option_dependency options "-mips16" "-mno-micromips"
+    mips_option_dependency options "-mmicromips" "-mno-mips16"
+    mips_option_dependency options "-mips3d" "-mpaired-single"
+    mips_option_dependency options "-mpaired-single" "-mfp64"
+    mips_option_dependency options "-mfp64" "-mhard-float"
+    mips_option_dependency options "-mabs=2008" "-mhard-float"
+    mips_option_dependency options "-mabs=legacy" "-mhard-float"
+    mips_option_dependency options "-mrelax-pic-calls" "-mno-plt"
+    mips_option_dependency options "-mrelax-pic-calls" "-mabicalls"
+    mips_option_dependency options "-mrelax-pic-calls" "-mexplicit-relocs"
+    mips_option_dependency options "-fpic" "-mshared"
+    mips_option_dependency options "-mshared" "-mno-plt"
+    mips_option_dependency options "-mshared" "-mabicalls"
+    mips_option_dependency options "-mno-plt" "addressing=unknown"
+    mips_option_dependency options "-mabicalls" "-G0"
+    mips_option_dependency options "-mno-gpopt" "-mexplicit-relocs"
+
+    # Work out information about the current ABI.
+    set abi_test_option_p [mips_test_option_p options abi]
+    set abi [mips_option options abi]
+    set eabi_p [mips_same_option_p $abi "-mabi=eabi"]
+
+    # If the test forces a particular ABI, set the register size
+    # accordingly.
+    if { $abi_test_option_p } {
+	if { [mips_32bit_abi_p $abi] } {
+	    mips_make_test_option options "-mgp32"
+	} elseif { [mips_64bit_abi_p $abi] } {
+	    mips_make_test_option options "-mgp64"
+	}
+    }
+
+    # See whether forbid_cpu forces us to choose a new architecture.
+    set arch [mips_option mips_base_options arch]
+    set force_generic_isa_p [expr {
+	[regexp "forbid_cpu=(.*)" [mips_option options forbid_cpu] dummy spec]
+	&& [regexp -- "^-march=$spec\$" $arch]
+    }]
+
+    # Interpret the special "isa" and "isa_rev" options.  If we have
+    # a choice of a 32-bit or a 64-bit architecture, prefer to keep
+    # the -mgp setting the same.
+    set spec [mips_option options arch]
+    if { [regexp {^[^-]} $spec] } {
+	if { [string equal $spec "isa=loongson"] } {
+	    if { ![regexp {^-march=loongson} $arch] } {
+		set arch "-march=loongson2f"
+	    }
+	} else {
+	    if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]*)$} \
+		       $spec dummy prop relation value nocpus] } {
+		error "Unrecognized isa specification: $spec"
+	    }
+	    set current [mips_arch_info $arch $prop]
+	    if { $force_generic_isa_p
+		 || ($current < $value && ![string equal $relation "<="])
+		 || ($current > $value && ![string equal $relation ">="])
+		 || ([mips_have_test_option_p options "-mgp64"]
+		     && [mips_32bit_arch_p $arch]) } {
+		# The current setting is out of range; it cannot
+		# possibly be used.  Find a replacement that can.
+		if { [string equal $prop "isa"] } {
+		    set arch "-mips$value"
+		} elseif { $value == 0 } {
+		    set arch "-mips4"
+		} else {
+		    if { [mips_have_option_p options "-mgp32"] } {
+			set arch "-mips32"
+		    } else {
+			set arch "-mips64"
+		    }
+		    if { $value > 1 } {
+			append arch "r$value"
+		    }
+		}
+	    }
+	}
+	set options(option,arch) $arch
+    }
+
+    # Work out information about the current architecture.
+    set arch_test_option_p [mips_test_option_p options arch]
+    set arch [mips_option options arch]
+    set isa [mips_arch_info $arch isa]
+    set isa_rev [mips_arch_info $arch isa_rev]
+
+    # If the test forces a 32-bit architecture, force -mgp32.
+    # Force the current -mgp setting otherwise; if we don't,
+    # some configurations would make a 64-bit architecture
+    # imply -mgp64.
+    if { $arch_test_option_p } {
+	if { [mips_32bit_arch_p $arch] } {
+	    mips_make_test_option options "-mgp32"
+	} else {
+	    mips_make_test_option options [mips_option options gp]
+	}
+    }
+
+    # We've now fixed the GP register size.  Make it easily available.
+    set gp_size [expr { [mips_have_option_p options "-mgp32"] ? 32 : 64 }]
+
+    # Handle dependencies between the pre-arch options and the arch option.
+    # This should mirror the arch and post-arch code below.
+    if { !$arch_test_option_p } {
+	# We need a revision 2 or better ISA for:
+	#
+	#   - the combination of -mgp32 -mfp64
+	#   - the DSP ASE
+	if { $isa_rev < 2
+	     && (($gp_size == 32 && [mips_have_test_option_p options "-mfp64"])
+		 || [mips_have_test_option_p options "-msynci"]
+		 || [mips_have_test_option_p options "-mdsp"]
+		 || [mips_have_test_option_p options "-mdspr2"]) } {
+	    if { $gp_size == 32 } {
+		mips_make_test_option options "-mips32r2"
+	    } else {
+		mips_make_test_option options "-mips64r2"
+	    }
+        # We need a MIPS32 or MIPS64 ISA for:
+	#
+        #   - paired-single instructions(*)
+        #
+	# (*) Note that we don't support MIPS V at the moment.
+	} elseif { $isa_rev < 1
+		   && [mips_have_test_option_p options "-mpaired-single"] } {
+	    if { $gp_size == 32 } {
+		mips_make_test_option options "-mips32"
+	    } else {
+		mips_make_test_option options "-mips64"
+	    }
+        # We need MIPS III or higher for:
+	#
+	#   - the "cache" instruction
+	} elseif { $isa < 3
+		   && ([mips_have_test_option_p options \
+			    "-mr10k-cache-barrier=load-store"]
+		       || [mips_have_test_option_p options \
+			       "-mr10k-cache-barrier=store"]) } {
+	    mips_make_test_option options "-mips3"
+        # We need MIPS II or higher for:
+	#
+	#   - branch-likely instructions(*)
+        #
+	# (*) needed by both -mbranch-likely and -mfix-r10000
+	} elseif { $isa < 2
+		   && ([mips_have_test_option_p options "-mbranch-likely"]
+		       || [mips_have_test_option_p options "-mfix-r10000"]) } {
+	    mips_make_test_option options "-mips2"
+	# Check whether we need to switch from a 32-bit processor to the
+	# "nearest" 64-bit processor.
+	} elseif { $gp_size == 64 && [mips_32bit_arch_p $arch] } {
+	    if { $isa_rev == 0 } {
+		mips_make_test_option options "-mips3"
+	    } elseif { $isa_rev == 1 } {
+		mips_make_test_option options "-mips64"
+	    } else {
+		mips_make_test_option options "-mips64r$isa_rev"
+	    }
+	# Otherwise, if the current choice of architecture is unacceptable,
+	# choose the equivalent generic architecture.
+	} elseif { $force_generic_isa_p } {
+	    set arch "-mips[mips_arch_info $arch isa]"
+	    if { $isa_rev > 1 } {
+		append arch "r$isa_rev"
+	    }
+	    mips_make_test_option options $arch
+	}
+	unset arch
+	unset isa
+	unset isa_rev
+    }
+
+    # Set an appropriate ABI, handling dependencies between the pre-abi
+    # options and the abi options.  This should mirror the abi and post-abi
+    # code below.
+    if { !$abi_test_option_p } {
+	if { ($eabi_p
+	      && ([mips_have_option_p options "-mabicalls"]
+		  || ($gp_size == 32
+		      && [mips_have_option_p options "-mfp64"]))) } {
+	    # EABI doesn't support -mabicalls.
+	    # EABI doesn't support the combination -mgp32 -mfp64.
+	    set force_abi 1
+	} elseif { [mips_using_mips16_p options]
+		   && ![mips_same_option_p $abi "-mabi=32"]
+		   && ![mips_same_option_p $abi "-mabi=o64"]
+		   && (![mips_have_option_p options "addressing=absolute"]
+		       || [mips_have_option_p options "-mhard-float"]) } {
+	    # -mips16 -mhard-float requires o32 or o64.
+	    # -mips16 PIC requires o32 or o64.
+	    set force_abi 1
+	} elseif { [mips_have_test_option_p options "-mlong32"]
+		   && [mips_long64_abi_p $abi] } {
+	    set force_abi 1
+	} elseif { [mips_have_test_option_p options "-mlong64"]
+		   && [mips_long32_abi_p $abi] } {
+	    set force_abi 1
+	} else {
+	    set force_abi 0
+	}
+	if { $gp_size == 32 } {
+	    if { $force_abi || [mips_64bit_abi_p $abi] } {
+		if { [mips_have_test_option_p options "-mlong64"] } {
+		    mips_make_test_option options "-mabi=eabi"
+		    mips_make_test_option options "-mgp32"
+		} else {
+		    mips_make_test_option options "-mabi=32"
+		}
+	    }
+	} else {
+	    if { $force_abi || [mips_32bit_abi_p $abi] } {
+		if { [mips_have_test_option_p options "-mlong64"] } {
+		    mips_make_test_option options "-mabi=eabi"
+		    mips_make_test_option options "-mgp64"
+		} else {
+		    # All configurations should have an assembler that
+		    # supports o64, since it requires the same BFD target
+		    # vector as o32.  In contrast, many assembler
+		    # configurations do not have n32 or n64 support.
+		    mips_make_test_option options "-mabi=o64"
+		}
+	    }
+	}
+	set abi_test_option_p [mips_test_option_p options abi]
+	set abi [mips_option options abi]
+	set eabi_p [mips_same_option_p $abi "-mabi=eabi"]
+    }
+
+    # Handle dependencies between the abi options and the post-abi options.
+    # This should mirror the abi and pre-abi code above.
+    if { $abi_test_option_p } {
+	if { $eabi_p } {
+	    mips_make_test_option options "-mno-abicalls"
+	    if { $gp_size == 32 } {
+		mips_make_test_option options "-mfp32"
+	    }
+	}
+	if { [mips_using_mips16_p options]
+	     && ![mips_same_option_p $abi "-mabi=32"]
+	     && ![mips_same_option_p $abi "-mabi=o64"]
+	     && ([mips_have_option_p options "-mabicalls"]
+		 || [mips_have_option_p options "-mhard-float"]) } {
+	    if { [mips_test_option_p options mips16] } {
+		mips_make_test_option options "addressing=absolute"
+		mips_make_test_option options "-msoft-float"
+	    } else {
+		mips_make_test_option options "-mno-mips16"
+	    }
+	}
+	if { [mips_long32_abi_p $abi] } {
+	    mips_make_test_option options "-mlong32"
+	} elseif { [mips_long64_abi_p $abi] } {
+	    mips_make_test_option options "-mlong64"
+	}
+    }
+
+    # Handle dependencies between the arch option and the post-arch options.
+    # This should mirror the arch and pre-arch code above.
+    if { $arch_test_option_p } {
+	if { $isa < 2 } {
+	    mips_make_test_option options "-mno-branch-likely"
+	    mips_make_test_option options "-mno-fix-r10000"
+	}
+	if { $isa < 3 } {
+	    mips_make_test_option options "-mr10k-cache-barrier=none"
+	}
+	if { $isa_rev < 1 } {
+	    mips_make_test_option options "-mno-paired-single"
+	}
+	if { $isa_rev < 2 } {
+	    if { $gp_size == 32 } {
+		mips_make_test_option options "-mfp32"
+	    }
+	    mips_make_test_option options "-mno-dsp"
+	    mips_make_test_option options "-mno-synci"
+	}
+	unset arch
+	unset isa
+	unset isa_rev
+    }
+
+    # Handle dependencies between options on the right of the diagram.
+    mips_option_dependency options "-mno-dsp" "-mno-dspr2"
+    mips_option_dependency options "-mno-explicit-relocs" "-mgpopt"
+    switch -- [mips_test_option options small-data] {
+	"" -
+	-G0 {}
+	default {
+	    mips_make_test_option options "-mno-abicalls"
+	}
+    }
+    if { [mips_have_option_p options "-mabicalls"] } {
+	mips_option_dependency options "addressing=absolute" "-mplt"
+    }
+    mips_option_dependency options "-mplt" "-msym32"
+    mips_option_dependency options "-mplt" "-mno-shared"
+    mips_option_dependency options "-mno-shared" "-fno-pic"
+    mips_option_dependency options "-mfp32" "-mno-paired-single"
+    mips_option_dependency options "-msoft-float" "-mno-paired-single"
+    mips_option_dependency options "-mno-paired-single" "-mno-mips3d"
+
+    # If the test requires an unsupported option, change run tests
+    # to link tests.
+
+    switch -- [lindex $do_what 0] {
+	run {
+	    set option [mips_first_unsupported_option options]
+	    if { ![string equal $option ""] } {
+		set do_what [lreplace $do_what 0 0 link]
+		verbose -log "Downgraded to a 'link' test due to unsupported option '$option'"
+	    }
+	}
+    }
+
+    # If the test has overridden a option that changes the ABI,
+    # downgrade a link or execution test to an assembler test.
+    foreach group $mips_abi_groups {
+	set old_option [mips_original_option $group]
+	set new_option [mips_option options $group]
+	if { ![mips_same_option_p $old_option $new_option] } {
+	    switch -- [lindex $do_what 0] {
+		link -
+		run {
+		    set do_what [lreplace $do_what 0 0 assemble]
+		    verbose -log "Downgraded to an 'assemble' test due to incompatible $group option ($old_option changed to $new_option)"
+		}
+	    }
+	    break
+	}
+    }
+
+    # Add all options to the dg variable.
+    set options(explicit_p,addressing) 0
+    set options(explicit_p,forbid_cpu) 0
+    foreach { group regexp } $mips_option_groups {
+	if { $options(explicit_p,$group) } {
+	    append extra_tool_flags " " $options(option,$group)
+	}
+    }
+
+    # If the test is MIPS16-compatible, provide a counterpart to the
+    # NOMIPS16 convenience macro.
+    if { [mips_have_test_option_p options "-mips16"] } {
+	append extra_tool_flags " -DMIPS16=__attribute__((mips16))"
+    }
+
+    if { [mips_have_test_option_p options "-mmicromips"] } {
+	append extra_tool_flags " -DMICROMIPS=__attribute__((micromips))"
+    }
+
+    # Use our version of gcc-dg-test for this test.
+    if { ![string equal [info procs "mips-gcc-dg-test"] ""] } {
+	rename gcc-dg-test mips-old-gcc-dg-test
+	rename mips-gcc-dg-test gcc-dg-test
+    }
+}
+
+# A version of gcc-dg-test that is used by dg-options tests.
+proc mips-gcc-dg-test { prog do_what extra_tool_flags } {
+    global board_info
+    global mips_extra_options
+
+    # Override the user's chosen test options with the combined test/user
+    # version.
+    mips_push_test_options saved_options $mips_extra_options
+    set result [gcc-dg-test-1 gcc_target_compile $prog \
+		    $do_what $extra_tool_flags]
+    mips_pop_test_options saved_options
+
+    # Restore the usual gcc-dg-test.
+    rename gcc-dg-test mips-gcc-dg-test
+    rename mips-old-gcc-dg-test gcc-dg-test
+
+    return $result
+}
+
+dg-init
+mips-dg-init
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.c]] \
+    "-DNOMIPS16=__attribute__((nomips16)) -DNOMICROMIPS=__attribute__((nomicromips)) -DNOCOMPRESSION=__attribute__((nocompression))"
+mips-dg-finish
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c
new file mode 100644
index 000000000..bc81cfa7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-2.c
@@ -0,0 +1,16 @@
+/* { dg-skip-if "" { *-*-* } { "-mflip-mips16" } { "" } } */
+/* { dg-options "(-mips16)" } */
+
+void f1 (void);
+void __attribute__((mips16)) f1 (void) {} /* { dg-error "conflicting" } */
+
+void __attribute__((mips16)) f2 (void);
+void f2 (void) {} /* { dg-error "conflicting" } */
+
+void f3 (void);
+void __attribute__((nomips16)) f3 (void) {} /* { dg-error "conflicting" } */
+
+void __attribute__((nomips16)) f4 (void);
+void f4 (void) {} /* { dg-error "conflicting" } */
+
+void __attribute__((mips16, nomips16)) f5 (void) {} /* { dg-error "cannot have both" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c
new file mode 100644
index 000000000..747450390
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-3.c
@@ -0,0 +1,7 @@
+/* { dg-options "(-mips16)" } */
+/* We should be able to assign mips16 and nomips16 functions to a pointer.  */
+void __attribute__((mips16)) f1 (void);
+void (*ptr1) (void) = f1;
+
+void __attribute__((nomips16)) f2 (void);
+void (*ptr2) (void) = f2;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c
new file mode 100644
index 000000000..de7cb4349
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-4.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-options "(-mips16)" } */
+
+extern void abort (void);
+
+__complex float f = { -1.0 + -1.0i };
+__complex float __attribute__((nomips16)) foo (void) { return f; }
+__complex float (*volatile foop) (void) = foo;
+__complex float __attribute__((mips16, noinline)) bar (void) { return foop (); }
+
+int
+main (void)
+{
+  if (bar () != f)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-5.c
new file mode 100644
index 000000000..b84fa8862
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-5.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "(-mips16) addressing=absolute" } */
+/* { dg-skip-if "requires inlining" { *-*-* } { "-O0" } { "" } } */
+
+static inline MIPS16 int i1 (void) { return 1; }
+static inline NOMIPS16 int i2 (void) { return 2; }
+static inline MIPS16 int i3 (void) { return 3; }
+static inline NOMIPS16 int i4 (void) { return 4; }
+
+int NOMIPS16 f1 (void) { return i1 (); }
+int MIPS16 f2 (void) { return i2 (); }
+int MIPS16 f3 (void) { return i3 (); }
+int NOMIPS16 f4 (void) { return i4 (); }
+
+/* { dg-final { scan-assembler "i1:" } } */
+/* { dg-final { scan-assembler "i2:" } } */
+/* { dg-final { scan-assembler-not "i3:" } } */
+/* { dg-final { scan-assembler-not "i4:" } } */
+/* { dg-final { scan-assembler "\tjal\ti1" } } */
+/* { dg-final { scan-assembler "\tjal\ti2" } } */
+/* { dg-final { scan-assembler-not "\tjal\ti3" } } */
+/* { dg-final { scan-assembler-not "\tjal\ti4" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-6.c
new file mode 100644
index 000000000..99bdf8c3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes-6.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-mips16 addressing=absolute -mips3d" } */
+
+static inline NOMIPS16 float
+i1 (float f)
+{
+  return __builtin_mips_recip1_s (f);
+}
+
+float f1 (float f) { return i1 (f); }
+
+/* { dg-final { scan-assembler "\trecip1.s\t" } } */
+/* { dg-final { scan-assembler "\tjal\ti1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes.c
new file mode 100644
index 000000000..28bb9aae7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16-attributes.c
@@ -0,0 +1,83 @@
+/* Verify that mips16 and nomips16 attributes work, checking all combinations
+   of calling a nomips16/mips16/default function from a nomips16/mips16/default
+   function.  */
+/* { dg-do run } */
+/* { dg-options "(-mips16)" } */
+
+#include <stdlib.h>
+
+#define ATTR1 __attribute__ ((nomips16))
+#define ATTR2 __attribute__ ((mips16))
+#define ATTR3
+
+double ATTR1
+f1 (int i, float f, double d)
+{
+  return i + f + d;
+}
+
+double ATTR2
+f2 (int i, float f, double d)
+{
+  return i + f + d;
+}
+
+double ATTR3
+f3 (int i, float f, double d)
+{
+  return i + f + d;
+}
+
+void ATTR1
+g1 (int i, float f, double d)
+{
+  double r = i + f + d;
+
+  if (f1 (i, f, d) != r)
+    abort ();
+  if (f2 (i+1, f+1, d+1) != r + 3)
+    abort ();
+  if (f3 (i+2, f+2, d+2) != r + 6)
+    abort ();
+}
+
+void ATTR2
+g2 (int i, float f, double d)
+{
+  double r = i + f + d;
+
+  if (f1 (i, f, d) != r)
+    abort ();
+  if (f2 (i+1, f+1, d+1) != r + 3)
+    abort ();
+  if (f3 (i+2, f+2, d+2) != r + 6)
+    abort ();
+}
+
+void ATTR3
+g3 (int i, float f, double d)
+{
+  double r = i + f + d;
+
+  if (f1 (i, f, d) != r)
+    abort ();
+  if (f2 (i+1, f+1, d+1) != r + 3)
+    abort ();
+  if (f3 (i+2, f+2, d+2) != r + 6)
+    abort ();
+}
+
+int ATTR3
+main (void)
+{
+  int i = 1;
+  float f = -2.0;
+  double d = 3.0;
+
+  g1 (i, f, d);
+  g2 (i, f, d);
+  g3 (i, f, d);
+
+  exit (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16e-extends.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16e-extends.c
new file mode 100644
index 000000000..d8946c979
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips16e-extends.c
@@ -0,0 +1,22 @@
+/* -mlong32 added because of PR target/38595.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mlong32" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+MIPS16 short cksum16 (unsigned long n)
+{
+  unsigned long l;
+  l = validate (n, (n >> 16) + (n & 0xffff));
+  return l;
+}
+
+MIPS16 signed char cksum8 (unsigned long n)
+{
+  unsigned long l;
+  l = validate (n, (n >> 8) + (n & 0xff));
+  return l;
+}
+
+/* { dg-final { scan-assembler "\tzeh\t" } } */
+/* { dg-final { scan-assembler "\tseh\t" } } */
+/* { dg-final { scan-assembler "\tzeb\t" } } */
+/* { dg-final { scan-assembler "\tseb\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-1.c
new file mode 100644
index 000000000..d26f99840
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-1.c
@@ -0,0 +1,22 @@
+/* { dg-options "-mdspr2 -mgp32 -mtune=74kc" } */
+/* References to RESULT within the loop need to have a higher frequency than
+   references to RESULT outside the loop, otherwise there is no reason
+   to prefer multiply/accumulator registers over GPRs.  */
+/* { dg-skip-if "requires register frequencies" { *-*-* } { "-O0" "-Os" } { "" } } */
+
+/* Check that the zero-initialization of the accumulator feeding into
+   the madd is done by means of a mult instruction instead of mthi/mtlo.  */
+
+NOMIPS16 long long f (int n, int *v, int m)
+{
+  long long result = 0;
+  int i;
+
+  for (i = 0; i < n; i++)
+    result = __builtin_mips_madd (result, v[i], m);
+  return result;
+}
+
+/* { dg-final { scan-assembler "\tmult\t\\\$ac.,\\\$0,\\\$0" } } */
+/* { dg-final { scan-assembler-not "mthi\t" } } */
+/* { dg-final { scan-assembler-not "mtlo\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c
new file mode 100644
index 000000000..74608d943
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c
@@ -0,0 +1,23 @@
+/* { dg-options "-mdspr2 -mgp32 -mtune=4kp" } */
+/* References to RESULT within the loop need to have a higher frequency than
+   references to RESULT outside the loop, otherwise there is no reason
+   to prefer multiply/accumulator registers over GPRs.  */
+/* { dg-skip-if "requires register frequencies" { *-*-* } { "-O0" "-Os" } { "" } } */
+
+/* Check that the zero-initialization of the accumulator feeding into
+   the madd is done by means of an mthi & mtlo pair instead of a
+   "mult $0,$0" instruction.  */
+
+NOMIPS16 long long f (int n, int *v, int m)
+{
+  long long result = 0;
+  int i;
+
+  for (i = 0; i < n; i++)
+    result = __builtin_mips_madd (result, v[i], m);
+  return result;
+}
+
+/* { dg-final { scan-assembler-not "mult\t\[^\n\]*\\\$0" } } */
+/* { dg-final { scan-assembler "\tmthi\t" } } */
+/* { dg-final { scan-assembler "\tmtlo\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
new file mode 100644
index 000000000..ccd9d380f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-run.c
@@ -0,0 +1,1063 @@
+/* Test MIPS32 DSP instructions */
+/* { dg-do run } */
+/* { dg-options "-mdsp" } */
+
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2q15 __attribute__ ((vector_size(4)));
+
+typedef int q31;
+typedef int i32;
+typedef unsigned int ui32;
+typedef long long a64;
+
+NOMIPS16 void test_MIPS_DSP (void);
+
+char array[100];
+int little_endian;
+
+int main ()
+{
+  int i;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  for (i = 0; i < 100; i++)
+    array[i] = i;
+
+  test_MIPS_DSP ();
+
+  exit (0);
+}
+
+NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b)
+{
+  return __builtin_mips_addq_ph (a, b);
+}
+
+NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b)
+{
+  return __builtin_mips_addu_qb (a, b);
+}
+
+NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b)
+{
+  return __builtin_mips_subq_ph (a, b);
+}
+
+NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b)
+{
+  return __builtin_mips_subu_qb (a, b);
+}
+
+NOMIPS16 void test_MIPS_DSP ()
+{
+  v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
+  v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
+  q31 q31_a,q31_b,q31_c,q31_r,q31_s;
+  /* To protect the multiplication-related tests from being optimized
+     at compile time.  */
+  volatile i32 i32_a,i32_b,i32_c,i32_r,i32_s;
+  volatile ui32 ui32_a,ui32_b,ui32_c;
+  a64 a64_a,a64_b,a64_c,a64_r,a64_s;
+
+  void *ptr_a;
+  int r,s;
+  long long lr,ls;
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x81bd, 0x6789};
+  v2q15_r = add_v2q15 (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x7fff, 0x6789};
+  v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_b = 0x71234567;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_addq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89};
+  v4i8_r = add_v4i8 (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89};
+  v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0xa2ab, 0x4567};
+  v2q15_r = sub_v2q15 (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x8000, 0x4567};
+  v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_b = 0x71234567;
+  q31_s = 0xfedcba99;
+  q31_r = __builtin_mips_subq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67};
+  v4i8_r = sub_v4i8 (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67};
+  v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0xf5678900;
+  i32_b = 0x7abcdef0;
+  i32_s = 0x702467f0;
+  i32_r = __builtin_mips_addsc (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x75678900;
+  i32_b = 0x7abcdef0;
+  i32_s = 0xf02467f1;
+  i32_r = __builtin_mips_addwc (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0;
+  i32_b = 0x00000901;
+  i32_s = 9;
+  i32_r = __builtin_mips_modsub (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_s = 0x1f4;
+  i32_r = __builtin_mips_raddu_w_qb (v4i8_a);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8134};
+  v2q15_s = (v2q15) {0x7fff, 0x7ecc};
+  v2q15_r = __builtin_mips_absq_s_ph (v2q15_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = (q31) 0x80000000;
+  q31_s = (q31) 0x7fffffff;
+  q31_r = __builtin_mips_absq_s_w (q31_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x9999, 0x5612};
+  v2q15_b = (v2q15) {0x5612, 0x3333};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56};
+  else
+    v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33};
+  v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x12348678;
+  q31_b = 0x44445555;
+  if (little_endian)
+    v2q15_s = (v2q15) {0x4444, 0x1234};
+  else
+    v2q15_s = (v2q15) {0x1234, 0x4444};
+  v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x12348678;
+  q31_b = 0x44445555;
+  if (little_endian)
+    v2q15_s = (v2q15) {0x4444, 0x1235};
+  else
+    v2q15_s = (v2q15) {0x1235, 0x4444};
+  v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x9999, 0x5612};
+  v2q15_b = (v2q15) {0x5612, 0x3333};
+  if (little_endian)
+    v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac};
+  else
+    v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66};
+  v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3589, 0x4444};
+  if (little_endian)
+    q31_s = 0x44440000;
+  else
+    q31_s = 0x35890000;
+  q31_r = __builtin_mips_preceq_w_phl (v2q15_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3589, 0x4444};
+  if (little_endian)
+    q31_s = 0x35890000;
+  else
+    q31_s = 0x44440000;
+  q31_r = __builtin_mips_preceq_w_phr (v2q15_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  else
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  else
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  else
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  else
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x56, 0x33};
+  else
+    v2q15_s = (v2q15) {0x12, 0x56};
+  v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x12, 0x56};
+  else
+    v2q15_s = (v2q15) {0x56, 0x33};
+  v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x99, 0x33};
+  else
+    v2q15_s = (v2q15) {0x12, 0x56};
+  v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x12, 0x56};
+  else
+    v2q15_s = (v2q15) {0x99, 0x33};
+  v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0};
+  v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_b = 1;
+  v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0};
+  v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d0, 0x59e0};
+  v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x2468, 0xacf0};
+  v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d0, 0x7fff};
+  v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x2468, 0x7fff};
+  v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_shll_s_w (q31_a, 2);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x70000000;
+  i32_b = 1;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_shll_s_w (q31_a, i32_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e};
+  v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_b = 1;
+  v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c};
+  v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d, 0x159e};
+  v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x91a, 0x2b3c};
+  v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d, 0x159e};
+  v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 3;
+  v2q15_s = (v2q15) {0x247, 0xacf};
+  v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_s = 0x1c000000;
+  q31_r = __builtin_mips_shra_r_w (q31_a, 2);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x70000004;
+  i32_b = 3;
+  q31_s = 0x0e000001;
+  q31_r = __builtin_mips_shra_r_w (q31_a, i32_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  if (little_endian)
+    v2q15_s = (v2q15) {0xffff, 0x4444};
+  else
+    v2q15_s = (v2q15) {0x6f89, 0x2222};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x6f89, 0x2222};
+  else
+    v2q15_s = (v2q15) {0xffff, 0x4444};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x0fdd, 0x0b87};
+  v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b);
+  if (q31_r != q31_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x22222f27;
+  else
+    a64_s = 0x222238d9;
+  a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x222238d9;
+  else
+    a64_s = 0x22222f27;
+  a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x2221f2fb;
+  else
+    a64_s = 0x2221e949;
+  a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x2221e949;
+  else
+    a64_s = 0x2221f2fb;
+  a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  a64_s = 0x8b877d00;
+  a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  a64_s = 0xffffffff7478a522LL;
+  a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  if (little_endian)
+    a64_s = 0xffffffff8b877d02LL;
+  else
+    a64_s = 0x7478a520;
+  a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_s = 0x7fffffffffffffffLL;
+  a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_s = 0x8000000000001112LL;
+  a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x1115;
+  else
+    a64_s = 0x80001110;
+  a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x80001110;
+  else
+    a64_s = 0x1115;
+  a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x1115;
+  else
+    a64_s = 0x7fffffff;
+  a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x7fffffff;
+  else
+    a64_s = 0x1115;
+  a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+  i32_a = 0x12345678;
+  i32_s = 0x00001e6a;
+  i32_r = __builtin_mips_bitrev (i32_a);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x00000208; // pos is 8, size is 4
+  __builtin_mips_wrdsp (i32_a, 31);
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x12345178;
+  i32_r = __builtin_mips_insv (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_s = (v4i8) {1, 1, 1, 1};
+  v4i8_r = __builtin_mips_repl_qb (1);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 99;
+  v4i8_s = (v4i8) {99, 99, 99, 99};
+  v4i8_r = __builtin_mips_repl_qb (i32_a);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_s = (v2q15) {30, 30};
+  v2q15_r = __builtin_mips_repl_ph (30);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x5612;
+  v2q15_s = (v2q15) {0x5612, 0x5612};
+  v2q15_r = __builtin_mips_repl_ph (i32_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x03000000;
+  else
+    i32_s = 0x0c000000;
+  __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x04000000;
+  else
+    i32_s = 0x02000000;
+  __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x07000000;
+  else
+    i32_s = 0x0e000000;
+  __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x3;
+  else
+    i32_s = 0xc;
+  i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x4;
+  else
+    i32_s = 0x2;
+  i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x7;
+  else
+    i32_s = 0xe;
+  i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0,31); // Clear all condition code bits.
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    i32_s = 0x01000000;
+  else
+    i32_s = 0x02000000;
+  __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    i32_s = 0x02000000;
+  else
+    i32_s = 0x01000000;
+  __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  i32_s = 0x03000000;
+  __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0a000000; // cc: 0000 1010
+  __builtin_mips_wrdsp (i32_a, 31);
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78};
+  else
+    v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87};
+  v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x02000000; // cc: 0000 0010
+  __builtin_mips_wrdsp (i32_a, 31);
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x2143, 0x6587};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2143, 0x5678};
+  else
+    v2q15_s = (v2q15) {0x1234, 0x6587};
+  v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x7856, 0x1234};
+  else
+    v2q15_s = (v2q15) {0x5678, 0x1234};
+  v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x1234567887654321LL;
+  i32_s = 0x88765432;
+  i32_r = __builtin_mips_extr_w (a64_a, 4);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_s = 0x56788766;
+  i32_r = __builtin_mips_extr_r_w (a64_a, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x12345677fffffff8LL;
+  i32_s = 0x7fffffff;
+  i32_r = __builtin_mips_extr_rs_w (a64_a, 4);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_s = 0x7fff;
+  i32_r = __builtin_mips_extr_s_h (a64_a, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x0000007887658321LL;
+  i32_b = 24;
+  i32_s = 0x7887;
+  i32_r = __builtin_mips_extr_s_h (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  i32_b = 4;
+  i32_s = 0x88765432;
+  i32_r = __builtin_mips_extr_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_b = 16;
+  i32_s = 0x56788766;
+  i32_r = __builtin_mips_extr_r_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x12345677fffffff8LL;
+  i32_b = 4;
+  i32_s = 0x7fffffff;
+  i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_s = 8;
+  i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 7; // size is 8. NOTE!! we should use 7
+  i32_s = 0x87;
+  i32_r = __builtin_mips_extp (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_s = 8;
+  i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_s = 0x0000021b; // pos is 27
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 11; // size is 12. NOTE!!! We should use 11
+  i32_s = 0x876;
+  i32_r = __builtin_mips_extpdp (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_s = 0x00000213; // pos is 19
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  a64_s = 0x0012345678876543LL;
+  a64_r = __builtin_mips_shilo (a64_a, 8);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  i32_b = -16;
+  a64_s = 0x5678876543210000LL;
+  a64_r = __builtin_mips_shilo (a64_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+
+  i32_a = 0x0;
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 0x11112222;
+  a64_s = 0x8765432111112222LL;
+  a64_r = __builtin_mips_mthlip (a64_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+  i32_s = 32;
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+#endif
+
+  i32_a = 0x1357a468;
+  __builtin_mips_wrdsp (i32_a, 63);
+  i32_s = 0x03572428;
+  i32_r = __builtin_mips_rddsp (63);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 37;
+  i32_s = 37;
+  i32_r = __builtin_mips_lbux (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 38;
+  if (little_endian)
+    i32_s = 0x2726;
+  else
+    i32_s = 0x2627;
+  i32_r = __builtin_mips_lhx (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 40;
+  if (little_endian)
+    i32_s = 0x2b2a2928;
+  else
+    i32_s = 0x28292a2b;
+  i32_r = __builtin_mips_lwx (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x00000220; // pos is 32, size is 4
+  __builtin_mips_wrdsp (i32_a, 63);
+  i32_s = 1;
+  i32_r = __builtin_mips_bposge32 ();
+  if (i32_r != i32_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_s = 0xF7776EEF12345678LL;
+  a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_s = 0x0888911112345678LL;
+  a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_s = 0x0888911112345678LL;
+  a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_s = 0xF7776EEF12345678LL;
+  a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  i32_a = 0x80000000;
+  i32_b = 0x11112222;
+  a64_s = 0xF7776EEF00000000LL;
+  a64_r = __builtin_mips_mult (i32_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  ui32_a = 0x80000000;
+  ui32_b = 0x11112222;
+  a64_s = 0x888911100000000LL;
+  a64_r = __builtin_mips_multu (ui32_a, ui32_b);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c
new file mode 100644
index 000000000..2a901bbf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp-type.c
@@ -0,0 +1,30 @@
+/* Test MIPS32 DSP instructions */
+/* { dg-do compile } */
+/* { dg-options "-mdsp" } */
+/* { dg-final { scan-assembler "\taddq.ph\t" } } */
+/* { dg-final { scan-assembler "\taddu.qb\t" } } */
+/* { dg-final { scan-assembler "\tsubq.ph\t" } } */
+/* { dg-final { scan-assembler "\tsubu.qb\t" } } */
+
+typedef char v4qi __attribute__ ((vector_size(4)));
+typedef short v2hi __attribute__ ((vector_size(4)));
+
+NOMIPS16 v2hi add_v2hi (v2hi a, v2hi b)
+{
+  return a + b;
+}
+
+NOMIPS16 v4qi add_v4qi (v4qi a, v4qi b)
+{
+  return a + b;
+}
+
+NOMIPS16 v2hi sub_v2hi (v2hi a, v2hi b)
+{
+  return a - b;
+}
+
+NOMIPS16 v4qi sub_v4qi (v4qi a, v4qi b)
+{
+  return a - b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp.c
new file mode 100644
index 000000000..9aaf12018
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dsp.c
@@ -0,0 +1,1160 @@
+/* Test MIPS32 DSP instructions */
+/* { dg-do compile } */
+/* { dg-options "-mgp32 -mdsp" } */
+/* { dg-final { scan-assembler "\taddq.ph\t" } } */
+/* { dg-final { scan-assembler "\taddq_s.ph\t" } } */
+/* { dg-final { scan-assembler "\taddq_s.w\t" } } */
+/* { dg-final { scan-assembler "\taddu.qb\t" } } */
+/* { dg-final { scan-assembler "\taddu_s.qb\t" } } */
+/* { dg-final { scan-assembler "\tsubq.ph\t" } } */
+/* { dg-final { scan-assembler "\tsubq_s.ph\t" } } */
+/* { dg-final { scan-assembler "\tsubq_s.w\t" } } */
+/* { dg-final { scan-assembler "\tsubu.qb\t" } } */
+/* { dg-final { scan-assembler "\tsubu_s.qb\t" } } */
+/* { dg-final { scan-assembler "\taddsc\t" } } */
+/* { dg-final { scan-assembler "\taddwc\t" } } */
+/* { dg-final { scan-assembler "\tmodsub\t" } } */
+/* { dg-final { scan-assembler "\traddu.w.qb\t" } } */
+/* { dg-final { scan-assembler "\tabsq_s.ph\t" } } */
+/* { dg-final { scan-assembler "\tabsq_s.w\t" } } */
+/* { dg-final { scan-assembler "\tprecrq.qb.ph\t" } } */
+/* { dg-final { scan-assembler "\tprecrq.ph.w\t" } } */
+/* { dg-final { scan-assembler "\tprecrq_rs.ph.w\t" } } */
+/* { dg-final { scan-assembler "\tprecrqu_s.qb.ph\t" } } */
+/* { dg-final { scan-assembler "\tpreceq.w.phl\t" } } */
+/* { dg-final { scan-assembler "\tpreceq.w.phr\t" } } */
+/* { dg-final { scan-assembler "\tprecequ.ph.qbl\t" } } */
+/* { dg-final { scan-assembler "\tprecequ.ph.qbr\t" } } */
+/* { dg-final { scan-assembler "\tprecequ.ph.qbla\t" } } */
+/* { dg-final { scan-assembler "\tprecequ.ph.qbra\t" } } */
+/* { dg-final { scan-assembler "\tpreceu.ph.qbl\t" } } */
+/* { dg-final { scan-assembler "\tpreceu.ph.qbr\t" } } */
+/* { dg-final { scan-assembler "\tpreceu.ph.qbla\t" } } */
+/* { dg-final { scan-assembler "\tpreceu.ph.qbra\t" } } */
+/* { dg-final { scan-assembler "\tshllv?.qb\t" } } */
+/* { dg-final { scan-assembler "\tshllv?.ph\t" } } */
+/* { dg-final { scan-assembler "\tshllv?_s.ph\t" } } */
+/* { dg-final { scan-assembler "\tshllv?_s.w\t" } } */
+/* { dg-final { scan-assembler "\tshrlv?.qb\t" } } */
+/* { dg-final { scan-assembler "\tshrav?.ph\t" } } */
+/* { dg-final { scan-assembler "\tshrav?_r.ph\t" } } */
+/* { dg-final { scan-assembler "\tshrav?_r.w\t" } } */
+/* { dg-final { scan-assembler "\tmuleu_s.ph.qbl\t" } } */
+/* { dg-final { scan-assembler "\tmuleu_s.ph.qbr\t" } } */
+/* { dg-final { scan-assembler "\tmulq_rs.ph\t" } } */
+/* { dg-final { scan-assembler "\tmuleq_s.w.phl\t" } } */
+/* { dg-final { scan-assembler "\tmuleq_s.w.phr\t" } } */
+/* { dg-final { scan-assembler "\tdpau.h.qbl\t" } } */
+/* { dg-final { scan-assembler "\tdpau.h.qbr\t" } } */
+/* { dg-final { scan-assembler "\tdpsu.h.qbl\t" } } */
+/* { dg-final { scan-assembler "\tdpsu.h.qbr\t" } } */
+/* { dg-final { scan-assembler "\tdpaq_s.w.ph\t" } } */
+/* { dg-final { scan-assembler "\tdpsq_s.w.ph\t" } } */
+/* { dg-final { scan-assembler "\tmulsaq_s.w.ph\t" } } */
+/* { dg-final { scan-assembler "\tdpaq_sa.l.w\t" } } */
+/* { dg-final { scan-assembler "\tdpsq_sa.l.w\t" } } */
+/* { dg-final { scan-assembler "\tmaq_s.w.phl\t" } } */
+/* { dg-final { scan-assembler "\tmaq_s.w.phr\t" } } */
+/* { dg-final { scan-assembler "\tmaq_sa.w.phl\t" } } */
+/* { dg-final { scan-assembler "\tmaq_sa.w.phr\t" } } */
+/* { dg-final { scan-assembler "\tbitrev\t" } } */
+/* { dg-final { scan-assembler "\tinsv\t" } } */
+/* { dg-final { scan-assembler "\treplv?.qb\t" } } */
+/* { dg-final { scan-assembler "\trepl.ph\t" } } */
+/* { dg-final { scan-assembler "\treplv.ph\t" } } */
+/* { dg-final { scan-assembler "\tcmpu.eq.qb\t" } } */
+/* { dg-final { scan-assembler "\tcmpu.lt.qb\t" } } */
+/* { dg-final { scan-assembler "\tcmpu.le.qb\t" } } */
+/* { dg-final { scan-assembler "\tcmpgu.eq.qb\t" } } */
+/* { dg-final { scan-assembler "\tcmpgu.lt.qb\t" } } */
+/* { dg-final { scan-assembler "\tcmpgu.le.qb\t" } } */
+/* { dg-final { scan-assembler "\tcmp.eq.ph\t" } } */
+/* { dg-final { scan-assembler "\tcmp.lt.ph\t" } } */
+/* { dg-final { scan-assembler "\tcmp.le.ph\t" } } */
+/* { dg-final { scan-assembler "\tpick.qb\t" } } */
+/* { dg-final { scan-assembler "\tpick.ph\t" } } */
+/* { dg-final { scan-assembler "\tpackrl.ph\t" } } */
+/* { dg-final { scan-assembler "\textrv?.w\t" } } */
+/* { dg-final { scan-assembler "\textrv?_s.h\t" } } */
+/* { dg-final { scan-assembler "\textrv?_r.w\t" } } */
+/* { dg-final { scan-assembler "\textrv?_rs.w\t" } } */
+/* { dg-final { scan-assembler "\textpv?\t" } } */
+/* { dg-final { scan-assembler "\textpdpv?\t" } } */
+/* { dg-final { scan-assembler "\tshilov?\t" } } */
+/* { dg-final { scan-assembler "\tmthlip\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmthi\t" } } */
+/* { dg-final { scan-assembler "\tmtlo\t" } } */
+/* { dg-final { scan-assembler "\twrdsp\t" } } */
+/* { dg-final { scan-assembler "\trddsp\t" } } */
+/* { dg-final { scan-assembler "\tlbux?\t" } } */
+/* { dg-final { scan-assembler "\tlhx?\t" } } */
+/* { dg-final { scan-assembler "\tlwx?\t" } } */
+/* { dg-final { scan-assembler "\tbposge32\t" } } */
+/* { dg-final { scan-assembler "\tmadd\t" } } */
+/* { dg-final { scan-assembler "\tmaddu\t" } } */
+/* { dg-final { scan-assembler "\tmsub\t" } } */
+/* { dg-final { scan-assembler "\tmsubu\t" } } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+
+#include <stdlib.h>
+#include <stdio.h>
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2q15 __attribute__ ((vector_size(4)));
+
+typedef int q31;
+typedef int i32;
+typedef unsigned int ui32;
+typedef long long a64;
+
+NOMIPS16 void test_MIPS_DSP (void);
+
+char array[100];
+int little_endian;
+
+int main ()
+{
+  int i;
+
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  for (i = 0; i < 100; i++)
+    array[i] = i;
+
+  test_MIPS_DSP ();
+
+  exit (0);
+}
+
+NOMIPS16 v2q15 add_v2q15 (v2q15 a, v2q15 b)
+{
+  return __builtin_mips_addq_ph (a, b);
+}
+
+NOMIPS16 v4i8 add_v4i8 (v4i8 a, v4i8 b)
+{
+  return __builtin_mips_addu_qb (a, b);
+}
+
+NOMIPS16 v2q15 sub_v2q15 (v2q15 a, v2q15 b)
+{
+  return __builtin_mips_subq_ph (a, b);
+}
+
+NOMIPS16 v4i8 sub_v4i8 (v4i8 a, v4i8 b)
+{
+  return __builtin_mips_subu_qb (a, b);
+}
+
+NOMIPS16 void test_MIPS_DSP ()
+{
+  v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
+  v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
+  q31 q31_a,q31_b,q31_c,q31_r,q31_s;
+  /* To protect the multiplication-related tests from being optimized
+     at compile time.  */
+  volatile i32 i32_a,i32_b,i32_c,i32_r,i32_s;
+  volatile ui32 ui32_a,ui32_b,ui32_c;
+  a64 a64_a,a64_b,a64_c,a64_r,a64_s;
+
+  void *ptr_a;
+  int r,s;
+  long long lr,ls;
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x81bd, 0x6789};
+  v2q15_r = add_v2q15 (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x7fff, 0x6789};
+  v2q15_r = __builtin_mips_addq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_b = 0x71234567;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_addq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xf1, 0xbd, 0x67, 0x89};
+  v4i8_r = add_v4i8 (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xff, 0xbd, 0x67, 0x89};
+  v4i8_r = __builtin_mips_addu_s_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0xa2ab, 0x4567};
+  v2q15_r = sub_v2q15 (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x8000, 0x4567};
+  v2q15_r = __builtin_mips_subq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_b = 0x71234567;
+  q31_s = 0xfedcba99;
+  q31_r = __builtin_mips_subq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0xf3, 0xab, 0x45, 0x67};
+  v4i8_r = sub_v4i8 (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0xff, 0x89, 0x11, 0x11};
+  v4i8_s = (v4i8) {0x0, 0x0, 0x45, 0x67};
+  v4i8_r = __builtin_mips_subu_s_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0xf5678900;
+  i32_b = 0x7abcdef0;
+  i32_s = 0x702467f0;
+  i32_r = __builtin_mips_addsc (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x75678900;
+  i32_b = 0x7abcdef0;
+  i32_s = 0xf02467f1;
+  i32_r = __builtin_mips_addwc (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0;
+  i32_b = 0x00000901;
+  i32_s = 9;
+  i32_r = __builtin_mips_modsub (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_s = 0x1f4;
+  i32_r = __builtin_mips_raddu_w_qb (v4i8_a);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8134};
+  v2q15_s = (v2q15) {0x7fff, 0x7ecc};
+  v2q15_r = __builtin_mips_absq_s_ph (v2q15_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = (q31) 0x80000000;
+  q31_s = (q31) 0x7fffffff;
+  q31_r = __builtin_mips_absq_s_w (q31_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x9999, 0x5612};
+  v2q15_b = (v2q15) {0x5612, 0x3333};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x56, 0x33, 0x99, 0x56};
+  else
+    v4i8_s = (v4i8) {0x99, 0x56, 0x56, 0x33};
+  v4i8_r = __builtin_mips_precrq_qb_ph (v2q15_a, v2q15_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x12348678;
+  q31_b = 0x44445555;
+  if (little_endian)
+    v2q15_s = (v2q15) {0x4444, 0x1234};
+  else
+    v2q15_s = (v2q15) {0x1234, 0x4444};
+  v2q15_r = __builtin_mips_precrq_ph_w (q31_a, q31_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x12348678;
+  q31_b = 0x44445555;
+  if (little_endian)
+    v2q15_s = (v2q15) {0x4444, 0x1235};
+  else
+    v2q15_s = (v2q15) {0x1235, 0x4444};
+  v2q15_r = __builtin_mips_precrq_rs_ph_w (q31_a, q31_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x9999, 0x5612};
+  v2q15_b = (v2q15) {0x5612, 0x3333};
+  if (little_endian)
+    v4i8_s = (v4i8) {0xac, 0x66, 0x00, 0xac};
+  else
+    v4i8_s = (v4i8) {0x00, 0xac, 0xac, 0x66};
+  v4i8_r = __builtin_mips_precrqu_s_qb_ph (v2q15_a, v2q15_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3589, 0x4444};
+  if (little_endian)
+    q31_s = 0x44440000;
+  else
+    q31_s = 0x35890000;
+  q31_r = __builtin_mips_preceq_w_phl (v2q15_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3589, 0x4444};
+  if (little_endian)
+    q31_s = 0x35890000;
+  else
+    q31_s = 0x44440000;
+  q31_r = __builtin_mips_preceq_w_phr (v2q15_a);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  else
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  v2q15_r = __builtin_mips_precequ_ph_qbl (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  else
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  v2q15_r = __builtin_mips_precequ_ph_qbr (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  else
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  v2q15_r = __builtin_mips_precequ_ph_qbla (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x0900, 0x2b00};
+  else
+    v2q15_s = (v2q15) {0x2b00, 0x1980};
+  v2q15_r = __builtin_mips_precequ_ph_qbra (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x56, 0x33};
+  else
+    v2q15_s = (v2q15) {0x12, 0x56};
+  v2q15_r = __builtin_mips_preceu_ph_qbl (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x56, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x12, 0x56};
+  else
+    v2q15_s = (v2q15) {0x56, 0x33};
+  v2q15_r = __builtin_mips_preceu_ph_qbr (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x99, 0x33};
+  else
+    v2q15_s = (v2q15) {0x12, 0x56};
+  v2q15_r = __builtin_mips_preceu_ph_qbla (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x99, 0x56, 0x33};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x12, 0x56};
+  else
+    v2q15_s = (v2q15) {0x99, 0x33};
+  v2q15_r = __builtin_mips_preceu_ph_qbra (v4i8_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_s = (v4i8) {0xc8, 0xd0, 0x58, 0xe0};
+  v4i8_r = __builtin_mips_shll_qb (v4i8_a, 2);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_b = 1;
+  v4i8_s = (v4i8) {0xe4, 0x68, 0xac, 0xf0};
+  v4i8_r = __builtin_mips_shll_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d0, 0x59e0};
+  v2q15_r = __builtin_mips_shll_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x2468, 0xacf0};
+  v2q15_r = __builtin_mips_shll_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d0, 0x7fff};
+  v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x2468, 0x7fff};
+  v2q15_r = __builtin_mips_shll_s_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_shll_s_w (q31_a, 2);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x70000000;
+  i32_b = 1;
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_shll_s_w (q31_a, i32_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  v4i8_s = (v4i8) {0x3c, 0xd, 0x15, 0x1e};
+  v4i8_r = __builtin_mips_shrl_qb (v4i8_a, 2);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0xf2, 0x34, 0x56, 0x78};
+  i32_b = 1;
+  v4i8_s = (v4i8) {0x79, 0x1a, 0x2b, 0x3c};
+  v4i8_r = __builtin_mips_shrl_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d, 0x159e};
+  v2q15_r = __builtin_mips_shra_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 1;
+  v2q15_s = (v2q15) {0x91a, 0x2b3c};
+  v2q15_r = __builtin_mips_shra_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_s = (v2q15) {0x48d, 0x159e};
+  v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, 2);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  i32_b = 3;
+  v2q15_s = (v2q15) {0x247, 0xacf};
+  v2q15_r = __builtin_mips_shra_r_ph (v2q15_a, i32_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x70000000;
+  q31_s = 0x1c000000;
+  q31_r = __builtin_mips_shra_r_w (q31_a, 2);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x70000004;
+  i32_b = 3;
+  q31_s = 0x0e000001;
+  q31_r = __builtin_mips_shra_r_w (q31_a, i32_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  if (little_endian)
+    v2q15_s = (v2q15) {0xffff, 0x4444};
+  else
+    v2q15_s = (v2q15) {0x6f89, 0x2222};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbl (v4i8_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x1, 0x2, 0x3, 0x4};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x6f89, 0x2222};
+  else
+    v2q15_s = (v2q15) {0xffff, 0x4444};
+  v2q15_r = __builtin_mips_muleu_s_ph_qbr (v4i8_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x6f89, 0x1111};
+  v2q15_s = (v2q15) {0x0fdd, 0x0b87};
+  v2q15_r = __builtin_mips_mulq_rs_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_muleq_s_w_phl (v2q15_a, v2q15_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x8000, 0x8000};
+  v2q15_b = (v2q15) {0x8000, 0x8000};
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_muleq_s_w_phr (v2q15_a, v2q15_b);
+  if (q31_r != q31_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x22222f27;
+  else
+    a64_s = 0x222238d9;
+  a64_r = __builtin_mips_dpau_h_qbl (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x222238d9;
+  else
+    a64_s = 0x22222f27;
+  a64_r = __builtin_mips_dpau_h_qbr (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x2221f2fb;
+  else
+    a64_s = 0x2221e949;
+  a64_r = __builtin_mips_dpsu_h_qbl (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x22221111;
+  v4i8_b = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_c = (v4i8) {0xaa, 0x89, 0x11, 0x34};
+  if (little_endian)
+    a64_s = 0x2221e949;
+  else
+    a64_s = 0x2221f2fb;
+  a64_r = __builtin_mips_dpsu_h_qbr (a64_a, v4i8_b, v4i8_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  a64_s = 0x8b877d00;
+  a64_r = __builtin_mips_dpaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  a64_s = 0xffffffff7478a522LL;
+  a64_r = __builtin_mips_dpsq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x5678};
+  v2q15_c = (v2q15) {0x8000, 0x1111};
+  if (little_endian)
+    a64_s = 0xffffffff8b877d02LL;
+  else
+    a64_s = 0x7478a520;
+  a64_r = __builtin_mips_mulsaq_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_s = 0x7fffffffffffffffLL;
+  a64_r = __builtin_mips_dpaq_sa_l_w (a64_a, q31_b, q31_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  q31_b = 0x80000000;
+  q31_c = 0x80000000;
+  a64_s = 0x8000000000001112LL;
+  a64_r = __builtin_mips_dpsq_sa_l_w (a64_a, q31_b, q31_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x1115;
+  else
+    a64_s = 0x80001110;
+  a64_r = __builtin_mips_maq_s_w_phl (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x80001110;
+  else
+    a64_s = 0x1115;
+  a64_r = __builtin_mips_maq_s_w_phr (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x1115;
+  else
+    a64_s = 0x7fffffff;
+  a64_r = __builtin_mips_maq_sa_w_phl (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x00001111;
+  v2q15_b = (v2q15) {0x8000, 0x1};
+  v2q15_c = (v2q15) {0x8000, 0x2};
+  if (little_endian)
+    a64_s = 0x7fffffff;
+  else
+    a64_s = 0x1115;
+  a64_r = __builtin_mips_maq_sa_w_phr (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+  i32_a = 0x12345678;
+  i32_s = 0x00001e6a;
+  i32_r = __builtin_mips_bitrev (i32_a);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x00000208; // pos is 8, size is 4
+  __builtin_mips_wrdsp (i32_a, 31);
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x12345178;
+  i32_r = __builtin_mips_insv (i32_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_s = (v4i8) {1, 1, 1, 1};
+  v4i8_r = __builtin_mips_repl_qb (1);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 99;
+  v4i8_s = (v4i8) {99, 99, 99, 99};
+  v4i8_r = __builtin_mips_repl_qb (i32_a);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_s = (v2q15) {30, 30};
+  v2q15_r = __builtin_mips_repl_ph (30);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x5612;
+  v2q15_s = (v2q15) {0x5612, 0x5612};
+  v2q15_r = __builtin_mips_repl_ph (i32_a);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x03000000;
+  else
+    i32_s = 0x0c000000;
+  __builtin_mips_cmpu_eq_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x04000000;
+  else
+    i32_s = 0x02000000;
+  __builtin_mips_cmpu_lt_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x07000000;
+  else
+    i32_s = 0x0e000000;
+  __builtin_mips_cmpu_le_qb (v4i8_a, v4i8_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x3;
+  else
+    i32_s = 0xc;
+  i32_r=__builtin_mips_cmpgu_eq_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x4;
+  else
+    i32_s = 0x2;
+  i32_r = __builtin_mips_cmpgu_lt_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x12, 0x34, 0x78, 0x56};
+  if (little_endian)
+    i32_s = 0x7;
+  else
+    i32_s = 0xe;
+  i32_r = __builtin_mips_cmpgu_le_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0,31); // Clear all condition code bits.
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    i32_s = 0x01000000;
+  else
+    i32_s = 0x02000000;
+  __builtin_mips_cmp_eq_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    i32_s = 0x02000000;
+  else
+    i32_s = 0x01000000;
+  __builtin_mips_cmp_lt_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  i32_s = 0x03000000;
+  __builtin_mips_cmp_le_ph (v2q15_a, v2q15_b);
+  i32_r = __builtin_mips_rddsp (16);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0a000000; // cc: 0000 1010
+  __builtin_mips_wrdsp (i32_a, 31);
+  v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
+  v4i8_b = (v4i8) {0x21, 0x43, 0x65, 0x87};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x21, 0x34, 0x65, 0x78};
+  else
+    v4i8_s = (v4i8) {0x12, 0x43, 0x56, 0x87};
+  v4i8_r = __builtin_mips_pick_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x02000000; // cc: 0000 0010
+  __builtin_mips_wrdsp (i32_a, 31);
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x2143, 0x6587};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x2143, 0x5678};
+  else
+    v2q15_s = (v2q15) {0x1234, 0x6587};
+  v2q15_r = __builtin_mips_pick_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x1234, 0x5678};
+  v2q15_b = (v2q15) {0x1234, 0x7856};
+  if (little_endian)
+    v2q15_s = (v2q15) {0x7856, 0x1234};
+  else
+    v2q15_s = (v2q15) {0x5678, 0x1234};
+  v2q15_r = __builtin_mips_packrl_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x1234567887654321LL;
+  i32_s = 0x88765432;
+  i32_r = __builtin_mips_extr_w (a64_a, 4);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_s = 0x56788766;
+  i32_r = __builtin_mips_extr_r_w (a64_a, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x12345677fffffff8LL;
+  i32_s = 0x7fffffff;
+  i32_r = __builtin_mips_extr_rs_w (a64_a, 4);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_s = 0x7fff;
+  i32_r = __builtin_mips_extr_s_h (a64_a, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x0000007887658321LL;
+  i32_b = 24;
+  i32_s = 0x7887;
+  i32_r = __builtin_mips_extr_s_h (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  i32_b = 4;
+  i32_s = 0x88765432;
+  i32_r = __builtin_mips_extr_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887658321LL;
+  i32_b = 16;
+  i32_s = 0x56788766;
+  i32_r = __builtin_mips_extr_r_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x12345677fffffff8LL;
+  i32_b = 4;
+  i32_s = 0x7fffffff;
+  i32_r = __builtin_mips_extr_rs_w (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_s = 8;
+  i32_r = __builtin_mips_extp (a64_a, 3); // extract 4 bits
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 7; // size is 8. NOTE!! we should use 7
+  i32_s = 0x87;
+  i32_r = __builtin_mips_extp (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_s = 8;
+  i32_r = __builtin_mips_extpdp (a64_a, 3); // extract 4 bits
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_s = 0x0000021b; // pos is 27
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x0000021f; // pos is 31
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 11; // size is 12. NOTE!!! We should use 11
+  i32_s = 0x876;
+  i32_r = __builtin_mips_extpdp (a64_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_s = 0x00000213; // pos is 19
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  a64_s = 0x0012345678876543LL;
+  a64_r = __builtin_mips_shilo (a64_a, 8);
+  if (a64_r != a64_s)
+    abort ();
+
+  a64_a = 0x1234567887654321LL;
+  i32_b = -16;
+  a64_s = 0x5678876543210000LL;
+  a64_r = __builtin_mips_shilo (a64_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+
+  i32_a = 0x0;
+  __builtin_mips_wrdsp (i32_a, 31);
+  a64_a = 0x1234567887654321LL;
+  i32_b = 0x11112222;
+  a64_s = 0x8765432111112222LL;
+  a64_r = __builtin_mips_mthlip (a64_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+  i32_s = 32;
+  i32_r = __builtin_mips_rddsp (31);
+  if (i32_r != i32_s)
+    abort ();
+#endif
+
+  i32_a = 0x1357a468;
+  __builtin_mips_wrdsp (i32_a, 63);
+  i32_s = 0x03572428;
+  i32_r = __builtin_mips_rddsp (63);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 37;
+  i32_s = 37;
+  i32_r = __builtin_mips_lbux (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 38;
+  if (little_endian)
+    i32_s = 0x2726;
+  else
+    i32_s = 0x2627;
+  i32_r = __builtin_mips_lhx (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  ptr_a = &array;
+  i32_b = 40;
+  if (little_endian)
+    i32_s = 0x2b2a2928;
+  else
+    i32_s = 0x28292a2b;
+  i32_r = __builtin_mips_lwx (ptr_a, i32_b);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x00000220; // pos is 32, size is 4
+  __builtin_mips_wrdsp (i32_a, 63);
+  i32_s = 1;
+  i32_r = __builtin_mips_bposge32 ();
+  if (i32_r != i32_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_s = 0xF7776EEF12345678LL;
+  a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_s = 0x0888911112345678LL;
+  a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_s = 0x0888911112345678LL;
+  a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_s = 0xF7776EEF12345678LL;
+  a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  i32_a = 0x80000000;
+  i32_b = 0x11112222;
+  a64_s = 0xF7776EEF00000000LL;
+  a64_r = __builtin_mips_mult (i32_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  ui32_a = 0x80000000;
+  ui32_b = 0x11112222;
+  a64_s = 0x888911100000000LL;
+  a64_r = __builtin_mips_multu (ui32_a, ui32_b);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c
new file mode 100644
index 000000000..9501e9cbe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2-type.c
@@ -0,0 +1,12 @@
+/* Test MIPS32 DSP REV 2 instructions */
+/* { dg-do compile } */
+/* { dg-options "-mdspr2" } */
+/* { dg-final { scan-assembler "\tmul.ph\t" } } */
+
+typedef short v2hi __attribute__ ((vector_size(4)));
+
+NOMIPS16 v2hi mul_v2hi (v2hi a, v2hi b)
+{
+  return a * b;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2.c
new file mode 100644
index 000000000..1f7e92873
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32-dspr2.c
@@ -0,0 +1,541 @@
+/* Test MIPS32 DSP REV 2 instructions */
+/* { dg-do run } */
+/* { dg-options "-mdspr2" } */
+
+typedef signed char v4q7 __attribute__ ((vector_size(4)));
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef short v2q15 __attribute__ ((vector_size(4)));
+typedef short v2i16 __attribute__ ((vector_size(4)));
+typedef int q31;
+typedef int i32;
+typedef unsigned int ui32;
+typedef long long a64;
+
+void abort (void);
+
+NOMIPS16 void test_MIPS_DSPR2 (void);
+
+int little_endian;
+
+int main ()
+{
+  union { long long ll; int i[2]; } endianness_test;
+  endianness_test.ll = 1;
+  little_endian = endianness_test.i[0];
+
+  test_MIPS_DSPR2 ();
+
+  return 0;
+}
+
+NOMIPS16 void test_MIPS_DSPR2 ()
+{
+  v4q7 v4q7_a,v4q7_b,v4q7_c,v4q7_r,v4q7_s;
+  v4i8 v4i8_a,v4i8_b,v4i8_c,v4i8_r,v4i8_s;
+  v2q15 v2q15_a,v2q15_b,v2q15_c,v2q15_r,v2q15_s;
+  v2i16 v2i16_a,v2i16_b,v2i16_c,v2i16_r,v2i16_s;
+  q31 q31_a,q31_b,q31_c,q31_r,q31_s;
+  i32 i32_a,i32_b,i32_c,i32_r,i32_s;
+  ui32 ui32_a,ui32_b,ui32_c,ui32_r,ui32_s;
+  a64 a64_a,a64_b,a64_c,a64_r,a64_s;
+
+  int r,s;
+
+  v4q7_a = (v4i8) {0x81, 0xff, 0x80, 0x23};
+  v4q7_s = (v4i8) {0x7f, 0x01, 0x7f, 0x23};
+  v4q7_r = __builtin_mips_absq_s_qb (v4q7_a);
+  r = (int) v4q7_r;
+  s = (int) v4q7_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0xffff, 0x2468};
+  v2i16_b = (v2i16) {0x1234, 0x1111};
+  v2i16_s = (v2i16) {0x1233, 0x3579};
+  v2i16_r = __builtin_mips_addu_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0xffff, 0x2468};
+  v2i16_b = (v2i16) {0x1234, 0x1111};
+  v2i16_s = (v2i16) {0xffff, 0x3579};
+  v2i16_r = __builtin_mips_addu_s_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
+  v4i8_s = (v4i8) {0x11, 0x2a, 0x66, 0xff};
+  v4i8_r = __builtin_mips_adduh_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0xff};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x99, 0xff};
+  v4i8_s = (v4i8) {0x11, 0x2b, 0x66, 0xff};
+  v4i8_r = __builtin_mips_adduh_r_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x56784321;
+  i32_r = __builtin_mips_append (i32_a, i32_b, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x78876543;
+  i32_r = __builtin_mips_balign (i32_a, i32_b, 3);
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0, 63);
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
+  if (little_endian)
+    i32_s = 0xd;
+  else
+    i32_s = 0xb;
+  i32_r = __builtin_mips_cmpgdu_eq_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+  i32_r = __builtin_mips_rddsp (16);
+  if (little_endian)
+    i32_s = 0x0d000000;
+  else
+    i32_s = 0x0b000000;
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0, 63);
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x44};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
+  if (little_endian)
+    i32_s = 0x2;
+  else
+    i32_s = 0x4;
+  i32_r = __builtin_mips_cmpgdu_lt_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+  i32_r = __builtin_mips_rddsp (16);
+  if (little_endian)
+    i32_s = 0x02000000;
+  else
+    i32_s = 0x04000000;
+  if (i32_r != i32_s)
+    abort ();
+
+  __builtin_mips_wrdsp (0, 63);
+  v4i8_a = (v4i8) {0x11, 0x22, 0x33, 0x54};
+  v4i8_b = (v4i8) {0x11, 0x33, 0x33, 0x44};
+  if (little_endian)
+    i32_s = 0x7;
+  else
+    i32_s = 0xe;
+  i32_r = __builtin_mips_cmpgdu_le_qb (v4i8_a, v4i8_b);
+  if (i32_r != i32_s)
+    abort ();
+  i32_r = __builtin_mips_rddsp (16);
+  if (little_endian)
+    i32_s = 0x07000000;
+  else
+    i32_s = 0x0e000000;
+  if (i32_r != i32_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  v2i16_b = (v2i16) {0xffff, 0x1555};
+  v2i16_c = (v2i16) {0x1234, 0x3322};
+  a64_s = 0x1677088e;
+  a64_r = __builtin_mips_dpa_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  v2i16_b = (v2i16) {0xffff, 0x1555};
+  v2i16_c = (v2i16) {0x1234, 0x3322};
+  a64_s = 0x0df1a462;
+  a64_r = __builtin_mips_dps_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_s = 0xF7776EEF12345678LL;
+  a64_r = __builtin_mips_madd (a64_a, i32_b, i32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_s = 0x0888911112345678LL;
+  a64_r = __builtin_mips_maddu (a64_a, ui32_b, ui32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  i32_b = 0x80000000;
+  i32_c = 0x11112222;
+  a64_s = 0x0888911112345678LL;
+  a64_r = __builtin_mips_msub (a64_a, i32_b, i32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x12345678;
+  ui32_b = 0x80000000;
+  ui32_c = 0x11112222;
+  a64_s = 0xF7776EEF12345678LL;
+  a64_r = __builtin_mips_msubu (a64_a, ui32_b, ui32_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+  v2i16_a = (v2i16) {0xffff, 0x2468};
+  v2i16_b = (v2i16) {0x1234, 0x1111};
+  v2i16_s = (v2i16) {0xedcc, 0x52e8};
+  v2i16_r = __builtin_mips_mul_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0x8000, 0x7fff};
+  v2i16_b = (v2i16) {0x1234, 0x1111};
+  v2i16_s = (v2i16) {0x8000, 0x7fff};
+  v2i16_r = __builtin_mips_mul_s_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x80000000;
+  q31_b = 0x80000000; 
+  q31_s = 0x7fffffff;
+  q31_r = __builtin_mips_mulq_rs_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0xffff, 0x8000};
+  v2q15_b = (v2q15) {0x1111, 0x8000};
+  v2q15_s = (v2q15) {0xffff, 0x7fff};
+  v2q15_r = __builtin_mips_mulq_s_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x00000002;
+  q31_b = 0x80000000; 
+  q31_s = 0xfffffffe;
+  q31_r = __builtin_mips_mulq_s_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x19848419;
+  v2i16_b = (v2i16) {0xffff, 0x8000};
+  v2i16_c = (v2i16) {0x1111, 0x8000};
+  if (little_endian)
+    a64_s = 0x5984952a;
+  else
+    a64_s = 0xffffffffd9847308LL;
+  a64_r = __builtin_mips_mulsa_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  i32_a = 0x80000000;
+  i32_b = 0x11112222;
+  a64_s = 0xF7776EEF00000000LL;
+  a64_r = __builtin_mips_mult (i32_a, i32_b);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  ui32_a = 0x80000000;
+  ui32_b = 0x11112222;
+  a64_s = 0x888911100000000LL;
+  a64_r = __builtin_mips_multu (ui32_a, ui32_b);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+  v2i16_a = (v2i16) {0x1234, 0x5678};
+  v2i16_b = (v2i16) {0x2233, 0x5566};
+  if (little_endian)
+    v4i8_s = (v4i8) {0x33, 0x66, 0x34, 0x78};
+  else
+    v4i8_s = (v4i8) {0x34, 0x78, 0x33, 0x66};
+  v4i8_r = __builtin_mips_precr_qb_ph (v2i16_a, v2i16_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x33334444;
+  if (little_endian)
+    v2i16_s = (v2i16) {0x3444, 0x4567};
+  else
+    v2i16_s = (v2i16) {0x4567, 0x3444};
+  v2i16_r = __builtin_mips_precr_sra_ph_w (i32_a, i32_b, 4);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x33334444;
+  if (little_endian)
+    v2i16_s = (v2i16) {0x3444, 0x4568};
+  else
+    v2i16_s = (v2i16) {0x4568, 0x3444};
+  v2i16_r = __builtin_mips_precr_sra_r_ph_w (i32_a, i32_b, 4);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  i32_a = 0x12345678;
+  i32_b = 0x87654321;
+  i32_s = 0x43211234;
+  i32_r = __builtin_mips_prepend (i32_a, i32_b, 16);
+  if (i32_r != i32_s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
+  v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc};
+  v4i8_r = __builtin_mips_shra_qb (v4i8_a, 1);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
+  v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd};
+  v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, 1);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_b = 1;  
+  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
+  v4i8_s = (v4i8) {0x9, 0x22, 0x3b, 0xcc};
+  v4i8_r = __builtin_mips_shra_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  i32_b = 1;  
+  v4i8_a = (v4i8) {0x12, 0x45, 0x77, 0x99};
+  v4i8_s = (v4i8) {0x9, 0x23, 0x3c, 0xcd};
+  v4i8_r = __builtin_mips_shra_r_qb (v4i8_a, i32_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0x1357, 0x2468};
+  v2i16_s = (v2i16) {0x0135, 0x0246};
+  v2i16_r = __builtin_mips_shrl_ph (v2i16_a, 4);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  i32_b = 8;
+  v2i16_a = (v2i16) {0x1357, 0x2468};
+  v2i16_s = (v2i16) {0x0013, 0x0024};
+  v2i16_r = __builtin_mips_shrl_ph (v2i16_a, i32_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0x1357, 0x4455};
+  v2i16_b = (v2i16) {0x3333, 0x4444};
+  v2i16_s = (v2i16) {0xe024, 0x0011};
+  v2i16_r = __builtin_mips_subu_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v2i16_a = (v2i16) {0x1357, 0x4455};
+  v2i16_b = (v2i16) {0x3333, 0x4444};
+  v2i16_s = (v2i16) {0x0000, 0x0011};
+  v2i16_r = __builtin_mips_subu_s_ph (v2i16_a, v2i16_b);
+  r = (int) v2i16_r;
+  s = (int) v2i16_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
+  v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
+  v4i8_s = (v4i8) {0xcd ,0x17, 0xe8, 0xb3};
+  v4i8_r = __builtin_mips_subuh_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v4i8_a = (v4i8) {0x33 ,0x44, 0x55, 0x66};
+  v4i8_b = (v4i8) {0x99 ,0x15, 0x85, 0xff};
+  v4i8_s = (v4i8) {0xcd ,0x18, 0xe8, 0xb4};
+  v4i8_r = __builtin_mips_subuh_r_qb (v4i8_a, v4i8_b);
+  r = (int) v4i8_r;
+  s = (int) v4i8_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3334, 0x4444};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v2q15_s = (v2q15) {0x2222, 0x3333};
+  v2q15_r = __builtin_mips_addqh_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3334, 0x4444};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v2q15_s = (v2q15) {0x2223, 0x3333};
+  v2q15_r = __builtin_mips_addqh_r_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x11111112;
+  q31_b = 0x99999999;
+  q31_s = 0xd5555555;
+  q31_r = __builtin_mips_addqh_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x11111112;
+  q31_b = 0x99999999;
+  q31_s = 0xd5555556;
+  q31_r = __builtin_mips_addqh_r_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3334, 0x4444};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v2q15_s = (v2q15) {0x1111, 0x1111};
+  v2q15_r = __builtin_mips_subqh_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  v2q15_a = (v2q15) {0x3334, 0x4444};
+  v2q15_b = (v2q15) {0x1111, 0x2222};
+  v2q15_s = (v2q15) {0x1112, 0x1111};
+  v2q15_r = __builtin_mips_subqh_r_ph (v2q15_a, v2q15_b);
+  r = (int) v2q15_r;
+  s = (int) v2q15_s;
+  if (r != s)
+    abort ();
+
+  q31_a = 0x11111112;
+  q31_b = 0x99999999;
+  q31_s = 0x3bbbbbbc;
+  q31_r = __builtin_mips_subqh_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+  q31_a = 0x11111112;
+  q31_b = 0x99999999;
+  q31_s = 0x3bbbbbbd;
+  q31_r = __builtin_mips_subqh_r_w (q31_a, q31_b);
+  if (q31_r != q31_s)
+    abort ();
+
+#ifndef __mips64
+  a64_a = 0x1111222212345678LL;
+  v2i16_b = (v2i16) {0x1, 0x2};
+  v2i16_c = (v2i16) {0x3, 0x4};
+  a64_s = 0x1111222212345682LL;
+  a64_r = __builtin_mips_dpax_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x9999111112345678LL;
+  v2i16_b = (v2i16) {0x1, 0x2};
+  v2i16_c = (v2i16) {0x3, 0x4};
+  a64_s = 0x999911111234566eLL;
+  a64_r = __builtin_mips_dpsx_w_ph (a64_a, v2i16_b, v2i16_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x70000000;
+  v2q15_b = (v2q15) {0x4000, 0x2000};
+  v2q15_c = (v2q15) {0x2000, 0x4000};
+  a64_s = 0x98000000;
+  a64_r = __builtin_mips_dpaqx_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x70000000;
+  v2q15_b = (v2q15) {0x4000, 0x2000};
+  v2q15_c = (v2q15) {0x2000, 0x4000};
+  a64_s = 0x7fffffff;
+  a64_r = __builtin_mips_dpaqx_sa_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0x70000000;
+  v2q15_b = (v2q15) {0x4000, 0x2000};
+  v2q15_c = (v2q15) {0x2000, 0x4000};
+  a64_s = 0x48000000;
+  a64_r = __builtin_mips_dpsqx_s_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+
+#ifndef __mips64
+  a64_a = 0xFFFFFFFF80000000LL;
+  v2q15_b = (v2q15) {0x4000, 0x2000};
+  v2q15_c = (v2q15) {0x2000, 0x4000};
+  a64_s = 0xFFFFFFFF80000000LL;
+  a64_r = __builtin_mips_dpsqx_sa_w_ph (a64_a, v2q15_b, v2q15_c);
+  if (a64_r != a64_s)
+    abort ();
+#endif
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c
new file mode 100644
index 000000000..899ac0100
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips32r2-mxhc1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=32 -mfp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmthc1\t" } } */
+/* { dg-final { scan-assembler "\tmfhc1\t" } } */
+
+NOMIPS16 double func1 (long long a)
+{
+  return a;
+}
+
+NOMIPS16 long long func2 (double b)
+{
+  return b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c
new file mode 100644
index 000000000..02e616657
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx.c
@@ -0,0 +1,11 @@
+/* Test MIPS64 DSP instructions */
+/* { dg-do compile } */
+/* { dg-options "-mgp64 -mdsp" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* { dg-final { scan-assembler "\tldx\t" } } */
+
+NOMIPS16 signed long long test (signed long long *a, int index)
+{
+  return a[index];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c
new file mode 100644
index 000000000..b7f3bc8f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mips64-dsp-ldx1.c
@@ -0,0 +1,10 @@
+/* Test MIPS64 DSP instructions */
+/* { dg-do compile } */
+/* { dg-options "-mgp64 -mdsp" }  */
+
+/* { dg-final { scan-assembler "\tldx\t" } } */
+
+NOMIPS16 signed long long test (signed long long *a, int index)
+{
+  return __builtin_mips_ldx (a, index);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c
new file mode 100644
index 000000000..3d07939ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-pg -mmcount-ra-address -mabi=64" } */
+/* { dg-final { scan-assembler "\tmove\t\\\$12,\\\$0" } } */
+NOMIPS16 int bazl(int i)
+{
+  return i + 2;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c
new file mode 100644
index 000000000..34b30d987
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-pg -mmcount-ra-address -mabi=64 -mno-abicalls" } */
+/* { dg-skip-if "requiring a specific frame layout makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdla\t\\\$12,8\\(\\\$sp\\)" } } */
+int foo (int);
+NOMIPS16 int bar (int i)
+{
+  return foo (i) + 2;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c
new file mode 100644
index 000000000..17bcb76be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mmcount-ra-address-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-pg -mmcount-ra-address -mabi=64 -mno-abicalls" } */
+/* { dg-skip-if "requiring a specific frame layout makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdla\t\\\$12,200008\\(\\\$sp\\)" } } */
+int foo (int *);
+NOMIPS16 int bar(int i)
+{
+  int big[50000];
+  return foo (big) + 2;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c
new file mode 100644
index 000000000..b3fe188d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "isa>=4" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmovz\t" } } */
+/* { dg-final { scan-assembler "\tmovn\t" } } */
+
+void ext_int (int);
+
+NOMIPS16 int
+sub1 (int i, int j, int k)
+{
+  ext_int (k ? i : j);
+}
+
+NOMIPS16 int
+sub2 (int i, int j, long l)
+{
+  ext_int (!l ? i : j);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c
new file mode 100644
index 000000000..2638d51fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "isa>=4" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmovz\t" } } */
+/* { dg-final { scan-assembler "\tmovn\t" } } */
+
+void ext_long (long);
+
+NOMIPS16 long
+sub4 (long i, long j, long k)
+{
+  ext_long (k ? i : j);
+}
+
+NOMIPS16 long
+sub5 (long i, long j, int k)
+{
+  ext_long (!k ? i : j);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c
new file mode 100644
index 000000000..f356465c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/movcc-3.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+/* { dg-options "isa>=4 -mhard-float" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmovt\t" } } */
+/* { dg-final { scan-assembler "\tmovf\t" } } */
+/* { dg-final { scan-assembler "\tmovz.s\t" } } */
+/* { dg-final { scan-assembler "\tmovn.s\t" } } */
+/* { dg-final { scan-assembler "\tmovt.s\t" } } */
+/* { dg-final { scan-assembler "\tmovz.d\t" } } */
+/* { dg-final { scan-assembler "\tmovn.d\t" } } */
+/* { dg-final { scan-assembler "\tmovf.d\t" } } */
+
+void ext_int (int);
+void ext_long (long);
+void ext_float (float);
+void ext_double (double);
+
+NOMIPS16 int
+sub3 (int i, int j, float f)
+{
+  ext_int (f ? i : j);
+}
+
+NOMIPS16 long
+sub6 (long i, long j, float f)
+{
+  ext_long (!f ? i : j);
+}
+
+NOMIPS16 float
+sub7 (float f, float g, int i)
+{
+  ext_float (i ? f : g);
+}
+
+NOMIPS16 float
+sub8 (float f, float g, long l)
+{
+  ext_float (!l ? f : g);
+}
+
+NOMIPS16 float
+sub9 (float f, float g, float h)
+{
+  ext_float (h ? f : g);
+}
+
+NOMIPS16 double
+suba (double f, double g, int i)
+{
+  ext_double (i ? f : g);
+}
+
+NOMIPS16 double
+subb (double f, double g, long l)
+{
+  ext_double (!l ? f : g);
+}
+
+NOMIPS16 double
+subc (double f, double g, double h)
+{
+  ext_double (!h ? f : g);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-1.c
new file mode 100644
index 000000000..9a222bfda
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-march=vr5400 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsac\t\\\$0," 2 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return z - (long long) y * x;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-2.c
new file mode 100644
index 000000000..c0923cd11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-march=vr5500 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return z - (long long) y * x;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c
new file mode 100644
index 000000000..aedd04302
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsub\t" 2 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return z - (long long) y * x;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-4.c
new file mode 100644
index 000000000..84cb5fe33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-mdspr2 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsub\t\\\$ac" 2 } } */
+
+NOMIPS16 long long
+f1 (int x, int y, long long z)
+{
+  return z - (long long) y * x;
+}
+
+NOMIPS16 long long
+f2 (int x, int y, long long z)
+{
+  long long t = (long long) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-5.c
new file mode 100644
index 000000000..eba104c7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-5.c
@@ -0,0 +1,9 @@
+/* { dg-options "-march=5kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsub\t" 4 } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-times "\tmflo\t" 3 } } */
+
+NOMIPS16 void f1 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3]; }
+NOMIPS16 void f2 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3] - a[4]; }
+NOMIPS16 void f3 (int *a) { a[0] = a[0] * a[1] - a[2] * a[3] - a[4] * a[5]; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-6.c
new file mode 100644
index 000000000..32411e61f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-6.c
@@ -0,0 +1,7 @@
+/* { dg-options "-march=5kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tmsub\t" } } */
+/* { dg-final { scan-assembler "\tmul\t" } } */
+/* { dg-final { scan-assembler "\tsubu\t" } } */
+
+NOMIPS16 void f1 (int *a) { a[0] = a[0] - a[1] * a[2]; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-7.c
new file mode 100644
index 000000000..ee049876e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-7.c
@@ -0,0 +1,16 @@
+/* { dg-options "-march=5kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-skip-if "requires -fira-region=all or =mixed" { *-*-* } { "-Os" } { "" } } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+/* { dg-final { scan-assembler "\tmsub\t" } } */
+
+NOMIPS16 int
+f1 (int *a, int *b, int n)
+{
+  int x, i;
+
+  x = 100;
+  for (i = 0; i < n; i++)
+    x -= a[i] * b[i];
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-8.c
new file mode 100644
index 000000000..a66307f10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msub-8.c
@@ -0,0 +1,16 @@
+/* { dg-options "-march=5kc" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmul\t" } } */
+/* { dg-final { scan-assembler-not "\tmsub\t" } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+NOMIPS16 int
+f2 (int x, int y, int z)
+{
+  asm volatile ("" ::: "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9",
+		"$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17",
+		"$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25",
+		"$31");
+  return x - y * z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-1.c
new file mode 100644
index 000000000..e1146f8bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-1.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-march=vr5400 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsacu\t\\\$0," 2 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return z - (ull) y * x;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-2.c
new file mode 100644
index 000000000..642d12394
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-march=vr5500 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsubu\t" 2 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return z - (ull) y * x;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c
new file mode 100644
index 000000000..2e936ebe0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-3.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "isa_rev>=1 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsubu\t" 2 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return z - (ull) y * x;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-4.c
new file mode 100644
index 000000000..a4f611860
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/msubu-4.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* This test requires widening_mul */
+/* { dg-options "-mdspr2 -mgp32 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tmsubu\t\\\$ac" 2 } } */
+
+typedef unsigned int ui;
+typedef unsigned long long ull;
+
+NOMIPS16 ull
+f1 (ui x, ui y, ull z)
+{
+  return z - (ull) y * x;
+}
+
+NOMIPS16 ull
+f2 (ui x, ui y, ull z)
+{
+  ull t = (ull) x * y;
+  int temp = 5;
+  if (temp == 5)
+    z -= t;
+  return z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-1.c
new file mode 100644
index 000000000..0997fd934
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-1.c
@@ -0,0 +1,10 @@
+/* { dg-final { scan-assembler "\t.globl\tf7" } } */
+/* { dg-final { scan-assembler "\tsll\t" } } */
+/* { dg-final { scan-assembler "\tsubu\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+int
+f7(int x)
+{
+  return x * 7;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-2.c
new file mode 100644
index 000000000..4cc2224df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-2.c
@@ -0,0 +1,10 @@
+/* { dg-final { scan-assembler "\t.globl\tf9" } } */
+/* { dg-final { scan-assembler "\tsll\t" } } */
+/* { dg-final { scan-assembler "\taddu\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+int
+f9(int x)
+{
+  return x * 9;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-3.c
new file mode 100644
index 000000000..552d8c99d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-3.c
@@ -0,0 +1,12 @@
+/* { dg-final { scan-assembler "\t.globl\tf15" } } */
+/* { dg-final { scan-assembler "\tsll\t" } } */
+/* { dg-final { scan-assembler "\tsubu\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+int
+f15(int x)
+{
+  return x * 15;
+}
+
+				    
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-4.c
new file mode 100644
index 000000000..7694d2c03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mulsize-4.c
@@ -0,0 +1,11 @@
+/* { dg-final { scan-assembler "\t.globl\tf17" } } */
+/* { dg-final { scan-assembler "\tsll\t" } } */
+/* { dg-final { scan-assembler "\taddu\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "\tmul\t" } } */
+int
+f17(int x)
+{
+  return x * 17;
+}
+				    
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-1.c
new file mode 100644
index 000000000..1038797f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-1.c
@@ -0,0 +1,16 @@
+/* For SI->DI widening multiplication we should use DINS to combine the two
+   halves.  For Octeon use DMUL with explicit widening.  */
+/* This test requires widening_mul */
+/* { dg-options "-mgp64 isa_rev>=2 forbid_cpu=octeon.* -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdins\t" } } */
+/* { dg-final { scan-assembler-not "\tdsll\t" } } */
+/* { dg-final { scan-assembler-not "\tdsrl\t" } } */
+/* { dg-final { scan-assembler-not "\tor\t" } } */
+
+NOMIPS16 unsigned long long
+f (unsigned int i, unsigned int j)
+{
+  i++;
+  return (unsigned long long) i * j;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-10.c
new file mode 100644
index 000000000..c479ebbc5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-10.c
@@ -0,0 +1,15 @@
+/* This test requires widening_mul */
+/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-11.c
new file mode 100644
index 000000000..8b26c1de7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-11.c
@@ -0,0 +1,15 @@
+/* This test requires widening_mul */
+/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-12.c
new file mode 100644
index 000000000..bf8d36c76
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-12.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-13.c
new file mode 100644
index 000000000..beb6ab943
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-13.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-14.c
new file mode 100644
index 000000000..e3cbd75bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-14.c
@@ -0,0 +1,16 @@
+/* { dg-options "-mgp32 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tdsll\t" } } */
+/* { dg-final { scan-assembler-not "\tdsrl\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 DI
+f (SI x, SI y)
+{
+  return (DI) x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-15.c
new file mode 100644
index 000000000..da47bd292
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-15.c
@@ -0,0 +1,16 @@
+/* { dg-options "-mgp32 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tdsll\t" } } */
+/* { dg-final { scan-assembler-not "\tdsrl\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 DI
+f (SI x, SI y)
+{
+  return (DI) x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-16.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-16.c
new file mode 100644
index 000000000..3e9b3785b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-16.c
@@ -0,0 +1,15 @@
+/* This test requires widening_mul */
+/* { dg-options "-mgp32 (-mips16) -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-17.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-17.c
new file mode 100644
index 000000000..84baff8cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-17.c
@@ -0,0 +1,14 @@
+/* { dg-options "-mgp32 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-18.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-18.c
new file mode 100644
index 000000000..52487f30d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-18.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mgp32 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-19.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-19.c
new file mode 100644
index 000000000..11cdb17c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-19.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mgp32 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 SI
+f (SI x, SI y)
+{
+  return x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-2.c
new file mode 100644
index 000000000..77be31162
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-2.c
@@ -0,0 +1,14 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdmult\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+
+typedef int TI __attribute__((mode(TI)));
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 TI
+f (DI x, DI y)
+{
+  return (TI) x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-3.c
new file mode 100644
index 000000000..e46978bc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-3.c
@@ -0,0 +1,14 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdmultu\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+
+typedef unsigned int TI __attribute__((mode(TI)));
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 TI
+f (DI x, DI y)
+{
+  return (TI) x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-4.c
new file mode 100644
index 000000000..939ca5cdb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-4.c
@@ -0,0 +1,15 @@
+/* This test requires widening_mul */
+/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdmult\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+typedef int TI __attribute__((mode(TI)));
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return ((TI) x * y) >> 64;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-5.c
new file mode 100644
index 000000000..efb06af85
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-5.c
@@ -0,0 +1,14 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdmultu\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+typedef unsigned int TI __attribute__((mode(TI)));
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return ((TI) x * y) >> 64;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-6.c
new file mode 100644
index 000000000..82d4f5d45
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-6.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-7.c
new file mode 100644
index 000000000..35b074980
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-7.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mgp64 (-mips16)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdmultu?\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+
+MIPS16 DI
+f (DI x, DI y)
+{
+  return x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-8.c
new file mode 100644
index 000000000..18dce2013
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-8.c
@@ -0,0 +1,17 @@
+/* This test requires widening_mul */
+/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmult\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */
+/* { dg-final { scan-assembler "\tdsrl\t" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+MIPS16 DI
+f (SI x, SI y)
+{
+  return (DI) x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-9.c
new file mode 100644
index 000000000..59d450ab2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/mult-9.c
@@ -0,0 +1,17 @@
+/* This test requires widening_mul */
+/* { dg-options "-mgp64 (-mips16) -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tmultu\t" } } */
+/* { dg-final { scan-assembler "\tmflo\t" } } */
+/* { dg-final { scan-assembler "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-times "\tdsll\t" 2 } } */
+/* { dg-final { scan-assembler "\tdsrl\t" } } */
+
+typedef unsigned int DI __attribute__((mode(DI)));
+typedef unsigned int SI __attribute__((mode(SI)));
+
+MIPS16 DI
+f (SI x, SI y)
+{
+  return (DI) x * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-2008.c
new file mode 100644
index 000000000..fc776e5fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-2008.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=2008 -EB" } */
+
+double d = __builtin_nan ("");
+
+/* { dg-final { scan-assembler "\t\\.nan\t2008\n" } } */
+/* { dg-final { scan-assembler "\t\\.word\t2146959360\n\t\\.word\t0\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-legacy.c
new file mode 100644
index 000000000..359ca221e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nan-legacy.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=legacy -EB" } */
+
+double d = __builtin_nan ("");
+
+/* { dg-final { scan-assembler "\t\\.nan\tlegacy\n" } } */
+/* { dg-final { scan-assembler "\t\\.word\t2146959359\n\t\\.word\t(?:-1|4294967295)\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-2008.c
new file mode 100644
index 000000000..fb5e28588
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-2008.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=2008 -EB" } */
+
+float f = __builtin_nanf ("");
+
+/* { dg-final { scan-assembler "\t\\.nan\t2008\n" } } */
+/* { dg-final { scan-assembler "\t\\.word\t2143289344\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-legacy.c
new file mode 100644
index 000000000..6db278ef1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nanf-legacy.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=legacy -EB" } */
+
+float f = __builtin_nanf ("");
+
+/* { dg-final { scan-assembler "\t\\.nan\tlegacy\n" } } */
+/* { dg-final { scan-assembler "\t\\.word\t2143289343\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-2008.c
new file mode 100644
index 000000000..2da0c2df4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-2008.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=2008 -EB" } */
+
+double ds = __builtin_nans ("");
+
+/* { dg-final { scan-assembler "\t\\.nan\t2008\n" } } */
+/* { dg-final { scan-assembler "\t\\.word\t2146697216\n\t\\.word\t0\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-legacy.c
new file mode 100644
index 000000000..0ce4226b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nans-legacy.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=legacy -EB" } */
+
+double ds = __builtin_nans ("");
+
+/* { dg-final { scan-assembler "\t\\.nan\tlegacy\n" } } */
+/* { dg-final { scan-assembler "\t\\.word\t2147483647\n\t\\.word\t(?:-1|4294967295)\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-2008.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-2008.c
new file mode 100644
index 000000000..d368add19
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-2008.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=2008 -EB" } */
+
+float fs = __builtin_nansf ("");
+
+/* { dg-final { scan-assembler "\t\\.nan\t2008\n" } } */
+/* { dg-final { scan-assembler "\t\\.word\t2141192192\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-legacy.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-legacy.c
new file mode 100644
index 000000000..8a518670c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nansf-legacy.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mnan=legacy -EB" } */
+
+float fs = __builtin_nansf ("");
+
+/* { dg-final { scan-assembler "\t\\.nan\tlegacy\n" } } */
+/* { dg-final { scan-assembler "\t\\.word\t2147483647\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-1.c
new file mode 100644
index 000000000..ac0cc1ef7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mlong-calls addressing=absolute" } */
+
+extern int long_call_func () __attribute__((long_call));
+extern int far_func () __attribute__((far));
+extern int near_func () __attribute__((near));
+extern int normal_func ();
+
+int test ()
+{
+  return (long_call_func ()
+          + far_func ()
+          + near_func ()
+          + normal_func ());
+}
+
+/* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */
+/* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */
+/* { dg-final { scan-assembler     "\tjal\tnear_func\n" } } */
+/* { dg-final { scan-assembler-not "\tjal\tnormal_func\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-2.c
new file mode 100644
index 000000000..c954b444c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-long-calls addressing=absolute" } */
+
+extern int long_call_func () __attribute__((long_call));
+extern int far_func () __attribute__((far));
+extern int near_func () __attribute__((near));
+extern int normal_func ();
+
+int test ()
+{
+  return (long_call_func ()
+          + far_func ()
+          + near_func ()
+          + normal_func ());
+}
+
+/* { dg-final { scan-assembler-not "\tjal\tlong_call_func\n" } } */
+/* { dg-final { scan-assembler-not "\tjal\tfar_func\n" } } */
+/* { dg-final { scan-assembler     "\tjal\tnear_func\n" } } */
+/* { dg-final { scan-assembler     "\tjal\tnormal_func\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-3.c
new file mode 100644
index 000000000..d4d48b1ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mlong-calls addressing=absolute" } */
+
+NOMIPS16 extern int long_call_func () __attribute__((long_call));
+NOMIPS16 extern int far_func () __attribute__((far));
+NOMIPS16 extern int near_func () __attribute__((near));
+NOMIPS16 extern int normal_func ();
+
+NOMIPS16 int test1 () { return long_call_func (); }
+NOMIPS16 int test2 () { return far_func (); }
+NOMIPS16 int test3 () { return near_func (); }
+NOMIPS16 int test4 () { return normal_func (); }
+
+/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */
+/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */
+/* { dg-final { scan-assembler     "\tj(|al)\tnear_func\n" } } */
+/* { dg-final { scan-assembler-not "\tj\tnormal_func\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-4.c
new file mode 100644
index 000000000..0ea07b062
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/near-far-4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-long-calls addressing=absolute" } */
+
+NOMIPS16 extern int long_call_func () __attribute__((long_call));
+NOMIPS16 extern int far_func () __attribute__((far));
+NOMIPS16 extern int near_func () __attribute__((near));
+NOMIPS16 extern int normal_func ();
+
+NOMIPS16 int test1 () { return long_call_func (); }
+NOMIPS16 int test2 () { return far_func (); }
+NOMIPS16 int test3 () { return near_func (); }
+NOMIPS16 int test4 () { return normal_func (); }
+
+/* { dg-final { scan-assembler-not "\tj\tlong_call_func\n" } } */
+/* { dg-final { scan-assembler-not "\tj\tfar_func\n" } } */
+/* { dg-final { scan-assembler     "\tj(|al)\tnear_func\n" } } */
+/* { dg-final { scan-assembler     "\tj(|al)\tnormal_func\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-1.c
new file mode 100644
index 000000000..fca525667
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-1.c
@@ -0,0 +1,13 @@
+/* Make sure that we use abs.fmt and neg.fmt when the signs of NaNs don't
+   matter.  */
+/* { dg-do compile } */
+/* { dg-options "-mhard-float -ffinite-math-only" } */
+/* { dg-final { scan-assembler "\tneg.s\t" } } */
+/* { dg-final { scan-assembler "\tneg.d\t" } } */
+/* { dg-final { scan-assembler "\tabs.s\t" } } */
+/* { dg-final { scan-assembler "\tabs.d\t" } } */
+
+NOMIPS16 float f1 (float f) { return -f; }
+NOMIPS16 float f2 (float f) { return __builtin_fabsf (f); }
+NOMIPS16 double d1 (double d) { return -d; }
+NOMIPS16 double d2 (double d) { return __builtin_fabs (d); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c
new file mode 100644
index 000000000..435751e0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/neg-abs-2.c
@@ -0,0 +1,13 @@
+/* Make sure that we avoid abs.fmt and neg.fmt when the signs of NaNs
+   matter.  */
+/* { dg-do compile } */
+/* { dg-options "-mhard-float -fno-finite-math-only" } */
+/* { dg-final { scan-assembler-not "\tneg.s\t" } } */
+/* { dg-final { scan-assembler-not "\tneg.d\t" } } */
+/* { dg-final { scan-assembler-not "\tabs.s\t" } } */
+/* { dg-final { scan-assembler-not "\tabs.d\t" } } */
+
+float f1 (float f) { return -f; }
+float f2 (float f) { return __builtin_fabsf (f); }
+double d1 (double d) { return -d; }
+double d2 (double d) { return __builtin_fabs (d); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-1.c
new file mode 100644
index 000000000..00be144d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-ffast-math isa=4 -mhard-float" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tnmadd.s\t" } } */
+/* { dg-final { scan-assembler "\tnmadd.d\t" } } */
+/* { dg-final { scan-assembler "\tnmsub.s\t" } } */
+/* { dg-final { scan-assembler "\tnmsub.d\t" } } */
+
+NOMIPS16 float
+sub1 (float f, float g, float h)
+{
+  return -((f * g) + h);
+}
+
+NOMIPS16 double
+sub2 (double f, double g, double h)
+{
+  return -((f * g) + h);
+}
+
+NOMIPS16 float
+sub3 (float f, float g, float h)
+{
+  return -((f * g) - h);
+}
+
+NOMIPS16 double
+sub4 (double f, double g, double h)
+{
+  return -((f * g) - h);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-2.c
new file mode 100644
index 000000000..a271f33b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-fno-fast-math -ffinite-math-only isa=4 -mhard-float" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tnmadd.s\t" } } */
+/* { dg-final { scan-assembler "\tnmadd.d\t" } } */
+/* { dg-final { scan-assembler "\tnmsub.s\t" } } */
+/* { dg-final { scan-assembler "\tnmsub.d\t" } } */
+
+NOMIPS16 float
+sub1 (float f, float g, float h)
+{
+  return -((f * g) + h);
+}
+
+NOMIPS16 double
+sub2 (double f, double g, double h)
+{
+  return -((f * g) + h);
+}
+
+NOMIPS16 float
+sub3 (float f, float g, float h)
+{
+  return -((f * g) - h);
+}
+
+NOMIPS16 double
+sub4 (double f, double g, double h)
+{
+  return -((f * g) - h);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-3.c
new file mode 100644
index 000000000..85de518a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nmadd-3.c
@@ -0,0 +1,30 @@
+/* The same code as nmadd-2.c, but compiled with -fno-finite-math-only.
+   We can't use nmadd and nmsub in that case.  */
+/* { dg-do compile } */
+/* { dg-options "-fno-fast-math -fno-finite-math-only isa=4 -mhard-float" } */
+/* { dg-final { scan-assembler-not "\tnmadd" } } */
+/* { dg-final { scan-assembler-not "\tnmsub" } } */
+
+float
+sub1 (float f, float g, float h)
+{
+  return -((f * g) + h);
+}
+
+double
+sub2 (double f, double g, double h)
+{
+  return -((f * g) + h);
+}
+
+float
+sub3 (float f, float g, float h)
+{
+  return -((f * g) - h);
+}
+
+double
+sub4 (double f, double g, double h)
+{
+  return -((f * g) - h);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/no-dsp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-dsp-1.c
new file mode 100644
index 000000000..c4a7b0aed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-dsp-1.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mno-dsp -ffat-lto-objects" } */
+
+void
+foo (void)
+{
+  register int x asm ("$ac1hi"); /* { dg-error "cannot be accessed" } */
+  asm volatile ("" : "=r" (x));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c
new file mode 100644
index 000000000..ecf856ea7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-lwxs.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-smartmips" } */
+
+NOMIPS16 int scaled_indexed_word_load (int a[], int b)
+{
+  return a[b];
+}
+/* { dg-final { scan-assembler-not "\tlwxs\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c
new file mode 100644
index 000000000..419d086b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/no-smartmips-ror-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-smartmips -march=mips32" } */
+
+NOMIPS16 int rotate_left (unsigned a, unsigned s)
+{
+  return (a << s) | (a >> (32 - s));
+}
+/* { dg-final { scan-assembler-not "\tror\t" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/nor.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/nor.c
new file mode 100644
index 000000000..e71791ba3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/nor.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tnor\t" 1 } } */
+/* { dg-final { scan-assembler-not "\tor" } } */
+
+/* Test that we generate a 'nor' instruction and no 'or' instructions.  */
+
+NOMIPS16 int f (int a, int b)
+{
+	return ~(a|b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c
new file mode 100644
index 000000000..e7150d297
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-baddu-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tbaddu\t" 4 } } */
+/* { dg-final { scan-assembler-not "\tandi\t" } } */
+
+NOMIPS16 unsigned char
+g (long long a, long long b)
+{
+  return a + b;
+}
+
+NOMIPS16 unsigned long long
+h (unsigned long long a, unsigned long long b)
+{
+  unsigned char c = a + b;
+  return c;
+}
+
+NOMIPS16 long long
+ff (long long a, long long b)
+{
+  unsigned char c = a + b;
+  return c;
+}
+
+NOMIPS16 int
+gg (int a, int b)
+{
+  return (a + b) & 0xff;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c
new file mode 100644
index 000000000..f91c68bcd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-1.c
@@ -0,0 +1,59 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tbbit1\t" } } */
+/* { dg-final { scan-assembler "\tbbit0\t" } } */
+/* { dg-final { scan-assembler-times "\tbbit.\t" 6 } } */
+/* { dg-final { scan-assembler-not "andi\t" } } */
+
+NOMIPS16 void foo (void);
+
+NOMIPS16 void
+f1 (long long i)
+{
+  if (i & 0x80)
+    foo ();
+}
+
+NOMIPS16 void
+f2 (int i)
+{
+  if (!(i & 0x80))
+    foo ();
+}
+
+NOMIPS16 void
+f3 (int i)
+{
+  if (i % 2)
+    foo ();
+}
+
+NOMIPS16 void
+f4 (int i)
+{
+  if (i & 1)
+    foo ();
+}
+
+NOMIPS16 void
+f5 (long long i)
+{
+  if ((i >> 3) & 1)
+    foo ();
+}
+
+unsigned long long r;
+
+NOMIPS16 static inline __attribute__((always_inline)) int
+test_bit(unsigned long long nr, const unsigned long long *addr)
+{
+  return 1UL & (addr[nr >> 6] >> (nr & 63ULL));
+}
+
+NOMIPS16 void
+f6 ()
+{
+  if (!test_bit(0, &r))
+    foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c
new file mode 100644
index 000000000..7e78d70e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mbranch-likely -fno-unroll-loops" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tbbit\[01\]\t" } } */
+/* { dg-final { scan-assembler-not "\tbbit\[01\]l\t" } } */
+/* { dg-final { scan-assembler "\tbnel\t" } } */
+
+NOMIPS16 int
+f (int *a, int *b)
+{
+  do
+    if (__builtin_expect (*a & 1, 1))
+      *a = 0;
+  while (++a < b);
+}
+
+NOMIPS16 int
+g (int *a, int *b)
+{
+  do
+    if (__builtin_expect (*a == 3, 1))
+      *a = 0;
+  while (++a < b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c
new file mode 100644
index 000000000..7b73f43a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-bbit-3.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+
+/* Force big-endian because for little-endian, combine generates this:
+
+ (if_then_else (ne (zero_extract:DI (subreg:DI (truncate:SI (reg:DI 196)) 0) 
+                 (const_int 1) 
+                 (const_int 0)) 
+             (const_int 0)) 
+         (label_ref 20) 
+         (pc))) 
+
+  which does not get recognized as a valid bbit pattern.  The
+  middle-end should be able to simplify this further.  */
+/* { dg-options "-march=octeon -meb" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* { dg-final { scan-assembler-times "\tbbit\[01\]\t|\tbgez\t|\tbltz\t" 2 } } */
+/* { dg-final { scan-assembler-not "ext\t" } } */
+
+void abort (void);
+void abort1 (void);
+void exit (int);
+
+typedef unsigned long long ulong64;
+
+typedef struct bitfield_s {
+  ulong64 a:1;
+  ulong64 b:29;
+  ulong64 c:1;
+  ulong64 d:15;
+  ulong64 f:18;
+} bitfield_t;
+
+bitfield_t bar;
+
+NOMIPS16 void
+f ()
+{
+  foo(&bar);
+  if (bar.a != 0x1)
+    abort ();
+  else if (!bar.c)
+    abort1 ();
+  else
+    exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-1.c
new file mode 100644
index 000000000..dd0b753ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-1.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* The tests also work with -mgp32.  For long long tests, only one of
+   the 32-bit parts is used.  */
+/* { dg-options "-march=octeon" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tcins\t" 3 } } */
+/* { dg-final { scan-assembler-not "\tandi\t|sll\t" } } */
+
+NOMIPS16 long long
+f (long long i)
+{
+  return (i & 0xff) << 34;
+}
+
+NOMIPS16 int
+g (int i)
+{
+  return (i << 4) & 0xff0;
+}
+
+NOMIPS16 long long
+h (long long i)
+{
+  return (i << 4) & 0xfff;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-2.c
new file mode 100644
index 000000000..71611bc9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-cins-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tcins\t" } } */
+
+NOMIPS16 unsigned
+f (unsigned i)
+{
+  return (i & 0xff) << 24;
+}
+
+NOMIPS16 unsigned long long
+g (unsigned long long i)
+{
+  return (i & 0x1ffffffffULL) << 4;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c
new file mode 100644
index 000000000..b8b8c1bc3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-final { scan-assembler "\tdmul\t" } } */
+/* { dg-final { scan-assembler-not "\tdmult\t" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+
+NOMIPS16 long long
+f (long long a, long long b)
+{
+  return a * b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c
new file mode 100644
index 000000000..cf8da24ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "using DMUL is no worse size-wise, and can be better if the constant is used elsewhere" { *-*-* } { "-Os" } { "" } } */
+/* { dg-final { scan-assembler-not "\tdmul" } } */
+
+NOMIPS16 long long
+f (long long a)
+{
+  return a * 7;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-3.c
new file mode 100644
index 000000000..38150a87e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-dmul-3.c
@@ -0,0 +1,20 @@
+/* Use DMUL for widening multiplication too.  */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tdmul\t" 2 } } */
+/* { dg-final { scan-assembler-not "\td?mult\t" } } */
+/* { dg-final { scan-assembler-times "\tdext\t" 2 } } */
+
+NOMIPS16 long long
+f (int i, int j)
+{
+  i++;
+  return (long long) i * j;
+}
+
+NOMIPS16 unsigned long long
+g (unsigned int i, unsigned int j)
+{
+  i++;
+  return (unsigned long long) i * j;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-1.c
new file mode 100644
index 000000000..b0f4be143
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon" } */
+/* { dg-final { scan-assembler "\texts\t" } } */
+
+struct foo
+{
+  long long a:3;
+  long long b:23;
+  long long c:38;
+};
+
+NOMIPS16 int
+f (struct foo s)
+{
+  return s.b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-2.c
new file mode 100644
index 000000000..21353d906
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -meb" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\texts\t" 4 } } */
+
+struct bar
+{
+  unsigned long long a:1;
+  long long b:14;
+  unsigned long long c:48;
+  long long d:1;
+};
+
+NOMIPS16 int
+f1 (struct bar *s, int a)
+{
+  return (int) s->b + a;
+}
+
+NOMIPS16 char
+f2 (struct bar *s)
+{
+  return s->d + 1;
+}
+
+NOMIPS16 int
+f3 ()
+{
+  struct bar s;
+  asm ("" : "=r"(s));
+  return (int) s.b + 1;
+}
+
+NOMIPS16 long long
+f4 (struct bar *s)
+{
+  return s->d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-3.c
new file mode 100644
index 000000000..be0419890
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\texts\t" 3 } } */
+
+struct foo
+{
+  unsigned long long a:10;
+  unsigned long long b:32;
+  unsigned long long c:22;
+};
+
+NOMIPS16 unsigned
+f (struct foo s)
+{
+  return s.b;
+}
+
+struct bar
+{
+  unsigned long long a:15;
+  unsigned long long b:48;
+  unsigned long long c:1;
+};
+
+NOMIPS16 int
+g (struct bar s)
+{
+  return (int) s.b;
+}
+
+NOMIPS16 int
+h (int i)
+{
+  return (i << 4) >> 24;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-4.c
new file mode 100644
index 000000000..0071ae173
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-4.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */
+/* { dg-final { scan-assembler-times "\texts\t" 6 } } */
+
+#define TEST(ID, TYPE, SHIFT)				\
+  int NOMIPS16						\
+  f##ID (long long y)					\
+  {							\
+    return (TYPE) ((TYPE) (y >> SHIFT) + 1);		\
+  }							\
+  int NOMIPS16						\
+  g##ID (unsigned long long y)				\
+  {							\
+    return (TYPE) ((TYPE) (y >> SHIFT) + 1);		\
+  }
+
+TEST (1, int, 10)
+TEST (2, short, 5)
+TEST (3, char, 31)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-5.c
new file mode 100644
index 000000000..0e587d7eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-5.c
@@ -0,0 +1,39 @@
+/* -mel version of octeon-exts-2.c.  */
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mel" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\texts\t" 4 } } */
+
+struct bar
+{
+  long long d:1;
+  unsigned long long c:48;
+  long long b:14;
+  unsigned long long a:1;
+};
+
+NOMIPS16 int
+f1 (struct bar *s, int a)
+{
+  return (int) s->b + a;
+}
+
+NOMIPS16 char
+f2 (struct bar *s)
+{
+  return s->d + 1;
+}
+
+NOMIPS16 int
+f3 ()
+{
+  struct bar s;
+  asm ("" : "=r"(s));
+  return (int) s.b + 1;
+}
+
+NOMIPS16 long long
+f4 (struct bar *s)
+{
+  return s->d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-6.c
new file mode 100644
index 000000000..b8da271ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-6.c
@@ -0,0 +1,23 @@
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\texts\t" 5 } } */
+/* { dg-final { scan-assembler-not "\t(dsll|dsra)\t" } } */
+/* { dg-final { scan-assembler-not "\tsll\t" } } */
+
+#define TEST_CHAR(T, N)				\
+  NOMIPS16 T					\
+  f##N (long long d, T *a, T *r)		\
+  {						\
+    T b = (signed char) d; *r = b + *a;		\
+  }
+#define TEST_SHORT(T, N)			\
+  NOMIPS16 T					\
+  g##N (long long d, T *a, T *r)		\
+  {						\
+    T b = (short) d; *r = b + *a;		\
+  }
+#define TEST(T, N) TEST_CHAR (T, N) TEST_SHORT (T, N)
+
+TEST (int, 1);
+TEST (long long, 2);
+TEST_CHAR (short, 3);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-7.c
new file mode 100644
index 000000000..fcae01261
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-exts-7.c
@@ -0,0 +1,19 @@
+/* Remove the redundant sign-extension after the sign-extraction.  */
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\texts\t" 1 } } */
+/* { dg-final { scan-assembler-not "\td?(sll|sra)" } } */
+
+struct bar
+{
+  long long a:18;
+  long long b:24;
+  long long c:22;
+};
+
+NOMIPS16 int
+f1 (struct bar *s)
+{
+  return s->b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c
new file mode 100644
index 000000000..4488e3d51
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pipe-1.c
@@ -0,0 +1,12 @@
+/* Check that we use the octeon pipeline description.  */
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -fschedule-insns2 -fdump-rtl-sched2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 int f (int a, int b)
+{
+  return a / b;
+}
+
+/* { dg-final { scan-rtl-dump "octeon_mult\\*71" "sched2" } }  */
+/* { dg-final { cleanup-rtl-dump "sched2" } }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-1.c
new file mode 100644
index 000000000..6a6791ce6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-final { scan-assembler "\tpop\t" } } */
+/* { dg-final { scan-assembler "\tdpop\t" } } */
+
+NOMIPS16 int
+f (long long a)
+{
+  return __builtin_popcountll (a);
+}
+
+NOMIPS16 int
+g (int a)
+{
+  return __builtin_popcount (a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-2.c
new file mode 100644
index 000000000..d6d2a7afb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-pop-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* The pop instruction does not depend on the word value to be sign extended. */
+/* { dg-final { scan-assembler-not "sll\t" } } */
+
+NOMIPS16 long long f(long long i)
+{
+  return __builtin_popcount (i);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-1.c
new file mode 100644
index 000000000..c07660a2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-1.c
@@ -0,0 +1,19 @@
+/* Check if we expand seq and sne.  */
+
+/* { dg-do compile } */
+/* { dg-options "-march=octeon" } */
+/* { dg-final { scan-assembler-times "\tseq\t|\tseqi\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tsne\t|\tsnei\t" 4 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 int f##N (int a, int b) { return LHS REL RHS; }
+
+TEST (0, a, ==, b);
+TEST (1, a, ==, 23);
+TEST (2, a, ==, 511);
+TEST (3, a, ==, -200);
+
+TEST (10, a, !=, b);
+TEST (11, a, !=, 1);
+TEST (12, a, !=, 350);
+TEST (13, a, !=, -512);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-2.c
new file mode 100644
index 000000000..83e068c54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-final { scan-assembler-times "\tseq\t|\tseqi\t" 3 } } */
+/* { dg-final { scan-assembler-times "\tsne\t|\tsnei\t" 3 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 long long f##N (long long a, long long b) { return LHS REL RHS; }
+
+TEST (0, a, ==, b);
+TEST (1, a, ==, 23);
+TEST (2, a, ==, 511);
+
+TEST (3, a, !=, b);
+TEST (4, a, !=, 1);
+TEST (5, a, !=, 350);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-3.c
new file mode 100644
index 000000000..71e09dc6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
+/* { dg-final { scan-assembler-times "\tseqi\t\|\tsnei\t" 4 } } */
+
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \
+  NOMIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \
+
+TEST (eq, a, ==, 10);
+TEST (ne, a, !=, 32);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-4.c
new file mode 100644
index 000000000..0fd83f0b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon-seq-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\txor" } } */
+
+unsigned
+m (unsigned e);
+
+NOMIPS16 void
+f (unsigned i)
+{
+  unsigned j = m (i);
+  h (j, i != j);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c
new file mode 100644
index 000000000..445e3fc2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon2 -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+#define TEST(N, R, T) \
+ T fll##N (T j, signed R *b, long long i) { return j + b[i]; } \
+ T gll##N (T j, unsigned R *b, long long i) { return j + b[i]; } \
+ T fi##N (T j, signed R *b, int i) { return j + b[i]; } \
+ T gi##N (T j, unsigned R *b, int i) { return j + b[i]; } \
+
+TEST (1, char, int)
+TEST (2, char, long long)
+/* { dg-final { scan-assembler-times "\tlbx\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tlbux\t" 4 } } */
+TEST (3, short, int)
+TEST (4, short, long long)
+/* { dg-final { scan-assembler-times "\tlhx\t" 4 } } */
+/* { dg-final { scan-assembler-times "\tlhux\t" 4 } } */
+TEST (5, int, long long)
+/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */
+/* { dg-final { scan-assembler-times "\tlwux\t" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c
new file mode 100644
index 000000000..b487637be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon2 -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+#define TEST(N, T) \
+  T f##N (T *p, int i) { return p[i]; } \
+  unsigned T g##N (unsigned T *p, int i) { return p[i]; }
+
+TEST (1, char)
+/* { dg-final { scan-assembler-times "\tlbu?x\t" 2 } } */
+TEST (2, short)
+/* { dg-final { scan-assembler-times "\tlhu?x\t" 2 } } */
+TEST (3, int)
+/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */
+TEST (4, long long)
+/* { dg-final { scan-assembler-times "\tldx\t" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c
new file mode 100644
index 000000000..110cf8bd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-lx-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=octeon2 -mgp32" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+#define TEST(N, T) \
+  T f##N (T *p, int i) { return p[i]; } \
+  unsigned T g##N (unsigned T *p, int i) { return p[i]; }
+
+TEST (1, char)
+/* { dg-final { scan-assembler-times "\tlbu?x\t" 2 } } */
+TEST (2, short)
+/* { dg-final { scan-assembler-times "\tlhu?x\t" 2 } } */
+TEST (3, int)
+/* { dg-final { scan-assembler-times "\tlwx\t" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c
new file mode 100644
index 000000000..18fd96671
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/octeon2-pipe-1.c
@@ -0,0 +1,12 @@
+/* Check that we use the octeon2 pipeline description.  */
+/* { dg-do compile } */
+/* { dg-options "-fschedule-insns2 -fdump-rtl-sched2 -march=octeon2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 int f (int a, int b)
+{
+  return a / b;
+}
+
+/* { dg-final { scan-rtl-dump "octeon_mult\\*17" "sched2" } }  */
+/* { dg-final { cleanup-rtl-dump "sched2" } }  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr26765.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr26765.c
new file mode 100644
index 000000000..c4716cff5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr26765.c
@@ -0,0 +1,13 @@
+/* PR target/pr26765
+   This testcase used to trigger an unrecognizable insn.  */
+
+/* { dg-do compile } */
+/* { dg-options "-w" } */
+
+__thread int *a = 0;
+
+NOMIPS16 void foo (void)
+{
+  extern int *b;
+  b = (int *) ((*a));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33256.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33256.c
new file mode 100644
index 000000000..109da4899
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33256.c
@@ -0,0 +1,11 @@
+/* GCC used to report an ICE for this test because we generated a LO_SUM
+   for an illegitimate constant.  */
+/* { dg-options "-mabi=64 -msym32 -EB -mno-abicalls" } */
+extern unsigned long a[];
+int b (int);
+
+int
+c (void)
+{
+  return b (a[0]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33635-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33635-1.c
new file mode 100644
index 000000000..f849b396e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33635-1.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mabi=64" } */
+
+NOMIPS16 long double __powitf2 (long double x, int m)
+{
+  long double y = x;
+  while (m >>= 1)
+    {
+      x = x * x;
+      if (m % 2)
+        y = y * x;
+    }
+  return y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33755.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33755.c
new file mode 100644
index 000000000..c3e2cbfd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr33755.c
@@ -0,0 +1,29 @@
+/* { dg-do link } */
+
+volatile int gv;
+const char *ptrs[2];
+
+void
+foo (volatile int *v, const char **ptrs)
+{
+  switch (*v & 1)
+    {
+    case 0:
+      ptrs[0] = 0;
+      break;
+    case 1:
+      break;
+    default:
+      ptrs[1] = "Some text";
+      break;
+    }
+  while (*v > 0)
+    *v -= 1;
+}
+
+int
+main (void)
+{
+  foo (&gv, ptrs);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr34831.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr34831.c
new file mode 100644
index 000000000..2da436f71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr34831.c
@@ -0,0 +1,7 @@
+/* { dg-options "-ffast-math -mips64 -mgp32" } */
+
+double
+foo (void)
+{
+  return __builtin_pow (0.0, -1.5);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr35802.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr35802.c
new file mode 100644
index 000000000..acdfaebe3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr35802.c
@@ -0,0 +1,17 @@
+/* { dg-options "-march=74kc -mgp32" } */
+__thread int x __attribute__((tls_model("initial-exec")));
+__thread int y __attribute__((tls_model("initial-exec")));
+
+int bar (void);
+
+NOMIPS16 void
+foo (int n)
+{
+  if (n > 5)
+    {
+      y = 0;
+      do
+	x += bar ();
+      while (n--);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c
new file mode 100644
index 000000000..848d879d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr37362.c
@@ -0,0 +1,20 @@
+/* mips*-sde-elf doesn't have 128-bit long doubles.  */
+/* { dg-do compile { target { ! { mips*-sde-elf mips*-mti-elf } } } } */
+/* { dg-options "-march=mips64r2 -mabi=n32" } */
+
+typedef float TFtype __attribute__((mode(TF)));
+
+TFtype
+__powitf (TFtype x, int m)
+{
+  unsigned int n = m < 0 ? -m : m;
+  TFtype y = n % 2 ? x : 1;
+  while (n >>= 1)
+    {
+      x = x * x;
+      if (n % 2)
+	y = y * x;
+    }
+  return m < 0 ? 1/y : y;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr45074.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr45074.c
new file mode 100644
index 000000000..129467fb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr45074.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mhard-float -mgp32" } */
+register double g __asm__("$f20");
+
+NOMIPS16 void
+test (double a)
+{
+  g = -a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr52125.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr52125.c
new file mode 100644
index 000000000..2ac806720
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr52125.c
@@ -0,0 +1,20 @@
+/* { dg-options "-mno-gpopt addressing=absolute" } */
+
+int a, b, c, d;
+
+NOMIPS16 void
+foo (void)
+{
+  asm ("%1 %z3"
+       : "=m" (a), "=m" (b)
+       : "m" (c), "m" (d));
+}
+
+/* { dg-final { scan-assembler-not "%hi\\(a\\)" } } */
+/* { dg-final { scan-assembler-not "%lo\\(a\\)" } } */
+/* { dg-final { scan-assembler "%hi\\(b\\)" } } */
+/* { dg-final { scan-assembler "%lo\\(b\\)" } } */
+/* { dg-final { scan-assembler-not "%hi\\(c\\)" } } */
+/* { dg-final { scan-assembler-not "%lo\\(c\\)" } } */
+/* { dg-final { scan-assembler "%hi\\(d\\)" } } */
+/* { dg-final { scan-assembler "%lo\\(d\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr54240.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr54240.c
new file mode 100644
index 000000000..cedb97a6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr54240.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-fdump-tree-phiopt-details -ffat-lto-objects isa>=4" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" "-O1" } { "" } } */
+
+typedef struct s {
+  int v;
+  int b;
+  struct s *l;
+  struct s *r;
+} S;
+
+/* Test requires conditional moves.  */
+NOMIPS16 int foo(S *s)
+{
+  S *this;
+  S *next;
+
+  this = s;
+  if (this->b)
+    next = this->l;
+  else
+    next = this->r;
+
+  return next->v;
+}
+
+/* { dg-final { scan-tree-dump "Hoisting adjacent loads" "phiopt1" } } */
+/* { dg-final { cleanup-tree-dump "phiopt1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr55315.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr55315.c
new file mode 100644
index 000000000..9dcf2893a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr55315.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+
+int data[4096];
+
+int
+f (void)
+{
+  return (((unsigned long) &data[0]) == 0xdeadbea0U);
+}
+
+/* { dg-final { scan-assembler-not "\tmove\t\\\$2,\\\$0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr56524.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr56524.c
new file mode 100644
index 000000000..7df021b69
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr56524.c
@@ -0,0 +1,8 @@
+/* { dg-options "-mips16" } */
+
+void bar (void) {}
+
+void __attribute__((optimize("schedule-insns")))
+foo (void)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59137.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59137.c
new file mode 100644
index 000000000..898650656
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59137.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-mno-plt" } */
+
+extern void abort (void);
+
+struct lispstruct
+{
+  int e;
+  int t;
+};
+
+struct lispstruct Cnil_body;
+struct lispstruct Ct_body;
+int nvalues;
+
+struct lispstruct * __attribute__ ((noinline))
+fLlistp (struct lispstruct *x0)
+{
+  if (x0 == &Cnil_body
+      || (((unsigned long) x0 >= 0x80000000) ? 0
+	  : (!x0->e ? (x0 != &Cnil_body) : x0->t)))
+    x0 = &Ct_body;
+  else
+    x0 = &Cnil_body;
+  nvalues = 1;
+  return x0;
+}
+
+int main ()
+{
+  if (fLlistp ((struct lispstruct *) 0xa0000001) != &Cnil_body)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59317.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59317.c
new file mode 100644
index 000000000..dd23f7c86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/pr59317.c
@@ -0,0 +1,83 @@
+/* { dg-do compile } */
+/* { dg-options "-mips16" } */
+extern void abort();
+
+int i_0, i_1, i_2, i_3, i_4, i_5, i_6, i_7, i_8, i_9;
+int j_0, j_1, j_2, j_3, j_4, j_5, j_6, j_7, j_8, j_9;
+
+int main()
+{
+  register int *x1 = &i_1; 
+  register int *x2 = &i_2; 
+  register int *x3 = &i_3; 
+  register int *x4 = &i_4; 
+  register int *x5 = &i_5; 
+  register int *x6 = &i_6;
+  register int *x7 = &i_7; 
+  register int *x8 = &i_8; 
+  register int *x9 = &i_9;
+  
+  register int *y0 = &j_0; 
+  register int *y1 = &j_1; 
+  register int *y2 = &i_2; 
+  register int *y3 = &j_3; 
+  register int *y4 = &j_4; 
+  register int *y5 = &j_5; 
+  register int *y6 = &j_6; 
+  register int *y7 = &j_7; 
+  register int *y8 = &j_8; 
+  register int *y9 = &j_9;
+
+  asm volatile ("" : "=r" (x2) : "0" (x2)); 
+  asm volatile ("" : "=r" (x3) : "0" (x3)); 
+  asm volatile ("" : "=r" (x4) : "0" (x4)); 
+  asm volatile ("" : "=r" (x5) : "0" (x5)); 
+  asm volatile ("" : "=r" (x6) : "0" (x6)); 
+  asm volatile ("" : "=r" (x7) : "0" (x7)); 
+  asm volatile ("" : "=r" (x8) : "0" (x8)); 
+  asm volatile ("" : "=r" (x9) : "0" (x9));
+
+  asm volatile ("" : "=r" (y0) : "0" (y0)); 
+  asm volatile ("" : "=r" (y1) : "0" (y1)); 
+  asm volatile ("" : "=r" (y2) : "0" (y2)); 
+  asm volatile ("" : "=r" (y3) : "0" (y3)); 
+  asm volatile ("" : "=r" (y4) : "0" (y4));
+  asm volatile ("" : "=r" (y5) : "0" (y5)); 
+  asm volatile ("" : "=r" (y6) : "0" (y6)); 
+  asm volatile ("" : "=r" (y7) : "0" (y7)); 
+  asm volatile ("" : "=r" (y8) : "0" (y8)); 
+  asm volatile ("" : "=r" (y9) : "0" (y9));
+
+  asm volatile ("" : "=r" (x1) : "0" (x1)); 
+  asm volatile ("" : "=r" (x2) : "0" (x2)); 
+  asm volatile ("" : "=r" (x3) : "0" (x3)); 
+  asm volatile ("" : "=r" (x4) : "0" (x4)); 
+  asm volatile ("" : "=r" (x5) : "0" (x5)); 
+  asm volatile ("" : "=r" (x6) : "0" (x6)); 
+  asm volatile ("" : "=r" (x7) : "0" (x7)); 
+  asm volatile ("" : "=r" (x8) : "0" (x8)); 
+  asm volatile ("" : "=r" (x9) : "0" (x9));
+
+  asm volatile ("" : "=r" (y0) : "0" (y0)); 
+  asm volatile ("" : "=r" (y1) : "0" (y1)); 
+  asm volatile ("" : "=r" (y2) : "0" (y2)); 
+  asm volatile ("" : "=r" (y3) : "0" (y3)); 
+  asm volatile ("" : "=r" (y4) : "0" (y4)); 
+  asm volatile ("" : "=r" (y5) : "0" (y5)); 
+  asm volatile ("" : "=r" (y6) : "0" (y6)); 
+  asm volatile ("" : "=r" (y7) : "0" (y7)); 
+  asm volatile ("" : "=r" (y8) : "0" (y8)); 
+  asm volatile ("" : "=r" (y9) : "0" (y9));
+
+  if (y0 != &j_0) abort (); 
+  if (y1 != &j_1) abort (); 
+  if (y2 != &j_2) abort (); 
+  if (y3 != &j_3) abort (); 
+  if (y4 != &j_4) abort (); 
+  if (y5 != &j_5) abort (); 
+  if (y6 != &j_6) abort (); 
+  if (y7 != &j_7) abort (); 
+  if (y8 != &j_8) abort (); 
+  if (y9 != &j_9) abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c
new file mode 100644
index 000000000..b5ffd0aeb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c
@@ -0,0 +1,45 @@
+/* { dg-options "-mabi=64 -mr10k-cache-barrier=store" } */
+
+/* Test that stores to uncached addresses do not get unnecessary
+   cache barriers.  */
+
+#define TEST(ADDR)					\
+  NOMIPS16 void						\
+  test_##ADDR (int n)					\
+  {							\
+    while (n--)						\
+      {							\
+	*(volatile char *) (0x##ADDR##UL) = 1;		\
+	*(volatile short *) (0x##ADDR##UL + 2) = 2;	\
+	*(volatile int *) (0x##ADDR##UL + 4) = 0;	\
+      }							\
+  }
+
+TEST (9000000000000000)
+TEST (900000fffffffff8)
+
+TEST (9200000000000000)
+TEST (920000fffffffff8)
+
+TEST (9400000000000000)
+TEST (940000fffffffff8)
+
+TEST (9600000000000000)
+TEST (960000fffffffff8)
+
+TEST (b800000000000000)
+TEST (b80000fffffffff8)
+
+TEST (ba00000000000000)
+TEST (ba0000fffffffff8)
+
+TEST (bc00000000000000)
+TEST (bc0000fffffffff8)
+
+TEST (be00000000000000)
+TEST (be0000fffffffff8)
+
+TEST (ffffffffa0000000)
+TEST (ffffffffbffffff8)
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c
new file mode 100644
index 000000000..ad0d2b049
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-10.c
@@ -0,0 +1,26 @@
+/* { dg-options "-mr10k-cache-barrier=store -mips4 -mbranch-likely -mno-abicalls" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+unsigned char *bar (int);
+
+/* Test that code after a branch-likely does not get an unnecessary
+   cache barrier.  */
+
+NOMIPS16 void
+foo (unsigned char *n)
+{
+  /* n starts in $4, but will be in $2 after the call to bar.
+     Encourage it to be in $2 on entry to the loop as well,
+     by doing some computation on it beforehand (D?ADDIU $2,$4,4).
+     dbr_schedule should then pull the *n load (L[WD] ...,0($2))
+     into the delay slot.  */
+  n += 4;
+  do
+    n = bar (*n + 1);
+  while (n);
+  /* The preceding branch should be a branch likely, with the shift as
+     its delay slot.  We therefore don't need a cache barrier here.  */
+  n[0] = 0;
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c
new file mode 100644
index 000000000..936c2589d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-11.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */
+
+/* Test that loads are not unnecessarily protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (int *ptr)
+{
+  *ptr = bar (*ptr);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c
new file mode 100644
index 000000000..34a12489c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-12.c
@@ -0,0 +1,13 @@
+/* { dg-options "-mr10k-cache-barrier=load-store -mno-abicalls" } */
+
+/* Test that loads are correctly protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (int *ptr)
+{
+  *ptr = bar (*ptr);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c
new file mode 100644
index 000000000..ee9c84b59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-13.c
@@ -0,0 +1,14 @@
+/* { dg-options "-mr10k-cache-barrier=store" } */
+
+/* Test that indirect calls are protected.  */
+
+int bar (int);
+
+NOMIPS16 void
+foo (void (*fn) (void), int x)
+{
+  if (x)
+    (*fn) ();
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c
new file mode 100644
index 000000000..92c37f497
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-14.c
@@ -0,0 +1,5 @@
+/* { dg-options "(-mips16) -mr10k-cache-barrier=store -ffat-lto-objects" } */
+
+/* Test that indirect calls are protected.  */
+
+MIPS16 void foo (void) { } /* { dg-message "sorry, unimplemented" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c
new file mode 100644
index 000000000..da655cda1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-15.c
@@ -0,0 +1,2 @@
+/* { dg-options "-mr10k-cache-barrier=store -mips2" } */
+/* { dg-error "requires.*cache.*instruction" "" { target *-*-* } 0 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c
new file mode 100644
index 000000000..ebf45f94f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-2.c
@@ -0,0 +1,40 @@
+/* { dg-options "-mabi=64 -mr10k-cache-barrier=store" } */
+
+/* Test that stores to constant cached addresses are protected
+   by cache barriers.  */
+
+#define TEST(ADDR)					\
+  NOMIPS16 void						\
+  test_##ADDR (int n)					\
+  {							\
+    *(volatile int *) (0x##ADDR##UL) = 1;		\
+  }
+
+TEST (8ffffffffffffffc)
+TEST (9000010000000000)
+
+TEST (91fffffffffffffc)
+TEST (9200010000000000)
+
+TEST (93fffffffffffffc)
+TEST (9500010000000000)
+
+TEST (95fffffffffffffc)
+TEST (9600010000000000)
+
+TEST (b7fffffffffffffc)
+TEST (b800010000000000)
+
+TEST (b9fffffffffffffc)
+TEST (ba00010000000000)
+
+TEST (bbfffffffffffffc)
+TEST (bc00010000000000)
+
+TEST (bdfffffffffffffc)
+TEST (be00010000000000)
+
+TEST (ffffffff9ffffffc)
+TEST (ffffffffc0000000)
+
+/* { dg-final { scan-assembler-times "\tcache\t" 18 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c
new file mode 100644
index 000000000..9e5678981
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-3.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */
+
+/* Test that in-range stores to the frame are not protected by
+   cache barriers.  */
+
+void bar (int *x);
+
+NOMIPS16 void
+foo (int v)
+{
+  int x[0x100000];
+  bar (x);
+  x[0x20] = v;
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c
new file mode 100644
index 000000000..7780460b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-4.c
@@ -0,0 +1,20 @@
+/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */
+
+void bar (int *x);
+
+/* Test that out-of-range stores to the frame are protected by cache
+   barriers.  */
+
+NOMIPS16 void
+foo (int v)
+{
+  int x[8];
+  bar (x);
+  if (v & 1)
+    x[0x100] = 0;
+  if (v & 2)
+    x[-0x100] = 0;
+  bar (x);
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c
new file mode 100644
index 000000000..757beefc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-5.c
@@ -0,0 +1,19 @@
+/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls -mabi=64" } */
+
+/* Test that in-range stores to static objects do not get an unnecessary
+   cache barrier.  */
+
+int x[4];
+void bar (void);
+
+NOMIPS16 void
+foo (int n)
+{
+  while (n--)
+    {
+      x[3] = 1;
+      bar ();
+    }
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c
new file mode 100644
index 000000000..32dd78cb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-6.c
@@ -0,0 +1,19 @@
+/* { dg-options "-mr10k-cache-barrier=store -mabi=64" } */
+
+int x[4];
+void bar (void);
+
+/* Test that out-of-range stores to static objects are protected by a
+   cache barrier.  */
+
+NOMIPS16 void
+foo (int n)
+{
+  while (n--)
+    {
+      x[4] = 1;
+      bar ();
+    }
+}
+
+/* { dg-final { scan-assembler "\tcache\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c
new file mode 100644
index 000000000..3a7a2538e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-7.c
@@ -0,0 +1,27 @@
+/* { dg-options "-mr10k-cache-barrier=store -mno-abicalls" } */
+
+void bar1 (void);
+void bar2 (void);
+void bar3 (void);
+
+NOMIPS16 void
+foo (int *x, int sel, int n)
+{
+  if (sel)
+    {
+      bar1 ();
+      x[0] = 1;
+    }
+  else
+    {
+      bar2 ();
+      x[1] = 0;
+    }
+  /* If there is one copy of this code, reached by two unconditional edges,
+     then it shouldn't need a third cache barrier.  */
+  x[2] = 2;
+  while (n--)
+    bar3 ();
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c
new file mode 100644
index 000000000..121b90723
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-8.c
@@ -0,0 +1,15 @@
+/* { dg-options "-mr10k-cache-barrier=store -G8" } */
+
+/* Test that in-range stores to components of static objects
+   do not get an unnecessary cache barrier.  */
+
+struct { struct { char i[4]; } a; struct { char j[4]; } b; } s;
+
+NOMIPS16 void
+foo (int sel)
+{
+  s.a.i[0] = 1;
+  s.b.j[3] = 100;
+}
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c
new file mode 100644
index 000000000..2f83968aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-9.c
@@ -0,0 +1,19 @@
+/* { dg-options "-mr10k-cache-barrier=store -G8" } */
+
+/* Test that out-of-range stores to components of static objects
+   are protected by a cache barrier.  */
+
+struct { struct { char i[4]; } a; struct { char j[4]; } b; } s;
+
+NOMIPS16 void
+foo (int sel1, int sel2, int sel3)
+{
+  if (sel1)
+    s.a.i[8] = 1;
+  if (sel2)
+    s.b.j[4] = 100;
+  if (sel3)
+    s.a.i[-1] = 0;
+}
+
+/* { dg-final { scan-assembler-times "\tcache\t" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r3900-mult.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r3900-mult.c
new file mode 100644
index 000000000..4dc2b003f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r3900-mult.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=r3900" } */
+/* { dg-final { scan-assembler "\tmult\t\[^\n\]*,\[^\n\]*," } } */
+
+NOMIPS16 int
+f (int a, int b)
+{
+  return a * b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/reg-var-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/reg-var-1.c
new file mode 100644
index 000000000..d8b811810
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/reg-var-1.c
@@ -0,0 +1,16 @@
+/* { dg-do run } */
+register int g asm ("$18");
+
+void __attribute__((noinline))
+test (void)
+{
+  g = g + 1;
+}
+
+int
+main (void)
+{
+  g = 2;
+  test ();
+  return g != 3;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-1.c
new file mode 100644
index 000000000..93fca39d6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-ffast-math isa=4 -mhard-float -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\trsqrt.d\t" } } */
+/* { dg-final { scan-assembler "\trsqrt.s\t" } } */
+
+extern double sqrt(double);
+extern float sqrtf(float);
+
+NOMIPS16 double foo(double x)
+{
+  return 1.0/sqrt(x);
+}
+
+NOMIPS16 float bar(float x)
+{
+  return 1.0f/sqrtf(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-2.c
new file mode 100644
index 000000000..c35ca0c6a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-ffast-math isa=4 -mhard-float -mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\trsqrt.d\t" } } */
+/* { dg-final { scan-assembler "\trsqrt.s\t" } } */
+
+extern double sqrt(double);
+extern float sqrtf(float);
+
+NOMIPS16 double foo(double x)
+{
+  return sqrt(1.0/x);
+}
+
+NOMIPS16 float bar(float x)
+{
+  return sqrtf(1.0f/x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-3.c
new file mode 100644
index 000000000..25178f2c8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-3.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "isa=4 -mhard-float" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\trsqrt.d\t" } } */
+/* { dg-final { scan-assembler-not "\trsqrt.s\t" } } */
+
+extern double sqrt(double);
+extern float sqrtf(float);
+
+double foo(double x)
+{
+  return 1.0/sqrt(x);
+}
+
+double bar(double x)
+{
+  return sqrt(1.0/x);
+}
+
+float foof(float x)
+{
+  return 1.0f/sqrtf(x);
+}
+
+float barf(float x)
+{
+  return sqrtf(1.0f/x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-4.c
new file mode 100644
index 000000000..6b6577e2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/rsqrt-4.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-ffast-math -mips64 -mhard-float -mgp32" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\trsqrt.d\t" } } */
+/* { dg-final { scan-assembler-times "\trsqrt.s\t" 2 } } */
+
+extern double sqrt(double);
+extern float sqrtf(float);
+
+NOMIPS16 double f1 (double x)
+{
+  return 1.0 / sqrt (x);
+}
+
+NOMIPS16 double f2 (double x)
+{
+  return sqrt (1.0 / x);
+}
+
+NOMIPS16 float f3 (float x)
+{
+  return 1.0f / sqrtf (x);
+}
+
+NOMIPS16 float f4 (float x)
+{
+  return sqrtf (1.0f / x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-1.c
new file mode 100644
index 000000000..b3ce1b18d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-1.c
@@ -0,0 +1,20 @@
+/* Check that we can use the save instruction to save varargs.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mabi=32" } */
+
+#include <stdarg.h>
+
+int bar (int, va_list ap);
+
+MIPS16 int
+foo (int n, ...)
+{
+  va_list ap;
+  int i;
+
+  va_start (ap, n);
+  i = bar (n, ap);
+  va_end (ap);
+  return i + 1;
+}
+/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$7" } } */
+/* { dg-final { scan-assembler "\trestore\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-2.c
new file mode 100644
index 000000000..899460fe7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-2.c
@@ -0,0 +1,16 @@
+/* Check that we can use the save instruction to save spilled arguments.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mabi=32" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+MIPS16 void
+foo (int *a, int b, int c)
+{
+  asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
+		"$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24",
+		"$25", "$30", "memory");
+  a[b] = 1;
+  a[c] = 1;
+}
+/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$6," } } */
+/* { dg-final { scan-assembler "\trestore\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-3.c
new file mode 100644
index 000000000..5d7aeb0ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-3.c
@@ -0,0 +1,20 @@
+/* Check that we can use the save instruction to save spilled arguments
+   when the argument save area is out of range of a direct load or store.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mabi=32" } */
+
+void bar (int *);
+
+MIPS16 void
+foo (int *a, int b, int c)
+{
+  int x[0x4000];
+  asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
+		"$18", "$19", "$20", "$21", "$22", "$23", "$24",
+		"$25", "$30", "memory");
+  bar (x);
+  a[b] = 1;
+  a[c] = 1;
+}
+/* { dg-final { scan-assembler "\tsave\t\\\$4-\\\$6," } } */
+/* { dg-final { scan-assembler "\trestore\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-4.c
new file mode 100644
index 000000000..25f3e6199
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-4.c
@@ -0,0 +1,14 @@
+/* Check that we can use the save instruction to save $16, $17 and $31.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mabi=32" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void bar (void);
+
+MIPS16 void
+foo (void)
+{
+  bar ();
+  asm volatile ("" ::: "$16", "$17");
+}
+/* { dg-final { scan-assembler "\tsave\t\[0-9\]*,\\\$16,\\\$17,\\\$31" } } */
+/* { dg-final { scan-assembler "\trestore\t\[0-9\]*,\\\$16,\\\$17,\\\$31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-5.c
new file mode 100644
index 000000000..b0dc1f057
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/save-restore-5.c
@@ -0,0 +1,15 @@
+/* Check that we don't try to save the same register twice.  */
+/* { dg-options "(-mips16) isa_rev>=1 -mgp32" } */
+
+int bar (int, int, int, int);
+void frob (void);
+
+MIPS16 void
+foo (int a1, int a2, int a3, int a4)
+{
+  asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
+		"$18", "$19", "$20", "$21", "$22", "$23", "$24",
+		"$25", "$30", "$31", "memory");
+  __builtin_eh_return (bar (a1, a2, a3, a4), frob);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sb1-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sb1-1.c
new file mode 100644
index 000000000..0c2ae066a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sb1-1.c
@@ -0,0 +1,30 @@
+/* Test SB-1 v2sf extensions.  */
+/* { dg-do compile } */ 
+/* { dg-options "-march=sb1 -mpaired-single -mgp64 -ffast-math" } */
+/* { dg-skip-if "rsqrt code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tdiv.ps\t" } } */
+/* { dg-final { scan-assembler "\trecip.ps\t" } } */
+/* { dg-final { scan-assembler "\tsqrt.ps\t" } } */
+/* { dg-final { scan-assembler "\trsqrt.ps\t" } } */
+
+typedef float v2sf __attribute__ ((vector_size (8)));
+
+NOMIPS16 v2sf divide (v2sf a, v2sf b)
+{
+  return a / b;
+}
+
+NOMIPS16 v2sf recip (v2sf a)
+{
+  return ((v2sf) {1.0, 1.0}) / a;
+}
+
+NOMIPS16 v2sf squareroot (v2sf a)
+{
+  return __builtin_mips_sqrt_ps (a);
+}
+
+NOMIPS16 v2sf rsqrt (v2sf a)
+{
+  return ((v2sf) {1.0, 1.0}) / __builtin_mips_sqrt_ps (a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-1.c
new file mode 100644
index 000000000..17599a837
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-1.c
@@ -0,0 +1,35 @@
+/* { dg-options "(-mips16) isa_rev>=1" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* { dg-final { scan-assembler-times {slt	\$2,\$5,\$4} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$2,\$5,\$4} 1 } } */
+/* { dg-final { scan-assembler-times {slt	\$5,\$4} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$5,\$4} 1 } } */
+
+/* { dg-final { scan-assembler-times {slt	\$2,\$0,\$4} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$2,\$0,\$4} 1 } } */
+
+/* { dg-final { scan-assembler-times {slt	\$2,\$4,\$5} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$2,\$4,\$5} 1 } } */
+/* { dg-final { scan-assembler-times {slt	\$4,\$5} 1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$4,\$5} 1 } } */
+
+/* { dg-final { scan-assembler-times {slt	\$2,\$4,23}  1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$2,\$4,23}  1 } } */
+/* { dg-final { scan-assembler-times {slt	\$4,23}  1 } } */
+/* { dg-final { scan-assembler-times {sltu	\$4,23}  1 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \
+  NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; } \
+  MIPS16 int s##N##_16 (int a, int b) { return LHS REL RHS; } \
+  MIPS16 int u##N##_16 (unsigned a, unsigned b) { return LHS REL RHS; }
+
+#define TEST_NO16(N, LHS, REL, RHS) \
+  NOMIPS16 int s##N (int a, int b) { return LHS REL RHS; } \
+  NOMIPS16 int u##N (unsigned a, unsigned b) { return LHS REL RHS; }
+
+TEST (1, a, >, b);
+TEST_NO16 (2, a, >=, 1);
+TEST (3, a, <, b);
+TEST (4, a, <=, 22);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-2.c
new file mode 100644
index 000000000..132da7bcf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
+/* { dg-final { scan-assembler-times "slt\t\|slti?u\t" 12 } } */
+
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \
+  NOMIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \
+
+TEST (eq, a, ==, 0);
+TEST (ne, a, !=, 0);
+TEST (gt, a, >, b);
+TEST (ge, a, >=, 1);
+TEST (lt, a, <, b);
+TEST (le, a, <=, 11);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-3.c
new file mode 100644
index 000000000..a07a85ada
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-3.c
@@ -0,0 +1,17 @@
+/* { dg-options "(-mips16) -mabi=o64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */
+/* { dg-final { scan-assembler-times "slt\t\|slti?u\t" 8 } } */
+
+
+#define TEST(N, LHS, REL, RHS) \
+  MIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \
+  MIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \
+
+TEST (eq, a, ==, 0);
+
+TEST (gt, a, >, b);
+
+TEST (lt, a, <, b);
+TEST (le, a, <=, 11);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-4.c
new file mode 100644
index 000000000..b8e289982
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/scc-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=o64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+/* { dg-final { scan-assembler "\tslt\t" } } */
+/* { dg-final { scan-assembler "\tsltu\t\|\txor\t\|\txori\t" } } */
+
+/* This test should work both in mips16 and non-mips16 mode.  */
+
+int
+f (long long a, long long b)
+{
+  return a > 5;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-1.c
new file mode 100644
index 000000000..646a44994
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-1.c
@@ -0,0 +1,61 @@
+/* { dg-options "-G4 -mexplicit-relocs" } */
+
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4c\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(c4\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4c\\)" } } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l8c\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e8b\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g8c\\)" } } */
+
+static volatile int l4a;
+static volatile int l4b = 1;
+static volatile int __attribute__((section(".sdata"))) l4c;
+extern int e4a;
+extern int __attribute__((section(".sdata"))) e4b;
+int __attribute__((common)) c4;
+int __attribute__((nocommon)) g4a;
+int g4b = 1;
+int __attribute__((section(".sdata"))) g4c = 2;
+
+static volatile int l8a[2];
+static volatile int l8b[2] = { 1, 2 };
+static volatile int __attribute__((section(".sdata"))) l8c[2];
+extern int e8a[2];
+extern int __attribute__((section(".sdata"))) e8b[2];
+int __attribute__((common)) c8[2];
+int __attribute__((nocommon)) g8a[2];
+int g8b[2] = { 1, 2 };
+int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
+
+int f32a (void) { return l4a; }
+int f32b (void) { return l4b; }
+int f32c (void) { return l4c; }
+int f32d (void) { return e4a; }
+int f32e (void) { return e4b; }
+int f32f (void) { return c4; }
+int f32g (void) { return g4a; }
+int f32h (void) { return g4b; }
+int f32i (void) { return g4c; }
+
+int f64a (void) { return l8a[0]; }
+int f64b (void) { return l8b[0]; }
+int f64c (void) { return l8c[0]; }
+int f64d (void) { return e8a[0]; }
+int f64e (void) { return e8b[0]; }
+int f64f (void) { return c8[0]; }
+int f64g (void) { return g8a[0]; }
+int f64h (void) { return g8b[0]; }
+int f64i (void) { return g8c[0]; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-2.c
new file mode 100644
index 000000000..fe55120f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-2.c
@@ -0,0 +1,61 @@
+/* { dg-options "-G4 -mexplicit-relocs -mno-local-sdata" } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l4a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4c\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(c4\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4c\\)" } } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l8c\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e8b\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g8c\\)" } } */
+
+static volatile int l4a;
+static volatile int l4b = 1;
+static volatile int __attribute__((section(".sdata"))) l4c;
+extern int e4a;
+extern int __attribute__((section(".sdata"))) e4b;
+int __attribute__((common)) c4;
+int __attribute__((nocommon)) g4a;
+int g4b = 1;
+int __attribute__((section(".sdata"))) g4c = 2;
+
+static volatile int l8a[2];
+static volatile int l8b[2] = { 1, 2 };
+static volatile int __attribute__((section(".sdata"))) l8c[2];
+extern int e8a[2];
+extern int __attribute__((section(".sdata"))) e8b[2];
+int __attribute__((common)) c8[2];
+int __attribute__((nocommon)) g8a[2];
+int g8b[2] = { 1, 2 };
+int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
+
+int f32a (void) { return l4a; }
+int f32b (void) { return l4b; }
+int f32c (void) { return l4c; }
+int f32d (void) { return e4a; }
+int f32e (void) { return e4b; }
+int f32f (void) { return c4; }
+int f32g (void) { return g4a; }
+int f32h (void) { return g4b; }
+int f32i (void) { return g4c; }
+
+int f64a (void) { return l8a[0]; }
+int f64b (void) { return l8b[0]; }
+int f64c (void) { return l8c[0]; }
+int f64d (void) { return e8a[0]; }
+int f64e (void) { return e8b[0]; }
+int f64f (void) { return c8[0]; }
+int f64g (void) { return g8a[0]; }
+int f64h (void) { return g8b[0]; }
+int f64i (void) { return g8c[0]; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-3.c
new file mode 100644
index 000000000..6705ee35a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-3.c
@@ -0,0 +1,61 @@
+/* { dg-options "-G4 -mexplicit-relocs -mno-extern-sdata" } */
+
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l4c\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(e4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e4b\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(c4\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g4c\\)" } } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(l8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(l8c\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(e8a\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(e8b\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(c8\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8a\\)" } } */
+/* { dg-final { scan-assembler-not "%gp_?rel\\(g8b\\)" } } */
+/* { dg-final { scan-assembler     "%gp_?rel\\(g8c\\)" } } */
+
+static volatile int l4a;
+static volatile int l4b = 1;
+static volatile int __attribute__((section(".sdata"))) l4c;
+extern int e4a;
+extern int __attribute__((section(".sdata"))) e4b;
+int __attribute__((common)) c4;
+int __attribute__((nocommon)) g4a;
+int g4b = 1;
+int __attribute__((section(".sdata"))) g4c = 2;
+
+static volatile int l8a[2];
+static volatile int l8b[2] = { 1, 2 };
+static volatile int __attribute__((section(".sdata"))) l8c[2];
+extern int e8a[2];
+extern int __attribute__((section(".sdata"))) e8b[2];
+int __attribute__((common)) c8[2];
+int __attribute__((nocommon)) g8a[2];
+int g8b[2] = { 1, 2 };
+int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
+
+int f32a (void) { return l4a; }
+int f32b (void) { return l4b; }
+int f32c (void) { return l4c; }
+int f32d (void) { return e4a; }
+int f32e (void) { return e4b; }
+int f32f (void) { return c4; }
+int f32g (void) { return g4a; }
+int f32h (void) { return g4b; }
+int f32i (void) { return g4c; }
+
+int f64a (void) { return l8a[0]; }
+int f64b (void) { return l8b[0]; }
+int f64c (void) { return l8c[0]; }
+int f64d (void) { return e8a[0]; }
+int f64e (void) { return e8b[0]; }
+int f64f (void) { return c8[0]; }
+int f64g (void) { return g8a[0]; }
+int f64h (void) { return g8b[0]; }
+int f64i (void) { return g8c[0]; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-4.c
new file mode 100644
index 000000000..82cfa61f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/sdata-4.c
@@ -0,0 +1,44 @@
+/* { dg-options "-G4 -mexplicit-relocs -mno-gpopt" } */
+
+/* { dg-final { scan-assembler-not "%gp_?rel" } } */
+/* { dg-final { scan-assembler-not "\\\$gp" } } */
+
+static volatile int l4a;
+static volatile int l4b = 1;
+static volatile int __attribute__((section(".sdata"))) l4c;
+extern int e4a;
+extern int __attribute__((section(".sdata"))) e4b;
+int __attribute__((common)) c4;
+int __attribute__((nocommon)) g4a;
+int g4b = 1;
+int __attribute__((section(".sdata"))) g4c = 2;
+
+static volatile int l8a[2];
+static volatile int l8b[2] = { 1, 2 };
+static volatile int __attribute__((section(".sdata"))) l8c[2];
+extern int e8a[2];
+extern int __attribute__((section(".sdata"))) e8b[2];
+int __attribute__((common)) c8[2];
+int __attribute__((nocommon)) g8a[2];
+int g8b[2] = { 1, 2 };
+int __attribute__((section(".sdata"))) g8c[2] = { 1, 2 };
+
+int f32a (void) { return l4a; }
+int f32b (void) { return l4b; }
+int f32c (void) { return l4c; }
+int f32d (void) { return e4a; }
+int f32e (void) { return e4b; }
+int f32f (void) { return c4; }
+int f32g (void) { return g4a; }
+int f32h (void) { return g4b; }
+int f32i (void) { return g4c; }
+
+int f64a (void) { return l8a[0]; }
+int f64b (void) { return l8b[0]; }
+int f64c (void) { return l8c[0]; }
+int f64d (void) { return e8a[0]; }
+int f64e (void) { return e8b[0]; }
+int f64f (void) { return c8[0]; }
+int f64g (void) { return g8a[0]; }
+int f64h (void) { return g8b[0]; }
+int f64i (void) { return g8c[0]; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/seq-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/seq-1.c
new file mode 100644
index 000000000..ae23608ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/seq-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-times "\tsltu\t|\tsltiu\t" 4 } } */
+
+#define TEST(N, LHS, REL, RHS) \
+  NOMIPS16 int f##N (int a, int b) { return LHS REL RHS; }
+
+TEST (0, a, ==, 0);
+TEST (1, a, ==, 600);
+TEST (10, a, !=, 0);
+TEST (11, a, !=, -800);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-1.c
new file mode 100644
index 000000000..0237272cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-1.c
@@ -0,0 +1,10 @@
+/* { dg-options "-mhard-float" } */
+/* { dg-skip-if "requiring \$4 is a code-quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 void
+foo (unsigned int x)
+{
+  __builtin_mips_set_fcsr (x);
+}
+
+/* { dg-final { scan-assembler "ctc1\t\\\$4,\\\$31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-2.c
new file mode 100644
index 000000000..82696298f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/set-fcsr-2.c
@@ -0,0 +1,10 @@
+/* { dg-options "-mhard-float (-mips16)" } */
+
+MIPS16 void
+foo (unsigned int x)
+{
+  __builtin_mips_set_fcsr (x);
+}
+
+/* { dg-final { scan-assembler "__mips16_set_fcsr" } } */
+/* { dg-final { scan-assembler "ctc1\t\\\$4,\\\$31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c
new file mode 100644
index 000000000..ce64b13a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-lwxs.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-msmartmips" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 int scaled_indexed_word_load (int a[], int b)
+{
+  return a[b];
+}
+/* { dg-final { scan-assembler "\tlwxs\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c
new file mode 100644
index 000000000..6300f8f03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-msmartmips" } */
+
+NOMIPS16 int rotate_left (unsigned a, unsigned s)
+{
+  return (a << s) | (a >> (32 - s));
+}
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c
new file mode 100644
index 000000000..2d7c5dcd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-msmartmips" } */
+
+NOMIPS16 int rotate_right (unsigned a, unsigned s)
+{
+  return (a >> s) | (a << (32 - s));
+}
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c
new file mode 100644
index 000000000..5e51aa3f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-msmartmips" } */
+
+#define S 13
+
+NOMIPS16 int rotate_left_constant (unsigned a)
+{
+  return (a << S) | (a >> (32 - S));
+}
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c
new file mode 100644
index 000000000..fc88a9a82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/smartmips-ror-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-msmartmips" } */
+
+#define S 13
+
+NOMIPS16 int rotate_right_constant (unsigned a)
+{
+  return (a >> S) | (a << (32 - S));
+}
+/* { dg-final { scan-assembler "\tror\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/soft-float-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/soft-float-1.c
new file mode 100644
index 000000000..855ff8ead
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/soft-float-1.c
@@ -0,0 +1,8 @@
+/* { dg-options "-msoft-float -ffat-lto-objects" } */
+
+void
+foo (void)
+{
+  register float x asm ("$f0"); /* { dg-error "cannot be accessed" } */
+  asm volatile ("" : "=r" (x));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/stack-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/stack-1.c
new file mode 100644
index 000000000..a28e4bf20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/stack-1.c
@@ -0,0 +1,11 @@
+/* { dg-final { scan-assembler "\td?addiu\t(\\\$sp,)?\\\$sp,\[1-9\]" } } */
+/* { dg-final { scan-assembler "\tlw\t" } } */
+/* { dg-final { scan-assembler-not "\td?addiu\t(\\\$sp,)?\\\$sp,\[1-9\].*\tlw\t" } } */
+
+/* Avoid use of SAVE and RESTORE.  */
+NOMIPS16 int foo (int y)
+{
+  volatile int a = y;
+  volatile int *volatile b = &a;
+  return *b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c
new file mode 100644
index 000000000..606fee0cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-1.c
@@ -0,0 +1,106 @@
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "we deliberately use calls when optimizing for size" { *-*-* } { "-Os" } { "" } } */
+typedef int int128_t __attribute__((mode(TI)));
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+
+#define UINT128_CONST(A, B) \
+  (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL))
+
+volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222);
+volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003);
+volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666);
+volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500);
+volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66);
+volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100);
+volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66);
+volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66);
+volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660);
+volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6);
+volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6);
+
+volatile int amount = 4;
+
+volatile uint128_t result;
+
+int
+test1 (void)
+{
+  result = a * b;
+  if (result != c)
+    return 1;
+  return 0;
+}
+
+int
+test2 (void)
+{
+  result = c + d;
+  if (result != e)
+    return 1;
+  return 0;
+}
+
+int
+test3 (void)
+{
+  result = e - d;
+  if (result != c)
+    return 1;
+  return 0;
+}
+
+int
+test4 (void)
+{
+  result = d & e;
+  if (result != f)
+    return 1;
+  return 0;
+}
+
+int
+test5 (void)
+{
+  result = d ^ e;
+  if (result != g)
+    return 1;
+  return 0;
+}
+
+int
+test6 (void)
+{
+  result = d | e;
+  if (result != h)
+    return 1;
+  return 0;
+}
+
+int
+test7 (void)
+{
+  result = g << amount;
+  if (result != i)
+    return 1;
+  return 0;
+}
+
+int
+test8 (void)
+{
+  result = g >> amount;
+  if (result != j)
+    return 1;
+  return 0;
+}
+
+int
+test9 (void)
+{
+  result = (int128_t) g >> amount;
+  if (result != k)
+    return 1;
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "\tjal" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-2.c
new file mode 100644
index 000000000..b6b8ea99b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/timode-2.c
@@ -0,0 +1,118 @@
+/* { dg-do run } */
+/* { dg-options "-mgp64" } */
+typedef int int128_t __attribute__((mode(TI)));
+typedef unsigned int uint128_t __attribute__((mode(TI)));
+
+#define UINT128_CONST(A, B) \
+  (((uint128_t) (0x ## A ## ULL) << 64) | (0x ## B ## ULL))
+
+volatile uint128_t a = UINT128_CONST (1111111111111111, a222222222222222);
+volatile uint128_t b = UINT128_CONST (0000000000000005, 0000000000000003);
+volatile uint128_t c = UINT128_CONST (5dddddddddddddde, e666666666666666);
+volatile uint128_t d = UINT128_CONST (e612340000000000, 5000000000234500);
+volatile uint128_t e = UINT128_CONST (43f011dddddddddf, 366666666689ab66);
+volatile uint128_t f = UINT128_CONST (4210100000000000, 1000000000010100);
+volatile uint128_t g = UINT128_CONST (a5e225dddddddddf, 6666666666aaee66);
+volatile uint128_t h = UINT128_CONST (e7f235dddddddddf, 7666666666abef66);
+volatile uint128_t i = UINT128_CONST (5e225dddddddddf6, 666666666aaee660);
+volatile uint128_t j = UINT128_CONST (0a5e225ddddddddd, f6666666666aaee6);
+volatile uint128_t k = UINT128_CONST (fa5e225ddddddddd, f6666666666aaee6);
+
+volatile int amount = 4;
+
+volatile uint128_t result;
+
+int
+test1 (void)
+{
+  result = a * b;
+  if (result != c)
+    return 1;
+  return 0;
+}
+
+int
+test2 (void)
+{
+  result = c + d;
+  if (result != e)
+    return 1;
+  return 0;
+}
+
+int
+test3 (void)
+{
+  result = e - d;
+  if (result != c)
+    return 1;
+  return 0;
+}
+
+int
+test4 (void)
+{
+  result = d & e;
+  if (result != f)
+    return 1;
+  return 0;
+}
+
+int
+test5 (void)
+{
+  result = d ^ e;
+  if (result != g)
+    return 1;
+  return 0;
+}
+
+int
+test6 (void)
+{
+  result = d | e;
+  if (result != h)
+    return 1;
+  return 0;
+}
+
+int
+test7 (void)
+{
+  result = g << amount;
+  if (result != i)
+    return 1;
+  return 0;
+}
+
+int
+test8 (void)
+{
+  result = g >> amount;
+  if (result != j)
+    return 1;
+  return 0;
+}
+
+int
+test9 (void)
+{
+  result = (int128_t) g >> amount;
+  if (result != k)
+    return 1;
+  return 0;
+}
+
+int
+main (void)
+{
+  return (test1 ()
+	  | test2 ()
+	  | test3 ()
+	  | test4 ()
+	  | test5 ()
+	  | test6 ()
+	  | test7 ()
+	  | test8 ()
+	  | test9 ());
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-1.c
new file mode 100644
index 000000000..d12ebd311
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-1.c
@@ -0,0 +1,21 @@
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+#define TEST(ID, TYPE, SHIFT)				\
+  int __attribute__((nomips16))				\
+  f##ID (unsigned long long y)				\
+  {							\
+    return (TYPE) ((TYPE) (y >> SHIFT) + 1);		\
+  }
+
+TEST (1, int, 32)
+TEST (2, short, 32)
+TEST (3, char, 32)
+TEST (4, int, 33)
+TEST (5, short, 33)
+TEST (6, char, 33)
+TEST (7, int, 61)
+TEST (8, short, 61)
+TEST (9, char, 61)
+
+/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-2.c
new file mode 100644
index 000000000..06ab58f5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-2.c
@@ -0,0 +1,21 @@
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+#define TEST(ID, TYPE, SHIFT)				\
+  int NOMIPS16						\
+  f##ID (long long y)					\
+  {							\
+    return (TYPE) ((TYPE) (y >> SHIFT) + 1);		\
+  }
+
+TEST (1, int, 32)
+TEST (2, short, 32)
+TEST (3, char, 32)
+TEST (4, int, 33)
+TEST (5, short, 33)
+TEST (6, char, 33)
+TEST (7, int, 61)
+TEST (8, short, 61)
+TEST (9, char, 61)
+
+/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-3.c
new file mode 100644
index 000000000..fcb69e4b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-3.c
@@ -0,0 +1,12 @@
+/* Remove redundant operations in truncate's operand.  */
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tandi?\t" } } */
+
+f (long long d)
+{
+  long long c = d & 0xffffffffff;
+  int i = (int) c;
+  g (i);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-4.c
new file mode 100644
index 000000000..cda90e00c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-4.c
@@ -0,0 +1,11 @@
+/* The and is performed in DI mode so there is no need for truncation.  */
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tsll\t" } } */
+
+NOMIPS16 unsigned long long
+f (unsigned long long s)
+{
+  unsigned u = s & 0xfff;
+  return u;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-5.c
new file mode 100644
index 000000000..f2a1875e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-5.c
@@ -0,0 +1,16 @@
+/* If we AND in DI mode (i.e. replace the order of TRUNCATE and AND) then we
+   can remove the TRUNCATE.  */
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */
+
+struct s
+{
+  unsigned a:5;
+};
+
+NOMIPS16 void
+f (struct s *s, unsigned long long a)
+{
+  s->a = a & 0x3;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-6.c
new file mode 100644
index 000000000..178d4baa4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-6.c
@@ -0,0 +1,13 @@
+/* setup_incoming_promotions should detect x to be already sign-extended due
+   to PROMOTE_MODE.  Thus the truncation should be removed by combine.  Based
+   on gcc.c-torture/execute/pr34070-2.c.  */
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tsll\t\[^\n\]*,0" } } */
+
+NOMIPS16 int f(unsigned int x, int n, int *p)
+{
+  if (p)
+    *p = 1;
+  return ((int)x) / (1 << n);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-8.c
new file mode 100644
index 000000000..f172b2223
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/truncate-8.c
@@ -0,0 +1,18 @@
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler "\tlw\t" } } */
+/* { dg-final { scan-assembler-not "\tsll\t" } } */
+/* { dg-final { scan-assembler-not "\tld\t" } } */
+
+struct s
+{
+  long long a;
+  int b;
+};
+
+int
+foo (struct s *x)
+{
+  return x->a;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-1.c
new file mode 100644
index 000000000..441abcaf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-1.c
@@ -0,0 +1,10 @@
+/* { dg-options "(-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+int MICROMIPS
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tmove\t\\\$2,\\\$0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-2.c
new file mode 100644
index 000000000..156476311
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-2.c
@@ -0,0 +1,10 @@
+/* { dg-options "(-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+int MICROMIPS
+foo (int *x)
+{
+  return x[5000];
+}
+
+/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tlw\t\\\$2,20000\\(\\\$4\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-3.c
new file mode 100644
index 000000000..8717362e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-3.c
@@ -0,0 +1,10 @@
+/* { dg-options "(-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (void)
+{
+  return;
+}
+
+/* { dg-final { scan-assembler "\tjrc\t\\\$31\n" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-4.c
new file mode 100644
index 000000000..0bd21f63b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-branch-4.c
@@ -0,0 +1,12 @@
+/* { dg-options "(-mmicromips) addressing=absolute" } */
+
+void foo (void);
+
+int MICROMIPS
+a (void)
+{
+  foo ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler "\tjals\tfoo\n\tnop" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-1.c
new file mode 100644
index 000000000..ddec815b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-1.c
@@ -0,0 +1,14 @@
+/* { dg-options "(-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+MICROMIPS void
+foo (int *x)
+{
+  asm volatile ("insn1\t%a0" :: "ZD" (&x[0]));
+  asm volatile ("insn2\t%a0" :: "ZD" (&x[511]));
+  asm volatile ("insn3\t%a0" :: "ZD" (&x[512]));
+}
+
+/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */
+/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */
+/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-2.c
new file mode 100644
index 000000000..0240d4670
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-constraints-2.c
@@ -0,0 +1,14 @@
+/* { dg-options "(-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+MICROMIPS void
+foo (int *x)
+{
+  asm volatile ("insn1\t%0" :: "ZC" (x[0]));
+  asm volatile ("insn2\t%0" :: "ZC" (x[511]));
+  asm volatile ("insn3\t%0" :: "ZC" (x[512]));
+}
+
+/* { dg-final { scan-assembler "\tinsn1\t0\\(" } } */
+/* { dg-final { scan-assembler "\tinsn2\t2044\\(" } } */
+/* { dg-final { scan-assembler-not "\tinsn3\t2048\\(" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c
new file mode 100644
index 000000000..0cdb1b7f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-1.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4)
+{
+  int r5 = r4[0];
+  int r6 = r4[1];
+  r4[2] = r5 * r5;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-2.c
new file mode 100644
index 000000000..ea3f39607
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-2.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4)
+{
+  int r5 = r4[0];
+  int r6 = r4[1];
+  r4[2] = r6 * r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tlwp\t\\\$5,0\\(\\\$4\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-3.c
new file mode 100644
index 000000000..2cb37510f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-3.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4)
+{
+  int r5 = r4[511];
+  int r6 = r4[512];
+  r4[2] = r5 * r5;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-4.c
new file mode 100644
index 000000000..b8a86b4ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-4.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4)
+{
+  int r5 = r4[511];
+  int r6 = r4[512];
+  r4[2] = r6 * r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tlwp\t\\\$5,2044\\(\\\$4\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-5.c
new file mode 100644
index 000000000..2315f21e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-5.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4)
+{
+  int r5 = r4[512];
+  int r6 = r4[513];
+  r4[2] = r5 * r5;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler-not "\tlwp" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c
new file mode 100644
index 000000000..9534974de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4)
+{
+  int r5 = r4[512];
+  int r6 = r4[513];
+  r4[2] = r6 * r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler-not "\tlwp" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-7.c
new file mode 100644
index 000000000..87ff6dc11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-7.c
@@ -0,0 +1,41 @@
+/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+f1 (int *r4, int dummy, int *other)
+{
+  int r5 = r4[1];
+  int newr4 = r4[0];
+  other[0] = r5 * r5;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r4asm asm ("$4") = newr4;
+    asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm));
+  }
+}
+
+void MICROMIPS
+f2 (int *r4, int dummy, int *other)
+{
+  int newr4 = r4[0];
+  int r5 = *(int *)(newr4 + 4);
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r4asm asm ("$4") = newr4;
+    asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm));
+  }
+}
+
+void MICROMIPS
+f3 (int dummy, int *r5, int *other)
+{
+  int newr5 = r5[1];
+  int r4 = *(int *)newr5;
+  {
+    register int r5asm asm ("$4") = r4;
+    register int r4asm asm ("$5") = newr5;
+    asm ("#foo" : "=m" (other[0]) : "d" (r4asm), "d" (r5asm));
+  }
+}
+
+/* { dg-final { scan-assembler-not "\tlwp" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-8.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-8.c
new file mode 100644
index 000000000..43b98423d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-8.c
@@ -0,0 +1,17 @@
+/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+f1 (int dummy, int *r5, int *other)
+{
+  int r4 = r5[0];
+  int newr5 = r5[1];
+  other[0] = r4 * r4;
+  {
+    register int r5asm asm ("$4") = r4;
+    register int r4asm asm ("$5") = newr5;
+    asm ("#foo" : "=m" (other[1]) : "d" (r4asm), "d" (r5asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tlwp\t\\\$4,0\\(\\\$5\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c
new file mode 100644
index 000000000..da2cbaff3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-swp-volatile.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-mmicromips" } */
+
+/* This test ensures that we do not generate microMIPS SWP or LWP
+   instructions when any component of the accessed memory is volatile;
+   they are unsafe for such since they might cause replay of partial
+   accesses if interrupted by an exception.  */
+
+static void set_csr (volatile void *p, int v)
+{
+  *(volatile int *) (p) = v;
+}
+
+static int get_csr (volatile void *p)
+{
+  return *(volatile int *) (p);
+}
+
+int main ()
+{
+  int i, q = 0, p = 0, r = 0;
+
+  for (i = 0; i < 20; i++)
+    {
+      set_csr ((volatile void *) 0xbf0100a8, 0xffff0002);
+      set_csr ((volatile void *) 0xbf0100a4, 0x80000008);
+    }
+
+  for (i = 0; i < 20; i++)
+    {
+      register int k, j;
+      k = get_csr ((volatile void *) 0xbf0100b8);
+      p += k;
+      j = get_csr ((volatile void *) 0xbf0100b4);
+      r += j;
+      q = j + k;
+    }
+  return q + r + p;
+}
+
+/* { dg-final { scan-assembler-not "\tswp" } } */
+/* { dg-final { scan-assembler-not "\tlwp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-1.c
new file mode 100644
index 000000000..0865b78bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-1.c
@@ -0,0 +1,16 @@
+/* Check that we can generate the MOVEP instruction.  */
+/* { dg-options "-mgp32 -fpeephole2 (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+long long bar (long long, long long);
+
+MICROMIPS long long
+foo (long long n, long long a)
+{
+  long long i, j;
+
+  i = bar (n, a);
+  j = bar (n, a);
+  return i + j;
+}
+/* { dg-final { scan-assembler "\tmovep\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-2.c
new file mode 100644
index 000000000..5a3a8419e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-movep-2.c
@@ -0,0 +1,13 @@
+/* Check that we can generate the MOVEP instruction.  */
+/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+int bar (int, int);
+
+int MICROMIPS
+foo (int n, int a)
+{
+  return bar (0, 0);
+}
+
+/* { dg-final { scan-assembler "\tmovep\t\\\$4,\\\$5,\\\$0,\\\$0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c
new file mode 100644
index 000000000..ff1ea4b33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-1.c
@@ -0,0 +1,18 @@
+/* Check that we can use the swm/lwm instructions.  */
+/* { dg-options "-mabi=32 (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+int bar (int, int, int, int, int);
+
+MICROMIPS int
+foo (int n, int a, int b, int c, int d)
+{
+  int i, j;
+
+  i = bar (n, a, b, c, d);
+  j = bar (n, a, b, c, d);
+  return i + j;
+}
+
+/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$2(0|1),\\\$31" } } */
+/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$2(0|1),\\\$31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c
new file mode 100644
index 000000000..cb421d5d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-2.c
@@ -0,0 +1,16 @@
+/* Check that we can use the save instruction to save spilled arguments.  */
+/* { dg-options "-mabi=32 (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+MICROMIPS void
+foo (int *a, int b, int c)
+{
+  asm volatile ("" ::: "$2", "$3", "$4", "$5", "$6", "$7", "$8",
+		"$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16",
+		"$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24",
+		"$25", "$30", "memory");
+  a[b] = 1;
+  a[c] = 1;
+}
+/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$23,\\\$fp" } } */
+/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$23,\\\$fp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c
new file mode 100644
index 000000000..22c6f45f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-save-restore-3.c
@@ -0,0 +1,14 @@
+/* Check that we can use the swm instruction to save $16, $17 and $31.  */
+/* { dg-options "-mgp32 (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void bar (void);
+
+MICROMIPS void
+foo (void)
+{
+  bar ();
+  asm volatile ("" ::: "$16", "$17");
+}
+/* { dg-final { scan-assembler "\tswm\t\\\$16-\\\$17,\\\$31" } } */
+/* { dg-final { scan-assembler "\tlwm\t\\\$16-\\\$17,\\\$31" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-1.c
new file mode 100644
index 000000000..5e337b27b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-1.c
@@ -0,0 +1,10 @@
+/* { dg-options "-fpeephole2 -mgp32 (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (long long l1, long long *l2)
+{
+  *l2 = l1;
+}
+
+/* { dg-final { scan-assembler "\tswp\t\\\$4,0\\(\\\$6\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-2.c
new file mode 100644
index 000000000..042322c21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-2.c
@@ -0,0 +1,17 @@
+/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4, int r5, int r6)
+{
+  r6 *= r6;
+  r4[0] = r5;
+  r4[1] = r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-3.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-3.c
new file mode 100644
index 000000000..f0e54647d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-3.c
@@ -0,0 +1,17 @@
+/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4, int r5, int r6)
+{
+  r5 *= r5;
+  r4[0] = r5;
+  r4[1] = r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tswp\t\\\$5,0\\(\\\$4\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-4.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-4.c
new file mode 100644
index 000000000..5e8f5ea2a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-4.c
@@ -0,0 +1,17 @@
+/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4, int r5, int r6)
+{
+  r6 *= r6;
+  r4[511] = r5;
+  r4[512] = r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-5.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-5.c
new file mode 100644
index 000000000..dc1938e47
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-5.c
@@ -0,0 +1,17 @@
+/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4, int r5, int r6)
+{
+  r5 *= r5;
+  r4[511] = r5;
+  r4[512] = r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler "\tswp\t\\\$5,2044\\(\\\$4\\)" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-6.c
new file mode 100644
index 000000000..b489006ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-6.c
@@ -0,0 +1,17 @@
+/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4, int r5, int r6)
+{
+  r6 *= r6;
+  r4[512] = r5;
+  r4[513] = r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler-not "\tswp" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-7.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-7.c
new file mode 100644
index 000000000..6dde49b8a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-swp-7.c
@@ -0,0 +1,17 @@
+/* { dg-options "-fpeephole2 -mtune=m14k (-mmicromips)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+void MICROMIPS
+foo (int *r4, int r5, int r6)
+{
+  r5 *= r5;
+  r4[512] = r5;
+  r4[513] = r6;
+  {
+    register int r5asm asm ("$5") = r5;
+    register int r6asm asm ("$6") = r6;
+    asm ("#foo" : "=m" (r4[2]) : "d" (r5asm), "d" (r6asm));
+  }
+}
+
+/* { dg-final { scan-assembler-not "\tswp" } }*/
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c
new file mode 100644
index 000000000..938f52d21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/unaligned-1.c
@@ -0,0 +1,45 @@
+/* { dg-options "-mgp64" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-times "\tsdl\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tsdr\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tldl\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tldr\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tswl\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tswr\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tlwl\t" 1 } } */
+/* { dg-final { scan-assembler-times "\tlwr\t" 1 } } */
+/* { dg-final { scan-assembler-not "\tnop" } } */
+
+/* Test to make sure we produce the unaligned load/store for
+   both 64bit and 32bits sized accesses.  */
+
+struct s
+{
+  char c;
+  int i;
+  long long l;
+} __attribute__ ((packed)) s __attribute__((aligned(1) ));
+
+NOMIPS16 void
+sd (long long l)
+{
+  s.l = l;
+}
+
+NOMIPS16 long long
+ld ()
+{
+  return s.l;
+}
+
+NOMIPS16 void
+sw (int i)
+{
+  s.i = i;
+}
+
+NOMIPS16 int
+lw ()
+{
+  return s.i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/va-arg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/va-arg-1.c
new file mode 100644
index 000000000..87c95f525
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/va-arg-1.c
@@ -0,0 +1,48 @@
+/* See PR 52154 for the xfail.  */
+/* { dg-do run { xfail { mips_eabi && { hard_float && ilp32 } } } } */
+
+#include <stdarg.h>
+
+extern void abort (void);
+
+struct __attribute__((aligned(16))) empty {};
+
+static void __attribute__((noinline))
+check_args (int count, ...)
+{
+  va_list va;
+  int i;
+
+  va_start (va, count);
+  for (i = 0; i < count; i++)
+    if (va_arg (va, int) != 1000 + i)
+      abort ();
+
+  va_arg (va, struct empty);
+  if (va_arg (va, int) != 2000 + count)
+    abort ();
+
+  va_end (va);
+}
+
+int
+main (void)
+{
+  struct empty e;
+
+  check_args (1, 1000, e, 2001);
+  check_args (2, 1000, 1001, e, 2002);
+  check_args (3, 1000, 1001, 1002, e, 2003);
+  check_args (4, 1000, 1001, 1002, 1003, e, 2004);
+  check_args (5, 1000, 1001, 1002, 1003, 1004, e, 2005);
+  check_args (6, 1000, 1001, 1002, 1003, 1004, 1005, e, 2006);
+  check_args (7, 1000, 1001, 1002, 1003, 1004, 1005, 1006, e, 2007);
+  check_args (8, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, e, 2008);
+  check_args (9, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+	      1008, e, 2009);
+  check_args (10, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+	      1008, 1009, e, 2010);
+  check_args (11, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+	      1008, 1009, 1010, e, 2011);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-1.c
new file mode 100644
index 000000000..db9ae3430
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-1.c
@@ -0,0 +1,8 @@
+/* Make sure that mul/addu is preferred over mtlo/macc and that mul/subu
+   is preferred over mtlo/msac.  */
+/* { dg-do compile } */
+/* { dg-options "-march=vr5400 -fpeephole2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; }
+NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; }
+/* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-2.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-2.c
new file mode 100644
index 000000000..58bdc0893
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/vr-mult-2.c
@@ -0,0 +1,8 @@
+/* Make sure that mul/addu is preferred over mtlo/macc and that mul/subu
+   is preferred over mtlo/msac.  */
+/* { dg-do compile } */
+/* { dg-options "-march=vr5500 -fpeephole2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+NOMIPS16 int f1 (int a, int b, int c) { return a + b * c; }
+NOMIPS16 int f2 (int a, int b, int c) { return a - b * c; }
+/* { dg-final { scan-assembler "\tmul\t.*\tmul\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nds32/basic-main.c b/gcc-4.9/gcc/testsuite/gcc.target/nds32/basic-main.c
new file mode 100644
index 000000000..6fdbc357f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nds32/basic-main.c
@@ -0,0 +1,9 @@
+/* This is a basic main function test program.  */
+
+/* { dg-do run }  */
+/* { dg-options "-O0" }  */
+
+int main(void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-isb.c b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-isb.c
new file mode 100644
index 000000000..e65061bae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-isb.c
@@ -0,0 +1,11 @@
+/* Verify that we generate isb instruction with builtin function.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O0" }  */
+/* { dg-final { scan-assembler "\\tisb" } }  */
+
+void
+test (void)
+{
+  __builtin_nds32_isb ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-isync.c b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-isync.c
new file mode 100644
index 000000000..3160e4ad3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-isync.c
@@ -0,0 +1,12 @@
+/* Verify that we generate isync instruction with builtin function.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O0" }  */
+/* { dg-final { scan-assembler "\\tisync" } }  */
+
+void
+test (void)
+{
+  int *addr = (int *) 0x53000000;
+  __builtin_nds32_isync (addr);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c
new file mode 100644
index 000000000..db4c55845
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-mfsr-mtsr.c
@@ -0,0 +1,17 @@
+/* Verify that we generate mfsr/mtsr instruction with builtin function.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O0" }  */
+/* { dg-final { scan-assembler "\\tmfsr" } }  */
+/* { dg-final { scan-assembler "\\tmtsr" } }  */
+
+#include <nds32_intrinsic.h>
+
+void
+test (void)
+{
+  int ipsw_value;
+
+  ipsw_value = __builtin_nds32_mfsr (__NDS32_REG_IPSW__);
+  __builtin_nds32_mtsr (ipsw_value, __NDS32_REG_IPSW__);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c
new file mode 100644
index 000000000..3cfaab951
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-mfusr-mtusr.c
@@ -0,0 +1,17 @@
+/* Verify that we generate mfusr/mtusr instruction with builtin function.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O0" }  */
+/* { dg-final { scan-assembler "\\tmfusr" } }  */
+/* { dg-final { scan-assembler "\\tmtusr" } }  */
+
+#include <nds32_intrinsic.h>
+
+void
+test (void)
+{
+  int itype_value;
+
+  itype_value = __builtin_nds32_mfusr (__NDS32_REG_ITYPE__);
+  __builtin_nds32_mtusr (itype_value, __NDS32_REG_ITYPE__);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c
new file mode 100644
index 000000000..2dceed98a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-setgie-dis.c
@@ -0,0 +1,11 @@
+/* Verify that we generate setgie.d instruction with builtin function.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O0" }  */
+/* { dg-final { scan-assembler "\\tsetgie.d" } }  */
+
+void
+test (void)
+{
+  __builtin_nds32_setgie_dis ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c
new file mode 100644
index 000000000..892887019
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nds32/builtin-setgie-en.c
@@ -0,0 +1,11 @@
+/* Verify that we generate setgie.e instruction with builtin function.  */
+
+/* { dg-do compile }  */
+/* { dg-options "-O0" }  */
+/* { dg-final { scan-assembler "\\tsetgie.e" } }  */
+
+void
+test (void)
+{
+  __builtin_nds32_setgie_en ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nds32/nds32.exp b/gcc-4.9/gcc/testsuite/gcc.target/nds32/nds32.exp
new file mode 100644
index 000000000..14665653a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nds32/nds32.exp
@@ -0,0 +1,45 @@
+# Target test cases of Andes NDS32 cpu for GNU compiler
+# Copyright (C) 2012-2014 Free Software Foundation, Inc.
+# Contributed by Andes Technology Corporation.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published
+# by the Free Software Foundation; either version 3, or (at your
+# option) any later version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a nds32 target.
+if ![istarget nds32*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/biggot-1.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/biggot-1.c
new file mode 100644
index 000000000..49b14ed0c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/biggot-1.c
@@ -0,0 +1,67 @@
+/* Check that the GOT pointer is being initialized correctly to allow
+   access to the full 64K maximum GOT size for -fpic, rather than only 32K
+   (which would happen if the GOT pointer points to the base of the GOT,
+   as the GOT16 and CALL16 relocations are signed).  */
+
+/* { dg-options "-fpic" } */
+/* { dg-do run { target nios2-*-linux-gnu } } */
+
+extern void abort (void);
+
+static int n = 0;
+
+void
+doit (int m)
+{
+  if (m != n)
+    abort ();
+  n++;
+}
+
+#define X(N) \
+  void f_##N (void) { doit (0x##N); }
+
+#define F(N) f_##N ();
+
+#define A(N) \
+  X(N##0) X(N##1) X(N##2) X(N##3) X(N##4) X(N##5) X(N##6) X(N##7) \
+  X(N##8) X(N##9) X(N##a) X(N##b) X(N##c) X(N##d) X(N##e) X(N##f) \
+  void f_##N (void) { \
+    F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
+    F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
+    }
+
+#define B(N) \
+  A(N##0) A(N##1) A(N##2) A(N##3) A(N##4) A(N##5) A(N##6) A(N##7) \
+  A(N##8) A(N##9) A(N##a) A(N##b) A(N##c) A(N##d) A(N##e) A(N##f) \
+  void f_##N (void) { \
+    F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
+    F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
+    }
+
+#define C(N) \
+  B(N##0) B(N##1) B(N##2) B(N##3) B(N##4) B(N##5) B(N##6) B(N##7) \
+  B(N##8) B(N##9) B(N##a) B(N##b) B(N##c) B(N##d) B(N##e) B(N##f) \
+  void f_##N (void) { \
+    F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
+    F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
+    }
+
+#define D(N) \
+  C(N##0) C(N##1) C(N##2) \
+  void f_##N (void) { \
+    F(N##0) F(N##1) F(N##2) \
+    }
+
+/* This defines 16x16x16x3 leaf functions, requiring something over
+   48K of GOT space overall.  */
+D(0)
+
+int
+main (void)
+{
+  f_0 ();
+  if (n != 16*16*16*3)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/biggot-2.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/biggot-2.c
new file mode 100644
index 000000000..7a34d3f6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/biggot-2.c
@@ -0,0 +1,68 @@
+/* Check that a program that requires large-GOT support builds and
+   executes without error.  This program defines a very large number
+   of leaf functions; compiled with -fPIC, they all require GOT
+   entries, which will overflow the range addressible by 16-bit -fpic
+   offsets by about a factor of 2.  */
+
+/* { dg-options "-fPIC" } */
+/* { dg-do run { target nios2-*-linux-gnu } } */
+
+extern void abort (void);
+
+static int n = 0;
+
+void
+doit (int m)
+{
+  if (m != n)
+    abort ();
+  n++;
+}
+
+#define X(N) \
+  void f_##N (void) { doit (0x##N); }
+
+#define F(N) f_##N ();
+
+#define A(N) \
+  X(N##0) X(N##1) X(N##2) X(N##3) X(N##4) X(N##5) X(N##6) X(N##7) \
+  X(N##8) X(N##9) X(N##a) X(N##b) X(N##c) X(N##d) X(N##e) X(N##f) \
+  void f_##N (void) { \
+    F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
+    F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
+    }
+
+#define B(N) \
+  A(N##0) A(N##1) A(N##2) A(N##3) A(N##4) A(N##5) A(N##6) A(N##7) \
+  A(N##8) A(N##9) A(N##a) A(N##b) A(N##c) A(N##d) A(N##e) A(N##f) \
+  void f_##N (void) { \
+    F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
+    F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
+    }
+
+#define C(N) \
+  B(N##0) B(N##1) B(N##2) B(N##3) B(N##4) B(N##5) B(N##6) B(N##7) \
+  B(N##8) B(N##9) B(N##a) B(N##b) B(N##c) B(N##d) B(N##e) B(N##f) \
+  void f_##N (void) { \
+    F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
+    F(N##8) F(N##9) F(N##a) F(N##b) F(N##c) F(N##d) F(N##e) F(N##f) \
+    }
+
+#define D(N) \
+  C(N##0) C(N##1) C(N##2) C(N##3) C(N##4) C(N##5) C(N##6) C(N##7) \
+  void f_##N (void) { \
+    F(N##0) F(N##1) F(N##2) F(N##3) F(N##4) F(N##5) F(N##6) F(N##7) \
+    }
+
+/* This defines 16x16x16x8 leaf functions, requiring something over
+   128K of GOT space overall.  */
+D(0)
+
+int
+main (void)
+{
+  f_0 ();
+  if (n != 16*16*16*8)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-1.c
new file mode 100644
index 000000000..c9afa6829
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-1.c
@@ -0,0 +1,22 @@
+/* Test specification of custom instructions via command-line options.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only -mcustom-fmaxs=246 -mcustom-fmins=247 -mcustom-fsqrts=251" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+void
+custom_fp (float operand_a, float operand_b, float *result)
+{
+  result[0] = fmaxf (operand_a, operand_b);
+  result[1] = fminf (operand_a, operand_b);
+  result[2] = sqrtf (operand_a);
+}
+
+/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
+/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
+/* { dg-final { scan-assembler "custom\\t251, .* # fsqrts .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-2.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-2.c
new file mode 100644
index 000000000..fc7c64370
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-2.c
@@ -0,0 +1,26 @@
+/* Test specification of custom instructions via pragmas.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+#pragma GCC target ("custom-fmaxs=246")
+#pragma GCC target ("custom-fmins=247")
+#pragma GCC target ("custom-fsqrts=251")
+
+void
+custom_fp (float operand_a, float operand_b, float *result)
+{
+  result[0] = fmaxf (operand_a, operand_b);
+  result[1] = fminf (operand_a, operand_b);
+  result[2] = sqrtf (operand_a);
+}
+
+/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
+/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
+/* { dg-final { scan-assembler "custom\\t251, .* # fsqrts .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-3.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-3.c
new file mode 100644
index 000000000..703bc9fa5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-3.c
@@ -0,0 +1,26 @@
+/* Test specification of custom instructions via function attributes.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+extern void
+custom_fp (float operand_a, float operand_b, float *result)
+  __attribute__ ((target ("custom-fmaxs=246,custom-fmins=247,custom-fsqrts=251")));
+
+void
+custom_fp (float operand_a, float operand_b, float *result)
+{
+  result[0] = fmaxf (operand_a, operand_b);
+  result[1] = fminf (operand_a, operand_b);
+  result[2] = sqrtf (operand_a);
+}
+
+/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
+/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
+/* { dg-final { scan-assembler "custom\\t251, .* # fsqrts .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-4.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-4.c
new file mode 100644
index 000000000..6c5f2a24b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-4.c
@@ -0,0 +1,29 @@
+/* Test conflict between pragma and attribute specification of custom
+   instructions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+/* This test case is expected to cause an error because GCC does not know
+   how to merge different custom instruction attribute sets.  The extern
+   declaration sees the options specified by both the pragma and the function
+   attribute, but the function definition sees only the pragma options.  */
+
+#pragma GCC target ("custom-fmaxs=246")
+
+extern void
+custom_fp (float operand_a, float operand_b, float *result)
+  __attribute__ ((target ("custom-fmins=247")));
+
+void
+custom_fp (float operand_a, float operand_b, float *result)
+{   /* { dg-error "conflicting" } */
+  result[0] = fmaxf (operand_a, operand_b);
+  result[1] = fminf (operand_a, operand_b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-5.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-5.c
new file mode 100644
index 000000000..1dba87a4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-5.c
@@ -0,0 +1,26 @@
+/* Test that forward declaration and definition don't conflict when used
+   with pragma specification of custom instructions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+#pragma GCC target ("custom-fmaxs=246,custom-fmins=247")
+
+extern void
+custom_fp (float operand_a, float operand_b, float *result);
+
+void
+custom_fp (float operand_a, float operand_b, float *result)
+{
+  result[0] = fmaxf (operand_a, operand_b);
+  result[1] = fminf (operand_a, operand_b);
+}
+
+/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
+/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-6.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-6.c
new file mode 100644
index 000000000..7540c57b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-6.c
@@ -0,0 +1,30 @@
+/* Test conflict between pragma and attribute specification of custom
+   instructions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+/* This test case is expected to cause an error because GCC does not know
+   how to merge different custom instruction attribute sets, even if they
+   do not overlap.  */
+
+extern void
+custom_fp (float operand_a, float operand_b, float *result)
+  __attribute__ ((target ("custom-fmaxs=246")));
+
+extern void
+custom_fp (float operand_a, float operand_b, float *result)
+  __attribute__ ((target ("custom-fmins=247")));    /* { dg-error "conflicting" } */
+
+void
+custom_fp (float operand_a, float operand_b, float *result)
+{
+  result[0] = fmaxf (operand_a, operand_b);
+  result[1] = fminf (operand_a, operand_b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-7.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-7.c
new file mode 100644
index 000000000..6f17336fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-7.c
@@ -0,0 +1,33 @@
+/* Test that duplicate declarations with the same custom insn attributes
+   don't cause an error.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+/* This test case is expected to cause an error because GCC does not know
+   how to merge different custom instruction attribute sets, even if they
+   do not overlap.  */
+
+extern void
+custom_fp (float operand_a, float operand_b, float *result)
+  __attribute__ ((target ("custom-fmaxs=246,custom-fmins=247")));
+
+extern void
+custom_fp (float operand_a, float operand_b, float *result)
+  __attribute__ ((target ("custom-fmaxs=246,custom-fmins=247")));
+
+void
+custom_fp (float operand_a, float operand_b, float *result)
+{
+  result[0] = fmaxf (operand_a, operand_b);
+  result[1] = fminf (operand_a, operand_b);
+}
+
+/* { dg-final { scan-assembler "custom\\t246, .* # fmaxs .*" } } */
+/* { dg-final { scan-assembler "custom\\t247, .* # fmins .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-8.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-8.c
new file mode 100644
index 000000000..32f8a0414
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-8.c
@@ -0,0 +1,24 @@
+/* Test whitespace skipping in target attributes.  */
+
+/* { dg-do compile } */
+
+#pragma GCC target ("custom-fdivs=246")
+#pragma GCC target (" custom-fdivs=246")
+#pragma GCC target ("custom-fdivs =246")
+#pragma GCC target ("custom-fdivs= 246")
+#pragma GCC target ("custom-fdivs=246 ")
+
+#pragma GCC target ("custom-fdivs=246,custom-fabss=247")
+#pragma GCC target ("custom-fdivs=246 ,custom-fabss=247")
+#pragma GCC target ("custom-fdivs=246, custom-fabss=247")
+#pragma GCC target ("custom-fdivs=246 , custom-fabss=247")
+
+void foo (void) __attribute__ ((target ("custom-fcmpnes=226,custom-fcmpeqs=227")));
+void foo (void) __attribute__ ((target ("custom-fcmpnes =226 ,custom-fcmpeqs=227")));
+void foo (void) __attribute__ ((target ("custom-fcmpnes= 226, custom-fcmpeqs=227")));
+void foo (void) __attribute__ ((target (" custom-fcmpnes=226 , custom-fcmpeqs = 227")));
+void foo (void) __attribute__ ((target (" custom-fcmpnes=226 ,custom-fcmpeqs =227 ")));
+
+#pragma GCC target ("custom-fpu-cfg=60-1")
+#pragma GCC target ("custom-fpu-cfg =60-1 ")
+#pragma GCC target (" custom-fpu-cfg= 60-1 ")
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-cmp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-cmp-1.c
new file mode 100644
index 000000000..b290c41e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-cmp-1.c
@@ -0,0 +1,53 @@
+/* Test generation of floating-point compare custom instructions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#pragma GCC target ("custom-frdxhi=40")
+#pragma GCC target ("custom-frdxlo=41")
+#pragma GCC target ("custom-frdy=42")
+#pragma GCC target ("custom-fwrx=43")
+#pragma GCC target ("custom-fwry=44")
+
+#pragma GCC target ("custom-fcmpeqs=200")
+
+int
+test_fcmpeqs (float a, float b)
+{
+  return (a == b);
+}
+
+/* { dg-final { scan-assembler "custom\\t200, .* # fcmpeqs .*" } } */
+
+#pragma GCC target ("custom-fcmpgtd=201")
+
+int
+test_fcmpgtd (double a, double b)
+{
+  return (a > b);
+}
+
+/* { dg-final { scan-assembler "custom\\t201, .* # fcmpgtd .*" } } */
+
+#pragma GCC target ("custom-fcmples=202")
+
+int
+test_fcmples (float a, float b)
+{
+  return (a <= b);
+}
+
+/* { dg-final { scan-assembler "custom\\t202, .* # fcmples .*" } } */
+
+#pragma GCC target ("custom-fcmpned=203")
+
+int
+test_fcmpned (double a, double b)
+{
+  return (a != b);
+}
+
+/* { dg-final { scan-assembler "custom\\t203, .* # fcmpned .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-conversion.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-conversion.c
new file mode 100644
index 000000000..20b215996
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-conversion.c
@@ -0,0 +1,66 @@
+/* Test generation of conversion custom instructions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only -funsafe-math-optimizations" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+#pragma GCC target ("custom-frdxhi=40")
+#pragma GCC target ("custom-frdxlo=41")
+#pragma GCC target ("custom-frdy=42")
+#pragma GCC target ("custom-fwrx=43")
+#pragma GCC target ("custom-fwry=44")
+
+#pragma GCC target ("custom-fextsd=100")
+#pragma GCC target ("custom-fixdi=101")
+#pragma GCC target ("custom-fixdu=102")
+#pragma GCC target ("custom-fixsi=103")
+#pragma GCC target ("custom-fixsu=104")
+#pragma GCC target ("custom-floatid=105")
+#pragma GCC target ("custom-floatis=106")
+#pragma GCC target ("custom-floatud=107")
+#pragma GCC target ("custom-floatus=108")
+#pragma GCC target ("custom-ftruncds=109")
+
+typedef struct data {
+  double fextsd;
+  int fixdi;
+  unsigned fixdu;
+  int fixsi;
+  unsigned fixsu;
+  double floatid;
+  float floatis;
+  double floatud;
+  float floatus;
+  float ftruncds;
+} data_t;
+
+void
+custom_fp (int i, unsigned u, float f, double d, data_t *out)
+{
+  out->fextsd = (double) f;
+  out->fixdi = (int) d;
+  out->fixdu = (unsigned) d;
+  out->fixsi = (int) f;
+  out->fixsu = (unsigned) f;
+  out->floatid = (double) i;
+  out->floatis = (float) i;
+  out->floatud = (double) u;
+  out->floatus = (float) u;
+  out->ftruncds = (float) d;
+}
+
+/* { dg-final { scan-assembler "custom\\t100, .* # fextsd .*" } } */
+/* { dg-final { scan-assembler "custom\\t101, .* # fixdi .*" } } */
+/* { dg-final { scan-assembler "custom\\t102, .* # fixdu .*" } } */
+/* { dg-final { scan-assembler "custom\\t103, .* # fixsi .*" } } */
+/* { dg-final { scan-assembler "custom\\t104, .* # fixsu .*" } } */
+/* { dg-final { scan-assembler "custom\\t105, .* # floatid .*" } } */
+/* { dg-final { scan-assembler "custom\\t106, .* # floatis .*" } } */
+/* { dg-final { scan-assembler "custom\\t107, .* # floatud .*" } } */
+/* { dg-final { scan-assembler "custom\\t108, .* # floatus .*" } } */
+/* { dg-final { scan-assembler "custom\\t109, .* # ftruncds .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-double.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-double.c
new file mode 100644
index 000000000..d907c572a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-double.c
@@ -0,0 +1,86 @@
+/* Test generation of all double-float custom instructions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only -funsafe-math-optimizations" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+#pragma GCC target ("custom-frdxhi=40")
+#pragma GCC target ("custom-frdxlo=41")
+#pragma GCC target ("custom-frdy=42")
+#pragma GCC target ("custom-fwrx=43")
+#pragma GCC target ("custom-fwry=44")
+
+#pragma GCC target ("custom-fabsd=100")
+#pragma GCC target ("custom-faddd=101")
+#pragma GCC target ("custom-fatand=102")
+#pragma GCC target ("custom-fcosd=103")
+#pragma GCC target ("custom-fdivd=104")
+#pragma GCC target ("custom-fexpd=105")
+#pragma GCC target ("custom-flogd=106")
+#pragma GCC target ("custom-fmaxd=107")
+#pragma GCC target ("custom-fmind=108")
+#pragma GCC target ("custom-fmuld=109")
+#pragma GCC target ("custom-fnegd=110")
+#pragma GCC target ("custom-fsind=111")
+#pragma GCC target ("custom-fsqrtd=112")
+#pragma GCC target ("custom-fsubd=113")
+#pragma GCC target ("custom-ftand=114")
+#pragma GCC target ("custom-fcmpeqd=200")
+#pragma GCC target ("custom-fcmpged=201")
+#pragma GCC target ("custom-fcmpgtd=202")
+#pragma GCC target ("custom-fcmpled=203")
+#pragma GCC target ("custom-fcmpltd=204")
+#pragma GCC target ("custom-fcmpned=205")
+
+void
+custom_fp (double a, double b, double *fp, int *ip)
+{
+  fp[0] = fabs (a);
+  fp[1] = a + b;
+  fp[2] = atan (a);
+  fp[3] = cos (a);
+  fp[4] = a / b;
+  fp[5] = exp (a);
+  fp[6] = log (a);
+  fp[7] = fmax (a, b);
+  fp[8] = fmin (a, b);
+  fp[9] = a * b;
+  fp[10] = -b;
+  fp[11] = sin (b);
+  fp[12] = sqrt (a);
+  fp[13] = a - b;
+  fp[14] = tan (a);
+  ip[0] = (a == fp[0]);
+  ip[1] = (a >= fp[1]);
+  ip[2] = (a > fp[2]);
+  ip[3] = (a <= fp[3]);
+  ip[4] = (a < fp[4]);
+  ip[5] = (a != fp[5]);
+}
+
+/* { dg-final { scan-assembler "custom\\t100, .* # fabsd .*" } } */
+/* { dg-final { scan-assembler "custom\\t101, .* # faddd .*" } } */
+/* { dg-final { scan-assembler "custom\\t102, .* # fatand .*" } } */
+/* { dg-final { scan-assembler "custom\\t103, .* # fcosd .*" } } */
+/* { dg-final { scan-assembler "custom\\t104, .* # fdivd .*" } } */
+/* { dg-final { scan-assembler "custom\\t105, .* # fexpd .*" } } */
+/* { dg-final { scan-assembler "custom\\t106, .* # flogd .*" } } */
+/* { dg-final { scan-assembler "custom\\t107, .* # fmaxd .*" } } */
+/* { dg-final { scan-assembler "custom\\t108, .* # fmind .*" } } */
+/* { dg-final { scan-assembler "custom\\t109, .* # fmuld .*" } } */
+/* { dg-final { scan-assembler "custom\\t110, .* # fnegd .*" } } */
+/* { dg-final { scan-assembler "custom\\t111, .* # fsind .*" } } */
+/* { dg-final { scan-assembler "custom\\t112, .* # fsqrtd .*" } } */
+/* { dg-final { scan-assembler "custom\\t113, .* # fsubd .*" } } */
+/* { dg-final { scan-assembler "custom\\t114, .* # ftand .*" } } */
+/* { dg-final { scan-assembler "custom\\t200, .* # fcmpeqd .*" } } */
+/* { dg-final { scan-assembler "custom\\t201, .* # fcmpged .*" } } */
+/* { dg-final { scan-assembler "custom\\t202, .* # fcmpgtd .*" } } */
+/* { dg-final { scan-assembler "custom\\t203, .* # fcmpled .*" } } */
+/* { dg-final { scan-assembler "custom\\t204, .* # fcmpltd .*" } } */
+/* { dg-final { scan-assembler "custom\\t205, .* # fcmpned .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-float.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-float.c
new file mode 100644
index 000000000..26919d2f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/custom-fp-float.c
@@ -0,0 +1,80 @@
+/* Test generation of all single-float custom instructions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -ffinite-math-only -funsafe-math-optimizations" } */
+
+/* -O1 in the options is significant.  Without it FP operations may not be
+   optimized to custom instructions.  */
+
+#include <stdio.h> 
+#include <math.h>
+
+#pragma GCC target ("custom-fabss=100")
+#pragma GCC target ("custom-fadds=101")
+#pragma GCC target ("custom-fatans=102")
+#pragma GCC target ("custom-fcoss=103")
+#pragma GCC target ("custom-fdivs=104")
+#pragma GCC target ("custom-fexps=105")
+#pragma GCC target ("custom-flogs=106")
+#pragma GCC target ("custom-fmaxs=107")
+#pragma GCC target ("custom-fmins=108")
+#pragma GCC target ("custom-fmuls=109")
+#pragma GCC target ("custom-fnegs=110")
+#pragma GCC target ("custom-fsins=111")
+#pragma GCC target ("custom-fsqrts=112")
+#pragma GCC target ("custom-fsubs=113")
+#pragma GCC target ("custom-ftans=114")
+#pragma GCC target ("custom-fcmpeqs=200")
+#pragma GCC target ("custom-fcmpges=201")
+#pragma GCC target ("custom-fcmpgts=202")
+#pragma GCC target ("custom-fcmples=203")
+#pragma GCC target ("custom-fcmplts=204")
+#pragma GCC target ("custom-fcmpnes=205")
+
+void
+custom_fp (float a, float b, float *fp, int *ip)
+{
+  fp[0] = fabsf (a);
+  fp[1] = a + b;
+  fp[2] = atanf (a);
+  fp[3] = cosf (a);
+  fp[4] = a / b;
+  fp[5] = expf (a);
+  fp[6] = logf (a);
+  fp[7] = fmaxf (a, b);
+  fp[8] = fminf (a, b);
+  fp[9] = a * b;
+  fp[10] = -b;
+  fp[11] = sinf (b);
+  fp[12] = sqrtf (a);
+  fp[13] = a - b;
+  fp[14] = tanf (a);
+  ip[0] = (a == fp[0]);
+  ip[1] = (a >= fp[1]);
+  ip[2] = (a > fp[2]);
+  ip[3] = (a <= fp[3]);
+  ip[4] = (a < fp[4]);
+  ip[5] = (a != fp[5]);
+}
+
+/* { dg-final { scan-assembler "custom\\t100, .* # fabss .*" } } */
+/* { dg-final { scan-assembler "custom\\t101, .* # fadds .*" } } */
+/* { dg-final { scan-assembler "custom\\t102, .* # fatans .*" } } */
+/* { dg-final { scan-assembler "custom\\t103, .* # fcoss .*" } } */
+/* { dg-final { scan-assembler "custom\\t104, .* # fdivs .*" } } */
+/* { dg-final { scan-assembler "custom\\t105, .* # fexps .*" } } */
+/* { dg-final { scan-assembler "custom\\t106, .* # flogs .*" } } */
+/* { dg-final { scan-assembler "custom\\t107, .* # fmaxs .*" } } */
+/* { dg-final { scan-assembler "custom\\t108, .* # fmins .*" } } */
+/* { dg-final { scan-assembler "custom\\t109, .* # fmuls .*" } } */
+/* { dg-final { scan-assembler "custom\\t110, .* # fnegs .*" } } */
+/* { dg-final { scan-assembler "custom\\t111, .* # fsins .*" } } */
+/* { dg-final { scan-assembler "custom\\t112, .* # fsqrts .*" } } */
+/* { dg-final { scan-assembler "custom\\t113, .* # fsubs .*" } } */
+/* { dg-final { scan-assembler "custom\\t114, .* # ftans .*" } } */
+/* { dg-final { scan-assembler "custom\\t200, .* # fcmpeqs .*" } } */
+/* { dg-final { scan-assembler "custom\\t201, .* # fcmpges .*" } } */
+/* { dg-final { scan-assembler "custom\\t202, .* # fcmpgts .*" } } */
+/* { dg-final { scan-assembler "custom\\t203, .* # fcmples .*" } } */
+/* { dg-final { scan-assembler "custom\\t204, .* # fcmplts .*" } } */
+/* { dg-final { scan-assembler "custom\\t205, .* # fcmpnes .*" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-ashlsi3-one_shift.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-ashlsi3-one_shift.c
new file mode 100644
index 000000000..6af6d4f9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-ashlsi3-one_shift.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options " " } */
+/* { dg-final { scan-assembler-not "slli" } } */
+
+int x;
+
+void foo(void)
+{
+  x <<= 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-builtin-custom.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-builtin-custom.c
new file mode 100644
index 000000000..18399facc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-builtin-custom.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "custom" } } */
+
+/* This test case used to cause an unrecognizable insn crash.  */
+
+void foo (void)
+{
+  int offset = __builtin_custom_in(0x1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-builtin-io.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-builtin-io.c
new file mode 100644
index 000000000..58bc83f8a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-builtin-io.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "ldbio" } } */
+/* { dg-final { scan-assembler "ldbuio" } } */
+/* { dg-final { scan-assembler "ldhio" } } */
+/* { dg-final { scan-assembler "ldhuio" } } */
+/* { dg-final { scan-assembler "ldwio" } } */
+/* { dg-final { scan-assembler "stbio" } } */
+/* { dg-final { scan-assembler "sthio" } } */
+/* { dg-final { scan-assembler "stwio" } } */
+
+volatile char b;
+volatile short h;
+volatile int w;
+
+void x ()
+{
+  __builtin_ldbio (&b);
+  __builtin_ldbuio (&b);
+  __builtin_ldhio (&h);
+  __builtin_ldhuio (&h);
+  __builtin_ldwio (&w);
+
+  __builtin_stbio (&b, 42);
+  __builtin_sthio (&h, 43);
+  __builtin_stwio (&w, 44);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-cache-1.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-cache-1.c
new file mode 100644
index 000000000..5516a1367
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-cache-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "ldwio" } } */
+/* { dg-final { scan-assembler-not "stwio" } } */
+
+/* Make sure the default behavior is not to generate I/O variants of
+   the load and stores to foo.  */
+
+extern volatile int foo;
+
+int
+read_foo (void)
+{
+  return foo;
+}
+
+void
+write_foo (int x)
+{
+  foo = x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-cache-2.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-cache-2.c
new file mode 100644
index 000000000..239c600ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-cache-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-cache-volatile" } */
+/* { dg-final { scan-assembler "ldwio" } } */
+/* { dg-final { scan-assembler "stwio" } } */
+
+/* Make sure -mno-cache-volatile generates I/O variants of the load and
+   stores to foo.  */
+
+extern volatile int foo;
+
+int
+read_foo (void)
+{
+  return foo;
+}
+
+void
+write_foo (int x)
+{
+  foo = x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-custom-1.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-custom-1.c
new file mode 100644
index 000000000..c6e4b517e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-custom-1.c
@@ -0,0 +1,64 @@
+/* { dg-do compile } */
+
+float fres, f1, f2;
+int ires, i1, i2;
+void *pres, *p1, *p2;
+
+void x ()
+{
+  __builtin_custom_n (0);
+  __builtin_custom_ni (1, i1);
+  __builtin_custom_nf (2, f1);
+  __builtin_custom_np (3, p1);
+  __builtin_custom_nii (4, i1, i2);
+  __builtin_custom_nif (5, i1, f2);
+  __builtin_custom_nip (6, i1, p2);
+  __builtin_custom_nfi (7, f1, i2);
+  __builtin_custom_nff (8, f1, f2);
+  __builtin_custom_nfp (9, f1, p2);
+  __builtin_custom_npi (10, p1, i2);
+  __builtin_custom_npf (11, p1, f2);
+  __builtin_custom_npp (12, p1, p2);
+
+  ires = __builtin_custom_in (13+0);
+  ires = __builtin_custom_ini (13+1, i1);
+  ires = __builtin_custom_inf (13+2, f1);
+  ires = __builtin_custom_inp (13+3, p1);
+  ires = __builtin_custom_inii (13+4, i1, i2);
+  ires = __builtin_custom_inif (13+5, i1, f2);
+  ires = __builtin_custom_inip (13+6, i1, p2);
+  ires = __builtin_custom_infi (13+7, f1, i2);
+  ires = __builtin_custom_inff (13+8, f1, f2);
+  ires = __builtin_custom_infp (13+9, f1, p2);
+  ires = __builtin_custom_inpi (13+10, p1, i2);
+  ires = __builtin_custom_inpf (13+11, p1, f2);
+  ires = __builtin_custom_inpp (13+12, p1, p2);
+
+  fres = __builtin_custom_fn (26+0);
+  fres = __builtin_custom_fni (26+1, i1);
+  fres = __builtin_custom_fnf (26+2, f1);
+  fres = __builtin_custom_fnp (26+3, p1);
+  fres = __builtin_custom_fnii (26+4, i1, i2);
+  fres = __builtin_custom_fnif (26+5, i1, f2);
+  fres = __builtin_custom_fnip (26+6, i1, p2);
+  fres = __builtin_custom_fnfi (26+7, f1, i2);
+  fres = __builtin_custom_fnff (26+8, f1, f2);
+  fres = __builtin_custom_fnfp (26+9, f1, p2);
+  fres = __builtin_custom_fnpi (26+10, p1, i2);
+  fres = __builtin_custom_fnpf (26+11, p1, f2);
+  fres = __builtin_custom_fnpp (26+12, p1, p2);
+
+  pres = __builtin_custom_pn (39+0);
+  pres = __builtin_custom_pni (39+1, i1);
+  pres = __builtin_custom_pnf (39+2, f1);
+  pres = __builtin_custom_pnp (39+3, p1);
+  pres = __builtin_custom_pnii (39+4, i1, i2);
+  pres = __builtin_custom_pnif (39+5, i1, f2);
+  pres = __builtin_custom_pnip (39+6, i1, p2);
+  pres = __builtin_custom_pnfi (39+7, f1, i2);
+  pres = __builtin_custom_pnff (39+8, f1, f2);
+  pres = __builtin_custom_pnfp (39+9, f1, p2);
+  pres = __builtin_custom_pnpi (39+10, p1, i2);
+  pres = __builtin_custom_pnpf (39+11, p1, f2);
+  pres = __builtin_custom_pnpp (39+12, p1, p2);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-custom-2.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-custom-2.c
new file mode 100644
index 000000000..7f5d21a54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-custom-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+
+float foo (float) __attribute__ ((target ("custom-fsqrts=128")));
+float foo (float x)
+{
+  return __builtin_custom_fsqrts (x) + __builtin_custom_fnf (128, x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-int-types.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-int-types.c
new file mode 100644
index 000000000..21b4a02be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-int-types.c
@@ -0,0 +1,34 @@
+/* Test that various types are all derived from int.  */
+/* { dg-do compile } */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+extern size_t a;
+unsigned int a;
+extern unsigned int aa;
+size_t aa;
+
+extern ssize_t b;
+int b;
+extern int bb;
+ssize_t bb;
+
+extern ptrdiff_t c;
+int c;
+extern int cc;
+ptrdiff_t cc;
+
+extern intptr_t d;
+int d;
+extern int dd;
+intptr_t dd;
+
+extern uintptr_t e;
+unsigned int e;
+extern unsigned int ee;
+uintptr_t ee;
+
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-1.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-1.c
new file mode 100644
index 000000000..b639482bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "" } */
+/* { dg-final { scan-assembler "__muldi3" } } */
+
+long long x, y, z;
+
+void test()
+{
+  x = y * z;
+}
+  
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-2.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-2.c
new file mode 100644
index 000000000..f93b4e7c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mhw-mulx" } */
+/* { dg-final { scan-assembler-not "__muldi3" } } */
+
+long long x, y, z;
+
+void test()
+{
+  x = y * z;
+}
+  
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-3.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-3.c
new file mode 100644
index 000000000..2da74ba6b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "" } */
+/* { dg-final { scan-assembler-not "__mulsi3" } } */
+
+int x, y, z;
+
+void test()
+{
+  x = y * z;
+}
+  
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-4.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-4.c
new file mode 100644
index 000000000..7794f6d87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-mul-options-4.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-mno-hw-mul" } */
+/* { dg-final { scan-assembler "__mulsi3" } } */
+
+int x, y, z;
+
+void test()
+{
+  x = y * z;
+}
+  
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-nor.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-nor.c
new file mode 100644
index 000000000..3a1911e32
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-nor.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler "nor" } } */
+
+int foo (int x, int y)
+{
+  return ~(x | y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-rdctl.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-rdctl.c
new file mode 100644
index 000000000..6b44d88e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-rdctl.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "rdctl" } } */
+
+int x ()
+{
+  __builtin_rdctl (0);
+  return 0;
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-rdwrctl-1.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-rdwrctl-1.c
new file mode 100644
index 000000000..922942ab9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-rdwrctl-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+
+volatile int res;
+
+void x ()
+{
+  __builtin_wrctl (0, res);
+  __builtin_wrctl (15, res);
+  __builtin_wrctl (31, res);
+
+  res = __builtin_rdctl (0);
+  res = __builtin_rdctl (15);
+  res = __builtin_rdctl (31);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stack-check-1.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stack-check-1.c
new file mode 100644
index 000000000..415906fc5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stack-check-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-fstack-limit-register=et" } */
+/* { dg-final { scan-assembler "bgeu\\tsp, et" } } */
+/* { dg-final { scan-assembler "break\\t3" } } */
+/* check stack checking */
+void test()
+{
+  int a, b, c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stack-check-2.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stack-check-2.c
new file mode 100644
index 000000000..b903db5cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stack-check-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options " " } */
+/* { dg-final { scan-assembler-not "bgeu\\tsp, et" } } */
+/* { dg-final { scan-assembler-not "break\\t3" } } */
+/* check stack checking */
+void test()
+{
+  int a, b, c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stxio.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stxio.c
new file mode 100644
index 000000000..af079d641
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-stxio.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+
+void test_stbio (unsigned char* p1, unsigned char* p2)
+{
+  __builtin_stbio (p1, *p2);
+  __builtin_stbio (p2, 0);
+  __builtin_stbio (p2 + 1, 0x80);
+  __builtin_stbio (p2 + 2, 0x7f);
+}
+
+void test_sthio (unsigned short* p1, unsigned short* p2)
+{
+  __builtin_sthio (p1, *p2);
+  __builtin_sthio (p2, 0);
+  __builtin_sthio (p2 + 1, 0x8000);
+  __builtin_sthio (p2 + 2, 0x7fff);
+}
+
+void test_stwio (unsigned int* p1, unsigned int* p2)
+{
+  __builtin_stwio (p1, *p2);
+  __builtin_stwio (p2, 0);
+  __builtin_stwio (p2 + 1, 0x80000000);
+  __builtin_stwio (p2 + 2, 0x7fffffff);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-trap-insn.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-trap-insn.c
new file mode 100644
index 000000000..dd881d166
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-trap-insn.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "break\\t3" } } */
+
+/* Test the nios2 trap instruction */
+void foo(void){
+  __builtin_trap();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl-not-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl-not-zero.c
new file mode 100644
index 000000000..f32a9ca4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl-not-zero.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options " " } */
+/* { dg-final { scan-assembler-not "wrctl\\tctl6, zero" } } */
+
+void foo(void){
+  __builtin_wrctl(6,4);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl-zero.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl-zero.c
new file mode 100644
index 000000000..93f01b077
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl-zero.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+/* { dg-final { scan-assembler "wrctl\\tctl6, zero" } } */
+
+void foo(void){
+  __builtin_wrctl(6,0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl.c b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl.c
new file mode 100644
index 000000000..5ebdc24b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2-wrctl.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "" } */
+/* { dg-final { scan-assembler "wrctl" } } */
+
+void foo(void){
+  __builtin_wrctl(6,4);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2.exp b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2.exp
new file mode 100644
index 000000000..4f027048a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/nios2/nios2.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2012-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a Nios II target.
+if ![istarget nios2*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20020118-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20020118-1.c
new file mode 100644
index 000000000..b92dd2a7a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20020118-1.c
@@ -0,0 +1,21 @@
+/* { dg-do run { target powerpc*-*-* } }*/
+/* VxWorks only guarantees 64 bits of alignment (STACK_BOUNDARY == 64).  */
+/* { dg-skip-if "" { "powerpc*-*-vxworks*" } { "*" } { "" } } */
+/* Force 128-bit stack alignment for eabi targets.  */
+/* { dg-options "-mno-eabi" { target powerpc*-*-eabi* } } */
+
+/* Test local alignment.  Test new target macro STARTING_FRAME_PHASE.  */
+/* Origin: Aldy Hernandez <aldyh@redhat.com>.  */
+
+extern void abort(void);
+
+int main ()
+{       
+  int darisa[4] __attribute__((aligned(16))) ;
+  int *stephanie = (int *) darisa;
+
+  if ((unsigned long) stephanie % 16 != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20030218-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20030218-1.c
new file mode 100644
index 000000000..2a1c4e6d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20030218-1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+/* Test vectors that can interconvert without a cast.  */
+
+__ev64_opaque__ opp;
+int vint   __attribute__((vector_size (8)));
+short vshort __attribute__((vector_size (8)));
+float vfloat __attribute__((vector_size (8)));
+
+int
+main (void)
+{
+  __ev64_opaque__ george = { 1, 2 }; /* { dg-error "opaque vector types cannot be initialized" } */
+
+  opp = vfloat;
+  vshort = opp;
+  vfloat = vshort; /* { dg-error "incompatible types when assigning" } */
+
+  /* Just because this is a V2SI, it doesn't make it an opaque.  */
+  vint = vshort; /* { dg-message "note: use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts" } */
+  /* { dg-error "incompatible types when assigning" "" { target *-*-* } 22 } */
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20030505.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20030505.c
new file mode 100644
index 000000000..2bef590bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20030505.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-W -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+#define __vector __attribute__((vector_size(8)))
+
+typedef float                   __vector __ev64_fs__;
+
+__ev64_opaque__ *p1;
+__ev64_fs__ *p2;
+int *x;
+
+extern void f (__ev64_opaque__ *); /* { dg-message "expected.*but argument is of type" } */
+
+int main ()
+{
+	f (x);	/* { dg-warning "incompatible pointer type" } */
+	f (p1);
+	f (p2);
+	return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20040121-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20040121-1.c
new file mode 100644
index 000000000..f819a4949
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20040121-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -mcpu=G5 " } */
+
+long long (*y)(int t);
+long long get_alias_set (int t)
+{
+  return y(t);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20040622-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20040622-1.c
new file mode 100644
index 000000000..c699296d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20040622-1.c
@@ -0,0 +1,13 @@
+/* { dg-options "-Os -mlong-double-128" } */
+/* { dg-do compile { target { { rs6000-*-* } || { powerpc*-*-* && lp64 } } } } */
+/* Make sure compiler doesn't generate [reg+reg] address mode
+   for long doubles. */
+union arg {
+  int intarg;
+  long double longdoublearg;
+};
+long double d;
+int va(int n, union arg **argtable)
+{
+  (*argtable)[n].longdoublearg = d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20041111-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20041111-1.c
new file mode 100644
index 000000000..94de2f03a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20041111-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-mcpu=power4 -O2" } */
+
+extern unsigned long long set_mask[65];
+extern  unsigned long long xyzzy(int) __attribute__((pure));
+
+int valid (int x)
+{
+  return(xyzzy(x) & set_mask[x]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050603-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050603-1.c
new file mode 100644
index 000000000..041551ba5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050603-1.c
@@ -0,0 +1,24 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+#include <locale.h>
+#include <stdlib.h>
+register int *testreg asm ("r29");
+
+int x;
+int y;
+int *ext_func (int *p) { return p; }
+
+void test_reg_save_restore (int*) __attribute__((noinline));
+void
+test_reg_save_restore (int *p)
+{
+    setlocale (LC_ALL, "C");
+    testreg = ext_func(p);
+}
+main() {
+  testreg = &x;
+  test_reg_save_restore (&y);
+  if (testreg != &y)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050603-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050603-3.c
new file mode 100644
index 000000000..0f328e171
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050603-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-options "-O2" } */
+struct Q 
+{
+  long x:20;
+  long y:4;
+  long z:8;
+}b;
+/* This should generate a single rl[w]imi. */
+void rotins (unsigned int x)
+{
+  b.y = (x<<12) | (x>>20);
+}
+
+/* { dg-final { scan-assembler-not "inm" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050830-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050830-1.c
new file mode 100644
index 000000000..4a8f71a98
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20050830-1.c
@@ -0,0 +1,13 @@
+/* Make sure the doloop optimization is done for this loop. */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "bdn" } } */
+extern int a[];
+int foo(int w) {
+  int n = w;
+  while (n >= 512)
+    {
+    a[n] = 42;
+    n -= 256;
+    }
+  }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20081204-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20081204-1.c
new file mode 100644
index 000000000..8a973d0ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/20081204-1.c
@@ -0,0 +1,9 @@
+/* Test for ICE arising from inconsistent use of TARGET_E500 versus
+   TARGET_HARD_FLOAT && !TARGET_FPRS.  */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=750 -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+static int comp(const void *a,const void *b){
+  return (*(float *)a<*(float *)b)-(*(float *)a>*(float *)b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c
new file mode 100644
index 000000000..b06a74f64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c
@@ -0,0 +1,19 @@
+/* Test generation of dlmzb for strlen on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "dlmzb\\. " } } */
+
+typedef __SIZE_TYPE__ size_t;
+
+size_t strlen(const char *);
+
+size_t
+strlen8(const long long *s)
+{
+  return strlen((const char *)s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c
new file mode 100644
index 000000000..e65ba08eb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of macchw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "macchw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c
new file mode 100644
index 000000000..6263818c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of macchw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "macchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c
new file mode 100644
index 000000000..18d448c06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of macchwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "macchwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c
new file mode 100644
index 000000000..7728c8b68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of macchwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "macchwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c
new file mode 100644
index 000000000..2211cd158
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of machhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "machhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c
new file mode 100644
index 000000000..4c54f27b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of machhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "machhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c
new file mode 100644
index 000000000..44d8ea68c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of machhwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "machhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c
new file mode 100644
index 000000000..0fc96d1bd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-machhwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of machhwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "machhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c
new file mode 100644
index 000000000..43ec01914
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of maclhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "maclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c
new file mode 100644
index 000000000..d79df5285
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of maclhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "maclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c
new file mode 100644
index 000000000..0d65a5d34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of maclhwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "maclhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (unsigned short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c
new file mode 100644
index 000000000..5b148d66c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of maclhwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "maclhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (unsigned short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c
new file mode 100644
index 000000000..510e0c81c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mulchw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulchw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c
new file mode 100644
index 000000000..14b4df1c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mulchw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulchw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c
new file mode 100644
index 000000000..a0ecdac65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mulchwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulchwu " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c
new file mode 100644
index 000000000..c4da99273
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mulchwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulchwu\\. " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c
new file mode 100644
index 000000000..efdd8cdbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mulhhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulhhw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c
new file mode 100644
index 000000000..cfa00034e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mulhhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulhhw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c
new file mode 100644
index 000000000..c6f7a2452
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mulhhwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulhhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c
new file mode 100644
index 000000000..9b647e7d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mulhhwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mulhhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c
new file mode 100644
index 000000000..ea28b5542
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mullhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mullhw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c
new file mode 100644
index 000000000..76bbb6403
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mullhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mullhw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c
new file mode 100644
index 000000000..152dfe9b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c
@@ -0,0 +1,15 @@
+/* Test generation of mullhwu on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mullhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (unsigned short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c
new file mode 100644
index 000000000..ff4b8eca5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c
@@ -0,0 +1,17 @@
+/* Test generation of mullhwu. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "mullhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (unsigned short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c
new file mode 100644
index 000000000..dd258efe5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmacchw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of nmacchw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmacchw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c
new file mode 100644
index 000000000..2a470b9e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmacchw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of nmacchw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmacchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c
new file mode 100644
index 000000000..f699a3fc4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmachhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of nmachhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmachhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c
new file mode 100644
index 000000000..07a30c13f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmachhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of nmachhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmachhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c
new file mode 100644
index 000000000..91eba842a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c
@@ -0,0 +1,15 @@
+/* Test generation of nmaclhw on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmaclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c
new file mode 100644
index 000000000..83717a4ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c
@@ -0,0 +1,17 @@
+/* Test generation of nmaclhw. on 405.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=405" } */
+/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */
+
+/* { dg-final { scan-assembler "nmaclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c
new file mode 100644
index 000000000..9571b6695
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c
@@ -0,0 +1,18 @@
+/* Test generation of dlmzb for strlen on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "dlmzb\\. " } } */
+
+typedef __SIZE_TYPE__ size_t;
+
+size_t strlen(const char *);
+
+size_t
+strlen8(const long long *s)
+{
+  return strlen((const char *)s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c
new file mode 100644
index 000000000..464eff43b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of macchw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c
new file mode 100644
index 000000000..bfe55d486
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of macchw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c
new file mode 100644
index 000000000..1db6c6e71
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of macchwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c
new file mode 100644
index 000000000..eb0b9251c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of macchwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "macchwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c
new file mode 100644
index 000000000..78aac5cb6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of machhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c
new file mode 100644
index 000000000..caf05eb41
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of machhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c
new file mode 100644
index 000000000..7f1cab988
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of machhwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c
new file mode 100644
index 000000000..88a23087b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of machhwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "machhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c
new file mode 100644
index 000000000..327d2fbea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of maclhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c
new file mode 100644
index 000000000..3e92d7ac8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of maclhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a += (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c
new file mode 100644
index 000000000..248e54e8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of maclhwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhwu " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (unsigned short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c
new file mode 100644
index 000000000..c27988e2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-maclhwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of maclhwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "maclhwu\\. " } } */
+
+unsigned int
+f(unsigned int a, unsigned int b, unsigned int c)
+{
+  a += (unsigned short)b * (unsigned short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c
new file mode 100644
index 000000000..14b11e2f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mulchw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c
new file mode 100644
index 000000000..d09561cb1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mulchw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c
new file mode 100644
index 000000000..44bb325ce
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mulchwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchwu " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c
new file mode 100644
index 000000000..cc72f6193
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulchwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mulchwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulchwu\\. " } } */
+
+int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c
new file mode 100644
index 000000000..4b27396ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mulhhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c
new file mode 100644
index 000000000..4cfb7ebf0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mulhhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c
new file mode 100644
index 000000000..b255a9bdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mulhhwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c
new file mode 100644
index 000000000..e82bbc678
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mulhhwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mulhhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c
new file mode 100644
index 000000000..910885753
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mullhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhw " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c
new file mode 100644
index 000000000..023eb7187
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mullhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhw\\. " } } */
+
+int
+f(int b, int c)
+{
+  int a = (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c
new file mode 100644
index 000000000..3636e4c4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhwu-1.c
@@ -0,0 +1,14 @@
+/* Test generation of mullhwu on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhwu " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (unsigned short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c
new file mode 100644
index 000000000..93bc9f390
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-mullhwu-2.c
@@ -0,0 +1,16 @@
+/* Test generation of mullhwu. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "mullhwu\\. " } } */
+
+unsigned int
+f(unsigned int b, unsigned int c)
+{
+  unsigned int a = (unsigned short)b * (unsigned short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c
new file mode 100644
index 000000000..2fc782688
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of nmacchw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmacchw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c
new file mode 100644
index 000000000..3931ec530
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of nmacchw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmacchw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c
new file mode 100644
index 000000000..62362d03c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of nmachhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmachhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (b >> 16) * (c >> 16);
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c
new file mode 100644
index 000000000..22dac059c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of nmachhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmachhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (b >> 16) * (c >> 16);
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c
new file mode 100644
index 000000000..1fe13b137
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-1.c
@@ -0,0 +1,14 @@
+/* Test generation of nmaclhw on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmaclhw " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (short)c;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c
new file mode 100644
index 000000000..f2abc4ccf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/440-nmaclhw-2.c
@@ -0,0 +1,16 @@
+/* Test generation of nmaclhw. on 440.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=440" } */
+
+/* { dg-final { scan-assembler "nmaclhw\\. " } } */
+
+int
+f(int a, int b, int c)
+{
+  a -= (short)b * (short)c;
+  if (!a)
+    return 10;
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/980827-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/980827-1.c
new file mode 100644
index 000000000..c2c92337a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/980827-1.c
@@ -0,0 +1,29 @@
+/* { dg-do run { target { { *-*-linux* && ilp32 } && powerpc_fprs } } } */
+/* { dg-options -O2 } */
+
+extern void exit (int);
+extern void abort (void);
+
+double dval = 0;
+
+void splat (double d);
+
+int main(void)
+{
+  splat(0);
+  if (dval == 0)
+    abort();
+  exit (0);
+}
+
+void splat (double d)
+{
+  union {
+    double f;
+    unsigned int l[2];
+  } u;
+  
+  u.f = d + d;
+  u.l[1] |= 1;
+  asm volatile ("stfd %0,dval@sdarel(13)" : : "f" (u.f));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-1.c
new file mode 100644
index 000000000..b1809fe2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Program to test PowerPC AltiVec instructions.  */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+vector int a1 = { 100, 200, 300, 400 };
+vector int a2 = { 500, 600, 700, 800 };
+vector int addi = { 600, 800, 1000, 1200 };
+vector int avgi = { 300, 400, 500, 600 };
+
+vector float f1 = { 1.0, 2.0, 3.0, 4.0 };  
+vector float f2 = { 5.0, 6.0, 7.0, 8.0 };
+vector float f3;
+vector float addf = { 6.0, 8.0, 10.0, 12.0 };
+
+vector int k;
+vector float f, g, h;
+
+int main ()
+{
+  k = vec_add (a1, a2);
+  if (!vec_all_eq (addi, k))
+    abort ();
+
+  k = vec_avg (a1, a2);
+  if (!vec_all_eq (k, avgi))
+    abort ();
+
+  h = vec_add (f1, f2);
+  if (!vec_all_eq (h, addf))
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-10.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-10.c
new file mode 100644
index 000000000..f532eebbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-10.c
@@ -0,0 +1,79 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */
+
+#include <altivec.h>
+
+extern void exit (int);
+extern void abort (void);
+
+typedef union
+{
+  float         f[4];
+  unsigned int  i[4];
+  vector float  v;
+} vec_float_t;
+
+void 
+check_vec_all_num ()
+{
+  vec_float_t a, b, c;
+
+  a.i[0] = 0xfffa5a5a;
+  a.f[1] = 1.0;
+  a.f[2] = 1.0;
+  a.f[3] = 1.0;
+
+  b.f[0] = 1.0;
+  b.f[1] = 1.0;
+  b.f[2] = 1.0;
+  b.f[3] = 1.0;
+
+  c.i[0] = 0xfffa5a5a;
+  c.i[1] = 0xfffa5a5a;
+  c.i[2] = 0xfffa5a5a;
+  c.i[3] = 0xfffa5a5a;
+
+  if (vec_all_numeric (a.v))
+    abort ();
+
+  if (vec_all_nan (a.v))
+    abort ();
+
+  if (!vec_all_numeric (b.v))
+    abort ();
+
+  if (vec_all_nan (b.v))
+    abort ();
+
+  if (vec_all_numeric (c.v))
+    abort ();
+
+  if (!vec_all_nan (c.v))
+    abort ();
+
+}
+
+void 
+check_cmple()
+{
+  vector float a = {1.0, 2.0, 3.0, 4.0};
+  vector float b = {1.0, 3.0, 2.0, 5.0};
+  vector bool int aux;
+  vector signed int le = {-1, -1, 0, -1};
+
+  aux = vec_cmple (a, b);
+
+  if (!vec_all_eq (aux, le))
+    abort ();
+}
+
+
+int 
+main()
+{
+  check_cmple ();
+  check_vec_all_num ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-11.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-11.c
new file mode 100644
index 000000000..7e3510c31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-11.c
@@ -0,0 +1,59 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mno-vsx -mabi=altivec" } */
+/* { dg-final { scan-assembler-not "lvx" } } */
+#include <altivec.h>
+
+void foo (vector int);
+void foo_s (vector short);
+void foo_c (vector char);
+
+/* All constants should be loaded into vector register without
+   load from memory.  */
+void
+bar (void) 
+{
+  foo ((vector int) {0, 0, 0, 0});
+  foo ((vector int) {1, 1, 1, 1});
+  foo ((vector int) {15, 15, 15, 15});
+  foo ((vector int) {-16, -16, -16, -16});
+  foo ((vector int) {0x10001, 0x10001, 0x10001, 0x10001});
+  foo ((vector int) {0xf000f, 0xf000f, 0xf000f, 0xf000f});
+  foo ((vector int) {0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0});
+  foo ((vector int) {0x1010101, 0x1010101, 0x1010101, 0x1010101});  
+  foo ((vector int) {0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f});  
+  foo ((vector int) {0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0});
+  foo ((vector int) {0x10101010, 0x10101010, 0x10101010, 0x10101010});
+  foo ((vector int) {0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e});
+  foo ((vector int) {0x100010, 0x100010, 0x100010, 0x100010});
+  foo ((vector int) {0x1e001e, 0x1e001e, 0x1e001e, 0x1e001e});
+  foo ((vector int) {0x10, 0x10, 0x10, 0x10});
+  foo ((vector int) {0x1e, 0x1e, 0x1e, 0x1e});
+
+  foo_s ((vector short int) {0, 0, 0, 0, 0, 0, 0, 0});
+  foo_s ((vector short int) {1, 1, 1, 1, 1, 1, 1, 1});
+  foo_s ((vector short int) {15, 15, 15, 15, 15, 15, 15, 15});
+  foo_s ((vector short int) {-16, -16, -16, -16, -16, -16, -16, -16});
+  foo_s ((vector short int) {0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0, 
+			       0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0});
+  foo_s ((vector short int) {0xf0f, 0xf0f, 0xf0f, 0xf0f, 
+			       0xf0f, 0xf0f, 0xf0f, 0xf0f});
+  foo_s ((vector short int) {0x1010, 0x1010, 0x1010, 0x1010, 
+			       0x1010, 0x1010, 0x1010, 0x1010});
+  foo_s ((vector short int) {0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e, 
+			       0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e});
+
+  foo_c ((vector char) {0, 0, 0, 0, 0, 0, 0, 0,
+			  0, 0, 0, 0, 0, 0, 0, 0});
+  foo_c ((vector char) {1, 1, 1, 1, 1, 1, 1, 1, 
+			  1, 1, 1, 1, 1, 1, 1, 1});
+  foo_c ((vector char) {15, 15, 15, 15, 15, 15, 15, 15,
+			  15, 15, 15, 15, 15, 15, 15, 15});
+  foo_c ((vector char) {-16, -16, -16, -16, -16, -16, -16, -16,
+			  -16, -16, -16, -16, -16, -16, -16, -16});
+  foo_c ((vector char) {16, 16, 16, 16, 16, 16, 16, 16,
+			  16, 16, 16, 16, 16, 16, 16, 16});
+  foo_c ((vector char) {30, 30, 30, 30, 30, 30, 30, 30,
+			  30, 30, 30, 30, 30, 30, 30, 30});
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-12.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-12.c
new file mode 100644
index 000000000..39d26940d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-12.c
@@ -0,0 +1,93 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Program to test PowerPC AltiVec instructions.  */
+
+#include <altivec.h>
+
+extern void abort (void);
+#define CHECK_IF(E) if(!(E)) abort()
+
+vector int a1 = (vector int){ 100, 200, 300, 400 };
+vector int a2 = (vector int){ 500, 600, 700, 800 };
+vector int addi = (vector int){ 600, 800, 1000, 1200 };
+vector int avgi = (vector int){ 300, 400, 500, 600 };
+
+vector float f1 = (vector float){ 1.0, 2.0, 3.0, 4.0 };
+vector float f2 = (vector float){ 5.0, 6.0, 7.0, 8.0 };
+vector float f3;
+vector float addf1 = (vector float){ 6.0, 8.0, 10.0, 12.0 };
+vector float addf2 = (vector float){ 6.1, 8.1, 10.1, 12.1 };
+vector float addf3 = (vector float){ 6.0, 8.0, 9.9, 12.1 };
+vector int k;
+vector float f, g, h;
+
+int main ()
+{
+  k = vec_add (a1, a2);
+  CHECK_IF (vec_all_eq (addi, k));
+  CHECK_IF (vec_all_ge (addi, k));
+  CHECK_IF (vec_all_le (addi, k));
+  CHECK_IF (vec_any_eq (addi, k));
+  CHECK_IF (vec_any_ge (addi, k));
+  CHECK_IF (vec_any_le (addi, k));
+  CHECK_IF (!vec_any_ne (addi, k));
+  CHECK_IF (!vec_any_lt (addi, k));
+  CHECK_IF (!vec_any_gt (addi, k));
+  CHECK_IF (!vec_any_ne (addi, k));
+  CHECK_IF (!vec_any_lt (addi, k));
+  CHECK_IF (!vec_any_gt (addi, k));
+
+  k = vec_avg (a1, a2);
+  CHECK_IF (vec_all_eq (k, avgi));
+
+  h = vec_add (f1, f2);
+  CHECK_IF (vec_all_eq (h, addf1));
+  CHECK_IF (vec_all_ge (h, addf1));
+  CHECK_IF (vec_all_le (h, addf1));
+  CHECK_IF (vec_any_eq (h, addf1));
+  CHECK_IF (vec_any_ge (h, addf1));
+  CHECK_IF (vec_any_le (h, addf1));
+  CHECK_IF (!vec_any_ne (h, addf1));
+  CHECK_IF (!vec_any_lt (h, addf1));
+  CHECK_IF (!vec_any_gt (h, addf1));
+  CHECK_IF (!vec_any_ne (h, addf1));
+  CHECK_IF (!vec_any_lt (h, addf1));
+  CHECK_IF (!vec_any_gt (h, addf1));
+
+  CHECK_IF (vec_all_gt (addf2, addf1));
+  CHECK_IF (vec_any_gt (addf2, addf1));
+  CHECK_IF (vec_all_ge (addf2, addf1));
+  CHECK_IF (vec_any_ge (addf2, addf1));
+  CHECK_IF (vec_all_ne (addf2, addf1));
+  CHECK_IF (vec_any_ne (addf2, addf1));
+  CHECK_IF (!vec_all_lt (addf2, addf1));
+  CHECK_IF (!vec_any_lt (addf2, addf1));
+  CHECK_IF (!vec_all_le (addf2, addf1));
+  CHECK_IF (!vec_any_le (addf2, addf1));
+  CHECK_IF (!vec_all_eq (addf2, addf1));
+  CHECK_IF (!vec_any_eq (addf2, addf1));
+
+  CHECK_IF (vec_any_eq (addf3, addf1));
+  CHECK_IF (vec_any_ne (addf3, addf1));
+  CHECK_IF (vec_any_lt (addf3, addf1));
+  CHECK_IF (vec_any_le (addf3, addf1));
+  CHECK_IF (vec_any_gt (addf3, addf1));
+  CHECK_IF (vec_any_ge (addf3, addf1));
+  CHECK_IF (!vec_all_eq (addf3, addf1));
+  CHECK_IF (!vec_all_ne (addf3, addf1));
+  CHECK_IF (!vec_all_lt (addf3, addf1));
+  CHECK_IF (!vec_all_le (addf3, addf1));
+  CHECK_IF (!vec_all_gt (addf3, addf1));
+  CHECK_IF (!vec_all_ge (addf3, addf1));
+
+  CHECK_IF (vec_all_numeric (addf3));
+  CHECK_IF (vec_all_in (addf1, addf2));
+
+  CHECK_IF (vec_step (vector bool char) == 16);
+  CHECK_IF (vec_step (addf3) == 4);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-13.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-13.c
new file mode 100644
index 000000000..22ff951b8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-13.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+/* Author: Ziemowit Laski  <zlaski@apple.com>  */
+
+/* This test case exercises intrinsic/argument combinations that,
+   while not in the Motorola AltiVec PIM, have nevertheless crept
+   into the AltiVec vernacular over the years.  */
+
+#include <altivec.h>
+
+void foo (void) 
+{
+  vector bool int boolVec1 = (vector bool int) vec_splat_u32(3);
+  vector bool short boolVec2 = (vector bool short) vec_splat_u16(3);
+  vector bool char boolVec3 = (vector bool char) vec_splat_u8(3);
+
+  boolVec1 = vec_sld( boolVec1, boolVec1, 4 );
+  boolVec2 = vec_sld( boolVec2, boolVec2, 2 );
+  boolVec3 = vec_sld( boolVec3, boolVec3, 1 );
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-14.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-14.c
new file mode 100644
index 000000000..55acb0b35
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-14.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+#include <altivec.h>
+
+vector bool long vbl;		/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector signed long vsl;		/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector unsigned long vul;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector bool long *pvbl;		/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector signed long *pvsl;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+vector unsigned long *pvul;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+
+void fvbl (vector bool long v) { }	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+void fvsl (vector signed long v) { }	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+void fvul (vector unsigned long v) { }	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+
+int main ()
+{
+  vector bool long lvbl;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+  vector signed long lvsl;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+  vector unsigned long lvul;	/* { dg-warning "use of .long. in AltiVec types is deprecated; use .int." } */
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-15.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-15.c
new file mode 100644
index 000000000..4e48cb765
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-15.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+/* Test whether the C front-end is not excessively picky about
+   the integral types and literals that AltiVec instrinsics will
+   accept.  */
+
+vector int vi = { 1, 2, 3, 4 };
+
+int
+main (void)
+{
+    unsigned long ul = 2;
+    signed long sl = 2;
+    unsigned int ui = 2;
+    signed int si = 2;
+    float fl = 2.0;
+
+    vec_dst (&vi, ul, '\0');
+    vec_dst (&vi, sl, 0);
+    vec_dst (&vi, ui, '\0');
+    vec_dst (&vi, si, 0);
+    vec_dstst (&vi, (short)fl, '\0');
+
+    return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-16.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-16.c
new file mode 100644
index 000000000..7f7d2b013
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-16.c
@@ -0,0 +1,22 @@
+/* This is a compile-only test for interaction of "-maltivec" and "-save-temps".  */
+/* Author:  Ziemowit Laski  <zlaski@apple.com>.  */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-save-temps -maltivec" } */
+
+#include <altivec.h>
+
+#define vector_float vector float
+#define vector_float_foo vector float foo
+#define vector_float_bar_eq vector float bar =
+
+/* NB: Keep the following split across three lines.  */
+vector
+int
+a1 = { 100, 200, 300, 400 };
+
+vector_float f1 = { 1.0, 2.0, 3.0, 4.0 };  
+vector_float_foo = { 3.0, 4.0, 5.0, 6.0 };
+vector_float_bar_eq { 8.0, 7.0, 6.0, 5.0 };
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-17.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-17.c
new file mode 100644
index 000000000..8b1083268
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-17.c
@@ -0,0 +1,11 @@
+/* Verify a statement in the GCC Manual that GCC allows the use of a
+   typedef name as a vector type specifier.  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+
+typedef unsigned int ui;
+typedef signed char sc;
+__vector ui vui;
+__vector sc vsc;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-18.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-18.c
new file mode 100644
index 000000000..5d9885820
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-18.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+/* { dg-final { scan-assembler "vcmpgtub" { target *-*-linux* } } } */
+/* { dg-final { scan-assembler "vcmpgtsb" { target *-*-darwin* } } } */
+/* { dg-final { scan-assembler "vcmpgtsh" } } */
+/* { dg-final { scan-assembler "vcmpgtsw" } } */
+
+/* Verify a statement in the GCC Manual that vector type specifiers can
+   omit "signed" or "unsigned".  The default is the default signedness
+   of the base type, which differs depending on the ABI.  */
+
+#include <altivec.h>
+
+extern vector char vc1, vc2;
+extern vector short vs1, vs2;
+extern vector int vi1, vi2;
+
+int signedness (void)
+{
+    return vec_all_le (vc1, vc2) 
+           && vec_all_le (vs1, vs2)
+           && vec_all_le (vi1, vi2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-19.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-19.c
new file mode 100644
index 000000000..80f305a54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-19.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+/* { dg-final { scan-assembler "dst" } } */
+
+void foo ( char* image )
+{
+  while ( 1 )
+    {
+      __builtin_altivec_dst( (void *)( (long)image & ~0x0f ), 0, 0 );
+      image += 48;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-2.c
new file mode 100644
index 000000000..4f341dd42
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Program to test the vector_size attribute.  This needs to run on a
+   target that has vectors, so use AltiVec.  */
+
+#define vector __attribute__((vector_size(16)))
+
+vector int foobar;
+
+/* Only floats and integrals allowed.  We don't care if they map to SIs.  */
+struct X { int frances; };
+vector struct X hotdog;	/* { dg-error "invalid vector type" } */
+
+/* Arrays of vectors.  */
+vector char b[10], ouch;
+
+/* Pointers of vectors.  */
+vector short *shoe, polish;
+
+int xxx[sizeof(foobar) == 16 ? 69 : -1];
+
+int nc17[sizeof(shoe) == sizeof (char *) ? 69 : -1];
+
+code ()
+{
+  *shoe = polish;
+  b[1] = ouch;
+}
+
+vector short
+hoop ()
+{
+  return polish;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-20.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-20.c
new file mode 100644
index 000000000..b2c29a979
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-20.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target powerpc_altivec_ok } } */
+/* { dg-options "-maltivec -mcpu=G5 -O2" } */
+
+#include <altivec.h>
+
+void foo( float scalar)
+{
+    unsigned long width;
+    unsigned long x;
+    vector float vColor;
+    vector unsigned int selectMask;
+    vColor = vec_perm( vec_ld( 0, &scalar), vec_ld( 3, &scalar), vec_lvsl( 0, &scalar) );
+
+    float *destRow;
+    vector float store, load0;
+
+    for( ; x < width; x++)
+    {
+            load0 = vec_sel( vColor, load0, selectMask );
+            vec_st( store, 0, destRow );
+            store = load0;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-21.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-21.c
new file mode 100644
index 000000000..906aa197a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-21.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+extern void preansi();
+
+typedef void (*pvecfunc) ();
+
+void foo(pvecfunc pvf) {
+   vector int v = (vector int){1, 2, 3, 4};
+#ifndef __LP64__
+   preansi (4, 4.0, v); /* { dg-error "AltiVec argument passed to unprototyped function" "" { target ilp32 } } */
+   (*pvf)  (4, 4.0, v); /* { dg-error "AltiVec argument passed to unprototyped function" "" { target ilp32 } } */
+#endif /* __LP64__ */
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-22.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-22.c
new file mode 100644
index 000000000..3c07309e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-22.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O3 -maltivec" } */
+/* { dg-final { scan-assembler-not "mfcr" } } */
+
+#include <altivec.h>
+
+int foo(vector float x, vector float y) {
+        if (vec_all_eq(x,y)) return 3245;
+        else return 12;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-23.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-23.c
new file mode 100644
index 000000000..3b039f73b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-23.c
@@ -0,0 +1,24 @@
+/* Verify that it is possible to define variables of composite types
+   containing vector types.  We used to crash handling the
+   initializer of automatic ones.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec" } */
+
+#include <altivec.h>
+
+typedef vector int vt;
+typedef struct { vt x; int y[sizeof(vt) / sizeof (int)]; } st;
+#define INIT { 1, 2, 3, 4 }
+
+void f ()
+{
+  vt x = INIT;
+  vt y[1] = { INIT };
+  st s = { INIT, INIT };
+}
+
+vt x = INIT;
+vt y[1] = { INIT };
+st s = { INIT, INIT };
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-24.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-24.c
new file mode 100644
index 000000000..d296fe246
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-24.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+typedef int v4si __attribute__ ((vector_size (16)));
+
+#define MAGIC_NUMBER 12345
+
+v4si my_vect;
+int my_array[4] __attribute__ ((aligned (16)));
+
+void initialize (int a)
+{
+  my_vect = (v4si) {0, a, 2, 3};
+  vec_st (my_vect, 0, my_array);
+}
+
+int verify (void)
+{
+  if (my_array[1] != MAGIC_NUMBER)
+    abort ();
+}
+
+int main (void)
+{
+  initialize (MAGIC_NUMBER);
+  verify ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-25.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-25.c
new file mode 100644
index 000000000..a3bd0fd00
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-25.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -Wall" } */
+
+
+#define vector __attribute__((__vector_size__(16) ))
+vector int f()
+{
+  int t = 4;
+  return (vector int){t,t,t,t};
+}
+vector int f1()
+{
+  return (vector int){4,4,4,4};
+}
+
+/* We should be able to materialize the constant vector without
+   any lvewx instructions as it is constant. */
+/* { dg-final { scan-assembler-not "lvewx" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-26.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-26.c
new file mode 100644
index 000000000..689d13a51
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-26.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* A compiler implementing context-sensitive keywords must define this
+   preprocessor macro so that altivec.h does not provide the vector,
+   pixel, etc. macros.  */
+
+#ifndef __APPLE_ALTIVEC__
+#error __APPLE_ALTIVEC__ not pre-defined
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-27.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-27.c
new file mode 100644
index 000000000..7db0ea01f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-27.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#define f0() void x0 (vector float x) { }
+f0 ()
+
+#define f1(type) void x1##type (vector type x) { }
+f1 (float)
+
+#define f2(v, type) void x2##type (v type x) { }
+f2 (vector, float)
+
+#define f3(type) void x3##type (vector bool type x) { }
+f3 (int)
+
+#define f4(v, type) void x4##type (v bool type x) { }
+f4 (vector, int)
+
+#define f5(b, type) void x5##type (vector b type x) { }
+f5 (bool, int)
+
+#define f6(v, b, type) void x6##type (v b type x) { }
+f6 (vector, bool, int)
+
+#define f7(v, b, type) void x7##type (v type b x) { }
+f7 (vector, bool, int)
+
+int vector = 6;
+
+#define v1(v) int x8 (int v) { return v; }
+v1(vector)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-28.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-28.c
new file mode 100644
index 000000000..db6c25ac7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-28.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#define B bool
+#define P pixel
+#define I int
+#define BI bool int
+#define PI pixel int
+
+vector B int i;
+vector P int j;
+vector B I k;
+vector P I l;
+vector BI m;
+vector PI n;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-29.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-29.c
new file mode 100644
index 000000000..10a25ecbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-29.c
@@ -0,0 +1,23 @@
+/* PR target/39558 */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -save-temps" } */
+
+#define ATTRIBUTE_UNUSED __attribute__((unused))
+
+int *foo (int *vector)
+{
+  return vector;
+}
+
+int *bar (int *vector ATTRIBUTE_UNUSED)
+{
+  return vector;
+}
+
+int *baz (int *vector __attribute__((unused)))
+{
+  return vector;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-3.c
new file mode 100644
index 000000000..d388ad299
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-3.c
@@ -0,0 +1,80 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+extern void exit (int);
+extern void abort (void);
+
+typedef int int4 __attribute__ ((vector_size (16)));
+typedef float float4 __attribute__ ((vector_size (16)));
+
+int4 a1 = (int4) { 100, 200, 300, 400 };
+int4 a2 = (int4) { 500, 600, 700, 800 };
+
+float4 f1 = (float4) { 1.0, 2.0, 3.0, 4.0 };  
+float4 f2 = (float4) { 5.0, 6.0, 7.0, 8.0 };
+
+int i3[4] __attribute__((aligned(16)));
+int j3[4] __attribute__((aligned(16)));
+float h3[4] __attribute__((aligned(16)));
+float g3[4] __attribute__((aligned(16)));
+
+#define vec_store(dst, src) \
+  __builtin_vec_st (src, 0, (__typeof__ (src) *) dst)
+
+#define vec_add_int4(x, y) \
+  __builtin_altivec_vaddsws (x, y)
+
+#define vec_add_float4(x, y) \
+  __builtin_altivec_vaddfp (x, y)
+
+#define my_abs(x) (x > 0.0F ? x : -x)
+
+void
+compare_int4 (int *a, int *b)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if (a[i] != b[i])
+      abort ();
+}
+
+void
+compare_float4 (float *a, float *b)
+{
+  int i;
+
+  for (i = 0; i < 4; ++i)
+    if (my_abs(a[i] - b[i]) >= 1.0e-6)
+      abort ();
+}
+
+void
+main1 ()
+{
+  int loc1 = 600, loc2 = 800;
+  int4 a3 = (int4) { loc1, loc2, 1000, 1200 };
+  int4 itmp;
+  double locf = 12.0;
+  float4 f3 = (float4) { 6.0, 8.0, 10.0, 12.0 };
+  float4 ftmp;
+
+  vec_store (i3, a3);
+  itmp = vec_add_int4 (a1, a2);
+  vec_store (j3, itmp);
+  compare_int4 (i3, j3);
+
+  vec_store (g3, f3);
+  ftmp = vec_add_float4 (f1, f2);
+  vec_store (h3, ftmp);
+  compare_float4 (g3, h3);
+}
+
+int
+main ()
+{
+  main1 ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-30.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-30.c
new file mode 100644
index 000000000..99783191d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-30.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <stdbool.h>
+#include <altivec.h>
+
+#define f0(type) void x0##type (vector bool type x) { }
+f0 (int)
+
+#define f1(v, type) void x1##type (v bool type x) { }
+f1 (vector, int)
+
+#define f2(b, type) void x2##type (vector b type x) { }
+f2 (bool, int)
+
+#define f3(v, b, type) void x3##type (v b type x) { }
+f3 (vector, bool, int)
+
+#define f4(v, b, type) void x4##type (v type b x) { }
+f4 (vector, bool, int)
+
+#define B bool
+#define I int
+#define BI bool int
+#define VBI vector bool int
+
+vector bool int a;
+vector B int b;
+vector B I c;
+vector BI d;
+VBI e;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-31.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-31.c
new file mode 100644
index 000000000..233efe1be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-31.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#define f0(type) void x0##type (vector _Bool type x) { }
+f0 (int)
+
+#define f1(v, type) void x1##type (v _Bool type x) { }
+f1 (vector, int)
+
+#define f2(b, type) void x2##type (vector b type x) { }
+f2 (_Bool, int)
+
+#define f3(v, b, type) void x3##type (v b type x) { }
+f3 (vector, _Bool, int)
+
+#define f4(v, b, type) void x4##type (v type b x) { }
+f4 (vector, _Bool, int)
+
+#define B _Bool
+#define I int
+#define BI _Bool int
+#define VBI vector _Bool int
+
+vector _Bool int a;
+vector B int b;
+vector B I c;
+vector BI d;
+VBI e;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-32.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-32.c
new file mode 100644
index 000000000..fd9f4bcca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-32.c
@@ -0,0 +1,59 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power6 -maltivec" } */
+/* { dg-final { scan-assembler "vsel" } } */
+/* { dg-final { scan-assembler "vrfim" } } */
+/* { dg-final { scan-assembler "vrfip" } } */
+/* { dg-final { scan-assembler "vrfiz" } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+float a[SIZE] __attribute__((__aligned__(32)));
+float b[SIZE] __attribute__((__aligned__(32)));
+float c[SIZE] __attribute__((__aligned__(32)));
+float d[SIZE] __attribute__((__aligned__(32)));
+float e[SIZE] __attribute__((__aligned__(32)));
+
+extern float floorf (float);
+extern float ceilf (float);
+extern float truncf (float);
+extern float copysignf (float, float);
+
+void
+vector_floor (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = floorf (b[i]);
+}
+
+void
+vector_ceil (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = ceilf (b[i]);
+}
+
+void
+vector_trunc (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = truncf (b[i]);
+}
+
+void
+vector_copysign (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = copysignf (b[i], c[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-33.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-33.c
new file mode 100644
index 000000000..8e912679d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-33.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mno-vsx" } */
+
+/* We should only produce one vspltw as we already splatted the value.  */
+/* { dg-final { scan-assembler-times "vspltw" 1 } } */
+
+#include <altivec.h>
+
+vector float f(vector float a)
+{
+  vector float b = vec_splat (a, 2);
+  return vec_splat (b, 0);
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-34.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-34.c
new file mode 100644
index 000000000..98fa5d2d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-34.c
@@ -0,0 +1,25 @@
+/* PR target/49621 */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mno-vsx" } */
+
+#include <altivec.h>
+
+int
+foo (void)
+{
+  vector unsigned a, b, c;
+  unsigned k = 1;
+
+  a = (vector unsigned) { 0, 0, 0, 1 };
+  b = c = (vector unsigned) { 0, 0, 0, 0 };
+
+  a = vec_add (a, vec_splats (k));
+  b = vec_add (b, a);
+  c = vec_sel (c, a, b);
+
+  if (vec_any_eq (b, c))
+    return 1;
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-4.c
new file mode 100644
index 000000000..2c78f6586
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-4.c
@@ -0,0 +1,65 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O0 -Wall" } */
+
+#define vector __attribute__((vector_size(16)))
+
+static int vector x, y, z;
+
+static vector signed int i,j;
+static vector signed short s,t;
+static vector signed char c,d;
+static vector float f,g;
+
+static vector unsigned char uc;
+
+static vector signed int *pi;
+
+static int int1, int2;
+
+void
+b()
+{
+  z = __builtin_altivec_vadduwm (x, y);
+
+  /* Make sure the predicates accept correct argument types.  */
+  
+  int1 = __builtin_altivec_vcmpbfp_p (0, f, g);
+  int1 = __builtin_altivec_vcmpeqfp_p (0, f, g);
+  int1 = __builtin_altivec_vcmpequb_p (0, c, d);
+  int1 = __builtin_altivec_vcmpequh_p (0, s, t);
+  int1 = __builtin_altivec_vcmpequw_p (0, i, j);
+  int1 = __builtin_altivec_vcmpgefp_p (0, f, g);
+  int1 = __builtin_altivec_vcmpgtfp_p (0, f, g);
+  int1 = __builtin_altivec_vcmpgtsb_p (0, c, d);
+  int1 = __builtin_altivec_vcmpgtsh_p (0, s, t);
+  int1 = __builtin_altivec_vcmpgtsw_p (0, i, j);
+  int1 = __builtin_altivec_vcmpgtub_p (0, c, d);
+  int1 = __builtin_altivec_vcmpgtuh_p (0, s, t);
+  int1 = __builtin_altivec_vcmpgtuw_p (0, i, j);
+
+  __builtin_altivec_mtvscr (i);
+  __builtin_altivec_dssall ();
+  s = __builtin_altivec_mfvscr ();
+  __builtin_altivec_dss (3);
+
+  __builtin_altivec_dst (pi, int1 + int2, 3);
+  __builtin_altivec_dstst (pi, int1 + int2, 3);
+  __builtin_altivec_dststt (pi, int1 + int2, 3);
+  __builtin_altivec_dstt (pi, int1 + int2, 3);
+
+  uc = (vector unsigned char) __builtin_altivec_lvsl (int1 + 69, pi);
+  uc = (vector unsigned char) __builtin_altivec_lvsr (int1 + 69, pi);
+
+  c = __builtin_altivec_lvebx (int1, pi);
+  s = __builtin_altivec_lvehx (int1, pi);
+  i = __builtin_altivec_lvewx (int1, pi);
+  i = __builtin_altivec_lvxl (int1, pi);
+  i = __builtin_altivec_lvx (int1, pi);
+
+  __builtin_altivec_stvx (i, int2, pi);
+  __builtin_altivec_stvebx (c, int2, pi);
+  __builtin_altivec_stvehx (s, int2, pi);
+  __builtin_altivec_stvewx (i, int2, pi);
+  __builtin_altivec_stvxl (i, int2, pi);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-5.c
new file mode 100644
index 000000000..ae85cdbdc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-5.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#define vector __attribute__((vector_size(16)))
+
+void foo (const unsigned long x,
+	  vector signed int a, vector signed int b)
+{
+  unsigned char d[64];
+
+  __builtin_altivec_stvewx (b, 0, d);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-6.c
new file mode 100644
index 000000000..51d411688
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-6.c
@@ -0,0 +1,66 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O0 -Wall" } */
+
+#include <altivec.h>
+
+/* These denote "generic" GCC vectors.  */
+static int __attribute__((vector_size(16))) x, y, z;
+
+static vector signed int i,j;
+static vector signed short s,t;
+static vector signed char c,d;
+static vector float f,g;
+
+static vector unsigned char uc;
+
+static vector signed int *pi;
+
+static int int1, int2;
+
+void
+b()
+{
+  z = vec_add (x, y);
+
+  /* Make sure the predicates accept correct argument types.  */
+
+  int1 = vec_all_in (f, g);
+  int1 = vec_all_ge (f, g);
+  int1 = vec_all_eq (c, d);
+  int1 = vec_all_ne (s, t);
+  int1 = vec_any_eq (i, j);
+  int1 = vec_any_ge (f, g);
+  int1 = vec_all_ngt (f, g);
+  int1 = vec_any_ge (c, d);
+  int1 = vec_any_ge (s, t);
+  int1 = vec_any_ge (i, j);
+  int1 = vec_any_ge (c, d);
+  int1 = vec_any_ge (s, t);
+  int1 = vec_any_ge (i, j);
+
+  vec_mtvscr (i);
+  vec_dssall ();
+  s = (vector signed short) vec_mfvscr ();
+  vec_dss (3);
+
+  vec_dst (pi, int1 + int2, 3);
+  vec_dstst (pi, int1 + int2, 3);
+  vec_dststt (pi, int1 + int2, 3);
+  vec_dstt (pi, int1 + int2, 3);
+
+  uc = (vector unsigned char) vec_lvsl (int1 + 69, (signed int *) pi);
+  uc = (vector unsigned char) vec_lvsr (int1 + 69, (signed int *) pi);
+
+  c = vec_lde (int1, (signed char *) pi);
+  s = vec_lde (int1, (signed short *) pi);
+  i = vec_lde (int1, (signed int *) pi);
+  i = vec_ldl (int1, pi);
+  i = vec_ld (int1, pi);
+
+  vec_st (i, int2, pi);
+  vec_ste (c, int2, (signed char *) pi);
+  vec_ste (s, int2, (signed short *) pi);
+  vec_ste (i, int2, (signed int *) pi);
+  vec_stl (i, int2, pi);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-7.c
new file mode 100644
index 000000000..30a1ee520
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -0,0 +1,46 @@
+/* Origin: Aldy Hernandez  <aldyh@redhat.com>  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+int **intp;
+int *var_int;
+unsigned int **uintp;
+vector pixel *varpixel;
+vector signed char *vecchar;
+vector signed int *vecint;
+vector signed short *vecshort;
+vector unsigned char *vecuchar;
+vector unsigned int *vecuint;
+vector unsigned short *vecushort;
+vector float *vecfloat;
+
+int main ()
+{
+  *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]);
+  *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]);
+  *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]);
+  *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]);
+  *varpixel++ = vec_packpx(vecuint[0], vecuint[1]);
+  *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]);
+  *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]);
+  *vecint++ = vec_ld(var_int[0], intp[1]);
+  *vecint++ = vec_lde(var_int[0], intp[1]);
+  *vecint++ = vec_ldl(var_int[0], intp[1]);
+  *vecint++ = vec_lvewx(var_int[0], intp[1]);
+  *vecint++ = vec_unpackh(vecshort[0]);
+  *vecint++ = vec_unpackl(vecshort[0]);
+  *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]);
+  *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]);
+  *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]);
+  *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]);
+  *vecuint++ = vec_ld(var_int[0], uintp[1]);
+  *vecuint++ = vec_lvx(var_int[0], uintp[1]);
+  *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]);
+  *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-8.c
new file mode 100644
index 000000000..6668cf2db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-8.c
@@ -0,0 +1,19 @@
+/* Origin: Aldy Hernandez  <aldyh@redhat.com>  */
+/* Test rs6000_legitimate_address.  PRE_INC should be invalid.  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector signed short *hannah;
+
+int
+main ()
+{
+  *hannah++ = __builtin_altivec_vspltish (5);
+  *hannah++ = __builtin_altivec_vspltish (6);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-9.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-9.c
new file mode 100644
index 000000000..b34dc1b51
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-9.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -g" } */
+
+/* PR9564 */
+
+extern int vfork(void);
+
+void
+boom (void)
+{
+  char buf[65536];
+  vfork();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c
new file mode 100644
index 000000000..20d29bf05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Basic test for the new VMX intrinsics.  */
+#include <altivec.h>
+
+int f(vector int a, int b)
+{
+  return vec_extract (a, b);
+}
+short f1(vector short a, int b)
+{
+  return vec_extract (a, b);
+}
+vector short f2(vector short a, int b)
+{
+  return vec_insert (b, a, b);
+}
+vector float f3(vector float a, int b)
+{
+  return vec_insert (b, a, b);
+}
+
+float g(void);
+
+vector float f4(float b, int t)
+{
+  return vec_promote (g(), t);
+}
+vector float f5(float b)
+{
+  return vec_splats (g());
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c
new file mode 100644
index 000000000..fdb375c9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-2.c
@@ -0,0 +1,141 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+/* Test the vec_extract VMX intrinsics.  */
+#include <altivec.h>
+
+extern void abort (void);
+
+vector int a = {0, 1, 2, 3};
+vector short b = {0, 1, 2, 3, 4, 5, 6, 7};
+
+int f(vector int a, int b)
+{
+  return vec_extract (a, b);
+}
+
+int f0 (vector int a)
+{
+  return vec_extract (a, 0);
+}
+int f1 (vector int a)
+{
+  return vec_extract (a, 1);
+}
+int f2 (vector int a)
+{
+  return vec_extract (a, 2);
+}
+int f3 (vector int a)
+{
+  return vec_extract (a, 3);
+}
+int f4 (vector int a)
+{
+  return vec_extract (a, 4);
+}
+
+int g(vector short a, int b)
+{
+  return vec_extract (a, b);
+}
+
+int g0 (vector short a)
+{
+  return vec_extract (a, 0);
+}
+int g1 (vector short a)
+{
+  return vec_extract (a, 1);
+}
+int g2 (vector short a)
+{
+  return vec_extract (a, 2);
+}
+int g3 (vector short a)
+{
+  return vec_extract (a, 3);
+}
+
+int g4 (vector short a)
+{ 
+  return vec_extract (a, 4);
+}
+int g5 (vector short a)
+{ 
+  return vec_extract (a, 5);
+}
+int g6 (vector short a)
+{ 
+  return vec_extract (a, 6);
+}
+int g7 (vector short a)
+{ 
+  return vec_extract (a, 7);
+}
+int g8 (vector short a)
+{ 
+  return vec_extract (a, 8);
+}
+int main1(void) __attribute__((noinline));
+int main1(void)
+{ 
+  int i;
+  /* Check vec_extract with a non constant element numbering */
+  for(i=0;i<10;i++)
+    { 
+      if (f(a, i) != (i&0x3))
+        abort ();
+    }
+  
+  /* Check vec_extract with a constant element numbering */
+  if (f0(a) != 0)
+    abort ();
+  if (f1(a) != 1)
+    abort ();
+  if (f2(a) != 2)
+    abort ();
+  if (f3(a) != 3)
+    abort ();
+  /* Check that vec_extract works with a constant element higher than
+     the number of elements.  */
+  if (f4(a) != 0)
+    abort ();
+
+  /* Check vec_extract with a non constant element numbering */
+  for(i=0;i<10;i++)
+    {
+      if (g(b, i) != (i&0x7))
+        abort ();
+    }
+  
+  /* Check vec_extract with a constant element numbering */
+  if (g0(b) != 0)
+    abort ();
+  if (g1(b) != 1)
+    abort ();
+  if (g2(b) != 2)
+    abort ();
+  if (g3(b) != 3)
+    abort ();
+  if (g4(b) != 4)
+    abort ();
+  if (g5(b) != 5)
+    abort ();
+  if (g6(b) != 6)
+    abort ();
+  if (g7(b) != 7)
+    abort ();
+  /* Check that vec_extract works with a constant element higher than
+     the number of elements.  */
+  if (g8(b) != 0)
+    abort ();
+  
+  return 0;
+}
+
+int main(void)
+{ 
+  return main1 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c
new file mode 100644
index 000000000..b941ab186
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+/* Test the vec_splats and vec_promote VMX intrinsics.  */
+#include <altivec.h>
+    
+extern void abort (void);
+        
+vector int a = {0, 0, 0, 0};
+int main1(int t) __attribute__((noinline));
+int main1(int t)
+{ 
+  int i;
+  vector int b = vec_splats(0);
+  if (__builtin_memcmp (&a, &b, sizeof(vector int)))
+    abort ();
+  
+  b = vec_splats(t);
+  if (__builtin_memcmp (&a, &b, sizeof(vector int)))
+    abort ();
+  
+  b = vec_promote(0, 1);
+  if (vec_extract (b, 1) != 0)
+    abort ();
+  
+  b = vec_promote(t, t);
+  if (vec_extract (b, t) != 0)
+    abort ();
+  
+  return 0;
+} 
+    
+int main(void)
+{ 
+  return main1 (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c
new file mode 100644
index 000000000..c694691d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c
@@ -0,0 +1,42 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Test the vec_splats and vec_promote VMX intrinsics.  */
+#include <altivec.h>
+    
+extern void abort (void);
+        
+vector int a[] = {{0, 0, 0, 0}, {1,0,0,0}, {1,2,0,0},{1,2,3,0},{1,2,3,4},{5,2,3,4},{5,6,3,4}};
+vector int c = {0,6,3,4};
+vector int d = {0,0,3,4};
+int main1(int t) __attribute__((noinline));
+int main1(int t)
+{ 
+  int i;
+  vector int b = vec_splats(0);
+  for(i = 0;i<sizeof(a)/sizeof(a[0])-1;i++)
+    { 
+	if (__builtin_memcmp (&b, &a[i], sizeof(vector int)))
+          abort ();
+        b = vec_insert(i+1, b, i);
+    } 
+  if (__builtin_memcmp (&b, &a[i], sizeof(vector int)))
+    abort ();
+  
+  b = vec_insert(0, b, 0);
+  if (__builtin_memcmp (&b, &c, sizeof(vector int)))
+    abort ();
+  
+  b = vec_insert(0, b, 1);
+  if (__builtin_memcmp (&b, &d, sizeof(vector int)))
+    abort ();
+  
+  return 0;
+} 
+  
+int main(void)
+{
+  return main1 (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c
new file mode 100644
index 000000000..95f109d1a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Basic test for the new VMX intrinsics and error messages.  */
+#include <altivec.h>
+
+int main(int argc, char **argv)
+{
+vector float t;
+    vec_promote();                      /* { dg-error "vec_promote only accepts 2" } */
+    vec_promote(1.0f);                  /* { dg-error "vec_promote only accepts 2" } */
+    vec_promote(1.0f, 2, 3);            /* { dg-error "vec_promote only accepts 2" } */
+    vec_extract ();                     /* { dg-error "vec_extract only accepts 2" } */
+    vec_extract (t);                    /* { dg-error "vec_extract only accepts 2" } */
+    vec_extract (t, 2);
+    vec_extract (t, 2, 5, 6);           /* { dg-error "vec_extract only accepts 2" } */
+    vec_splats ();                      /* { dg-error "vec_splats only accepts 1" } */
+    vec_splats (t, 3);                  /* { dg-error "vec_splats only accepts 1" } */
+    vec_insert ();                      /* { dg-error "vec_insert only accepts 3" } */
+    vec_insert (t);                     /* { dg-error "vec_insert only accepts 3" } */
+    vec_insert (t, 3);                  /* { dg-error "vec_insert only accepts 3" } */
+    vec_insert (t, 3, 2, 4, 6, 6);      /* { dg-error "vec_insert only accepts 3" } */
+    return 0;
+}  
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c
new file mode 100644
index 000000000..5d62f18e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c
@@ -0,0 +1,12 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
+#include <altivec.h>
+
+/* This used to ICE with reloading of a constant address. */
+
+vector float f(void)
+{
+  vector float * a = (void*)16;
+  return vec_lvlx (0, a);
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c
new file mode 100644
index 000000000..ae7769400
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c
@@ -0,0 +1,28 @@
+/* { dg-do compile  } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "vor" 2 } } */
+#include <altivec.h>
+
+/* Make sure that lvlx and lvrx are not combined into one insn and
+   we still get a vor. */
+
+vector unsigned char
+lvx_float (long off, float *p)
+{
+    vector unsigned char l, r;
+
+    l = (vector unsigned char) vec_lvlx (off, p);
+    r = (vector unsigned char) vec_lvrx (off, p);
+    return vec_or(l, r);
+}
+
+vector unsigned char
+lvxl_float (long off, float *p)
+{
+    vector unsigned char l, r;
+
+    l = (vector unsigned char) vec_lvlxl (off, p);
+    r = (vector unsigned char) vec_lvrxl (off, p);
+    return vec_or(l, r);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c
new file mode 100644
index 000000000..dda5eb0c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c
@@ -0,0 +1,57 @@
+/* { dg-do run { target { powerpc*-*-* && cell_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! cell_hw } } } } */
+/* { dg-require-effective-target powerpc_ppu_ok } */
+/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
+#include <altivec.h>
+#include <string.h>
+
+extern void abort (void);
+
+typedef short int sint16;
+typedef signed char int8;
+
+int main1(void) __attribute__((noinline));
+int main1(void)
+{
+    sint16 test_vector[4] = { 1678, -2356, 19246, -17892 };
+    int8 test_dst[128] __attribute__(( aligned( 16 )));
+    float test_out[4] __attribute__(( aligned( 16 )));
+    int p;
+
+    for( p = 0; p < 24; ++p )
+    {
+        memset( test_dst, 0, 128 );
+        memcpy( &test_dst[p], test_vector, 8 );
+        {
+            vector float VR, VL, V;
+   /* load the righthand section of the misaligned vector */
+            VR = (vector float) vec_lvrx( 8, &test_dst[p] );
+            VL = (vector float) vec_lvlx( 0, &test_dst[p] );
+   /* Vector Shift Left Double by Octet Immediate, move the right hand section into the bytes */
+            VR = vec_vsldoi( VR, VR, 2 << 2 ); 
+   /* or those two together */
+            V = vec_vor( VL, VR );
+   /* sign extend */
+            V = (vector float) vec_vupkhsh((vector bool short)V );
+   /* fixed to float by S16_SHIFT_BITS bits */
+            V = (vector float) vec_vcfsx ((vector signed int)V, 5 ); 
+
+            vec_stvx( V, 0, &test_out[0] );
+            if (test_out[0] != 52.437500)
+                abort ();
+            if (test_out[1] != -73.625000)
+                abort ();
+            if (test_out[2] != 601.437500)
+                abort ();
+            if (test_out[3] != -559.125000)
+                abort ();
+        }
+    }
+return 0;
+}
+
+
+int main(void)
+{
+  return main1();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-consts.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
new file mode 100644
index 000000000..2afd13fa8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
@@ -0,0 +1,253 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -O2" } */
+
+/* Check that "easy" AltiVec constants are correctly synthesized.  */
+
+extern void abort (void);
+
+typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
+typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
+typedef __attribute__ ((vector_size (16))) unsigned int v4si;
+
+typedef __attribute__((aligned(16))) char c16[16];
+typedef __attribute__((aligned(16))) short s8[8];
+typedef __attribute__((aligned(16))) int i4[4];
+
+#define V16QI(V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16)	\
+  v16qi v = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16};	\
+  static c16 w = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16}; \
+  check_v16qi (v, w);
+
+#define V8HI(V1,V2,V3,V4,V5,V6,V7,V8)		\
+  v8hi v = {V1,V2,V3,V4,V5,V6,V7,V8};		\
+  static s8 w = {V1,V2,V3,V4,V5,V6,V7,V8};	\
+  check_v8hi (v, w);
+
+#define V4SI(V1,V2,V3,V4)	\
+  v4si v = {V1,V2,V3,V4};	\
+  static i4 w = {V1,V2,V3,V4};	\
+  check_v4si (v, w);
+
+
+/* Use three different check functions for each mode-instruction pair.
+   The callers have no typecasting and no addressable vectors, to make
+   the test more robust.  */
+
+void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+void __attribute__ ((noinline)) check_v8hi (v8hi v1, short *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+void __attribute__ ((noinline)) check_v4si (v4si v1, int *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+
+/* V16QI tests.  */
+
+void v16qi_vspltisb ()
+{
+  V16QI (15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15);
+}
+
+void v16qi_vspltisb_neg ()
+{
+  V16QI (-5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5);
+}
+
+void v16qi_vspltisb_addself ()
+{
+  V16QI (30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30);
+}
+
+void v16qi_vspltisb_neg_addself ()
+{
+  V16QI (-24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24);
+}
+
+void v16qi_vspltish ()
+{
+  V16QI (0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15);
+}
+
+void v16qi_vspltish_addself ()
+{
+  V16QI (0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30);
+}
+
+void v16qi_vspltish_neg ()
+{
+  V16QI (-1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5);
+}
+
+void v16qi_vspltisw ()
+{
+  V16QI (0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15);
+}
+
+void v16qi_vspltisw_addself ()
+{
+  V16QI (0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30);
+}
+
+void v16qi_vspltisw_neg ()
+{
+  V16QI (-1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5);
+}
+
+
+/* V8HI tests. */
+
+void v8hi_vspltisb ()
+{
+  V8HI (0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F);
+}
+
+void v8hi_vspltisb_addself ()
+{
+  V8HI (0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E);
+}
+
+void v8hi_vspltisb_neg ()
+{
+  V8HI (0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB);
+}
+
+void v8hi_vspltish ()
+{
+  V8HI (15, 15, 15, 15, 15, 15, 15, 15);
+}
+
+void v8hi_vspltish_neg ()
+{
+  V8HI (-5, -5, -5, -5, -5, -5, -5, -5);
+}
+
+void v8hi_vspltish_addself ()
+{
+  V8HI (30, 30, 30, 30, 30, 30, 30, 30);
+}
+
+void v8hi_vspltish_neg_addself ()
+{
+  V8HI (-24, -24, -24, -24, -24, -24, -24, -24);
+}
+
+void v8hi_vspltisw ()
+{
+  V8HI (0, 15, 0, 15, 0, 15, 0, 15);
+}
+
+void v8hi_vspltisw_addself ()
+{
+  V8HI (0, 30, 0, 30, 0, 30, 0, 30);
+}
+
+void v8hi_vspltisw_neg ()
+{
+  V8HI (-1, -5, -1, -5, -1, -5, -1, -5);
+}
+
+/* V4SI tests. */
+
+void v4si_vspltisb ()
+{
+  V4SI (0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F);
+}
+
+void v4si_vspltisb_addself ()
+{
+  V4SI (0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E);
+}
+
+void v4si_vspltisb_neg ()
+{
+  V4SI (0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB);
+}
+
+void v4si_vspltish ()
+{
+  V4SI (0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F);
+}
+
+void v4si_vspltish_addself ()
+{
+  V4SI (0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E);
+}
+
+void v4si_vspltish_neg ()
+{
+  V4SI (0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB);
+}
+
+void v4si_vspltisw ()
+{
+  V4SI (15, 15, 15, 15);
+}
+
+void v4si_vspltisw_neg ()
+{
+  V4SI (-5, -5, -5, -5);
+}
+
+void v4si_vspltisw_addself ()
+{
+  V4SI (30, 30, 30, 30);
+}
+
+void v4si_vspltisw_neg_addself ()
+{
+  V4SI (-24, -24, -24, -24);
+}
+
+
+
+int main ()
+{
+  v16qi_vspltisb ();
+  v16qi_vspltisb_neg ();
+  v16qi_vspltisb_addself ();
+  v16qi_vspltisb_neg_addself ();
+  v16qi_vspltish ();
+  v16qi_vspltish_addself ();
+  v16qi_vspltish_neg ();
+  v16qi_vspltisw ();
+  v16qi_vspltisw_addself ();
+  v16qi_vspltisw_neg ();
+
+  v8hi_vspltisb ();
+  v8hi_vspltisb_addself ();
+  v8hi_vspltisb_neg ();
+  v8hi_vspltish ();
+  v8hi_vspltish_neg ();
+  v8hi_vspltish_addself ();
+  v8hi_vspltish_neg_addself ();
+  v8hi_vspltisw ();
+  v8hi_vspltisw_addself ();
+  v8hi_vspltisw_neg ();
+
+  v4si_vspltisb ();
+  v4si_vspltisb_addself ();
+  v4si_vspltisb_neg ();
+  v4si_vspltish ();
+  v4si_vspltish_addself ();
+  v4si_vspltish_neg ();
+  v4si_vspltisw ();
+  v4si_vspltisw_neg ();
+  v4si_vspltisw_addself ();
+  v4si_vspltisw_neg_addself ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "lvx" { target { ! powerpc*le-*-* } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-macros.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-macros.c
new file mode 100644
index 000000000..c07eaa36a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-macros.c
@@ -0,0 +1,64 @@
+/* Copyright (C) 2007 Free Software Foundation, Inc.  */
+
+/* { dg-do preprocess } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Conditional macros should not be expanded by pragmas.  */
+#pragma __vector
+_Pragma ("__vector")
+
+/* Redefinition of conditional macros.  */
+/* No warning should be generated.  */
+
+#define __vector __new_vector
+#define __pixel __new_pixel
+#define __bool __new_bool
+#define vector new_vector
+#define pixel new_pixel
+#define bool new_bool
+
+/* Definition of conditional macros.  */
+/* No warning should be generated.  */
+
+#undef __vector
+#define __vector __new_vector
+
+#undef __pixel
+#define __pixel __new_pixel
+
+#undef __bool
+#define __bool __new_bool
+
+#undef vector
+#define vector new_vector
+
+#undef pixel
+#define pixel new_pixel
+
+#undef bool
+#define bool new_bool
+
+/* Re-definition of "unconditional" macros.  */
+/* Warnings should be generated as usual.  */
+
+#define __vector	__newer_vector
+#define __pixel		__newer_pixel
+#define __bool		__newer_bool
+#define vector		newer_vector
+#define pixel		newer_pixel
+#define bool		newer_bool
+
+/* { dg-warning "redefined" "__vector redefined"  { target *-*-* } 45 } */
+/* { dg-warning "redefined" "__pixel redefined"   { target *-*-* } 46 } */
+/* { dg-warning "redefined" "__bool redefined"    { target *-*-* } 47 } */
+/* { dg-warning "redefined" "vector redefined"    { target *-*-* } 48 } */
+/* { dg-warning "redefined" "pixel redefined"     { target *-*-* } 49 } */
+/* { dg-warning "redefined" "bool redefined"      { target *-*-* } 50 } */
+
+/* { dg-message "location of the previous"  "prev __vector defn"  { target *-*-* } 25 } */
+/* { dg-message "location of the previous"  "prev __pixel defn"   { target *-*-* } 28 } */
+/* { dg-message "location of the previous"  "prev __bool defn"    { target *-*-* } 31 } */
+/* { dg-message "location of the previous"  "prev vector defn"    { target *-*-* } 34 } */
+/* { dg-message "location of the previous"  "prev pixel defn"     { target *-*-* } 37 } */
+/* { dg-message "location of the previous"  "prev bool defn"      { target *-*-* } 40 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c
new file mode 100644
index 000000000..c3cf67e44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O -maltivec -mno-vsx" } */
+
+typedef unsigned char V __attribute__((vector_size(16)));
+
+V b1(V x)
+{
+  return __builtin_shuffle(x, (V){ 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, });
+}
+
+V b2(V x)
+{
+  return __builtin_shuffle(x, (V){ 2,3,2,3, 2,3,2,3, 2,3,2,3, 2,3,2,3, });
+}
+
+V b4(V x)
+{
+  return __builtin_shuffle(x, (V){ 4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7, });
+}
+
+V h1(V x, V y)
+{
+  return __builtin_shuffle(x, y,
+	(V){ 0, 16,  1, 17,  2, 18,  3, 19,  4, 20,  5, 21,  6, 22,  7, 23 });
+}
+
+V h2(V x, V y)
+{
+  return __builtin_shuffle(x, y,
+	(V){ 0,  1, 16, 17,  2,  3, 18, 19,  4,  5, 20, 21,  6,  7, 22, 23 });
+}
+
+V h4(V x, V y)
+{
+  return __builtin_shuffle(x, y,
+	(V){ 0,  1,  2,  3, 16, 17, 18, 19,  4,  5,  6,  7, 20, 21, 22, 23 });
+}
+
+V l1(V x, V y)
+{
+  return __builtin_shuffle(x, y,
+	(V){ 8, 24,  9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 });
+}
+
+V l2(V x, V y)
+{
+  return __builtin_shuffle(x, y,
+	(V){ 8,  9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 });
+}
+
+V l4(V x, V y)
+{
+  return __builtin_shuffle(x, y,
+	(V){ 8,  9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 });
+}
+
+/* { dg-final { scan-assembler-not "vperm" } } */
+/* { dg-final { scan-assembler "vspltb" } } */
+/* { dg-final { scan-assembler "vsplth" } } */
+/* { dg-final { scan-assembler "vspltw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-2.c
new file mode 100644
index 000000000..1b90bb956
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O -maltivec -mno-vsx" } */
+
+typedef unsigned short V __attribute__((vector_size(16)));
+
+V f2(V x)
+{
+  return __builtin_shuffle(x, (V){ 1,1,1,1, 1,1,1,1, });
+}
+
+V f4(V x)
+{
+  return __builtin_shuffle(x, (V){ 2,3,2,3, 2,3,2,3, });
+}
+
+/* { dg-final { scan-assembler-not "vperm" } } */
+/* { dg-final { scan-assembler "vsplth" } } */
+/* { dg-final { scan-assembler "vspltw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c
new file mode 100644
index 000000000..d0b671eac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */
+/* { dg-options "-O -maltivec -mno-vsx" } */
+
+typedef unsigned char V __attribute__((vector_size(16)));
+
+V p2(V x, V y)
+{
+  return __builtin_shuffle(x, y,
+	(V){ 1,  3,  5,  7,  9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 });
+
+}
+
+V p4(V x, V y)
+{
+  return __builtin_shuffle(x, y,
+	(V){ 2,  3,  6,  7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 });
+}
+
+/* { dg-final { scan-assembler-not "vperm" } } */
+/* { dg-final { scan-assembler "vpkuhum" } } */
+/* { dg-final { scan-assembler "vpkuwum" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-4.c
new file mode 100644
index 000000000..9598edfb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-perm-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O -maltivec -mno-vsx" } */
+
+typedef unsigned int V __attribute__((vector_size(16)));
+
+V f4(V x)
+{
+  return __builtin_shuffle(x, (V){ 1,1,1,1, });
+}
+
+/* { dg-final { scan-assembler-not "vperm" } } */
+/* { dg-final { scan-assembler "vspltw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c
new file mode 100644
index 000000000..a7b81bbad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-pr22085.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -fpreprocessed" } */
+
+/* Program to test AltiVec with -fpreprocessed.  */
+int foo(__attribute__((altivec(vector__))) float x,
+        __attribute__((altivec(vector__))) float y)
+{
+  if (__builtin_vec_vcmpeq_p (2, (x), (y)))
+    return 3245;
+  else
+    return 12;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-splat.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-splat.c
new file mode 100644
index 000000000..91ab72d78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-splat.c
@@ -0,0 +1,49 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -O2" } */
+
+/* Testcase by Richard Guenther and Steven Bosscher.
+   Check that "easy" AltiVec constants are correctly synthesized
+   if they need to be reloaded.  */
+
+typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
+typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
+typedef __attribute__ ((vector_size (16))) unsigned int v4si;
+
+#define REGLIST								\
+  "77",  "78",  "79",  "80",  "81",  "82",  "83",  "84",  "85",  "86",	\
+  "87",  "88",  "89",  "90",  "91",  "92",  "93",  "94",  "95",  "96",	\
+  "97",  "98",  "99", "100", "101", "102", "103", "104", "105", "106",	\
+ "107", "108"
+
+
+#define TEST(a, result, b)				\
+  void a##_##b (int h)					\
+  {							\
+    volatile a tmp;					\
+    while (h-- > 0)					\
+      {							\
+        asm ("" : : : REGLIST);				\
+        tmp = (a) (result) __builtin_altivec_##b (5);	\
+      }							\
+  }							\
+							\
+  void a##_##b##_neg (int h)				\
+  {							\
+    volatile a tmp;					\
+    while (h-- > 0)					\
+      {							\
+        asm ("" : : : REGLIST);				\
+        tmp = (a) (result) __builtin_altivec_##b (-5);	\
+      }							\
+  }
+
+TEST(v16qi, v16qi, vspltisb)
+TEST(v16qi, v8hi, vspltish)
+TEST(v16qi, v4si, vspltisw)
+TEST(v8hi, v16qi, vspltisb)
+TEST(v8hi, v8hi, vspltish)
+TEST(v8hi, v4si, vspltisw)
+TEST(v4si, v16qi, vspltisb)
+TEST(v4si, v8hi, vspltish)
+TEST(v4si, v4si, vspltisw)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c
new file mode 100644
index 000000000..9096892ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c
@@ -0,0 +1,91 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Valid AltiVec vector types should be accepted with no warnings.  */
+
+__vector char vc;
+__vector unsigned char vuc;
+__vector signed char vsc;
+__vector __bool char vbc;
+__vector short vh;
+__vector signed short vsh;
+__vector unsigned short vuh;
+__vector short int vhi;
+__vector signed short int vshi;
+__vector unsigned short int vuhi;
+__vector __bool short vbh;
+__vector __bool short int vbhi;
+__vector int vi;
+__vector unsigned int vui;
+__vector signed int vsi;
+__vector __bool int vbi;
+__vector unsigned vuj;
+__vector signed vsj;
+__vector __bool vbj;
+__vector float vf;
+__vector _Bool vb;
+
+/* These should be rejected as invalid AltiVec types.  */
+
+__vector long long vll;			/* { dg-error "AltiVec types" "" } */
+__vector unsigned long long vull;	/* { dg-error "AltiVec types" "" } */
+__vector signed long long vsll;		/* { dg-error "AltiVec types" "" } */
+__vector __bool long long vbll;		/* { dg-error "AltiVec types" "" } */
+__vector long long int vlli;		/* { dg-error "AltiVec types" "" } */
+__vector unsigned long long int vulli;	/* { dg-error "AltiVec types" "" } */
+__vector signed long long int vslli;	/* { dg-error "AltiVec types" "" } */
+__vector __bool long long int vblli;	/* { dg-error "AltiVec types" "" } */
+__vector double vd1;			/* { dg-error "AltiVec types" "" } */
+__vector long double vld;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex float vcf;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex double vcd;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex long double vcld;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex signed char vcsc;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned char vcuc;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex short vcss;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned short vcus;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex int vcsi;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned int vcui;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex long vcsl;		/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned long vcul;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex long long vcsll;	/* { dg-error "AltiVec types" "" } */
+__vector _Complex unsigned long long vcull; /* { dg-error "AltiVec types" "" } */
+__vector __complex float v_cf;		/* { dg-error "AltiVec types" "" } */
+__vector __complex double v_cd;		/* { dg-error "AltiVec types" "" } */
+__vector __complex long double v_cld;	/* { dg-error "AltiVec types" "" } */
+__vector __complex signed char v_csc;	/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned char v_cuc;	/* { dg-error "AltiVec types" "" } */
+__vector __complex short v_css;		/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned short v_cus; /* { dg-error "AltiVec types" "" } */
+__vector __complex int v_csi;		/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned int v_cui;	/* { dg-error "AltiVec types" "" } */
+__vector __complex long v_csl;		/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned long v_cul;	/* { dg-error "AltiVec types" "" } */
+__vector __complex long long v_csll;	/* { dg-error "AltiVec types" "" } */
+__vector __complex unsigned long long v_cull; /* { dg-error "AltiVec types" "" } */
+
+/* These should be rejected because the component types are invalid.  We
+   don't care about the actual error messages here.  */
+
+__vector __bool unsigned char vbuc;	/* { dg-error "" "" } */
+__vector __bool signed char vbsc;	/* { dg-error "" "" } */
+__vector __bool unsigned short vbuh;	/* { dg-error "" "" } */
+__vector __bool signed short vbsh;	/* { dg-error "" "" } */
+__vector __bool unsigned int vbui;	/* { dg-error "" "" } */
+__vector __bool signed int vbsi;	/* { dg-error "" "" } */
+__vector __bool unsigned vbuj;		/* { dg-error "" "" } */
+__vector __bool signed vbsj;		/* { dg-error "" "" } */
+__vector signed float vsf;		/* { dg-error "" "" } */
+__vector unsigned float vuf;		/* { dg-error "" "" } */
+__vector short float vsf;		/* { dg-error "" "" } */
+__vector signed double vsd;		/* { dg-error "" "" } */
+__vector unsigned double vud;		/* { dg-error "" "" } */
+__vector short double vsd;		/* { dg-error "" "" } */
+__vector __bool float vbf;		/* { dg-error "" "" } */
+__vector __bool double vbd;		/* { dg-error "" "" } */
+__vector __bool short float blf;	/* { dg-error "" "" } */
+__vector __bool short double vlbd;	/* { dg-error "" "" } */
+
+/* { dg-message "note: previous" "prev vsf" { target *-*-* } 79 } */
+/* { dg-message "note: previous" "prev vsd" { target *-*-* } 82 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c
new file mode 100644
index 000000000..cee6c8f26
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* These should get warnings for 32-bit code.  */
+
+__vector long vl;			/* { dg-warning "deprecated" "" } */
+__vector unsigned long vul;		/* { dg-warning "deprecated" "" } */
+__vector signed long vsl;		/* { dg-warning "deprecated" "" } */
+__vector __bool long int vbli;		/* { dg-warning "deprecated" "" } */
+__vector long int vli;			/* { dg-warning "deprecated" "" } */
+__vector unsigned long int vuli;	/* { dg-warning "deprecated" "" } */
+__vector signed long int vsli;		/* { dg-warning "deprecated" "" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c
new file mode 100644
index 000000000..ea371ce77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* These should be rejected for 64-bit code.  */
+
+__vector long vl;			/* { dg-error "invalid for 64" "" } */
+__vector unsigned long vul;		/* { dg-error "invalid for 64" "" } */
+__vector signed long vsl;		/* { dg-error "invalid for 64" "" } */
+__vector __bool long int vbli;		/* { dg-error "invalid for 64" "" } */
+__vector long int vli;			/* { dg-error "invalid for 64" "" } */
+__vector unsigned long int vuli;	/* { dg-error "invalid for 64" "" } */
+__vector signed long int vsli;		/* { dg-error "invalid for 64" "" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c
new file mode 100644
index 000000000..52fa91453
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-types-4.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-warn-altivec-long -mno-vsx" } */
+
+/* These should not get warnings for 32-bit code when the warning is
+   disabled.  */
+
+__vector long vl;
+__vector unsigned long vul;
+__vector signed long vsl;
+__vector __bool long int vbli;
+__vector long int vli;
+__vector unsigned long int vuli;
+__vector signed long int vsli;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c
new file mode 100644
index 000000000..1349ae590
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c
@@ -0,0 +1,82 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */
+
+#include <stdarg.h>
+
+extern void exit (int);
+extern void abort (void);
+
+#define vector __attribute__((vector_size (16)))
+
+const vector unsigned int v1 = {10,11,12,13};
+const vector unsigned int v2 = {20,21,22,23};
+const vector unsigned int v3 = {30,31,32,33};
+const vector unsigned int v4 = {40,41,42,43};
+
+void foo(vector unsigned int a, ...)
+{
+  va_list args;
+  vector unsigned int v;
+
+  va_start (args, a);
+  if (memcmp (&a, &v1, sizeof (v)) != 0)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v2, sizeof (v)) != 0)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v3, sizeof (v)) != 0)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v4, sizeof (v)) != 0)
+    abort ();
+  va_end (args);
+}
+
+void bar(vector unsigned int a, ...)
+{
+  va_list args;
+  vector unsigned int v;
+  int b;
+
+  va_start (args, a);
+  if (memcmp (&a, &v1, sizeof (v)) != 0)
+    abort ();
+  b = va_arg (args, int);
+  if (b != 2)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v2, sizeof (v)) != 0)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v3, sizeof (v)) != 0)
+    abort ();
+  va_end (args);
+}
+
+
+int main1(void)
+{
+  /* In this call, in the Darwin ABI, the first argument goes into v2
+     the second one into r9-r10 and memory,
+     and the next two in memory.  */
+  foo ((vector unsigned int){10,11,12,13},
+       (vector unsigned int){20,21,22,23},
+       (vector unsigned int){30,31,32,33},
+       (vector unsigned int){40,41,42,43});
+  /* In this call, in the Darwin ABI, the first argument goes into v2
+     the second one into r9, then r10 is reserved and
+     there are two words of padding in memory, and the next two arguments
+     go after the padding.  */
+  bar ((vector unsigned int){10,11,12,13}, 2,
+       (vector unsigned int){20,21,22,23},
+       (vector unsigned int){30,31,32,33});
+  return 0;
+}
+
+int main (void)
+{
+  return main1 ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
new file mode 100644
index 000000000..3689f9749
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c
@@ -0,0 +1,605 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+int printf(const char * , ...);
+extern void abort();
+
+void foo(char *bS, char *bS_edge, int field_MBAFF, int top){
+  char intra[16]       __attribute__ ((aligned(16)));
+  signed short mv_const[8] __attribute__((aligned(16)));
+  
+  vector signed short v_three, v_ref_mask00, v_ref_mask01, v_vec_maskv, v_vec_maskh;
+  vector unsigned char v_permv, v_permh, v_bS, v_bSh, v_bSv, v_cbp_maskv, v_cbp_maskvn, v_cbp_maskh, v_cbp_maskhn, v_intra_maskh, v_intra_maskv, v_intra_maskhn, v_intra_maskvn;
+  vector unsigned char tmp7, tmp8, tmp9, tmp10, v_c1, v_cbp1, v_cbp2, v_pocl, v_poch;
+  vector signed short v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
+  vector signed short idx0;
+  vector signed short tmp00, tmp01, tmp02, tmp03;
+  vector unsigned char v_zero   = (vector unsigned char) {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p'};
+  v_three  = (vector signed short) vec_ld (0, (vector signed short *) mv_const);
+
+  vector unsigned char v_coef_mask = vec_ld(0, (vector unsigned char *)mv_const);
+  vector unsigned char v_coef_mask_hi = vec_splat(v_coef_mask, 0);
+  vector unsigned char v_coef_mask_lo = vec_splat(v_coef_mask, 1);
+  v_coef_mask = vec_sld(v_coef_mask_hi, v_coef_mask_lo, 8);
+  vector unsigned char v_bit_mask = vec_sub(vec_splat_u8(7), vec_lvsl(0, (unsigned char *)0));
+  v_bit_mask  = vec_sld(vec_sld(v_bit_mask, v_bit_mask, 8), v_bit_mask, 8);
+  v_bit_mask  = vec_sl(vec_splat_u8(1), v_bit_mask);
+  tmp5        = (vector signed short) vec_and(v_coef_mask, v_bit_mask);
+
+  intra[0] = 1;
+  tmp8     = vec_ld (0, (vector unsigned char *) intra);
+  tmp9     = vec_ld (0, (vector unsigned char *) mv_const);
+  tmp10    = vec_ld (0, (vector unsigned char *) mv_const);
+  v_permv  = vec_ld (0, (vector unsigned char *) mv_const);
+  v_permh  = vec_ld (0, (vector unsigned char *) mv_const);
+  tmp6     = vec_ld (0, (vector signed short *) mv_const);
+
+  tmp8     = vec_splat((vector unsigned char) tmp8, 0);
+  tmp9     = vec_splat((vector unsigned char) tmp9, 12);
+  tmp10    = vec_splat((vector unsigned char) tmp10, 12);
+  tmp9     = vec_sld ((vector unsigned char) tmp9,(vector unsigned char) tmp8, 12);
+  tmp10    = vec_sld ((vector unsigned char) tmp10, (vector unsigned char) tmp8, 12);
+  v_intra_maskv  = vec_or (tmp9, tmp8);
+  v_intra_maskh  = vec_or (tmp10, tmp8);
+  v_intra_maskv  = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskv, (vector unsigned char) v_zero);
+  v_intra_maskh  = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskh, (vector unsigned char) v_zero);
+
+  tmp9   = vec_lvsl (4 + (top<<2), (unsigned char *) 0x0);
+  v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9);
+  v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permv);
+  v_cbp1 = (vector unsigned char) vec_sld  ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12);
+  v_cbp_maskv = vec_or (v_cbp1, v_cbp2);
+
+  tmp9   = vec_lvsl (12 + (top<<2), (unsigned char *) 0x0);
+  v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9);
+  v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permh);
+  v_cbp1 = (vector unsigned char) vec_sld  ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12);
+  v_cbp_maskh = vec_or (v_cbp1, v_cbp2);
+
+  v_cbp_maskv = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero);
+  v_cbp_maskh = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero);
+
+  intra[0]  =0; 
+  intra[1]  =1;
+  intra[2]  =2;
+  intra[3]  =3;
+  intra[4]  =4;
+  intra[5]  = 5;
+  intra[6]  =6;
+  intra[7]  =7;
+  intra[8]  =8;
+  intra[9]  =9;
+  intra[10] =9;
+  intra[11] =9;
+  intra[12] = 0xff;
+
+  idx0   = vec_ld (0, (signed short *) intra);
+  
+  v_c1   = (vector unsigned char)  {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'};
+
+  if (field_MBAFF){
+    v0   = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1);
+    idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1);
+
+    v1   = vec_sld (v0, v0, 15);
+    v1   = (vector signed short) vec_pack (v1, v0);
+    
+    v2   = vec_sld (v1, v1, 2);
+    v3   = vec_sld (v1, v1, 10);
+    
+    v4   = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v2);
+    v5   = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v3);
+    v6   = (vector signed short) vec_cmpeq ((vector signed char) v2, (vector signed char) v3);
+  }
+  else  {
+    v4 = v5 = v6 = (vector signed short) vec_nor (v_zero, v_zero);
+  }
+
+  tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
+  v_c1   = vec_mergeh ((vector unsigned char) v_zero, v_c1);
+  tmp1   = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); 
+
+  v_pocl = vec_ld (0, (vector unsigned char *) mv_const);
+  v_poch = vec_ld (0, (vector unsigned char *) mv_const);
+  tmp2   = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1);      
+
+  v_pocl = vec_ld (0,  (vector unsigned char *) mv_const);
+  v_poch = vec_ld (16, (vector unsigned char *) mv_const);
+  tmp1   = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1);
+  tmp1   = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0});
+
+  tmp3   = (vector signed short) vec_splat ((vector unsigned char) idx0, 12);
+  v_c1   = (vector unsigned char) vec_nor (v_zero, v_zero);
+  tmp0   = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1);
+  tmp1   = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0);
+
+  tmp2   = vec_sld (tmp1, tmp1, 15);
+  tmp1   = (vector signed short) vec_pack (tmp2, tmp1);
+  
+  tmp2   = vec_sld (tmp1, tmp1, 2);
+  tmp3   = vec_sld (tmp1, tmp1, 10);
+
+  tmp0   = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2);
+  tmp4   = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3);
+  tmp1   = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3);
+  tmp0   = vec_and (tmp0, v4);
+  tmp4   = vec_and (tmp4, v5);
+  tmp1   = vec_and (tmp1, v6);
+  tmp2   = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8);
+  tmp3   = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8);
+  tmp5   = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8);
+  tmp0   = vec_and (tmp0, tmp2);
+  tmp4   = vec_and (tmp4, tmp3);
+  tmp1   = vec_and (tmp1, tmp5);
+  v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1);
+  v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1);
+  v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00);
+  v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01);
+  
+  v0     = vec_ld (0,  (vector signed short *) mv_const);
+  v1     = vec_ld (16, (vector signed short *) mv_const);
+  v4     = vec_ld (64, (vector signed short *) mv_const);
+  v5     = vec_ld (80, (vector signed short *) mv_const);
+  v8     = vec_ld (0,  (vector signed short *) mv_const);
+  v9     = vec_ld (16, (vector signed short *) mv_const);
+
+  tmp0   = (vector signed short) vec_perm ((vector unsigned char) v8, 
+		(vector unsigned char) v8, (vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15});
+  tmp1   = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp3   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp4   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp0   = (vector signed short) vec_perm ((vector unsigned char) v9, (vector unsigned char) v9, 
+			(vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15});
+  tmp1   = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp5   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp6   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 12);
+  tmp6   = vec_sld (tmp4, tmp4, 12);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp00  = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4);
+
+  tmp0   = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1);
+  tmp1   = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp3   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp4   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp0   = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5);
+  tmp1   = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp5   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp6   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 12);
+  tmp6   = vec_sld (tmp4, tmp4, 12);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp01  = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4);
+
+  v2     = vec_ld (32, (vector signed short *) mv_const);
+  v3     = vec_ld (48, (vector signed short *) mv_const);
+  v6     = vec_ld (96, (vector signed short *) mv_const);
+  v7     = vec_ld (112,(vector signed short *) mv_const);
+
+  tmp0   = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1);
+  tmp1   = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp3   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp4   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp0   = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5);
+  tmp1   = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp5   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp6   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 12);
+  tmp6   = vec_sld (tmp4, tmp4, 12);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp02  = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4);
+
+  tmp0   = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3);
+  tmp1   = (vector signed short) vec_mergel ((vector signed int) v2, (vector signed int) v3);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp3   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp4   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp0   = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7);
+  tmp1   = (vector signed short) vec_mergel ((vector signed int) v6, (vector signed int) v7);
+  tmp2   = vec_sld (tmp1, tmp1, 8);
+  tmp5   = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1));
+  tmp6   = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 12);
+  tmp6   = vec_sld (tmp4, tmp4, 12);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp03  = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4);
+
+  tmp0   = (vector signed short) vec_pack ((vector unsigned int) tmp00, (vector unsigned int) tmp01);
+  tmp1   = (vector signed short) vec_pack ((vector unsigned int) tmp02, (vector unsigned int) tmp03);
+  tmp2   = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1);
+  tmp3   = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1);
+  tmp4   = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3);
+  tmp5   = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3);
+  tmp4   = vec_and (v_ref_mask00, tmp4);
+  tmp5   = vec_and (v_ref_mask01, tmp5);
+
+  tmp0   = vec_nor (v_ref_mask00, v_ref_mask01);
+  tmp1   = vec_and (v_ref_mask00, v_ref_mask01);
+  tmp2   = vec_and (tmp4, tmp5);
+  tmp2   = vec_and (tmp2, tmp1);
+  tmp3   = vec_nor (tmp4, tmp5);
+  tmp3   = vec_nor (tmp3, tmp1);
+  v_vec_maskv = vec_or (tmp0, tmp2);
+  v_vec_maskv = vec_or (v_vec_maskv, tmp3);
+
+  intra[0]  = 1; 
+  intra[1]  = 1;
+  intra[2]  = 2;
+  intra[3]  = 3;
+  intra[4]  = 2;
+  intra[5]  = 2;
+  intra[6]  = 2;
+  intra[7]  = 1;
+  intra[8]  = 1;
+  intra[9]  = 5;
+  intra[10] = 5;
+  intra[11] = 5;
+  
+  intra[13] = 0;
+  intra[14] = 0;
+  intra[15] = 0;
+
+  idx0   = vec_ld (0, (signed short *) intra);
+  
+  v_c1   = (vector unsigned char)  {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'};
+
+  if (field_MBAFF){
+    v8   = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1);
+    idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1);
+
+    v9   = vec_sld (v8, v8, 15);
+    v9   = (vector signed short) vec_pack (v9, v8);
+    
+    v10  = vec_sld (v9, v9, 2);
+    v11  = vec_sld (v9, v9, 10);
+    
+    v8   = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v10);
+    v9   = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v11);
+    v10  = (vector signed short) vec_cmpeq ((vector signed char) v10, (vector signed char) v11);
+  }
+  else  {
+    v8 = v9 = v10 = (vector signed short) vec_nor (v_zero, v_zero);
+  }
+
+  tmp1   = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1);
+  
+if (1){
+	int m;
+	unsigned char toto2[16] __attribute__((aligned(16)));
+	
+	printf("vc1\n");
+	vec_st(v_c1, 0, (unsigned char *) toto2);
+	for (m=0; m<16;m++) {printf("%c ", toto2[m]);}
+	
+	printf("\nv_zero\n");
+	
+	vec_st (v_zero, 0, (unsigned char *) toto2);
+	for (m=0; m< 16; m++) {printf("%c ", toto2[m]);}
+	printf("\n");
+}
+
+  v_c1   = vec_mergeh ((vector unsigned char) v_zero, v_c1);
+  tmp1   = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); 
+
+if (1){
+	vector unsigned char vres = 
+        (vector unsigned char){'a','1','b','2','c','3','d','4','e','5','f','6','g','7','h','8'};
+	unsigned char toto2[16] __attribute__((aligned(16)));
+	int m;
+	
+	printf("vc1\n");
+	vec_st(v_c1, 0, (unsigned char *) toto2);
+	for (m=0; m<16;m++) {printf("%c ", toto2[m]);}
+	printf("\n");
+	if (!vec_all_eq (vres, v_c1))
+	  abort();
+}
+
+  v_pocl = vec_ld (32, (vector unsigned char *) mv_const);
+  v_poch = vec_ld (48, (vector unsigned char *) mv_const);
+  tmp2   = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1);      
+
+  v_pocl = vec_ld (0,  (vector unsigned char *) mv_const);
+  v_poch = vec_ld (16, (vector unsigned char *) mv_const);
+
+  tmp1   = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1);
+ 
+  tmp1   = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0});
+
+
+  tmp3   = (vector signed short) vec_splat ((vector unsigned char) idx0, 12);
+  v_c1   = (vector unsigned char) vec_nor (v_zero, v_zero);
+  tmp0   = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1);
+  tmp1   = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0);
+
+  tmp2   = vec_sld (tmp1, tmp1, 15);
+  tmp1   = (vector signed short) vec_pack (tmp2, tmp1);
+  
+
+  tmp2   = vec_sld (tmp1, tmp1, 2);
+  tmp3   = vec_sld (tmp1, tmp1, 10);
+
+  tmp0   = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2);
+  tmp4   = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3);
+  tmp1   = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3);
+  tmp0   = vec_and (tmp0, v8);
+  tmp4   = vec_and (tmp4, v9);
+  tmp1   = vec_and (tmp1, v10);
+  tmp2   = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8);
+  tmp3   = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8);
+  tmp5   = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8);
+  tmp0   = vec_and (tmp0, tmp2);
+  tmp4   = vec_and (tmp4, tmp3);
+  tmp1   = vec_and (tmp1, tmp5);
+  v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1);
+  v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1);
+  v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00);
+  v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01);
+  
+
+  v_permv= vec_ld (0, (vector unsigned char *) mv_const);
+  v8     = vec_ld (0,  (vector signed short *) mv_const);
+  v9     = vec_ld (16, (vector signed short *) mv_const);
+  tmp2   = vec_perm (v0, v0, v_permv);
+  tmp3   = vec_sub (vec_max (v8, v0), vec_min (v8, v0));
+  tmp4   = vec_sub (vec_max (v8, tmp2), vec_min (v8, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp2   = vec_perm (v2, v2, v_permv);
+  tmp5   = vec_sub (vec_max (v9, v2), vec_min (v9, v2));
+  tmp6   = vec_sub (vec_max (v9, tmp2), vec_min (v9, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp00  = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4);
+
+  tmp2   = vec_perm (v1, v1, v_permv);
+  tmp3   = vec_sub (vec_max (v0, v1), vec_min (v0, v1));
+  tmp4   = vec_sub (vec_max (v0, tmp2), vec_min (v0, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp2   = vec_perm (v3, v3, v_permv);
+  tmp5   = vec_sub (vec_max (v2, v3), vec_min (v2, v3));
+  tmp6   = vec_sub (vec_max (v2, tmp2), vec_min (v2, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp01  = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4);
+
+  tmp2   = vec_perm (v4, v4, v_permv);
+  tmp3   = vec_sub (vec_max (v1, v4), vec_min (v1, v4));
+  tmp4   = vec_sub (vec_max (v1, tmp2), vec_min (v1, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp2   = vec_perm (v6, v6, v_permv);
+  tmp5   = vec_sub (vec_max (v3, v6), vec_min (v3, v6));
+  tmp6   = vec_sub (vec_max (v3, tmp2), vec_min (v3, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp02  = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4);
+
+
+  tmp2   = vec_perm (v5, v5, v_permv);
+  tmp3   = vec_sub (vec_max (v4, v5), vec_min (v4, v5));
+  tmp4   = vec_sub (vec_max (v4, tmp2), vec_min (v4, tmp2));
+  tmp3   = (vector signed short) vec_cmpgt (tmp3, v_three); 
+  tmp4   = (vector signed short) vec_cmpgt (tmp4, v_three);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  
+  tmp2   = vec_perm (v7, v7, v_permv);
+  tmp5   = vec_sub (vec_max (v6, v7), vec_min (v6, v7));
+  tmp6   = vec_sub (vec_max (v6, tmp2), vec_min (v6, tmp2));
+  tmp5   = (vector signed short) vec_cmpgt (tmp5, v_three); 
+  tmp6   = (vector signed short) vec_cmpgt (tmp6, v_three);
+  tmp0   = vec_sld (tmp5, tmp5, 14);
+  tmp1   = vec_sld (tmp6, tmp6, 14);
+  tmp5   = vec_or (tmp0, tmp5);
+  tmp6   = vec_or (tmp1, tmp6);
+  
+  tmp3   = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5);
+  tmp4   = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6);
+  tmp5   = vec_sld (tmp3, tmp3, 14);
+  tmp6   = vec_sld (tmp4, tmp4, 14);
+  tmp3   = vec_or (tmp3, tmp5);
+  tmp4   = vec_or (tmp4, tmp6);
+  tmp03  = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4);
+
+  tmp0   = (vector signed short) vec_pack ((vector unsigned short) tmp00, (vector unsigned short) tmp01);
+  tmp1   = (vector signed short) vec_pack ((vector unsigned short) tmp02, (vector unsigned short) tmp03);
+  tmp2   = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1);
+  tmp3   = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1);
+  tmp4   = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3);
+  tmp5   = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3);
+  tmp4   = vec_and (v_ref_mask00, tmp4);
+  tmp5   = vec_and (v_ref_mask01, tmp5);
+
+  tmp0   = vec_nor (v_ref_mask00, v_ref_mask01);
+  tmp1   = vec_and (v_ref_mask00, v_ref_mask01);
+  tmp2   = vec_and (tmp4, tmp5);
+  tmp2   = vec_and (tmp2, tmp1);
+  tmp3   = vec_nor (tmp4, tmp5);
+  tmp3   = vec_nor (tmp3, tmp1);
+  v_vec_maskh = vec_or (tmp0, tmp2);
+  v_vec_maskh = vec_or (v_vec_maskh, tmp3);
+
+
+  v_intra_maskvn = vec_nor (v_intra_maskv, v_intra_maskv);
+  v_intra_maskhn = vec_nor (v_intra_maskh, v_intra_maskh);
+  v_cbp_maskvn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero);
+  v_cbp_maskhn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero);
+
+  v_cbp_maskv  = vec_and (v_cbp_maskv, v_intra_maskvn);
+  v_cbp_maskh  = vec_and (v_cbp_maskh, v_intra_maskhn);
+  v_vec_maskv  = vec_and (v_vec_maskv, (vector signed short) v_intra_maskvn);
+  v_vec_maskv  = vec_and (v_vec_maskv, (vector signed short) v_cbp_maskvn);
+  v_vec_maskh  = vec_and (v_vec_maskh, (vector signed short) v_intra_maskhn);
+  v_vec_maskh  = vec_and (v_vec_maskh, (vector signed short) v_cbp_maskhn);
+
+  tmp9        = vec_splat_u8(2);
+  tmp8        = vec_splat_u8(1);
+  v_bS        = vec_ld (0, (vector unsigned char *) mv_const);
+  
+  v_bSv       = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskv);
+  tmp7        = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskv);
+  tmp6        = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskv);
+  tmp7        = vec_or  ((vector unsigned char)tmp7, (vector unsigned char)tmp6);
+  v_bSv       = vec_or  ((vector unsigned char)tmp7, (vector unsigned char)v_bSv);
+
+  v_bS        = vec_ld (0, (vector unsigned char *) mv_const);
+  v_bSh       = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskh);
+  tmp7        = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskh);
+  tmp6        = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskh);
+  tmp7        = vec_or  ((vector unsigned char)tmp7, (vector unsigned char)tmp6);
+  v_bSh       = vec_or  ((vector unsigned char)tmp7, (vector unsigned char)v_bSh);
+
+  v_permh     = (vector unsigned char) vec_ld (0 , (vector unsigned char *) mv_const);
+  v_permv     = (vector unsigned char) vec_ld (0, (vector unsigned char *) mv_const);
+  v_bSv       = vec_and (v_bSv, v_permv);
+  v_bSh       = vec_and (v_bSh, v_permh);
+
+  vec_st (v_bSv, 0, (unsigned char *) mv_const);
+  vec_st (v_bSh, 0, (unsigned char *) mv_const);
+
+  v_bSv = vec_mergeh (v_bSv, v_bSv);
+  v_bSv = vec_mergeh (v_bSv, v_bSv);
+  v_bSh = vec_mergeh (v_bSh, v_bSh);
+  v_bSh = vec_mergeh (v_bSh, v_bSh);
+    
+  vec_st (v_bSv, 0, (vector unsigned char *) mv_const);
+  vec_st (v_bSh, 0,(vector unsigned char *) mv_const);
+}
+
+
+int main(int argc, char **argv)
+{
+    char toto[32] __attribute__((aligned(16)));
+
+    foo(toto, toto, 0, 0);
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c
new file mode 100644
index 000000000..a2aa11145
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Check that "volatile" type qualifier is propagated to vector type.  */
+
+#include <altivec.h>
+
+vector float *f (volatile vector float *a)
+{
+  return a;  /* { dg-warning "discards 'volatile' qualifier" } */
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-es-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-es-1.c
new file mode 100644
index 000000000..fe3e899d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-es-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+static inline void __attribute__((always_inline))
+f1 (void)
+{
+  long unused;
+  asm volatile ("" : "=es" (unused) :: "memory");
+}
+
+static void __attribute__((noinline))
+f2 (long *val)
+{
+  *val = 0x1234;
+}
+
+static long __attribute__((noinline))
+test (void)
+{
+  f1 ();
+  {
+    long val;
+    f2 (&val);
+    return val;
+  }
+}
+
+int
+main (void)
+{
+  return test () != 0x1234;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-es-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-es-2.c
new file mode 100644
index 000000000..d2b46913b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-es-2.c
@@ -0,0 +1,37 @@
+/* { dg-options "-O2" } */
+void
+f1 (int *p, int x)
+{
+  asm ("asm1 %0" : "=es" (p[x]));
+}
+
+void
+f2 (int *p)
+{
+  while (1)
+    {
+      p += 4;
+      asm ("asm2%U0 %0" : "=m<>" (*p));
+    }
+}
+
+void
+f3 (int *p)
+{
+  while (1)
+    {
+      p += 4;
+      asm ("asm3%U0 %0" : "=es" (*p));
+    }
+}
+
+void
+f4 (int *p)
+{
+  asm ("asm4 %0" : "=es" (p[100]));
+}
+
+/* { dg-final { scan-assembler "asm1 %?r?3,%?r?4" } } */
+/* { dg-final { scan-assembler "asm2u 16\\(%?r?3\\)" } } */
+/* { dg-final { scan-assembler "asm3 0\\(%?r?3\\)" } } */
+/* { dg-final { scan-assembler "asm4 400\\(%?r?3\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-y.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-y.c
new file mode 100644
index 000000000..7d5a6a617
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/asm-y.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+/* Test that %yN does not cause an internal error if used incorrectly.  */
+
+int f(int *a)
+{
+  asm ("#%y0" : "=m"(a[2])); /* { dg-error "try using the 'Z' constraint" } */
+  asm ("#%y0" : "=m"(a[1])); /* { dg-error "try using the 'Z' constraint" } */
+  asm ("#%y0" : "=m"(a[0]));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic-p7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic-p7.c
new file mode 100644
index 000000000..3442bfba4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic-p7.c
@@ -0,0 +1,207 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2" } */
+/* { dg-final { scan-assembler-not "lbarx" } } */
+/* { dg-final { scan-assembler-not "lharx" } } */
+/* { dg-final { scan-assembler-times "lwarx" 18 } } */
+/* { dg-final { scan-assembler-times "ldarx" 6 } } */
+/* { dg-final { scan-assembler-not "lqarx" } } */
+/* { dg-final { scan-assembler-not "stbcx" } } */
+/* { dg-final { scan-assembler-not "sthcx" } } */
+/* { dg-final { scan-assembler-times "stwcx" 18 } } */
+/* { dg-final { scan-assembler-times "stdcx" 6 } } */
+/* { dg-final { scan-assembler-not "stqcx" } } */
+/* { dg-final { scan-assembler-times "bl __atomic" 6 } } */
+/* { dg-final { scan-assembler-times "isync" 12 } } */
+/* { dg-final { scan-assembler-times "lwsync" 8 } } */
+/* { dg-final { scan-assembler-not "mtvsrd" } } */
+/* { dg-final { scan-assembler-not "mtvsrwa" } } */
+/* { dg-final { scan-assembler-not "mtvsrwz" } } */
+/* { dg-final { scan-assembler-not "mfvsrd" } } */
+/* { dg-final { scan-assembler-not "mfvsrwz" } } */
+
+/* Test for the byte atomic operations on power8 using lbarx/stbcx.  */
+char
+char_fetch_add_relaxed (char *ptr, int value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+char
+char_fetch_sub_consume (char *ptr, int value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+char
+char_fetch_and_acquire (char *ptr, int value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+char
+char_fetch_ior_release (char *ptr, int value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+char
+char_fetch_xor_acq_rel (char *ptr, int value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+char
+char_fetch_nand_seq_cst (char *ptr, int value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+/* Test for the half word atomic operations on power8 using lharx/sthcx.  */
+short
+short_fetch_add_relaxed (short *ptr, int value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+short
+short_fetch_sub_consume (short *ptr, int value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+short
+short_fetch_and_acquire (short *ptr, int value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+short
+short_fetch_ior_release (short *ptr, int value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+short
+short_fetch_xor_acq_rel (short *ptr, int value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+short
+short_fetch_nand_seq_cst (short *ptr, int value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+/* Test for the word atomic operations on power8 using lwarx/stwcx.  */
+int
+int_fetch_add_relaxed (int *ptr, int value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+int
+int_fetch_sub_consume (int *ptr, int value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+int
+int_fetch_and_acquire (int *ptr, int value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+int
+int_fetch_ior_release (int *ptr, int value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+int
+int_fetch_xor_acq_rel (int *ptr, int value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+int
+int_fetch_nand_seq_cst (int *ptr, int value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+/* Test for the double word atomic operations on power8 using ldarx/stdcx.  */
+long
+long_fetch_add_relaxed (long *ptr, long value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+long
+long_fetch_sub_consume (long *ptr, long value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+long
+long_fetch_and_acquire (long *ptr, long value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+long
+long_fetch_ior_release (long *ptr, long value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+long
+long_fetch_xor_acq_rel (long *ptr, long value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+long
+long_fetch_nand_seq_cst (long *ptr, long value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+/* Test for the quad word atomic operations on power8 using ldarx/stdcx.  */
+__int128_t
+quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+__int128_t
+quad_fetch_sub_consume (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+__int128_t
+quad_fetch_and_acquire (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+__int128_t
+quad_fetch_ior_release (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+__int128_t
+quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+__int128_t
+quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic-p8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic-p8.c
new file mode 100644
index 000000000..17460ac4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/atomic-p8.c
@@ -0,0 +1,237 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+/* { dg-final { scan-assembler-times "lbarx" 7 } } */
+/* { dg-final { scan-assembler-times "lharx" 7 } } */
+/* { dg-final { scan-assembler-times "lwarx" 7 } } */
+/* { dg-final { scan-assembler-times "ldarx" 7 } } */
+/* { dg-final { scan-assembler-times "lqarx" 7 } } */
+/* { dg-final { scan-assembler-times "stbcx" 7 } } */
+/* { dg-final { scan-assembler-times "sthcx" 7 } } */
+/* { dg-final { scan-assembler-times "stwcx" 7 } } */
+/* { dg-final { scan-assembler-times "stdcx" 7 } } */
+/* { dg-final { scan-assembler-times "stqcx" 7 } } */
+/* { dg-final { scan-assembler-not "bl __atomic" } } */
+/* { dg-final { scan-assembler-times "isync" 20 } } */
+/* { dg-final { scan-assembler-times "lwsync" 10 } } */
+/* { dg-final { scan-assembler-not "mtvsrd" } } */
+/* { dg-final { scan-assembler-not "mtvsrwa" } } */
+/* { dg-final { scan-assembler-not "mtvsrwz" } } */
+/* { dg-final { scan-assembler-not "mfvsrd" } } */
+/* { dg-final { scan-assembler-not "mfvsrwz" } } */
+
+/* Test for the byte atomic operations on power8 using lbarx/stbcx.  */
+char
+char_fetch_add_relaxed (char *ptr, int value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+char
+char_fetch_sub_consume (char *ptr, int value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+char
+char_fetch_and_acquire (char *ptr, int value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+char
+char_fetch_ior_release (char *ptr, int value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+char
+char_fetch_xor_acq_rel (char *ptr, int value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+char
+char_fetch_nand_seq_cst (char *ptr, int value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+void
+char_val_compare_and_swap (char *p, int i, int j, char *q)
+{
+  *q = __sync_val_compare_and_swap (p, i, j);
+}
+
+/* Test for the half word atomic operations on power8 using lharx/sthcx.  */
+short
+short_fetch_add_relaxed (short *ptr, int value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+short
+short_fetch_sub_consume (short *ptr, int value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+short
+short_fetch_and_acquire (short *ptr, int value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+short
+short_fetch_ior_release (short *ptr, int value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+short
+short_fetch_xor_acq_rel (short *ptr, int value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+short
+short_fetch_nand_seq_cst (short *ptr, int value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+void
+short_val_compare_and_swap (short *p, int i, int j, short *q)
+{
+  *q = __sync_val_compare_and_swap (p, i, j);
+}
+
+/* Test for the word atomic operations on power8 using lwarx/stwcx.  */
+int
+int_fetch_add_relaxed (int *ptr, int value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+int
+int_fetch_sub_consume (int *ptr, int value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+int
+int_fetch_and_acquire (int *ptr, int value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+int
+int_fetch_ior_release (int *ptr, int value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+int
+int_fetch_xor_acq_rel (int *ptr, int value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+int
+int_fetch_nand_seq_cst (int *ptr, int value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+void
+int_val_compare_and_swap (int *p, int i, int j, int *q)
+{
+  *q = __sync_val_compare_and_swap (p, i, j);
+}
+
+/* Test for the double word atomic operations on power8 using ldarx/stdcx.  */
+long
+long_fetch_add_relaxed (long *ptr, long value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+long
+long_fetch_sub_consume (long *ptr, long value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+long
+long_fetch_and_acquire (long *ptr, long value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+long
+long_fetch_ior_release (long *ptr, long value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+long
+long_fetch_xor_acq_rel (long *ptr, long value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+long
+long_fetch_nand_seq_cst (long *ptr, long value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+void
+long_val_compare_and_swap (long *p, long i, long j, long *q)
+{
+  *q = __sync_val_compare_and_swap (p, i, j);
+}
+
+/* Test for the quad word atomic operations on power8 using ldarx/stdcx.  */
+__int128_t
+quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED);
+}
+
+__int128_t
+quad_fetch_sub_consume (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME);
+}
+
+__int128_t
+quad_fetch_and_acquire (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+__int128_t
+quad_fetch_ior_release (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE);
+}
+
+__int128_t
+quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL);
+}
+
+__int128_t
+quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST);
+}
+
+void
+quad_val_compare_and_swap (__int128_t *p, __int128_t i, __int128_t j, __int128_t *q)
+{
+  *q = __sync_val_compare_and_swap (p, i, j);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c
new file mode 100644
index 000000000..e86aa8a5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mavoid-indexed-addresses -mno-altivec -mno-vsx" } */
+
+/* { dg-final { scan-assembler-not "lbzx" } }
+
+/* Ensure that an indexed load is not generated with
+   -mavoid-indexed-addresses. */
+
+char
+do_one (char *base, unsigned long offset)
+{
+  return base[offset];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/block-move-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/block-move-1.c
new file mode 100644
index 000000000..7b6623fbe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/block-move-1.c
@@ -0,0 +1,14 @@
+/* Test that we bump up low values of -mblock-move-inline-limit */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mblock-move-inline-limit=8" } */
+
+typedef __SIZE_TYPE__ size_t;
+extern void *memcpy (void *, const void *, size_t);
+
+void
+cpy16 (void *x, void *y)
+{
+  memcpy (x, y, 16);
+}
+
+/* { dg-final { scan-assembler-not "memcpy" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/block-move-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/block-move-2.c
new file mode 100644
index 000000000..ffaf9ef05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/block-move-2.c
@@ -0,0 +1,14 @@
+/* Test that we honor -mblock-move-inline-limit.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mblock-move-inline-limit=128" } */
+
+typedef __SIZE_TYPE__ size_t;
+extern void *memcpy (void *, const void *, size_t);
+
+void
+cpy128 (void *x, void *y)
+{
+  memcpy (x, y, 128);
+}
+
+/* { dg-final { scan-assembler-not "memcpy" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool.c
new file mode 100644
index 000000000..f007db4b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "eqv" } } */
+/* { dg-final { scan-assembler "nand" } } */
+/* { dg-final { scan-assembler "nor" } } */
+
+#ifndef TYPE
+#define TYPE unsigned long
+#endif
+
+TYPE op1 (TYPE a, TYPE b) { return ~(a ^ b); }	/* eqv */
+TYPE op2 (TYPE a, TYPE b) { return ~(a & b); }	/* nand */
+TYPE op3 (TYPE a, TYPE b) { return ~(a | b); }	/* nor */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-av.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-av.c
new file mode 100644
index 000000000..fc56ce261
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-av.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -mcpu=power6 -maltivec" } */
+/* { dg-final { scan-assembler-not "\[ \t\]and "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]or "      } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]nor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]andc "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]eqv "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]orc "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]nand "    } } */
+/* { dg-final { scan-assembler     "\[ \t\]vand "    } } */
+/* { dg-final { scan-assembler     "\[ \t\]vandc "   } } */
+/* { dg-final { scan-assembler     "\[ \t\]vor "     } } */
+/* { dg-final { scan-assembler     "\[ \t\]vxor "    } } */
+/* { dg-final { scan-assembler     "\[ \t\]vnor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxland "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlor "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
+
+#ifndef TYPE
+typedef int v4si __attribute__ ((vector_size (16)));
+#define TYPE v4si
+#endif
+
+#include "bool2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p5.c
new file mode 100644
index 000000000..e4810d00d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p5.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -mcpu=power5 -mabi=altivec -mno-altivec -mno-vsx" } */
+/* { dg-final { scan-assembler	   "\[ \t\]and "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]or "      } } */
+/* { dg-final { scan-assembler	   "\[ \t\]xor "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]nor "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]andc "    } } */
+/* { dg-final { scan-assembler	   "\[ \t\]eqv "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]orc "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]nand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vandc "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vxor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vnor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxland "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlor "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
+
+#ifndef TYPE
+typedef int v4si __attribute__ ((vector_size (16)));
+#define TYPE v4si
+#endif
+
+#include "bool2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p7.c
new file mode 100644
index 000000000..274fcb090
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p7.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler-not "\[ \t\]and "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]or "      } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]nor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]eqv "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]andc "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]orc "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]nand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vxor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vnor "    } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxland "  } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlor "   } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlxor "  } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlnor "  } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlandc " } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
+
+#ifndef TYPE
+typedef int v4si __attribute__ ((vector_size (16)));
+#define TYPE v4si
+#endif
+
+#include "bool2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p8.c
new file mode 100644
index 000000000..34f4d2df8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2-p8.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mcpu=power8" } */
+/* { dg-final { scan-assembler-not "\[ \t\]and "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]or "      } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]nor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]eqv "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]andc "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]orc "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]nand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vandc "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vxor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vnor "    } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxland "  } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlor "   } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlxor "  } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlnor "  } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlandc " } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxleqv "  } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlorc "  } } */
+/* { dg-final { scan-assembler     "\[ \t\]xxlnand " } } */
+
+#ifndef TYPE
+typedef int v4si __attribute__ ((vector_size (16)));
+#define TYPE v4si
+#endif
+
+#include "bool2.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2.h b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2.h
new file mode 100644
index 000000000..4513944c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool2.h
@@ -0,0 +1,29 @@
+/* Test various logical operations.  */
+
+TYPE arg1 (TYPE p, TYPE q) { return p & q; }		/* AND  */
+TYPE arg2 (TYPE p, TYPE q) { return p | q; }		/* OR   */
+TYPE arg3 (TYPE p, TYPE q) { return p ^ q; }		/* XOR  */
+TYPE arg4 (TYPE p)	   { return ~ p; }		/* NOR  */
+TYPE arg5 (TYPE p, TYPE q) { return ~(p & q); }		/* NAND */
+TYPE arg6 (TYPE p, TYPE q) { return ~(p | q); }		/* NOR  */
+TYPE arg7 (TYPE p, TYPE q) { return ~(p ^ q); }		/* EQV  */
+TYPE arg8 (TYPE p, TYPE q) { return (~p) & q; }		/* ANDC */
+TYPE arg9 (TYPE p, TYPE q) { return (~p) | q; }		/* ORC  */
+TYPE arg10(TYPE p, TYPE q) { return (~p) ^ q; }		/* EQV  */
+TYPE arg11(TYPE p, TYPE q) { return p & (~q); }		/* ANDC */
+TYPE arg12(TYPE p, TYPE q) { return p | (~q); }		/* ORC  */
+TYPE arg13(TYPE p, TYPE q) { return p ^ (~q); }		/* EQV  */
+
+void ptr1 (TYPE *p) { p[0] = p[1] & p[2]; }		/* AND  */
+void ptr2 (TYPE *p) { p[0] = p[1] | p[2]; }		/* OR   */
+void ptr3 (TYPE *p) { p[0] = p[1] ^ p[2]; }		/* XOR  */
+void ptr4 (TYPE *p) { p[0] = ~p[1]; }			/* NOR  */
+void ptr5 (TYPE *p) { p[0] = ~(p[1] & p[2]); }		/* NAND */
+void ptr6 (TYPE *p) { p[0] = ~(p[1] | p[2]); }		/* NOR  */
+void ptr7 (TYPE *p) { p[0] = ~(p[1] ^ p[2]); }		/* EQV  */
+void ptr8 (TYPE *p) { p[0] = ~(p[1]) & p[2]; }		/* ANDC */
+void ptr9 (TYPE *p) { p[0] = (~p[1]) | p[2]; }		/* ORC  */
+void ptr10(TYPE *p) { p[0] = (~p[1]) ^ p[2]; }		/* EQV  */
+void ptr11(TYPE *p) { p[0] = p[1] & (~p[2]); }		/* ANDC */
+void ptr12(TYPE *p) { p[0] = p[1] | (~p[2]); }		/* ORC  */
+void ptr13(TYPE *p) { p[0] = p[1] ^ (~p[2]); }		/* EQV  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-av.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-av.c
new file mode 100644
index 000000000..d4aac786b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-av.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */
+/* { dg-final { scan-assembler	   "\[ \t\]and "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]or "      } } */
+/* { dg-final { scan-assembler	   "\[ \t\]xor "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]nor "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]andc "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vandc "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vxor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vnor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxland "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlor "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
+
+/* On altivec, for 128-bit types, ORC/ANDC/EQV might not show up, since the
+   vector unit doesn't support these, so the appropriate combine patterns may
+   not be generated.  */
+
+#ifndef TYPE
+#ifdef _ARCH_PPC64
+#define TYPE __int128_t
+#else
+typedef int v4si __attribute__ ((vector_size (16)));
+#define TYPE v4si
+#endif
+#endif
+
+#include "bool3.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-p7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-p7.c
new file mode 100644
index 000000000..34e3c9e79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-p7.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler	   "\[ \t\]and "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]or "      } } */
+/* { dg-final { scan-assembler	   "\[ \t\]xor "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]nor "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]andc "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vandc "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vxor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vnor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxland "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlor "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
+
+/* On power7, for 128-bit types, ORC/ANDC/EQV might not show up, since the
+   vector unit doesn't support these, so the appropriate combine patterns may
+   not be generated.  */
+
+#ifndef TYPE
+#ifdef _ARCH_PPC64
+#define TYPE __int128_t
+#else
+typedef int v4si __attribute__ ((vector_size (16)));
+#define TYPE v4si
+#endif
+#endif
+
+#include "bool3.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-p8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-p8.c
new file mode 100644
index 000000000..e1b2dfa7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3-p8.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mcpu=power8" } */
+/* { dg-final { scan-assembler	   "\[ \t\]and "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]or "      } } */
+/* { dg-final { scan-assembler	   "\[ \t\]xor "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]nor "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]andc "    } } */
+/* { dg-final { scan-assembler	   "\[ \t\]eqv "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]orc "     } } */
+/* { dg-final { scan-assembler	   "\[ \t\]nand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vand "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vandc "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vor "     } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vxor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]vnor "    } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxland "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlor "   } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlxor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnor "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxleqv "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlorc "  } } */
+/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
+
+#ifndef TYPE
+#ifdef _ARCH_PPC64
+#define TYPE __int128_t
+#else
+typedef int v4si __attribute__ ((vector_size (16)));
+#define TYPE v4si
+#endif
+#endif
+
+#include "bool3.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3.h b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3.h
new file mode 100644
index 000000000..7b99a4a61
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bool3.h
@@ -0,0 +1,186 @@
+/* Test forcing 128-bit logical types into GPR registers.  */
+
+#if defined(NO_ASM)
+#define FORCE_REG1(X)
+#define FORCE_REG2(X,Y)
+
+#else
+#if defined(USE_ALTIVEC)
+#define REG_CLASS "+v"
+#define PRINT_REG1 "# altivec reg %0"
+#define PRINT_REG2 "# altivec reg %0, %1"
+
+#elif defined(USE_FPR)
+#define REG_CLASS "+d"
+#define PRINT_REG1 "# fpr reg %0"
+#define PRINT_REG2 "# fpr reg %0, %1"
+
+#elif defined(USE_VSX)
+#define REG_CLASS "+wa"
+#define PRINT_REG1 "# vsx reg %x0"
+#define PRINT_REG2 "# vsx reg %x0, %x1"
+
+#else
+#define REG_CLASS "+r"
+#define PRINT_REG1 "# gpr reg %0"
+#define PRINT_REG2 "# gpr reg %0, %1"
+#endif
+
+#define FORCE_REG1(X) __asm__ (PRINT_REG1 : REG_CLASS (X))
+#define FORCE_REG2(X,Y) __asm__ (PRINT_REG2 : REG_CLASS (X), REG_CLASS (Y))
+#endif
+
+void ptr1 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = a & b;					/* AND */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr2 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = a | b;					/* OR */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr3 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = a ^ b;					/* XOR */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr4 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b;
+
+  FORCE_REG1 (a);
+  b = ~a;					/* NOR */
+  FORCE_REG1 (b);
+  p[0] = b;
+}
+
+void ptr5 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = ~(a & b);					   /* NAND */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr6 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = ~(a | b);					   /* AND */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr7 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = ~(a ^ b);					   /* EQV */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr8 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = (~a) & b;					   /* ANDC */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr9 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = (~a) | b;					   /* ORC */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr10 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = (~a) ^ b;					   /* EQV */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr11 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = a & (~b);					   /* ANDC */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr12 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = a | (~b);					   /* ORC */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
+
+void ptr13 (TYPE *p)
+{
+  TYPE a = p[1];
+  TYPE b = p[2];
+  TYPE c;
+
+  FORCE_REG2 (a, b);
+  c = a ^ (~b);					   /* AND */
+  FORCE_REG1 (c);
+  p[0] = c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap-run.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap-run.c
new file mode 100644
index 000000000..484908a81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap-run.c
@@ -0,0 +1,102 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-options "-O2 -std=gnu99" } */
+
+extern void abort (void);
+
+static unsigned char bytes[] = { 0, 1, 2, 0x80, 0xff };
+
+unsigned short b16a (unsigned short *p) { return __builtin_bswap16 (*p); }
+void b16b (unsigned short *p, unsigned short a) { *p = __builtin_bswap16 (a); }
+int b16c (unsigned short a) { return __builtin_bswap16 (a); }
+
+unsigned int b32a (unsigned int *p) { return __builtin_bswap32 (*p); }
+void b32b (unsigned int *p, unsigned int a) { *p = __builtin_bswap32 (a); }
+static unsigned int b32c (unsigned int a) { return __builtin_bswap32 (a); }
+
+unsigned long long b64a (unsigned long long *p) { return __builtin_bswap64 (*p); }
+void b64b (unsigned long long *p, unsigned long long a) { *p = __builtin_bswap64 (a); }
+unsigned long long b64c (unsigned long long a) { return __builtin_bswap64 (a); }
+
+int
+main (void)
+{
+  unsigned i1, i2, i3, i4, i5;
+  unsigned b1, b2, b3, b4, b5;
+  unsigned short b16_inp, b16_exp, b16_var;
+  unsigned int b32_inp, b32_exp, b32_var;
+  unsigned long long b64_inp, b64_exp, b64_var;
+
+  for (i1 = 0; i1 < sizeof (bytes); i1++)
+    {
+      b1 = bytes[i1];
+      for (i2 = 0; i2 < sizeof (bytes); i2++)
+	{
+	  b2 = bytes[i2];
+	  b16_inp = (b1 << 8) | b2;
+	  b16_exp = (b2 << 8) | b1;
+
+	  if (b16a (&b16_inp) != b16_exp)
+	    abort ();
+
+	  b16b (&b16_var, b16_inp);
+	  if (b16_var != b16_exp)
+	    abort ();
+
+	  if (b16c (b16_inp) != b16_exp)
+	    abort ();
+
+	  for (i3 = 0; i3 < sizeof (bytes); i3++)
+	    {
+	      b3 = bytes[i3];
+	      for (i4 = 0; i4 < sizeof (bytes); i4++)
+		{
+		  b4 = bytes[i4];
+		  b32_inp = (b1 << 24) | (b2 << 16) | (b3 << 8) | b4;
+		  b32_exp = (b4 << 24) | (b3 << 16) | (b2 << 8) | b1;
+
+		  if (b32a (&b32_inp) != b32_exp)
+		    abort ();
+
+		  b32b (&b32_var, b32_inp);
+		  if (b32_var != b32_exp)
+		    abort ();
+
+		  if (b32c (b32_inp) != b32_exp)
+		    abort ();
+
+		  for (i5 = 0; i5 < sizeof (bytes); i5++)
+		    {
+		      b5 = bytes[i5];
+		      b64_inp = (((unsigned long long)b32_inp) << 32) | b5;
+		      b64_exp = (((unsigned long long)b5) << 56) | b32_exp;
+
+		      if (b64a (&b64_inp) != b64_exp)
+			abort ();
+
+		      b64b (&b64_var, b64_inp);
+		      if (b64_var != b64_exp)
+			abort ();
+
+		      if (b64c (b64_inp) != b64_exp)
+			abort ();
+
+		      b64_inp = (((unsigned long long)b5) << 56) | b32_inp;
+		      b64_exp = (((unsigned long long)b32_exp) << 32) | b5;
+
+		      if (b64a (&b64_inp) != b64_exp)
+			abort ();
+
+		      b64b (&b64_var, b64_inp);
+		      if (b64_var != b64_exp)
+			abort ();
+
+		      if (b64c (b64_inp) != b64_exp)
+			abort ();
+		    }
+		}
+	    }
+	}
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap16.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap16.c
new file mode 100644
index 000000000..5eea4f774
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap16.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "lhbrx" } } */
+/* { dg-final { scan-assembler "sthbrx" } } */
+
+unsigned short us;
+unsigned int load_bswap16 (unsigned short *p) { return __builtin_bswap16 (*p); }
+void store_bswap16 (unsigned int a) { us = __builtin_bswap16 (a); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap32.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap32.c
new file mode 100644
index 000000000..1b1e189aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "lwbrx" } } */
+/* { dg-final { scan-assembler "stwbrx" } } */
+
+unsigned int ui;
+unsigned int load_bswap32 (unsigned int *p) { return __builtin_bswap32 (*p); }
+void store_bswap32 (unsigned int a) { ui = __builtin_bswap32 (a); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-1.c
new file mode 100644
index 000000000..480e1cd7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mno-popcntd -mcpu=power5" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-final { scan-assembler "lwbrx" } } */
+/* { dg-final { scan-assembler "stwbrx" } } */
+
+unsigned long ul;
+unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); }
+void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-2.c
new file mode 100644
index 000000000..6c3d8ca05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mpopcntd" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-final { scan-assembler "ldbrx" } } */
+/* { dg-final { scan-assembler "stdbrx" } } */
+
+unsigned long ul;
+unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); }
+void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-3.c
new file mode 100644
index 000000000..7f1138cf9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2 -mcpu=cell" } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-require-effective-target powerpc_ppu_ok } */
+/* { dg-final { scan-assembler "ldbrx" } } */
+/* { dg-final { scan-assembler "stdbrx" } } */
+
+unsigned long ul;
+unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); }
+void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-4.c
new file mode 100644
index 000000000..826999cf1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/bswap64-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
+/* { dg-options "-O2 -mpowerpc64" } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-final { scan-assembler-times "lwbrx" 2 } } */
+/* { dg-final { scan-assembler-times "stwbrx" 2 } } */
+
+long long swap_load (long long *a) { return __builtin_bswap64 (*a); }
+long long swap_reg (long long a) { return __builtin_bswap64 (a); }
+void swap_store (long long *a, long long b) { *a = __builtin_bswap64 (b); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c
new file mode 100644
index 000000000..f2bc7ffb3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-1.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "lvlx" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+vsc  lc1(long a, void *p)           { return __builtin_altivec_lvlx (a,p); }
+vsf  llx01(long a, vsf *p)          { return __builtin_vec_lvlx (a,p); }
+vsf  llx02(long a, sf *p)           { return __builtin_vec_lvlx (a,p); }
+vbi  llx03(long a, vbi *p)          { return __builtin_vec_lvlx (a,p); }
+vsi  llx04(long a, vsi *p)          { return __builtin_vec_lvlx (a,p); }
+vsi  llx05(long a, si *p)           { return __builtin_vec_lvlx (a,p); }
+vui  llx06(long a, vui *p)          { return __builtin_vec_lvlx (a,p); }
+vui  llx07(long a, ui *p)           { return __builtin_vec_lvlx (a,p); }
+vbs  llx08(long a, vbs *p)          { return __builtin_vec_lvlx (a,p); }
+vp   llx09(long a, vp *p)           { return __builtin_vec_lvlx (a,p); }
+vss  llx10(long a, vss *p)          { return __builtin_vec_lvlx (a,p); }
+vss  llx11(long a, ss *p)           { return __builtin_vec_lvlx (a,p); }
+vus  llx12(long a, vus *p)          { return __builtin_vec_lvlx (a,p); }
+vus  llx13(long a, us *p)           { return __builtin_vec_lvlx (a,p); }
+vbc  llx14(long a, vbc *p)          { return __builtin_vec_lvlx (a,p); }
+vsc  llx15(long a, vsc *p)          { return __builtin_vec_lvlx (a,p); }
+vsc  llx16(long a, sc *p)           { return __builtin_vec_lvlx (a,p); }
+vuc  llx17(long a, vuc *p)          { return __builtin_vec_lvlx (a,p); }
+vuc  llx18(long a, uc *p)           { return __builtin_vec_lvlx (a,p); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c
new file mode 100644
index 000000000..220be5716
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "lvlxl" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+vsc  lc2(long a, void *p)           { return __builtin_altivec_lvlxl (a,p); }
+vsf  llxl01(long a, vsf *p)         { return __builtin_vec_lvlxl (a,p); }
+vsf  llxl02(long a, sf *p)          { return __builtin_vec_lvlxl (a,p); }
+vbi  llxl03(long a, vbi *p)         { return __builtin_vec_lvlxl (a,p); }
+vsi  llxl04(long a, vsi *p)         { return __builtin_vec_lvlxl (a,p); }
+vsi  llxl05(long a, si *p)          { return __builtin_vec_lvlxl (a,p); }
+vui  llxl06(long a, vui *p)         { return __builtin_vec_lvlxl (a,p); }
+vui  llxl07(long a, ui *p)          { return __builtin_vec_lvlxl (a,p); }
+vbs  llxl08(long a, vbs *p)         { return __builtin_vec_lvlxl (a,p); }
+vp   llxl09(long a, vp *p)          { return __builtin_vec_lvlxl (a,p); }
+vss  llxl10(long a, vss *p)         { return __builtin_vec_lvlxl (a,p); }
+vss  llxl11(long a, ss *p)          { return __builtin_vec_lvlxl (a,p); }
+vus  llxl12(long a, vus *p)         { return __builtin_vec_lvlxl (a,p); }
+vus  llxl13(long a, us *p)          { return __builtin_vec_lvlxl (a,p); }
+vbc  llxl14(long a, vbc *p)         { return __builtin_vec_lvlxl (a,p); }
+vsc  llxl15(long a, vsc *p)         { return __builtin_vec_lvlxl (a,p); }
+vsc  llxl16(long a, sc *p)          { return __builtin_vec_lvlxl (a,p); }
+vuc  llxl17(long a, vuc *p)         { return __builtin_vec_lvlxl (a,p); }
+vuc  llxl18(long a, uc *p)          { return __builtin_vec_lvlxl (a,p); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c
new file mode 100644
index 000000000..4b437291e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-3.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "lvrx" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+vsc  lc3(long a, void *p)           { return __builtin_altivec_lvrx (a,p); }
+vsf  lrx01(long a, vsf *p)          { return __builtin_vec_lvrx (a,p); }
+vsf  lrx02(long a, sf *p)           { return __builtin_vec_lvrx (a,p); }
+vbi  lrx03(long a, vbi *p)          { return __builtin_vec_lvrx (a,p); }
+vsi  lrx04(long a, vsi *p)          { return __builtin_vec_lvrx (a,p); }
+vsi  lrx05(long a, si *p)           { return __builtin_vec_lvrx (a,p); }
+vui  lrx06(long a, vui *p)          { return __builtin_vec_lvrx (a,p); }
+vui  lrx07(long a, ui *p)           { return __builtin_vec_lvrx (a,p); }
+vbs  lrx08(long a, vbs *p)          { return __builtin_vec_lvrx (a,p); }
+vp   lrx09(long a, vp *p)           { return __builtin_vec_lvrx (a,p); }
+vss  lrx10(long a, vss *p)          { return __builtin_vec_lvrx (a,p); }
+vss  lrx11(long a, ss *p)           { return __builtin_vec_lvrx (a,p); }
+vus  lrx12(long a, vus *p)          { return __builtin_vec_lvrx (a,p); }
+vus  lrx13(long a, us *p)           { return __builtin_vec_lvrx (a,p); }
+vbc  lrx14(long a, vbc *p)          { return __builtin_vec_lvrx (a,p); }
+vsc  lrx15(long a, vsc *p)          { return __builtin_vec_lvrx (a,p); }
+vsc  lrx16(long a, sc *p)           { return __builtin_vec_lvrx (a,p); }
+vuc  lrx17(long a, vuc *p)          { return __builtin_vec_lvrx (a,p); }
+vuc  lrx18(long a, uc *p)           { return __builtin_vec_lvrx (a,p); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c
new file mode 100644
index 000000000..d73328ac4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-4.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "lvrxl" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+vsc  lc4(long a, void *p)           { return __builtin_altivec_lvrxl (a,p); }
+vsf  lrxl01(long a, vsf *p)         { return __builtin_vec_lvrxl (a,p); }
+vsf  lrxl02(long a, sf *p)          { return __builtin_vec_lvrxl (a,p); }
+vbi  lrxl03(long a, vbi *p)         { return __builtin_vec_lvrxl (a,p); }
+vsi  lrxl04(long a, vsi *p)         { return __builtin_vec_lvrxl (a,p); }
+vsi  lrxl05(long a, si *p)          { return __builtin_vec_lvrxl (a,p); }
+vui  lrxl06(long a, vui *p)         { return __builtin_vec_lvrxl (a,p); }
+vui  lrxl07(long a, ui *p)          { return __builtin_vec_lvrxl (a,p); }
+vbs  lrxl08(long a, vbs *p)         { return __builtin_vec_lvrxl (a,p); }
+vp   lrxl09(long a, vp *p)          { return __builtin_vec_lvrxl (a,p); }
+vss  lrxl10(long a, vss *p)         { return __builtin_vec_lvrxl (a,p); }
+vss  lrxl11(long a, ss *p)          { return __builtin_vec_lvrxl (a,p); }
+vus  lrxl12(long a, vus *p)         { return __builtin_vec_lvrxl (a,p); }
+vus  lrxl13(long a, us *p)          { return __builtin_vec_lvrxl (a,p); }
+vbc  lrxl14(long a, vbc *p)         { return __builtin_vec_lvrxl (a,p); }
+vsc  lrxl15(long a, vsc *p)         { return __builtin_vec_lvrxl (a,p); }
+vsc  lrxl16(long a, sc *p)          { return __builtin_vec_lvrxl (a,p); }
+vuc  lrxl17(long a, vuc *p)         { return __builtin_vec_lvrxl (a,p); }
+vuc  lrxl18(long a, uc *p)          { return __builtin_vec_lvrxl (a,p); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c
new file mode 100644
index 000000000..cc6adba80
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-5.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "stvlx" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+void sc1(vsc v, long a, void *p)    { __builtin_altivec_stvlx (v,a,p); }
+void slx01(vsf v, long a, vsf *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx02(vsf v, long a, sf *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx03(vbi v, long a, vbi *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx04(vsi v, long a, vsi *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx05(vsi v, long a, si *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx06(vui v, long a, vui *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx07(vui v, long a, ui *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx08(vbs v, long a, vbs *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx09(vp v, long a, vp *p)     { __builtin_vec_stvlx (v,a,p); }
+void slx10(vss v, long a, vss *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx11(vss v, long a, ss *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx12(vus v, long a, vus *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx13(vus v, long a, us *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx14(vbc v, long a, vbc *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx15(vsc v, long a, vsc *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx16(vsc v, long a, sc *p)    { __builtin_vec_stvlx (v,a,p); }
+void slx17(vuc v, long a, vuc *p)   { __builtin_vec_stvlx (v,a,p); }
+void slx18(vuc v, long a, uc *p)    { __builtin_vec_stvlx (v,a,p); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c
new file mode 100644
index 000000000..9c748d973
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-6.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "stvlxl" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+void sc2(vsc v, long a, void *p)    { __builtin_altivec_stvlxl (v,a,p); }
+void slxl01(vsf v, long a, vsf *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl02(vsf v, long a, sf *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl03(vbi v, long a, vbi *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl04(vsi v, long a, vsi *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl05(vsi v, long a, si *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl06(vui v, long a, vui *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl07(vui v, long a, ui *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl08(vbs v, long a, vbs *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl09(vp v, long a, vp *p)    { __builtin_vec_stvlxl (v,a,p); }
+void slxl10(vss v, long a, vss *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl11(vss v, long a, ss *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl12(vus v, long a, vus *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl13(vus v, long a, us *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl14(vbc v, long a, vbc *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl15(vsc v, long a, vsc *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl16(vsc v, long a, sc *p)   { __builtin_vec_stvlxl (v,a,p); }
+void slxl17(vuc v, long a, vuc *p)  { __builtin_vec_stvlxl (v,a,p); }
+void slxl18(vuc v, long a, uc *p)   { __builtin_vec_stvlxl (v,a,p); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c
new file mode 100644
index 000000000..abdb3b0ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-7.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "stvrx" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+void sc3(vsc v, long a, void *p)    { __builtin_altivec_stvrx (v,a,p); }
+void srx01(vsf v, long a, vsf *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx02(vsf v, long a, sf *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx03(vbi v, long a, vbi *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx04(vsi v, long a, vsi *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx05(vsi v, long a, si *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx06(vui v, long a, vui *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx07(vui v, long a, ui *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx08(vbs v, long a, vbs *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx09(vp v, long a, vp *p)     { __builtin_vec_stvrx (v,a,p); }
+void srx10(vss v, long a, vss *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx11(vss v, long a, ss *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx12(vus v, long a, vus *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx13(vus v, long a, us *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx14(vbc v, long a, vbc *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx15(vsc v, long a, vsc *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx16(vsc v, long a, sc *p)    { __builtin_vec_stvrx (v,a,p); }
+void srx17(vuc v, long a, vuc *p)   { __builtin_vec_stvrx (v,a,p); }
+void srx18(vuc v, long a, uc *p)    { __builtin_vec_stvrx (v,a,p); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c
new file mode 100644
index 000000000..ec7fc3031
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/cell_builtin-8.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec -mcpu=cell" } */
+/* { dg-final { scan-assembler-times "stvrxl" 19 } } */
+
+#include <altivec.h>
+
+typedef __vector signed char vsc;
+typedef __vector signed short vss;
+typedef __vector signed int vsi;
+typedef __vector unsigned char vuc;
+typedef __vector unsigned short vus;
+typedef __vector unsigned int vui;
+typedef __vector bool char vbc;
+typedef __vector bool short vbs;
+typedef __vector bool int vbi;
+typedef __vector float vsf;
+typedef __vector pixel vp;
+typedef signed char sc;
+typedef signed short ss;
+typedef signed int si;
+typedef signed long sl;
+typedef unsigned char uc;
+typedef unsigned short us;
+typedef unsigned int ui;
+typedef unsigned long ul;
+typedef float sf;
+
+void sc4(vsc v, long a, void *p)    { __builtin_altivec_stvrxl (v,a,p); }
+void srxl01(vsf v, long a, vsf *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl02(vsf v, long a, sf *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl03(vbi v, long a, vbi *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl04(vsi v, long a, vsi *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl05(vsi v, long a, si *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl06(vui v, long a, vui *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl07(vui v, long a, ui *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl08(vbs v, long a, vbs *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl09(vp v, long a, vp *p)    { __builtin_vec_stvrxl (v,a,p); }
+void srxl10(vss v, long a, vss *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl11(vss v, long a, ss *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl12(vus v, long a, vus *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl13(vus v, long a, us *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl14(vbc v, long a, vbc *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl15(vsc v, long a, vsc *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl16(vsc v, long a, sc *p)   { __builtin_vec_stvrxl (v,a,p); }
+void srxl17(vuc v, long a, vuc *p)  { __builtin_vec_stvrxl (v,a,p); }
+void srxl18(vuc v, long a, uc *p)   { __builtin_vec_stvrxl (v,a,p); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c
new file mode 100644
index 000000000..aa1da5245
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target powerpc_fprs } } */
+/* { dg-options "-O2 -fpic" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "lfs" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c
new file mode 100644
index 000000000..312642e68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/compress-float-ppc.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target powerpc_fprs } } */
+/* { dg-options "-O2" } */
+double foo (double x) {
+  return x + 1.75;
+}
+/* { dg-final { scan-assembler "lfs" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/const-compare.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/const-compare.c
new file mode 100644
index 000000000..a09957d34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/const-compare.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target { powerpc*-*-darwin* && lp64 } } } */
+/* { dg-options "-O1 -static" } */
+typedef unsigned long long uint64_t;
+
+static int
+match(name, pat)
+ uint64_t *name, *pat;
+{
+ int ok=0, negate_range;
+ uint64_t c, k;
+
+  c = *pat++;
+  switch (c & 0xffffffffffULL) {
+  case ((uint64_t)(('[')|0x8000000000ULL)):
+   if ((negate_range = ((*pat & 0xffffffffffULL) == ((uint64_t)(('!')|0x8000000000ULL)) )) != '\0')
+    ++pat;
+   while (((c = *pat++) & 0xffffffffffULL) )
+    if ((*pat & 0xffffffffffULL) == ((uint64_t)(('-')|0x8000000000ULL))) 
+      {
+       pat += 2;
+      } 
+
+   if (ok == negate_range)
+    return(0);
+   break;
+  }
+ return(*name == '\0');
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c
new file mode 100644
index 000000000..ce5da6a03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c
@@ -0,0 +1,130 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */
+
+typedef vector unsigned long long	crypto_t;
+typedef vector unsigned long long	v2di_t;
+typedef vector unsigned int		v4si_t;
+typedef vector unsigned short		v8hi_t;
+typedef vector unsigned char		v16qi_t;
+
+crypto_t crpyto1 (crypto_t a)
+{
+  return __builtin_crypto_vsbox (a);
+}
+
+crypto_t crypto2 (crypto_t a, crypto_t b)
+{
+  return __builtin_crypto_vcipher (a, b);
+}
+
+crypto_t crypto3 (crypto_t a, crypto_t b)
+{
+  return __builtin_crypto_vcipherlast (a, b);
+}
+
+crypto_t crypto4 (crypto_t a, crypto_t b)
+{
+  return __builtin_crypto_vncipher (a, b);
+}
+
+crypto_t crypto5 (crypto_t a, crypto_t b)
+{
+  return __builtin_crypto_vncipherlast (a, b);
+}
+
+v16qi_t crypto6a (v16qi_t a, v16qi_t b, v16qi_t c)
+{
+  return __builtin_crypto_vpermxor (a, b, c);
+}
+
+v8hi_t crypto6b (v8hi_t a, v8hi_t b, v8hi_t c)
+{
+  return __builtin_crypto_vpermxor (a, b, c);
+}
+
+v4si_t crypto6c (v4si_t a, v4si_t b, v4si_t c)
+{
+  return __builtin_crypto_vpermxor (a, b, c);
+}
+
+v2di_t crypto6d (v2di_t a, v2di_t b, v2di_t c)
+{
+  return __builtin_crypto_vpermxor (a, b, c);
+}
+
+v16qi_t crypto7a (v16qi_t a, v16qi_t b)
+{
+  return __builtin_crypto_vpmsumb (a, b);
+}
+
+v16qi_t crypto7b (v16qi_t a, v16qi_t b)
+{
+  return __builtin_crypto_vpmsum (a, b);
+}
+
+v8hi_t crypto7c (v8hi_t a, v8hi_t b)
+{
+  return __builtin_crypto_vpmsumh (a, b);
+}
+
+v8hi_t crypto7d (v8hi_t a, v8hi_t b)
+{
+  return __builtin_crypto_vpmsum (a, b);
+}
+
+v4si_t crypto7e (v4si_t a, v4si_t b)
+{
+  return __builtin_crypto_vpmsumw (a, b);
+}
+
+v4si_t crypto7f (v4si_t a, v4si_t b)
+{
+  return __builtin_crypto_vpmsum (a, b);
+}
+
+v2di_t crypto7g (v2di_t a, v2di_t b)
+{
+  return __builtin_crypto_vpmsumd (a, b);
+}
+
+v2di_t crypto7h (v2di_t a, v2di_t b)
+{
+  return __builtin_crypto_vpmsum (a, b);
+}
+
+v2di_t crypto8a (v2di_t a)
+{
+  return __builtin_crypto_vshasigmad (a, 0, 8);
+}
+
+v2di_t crypto8b (v2di_t a)
+{
+  return __builtin_crypto_vshasigma (a, 0, 8);
+}
+
+v4si_t crypto8c (v4si_t a)
+{
+  return __builtin_crypto_vshasigmaw (a, 1, 15);
+}
+
+v4si_t crypto8d (v4si_t a)
+{
+  return __builtin_crypto_vshasigma (a, 1, 15);
+}
+
+/* Note space is used after the instruction so that vcipherlast does not match
+   vcipher.  */
+/* { dg-final { scan-assembler-times "vcipher "      1 } } */
+/* { dg-final { scan-assembler-times "vcipherlast "  1 } } */
+/* { dg-final { scan-assembler-times "vncipher "     1 } } */
+/* { dg-final { scan-assembler-times "vncipherlast " 1 } } */
+/* { dg-final { scan-assembler-times "vpermxor "     4 } } */
+/* { dg-final { scan-assembler-times "vpmsumb "      2 } } */
+/* { dg-final { scan-assembler-times "vpmsumd "      2 } } */
+/* { dg-final { scan-assembler-times "vpmsumh "      2 } } */
+/* { dg-final { scan-assembler-times "vpmsumw "      2 } } */
+/* { dg-final { scan-assembler-times "vsbox "        1 } } */
+/* { dg-final { scan-assembler-times "vshasigmad "   2 } } */
+/* { dg-final { scan-assembler-times "vshasigmaw "   2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c
new file mode 100644
index 000000000..3b13c6236
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler "li r3,12345\n\t(bl|jbsr) " } } */
+
+/* Check that zero-size structures don't affect parameter passing.  */
+
+struct empty { };
+extern void foo (struct empty e, int a);
+void bar (void) {
+  struct empty e;
+  foo (e, 12345);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c
new file mode 100644
index 000000000..68540b8a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-10.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct b
+{
+  long long t;
+  int i;
+};
+
+struct c
+{
+  double d;
+  int i;
+};
+
+struct n
+{
+  long long ll;
+  int tt;
+  struct c d;
+  struct b h;
+  int t;
+};
+int f[sizeof(struct n)!=48?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c
new file mode 100644
index 000000000..5d01572a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct A
+{
+  long long a;
+  unsigned char b;
+};
+
+struct D
+{
+  unsigned char y;
+  struct A x;
+  unsigned char z;
+};
+
+struct E
+{
+  long long d;
+  unsigned char e;
+};
+
+struct y
+{
+  struct A b2;
+  struct D b3;
+  struct E b4;
+};
+
+int f[sizeof(struct y)!=56?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c
new file mode 100644
index 000000000..5f5764368
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-final { scan-assembler ".comm\[\t \]_x,12,2" } } */
+/* { dg-final { scan-assembler-not ".space 7" } } */
+/* PR 23071 */
+
+struct Test {
+  double D __attribute__((packed,aligned(4)));
+  short X;
+} x;
+
+struct {
+  char x;
+  struct Test t;
+} b = { 1, { 2, 3 } };
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c
new file mode 100644
index 000000000..4764831e8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c
@@ -0,0 +1,24 @@
+/* { dg-do run { target powerpc*-*-darwin* } } */
+
+/* You might think you'd need -maltivec for this, but actually you
+   don't; GCC will happily do everything in GPRs, and it still
+   tests that the ABI is correct.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#define vector __attribute__((vector_size(16)))
+
+int main(void)
+{
+  vector unsigned int v = { 100, 200, 300, 400 };
+  vector unsigned int w = { 4, 5, 6, 7 };
+  char x[64];
+  sprintf (x, "%lvu,%d,%lvu", v, 1, w);
+  if (strcmp (x, "100 200 300 400,1,4 5 6 7") != 0)
+    {
+      puts (x);
+      abort ();
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c
new file mode 100644
index 000000000..021abc8fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+struct f
+{
+  int i;
+  long long ll;
+};
+
+int f[sizeof(struct f)!=12?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c
new file mode 100644
index 000000000..d146c46ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+struct f
+{
+  long long ll;
+  int i;
+};
+
+int f[sizeof(struct f)!=16?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c
new file mode 100644
index 000000000..4965c5bd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-5.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct A
+{
+  long long a;
+  unsigned char b;
+};
+
+struct B
+{
+  struct A x;
+  unsigned char z;
+};
+
+struct C
+{
+  long d;
+  unsigned char e;
+};
+
+struct z
+{ 
+  struct A b2;
+  struct B b3;
+  struct C b4;
+};
+
+int f[sizeof(struct z)!=48?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c
new file mode 100644
index 000000000..1892e15bc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-6.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct a
+{
+  int tt;
+  long long t;
+  int i;
+};
+
+struct g
+{
+  int tt;
+  struct a d;
+  int t;
+};
+
+int f[sizeof(struct g)!=24?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c
new file mode 100644
index 000000000..8af61ddac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-7.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct b
+{
+  long long t;
+  int i;
+};
+struct h
+{
+  int tt;
+  struct b d;
+  int t;
+};
+
+int f[sizeof(struct h)!=24?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c
new file mode 100644
index 000000000..eac0d12d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+
+struct c
+{
+  double d;
+  int i;
+};
+
+struct j
+{
+  int tt;
+  struct c d;
+  int t;
+};
+
+int f[sizeof(struct j)!=24?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c
new file mode 100644
index 000000000..fa5bd017f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Wno-long-long" } */
+
+struct b
+{
+  long long t;
+  int i;
+};
+
+struct l
+{
+  int i;
+  double d;
+};
+struct k
+{
+  int tt;
+  struct l d;
+  struct b h;
+  int t;
+};
+
+int f[sizeof(struct k)!=36?-1:1];
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c
new file mode 100644
index 000000000..2f147d073
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c
@@ -0,0 +1,11 @@
+/* Check that sizeof(bool) is 4 if we don't use special options. */
+/* Matt Austern  <austern@apple.com> */
+/* { dg-do run { target { powerpc*-*-darwin* && ilp32 } } } */
+
+int dummy1[sizeof(_Bool) - 3];
+int dummy2[5 - sizeof(_Bool)];
+
+int main()
+{
+  return sizeof(_Bool) == 4 ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c
new file mode 100644
index 000000000..fdbe1a2a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-bool-2.c
@@ -0,0 +1,12 @@
+/* Check that sizeof(bool) is 1 if we use the -mone-byte-bool option. */
+/* Matt Austern  <austern@apple.com> */
+/* { dg-do run { target powerpc*-*-darwin* } } */
+/* { dg-options "-mone-byte-bool" } */
+
+int dummy1[sizeof(_Bool)];
+int dummy2[2 - sizeof(_Bool)];
+
+int main()
+{
+  return sizeof(_Bool) == 1 ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c
new file mode 100644
index 000000000..71ee094bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mcpu=G3 -funwind-tables" } */
+/* { dg-final { scan-assembler "bl save_world" } } */
+/* { dg-final { scan-assembler ".byte\t0x6b" } } */
+
+/* Verify that on Darwin, even with -mcpu=G3, __builtin_eh_return
+   saves Altivec registers using save_world, and reports their
+   location in its EH information.  */
+
+long offset;
+void *handler;
+
+extern void setup_offset(void);
+
+void foo(void)
+{
+  __builtin_unwind_init ();
+  setup_offset();
+  __builtin_eh_return (offset, handler);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c
new file mode 100644
index 000000000..8e4259af3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-longdouble.c
@@ -0,0 +1,119 @@
+/* { dg-do run { target powerpc*-*-darwin* } } */
+/* { dg-options "" } */
+/* No options so 'long long' can be used.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+typedef unsigned long long uint64_t;
+typedef uint64_t ldbits[2];
+
+union ldu 
+{
+  ldbits lb;
+  long double ld;
+};
+
+static const struct {
+  ldbits a;
+  ldbits b;
+  ldbits result;
+} single_tests[] = {
+  /* Test of values that add to near +Inf.  */
+  { { 0x7FEFFFFFFFFFFFFFLL, 0xFC88000000000000LL },
+    { 0x7C94000000000000LL, 0x0000000000000000LL },
+    { 0x7FEFFFFFFFFFFFFFLL, 0x7C80000000000000LL } },
+  { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL },
+    { 0x792FFFFFFFFFFFFFLL, 0x0000000000000000LL },
+    { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL } },
+  { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL },
+    { 0x7930000000000000LL, 0xF5DFFFFFFFFFFFFFLL },
+    /* correct result is: { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL } */
+    { 0x7FF0000000000000LL, 0x0000000000000000LL } },
+  /* Test of values that add to +Inf.  */
+  { { 0x7FEFFFFFFFFFFFFFLL, 0x7C8FFFFFFFFFFFFFLL },
+    { 0x7930000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL } },
+  /* Tests of Inf addition.  */
+  { { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0x0000000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL } },
+  { { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL } },
+  /* Test of Inf addition producing NaN.  */
+  { { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0xFFF0000000000000LL, 0x0000000000000000LL },
+    { 0x7FF8000000000000LL, 0x0000000000000000LL } },
+  /* Tests of NaN addition.  */
+  { { 0x7FF8000000000000LL, 0x0000000000000000LL },
+    { 0x0000000000000000LL, 0x0000000000000000LL },
+    { 0x7FF8000000000000LL, 0x7FF8000000000000LL } },
+  { { 0x7FF8000000000000LL, 0x0000000000000000LL },
+    { 0x7FF0000000000000LL, 0x0000000000000000LL },
+    { 0x7FF8000000000000LL, 0x7FF8000000000000LL } },
+  /* Addition of positive integers, with interesting rounding properties.  */
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0x4650000000000009LL, 0xC2FFFFFFFFFFFFF2LL },
+    /* correct result is: { 0x4691000000000001LL, 0xC32C000000000000LL } */
+    { 0x4691000000000001LL, 0xc32bfffffffffffeLL } },
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0x4650000000000008LL, 0x42F0000000000010LL },
+    { 0x4691000000000001LL, 0xC32E000000000000LL } },
+  { { 0x469FFFFFFFFFFFFFLL, 0x433FFFFFFFFFFFFFLL },
+    { 0x4340000000000000LL, 0x3FF0000000000000LL },
+    { 0x46A0000000000000LL, 0x0000000000000000LL } },
+  { { 0x469FFFFFFFFFFFFFLL, 0x433FFFFFFFFFFFFFLL },
+    { 0x4340000000000000LL, 0x0000000000000000LL },
+    { 0x46A0000000000000LL, 0xBFF0000000000000LL } },
+  /* Subtraction of integers, with cancellation.  */
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0xC690000000000000LL, 0xC330000000000000LL },
+    { 0x0000000000000000LL, 0x0000000000000000LL } },
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0xC330000000000000LL, 0x0000000000000000LL },
+    { 0x4690000000000000LL, 0x0000000000000000LL } },
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0xC330000000000000LL, 0x3FA0000000000000LL },
+    { 0x4690000000000000LL, 0x3FA0000000000000LL } },
+  { { 0x4690000000000000LL, 0x4330000000000000LL },
+    { 0xC690000000000000LL, 0x3FA0000000000000LL },
+    /* correct result is: { 0x4330000000000000LL, 0x3FA0000000000000LL } */
+    { 0x4330000000000000LL, 0x0000000000000000LL } }
+};
+    
+static int fail = 0;
+
+static void
+run_single_tests (void)
+{
+  size_t i;
+  for (i = 0; i < sizeof (single_tests) / sizeof (single_tests[0]); i++)
+    {
+      union ldu a, b, result, expected;
+      memcpy (a.lb, single_tests[i].a, sizeof (ldbits));
+      memcpy (b.lb, single_tests[i].b, sizeof (ldbits));
+      memcpy (expected.lb, single_tests[i].result, sizeof (ldbits));
+      result.ld = a.ld + b.ld;
+      if (memcmp (result.lb, expected.lb,
+		  result.ld == result.ld ? sizeof (ldbits) : sizeof (double))
+	  != 0)
+	{
+	  printf ("FAIL: %016llx %016llx + %016llx %016llx\n",
+		  a.lb[0], a.lb[1], b.lb[0], b.lb[1]);
+	  printf (" = %016llx %016llx not %016llx %016llx\n",
+		  result.lb[0], result.lb[1], expected.lb[0], expected.lb[1]);
+	  fail = 1;
+	}
+    }
+}
+
+int main(void)
+{
+  run_single_tests();
+  if (fail)
+    abort ();
+  else
+    exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c
new file mode 100644
index 000000000..14b56d082
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc64 } */
+/* { dg-options "-mcpu=G5" } */
+
+#include <stdlib.h>
+
+int  msw(long long in)
+{
+  union {
+    long long ll;
+    int  i[2];
+  } ud;
+  ud.ll = in;
+#ifdef __LITTLE_ENDIAN__
+  return ud.i[1];
+#else
+  return ud.i[0];
+#endif
+}
+
+int main()
+{
+  if (msw(1) != 0)
+    abort();
+  exit(0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c
new file mode 100644
index 000000000..9e53b7b22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-misaligned.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -mpowerpc64" } */
+
+typedef struct Nlm_rect {
+  short sh1;
+  short sh2;
+  short sh3;
+  short sh4;
+} S8;
+
+typedef struct udv_mouse_select {
+    short Action_type;
+    S8 rcClip;
+    int pgp;
+  } UDVselect;
+
+UDVselect ms;
+int UDV(S8 rcClip);
+
+int main()
+{
+    ms.rcClip.sh1 = 1;
+    ms.rcClip.sh4 = 4;
+    return UDV(ms.rcClip);
+}
+
+int UDV(S8 rcClip){
+
+	return !(rcClip.sh1 == 1 && rcClip.sh4 == 4);
+}
+	
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c
new file mode 100644
index 000000000..c45a90f0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-skip-if "need to be able to execute AltiVec" { ! { powerpc_altivec_ok && vmx_hw } } } */
+/* { dg-options "-maltivec" } */
+
+/* With altivec turned on, Darwin wants to save the world but we did not mark lr as being saved any more
+   as saving the lr is not needed for saving altivec registers.  */
+
+int main (void)
+{
+  __label__ l1;
+  void __attribute__((used)) q(void)
+  {
+    goto l1;
+  }
+
+  l1:;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-split-ld-stret.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-split-ld-stret.c
new file mode 100644
index 000000000..be4e43892
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin-split-ld-stret.c
@@ -0,0 +1,87 @@
+/* Check for Darwin m64 that we do not try to pass & return by value for a
+   struct exceeding the number of arg FPRs (the struct here straddles the 
+   split-point).  */
+/* { dg-do run { target { powerpc*-*-darwin* && lp64 } } } */
+
+extern void abort (void);
+
+/*#define DEBUG*/
+
+#ifdef DEBUG
+extern int printf (const char *, ...);
+extern int printf$LDBL128 (const char *, ...);
+#endif
+
+typedef struct fourteen {
+  long double a, b, c, d, e, f, g;
+} fourteen_t ;
+
+fourteen_t foo (fourteen_t, fourteen_t) __attribute__ ((noinline));
+
+fourteen_t 
+foo (fourteen_t aa, fourteen_t bb) 
+{
+  fourteen_t r;
+
+  r.a = aa.a + bb.a;
+  r.b = aa.b + bb.b;
+  r.c = aa.c + bb.c;
+  r.d = aa.d + bb.d;
+  r.e = aa.e + bb.e;
+  r.f = aa.f + bb.f;
+  r.g = aa.g + bb.g;
+
+#ifdef DEBUG
+#ifdef __ppc64__
+  printf
+#else
+  printf$LDBL128
+#endif	  
+	("%Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg %Lg: "
+	"%Lg %Lg %Lg %Lg %Lg %Lg %Lg\n",
+	aa.a, aa.b, aa.c, aa.d, aa.e, aa.f, aa.g,
+	bb.a, bb.b, bb.c, bb.d, bb.e, bb.f, bb.g,
+	r.a, r.b, r.c, r.d, r.e, r.f, r.g);
+ printf ("aa.g %ll16x %ll16x\nbb.g %ll16x %ll16x\n",
+		*(unsigned long long*)&aa.g,
+		*(unsigned long long*)(((char *)&aa.g)+8),
+		*(unsigned long long*)&bb.g,
+		*(unsigned long long*)(((char *)&bb.g)+8));
+ 
+#endif
+
+  __asm__ (""); /* double make sure we don't get inlined */
+  return r;
+}
+
+int
+main (void)
+{
+  fourteen_t x = { 1.L, 2.L,  3.L,  4.L,  5.L,  6.L,-12.3456789123456789L };
+  fourteen_t y = { 8.L, 9.L, 10.L, 11.L, 12.L, 13.L, 12.3456789123456789L };
+  fourteen_t z ;
+  long double zz;
+  
+  z = foo (x,y);
+  zz = x.g + y.g;
+#ifdef DEBUG
+#ifdef __ppc64__
+	printf
+#else
+	printf$LDBL128
+#endif	  
+		("  z: %Lg %Lg %Lg %Lg %Lg %Lg %Lg\n"
+		 "ret: %ll16x %ll16x\nzz : %ll16x %ll16x\n",
+		z.a, z.b, z.c, z.d, z.e, z.f, z.g,
+		*(unsigned long long*)&z.g,
+		*(unsigned long long*)(((char *)&z.g)+8),
+		*(unsigned long long*)&zz,
+		*(unsigned long long*)(((char *)&zz)+8));
+#endif
+
+  /* Yes, we really do want to do an equality test here.  */
+  if (z.g != zz)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin64-abi.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin64-abi.c
new file mode 100644
index 000000000..e185cdf0e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/darwin64-abi.c
@@ -0,0 +1,634 @@
+/* Darwin 64-bit ABI testing */
+/* { dg-do run { target { powerpc*-*-darwin* && lp64 } } } */
+/* { dg-options "-std=c99 -maltivec" } */
+
+/* Set this if 8-byte structs are being passed as integers.  */
+/* #define STRUCT8INT */
+
+#include <stdarg.h>
+#include <stdio.h>
+#include <complex.h>
+#include <altivec.h>
+
+extern void abort (void);
+
+struct s3c { char ch[3]; };
+struct ssc { short sh; char ch; };
+struct sif { int i; float f; };
+struct sfi { float f; int i; };
+struct sfii { float f; int i; int j; };
+struct sfil { float f; int i; long l; };
+struct sfif { float f; int i; float g; };
+struct sfill { float f; int i; long l, m; };
+struct sfl { float f; long l; };
+struct sfldl { float f; long l1; double d; long l2; };
+struct sfpp { float f; char *p1; char *p2; };
+
+
+struct sff { float f1, f2; };
+struct sfff { float f1, f2, f3; };
+struct sffff { float f1, f2, f3, f4; };
+
+struct sfD { float f; long double D; };
+
+struct sidi { int i1; double d; int i2; };
+
+struct sdd { double d1, d2; };
+struct sddd { double d1, d2, d3; };
+struct sdddd { double d1, d2, d3, d4; };
+struct s3d { double d[3]; };
+
+struct vr { union { int ielts[4]; float felts[4]; } elts; };
+
+typedef struct
+{
+  unsigned long gprs[32];
+  double fprs[32];
+  struct vr vrs[32];
+  unsigned char stack[1000];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+#define TESTFN(RET,NAME,PARAMS) \
+RET NAME PARAMS;  \
+RET dummy_ ## NAME PARAMS  \
+{  \
+  __asm__("b end_" #NAME "\n_" # NAME ":\n\t" SAVE_STATE "b _dummy_" # NAME "\n\tend_" #NAME ":\n\n" ); \
+}
+
+#define SAVE_STATE \
+SAVE_GPR(0)  \
+SAVE_GPR(1)  \
+SAVE_GPR(3)  \
+SAVE_GPR(4)  \
+SAVE_GPR(5)  \
+SAVE_GPR(6)  \
+SAVE_GPR(7)  \
+SAVE_GPR(8)  \
+SAVE_GPR(9)  \
+SAVE_GPR(10)  \
+SAVE_FPR(0)  \
+SAVE_FPR(1)  \
+SAVE_FPR(2)  \
+SAVE_FPR(3)  \
+SAVE_FPR(4)  \
+SAVE_FPR(5)  \
+SAVE_FPR(6)  \
+SAVE_FPR(7)  \
+SAVE_FPR(8)  \
+SAVE_FPR(9)  \
+SAVE_FPR(10)  \
+SAVE_FPR(12)  \
+SAVE_FPR(13)  \
+SAVE_VR(0)  \
+SAVE_VR(1)  \
+SAVE_VR(2)  \
+SAVE_VR(3)  \
+SAVE_VR(4)  \
+SAVE_STACK(112)  \
+SAVE_STACK(120)  \
+SAVE_STACK(128)  \
+SAVE_STACK(136)  \
+SAVE_STACK(144)  \
+
+
+#ifdef __LP64__
+#define SAVE_GPR(N) "std r" #N "," #N "*8(r25)\n\t"
+#define SAVE_FPR(N) "stfd f" #N "," #N "*8+256(r25)\n\t"
+#define SAVE_VR(N) "li r26," #N "*16+512\n\tstvx v" #N ",r25,r26\n\t"
+#define SAVE_STACK(N) "ld r26," #N "(r1)\n\tstd r26," #N "+1024(r25)\n\t"
+#else
+#define SAVE_GPR(N) "stw r" #N "," #N "*4(r25)\n\t"
+#define SAVE_FPR(N) "stfd f" #N "," #N "*8+128(r25)\n\t"
+#define SAVE_VR(N)
+#define SAVE_STACK(N)
+#endif
+
+TESTFN(void, fffi, (float x, float y, int z))
+
+#define clearall \
+__asm__ volatile ( \
+"\n\t" \
+"li r3,0x333\n\t" \
+"li r4,0x444 \n\t" \
+"li r5,0x555\n\t" \
+"li r6,0x666\n\t" \
+"li r7,0x777\n\t" \
+"li r8,0x888\n\t" \
+"li r9,0x999\n\t" \
+"li r10,0xaaa\n\t" \
+"fsub f0,f0,f0\n\t" \
+"fsub f1,f1,f1\n\t" \
+"fsub f2,f2,f2\n\t" \
+"fsub f3,f3,f3\n\t" \
+"fsub f4,f4,f4\n\t" \
+"fsub f5,f5,f5\n\t" \
+"fsub f6,f6,f6\n\t" \
+"fsub f7,f7,f7\n\t" \
+"vsubuwm v0,v0,v0\n\t" \
+"vsubuwm v1,v1,v1\n\t" \
+"vsubuwm v2,v2,v2\n\t" \
+"vsubuwm v3,v3,v3\n\t" \
+"vsubuwm v4,v4,v4\n\t" \
+: : : "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
+      "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
+      "v0", "v1", "v2", "v3", "v4" );
+
+TESTFN(void, fii, (int a, int b))
+TESTFN(void, fid, (int i, double d))
+TESTFN(void, fc, (complex float z))
+TESTFN(void, fffff, (float f1, float f2, float f3, float f4))
+TESTFN(void, fdddd, (double d1, double d2, double d3, double d4))
+TESTFN(void, f_s3c_ssc, (struct s3c s1, struct ssc s2))
+TESTFN(void, f_sff, (struct sff s))
+TESTFN(void, f_sfff, (struct sfff s))
+TESTFN(void, f_sffff, (struct sffff s))
+TESTFN(void, f_sdd, (struct sdd s))
+TESTFN(void, f_sddd, (struct sddd s))
+TESTFN(void, f_sdddd, (struct sdddd s))
+TESTFN(void, f_s3d, (struct s3d s))
+TESTFN(void, f_sif, (int i, struct sif s))
+TESTFN(void, fi_sif, (int i, struct sif s))
+TESTFN(void, fi_sif_i, (int i, struct sif s, int j))
+TESTFN(void, f_sfi, (int i, struct sfi s))
+TESTFN(void, fi_sfi, (int i, struct sfi s))
+TESTFN(void, fi_sfi_if, (int i, struct sfi s, int j, float f))
+TESTFN(void, fi_sfill, (int i, struct sfill s))
+TESTFN(void, fi_sfill_i, (int i, struct sfill s, int j))
+TESTFN(void, f_sfl, (struct sfl s))
+TESTFN(void, f_sfl_sfl_sfl_sfl_sfl, (struct sfl s1, struct sfl s2, struct sfl s3, struct sfl s4, struct sfl s5))
+TESTFN(void, fi_sff, (int i, struct sff s))
+TESTFN(void, f_sfpp_p, (struct sfpp s, char *p))
+TESTFN(void, f_sfldl, (struct sfldl s))
+TESTFN(void, fi_sff_i, (int i, struct sff s, int j))
+TESTFN(void, f_sfD_sfD_sfD_sfD_sfD, (struct sfD s1, struct sfD s2, struct sfD s3, struct sfD s4, struct sfD s5))
+TESTFN(void, fi_sidi, (int i, struct sidi s))
+TESTFN(void, fifvf_sfi_dots, (int i, float f, vector float vf, struct sfi s, ...))
+TESTFN(void, fifvf_sfii_dots, (int i, float f, vector float vf, struct sfii s, ...))
+
+int numerrs;
+
+#ifndef SKIP
+static __attribute__ ((noinline)) void
+check_gpr (int line, int reg, long expected)
+{
+  if (gparms.gprs[reg] != expected)
+    {
+      printf("%d: r%d is 0x%lx, expected 0x%lx\n",
+	     line, reg, gparms.gprs[reg], expected);
+      ++numerrs;
+    }
+}
+
+static __attribute__ ((noinline)) void
+check_gpr_double (int line, int reg, double expected)
+{
+  double tmp = *((double *) &(gparms.gprs[reg]));
+  if (tmp != expected)
+    {
+      printf("%d: r%d is %f (0x%llx), expected %f (0x%llx)\n",
+	     line, reg,
+	     tmp, *((long long *) &tmp),
+	     expected, *((long long *) &expected));
+      ++numerrs;
+    }
+}
+
+static __attribute__ ((noinline)) void
+check_gpr_float_pair (int line, int reg, float exp1, float exp2)
+{
+  float tmp1 = *((float *) &(gparms.gprs[reg]));
+  float tmp2 = *(((float *) &(gparms.gprs[reg])) + 1);
+
+  if (tmp1 != exp1 || tmp2 != exp2)
+    {
+      printf("%d: r%d is %f / %f (0x%llx), expected %f (0x%x) / %f (0x%x)\n",
+	     line, reg,
+	     tmp1, tmp2, *((long long *) &(gparms.gprs[reg])),
+	     exp1, *((int *) &exp1),
+	     exp2, *((int *) &exp2));
+      ++numerrs;
+    }
+}
+
+static __attribute__ ((noinline)) void
+check_fpr (int line, int reg, double expected)
+{
+  if (gparms.fprs[reg] != expected)
+    {
+      printf("%d: f%d is %f (0x%llx), expected %f (0x%llx)\n",
+	     line, reg,
+	     gparms.fprs[reg], *((long long *) &(gparms.fprs[reg])),
+	     expected, *((long long *) &expected));
+      ++numerrs;
+    }
+}
+
+static __attribute__ ((noinline)) void
+check_vr_int (int reg, int n1, int n2, int n3, int n4)
+{
+  if (gparms.vrs[reg].elts.ielts[0] != n1
+      || gparms.vrs[reg].elts.ielts[1] != n2
+      || gparms.vrs[reg].elts.ielts[2] != n3
+      || gparms.vrs[reg].elts.ielts[3] != n4)
+    {
+      printf("v%d is   (%d,%d,%d,%d) (0x%x,0x%x,0x%x,0x%x),\n"
+	     " expected (%d,%d,%d,%d) (0x%x,0x%x,0x%x,0x%x)\n",
+	     reg,
+	     gparms.vrs[reg].elts.ielts[0],
+	     gparms.vrs[reg].elts.ielts[1],
+	     gparms.vrs[reg].elts.ielts[2],
+	     gparms.vrs[reg].elts.ielts[3],
+	     gparms.vrs[reg].elts.ielts[0],
+	     gparms.vrs[reg].elts.ielts[1],
+	     gparms.vrs[reg].elts.ielts[2],
+	     gparms.vrs[reg].elts.ielts[3],
+	     n1, n2, n3, n4,
+	     n1, n2, n3, n4
+	     );
+      ++numerrs;
+    }
+}
+
+static __attribute__ ((noinline)) void
+check_vr_float (int reg, float f1, float f2, float f3, float f4)
+{
+  if (gparms.vrs[reg].elts.felts[0] != f1
+      || gparms.vrs[reg].elts.felts[1] != f2
+      || gparms.vrs[reg].elts.felts[2] != f3
+      || gparms.vrs[reg].elts.felts[3] != f4)
+    {
+      printf("v%d is    (%f,%f,%f,%f) (0x%x,0x%x,0x%x,0x%x),\n"
+	     " expected (%f,%f,%f,%f) (0x%x,0x%x,0x%x,0x%x)\n",
+	     reg,
+	     gparms.vrs[reg].elts.felts[0],
+	     gparms.vrs[reg].elts.felts[1],
+	     gparms.vrs[reg].elts.felts[2],
+	     gparms.vrs[reg].elts.felts[3],
+	     gparms.vrs[reg].elts.ielts[0],
+	     gparms.vrs[reg].elts.ielts[1],
+	     gparms.vrs[reg].elts.ielts[2],
+	     gparms.vrs[reg].elts.ielts[3],
+	     f1, f2, f3, f4,
+	     *((int *) &f1), *((int *) &f2), *((int *) &f3), *((int *) &f4)
+	     );
+      ++numerrs;
+    }
+}
+#endif
+
+int main (void)
+{
+  complex float cpx = 4.45f + I * 4.92f;
+  struct s3c s3c_loc;
+  struct ssc ssc_loc;
+  struct sfi sfi_loc;
+  struct sfi sfi_loc2 = { 6.3f, 0x1108 };
+  struct sfii sfii_loc;
+  struct sfii sfii_loc2 = { 6.9f, 0x1110, 0x6372 };
+  vector float vf_loc = (vector float) { 7.1f, 7.2f, 7.3f, 7.4f };
+  vector int vi_loc = (vector int) { 0xabc, 0xdef, 0xfed, 0xcba };
+
+  __asm__ ("mr r25,%0" : : "b" (&gparms) );
+
+  clearall;
+  fii(1, 2);
+  check_gpr (__LINE__, 3, 1);
+  check_gpr (__LINE__, 4, 2);
+
+  clearall;
+  fid(45, 4.5);
+  check_gpr (__LINE__, 3, 45);
+  check_fpr (__LINE__, 1, 4.5);
+
+  clearall;
+  fffi(1.2f, 3.4f, 456);
+  check_fpr(__LINE__, 1, 1.2f);
+
+  clearall;
+  fc(cpx);
+  /* Two floats are packed into r3 */
+  check_gpr_float_pair (__LINE__, 3, 4.45f, 4.92f);
+
+  clearall;
+  fffff (4.1f, 4.2f, 4.3f, 4.4f);
+  check_fpr (__LINE__, 1, 4.1f);
+  check_fpr (__LINE__, 4, 4.4f);
+
+  clearall;
+  fdddd (4.1, 4.2, 4.3, 4.4);
+  check_fpr (__LINE__, 1, 4.1);
+  check_fpr (__LINE__, 4, 4.4);
+
+  {
+    struct sff sff_loc = { 2.1f, 2.2f };
+    clearall;
+    f_sff(sff_loc);
+#ifdef STRUCT8INT
+    check_gpr_float_pair (__LINE__, 3, 2.1f, 2.2f);
+#else
+    check_fpr(__LINE__, 1, 2.1f);
+    check_fpr(__LINE__, 2, 2.2f);
+#endif
+    clearall;
+    fi_sff_i(65, sff_loc, 66);
+    check_gpr(__LINE__, 3, 65);
+#ifdef STRUCT8INT
+    check_gpr_float_pair (__LINE__, 4, 2.1f, 2.2f);
+#else
+    check_fpr(__LINE__, 1, 2.1f);
+    check_fpr(__LINE__, 2, 2.2f);
+#endif
+    check_gpr(__LINE__, 5, 66);
+  }
+
+  {
+    struct sfff sfff_loc = { 3.1f, 3.2f, 3.3f };
+    clearall;
+    f_sfff(sfff_loc);
+    check_fpr(__LINE__, 1, 3.1f);
+    check_fpr(__LINE__, 2, 3.2f);
+    check_fpr(__LINE__, 3, 3.3f);
+    clearall;
+    f_sfff(sfff_loc);
+    check_fpr(__LINE__, 1, 3.1f);
+    check_fpr(__LINE__, 2, 3.2f);
+    check_fpr(__LINE__, 3, 3.3f);
+  }
+
+  {
+    struct sffff sffff_loc = { 4.1f, 4.2f, 4.3f, 4.4f };
+    clearall;
+    f_sffff(sffff_loc);
+    check_gpr_float_pair(__LINE__, 3, 4.1f, 4.2f);
+    check_gpr_float_pair(__LINE__, 4, 4.3f, 4.4f);
+  }
+
+  {
+    struct sdd sdd_loc = { 2.1, 2.2 };
+    clearall;
+    f_sdd(sdd_loc);
+    /* 16-byte struct is passed in two GPRs.  */
+    check_gpr_double(__LINE__, 3, 2.1);
+    check_gpr_double(__LINE__, 4, 2.2);
+  }
+
+  {
+    struct sddd sddd_loc = { 3.1, 3.2, 3.3 };
+    clearall;
+    f_sddd(sddd_loc);
+    check_fpr(__LINE__, 1, 3.1);
+    check_fpr(__LINE__, 2, 3.2);
+    check_fpr(__LINE__, 3, 3.3);
+  }
+
+  {
+    struct sdddd sdddd_loc = { 4.1, 4.2, 4.3, 4.4 };
+    clearall;
+    f_sdddd(sdddd_loc);
+    check_fpr(__LINE__, 1, 4.1);
+    check_fpr(__LINE__, 2, 4.2);
+    check_fpr(__LINE__, 3, 4.3);
+    check_fpr(__LINE__, 4, 4.4);
+  }
+
+  {
+    struct s3d s3d_loc = { 89.92, 4.89, 90.9 };
+    clearall;
+    f_s3d(s3d_loc);
+    check_gpr_double (__LINE__, 3, 89.92);
+    check_gpr_double (__LINE__, 4, 4.89);
+    check_gpr_double (__LINE__, 5, 90.9);
+  }
+
+  {
+    s3c_loc.ch[0] = 'A';
+    s3c_loc.ch[1] = 'B';
+    s3c_loc.ch[2] = 'C';
+    ssc_loc.sh = 0x1234;
+    ssc_loc.ch = 'D';
+    clearall;
+    f_s3c_ssc(s3c_loc, ssc_loc);
+  }
+
+  {
+    struct sif sif_loc_n = { 334, 4.3f };
+    long floatcast;
+    floatcast = *((int *) &(sif_loc_n.f));
+    clearall;
+    fi_sif(29, sif_loc_n);
+    check_gpr (__LINE__, 3, 29);
+    check_gpr (__LINE__, 4, 334LL << 32 | floatcast);
+#ifdef STRUCT8INT
+#else
+    check_fpr (__LINE__, 1, 4.3f);
+#endif
+    clearall;
+    fi_sif_i(31, sif_loc_n, 33);
+    check_gpr (__LINE__, 3, 31);
+    check_gpr (__LINE__, 4, 334LL << 32 | floatcast);
+#ifdef STRUCT8INT
+#else
+    check_fpr (__LINE__, 1, 4.3f);
+#endif
+    check_gpr (__LINE__, 5, 33);
+  }
+
+  {
+    struct sfi sfi_loc_n = { 4.145f, 335 };
+    clearall;
+    fi_sfi(29, sfi_loc_n);
+    check_gpr (__LINE__, 3, 29);
+#ifdef STRUCT8INT
+    check_gpr (__LINE__, 4, 0x4084a3d70000014fLL);
+#else
+    check_fpr (__LINE__, 1, 4.145f);
+    check_gpr (__LINE__, 4, 335);
+#endif
+  }
+
+  {
+    struct sfi sfi_loc_n = { 4.145f, 335 };
+    clearall;
+    fi_sfi_if (29, sfi_loc_n, 65, 9.8f);
+    check_gpr (__LINE__, 3, 29);
+#ifdef STRUCT8INT
+    check_gpr (__LINE__, 4, 0x4084a3d70000014fLL);
+#else
+    check_fpr (__LINE__, 1, 4.145f);
+    check_gpr (__LINE__, 4, 335);
+#endif
+    check_gpr (__LINE__, 5, 65);
+    check_gpr (__LINE__, 6, 0x666);
+#ifdef STRUCT8INT
+    check_fpr (__LINE__, 1, 9.8f);
+#else
+    check_fpr (__LINE__, 2, 9.8f);
+#endif
+    check_gpr (__LINE__, 7, 0x777);
+  }
+
+  {
+    struct sfill sfill_loc_n = { 4.145f, 335, 10000000000LL, 20000000000LL };
+    clearall;
+    fi_sfill(29, sfill_loc_n);
+    check_gpr (__LINE__, 3, 29);
+    check_fpr (__LINE__, 1, 4.145f);
+    check_gpr (__LINE__, 4, 335);
+    check_gpr (__LINE__, 5, 10000000000LL);
+    check_gpr (__LINE__, 6, 20000000000LL);
+  }
+
+  {
+    struct sfl sfl_loc_n = { 4.145f, 335 };
+    clearall;
+    f_sfl (sfl_loc_n);
+    check_gpr_float_pair (__LINE__, 3, 4.145f, 0.0f);
+    check_gpr (__LINE__, 4, 335);
+    check_gpr (__LINE__, 5, 0x555);
+    clearall;
+    f_sfl_sfl_sfl_sfl_sfl (sfl_loc_n, sfl_loc_n, sfl_loc_n, sfl_loc_n, sfl_loc_n);
+    check_gpr_float_pair (__LINE__, 3, 4.145f, 0.0f);
+    check_gpr (__LINE__, 4, 335);
+    check_gpr (__LINE__, 6, 335);
+    check_gpr (__LINE__, 8, 335);
+    check_gpr (__LINE__, 10, 335);
+  }
+
+  {
+    struct sfldl sfldl_loc_n = { 4.145f, 335, 3.3, 336 };
+    clearall;
+    f_sfldl (sfldl_loc_n);
+    check_fpr (__LINE__, 1, 4.145f);
+    check_gpr (__LINE__, 4, 335);
+    check_fpr (__LINE__, 2, 3.3);
+    check_gpr (__LINE__, 6, 336);
+  }
+
+  {
+    char *p1 = "abc";
+    char *p2 = "def";
+    char *p3 = "ghi";
+    struct sfpp sfpp_loc_n = { 4.145f, p1, p2 };
+    clearall;
+    f_sfpp_p(sfpp_loc_n, p3);
+    check_fpr (__LINE__, 1, 4.145f);
+    check_gpr (__LINE__, 4, (long) p1);
+    check_gpr (__LINE__, 5, (long) p2);
+    check_gpr (__LINE__, 6, (long) p3);
+  }
+
+  {
+    struct sff sff_loc_n = { 4.145f, 335.3f };
+    clearall;
+    fi_sff(29, sff_loc_n);
+    check_gpr (__LINE__, 3, 29);
+#ifdef STRUCT8INT
+    check_gpr_float_pair (__LINE__, 4, 4.145f, 335.3f);
+#else
+    check_fpr (__LINE__, 1, 4.145f);
+    check_fpr (__LINE__, 2, 335.3f);
+#endif
+  }
+
+  {
+    struct sfD sfD_loc_n = { 4.145f, 335.335 };
+    clearall;
+    f_sfD_sfD_sfD_sfD_sfD (sfD_loc_n, sfD_loc_n, sfD_loc_n, sfD_loc_n, sfD_loc_n);
+    check_fpr (__LINE__, 1, 4.145f);
+    check_fpr (__LINE__, 2, 335.335);
+    check_fpr (__LINE__, 4, 4.145f);
+    check_fpr (__LINE__, 5, 335.335);
+    check_fpr (__LINE__, 7, 4.145f);
+    check_fpr (__LINE__, 10, 4.145f);
+    check_fpr (__LINE__, 13, 4.145f);
+  }
+
+  {
+    struct sidi sidi_loc_n = { 257, 4.14515, 258 };
+    clearall;
+    fi_sidi(16, sidi_loc_n);
+    check_gpr (__LINE__, 3, 16);
+    check_fpr (__LINE__, 1, 4.14515);
+    check_gpr (__LINE__, 4, 257LL << 32);
+    check_gpr (__LINE__, 5, 0x555);
+    check_gpr (__LINE__, 6, 258LL << 32);
+  }
+
+  sfi_loc.f = 5.2f;
+  sfi_loc.i = 98;
+  clearall;
+  fifvf_sfi_dots(41, 4.3f, vf_loc, sfi_loc, 4.63f, vi_loc, sfi_loc2);
+  __asm__ ("\n");
+  check_gpr (__LINE__, 3, 41);
+  check_fpr (__LINE__, 1, 4.3f); /* float skips r4 */
+  check_vr_float(2, 7.1f, 7.2f, 7.3f, 7.4f); /* vector skips r5/r6 */
+#ifdef STRUCT8INT
+  check_gpr (__LINE__, 7, 0x40a6666600000062);
+#else
+  check_fpr (__LINE__, 2, sfi_loc.f);
+  check_gpr (__LINE__, 7, sfi_loc.i);
+#endif
+  /* start of varying parameters */
+#ifdef STRUCT8INT
+  check_fpr (__LINE__, 2, 4.63f);
+#else
+  check_fpr (__LINE__, 3, 4.63f);
+#endif
+  check_gpr_double (__LINE__, 8, 4.63f);
+  /* vector takes up r9/r10 */
+  /* sfi_loc2 on stack */
+
+  clearall;
+  sfii_loc.f = 5.2f;
+  sfii_loc.i = 98;
+  sfii_loc.j = 777;
+  clearall;
+  fifvf_sfii_dots(41, 4.3f, vf_loc, sfii_loc, 4.63f, vi_loc, sfii_loc2);
+  __asm__ ("\n");
+  check_gpr (__LINE__, 3, 41);
+  check_fpr (__LINE__, 1, 4.3f); /* float skips r4 */
+  check_vr_float(2, 7.1f, 7.2f, 7.3f, 7.4f); /* vector skips r5/r6 */
+  check_fpr (__LINE__, 2, sfii_loc.f);
+  check_gpr (__LINE__, 7, sfii_loc.i);
+  check_gpr (__LINE__, 8, ((long)sfii_loc.j) << 32);
+  /* start of varying parameters */
+  check_fpr (__LINE__, 3, 4.63f);
+  check_gpr_double (__LINE__, 9, 4.63f);
+  /* vector takes up r10/stack (?) */
+  /* sfii_loc2 on stack */
+
+  if (numerrs > 0)
+    abort ();
+  return 0;
+}
+
+int dumpall()
+{
+  int i;
+
+  printf("\n");
+  for (i = 3; i <= 10; ++i)
+#ifdef __LP64__
+    printf("r%d=0x%16.16lx ", i, gparms.gprs[i]);
+#else
+    printf("r%d=0x%8.8x ", i, gparms.gprs[i]);
+#endif
+  printf("\n");
+  for (i = 1; i <= 13; ++i)
+    printf("f%d=%8.8f ", i, gparms.fprs[i]);
+  printf("\n");
+  for (i = 0; i <= 4; ++i)
+    printf("v%d=(%x,%x,%x,%x)  ", i,
+	   gparms.vrs[i].elts.ielts[0], gparms.vrs[i].elts.ielts[1],
+	   gparms.vrs[i].elts.ielts[2], gparms.vrs[i].elts.ielts[3]);
+  printf("\n");
+  for (i = 112; i < 152; ++i)
+    {
+      if (i > 112 && i % 8 == 0)
+	printf(" | ");
+      printf("%02x", gparms.stack[i]);
+    }
+  printf("\n");
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfmode_off.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfmode_off.c
new file mode 100644
index 000000000..ab711195f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfmode_off.c
@@ -0,0 +1,47 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */
+
+void w1 (void *x, double y) { *(double *) (x + 32767) = y; }
+void w2 (void *x, double y) { *(double *) (x + 32766) = y; }
+void w3 (void *x, double y) { *(double *) (x + 32765) = y; }
+void w4 (void *x, double y) { *(double *) (x + 32764) = y; }
+void w5 (void *x, double y) { *(double *) (x + 32763) = y; }
+void w6 (void *x, double y) { *(double *) (x + 32762) = y; }
+void w7 (void *x, double y) { *(double *) (x + 32761) = y; }
+void w8 (void *x, double y) { *(double *) (x + 32760) = y; }
+void w9 (void *x, double y) { *(double *) (x + 32759) = y; }
+void w10 (void *x, double y) { *(double *) (x + 32758) = y; }
+void w11 (void *x, double y) { *(double *) (x + 32757) = y; }
+void w12 (void *x, double y) { *(double *) (x + 32756) = y; }
+void w13 (void *x, double y) { *(double *) (x + 32755) = y; }
+void w14 (void *x, double y) { *(double *) (x + 32754) = y; }
+void w15 (void *x, double y) { *(double *) (x + 32753) = y; }
+void w16 (void *x, double y) { *(double *) (x + 32752) = y; }
+void w17 (void *x, double y) { *(double *) (x + 32751) = y; }
+void w18 (void *x, double y) { *(double *) (x + 32750) = y; }
+void w19 (void *x, double y) { *(double *) (x + 32749) = y; }
+void w20 (void *x, double y) { *(double *) (x + 32748) = y; }
+
+double r1 (void *x) { return *(double *) (x + 32767); }
+double r2 (void *x) { return *(double *) (x + 32766); }
+double r3 (void *x) { return *(double *) (x + 32765); }
+double r4 (void *x) { return *(double *) (x + 32764); }
+double r5 (void *x) { return *(double *) (x + 32763); }
+double r6 (void *x) { return *(double *) (x + 32762); }
+double r7 (void *x) { return *(double *) (x + 32761); }
+double r8 (void *x) { return *(double *) (x + 32760); }
+double r9 (void *x) { return *(double *) (x + 32759); }
+double r10 (void *x) { return *(double *) (x + 32758); }
+double r11 (void *x) { return *(double *) (x + 32757); }
+double r12 (void *x) { return *(double *) (x + 32756); }
+double r13 (void *x) { return *(double *) (x + 32755); }
+double r14 (void *x) { return *(double *) (x + 32754); }
+double r15 (void *x) { return *(double *) (x + 32753); }
+double r16 (void *x) { return *(double *) (x + 32752); }
+double r17 (void *x) { return *(double *) (x + 32751); }
+double r18 (void *x) { return *(double *) (x + 32750); }
+double r19 (void *x) { return *(double *) (x + 32749); }
+double r20 (void *x) { return *(double *) (x + 32748); }
+
+/* { dg-final { object-size text == 320 } } */
+/* { dg-final { cleanup-saved-temps "dfmode_off" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c
new file mode 100644
index 000000000..fcb72bdff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c
@@ -0,0 +1,26 @@
+/* Test generation of DFP instructions for POWER6.  */
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */
+
+/* { dg-final { scan-assembler-times "fneg" 1 } } */
+/* { dg-final { scan-assembler-times "fabs" 1 } } */
+/* { dg-final { scan-assembler-times "fnabs" 1 } } */
+/* { dg-final { scan-assembler-times "fmr" 0 } } */
+
+_Decimal64
+func1 (_Decimal64 a, _Decimal64 b)
+{
+  return -b;
+}
+
+_Decimal64
+func2 (_Decimal64 a, _Decimal64 b)
+{
+  return __builtin_fabsd64 (b);
+}
+
+_Decimal64
+func3 (_Decimal64 a, _Decimal64 b)
+{
+  return - __builtin_fabsd64 (b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-dd.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-dd.c
new file mode 100644
index 000000000..85da90705
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-dd.c
@@ -0,0 +1,33 @@
+/* Test generation of DFP instructions for POWER6.  */
+/* Origin: Janis Johnson <janis187@us.ibm.com> */
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -mcpu=power6" } */
+
+/* { dg-final { scan-assembler "dadd" } } */
+/* { dg-final { scan-assembler "ddiv" } } */
+/* { dg-final { scan-assembler "dmul" } } */
+/* { dg-final { scan-assembler "dsub" } } */
+/* { dg-final { scan-assembler-times "dcmpu" 6 } } */
+/* { dg-final { scan-assembler-times "dctfix" 2 } } */
+/* { dg-final { scan-assembler-times "drintn" 2 } } */
+/* { dg-final { scan-assembler-times "dcffixq" 2 } } */
+
+extern _Decimal64 a, b, c;
+extern int result;
+extern int si;
+extern long long di;
+
+void add (void) { a = b + c; }
+void div (void) { a = b / c; }
+void mul (void) { a = b * c; }
+void sub (void) { a = b - c; }
+void eq (void) { result = a == b; }
+void ne (void) { result = a != b; }
+void lt (void) { result = a < b; }
+void le (void) { result = a <= b; }
+void gt (void) { result = a > b; }
+void ge (void) { result = a >= b; }
+void ddsi (void) { si = a; }
+void dddi (void) { di = a; }
+void sidd (void) { a = si; }
+void didd (void) { a = di; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c
new file mode 100644
index 000000000..a078cc469
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c
@@ -0,0 +1,29 @@
+/* Test generation of DFP instructions for POWER6.  */
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */
+
+/* { dg-final { scan-assembler-times "fneg" 1 } } */
+/* { dg-final { scan-assembler-times "fabs" 1 } } */
+/* { dg-final { scan-assembler-times "fnabs" 1 } } */
+/* { dg-final { scan-assembler-times "fmr" 0 } } */
+
+/* These tests verify we only generate fneg, fabs and fnabs
+   instructions and no fmr's since these are done in place.  */
+
+_Decimal128
+func1 (_Decimal128 a)
+{
+  return -a;
+}
+
+_Decimal128
+func2 (_Decimal128 a)
+{
+  return __builtin_fabsd128 (a);
+}
+
+_Decimal128
+func3 (_Decimal128 a)
+{
+  return - __builtin_fabsd128 (a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c
new file mode 100644
index 000000000..e825e5cad
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c
@@ -0,0 +1,29 @@
+/* Test generation of DFP instructions for POWER6.  */
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */
+
+/* { dg-final { scan-assembler-times "fneg" 1 } } */
+/* { dg-final { scan-assembler-times "fabs" 1 } } */
+/* { dg-final { scan-assembler-times "fnabs" 1 } } */
+/* { dg-final { scan-assembler-times "fmr" 3 } } */
+
+/* These tests verify we generate fneg, fabs and fnabs and
+   associated fmr's since these are not done in place.  */
+
+_Decimal128
+func1 (_Decimal128 a, _Decimal128 b)
+{
+  return -b;
+}
+
+_Decimal128
+func2 (_Decimal128 a, _Decimal128 b)
+{
+  return __builtin_fabsd128 (b);
+}
+
+_Decimal128
+func3 (_Decimal128 a, _Decimal128 b)
+{
+  return - __builtin_fabsd128 (b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td.c
new file mode 100644
index 000000000..752ba8874
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dfp-td.c
@@ -0,0 +1,33 @@
+/* Test generation of DFP instructions for POWER6.  */
+/* Origin: Janis Johnson <janis187@us.ibm.com> */
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -mcpu=power6" } */
+
+/* { dg-final { scan-assembler "daddq" } } */
+/* { dg-final { scan-assembler "ddivq" } } */
+/* { dg-final { scan-assembler "dmulq" } } */
+/* { dg-final { scan-assembler "dsubq" } } */
+/* { dg-final { scan-assembler-times "dcmpuq" 6 } } */
+/* { dg-final { scan-assembler-times "dctfixq" 2 } } */
+/* { dg-final { scan-assembler-times "drintnq" 2 } } */
+/* { dg-final { scan-assembler-times "dcffixq" 2 } } */
+
+extern _Decimal128 a, b, c;
+extern int result;
+extern int si;
+extern long long di;
+
+void add (void) { a = b + c; }
+void div (void) { a = b / c; }
+void mul (void) { a = b * c; }
+void sub (void) { a = b - c; }
+void eq (void) { result = a == b; }
+void ne (void) { result = a != b; }
+void lt (void) { result = a < b; }
+void le (void) { result = a <= b; }
+void gt (void) { result = a > b; }
+void ge (void) { result = a >= b; }
+void tdsi (void) { si = a; }
+void tddi (void) { di = a; }
+void sitd (void) { a = si; }
+void ditd (void) { a = di; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dimode_off.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dimode_off.c
new file mode 100644
index 000000000..3d7489b59
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/dimode_off.c
@@ -0,0 +1,50 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */
+
+void w1 (void *x, long long y) { *(long long *) (x + 32767) = y; }
+void w2 (void *x, long long y) { *(long long *) (x + 32766) = y; }
+void w3 (void *x, long long y) { *(long long *) (x + 32765) = y; }
+void w4 (void *x, long long y) { *(long long *) (x + 32764) = y; }
+void w5 (void *x, long long y) { *(long long *) (x + 32763) = y; }
+void w6 (void *x, long long y) { *(long long *) (x + 32762) = y; }
+void w7 (void *x, long long y) { *(long long *) (x + 32761) = y; }
+void w8 (void *x, long long y) { *(long long *) (x + 32760) = y; }
+void w9 (void *x, long long y) { *(long long *) (x + 32759) = y; }
+void w10 (void *x, long long y) { *(long long *) (x + 32758) = y; }
+void w11 (void *x, long long y) { *(long long *) (x + 32757) = y; }
+void w12 (void *x, long long y) { *(long long *) (x + 32756) = y; }
+void w13 (void *x, long long y) { *(long long *) (x + 32755) = y; }
+void w14 (void *x, long long y) { *(long long *) (x + 32754) = y; }
+void w15 (void *x, long long y) { *(long long *) (x + 32753) = y; }
+void w16 (void *x, long long y) { *(long long *) (x + 32752) = y; }
+void w17 (void *x, long long y) { *(long long *) (x + 32751) = y; }
+void w18 (void *x, long long y) { *(long long *) (x + 32750) = y; }
+void w19 (void *x, long long y) { *(long long *) (x + 32749) = y; }
+void w20 (void *x, long long y) { *(long long *) (x + 32748) = y; }
+
+long long r1 (void *x) { return *(long long *) (x + 32767); }
+long long r2 (void *x) { return *(long long *) (x + 32766); }
+long long r3 (void *x) { return *(long long *) (x + 32765); }
+long long r4 (void *x) { return *(long long *) (x + 32764); }
+long long r5 (void *x) { return *(long long *) (x + 32763); }
+long long r6 (void *x) { return *(long long *) (x + 32762); }
+long long r7 (void *x) { return *(long long *) (x + 32761); }
+long long r8 (void *x) { return *(long long *) (x + 32760); }
+long long r9 (void *x) { return *(long long *) (x + 32759); }
+long long r10 (void *x) { return *(long long *) (x + 32758); }
+long long r11 (void *x) { return *(long long *) (x + 32757); }
+long long r12 (void *x) { return *(long long *) (x + 32756); }
+long long r13 (void *x) { return *(long long *) (x + 32755); }
+long long r14 (void *x) { return *(long long *) (x + 32754); }
+long long r15 (void *x) { return *(long long *) (x + 32753); }
+long long r16 (void *x) { return *(long long *) (x + 32752); }
+long long r17 (void *x) { return *(long long *) (x + 32751); }
+long long r18 (void *x) { return *(long long *) (x + 32750); }
+long long r19 (void *x) { return *(long long *) (x + 32749); }
+long long r20 (void *x) { return *(long long *) (x + 32748); }
+
+/* { dg-final { object-size text == 440 { target { lp64 } } } } */
+/* 32-bit test should really be == 512 bytes, see pr54110 */
+/* { dg-final { object-size text <= 640 { target { ilp32 } } } } */
+/* { dg-final { scan-assembler-not "(st|l)fd" } } */
+/* { dg-final { cleanup-saved-temps "dimode_off" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
new file mode 100644
index 000000000..2569ac843
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+
+/* Check code generation for direct move for double types.  */
+
+#define TYPE double
+#define IS_FLOAT 1
+#define NO_ALTIVEC 1
+#define VSX_REG_ATTR "ws"
+
+#include "direct-move.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
new file mode 100644
index 000000000..c8702204b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+/* Check whether we get the right bits for direct move at runtime.  */
+
+#define TYPE double
+#define IS_FLOAT 1
+#define NO_ALTIVEC 1
+#define DO_MAIN
+#define VSX_REG_ATTR "ws"
+
+#include "direct-move.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
new file mode 100644
index 000000000..524c0eead
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+/* { dg-final { scan-assembler "xscvdpspn" } } */
+/* { dg-final { scan-assembler "xscvspdpn" } } */
+
+/* Check code generation for direct move for float types.  */
+
+#define TYPE float
+#define IS_FLOAT 1
+#define NO_ALTIVEC 1
+#define VSX_REG_ATTR "ww"
+
+#include "direct-move.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
new file mode 100644
index 000000000..352e76166
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+/* Check whether we get the right bits for direct move at runtime.  */
+
+#define TYPE float
+#define IS_FLOAT 1
+#define NO_ALTIVEC 1
+#define DO_MAIN
+#define VSX_REG_ATTR "ww"
+
+#include "direct-move.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c
new file mode 100644
index 000000000..0a78f9cb2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+
+/* Check code generation for direct move for long types.  */
+
+#define TYPE long
+#define IS_INT 1
+#define NO_ALTIVEC 1
+#define VSX_REG_ATTR "d"
+
+#include "direct-move.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c
new file mode 100644
index 000000000..cee9e0e0f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+/* Check whether we get the right bits for direct move at runtime.  */
+
+#define TYPE long
+#define IS_INT 1
+#define NO_ALTIVEC 1
+#define DO_MAIN
+#define VSX_REG_ATTR "d"
+
+#include "direct-move.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
new file mode 100644
index 000000000..3067b9a8e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+/* { dg-final { scan-assembler "mtvsrd" } } */
+/* { dg-final { scan-assembler "mfvsrd" } } */
+
+/* Check code generation for direct move for vector types.  */
+
+#define TYPE vector int
+#define VSX_REG_ATTR "wa"
+
+#include "direct-move.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
new file mode 100644
index 000000000..0d8264faf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c
@@ -0,0 +1,13 @@
+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+/* Check whether we get the right bits for direct move at runtime.  */
+
+#define TYPE vector int
+#define DO_MAIN
+#define VSX_REG_ATTR "wa"
+
+#include "direct-move.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move.h b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move.h
new file mode 100644
index 000000000..6a5b7ba18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/direct-move.h
@@ -0,0 +1,188 @@
+/* Test functions for direct move support.  */
+
+#include <math.h>
+extern void abort (void);
+
+#ifndef VSX_REG_ATTR
+#define VSX_REG_ATTR "wa"
+#endif
+
+void __attribute__((__noinline__))
+copy (TYPE *a, TYPE *b)
+{
+  *b = *a;
+}
+
+#ifndef NO_GPR
+void __attribute__((__noinline__))
+load_gpr (TYPE *a, TYPE *b)
+{
+  TYPE c = *a;
+  __asm__ ("# gpr, reg = %0" : "+b" (c));
+  *b = c;
+}
+#endif
+
+#ifndef NO_FPR
+void __attribute__((__noinline__))
+load_fpr (TYPE *a, TYPE *b)
+{
+  TYPE c = *a;
+  __asm__ ("# fpr, reg = %0" : "+d" (c));
+  *b = c;
+}
+#endif
+
+#ifndef NO_ALTIVEC
+void __attribute__((__noinline__))
+load_altivec (TYPE *a, TYPE *b)
+{
+  TYPE c = *a;
+  __asm__ ("# altivec, reg = %0" : "+v" (c));
+  *b = c;
+}
+#endif
+
+#ifndef NO_VSX
+void __attribute__((__noinline__))
+load_vsx (TYPE *a, TYPE *b)
+{
+  TYPE c = *a;
+  __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));
+  *b = c;
+}
+#endif
+
+#ifndef NO_GPR_TO_VSX
+void __attribute__((__noinline__))
+load_gpr_to_vsx (TYPE *a, TYPE *b)
+{
+  TYPE c = *a;
+  TYPE d;
+  __asm__ ("# gpr, reg = %0" : "+b" (c));
+  d = c;
+  __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (d));
+  *b = d;
+}
+#endif
+
+#ifndef NO_VSX_TO_GPR
+void __attribute__((__noinline__))
+load_vsx_to_gpr (TYPE *a, TYPE *b)
+{
+  TYPE c = *a;
+  TYPE d;
+  __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c));
+  d = c;
+  __asm__ ("# gpr, reg = %0" : "+b" (d));
+  *b = d;
+}
+#endif
+
+#ifdef DO_MAIN
+typedef void (fn_type (TYPE *, TYPE *));
+
+struct test_struct {
+  fn_type *func;
+  const char *name;
+};
+
+const struct test_struct test_functions[] = {
+  { copy,		"copy"		  },
+#ifndef NO_GPR
+  { load_gpr,		"load_gpr"	  },
+#endif
+#ifndef NO_FPR
+  { load_fpr,		"load_fpr"	  },
+#endif
+#ifndef NO_ALTIVEC
+  { load_altivec,	"load_altivec"	  },
+#endif
+#ifndef NO_VSX
+  { load_vsx,		"load_vsx"	  },
+#endif
+#ifndef NO_GPR_TO_VSX
+  { load_gpr_to_vsx,	"load_gpr_to_vsx" },
+#endif
+#ifndef NO_VSX_TO_GPR
+  { load_vsx_to_gpr,	"load_vsx_to_gpr" },
+#endif
+};
+
+/* Test a given value for each of the functions.  */
+void __attribute__((__noinline__))
+test_value (TYPE a)
+{
+  long i;
+
+  for (i = 0; i < sizeof (test_functions) / sizeof (test_functions[0]); i++)
+    {
+      TYPE b;
+
+      test_functions[i].func (&a, &b);
+      if (memcmp ((void *)&a, (void *)&b, sizeof (TYPE)) != 0)
+	abort ();
+    }
+}
+
+/* Main program.  */
+int
+main (void)
+{
+  long i,j;
+  union {
+    TYPE value;
+    unsigned char bytes[sizeof (TYPE)];
+  } u;
+
+#if IS_INT
+  TYPE value = (TYPE)-5;
+  for (i = 0; i < 12; i++)
+    {
+      test_value (value);
+      value++;
+    }
+
+  for (i = 0; i < 8*sizeof (TYPE); i++)
+    test_value (((TYPE)1) << i);
+
+#elif IS_UNS
+  TYPE value = (TYPE)0;
+  for (i = 0; i < 10; i++)
+    {
+      test_value (value);
+      test_value (~ value);
+      value++;
+    }
+
+  for (i = 0; i < 8*sizeof (TYPE); i++)
+    test_value (((TYPE)1) << i);
+
+#elif IS_FLOAT
+  TYPE value = (TYPE)-5;
+  for (i = 0; i < 12; i++)
+    {
+      test_value (value);
+      value++;
+    }
+
+  test_value ((TYPE)3.1415926535);
+  test_value ((TYPE)1.23456);
+  test_value ((TYPE)(-0.0));
+  test_value ((TYPE)NAN);
+  test_value ((TYPE)+INFINITY);
+  test_value ((TYPE)-INFINITY);
+#else
+
+  for (j = 0; j < 10; j++)
+    {
+      for (i = 0; i < sizeof (TYPE); i++)
+	u.bytes[i] = (unsigned char) (random () >> 4);
+
+      test_value (u.value);
+    }
+#endif
+
+  return 0;
+}
+#endif
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/doloop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/doloop-1.c
new file mode 100644
index 000000000..d4bc45415
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/doloop-1.c
@@ -0,0 +1,17 @@
+/* Make sure both loops are recognized as doloops.
+   If so, "bdnz" will be generated on ppc; if not,
+   you will get "ble" or "blt" or "bge".  */
+
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+void foo (int count, char* pca, char* pcb) {
+    int i;
+    if (count > 10)
+        for (i = 0; i < count; ++i)
+            pcb += i;
+    else
+        for (i = 0; i < count; ++i)
+            pca += i;
+    *pca = *pcb;
+}
+/* { dg-final { scan-assembler "bdnz" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-1.c
new file mode 100644
index 000000000..76a0e4a22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-1.c
@@ -0,0 +1,14 @@
+/* Test functioning of command option -mno-isel */
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-options "-O2 -mno-isel" } */
+
+/* { dg-final { scan-assembler-not "isel" } } */
+
+int
+foo (int x, int y)
+{
+  if (x < y)
+    return x;
+  else
+    return y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-ord-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-ord-1.c
new file mode 100644
index 000000000..c4f276990
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-ord-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-eabi* } } */
+/* { dg-options "-O -ftrapping-math -fdump-rtl-final" } */
+
+int isgreater (float f1, float f2)
+{
+  int r = (f1 > f2);
+  return !r ?  -1 : 1;
+}
+
+int isgreaterequal (float f1, float f2)
+{
+  int r = (f1 >= f2);
+  return !r ?  -1 : 1;
+}
+
+int isless (float f1, float f2)
+{
+  int r = (f1 < f2);
+  return !r ?  -1 : 1;
+}
+
+int islessequal (float f1, float f2)
+{
+  int r = (f1 <= f2);
+  return !r ?  -1 : 1;
+}
+
+/* { dg-final { scan-rtl-dump-not "__unordsf2" "final" } } */
+/* { dg-final { cleanup-rtl-dump "final" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-ord-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-ord-2.c
new file mode 100644
index 000000000..a6b5c2973
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-ord-2.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-eabi* } } */
+/* { dg-options "-O -fno-trapping-math -fdump-rtl-final" } */
+
+int isgreater (float f1, float f2)
+{
+  int r = (f1 > f2);
+  return !r ?  -1 : 1;
+}
+
+int isgreaterequal (float f1, float f2)
+{
+  int r = (f1 >= f2);
+  return !r ?  -1 : 1;
+}
+
+int isless (float f1, float f2)
+{
+  int r = (f1 < f2);
+  return !r ?  -1 : 1;
+}
+
+int islessequal (float f1, float f2)
+{
+  int r = (f1 <= f2);
+  return !r ?  -1 : 1;
+}
+
+/* { dg-final { scan-rtl-dump-not "__unordsf2" "final" } } */
+/* { dg-final { cleanup-rtl-dump "final" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-unord-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-unord-1.c
new file mode 100644
index 000000000..0cd75d8d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-unord-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-eabi* } } */
+/* { dg-options "-O -ftrapping-math -fdump-rtl-final" } */
+
+int isgreater (float f1, float f2)
+{
+  int r = __builtin_isgreater (f1, f2);
+  return !r ?  -1 : 1;
+}
+
+int isgreaterequal (float f1, float f2)
+{
+  int r = __builtin_isgreaterequal (f1, f2);
+  return !r ?  -1 : 1;
+}
+
+int isless (float f1, float f2)
+{
+  int r = __builtin_isless (f1, f2);
+  return !r ?  -1 : 1;
+}
+
+int islessequal (float f1, float f2)
+{
+  int r = __builtin_islessequal (f1, f2);
+  return !r ?  -1 : 1;
+}
+
+/* { dg-final { scan-rtl-dump-times "__unordsf2" 4 "final" } } */
+/* { dg-final { cleanup-rtl-dump "final" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-unord-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-unord-2.c
new file mode 100644
index 000000000..51b1316f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/e500-unord-2.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-eabi* } } */
+/* { dg-options "-O -fno-trapping-math -fdump-rtl-final" } */
+
+int isgreater (float f1, float f2)
+{
+  int r = __builtin_isgreater (f1, f2);
+  return !r ?  -1 : 1;
+}
+
+int isgreaterequal (float f1, float f2)
+{
+  int r = __builtin_isgreaterequal (f1, f2);
+  return !r ?  -1 : 1;
+}
+
+int isless (float f1, float f2)
+{
+  int r = __builtin_isless (f1, f2);
+  return !r ?  -1 : 1;
+}
+
+int islessequal (float f1, float f2)
+{
+  int r = __builtin_islessequal (f1, f2);
+  return !r ?  -1 : 1;
+}
+
+/* { dg-final { scan-rtl-dump-not "__unordsf2" "final" } } */
+/* { dg-final { cleanup-rtl-dump "final" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ehreturn.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ehreturn.c
new file mode 100644
index 000000000..558db4238
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ehreturn.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mminimal-toc -mno-multiple" } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+
+void foo ()
+{
+  long l; void *p;
+  volatile int x;
+
+  __builtin_unwind_init ();
+  x = 12;
+  __builtin_eh_return (l, p);
+}
+
+/* { dg-final { scan-assembler "(st\[wd\]|evstdd) 30," } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/fusion.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/fusion.c
new file mode 100644
index 000000000..60e635972
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/fusion.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */
+
+#define LARGE 0x12345
+
+int fusion_uchar (unsigned char *p){ return p[LARGE]; }
+int fusion_schar (signed char *p){ return p[LARGE]; }
+int fusion_ushort (unsigned short *p){ return p[LARGE]; }
+int fusion_short (short *p){ return p[LARGE]; }
+int fusion_int (int *p){ return p[LARGE]; }
+unsigned fusion_uns (unsigned *p){ return p[LARGE]; }
+
+vector double fusion_vector (vector double *p) { return p[2]; }
+
+/* { dg-final { scan-assembler-times "gpr load fusion"    6 } } */
+/* { dg-final { scan-assembler-times "vector load fusion" 1 } } */
+/* { dg-final { scan-assembler-times "lbz"                2 } } */
+/* { dg-final { scan-assembler-times "extsb"              1 } } */
+/* { dg-final { scan-assembler-times "lhz"                2 } } */
+/* { dg-final { scan-assembler-times "extsh"              1 } } */
+/* { dg-final { scan-assembler-times "lwz"                2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/gcse-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/gcse-1.c
new file mode 100644
index 000000000..799cde1dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/gcse-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { *-*-linux* && ilp32 } } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "@ha" 1 } } */
+
+
+/* Test for PR 7003, address of array loaded int register
+   twice without any need. */
+
+extern const char flags [256];
+
+unsigned char * f (unsigned char * s) {
+  while (flags[*++s]);
+  while (!flags[*++s]);
+  return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c
new file mode 100644
index 000000000..e58816a7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_htm_ok } */
+/* { dg-options "-O2 -mhtm" } */
+
+/* { dg-final { scan-assembler-times "tbegin\\." 1 } } */
+/* { dg-final { scan-assembler-times "tend\\." 2 } } */
+/* { dg-final { scan-assembler-times "tabort\\." 2 } } */
+/* { dg-final { scan-assembler-times "tabortdc\\." 1 } } */
+/* { dg-final { scan-assembler-times "tabortdci\\." 1 } } */
+/* { dg-final { scan-assembler-times "tabortwc\\." 1 } } */
+/* { dg-final { scan-assembler-times "tabortwci\\." 2 } } */
+/* { dg-final { scan-assembler-times "tcheck\\." 1 } } */
+/* { dg-final { scan-assembler-times "trechkpt\\." 1 } } */
+/* { dg-final { scan-assembler-times "treclaim\\." 1 } } */
+/* { dg-final { scan-assembler-times "tsr\\." 3 } } */
+/* { dg-final { scan-assembler-times "mfspr" 4 } } */
+/* { dg-final { scan-assembler-times "mtspr" 4 } } */
+
+void use_builtins (long *p, char code, long *a, long *b)
+{
+  p[0] = __builtin_tbegin (0);
+  p[1] = __builtin_tend (0);
+  p[2] = __builtin_tendall ();
+  p[3] = __builtin_tabort (0);
+  p[4] = __builtin_tabort (code);
+
+  p[5] = __builtin_tabortdc (0xf, a[5], b[5]);
+  p[6] = __builtin_tabortdci (0xf, a[6], 13);
+  p[7] = __builtin_tabortwc (0xf, a[7], b[7]);
+  p[8] = __builtin_tabortwci (0xf, a[8], 13);
+
+  p[9] = __builtin_tcheck (5);
+  p[10] = __builtin_trechkpt ();
+  p[11] = __builtin_treclaim (0);
+  p[12] = __builtin_tresume ();
+  p[13] = __builtin_tsuspend ();
+  p[14] = __builtin_tsr (0);
+  p[15] = __builtin_ttest (); /* This expands to a tabortwci.  */
+
+
+  p[16] = __builtin_get_texasr ();
+  p[17] = __builtin_get_texasru ();
+  p[18] = __builtin_get_tfhar ();
+  p[19] = __builtin_get_tfiar ();
+
+  __builtin_set_texasr (a[20]);
+  __builtin_set_texasru (a[21]);
+  __builtin_set_tfhar (a[22]);
+  __builtin_set_tfiar (a[23]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c
new file mode 100644
index 000000000..5e92814b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c
@@ -0,0 +1,32 @@
+/* This checks the availability of the XL compiler intrinsics for
+   transactional execution with the expected prototypes.  */
+
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_htm_ok } */
+/* { dg-options "-O2 -mhtm" } */
+
+#include <htmxlintrin.h>
+
+void
+foo (void *TM_buff, long *result, unsigned char *code)
+{
+  *result++ = __TM_simple_begin ();
+  *result++ = __TM_begin (TM_buff);
+  *result++ = __TM_end ();
+  __TM_abort ();
+  __TM_named_abort (*code);
+  __TM_resume ();
+  __TM_suspend ();
+  *result++ = __TM_is_user_abort (TM_buff);
+  *result++ = __TM_is_named_user_abort (TM_buff, code);
+  *result++ = __TM_is_illegal (TM_buff);
+  *result++ = __TM_is_footprint_exceeded (TM_buff);
+  *result++ = __TM_nesting_depth (TM_buff);
+  *result++ = __TM_is_nested_too_deep (TM_buff);
+  *result++ = __TM_is_conflict (TM_buff);
+  *result++ = __TM_is_failure_persistent (TM_buff);
+  *result++ = __TM_failure_address (TM_buff);
+  *result++ = __TM_failure_code (TM_buff);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/indexed-addr.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/indexed-addr.c
new file mode 100644
index 000000000..6933b23e0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/indexed-addr.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler "3,\.*3,\.*4" } }
+
+/* Ensure that indexed address are output with base address in rA position
+   and index in rB position.  */
+
+char
+do_one (char *base, unsigned long offset)
+{
+  return base[offset];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c
new file mode 100644
index 000000000..75733d64b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/le-altivec-consts.c
@@ -0,0 +1,253 @@
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mabi=altivec -O2" } */
+
+/* Check that "easy" AltiVec constants are correctly synthesized.  */
+
+extern void abort (void);
+
+typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
+typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
+typedef __attribute__ ((vector_size (16))) unsigned int v4si;
+
+typedef __attribute__((aligned(16))) char c16[16];
+typedef __attribute__((aligned(16))) short s8[8];
+typedef __attribute__((aligned(16))) int i4[4];
+
+#define V16QI(V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16)	\
+  v16qi v = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16};	\
+  static c16 w = {V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16}; \
+  check_v16qi (v, w);
+
+#define V8HI(V1,V2,V3,V4,V5,V6,V7,V8)		\
+  v8hi v = {V1,V2,V3,V4,V5,V6,V7,V8};		\
+  static s8 w = {V1,V2,V3,V4,V5,V6,V7,V8};	\
+  check_v8hi (v, w);
+
+#define V4SI(V1,V2,V3,V4)	\
+  v4si v = {V1,V2,V3,V4};	\
+  static i4 w = {V1,V2,V3,V4};	\
+  check_v4si (v, w);
+
+
+/* Use three different check functions for each mode-instruction pair.
+   The callers have no typecasting and no addressable vectors, to make
+   the test more robust.  */
+
+void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+void __attribute__ ((noinline)) check_v8hi (v8hi v1, short *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+void __attribute__ ((noinline)) check_v4si (v4si v1, int *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+
+/* V16QI tests.  */
+
+void v16qi_vspltisb ()
+{
+  V16QI (15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15);
+}
+
+void v16qi_vspltisb_neg ()
+{
+  V16QI (-5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5);
+}
+
+void v16qi_vspltisb_addself ()
+{
+  V16QI (30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30);
+}
+
+void v16qi_vspltisb_neg_addself ()
+{
+  V16QI (-24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24);
+}
+
+void v16qi_vspltish ()
+{
+  V16QI (15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0);
+}
+
+void v16qi_vspltish_addself ()
+{
+  V16QI (30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0);
+}
+
+void v16qi_vspltish_neg ()
+{
+  V16QI (-5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1);
+}
+
+void v16qi_vspltisw ()
+{
+  V16QI (15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0);
+}
+
+void v16qi_vspltisw_addself ()
+{
+  V16QI (30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0);
+}
+
+void v16qi_vspltisw_neg ()
+{
+  V16QI (-5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1);
+}
+
+
+/* V8HI tests. */
+
+void v8hi_vspltisb ()
+{
+  V8HI (0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F);
+}
+
+void v8hi_vspltisb_addself ()
+{
+  V8HI (0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E);
+}
+
+void v8hi_vspltisb_neg ()
+{
+  V8HI (0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB);
+}
+
+void v8hi_vspltish ()
+{
+  V8HI (15, 15, 15, 15, 15, 15, 15, 15);
+}
+
+void v8hi_vspltish_neg ()
+{
+  V8HI (-5, -5, -5, -5, -5, -5, -5, -5);
+}
+
+void v8hi_vspltish_addself ()
+{
+  V8HI (30, 30, 30, 30, 30, 30, 30, 30);
+}
+
+void v8hi_vspltish_neg_addself ()
+{
+  V8HI (-24, -24, -24, -24, -24, -24, -24, -24);
+}
+
+void v8hi_vspltisw ()
+{
+  V8HI (15, 0, 15, 0, 15, 0, 15, 0);
+}
+
+void v8hi_vspltisw_addself ()
+{
+  V8HI (30, 0, 30, 0, 30, 0, 30, 0);
+}
+
+void v8hi_vspltisw_neg ()
+{
+  V8HI (-5, -1, -5, -1, -5, -1, -5, -1);
+}
+
+/* V4SI tests. */
+
+void v4si_vspltisb ()
+{
+  V4SI (0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F);
+}
+
+void v4si_vspltisb_addself ()
+{
+  V4SI (0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E);
+}
+
+void v4si_vspltisb_neg ()
+{
+  V4SI (0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB);
+}
+
+void v4si_vspltish ()
+{
+  V4SI (0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F);
+}
+
+void v4si_vspltish_addself ()
+{
+  V4SI (0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E);
+}
+
+void v4si_vspltish_neg ()
+{
+  V4SI (0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB);
+}
+
+void v4si_vspltisw ()
+{
+  V4SI (15, 15, 15, 15);
+}
+
+void v4si_vspltisw_neg ()
+{
+  V4SI (-5, -5, -5, -5);
+}
+
+void v4si_vspltisw_addself ()
+{
+  V4SI (30, 30, 30, 30);
+}
+
+void v4si_vspltisw_neg_addself ()
+{
+  V4SI (-24, -24, -24, -24);
+}
+
+
+
+int main ()
+{
+  v16qi_vspltisb ();
+  v16qi_vspltisb_neg ();
+  v16qi_vspltisb_addself ();
+  v16qi_vspltisb_neg_addself ();
+  v16qi_vspltish ();
+  v16qi_vspltish_addself ();
+  v16qi_vspltish_neg ();
+  v16qi_vspltisw ();
+  v16qi_vspltisw_addself ();
+  v16qi_vspltisw_neg ();
+
+  v8hi_vspltisb ();
+  v8hi_vspltisb_addself ();
+  v8hi_vspltisb_neg ();
+  v8hi_vspltish ();
+  v8hi_vspltish_neg ();
+  v8hi_vspltish_addself ();
+  v8hi_vspltish_neg_addself ();
+  v8hi_vspltisw ();
+  v8hi_vspltisw_addself ();
+  v8hi_vspltisw_neg ();
+
+  v4si_vspltisb ();
+  v4si_vspltisb_addself ();
+  v4si_vspltisb_neg ();
+  v4si_vspltish ();
+  v4si_vspltish_addself ();
+  v4si_vspltish_neg ();
+  v4si_vspltisw ();
+  v4si_vspltisw_neg ();
+  v4si_vspltisw_addself ();
+  v4si_vspltisw_neg_addself ();
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "lvx" { target { powerpc*le-*-* } } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/leaf.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/leaf.c
new file mode 100644
index 000000000..079418930
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/leaf.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target rs6000-*-* } }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\tstwu 1,-\[0-9\]*(1)\n" } } */
+
+int Leaf (int i)
+{
+  return i + 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-1.c
new file mode 100644
index 000000000..000ebcadf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-1.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power5" } */
+/* { dg-final { scan-assembler-times "nop" 3 } } */
+
+/* Test generation of nops in load hit store situation.  */
+
+typedef union {
+  double val;
+  struct {
+    unsigned int w1;
+    unsigned int w2;
+  };
+} words;
+
+unsigned int f (double d, words *u)
+{
+  u->val = d;
+  return u->w2;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-2.c
new file mode 100644
index 000000000..748011f8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power6 -msched-groups" } */
+/* { dg-final { scan-assembler "ori 1,1,0" } } */
+
+/* Test generation of group ending nop in load hit store situation.  */
+typedef union {
+  double val;
+  struct {
+    unsigned int w1;
+    unsigned int w2;
+  };
+} words;
+
+unsigned int f (double d)
+{
+  words u;
+  u.val = d;
+  return u.w2;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-3.c
new file mode 100644
index 000000000..31677ed66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/lhs-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "ori 2,2,0" } } */
+
+/* Test generation of group ending nop in load hit store situation.  */
+typedef union {
+  double val;
+  struct {
+    unsigned int w1;
+    unsigned int w2;
+  };
+} words;
+
+unsigned int f (double d)
+{
+  words u;
+  u.val = d;
+  return u.w2;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/longcall-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/longcall-1.c
new file mode 100644
index 000000000..e7187f17a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/longcall-1.c
@@ -0,0 +1,13 @@
+/* PR target/35100 */
+/* { dg-do compile { target fpic } } */
+/* { dg-options "-fpic" } */
+
+void foo (void) __attribute__((__longcall__));
+int baz (void) __attribute__((__longcall__));
+
+int
+bar (void)
+{
+  foo ();
+  return baz () + 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/loop_align.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/loop_align.c
new file mode 100644
index 000000000..b49980ab4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/loop_align.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7 -falign-functions=16" } */
+/* { dg-final { scan-assembler ".p2align 5,,31" } } */
+
+void f(double *a, double *b, double *c, int n) {
+  int i;
+  for (i=0; i < n; i++)
+    a[i] = b[i] + c[i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c
new file mode 100644
index 000000000..9e0b8656c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/macho-lo-sum.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -mpowerpc64 -mdynamic-no-pic" } */
+
+long long knight_attacks[64];
+long long InitializeAttackBoards(void);
+
+int main()
+{
+	return InitializeAttackBoards();
+}
+
+long long InitializeAttackBoards(void)
+{
+
+  int i,j;
+
+  for(i=0;i<64;i++) { }
+
+  for(i=0;i<64;i++) {
+    knight_attacks[i]=0;
+    for(j=0;j<8;j++) {
+      knight_attacks[i]= 0;
+    }
+  }
+
+  return knight_attacks[0];
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/medium_offset.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/medium_offset.c
new file mode 100644
index 000000000..f29eba08c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/medium_offset.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O" } */
+/* { dg-final { scan-assembler-not "\\+4611686018427387904" } } */
+
+static int x;
+
+unsigned long
+foo (void)
+{
+  return ((unsigned long) &x) - 0xc000000000000000;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c
new file mode 100644
index 000000000..7f2d3d3ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power6x -mmfpgpr" } */
+/* { dg-final { scan-assembler "mffgpr" } } */
+/* { dg-final { scan-assembler "mftgpr" } } */
+
+/* Test that we generate the instructions to move between the GPR and FPR
+   registers under power6x.  */
+
+extern long return_long (void);
+extern double return_double (void);
+
+double return_double2 (void)
+{
+  return (double) return_long ();
+}
+
+long return_long2 (void)
+{
+  return (long) return_double ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-1.c
new file mode 100644
index 000000000..94b7988ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
+/* { dg-options "-O2 -mno-pointers-to-nested-functions" } */
+
+int
+call_ptr (int (func) (void))
+{
+  return func () + 1;
+}
+
+/* { dg-final { scan-assembler-not "ld 11,16(3)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-2.c
new file mode 100644
index 000000000..214a9dfb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
+/* { dg-options "-O2 -mpointers-to-nested-functions" } */
+
+int
+call_ptr (int (func) (void))
+{
+  return func () + 1;
+}
+
+/* { dg-final { scan-assembler "ld 11,16" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-3.c
new file mode 100644
index 000000000..9cc830909
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/no-r11-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
+/* { dg-options "-O2 -mno-pointers-to-nested-functions" } */
+
+extern void ext_call (int (func) (void));
+
+int
+outer_func (int init)	/* { dg-error "-mno-pointers-to-nested-functions option" "" } */
+{
+  int value = init;
+
+  int inner (void)
+  {
+    return ++value;
+  }
+
+  ext_call (inner);
+  return value;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c
new file mode 100644
index 000000000..10cce470a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c
@@ -0,0 +1,40 @@
+/* { dg-do compile { target powerpc*-apple-darwin* } } */
+/* { dg-options "-S" } */
+
+typedef void PF (void);
+
+static void f(void) {
+}
+
+void f1(void) {
+}
+
+extern void f2(void) {
+}
+
+static void f3(void);
+
+void pe(void)
+{
+}
+
+PF* g (void) { f(); return f; }
+PF* x (void) { return f1; }
+PF* y (void) { f2(); return f2; }
+PF* z (void) { return f3; }
+PF* w (void) { pe(); return pe; }
+
+int main()
+{
+	(*g())();
+	(*x())();
+	(*y())();
+	(*z())();
+	(*w())();
+	return 0;
+}
+
+void f3(void) {
+}
+
+/* { dg-final { scan-assembler-not "non_lazy_ptr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c
new file mode 100644
index 000000000..7337e99b1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c
@@ -0,0 +1,36 @@
+/* { dg-require-effective-target stdint_types } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mcpu=power5" } */
+
+/* This is a clone of gcc-dg/optimize-bswapdi-1.c, redone to use load and stores
+   to test whether lwbrx/stwbrx is generated for normal power systems.  */
+
+#include <stdint.h>
+#define __const_swab64(x) ((uint64_t)(			                        \
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |             \
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |		\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |		\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |		\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |		\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |		\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |		\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+
+/* This byte swap implementation is used by the Linux kernel and the
+   GNU C library.  */
+
+uint64_t
+swap64_load (uint64_t *in)
+{
+  return __const_swab64 (*in);
+}
+
+void
+swap64_store (uint64_t *out, uint64_t in)
+{
+  *out = __const_swab64 (in);
+}
+
+/* { dg-final { scan-assembler-times "lwbrx" 2 } } */
+/* { dg-final { scan-assembler-times "stwbrx" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c
new file mode 100644
index 000000000..9dcd824c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c
@@ -0,0 +1,36 @@
+/* { dg-require-effective-target stdint_types } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* This is a clone of gcc-dg/optimize-bswapdi-1.c, redone to use load and stores
+   to test whether ldbrx/stdbrx is generated for power7.  */
+
+#include <stdint.h>
+#define __const_swab64(x) ((uint64_t)(			                        \
+	(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) |             \
+	(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) |		\
+	(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) |		\
+	(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) |		\
+	(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) |		\
+	(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) |		\
+	(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) |		\
+	(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
+
+
+/* This byte swap implementation is used by the Linux kernel and the
+   GNU C library.  */
+
+uint64_t
+swap64_load (uint64_t *in)
+{
+  return __const_swab64 (*in);
+}
+
+void
+swap64_store (uint64_t *out, uint64_t in)
+{
+  *out = __const_swab64 (in);
+}
+
+/* { dg-final { scan-assembler "ldbrx" } } */
+/* { dg-final { scan-assembler "stdbrx" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapsi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapsi-2.c
new file mode 100644
index 000000000..34cc8236f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/optimize-bswapsi-2.c
@@ -0,0 +1,55 @@
+/* { dg-require-effective-target stdint_types } */
+/* { dg-options "-O2 -mcpu=power5" } */
+
+#include <stdint.h>
+
+/* This is a clone of gcc-dg/optimize-bswapsi-1.c, redone to use load and stores
+   to test whether lwbrx/stwbrx is generated for normal power systems.  */
+
+#define __const_swab32(x) ((uint32_t)(				      \
+        (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) |            \
+        (((uint32_t)(x) & (uint32_t)0x0000ff00UL) <<  8) |            \
+        (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >>  8) |            \
+        (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
+
+/* This byte swap implementation is used by the Linux kernel and the
+   GNU C library.  */
+
+uint32_t
+swap32_a_load (uint32_t *in)
+{
+  return __const_swab32 (*in);
+}
+
+/* The OpenSSH byte swap implementation.  */
+uint32_t
+swap32_b_load (uint32_t *in)
+{
+  uint32_t a;
+
+  a = (*in << 16) | (*in >> 16);
+  a = ((a & 0x00ff00ff) << 8) | ((a & 0xff00ff00) >> 8);
+
+  return a;
+}
+
+void
+swap32_a_store (uint32_t *out, uint32_t in)
+{
+  *out = __const_swab32 (in);
+}
+
+/* The OpenSSH byte swap implementation.  */
+void
+swap32_b_store (uint32_t *out, uint32_t in)
+{
+  uint32_t a;
+
+  a = (in << 16) | (in >> 16);
+  a = ((a & 0x00ff00ff) << 8) | ((a & 0xff00ff00) >> 8);
+
+  *out = a;
+}
+
+/* { dg-final { scan-assembler-times "lwbrx" 2 } } */
+/* { dg-final { scan-assembler-times "stwbrx" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/outofline_rnreg.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/outofline_rnreg.c
new file mode 100644
index 000000000..a80a46f40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/outofline_rnreg.c
@@ -0,0 +1,15 @@
+/* Test that registers used by out of line restore functions does not get renamed.
+   AIX, and 64 bit targets uses r1, which rnreg stays away from.
+   Linux 32 bits targets uses r11, which is susceptible to be renamed */
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-Os -frename-registers -fdump-rtl-rnreg" } */
+/* "* renamed" or "* no available better choice" results are not acceptable */
+/* { dg-final { scan-rtl-dump-not "Register 11 in insn *" "rnreg" { target powerpc*-*-linux* } } } */
+/* { dg-final { cleanup-rtl-dump "rnreg" } } */
+int
+calc (int j)
+{
+  if (j<=1) return 1;
+  return calc(j-1)*(j+1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c
new file mode 100644
index 000000000..f0a68ec88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c
@@ -0,0 +1,65 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */
+
+#ifndef TYPE
+#define TYPE long long
+#endif
+
+#ifndef SIGN_TYPE
+#define SIGN_TYPE signed TYPE
+#endif
+
+#ifndef UNS_TYPE
+#define UNS_TYPE unsigned TYPE
+#endif
+
+typedef vector SIGN_TYPE v_sign;
+typedef vector UNS_TYPE  v_uns;
+
+v_sign sign_add (v_sign a, v_sign b)
+{
+  return a + b;
+}
+
+v_sign sign_sub (v_sign a, v_sign b)
+{
+  return a - b;
+}
+
+v_sign sign_shift_left (v_sign a, v_sign b)
+{
+  return a << b;
+}
+
+v_sign sign_shift_right (v_sign a, v_sign b)
+{
+  return a >> b;
+}
+
+v_uns uns_add (v_uns a, v_uns b)
+{
+  return a + b;
+}
+
+v_uns uns_sub (v_uns a, v_uns b)
+{
+  return a - b;
+}
+
+v_uns uns_shift_left (v_uns a, v_uns b)
+{
+  return a << b;
+}
+
+v_uns uns_shift_right (v_uns a, v_uns b)
+{
+  return a >> b;
+}
+
+/* { dg-final { scan-assembler-times "vaddudm" 2 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 2 } } */
+/* { dg-final { scan-assembler-times "vsld"    2 } } */
+/* { dg-final { scan-assembler-times "vsrad"   1 } } */
+/* { dg-final { scan-assembler-times "vsrd"    1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
new file mode 100644
index 000000000..394f41640
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c
@@ -0,0 +1,204 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */
+
+#include <altivec.h>
+
+typedef vector long long		v_sign;
+typedef vector unsigned long long	v_uns;
+typedef vector bool long long		v_bool;
+
+v_sign sign_add_1 (v_sign a, v_sign b)
+{
+  return __builtin_altivec_vaddudm (a, b);
+}
+
+v_sign sign_add_2 (v_sign a, v_sign b)
+{
+  return vec_add (a, b);
+}
+
+v_sign sign_add_3 (v_sign a, v_sign b)
+{
+  return vec_vaddudm (a, b);
+}
+
+v_sign sign_sub_1 (v_sign a, v_sign b)
+{
+  return __builtin_altivec_vsubudm (a, b);
+}
+
+v_sign sign_sub_2 (v_sign a, v_sign b)
+{
+  return vec_sub (a, b);
+}
+
+
+v_sign sign_sub_3 (v_sign a, v_sign b)
+{
+  return vec_vsubudm (a, b);
+}
+
+v_sign sign_min_1 (v_sign a, v_sign b)
+{
+  return __builtin_altivec_vminsd (a, b);
+}
+
+v_sign sign_min_2 (v_sign a, v_sign b)
+{
+  return vec_min (a, b);
+}
+
+v_sign sign_min_3 (v_sign a, v_sign b)
+{
+  return vec_vminsd (a, b);
+}
+
+v_sign sign_max_1 (v_sign a, v_sign b)
+{
+  return __builtin_altivec_vmaxsd (a, b);
+}
+
+v_sign sign_max_2 (v_sign a, v_sign b)
+{
+  return vec_max (a, b);
+}
+
+v_sign sign_max_3 (v_sign a, v_sign b)
+{
+  return vec_vmaxsd (a, b);
+}
+
+v_sign sign_abs (v_sign a)
+{
+  return vec_abs (a);		/* xor, vsubudm, vmaxsd.  */
+}
+
+v_bool sign_eq (v_sign a, v_sign b)
+{
+  return vec_cmpeq (a, b);
+}
+
+v_bool sign_lt (v_sign a, v_sign b)
+{
+  return vec_cmplt (a, b);
+}
+
+v_uns uns_add_2 (v_uns a, v_uns b)
+{
+  return vec_add (a, b);
+}
+
+v_uns uns_add_3 (v_uns a, v_uns b)
+{
+  return vec_vaddudm (a, b);
+}
+
+v_uns uns_sub_2 (v_uns a, v_uns b)
+{
+  return vec_sub (a, b);
+}
+
+v_uns uns_sub_3 (v_uns a, v_uns b)
+{
+  return vec_vsubudm (a, b);
+}
+
+v_uns uns_min_2 (v_uns a, v_uns b)
+{
+  return vec_min (a, b);
+}
+
+v_uns uns_min_3 (v_uns a, v_uns b)
+{
+  return vec_vminud (a, b);
+}
+
+v_uns uns_max_2 (v_uns a, v_uns b)
+{
+  return vec_max (a, b);
+}
+
+v_uns uns_max_3 (v_uns a, v_uns b)
+{
+  return vec_vmaxud (a, b);
+}
+
+v_bool uns_eq (v_uns a, v_uns b)
+{
+  return vec_cmpeq (a, b);
+}
+
+v_bool uns_lt (v_uns a, v_uns b)
+{
+  return vec_cmplt (a, b);
+}
+
+v_sign sign_rl_1 (v_sign a, v_sign b)
+{
+  return __builtin_altivec_vrld (a, b);
+}
+
+v_sign sign_rl_2 (v_sign a, v_uns b)
+{
+  return vec_rl (a, b);
+}
+
+v_uns uns_rl_2 (v_uns a, v_uns b)
+{
+  return vec_rl (a, b);
+}
+
+v_sign sign_sl_1 (v_sign a, v_sign b)
+{
+  return __builtin_altivec_vsld (a, b);
+}
+
+v_sign sign_sl_2 (v_sign a, v_uns b)
+{
+  return vec_sl (a, b);
+}
+
+v_sign sign_sl_3 (v_sign a, v_uns b)
+{
+  return vec_vsld (a, b);
+}
+
+v_uns uns_sl_2 (v_uns a, v_uns b)
+{
+  return vec_sl (a, b);
+}
+
+v_uns uns_sl_3 (v_uns a, v_uns b)
+{
+  return vec_vsld (a, b);
+}
+
+v_sign sign_sra_1 (v_sign a, v_sign b)
+{
+  return __builtin_altivec_vsrad (a, b);
+}
+
+v_sign sign_sra_2 (v_sign a, v_uns b)
+{
+  return vec_sra (a, b);
+}
+
+v_sign sign_sra_3 (v_sign a, v_uns b)
+{
+  return vec_vsrad (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vaddudm" 	5 } } */
+/* { dg-final { scan-assembler-times "vsubudm" 	6 } } */
+/* { dg-final { scan-assembler-times "vmaxsd"  	4 } } */
+/* { dg-final { scan-assembler-times "vminsd"  	3 } } */
+/* { dg-final { scan-assembler-times "vmaxud"  	2 } } */
+/* { dg-final { scan-assembler-times "vminud"  	2 } } */
+/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */
+/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */
+/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */
+/* { dg-final { scan-assembler-times "vrld"     3 } } */
+/* { dg-final { scan-assembler-times "vsld"     5 } } */
+/* { dg-final { scan-assembler-times "vsrad"    3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
new file mode 100644
index 000000000..cb8a5b8af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c
@@ -0,0 +1,104 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */
+
+#include <altivec.h>
+
+typedef vector long long		vll_sign;
+typedef vector unsigned long long	vll_uns;
+typedef vector bool long long		vll_bool;
+
+typedef vector int			vi_sign;
+typedef vector unsigned int		vi_uns;
+typedef vector bool int			vi_bool;
+
+typedef vector short			vs_sign;
+typedef vector unsigned short		vs_uns;
+typedef vector bool short		vs_bool;
+
+typedef vector signed char		vc_sign;
+typedef vector unsigned char		vc_uns;
+typedef vector bool char		vc_bool;
+
+
+vi_sign vi_pack_1 (vll_sign a, vll_sign b)
+{
+  return __builtin_altivec_vpkudum (a, b);
+}
+
+vi_sign vi_pack_2 (vll_sign a, vll_sign b)
+{
+  return vec_pack (a, b);
+}
+
+vi_sign vi_pack_3 (vll_sign a, vll_sign b)
+{
+  return vec_vpkudum (a, b);
+}
+
+vs_sign vs_pack_1 (vi_sign a, vi_sign b)
+{
+  return __builtin_altivec_vpkuwum (a, b);
+}
+
+vs_sign vs_pack_2 (vi_sign a, vi_sign b)
+{
+  return vec_pack (a, b);
+}
+
+vs_sign vs_pack_3 (vi_sign a, vi_sign b)
+{
+  return vec_vpkuwum (a, b);
+}
+
+vc_sign vc_pack_1 (vs_sign a, vs_sign b)
+{
+  return __builtin_altivec_vpkuhum (a, b);
+}
+
+vc_sign vc_pack_2 (vs_sign a, vs_sign b)
+{
+  return vec_pack (a, b);
+}
+
+vc_sign vc_pack_3 (vs_sign a, vs_sign b)
+{
+  return vec_vpkuhum (a, b);
+}
+
+vll_sign vll_unpack_hi_1 (vi_sign a)
+{
+  return __builtin_altivec_vupkhsw (a);
+}
+
+vll_sign vll_unpack_hi_2 (vi_sign a)
+{
+  return vec_unpackh (a);
+}
+
+vll_sign vll_unpack_hi_3 (vi_sign a)
+{
+  return __builtin_vec_vupkhsw (a);
+}
+
+vll_sign vll_unpack_lo_1 (vi_sign a)
+{
+  return vec_vupklsw (a);
+}
+
+vll_sign vll_unpack_lo_2 (vi_sign a)
+{
+  return vec_unpackl (a);
+}
+
+vll_sign vll_unpack_lo_3 (vi_sign a)
+{
+  return vec_vupklsw (a);
+}
+
+/* { dg-final { scan-assembler-times "vpkudum" 3 } } */
+/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */
+/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */
+/* { dg-final { scan-assembler-times "vupklsw" 3 } } */
+/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
new file mode 100644
index 000000000..8aaa6eaca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c
@@ -0,0 +1,249 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model=dynamic" } */
+
+#include <altivec.h>
+
+typedef vector long long		vll_sign;
+typedef vector unsigned long long	vll_uns;
+typedef vector bool long long		vll_bool;
+
+typedef vector int			vi_sign;
+typedef vector unsigned int		vi_uns;
+typedef vector bool int			vi_bool;
+
+typedef vector short			vs_sign;
+typedef vector unsigned short		vs_uns;
+typedef vector bool short		vs_bool;
+
+typedef vector signed char		vc_sign;
+typedef vector unsigned char		vc_uns;
+typedef vector bool char		vc_bool;
+
+vll_sign vll_clz_1 (vll_sign a)
+{
+  return __builtin_altivec_vclzd (a);
+}
+
+vll_sign vll_clz_2 (vll_sign a)
+{
+  return vec_vclz (a);
+}
+
+vll_sign vll_clz_3 (vll_sign a)
+{
+  return vec_vclzd (a);
+}
+
+vll_uns vll_clz_4 (vll_uns a)
+{
+  return vec_vclz (a);
+}
+
+vll_uns vll_clz_5 (vll_uns a)
+{
+  return vec_vclzd (a);
+}
+
+vi_sign vi_clz_1 (vi_sign a)
+{
+  return __builtin_altivec_vclzw (a);
+}
+
+vi_sign vi_clz_2 (vi_sign a)
+{
+  return vec_vclz (a);
+}
+
+vi_sign vi_clz_3 (vi_sign a)
+{
+  return vec_vclzw (a);
+}
+
+vi_uns vi_clz_4 (vi_uns a)
+{
+  return vec_vclz (a);
+}
+
+vi_uns vi_clz_5 (vi_uns a)
+{
+  return vec_vclzw (a);
+}
+
+vs_sign vs_clz_1 (vs_sign a)
+{
+  return __builtin_altivec_vclzh (a);
+}
+
+vs_sign vs_clz_2 (vs_sign a)
+{
+  return vec_vclz (a);
+}
+
+vs_sign vs_clz_3 (vs_sign a)
+{
+  return vec_vclzh (a);
+}
+
+vs_uns vs_clz_4 (vs_uns a)
+{
+  return vec_vclz (a);
+}
+
+vs_uns vs_clz_5 (vs_uns a)
+{
+  return vec_vclzh (a);
+}
+
+vc_sign vc_clz_1 (vc_sign a)
+{
+  return __builtin_altivec_vclzb (a);
+}
+
+vc_sign vc_clz_2 (vc_sign a)
+{
+  return vec_vclz (a);
+}
+
+vc_sign vc_clz_3 (vc_sign a)
+{
+  return vec_vclzb (a);
+}
+
+vc_uns vc_clz_4 (vc_uns a)
+{
+  return vec_vclz (a);
+}
+
+vc_uns vc_clz_5 (vc_uns a)
+{
+  return vec_vclzb (a);
+}
+
+vll_sign vll_popcnt_1 (vll_sign a)
+{
+  return __builtin_altivec_vpopcntd (a);
+}
+
+vll_sign vll_popcnt_2 (vll_sign a)
+{
+  return vec_vpopcnt (a);
+}
+
+vll_sign vll_popcnt_3 (vll_sign a)
+{
+  return vec_vpopcntd (a);
+}
+
+vll_uns vll_popcnt_4 (vll_uns a)
+{
+  return vec_vpopcnt (a);
+}
+
+vll_uns vll_popcnt_5 (vll_uns a)
+{
+  return vec_vpopcntd (a);
+}
+
+vi_sign vi_popcnt_1 (vi_sign a)
+{
+  return __builtin_altivec_vpopcntw (a);
+}
+
+vi_sign vi_popcnt_2 (vi_sign a)
+{
+  return vec_vpopcnt (a);
+}
+
+vi_sign vi_popcnt_3 (vi_sign a)
+{
+  return vec_vpopcntw (a);
+}
+
+vi_uns vi_popcnt_4 (vi_uns a)
+{
+  return vec_vpopcnt (a);
+}
+
+vi_uns vi_popcnt_5 (vi_uns a)
+{
+  return vec_vpopcntw (a);
+}
+
+vs_sign vs_popcnt_1 (vs_sign a)
+{
+  return __builtin_altivec_vpopcnth (a);
+}
+
+vs_sign vs_popcnt_2 (vs_sign a)
+{
+  return vec_vpopcnt (a);
+}
+
+vs_sign vs_popcnt_3 (vs_sign a)
+{
+  return vec_vpopcnth (a);
+}
+
+vs_uns vs_popcnt_4 (vs_uns a)
+{
+  return vec_vpopcnt (a);
+}
+
+vs_uns vs_popcnt_5 (vs_uns a)
+{
+  return vec_vpopcnth (a);
+}
+
+vc_sign vc_popcnt_1 (vc_sign a)
+{
+  return __builtin_altivec_vpopcntb (a);
+}
+
+vc_sign vc_popcnt_2 (vc_sign a)
+{
+  return vec_vpopcnt (a);
+}
+
+vc_sign vc_popcnt_3 (vc_sign a)
+{
+  return vec_vpopcntb (a);
+}
+
+vc_uns vc_popcnt_4 (vc_uns a)
+{
+  return vec_vpopcnt (a);
+}
+
+vc_uns vc_popcnt_5 (vc_uns a)
+{
+  return vec_vpopcntb (a);
+}
+
+vc_uns vc_gbb_1 (vc_uns a)
+{
+  return __builtin_altivec_vgbbd (a);
+}
+
+vc_sign vc_gbb_2 (vc_sign a)
+{
+  return vec_vgbbd (a);
+}
+
+vc_uns vc_gbb_3 (vc_uns a)
+{
+  return vec_vgbbd (a);
+}
+
+/* { dg-final { scan-assembler-times "vclzd" 	5 } } */
+/* { dg-final { scan-assembler-times "vclzw" 	5 } } */
+/* { dg-final { scan-assembler-times "vclzh" 	5 } } */
+/* { dg-final { scan-assembler-times "vclzb" 	5 } } */
+
+/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */
+/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */
+/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */
+/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */
+
+/* { dg-final { scan-assembler-times "vgbbd"    3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c
new file mode 100644
index 000000000..36de9eb9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c
@@ -0,0 +1,105 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */
+
+#include <altivec.h>
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifndef ALIGN
+#define ALIGN 32
+#endif
+
+#ifndef ATTR_ALIGN
+#define ATTR_ALIGN __attribute__((__aligned__(ALIGN)))
+#endif
+
+#define DOIT(TYPE, PREFIX)						\
+TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b)				\
+{									\
+  return vec_eqv (a, b);						\
+}									\
+									\
+TYPE PREFIX ## _eqv_arith (TYPE a, TYPE b)				\
+{									\
+  return ~(a ^ b);							\
+}									\
+									\
+TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b)				\
+{									\
+  return vec_nand (a, b);						\
+}									\
+									\
+TYPE PREFIX ## _nand_arith1 (TYPE a, TYPE b)				\
+{									\
+  return ~(a & b);							\
+}									\
+									\
+TYPE PREFIX ## _nand_arith2 (TYPE a, TYPE b)				\
+{									\
+  return (~a) | (~b);							\
+}									\
+									\
+TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b)				\
+{									\
+  return vec_orc (a, b);						\
+}									\
+									\
+TYPE PREFIX ## _orc_arith1 (TYPE a, TYPE b)				\
+{									\
+  return (~ a) | b;							\
+}									\
+									\
+TYPE PREFIX ## _orc_arith2 (TYPE a, TYPE b)				\
+{									\
+  return a | (~ b);							\
+}
+
+#define DOIT_FLOAT(TYPE, PREFIX)					\
+TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b)				\
+{									\
+  return vec_eqv (a, b);						\
+}									\
+									\
+TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b)				\
+{									\
+  return vec_nand (a, b);						\
+}									\
+									\
+TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b)				\
+{									\
+  return vec_orc (a, b);						\
+}
+
+typedef vector signed char		sign_char_vec;
+typedef vector short			sign_short_vec;
+typedef vector int			sign_int_vec;
+typedef vector long long		sign_llong_vec;
+
+typedef vector unsigned char		uns_char_vec;
+typedef vector unsigned short		uns_short_vec;
+typedef vector unsigned int		uns_int_vec;
+typedef vector unsigned long long	uns_llong_vec;
+
+typedef vector float			float_vec;
+typedef vector double			double_vec;
+
+DOIT(sign_char_vec,	sign_char)
+DOIT(sign_short_vec,	sign_short)
+DOIT(sign_int_vec,	sign_int)
+DOIT(sign_llong_vec,	sign_llong)
+
+DOIT(uns_char_vec,	uns_char)
+DOIT(uns_short_vec,	uns_short)
+DOIT(uns_int_vec,	uns_int)
+DOIT(uns_llong_vec,	uns_llong)
+
+DOIT_FLOAT(float_vec,	float)
+DOIT_FLOAT(double_vec,	double)
+
+/* { dg-final { scan-assembler-times "xxleqv"  18 } } */
+/* { dg-final { scan-assembler-times "xxlnand" 26 } } */
+/* { dg-final { scan-assembler-times "xxlorc"  26 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c
new file mode 100644
index 000000000..8b81781c6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+vector float dbl_to_float_p8 (double x) { return __builtin_vsx_xscvdpspn (x); }
+double float_to_dbl_p8 (vector float x) { return __builtin_vsx_xscvspdpn (x); }
+
+/* { dg-final { scan-assembler "xscvdpspn" } } */
+/* { dg-final { scan-assembler "xscvspdpn" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
new file mode 100644
index 000000000..45a300fb9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+#include <altivec.h>
+
+typedef vector int		v_sign;
+typedef vector unsigned int	v_uns;
+
+v_sign even_sign (v_sign a, v_sign b)
+{
+  return vec_vmrgew (a, b);
+}
+
+v_uns even_uns (v_uns a, v_uns b)
+{
+  return vec_vmrgew (a, b);
+}
+
+v_sign odd_sign (v_sign a, v_sign b)
+{
+  return vec_vmrgow (a, b);
+}
+
+v_uns odd_uns (v_uns a, v_uns b)
+{
+  return vec_vmrgow (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vmrgew" 2 } } */
+/* { dg-final { scan-assembler-times "vmrgow" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c
new file mode 100644
index 000000000..3cfd8161d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c
@@ -0,0 +1,139 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */
+
+float abs_sf (float *p)
+{
+  float f = *p;
+  __asm__ ("# reg %x0" : "+v" (f));
+  return __builtin_fabsf (f);
+}
+
+float nabs_sf (float *p)
+{
+  float f = *p;
+  __asm__ ("# reg %x0" : "+v" (f));
+  return - __builtin_fabsf (f);
+}
+
+float neg_sf (float *p)
+{
+  float f = *p;
+  __asm__ ("# reg %x0" : "+v" (f));
+  return - f;
+}
+
+float add_sf (float *p, float *q)
+{
+  float f1 = *p;
+  float f2 = *q;
+  __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));
+  return f1 + f2;
+}
+
+float sub_sf (float *p, float *q)
+{
+  float f1 = *p;
+  float f2 = *q;
+  __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));
+  return f1 - f2;
+}
+
+float mul_sf (float *p, float *q)
+{
+  float f1 = *p;
+  float f2 = *q;
+  __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));
+  return f1 * f2;
+}
+
+float div_sf (float *p, float *q)
+{
+  float f1 = *p;
+  float f2 = *q;
+  __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2));
+  return f1 / f2;
+}
+
+float sqrt_sf (float *p)
+{
+  float f = *p;
+  __asm__ ("# reg %x0" : "+v" (f));
+  return __builtin_sqrtf (f);
+}
+
+
+double abs_df (double *p)
+{
+  double d = *p;
+  __asm__ ("# reg %x0" : "+v" (d));
+  return __builtin_fabs (d);
+}
+
+double nabs_df (double *p)
+{
+  double d = *p;
+  __asm__ ("# reg %x0" : "+v" (d));
+  return - __builtin_fabs (d);
+}
+
+double neg_df (double *p)
+{
+  double d = *p;
+  __asm__ ("# reg %x0" : "+v" (d));
+  return - d;
+}
+
+double add_df (double *p, double *q)
+{
+  double d1 = *p;
+  double d2 = *q;
+  __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));
+  return d1 + d2;
+}
+
+double sub_df (double *p, double *q)
+{
+  double d1 = *p;
+  double d2 = *q;
+  __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));
+  return d1 - d2;
+}
+
+double mul_df (double *p, double *q)
+{
+  double d1 = *p;
+  double d2 = *q;
+  __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));
+  return d1 * d2;
+}
+
+double div_df (double *p, double *q)
+{
+  double d1 = *p;
+  double d2 = *q;
+  __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2));
+  return d1 / d2;
+}
+
+double sqrt_df (float *p)
+{
+  double d = *p;
+  __asm__ ("# reg %x0" : "+v" (d));
+  return __builtin_sqrt (d);
+}
+
+/* { dg-final { scan-assembler "xsabsdp"  } } */
+/* { dg-final { scan-assembler "xsadddp"  } } */
+/* { dg-final { scan-assembler "xsaddsp"  } } */
+/* { dg-final { scan-assembler "xsdivdp"  } } */
+/* { dg-final { scan-assembler "xsdivsp"  } } */
+/* { dg-final { scan-assembler "xsmuldp"  } } */
+/* { dg-final { scan-assembler "xsmulsp"  } } */
+/* { dg-final { scan-assembler "xsnabsdp" } } */
+/* { dg-final { scan-assembler "xsnegdp"  } } */
+/* { dg-final { scan-assembler "xssqrtdp" } } */
+/* { dg-final { scan-assembler "xssqrtsp" } } */
+/* { dg-final { scan-assembler "xssubdp"  } } */
+/* { dg-final { scan-assembler "xssubsp"  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
new file mode 100644
index 000000000..86bde3241
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
@@ -0,0 +1,85 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE vector __int128_t
+#endif
+
+TYPE
+do_addcuq (TYPE p, TYPE q)
+{
+  return __builtin_vec_vaddcuq (p, q);
+}
+
+TYPE
+do_adduqm (TYPE p, TYPE q)
+{
+  return __builtin_vec_add (p, q);
+}
+
+TYPE
+do_addeuqm (TYPE p, TYPE q, TYPE r)
+{
+  return __builtin_vec_vaddeuqm (p, q, r);
+}
+
+TYPE
+do_addecuq (TYPE p, TYPE q, TYPE r)
+{
+  return __builtin_vec_vaddecuq (p, q, r);
+}
+
+TYPE
+do_subeuqm (TYPE p, TYPE q, TYPE r)
+{
+  return __builtin_vec_vsubeuqm (p, q, r);
+}
+
+TYPE
+do_subecuq (TYPE p, TYPE q, TYPE r)
+{
+  return __builtin_vec_vsubecuq (p, q, r);
+}
+
+TYPE
+do_subcuq (TYPE p, TYPE q)
+{
+  return __builtin_vec_vsubcuq (p, q);
+}
+
+TYPE
+do_subuqm (TYPE p, TYPE q)
+{
+  return __builtin_vec_vsubuqm (p, q);
+}
+
+TYPE
+do_zero (void)
+{
+  return (TYPE) { 0 };
+}
+
+TYPE
+do_minus_one (void)
+{
+  return (TYPE) { -1 };
+}
+
+/* { dg-final { scan-assembler	   "vaddcuq"   } } */
+/* { dg-final { scan-assembler	   "vadduqm"   } } */
+/* { dg-final { scan-assembler	   "vaddecuq"  } } */
+/* { dg-final { scan-assembler	   "vaddeuqm"  } } */
+/* { dg-final { scan-assembler	   "vsubecuq"  } } */
+/* { dg-final { scan-assembler	   "vsubeuqm"  } } */
+/* { dg-final { scan-assembler	   "vsubcuq"   } } */
+/* { dg-final { scan-assembler	   "vsubuqm"   } } */
+/* { dg-final { scan-assembler-not "mtvsrd"    } } */
+/* { dg-final { scan-assembler-not "mfvsrd"    } } */
+/* { dg-final { scan-assembler-not "ori 2,2,0" } } */
+/* { dg-final { scan-assembler-not "xxpermdi"  } } */
+/* { dg-final { scan-assembler-not "stxvd2x"   } } */
+/* { dg-final { scan-assembler-not "stxvw4x"   } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
new file mode 100644
index 000000000..1064894dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c
@@ -0,0 +1,177 @@
+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <altivec.h>
+
+#ifdef DEBUG
+#include <stdio.h>
+#define UNUSED
+
+#ifdef __LITTLE_ENDIAN__
+#define HI_WORD 1
+#define LO_WORD 0
+#else
+#define HI_WORD 0
+#define LO_WORD 1
+#endif
+
+#else
+#define UNUSED __attribute__((__unused__))
+#endif
+
+#ifndef S_TYPE
+#define S_TYPE __uint128_t
+#endif
+
+#ifndef V_TYPE
+#define V_TYPE vector S_TYPE
+#endif
+
+static int compare (S_TYPE, V_TYPE, const char *, const char *)
+  __attribute__((__noinline__));
+
+static int
+compare (S_TYPE scalar,
+	 V_TYPE vect,
+	 const char *nl    UNUSED,
+	 const char *which UNUSED)
+{
+  unsigned long scalar_lo = (unsigned long) scalar;
+  unsigned long scalar_hi = (unsigned long) (scalar >> 64);
+  unsigned long vect_lo;
+  unsigned long vect_hi;
+  vector long long tmp;
+  int ret;
+
+  __asm__ ("mfvsrd %0,%x3\n\t"
+	   "xxpermdi %x2,%x3,%x3,3\n\t"
+	   "mfvsrd %1,%x2"
+	   : "=r" (vect_hi),
+	     "=r" (vect_lo),
+	     "=wa" (tmp)
+	   : "wa" (vect));
+
+  ret = (scalar_lo != vect_lo) || (scalar_hi != vect_hi);
+
+#ifdef DEBUG
+  printf ("%s%s: 0x%.16lx %.16lx %s 0x%.16lx %.16lx\n",
+	  nl, which,
+	  scalar_hi, scalar_lo,
+	  (ret) ? "!=" : "==",
+	  vect_hi, vect_lo);
+
+  fflush (stdout);
+#endif
+
+  return ret;
+}
+
+static void convert_via_mem (V_TYPE *, S_TYPE *)
+  __attribute__((__noinline__));
+
+static void
+convert_via_mem (V_TYPE *v, S_TYPE *s)
+{
+  *v = (V_TYPE) { *s };
+  __asm__ volatile ("nop"
+		    : "+m" (*s), "+m" (*v)
+		    :
+		    : "memory");
+
+}
+
+
+/* Check if vadduqm returns the same values as normal 128-bit add.  */
+
+/* Values to add together.  */
+const static struct {
+  unsigned long hi_1;
+  unsigned long lo_1;
+  unsigned long hi_2;
+  unsigned long lo_2;
+} values[] = {
+  { 0x0000000000000000UL, 0xfffffffffffffffeUL,
+    0x0000000000000000UL, 0x0000000000000002UL },
+  { 0x0000000000000000UL, 0x0000000000000002UL,
+    0x0000000000000000UL, 0xfffffffffffffffeUL },
+  { 0xffffffffffffffffUL, 0xfffffffffffffffeUL,
+    0x0000000000000000UL, 0x0000000000000002UL },
+  { 0xfffffffffffffff2UL, 0xffffffffffffffffUL,
+    0x0000000000000002UL, 0x0000000000000000UL },
+  { 0x7fffffffffffffffUL, 0xfffffffffffffffeUL,
+    0x0000000000000000UL, 0x0000000000000002UL },
+  { 0x7ffffffffffffff2UL, 0xffffffffffffffffUL,
+    0x0000000000000002UL, 0x0000000000000000UL },
+};
+
+int
+main (void)
+{
+  int reg_errors = 0;
+  int mem_errors = 0;
+  size_t i;
+  const char *nl = "";
+
+  for (i = 0; i < sizeof (values) / sizeof (values[0]); i++)
+    {
+      S_TYPE s_reg_res, s_reg_in1, s_reg_in2, s_mem_res, s_mem_in1, s_mem_in2;
+      V_TYPE v_reg_res, v_reg_in1, v_reg_in2, v_mem_res, v_mem_in1, v_mem_in2;
+
+      s_reg_in1 = ((((S_TYPE)values[i].hi_1 << 64)) + ((S_TYPE)values[i].lo_1));
+      reg_errors += compare (s_reg_in1, (V_TYPE) { s_reg_in1 }, nl, "reg, in1");
+
+      s_reg_in2 = ((((S_TYPE)values[i].hi_2 << 64)) + ((S_TYPE)values[i].lo_2));
+      reg_errors += compare (s_reg_in2, (V_TYPE) { s_reg_in2 }, "", "reg, in2");
+
+      s_reg_res = s_reg_in1 + s_reg_in2;
+
+      v_reg_in1 = (V_TYPE) { s_reg_in1 };
+      v_reg_in2 = (V_TYPE) { s_reg_in2 };
+      v_reg_res = vec_vadduqm (v_reg_in1, v_reg_in2);
+      reg_errors += compare (s_reg_res, v_reg_res, "", "reg, res");
+
+      s_mem_in1 = s_reg_in1;
+      convert_via_mem (&v_mem_in1, &s_mem_in1);
+      mem_errors += compare (s_mem_in1, (V_TYPE) { s_mem_in1 }, "\n", "mem, in1");
+
+      s_mem_in2 = s_reg_in2;
+      convert_via_mem (&v_mem_in2, &s_mem_in2);
+      mem_errors += compare (s_mem_in2, (V_TYPE) { s_mem_in2 }, "", "mem, in2");
+
+      s_mem_res = s_mem_in1 + s_mem_in2;
+      v_mem_res = vec_vadduqm (v_mem_in1, v_mem_in2);
+      mem_errors += compare (s_mem_res, v_mem_res, "", "mem, res");
+
+      nl = "\n";
+    }
+
+#ifdef DEBUG
+  putchar ('\n');
+
+  if (!reg_errors)
+    fputs ("no errors found on register operations\n", stdout);
+  else
+    printf ("%d error%s found on register operations\n",
+	    reg_errors,
+	    (reg_errors == 1) ? "s" : "");
+
+  if (!mem_errors)
+    fputs ("no errors found on memory operations\n", stdout);
+  else
+    printf ("%d error%s found on memory operations\n",
+	    mem_errors,
+	    (mem_errors == 1) ? "s" : "");
+
+  fflush (stdout);
+#endif
+
+  if ((reg_errors + mem_errors) != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
new file mode 100644
index 000000000..33f19991f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c
@@ -0,0 +1,42 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */
+
+float load_sf (float *p)
+{
+  float f = *p;
+  __asm__ ("# reg %x0" : "+v" (f));
+  return f;
+}
+
+double load_df (double *p)
+{
+  double d = *p;
+  __asm__ ("# reg %x0" : "+v" (d));
+  return d;
+}
+
+double load_dfsf (float *p)
+{
+  double d = (double) *p;
+  __asm__ ("# reg %x0" : "+v" (d));
+  return d;
+}
+
+void store_sf (float *p, float f)
+{
+  __asm__ ("# reg %x0" : "+v" (f));
+  *p = f;
+}
+
+void store_df (double *p, double d)
+{
+  __asm__ ("# reg %x0" : "+v" (d));
+  *p = d;
+}
+
+/* { dg-final { scan-assembler "lxsspx"  } } */
+/* { dg-final { scan-assembler "lxsdx"   } } */
+/* { dg-final { scan-assembler "stxsspx" } } */
+/* { dg-final { scan-assembler "stxsdx"  } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c
new file mode 100644
index 000000000..99b7ddfb2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c
@@ -0,0 +1,200 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifndef ALIGN
+#define ALIGN 32
+#endif
+
+#ifndef TYPE
+#define TYPE long long
+#endif
+
+#ifndef SIGN_TYPE
+#define SIGN_TYPE signed TYPE
+#endif
+
+#ifndef UNS_TYPE
+#define UNS_TYPE unsigned TYPE
+#endif
+
+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
+
+SIGN_TYPE	sa[SIZE] ALIGN_ATTR;
+SIGN_TYPE	sb[SIZE] ALIGN_ATTR;
+SIGN_TYPE	sc[SIZE] ALIGN_ATTR;
+
+UNS_TYPE	ua[SIZE] ALIGN_ATTR;
+UNS_TYPE	ub[SIZE] ALIGN_ATTR;
+UNS_TYPE	uc[SIZE] ALIGN_ATTR;
+
+void
+sign_add (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = sb[i] + sc[i];
+}
+
+void
+sign_sub (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = sb[i] - sc[i];
+}
+
+void
+sign_shift_left (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = sb[i] << sc[i];
+}
+
+void
+sign_shift_right (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = sb[i] >> sc[i];
+}
+
+void
+sign_max (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] > sc[i]) ? sb[i] : sc[i];
+}
+
+void
+sign_min (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] < sc[i]) ? sb[i] : sc[i];
+}
+
+void
+sign_abs (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] < 0) ? -sb[i] : sb[i];	/* xor, vsubudm, vmaxsd.  */
+}
+
+void
+sign_eq (SIGN_TYPE val1, SIGN_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] == sc[i]) ? val1 : val2;
+}
+
+void
+sign_lt (SIGN_TYPE val1, SIGN_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    sa[i] = (sb[i] < sc[i]) ? val1 : val2;
+}
+
+void
+uns_add (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = ub[i] + uc[i];
+}
+
+void
+uns_sub (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = ub[i] - uc[i];
+}
+
+void
+uns_shift_left (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = ub[i] << uc[i];
+}
+
+void
+uns_shift_right (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = ub[i] >> uc[i];
+}
+
+void
+uns_max (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = (ub[i] > uc[i]) ? ub[i] : uc[i];
+}
+
+void
+uns_min (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = (ub[i] < uc[i]) ? ub[i] : uc[i];
+}
+
+void
+uns_eq (UNS_TYPE val1, UNS_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = (ub[i] == uc[i]) ? val1 : val2;
+}
+
+void
+uns_lt (UNS_TYPE val1, UNS_TYPE val2)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    ua[i] = (ub[i] < uc[i]) ? val1 : val2;
+}
+
+/* { dg-final { scan-assembler-times "\[\t \]vaddudm\[\t \]"  2 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vsubudm\[\t \]"  3 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vmaxsd\[\t \]"   2 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vmaxud\[\t \]"   1 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vminsd\[\t \]"   1 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vminud\[\t \]"   1 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vsld\[\t \]"     2 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vsrad\[\t \]"    1 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vsrd\[\t \]"     1 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vcmpequd\[\t \]" 2 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vcmpgtsd\[\t \]" 1 } } */
+/* { dg-final { scan-assembler-times "\[\t \]vcmpgtud\[\t \]" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c
new file mode 100644
index 000000000..a29240754
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic" } */
+
+#include <stddef.h>
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifndef ALIGN
+#define ALIGN 32
+#endif
+
+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
+
+long long sign_ll[SIZE]	ALIGN_ATTR;
+int	  sign_i [SIZE]	ALIGN_ATTR;
+
+void copy_int_to_long_long (void)
+{
+  size_t i;
+
+  for (i = 0; i < SIZE; i++)
+    sign_ll[i] = sign_i[i];
+}
+
+/* { dg-final { scan-assembler "vupkhsw" } } */
+/* { dg-final { scan-assembler "vupklsw" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c
new file mode 100644
index 000000000..b86f7de81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic" } */
+
+#include <stddef.h>
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifndef ALIGN
+#define ALIGN 32
+#endif
+
+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
+
+long long sign_ll[SIZE]	ALIGN_ATTR;
+int	  sign_i [SIZE]	ALIGN_ATTR;
+
+void copy_long_long_to_int (void)
+{
+  size_t i;
+
+  for (i = 0; i < SIZE; i++)
+    sign_i[i] = sign_ll[i];
+}
+
+/* { dg-final { scan-assembler "vpkudum" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c
new file mode 100644
index 000000000..1e886387e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c
@@ -0,0 +1,69 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifndef ALIGN
+#define ALIGN 32
+#endif
+
+#define ALIGN_ATTR __attribute__((__aligned__(ALIGN)))
+
+#define DO_BUILTIN(PREFIX, TYPE, CLZ, POPCNT)				\
+TYPE PREFIX ## _a[SIZE] ALIGN_ATTR;					\
+TYPE PREFIX ## _b[SIZE] ALIGN_ATTR;					\
+									\
+void									\
+PREFIX ## _clz (void)							\
+{									\
+  unsigned long i;							\
+									\
+  for (i = 0; i < SIZE; i++)						\
+    PREFIX ## _a[i] = CLZ (PREFIX ## _b[i]);				\
+}									\
+									\
+void									\
+PREFIX ## _popcnt (void)						\
+{									\
+  unsigned long i;							\
+									\
+  for (i = 0; i < SIZE; i++)						\
+    PREFIX ## _a[i] = POPCNT (PREFIX ## _b[i]);				\
+}
+
+#if !defined(DO_LONG_LONG) && !defined(DO_LONG) && !defined(DO_INT) && !defined(DO_SHORT) && !defined(DO_CHAR)
+#define DO_INT 1
+#endif
+
+#if DO_LONG_LONG
+/* At the moment, only int is auto vectorized.  */
+DO_BUILTIN (sll, long long,		__builtin_clzll, __builtin_popcountll)
+DO_BUILTIN (ull, unsigned long long,	__builtin_clzll, __builtin_popcountll)
+#endif
+
+#if defined(_ARCH_PPC64) && DO_LONG
+DO_BUILTIN (sl,  long,			__builtin_clzl,  __builtin_popcountl)
+DO_BUILTIN (ul,  unsigned long,		__builtin_clzl,  __builtin_popcountl)
+#endif
+
+#if DO_INT
+DO_BUILTIN (si,  int,			__builtin_clz,   __builtin_popcount)
+DO_BUILTIN (ui,  unsigned int,		__builtin_clz,   __builtin_popcount)
+#endif
+
+#if DO_SHORT
+DO_BUILTIN (ss,  short,			__builtin_clz,   __builtin_popcount)
+DO_BUILTIN (us,  unsigned short,	__builtin_clz,   __builtin_popcount)
+#endif
+
+#if DO_CHAR
+DO_BUILTIN (sc,  signed char,		__builtin_clz,   __builtin_popcount)
+DO_BUILTIN (uc,  unsigned char,		__builtin_clz,   __builtin_popcount)
+#endif
+
+/* { dg-final { scan-assembler-times "vclzw"     2 } } */
+/* { dg-final { scan-assembler-times "vpopcntw"  2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c
new file mode 100644
index 000000000..0102510da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c
@@ -0,0 +1,87 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model=dynamic -fno-unroll-loops -fno-unroll-all-loops" } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifndef ALIGN
+#define ALIGN 32
+#endif
+
+#ifndef ATTR_ALIGN
+#define ATTR_ALIGN __attribute__((__aligned__(ALIGN)))
+#endif
+
+#ifndef TYPE
+#define TYPE unsigned int
+#endif
+
+TYPE in1  [SIZE] ATTR_ALIGN;
+TYPE in2  [SIZE] ATTR_ALIGN;
+TYPE eqv  [SIZE] ATTR_ALIGN;
+TYPE nand1[SIZE] ATTR_ALIGN;
+TYPE nand2[SIZE] ATTR_ALIGN;
+TYPE orc1 [SIZE] ATTR_ALIGN;
+TYPE orc2 [SIZE] ATTR_ALIGN;
+
+void
+do_eqv (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      eqv[i] = ~(in1[i] ^ in2[i]);
+    }
+}
+
+void
+do_nand1 (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      nand1[i] = ~(in1[i] & in2[i]);
+    }
+}
+
+void
+do_nand2 (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      nand2[i] = (~in1[i]) | (~in2[i]);
+    }
+}
+
+void
+do_orc1 (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      orc1[i] = (~in1[i]) | in2[i];
+    }
+}
+
+void
+do_orc2 (void)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    {
+      orc1[i] = in1[i] | (~in2[i]);
+    }
+}
+
+/* { dg-final { scan-assembler-times "xxleqv"  1 } } */
+/* { dg-final { scan-assembler-times "xxlnand" 2 } } */
+/* { dg-final { scan-assembler-times "xxlorc"  2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-1.c
new file mode 100644
index 000000000..19a66a15b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-1.c
@@ -0,0 +1,33 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32} } } */
+/* { dg-options "-mpaired -ffinite-math-only " } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+static float in1[2] __attribute__ ((aligned (8))) =
+{6.0, 7.0};
+static float in2[2] __attribute__ ((aligned (8))) =
+{4.0, 3.0};
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float a, b, c, d;
+void
+test_api ()
+{
+  b = paired_lx (0, in1);
+  c = paired_lx (0, in2);
+
+  a = paired_sub (b, c);
+
+  paired_stx (a, 0, out);
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-10.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-10.c
new file mode 100644
index 000000000..1f904c258
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-10.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only " } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+void
+test_api (float y, float x)
+{
+  vector float c = {x, y};
+  vector float b = {0.0, 8.0};
+  vector float a;
+
+  a = paired_sub (b, c);
+  paired_stx (a, 0, out);
+}
+
+
+int main ()
+{
+  test_api (6, 7);
+  return (0); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-2.c
new file mode 100644
index 000000000..181bbf1c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 3.0, 8.0 };
+vector float c = { 3.0, 5.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu0_eq (b, c))
+    {
+      a = paired_sub (b, c);
+      paired_stx (a, 0, out);
+    }
+
+  if ((out[1]) != 3.0)
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-3.c
new file mode 100644
index 000000000..2e4bbf4af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-3.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 2.0, 8.0 };
+vector float c = { 3.0, 5.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu0_lt (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 13.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-4.c
new file mode 100644
index 000000000..2c7cb1b67
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-4.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 3.0, 8.0 };
+vector float c = { 2.0, 5.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu0_gt (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 13.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-5.c
new file mode 100644
index 000000000..3914c2a6f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-5.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 3.0, 5.0 };
+vector float c = { 2.0, 5.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu1_eq (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 10.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-6.c
new file mode 100644
index 000000000..25dd42835
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-6.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 3.0, 5.0 };
+vector float c = { 2.0, 6.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu1_lt (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 11.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-7.c
new file mode 100644
index 000000000..6e4b80917
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-7.c
@@ -0,0 +1,34 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+#include <stdlib.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+
+vector float b = { 2.0, 8.0 };
+vector float c = { 3.0, 6.0 };
+
+vector float a = { 0.0, 0.0 };
+void
+test_api ()
+{
+
+  if (paired_cmpu1_gt (b, c))
+    {
+      a = paired_add (b, c);
+      paired_stx (a, 0, out);
+    }
+  if ((out[0] != 5.0) || (out[1] != 14.0))
+    abort ();
+}
+
+int
+main ()
+{
+  test_api ();
+  return (0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-8.c
new file mode 100644
index 000000000..1dfaf5187
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-8.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only " } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+void
+test_api (float x)
+{
+  vector float c = {x, x};
+  vector float b = {60.0, 88.0};
+  vector float a;
+
+  a = paired_sub (b, c);
+  paired_stx (a, 0, out);
+}
+
+
+int main ()
+{
+  test_api (6);
+  return (0); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-9.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-9.c
new file mode 100644
index 000000000..c72132fec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/paired-9.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only " } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+static float out[2] __attribute__ ((aligned (8)));
+void
+test_api (float y, float x)
+{
+  vector float c = {x, 7.0};
+  vector float b = {0.0, 8.0};
+  vector float a;
+
+  a = paired_sub (b, c);
+  paired_stx (a, 0, out);
+}
+
+
+int main ()
+{
+  test_api (6, 7);
+  return (0); 
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/parity-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/parity-1.c
new file mode 100644
index 000000000..c991d4caa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/parity-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power5" } */
+/* { dg-final { scan-assembler "popcntb" } } */
+/* { dg-final { scan-assembler-not "mullw" } } */
+
+int foo(int x)
+{
+  return __builtin_parity(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-1.c
new file mode 100644
index 000000000..c94d155e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power5" } */
+/* { dg-final { scan-assembler "popcntb" } } */
+/* { dg-final { scan-assembler-not "mullw" } } */
+
+int foo(int x)
+{
+  return __builtin_popcount(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-2.c
new file mode 100644
index 000000000..43b2ce7fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "popcntw" } } */
+
+int foo(int x)
+{
+  return __builtin_popcount(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-3.c
new file mode 100644
index 000000000..341816f9f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/popcount-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "popcntd" } } */
+
+long foo(int x)
+{
+  return __builtin_popcountl(x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/powerpc.exp b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/powerpc.exp
new file mode 100644
index 000000000..bf270d58d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/powerpc.exp
@@ -0,0 +1,52 @@
+#   Copyright (C) 2005-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the 'dg.exp' driver.
+
+# Exit immediately if this isn't a PowerPC target.
+if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+load_lib torture-options.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize 'dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+set SAVRES_TEST_OPTS [list -Os -O2 {-Os -mno-multiple} {-O2 -mno-multiple}]
+set alti ""
+if [check_vmx_hw_available] {
+    set alti "-maltivec"
+}
+torture-init
+set-torture-options $SAVRES_TEST_OPTS
+gcc-dg-runtest [list $srcdir/$subdir/savres.c] $alti
+
+# All done.
+torture-finish
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c
new file mode 100644
index 000000000..3d4237ce9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-and-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,0,0,30"  } } */
+/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,0,29,30"  } } */
+/* { dg-final { scan-assembler-not "rldicr" } } */
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 16457 - use rlwinm insn.  */
+
+char *foo1 (char *p, unsigned int x)
+{
+  return p - (x & ~1);
+}
+
+char *foo2 (char *p, unsigned int x)
+{
+  return p - (x & 6);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c
new file mode 100644
index 000000000..34e5a28e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c
@@ -0,0 +1,67 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,1,31"  } } */
+/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,0xffffffff" } } */
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 17104 many sign extends added.  */
+
+struct {
+ int f1 : 1;
+ int f2 : 1;
+ int f3 : 1;
+ int f4 : 1;
+ int f5 : 1;
+ int f6 : 1;
+ int f7 : 1;
+ int f8 : 1;
+ int f9 : 1;
+ int f10 : 1;
+ int f11 : 1;
+ int f12 : 1;
+ int f13 : 1;
+ int f14 : 1;
+ int f15 : 1;
+ int f16 : 1;
+ int f17 : 2;
+ int f18 : 2;
+ int f19 : 2;
+ int f20 : 2;
+ int f21 : 2;
+ int f22 : 2;
+ int f23 : 2;
+ int f24 : 2;
+ } s;
+
+void foo ()
+{
+
+    s.f1 = 0;
+    s.f2 = 0;
+    s.f3 = 0;
+    s.f4 = 0;
+    s.f5 = 0;
+    s.f6 = 0;
+    s.f7 = 0;
+    s.f8 = 0;
+    s.f9 = 0;
+    s.f10 = 0;
+    s.f11 = 0;
+    s.f12 = 0;
+    s.f13 = 0;
+    s.f14 = 0;
+    s.f15 = 0;
+    s.f16 = 0;
+    s.f17 = 0;
+    s.f18 = 0;
+    s.f19 = 0;
+    s.f20 = 0;
+    s.f21 = 0;
+    s.f22 = 0;
+    s.f23 = 0;
+    s.f24 = 0;
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c
new file mode 100644
index 000000000..2566423a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-compare-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "cmpw" } } */
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 16458: Extraneous compare.  */
+
+int foo (unsigned a, unsigned b)
+{
+  if (a == b) return 1;
+  if (a > b)  return 2;
+  if (a < b)  return 3;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c
new file mode 100644
index 000000000..cd15586c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-eabi.c
@@ -0,0 +1,5 @@
+/* PR target/16952 */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_eabi_ok } */
+/* { dg-options "-meabi -mrelocatable" } */
+char *s = "boo";
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
new file mode 100644
index 000000000..496a6e340
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
@@ -0,0 +1,10 @@
+/* PR rtl-optimization/10588 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int foo(int x)
+{
+  return x == 0;
+}
+
+/* { dg-final { scan-assembler "cntlzw|isel" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c
new file mode 100644
index 000000000..a3d532485
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-1.c
@@ -0,0 +1,183 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times "xvmadd" 4 } } */
+/* { dg-final { scan-assembler-times "xsmadd\|fmadd\ " 2 } } */
+/* { dg-final { scan-assembler-times "fmadds" 2 } } */
+/* { dg-final { scan-assembler-times "xvmsub" 2 } } */
+/* { dg-final { scan-assembler-times "xsmsub\|fmsub\ " 1 } } */
+/* { dg-final { scan-assembler-times "fmsubs" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmadd" 2 } } */
+/* { dg-final { scan-assembler-times "xsnmadd\|fnmadd " 1 } } */
+/* { dg-final { scan-assembler-times "fnmadds" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmsub" 2 } } */
+/* { dg-final { scan-assembler-times "xsnmsub\|fnmsub " 1 } } */
+/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */
+
+/* All functions should generate an appropriate (a * b) + c instruction
+   since -mfused-madd is on by default.  */
+
+double
+builtin_fma (double b, double c, double d)
+{
+  return __builtin_fma (b, c, d);			/* xsmadd{a,m}dp */
+}
+
+double
+builtin_fms (double b, double c, double d)
+{
+  return __builtin_fma (b, c, -d);			/* xsmsub{a,b}dp */
+}
+
+double
+builtin_fnma (double b, double c, double d)
+{
+  return - __builtin_fma (b, c, d);			/* xsnmadd{a,b}dp */
+}
+
+double
+builtin_fnms (double b, double c, double d)
+{
+  return - __builtin_fma (b, c, -d);			/* xsnmsub{a,b}dp */
+}
+
+float
+builtin_fmaf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, d);			/* fmadds */
+}
+
+float
+builtin_fmsf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, -d);			/* fmsubs */
+}
+
+float
+builtin_fnmaf (float b, float c, float d)
+{
+  return - __builtin_fmaf (b, c, d);			/* fnmadds */
+}
+
+float
+builtin_fnmsf (float b, float c, float d)
+{
+  return - __builtin_fmaf (b, c, -d);			/* fnmsubs */
+}
+
+double
+normal_fma (double b, double c, double d)
+{
+  return (b * c) + d;					/* xsmadd{a,m}dp */
+}
+
+float
+normal_fmaf (float b, float c, float d)
+{
+  return (b * c) + d;					/* fmadds */
+}
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+double vda[SIZE] __attribute__((__aligned__(32)));
+double vdb[SIZE] __attribute__((__aligned__(32)));
+double vdc[SIZE] __attribute__((__aligned__(32)));
+double vdd[SIZE] __attribute__((__aligned__(32)));
+
+float vfa[SIZE] __attribute__((__aligned__(32)));
+float vfb[SIZE] __attribute__((__aligned__(32)));
+float vfc[SIZE] __attribute__((__aligned__(32)));
+float vfd[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_fma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]);	/* xvmadd{a,m}dp */
+}
+
+void
+vector_fms (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]);	/* xvmsub{a,m}dp */
+}
+
+void
+vector_fnma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = - __builtin_fma (vdb[i], vdc[i], vdd[i]);	/* xvnmadd{a,m}dp */
+}
+
+void
+vector_fnms (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = - __builtin_fma (vdb[i], vdc[i], -vdd[i]);	/* xvnmsub{a,m}dp */
+}
+
+void
+vector_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]);	/* xvmadd{a,m}sp */
+}
+
+void
+vector_fmsf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]);	/* xvmsub{a,m}sp */
+}
+
+void
+vector_fnmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], vfd[i]);	/* xvnmadd{a,m}sp */
+}
+
+void
+vector_fnmsf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvnmsub{a,m}sp */
+}
+
+void
+vnormal_fma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = (vdb[i] * vdc[i]) + vdd[i];		/* xvmadd{a,m}dp */
+}
+
+void
+vnormal_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = (vfb[i] * vfc[i]) + vfd[i];		/* xvmadd{a,m}sp */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c
new file mode 100644
index 000000000..f732b9fa4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-2.c
@@ -0,0 +1,183 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -ffp-contract=off" } */
+/* { dg-final { scan-assembler-times "xvmadd" 2 } } */
+/* { dg-final { scan-assembler-times "xsmadd\|fmadd\ " 1 } } */
+/* { dg-final { scan-assembler-times "fmadds" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsub" 2 } } */
+/* { dg-final { scan-assembler-times "xsmsub\|fmsub\ " 1 } } */
+/* { dg-final { scan-assembler-times "fmsubs" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmadd" 2 } } */
+/* { dg-final { scan-assembler-times "xsnmadd\|fnmadd\ " 1 } } */
+/* { dg-final { scan-assembler-times "fnmadds" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmsub" 2 } } */
+/* { dg-final { scan-assembler-times "xsnmsub\|fnmsub\ " 1 } } */
+/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */
+
+/* Only the functions calling the bulitin should generate an appropriate (a *
+   b) + c instruction.  */
+
+double
+builtin_fma (double b, double c, double d)
+{
+  return __builtin_fma (b, c, d);			/* xsmadd{a,m}dp */
+}
+
+double
+builtin_fms (double b, double c, double d)
+{
+  return __builtin_fma (b, c, -d);			/* xsmsub{a,b}dp */
+}
+
+double
+builtin_fnma (double b, double c, double d)
+{
+  return - __builtin_fma (b, c, d);			/* xsnmadd{a,b}dp */
+}
+
+double
+builtin_fnms (double b, double c, double d)
+{
+  return - __builtin_fma (b, c, -d);			/* xsnmsub{a,b}dp */
+}
+
+float
+builtin_fmaf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, d);			/* fmadds */
+}
+
+float
+builtin_fmsf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, -d);			/* fmsubs */
+}
+
+float
+builtin_fnmaf (float b, float c, float d)
+{
+  return - __builtin_fmaf (b, c, d);			/* fnmadds */
+}
+
+float
+builtin_fnmsf (float b, float c, float d)
+{
+  return - __builtin_fmaf (b, c, -d);			/* fnmsubs */
+}
+
+double
+normal_fma (double b, double c, double d)
+{
+  return (b * c) + d;					/* fmul/fadd */
+}
+
+float
+normal_fmaf (float b, float c, float d)
+{
+  return (b * c) + d;					/* fmuls/fadds */
+}
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+double vda[SIZE] __attribute__((__aligned__(32)));
+double vdb[SIZE] __attribute__((__aligned__(32)));
+double vdc[SIZE] __attribute__((__aligned__(32)));
+double vdd[SIZE] __attribute__((__aligned__(32)));
+
+float vfa[SIZE] __attribute__((__aligned__(32)));
+float vfb[SIZE] __attribute__((__aligned__(32)));
+float vfc[SIZE] __attribute__((__aligned__(32)));
+float vfd[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_fma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (vdb[i], vdc[i], vdd[i]);	/* xvmadd{a,m}dp */
+}
+
+void
+vector_fms (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = __builtin_fma (vdb[i], vdc[i], -vdd[i]);	/* xvmsub{a,m}dp */
+}
+
+void
+vector_fnma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = - __builtin_fma (vdb[i], vdc[i], vdd[i]);	/* xvnmadd{a,m}dp */
+}
+
+void
+vector_fnms (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = - __builtin_fma (vdb[i], vdc[i], -vdd[i]);	/* xvnmsub{a,m}dp */
+}
+
+void
+vector_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]);	/* xvmadd{a,m}sp */
+}
+
+void
+vector_fmsf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], -vfd[i]);	/* xvmsub{a,m}sp */
+}
+
+void
+vector_fnmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], vfd[i]);	/* xvnmadd{a,m}sp */
+}
+
+void
+vector_fnmsf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = - __builtin_fmaf (vfb[i], vfc[i], -vfd[i]); /* xvnmsub{a,m}sp */
+}
+
+void
+vnormal_fma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vda[i] = (vdb[i] * vdc[i]) + vdd[i];		/* xvmadd{a,m}dp */
+}
+
+void
+vnormal_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = (vfb[i] * vfc[i]) + vfd[i];		/* xvmadd{a,m}sp */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c
new file mode 100644
index 000000000..3203704be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-3.c
@@ -0,0 +1,104 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -maltivec -ffast-math" } */
+/* { dg-final { scan-assembler-times "vmaddfp" 2 } } */
+/* { dg-final { scan-assembler-times "fmadd " 2 } } */
+/* { dg-final { scan-assembler-times "fmadds" 2 } } */
+/* { dg-final { scan-assembler-times "fmsub " 1 } } */
+/* { dg-final { scan-assembler-times "fmsubs" 1 } } */
+/* { dg-final { scan-assembler-times "fnmadd " 1 } } */
+/* { dg-final { scan-assembler-times "fnmadds" 1 } } */
+/* { dg-final { scan-assembler-times "fnmsub " 1 } } */
+/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */
+
+/* All functions should generate an appropriate (a * b) + c instruction
+   since -mfused-madd is on by default.  */
+
+double
+builtin_fma (double b, double c, double d)
+{
+  return __builtin_fma (b, c, d);			/* fmadd */
+}
+
+double
+builtin_fms (double b, double c, double d)
+{
+  return __builtin_fma (b, c, -d);			/* fmsub */
+}
+
+double
+builtin_fnma (double b, double c, double d)
+{
+  return - __builtin_fma (b, c, d);			/* fnmadd */
+}
+
+double
+builtin_fnms (double b, double c, double d)
+{
+  return - __builtin_fma (b, c, -d);			/* fnmsub */
+}
+
+float
+builtin_fmaf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, d);			/* fmadds */
+}
+
+float
+builtin_fmsf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, -d);			/* fmsubs */
+}
+
+float
+builtin_fnmaf (float b, float c, float d)
+{
+  return - __builtin_fmaf (b, c, d);			/* fnmadds */
+}
+
+float
+builtin_fnmsf (float b, float c, float d)
+{
+  return - __builtin_fmaf (b, c, -d);			/* fnmsubs */
+}
+
+double
+normal_fma (double b, double c, double d)
+{
+  return (b * c) + d;					/* fmadd */
+}
+
+float
+normal_fmaf (float b, float c, float d)
+{
+  return (b * c) + d;					/* fmadds */
+}
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+float vfa[SIZE] __attribute__((__aligned__(32)));
+float vfb[SIZE] __attribute__((__aligned__(32)));
+float vfc[SIZE] __attribute__((__aligned__(32)));
+float vfd[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]);	/* vaddfp */
+}
+
+void
+vnormal_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = (vfb[i] * vfc[i]) + vfd[i];		/* vaddfp */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c
new file mode 100644
index 000000000..35836eec2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-4.c
@@ -0,0 +1,95 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -maltivec -ffast-math -ffp-contract=off" } */
+/* { dg-final { scan-assembler-times "vmaddfp" 1 } } */
+/* { dg-final { scan-assembler-times "fmadd " 1 } } */
+/* { dg-final { scan-assembler-times "fmadds" 1 } } */
+/* { dg-final { scan-assembler-times "fmsub " 1 } } */
+/* { dg-final { scan-assembler-times "fmsubs" 1 } } */
+/* { dg-final { scan-assembler-times "fnmadd " 1 } } */
+/* { dg-final { scan-assembler-times "fnmadds" 1 } } */
+/* { dg-final { scan-assembler-times "fnmsub " 1 } } */
+/* { dg-final { scan-assembler-times "fnmsubs" 1 } } */
+
+/* Only the functions calling the builtin should generate an appropriate
+   (a * b) + c instruction.  */
+
+double
+builtin_fma (double b, double c, double d)
+{
+  return __builtin_fma (b, c, d);			/* fmadd */
+}
+
+double
+builtin_fms (double b, double c, double d)
+{
+  return __builtin_fma (b, c, -d);			/* fmsub */
+}
+
+double
+builtin_fnma (double b, double c, double d)
+{
+  return - __builtin_fma (b, c, d);			/* fnmadd */
+}
+
+double
+builtin_fnms (double b, double c, double d)
+{
+  return - __builtin_fma (b, c, -d);			/* fnmsub */
+}
+
+float
+builtin_fmaf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, d);			/* fmadds */
+}
+
+float
+builtin_fmsf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, -d);			/* fmsubs */
+}
+
+float
+builtin_fnmaf (float b, float c, float d)
+{
+  return - __builtin_fmaf (b, c, d);			/* fnmadds */
+}
+
+float
+builtin_fnmsf (float b, float c, float d)
+{
+  return - __builtin_fmaf (b, c, -d);			/* fnmsubs */
+}
+
+double
+normal_fma (double b, double c, double d)
+{
+  return (b * c) + d;					/* fmul/fadd */
+}
+
+float
+normal_fmaf (float b, float c, float d)
+{
+  return (b * c) + d;					/* fmuls/fadds */
+}
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+float vfa[SIZE] __attribute__((__aligned__(32)));
+float vfb[SIZE] __attribute__((__aligned__(32)));
+float vfc[SIZE] __attribute__((__aligned__(32)));
+float vfd[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_fmaf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    vfa[i] = __builtin_fmaf (vfb[i], vfc[i], vfd[i]);	/* vaddfp */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c
new file mode 100644
index 000000000..e5ba874e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-5.c
@@ -0,0 +1,27 @@
+/* { dg-do run { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O2 -mcpu=power5 -std=c99" } */
+
+#ifndef __FP_FAST_FMA
+#error "__FP_FAST_FMA should be defined"
+#endif
+
+#ifndef __FP_FAST_FMAF
+#error "__FP_FAST_FMAF should be defined"
+#endif
+
+double d_a = 2.0,  d_b = 3.0,  d_c = 4.0;
+float  f_a = 2.0f, f_b = 3.0f, f_c = 4.0f;
+
+int
+main (void)
+{
+  if (__builtin_fma (d_a, d_b, d_c) != (2.0 * 3.0) + 4.0)
+    __builtin_abort ();
+
+  if (__builtin_fmaf (f_a, f_b, f_c) != (2.0f * 3.0f) + 4.0f)
+    __builtin_abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c
new file mode 100644
index 000000000..c9132bbf8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-6.c
@@ -0,0 +1,28 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=power5 -std=c99 -msoft-float" } */
+/* { dg-final { scan-assembler-not "fmadd" } } */
+/* { dg-final { scan-assembler-not "xsfmadd" } } */
+
+/* Test whether -msoft-float turns off the macros math.h uses for
+   FP_FAST_FMA{,F,L}.  */
+#ifdef __FP_FAST_FMA
+#error "__FP_FAST_FMA should not be defined"
+#endif
+
+#ifdef __FP_FAST_FMAF
+#error "__FP_FAST_FMAF should not be defined"
+#endif
+
+double
+builtin_fma (double b, double c, double d)
+{
+  return __builtin_fma (b, c, d);			/* bl fma  */
+}
+
+float
+builtin_fmaf (float b, float c, float d)
+{
+  return __builtin_fmaf (b, c, -d);			/* bl fmaf */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c
new file mode 100644
index 000000000..f6e7e4ce5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fma-7.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O3 -ftree-vectorize -mcpu=power6 -ffast-math" } */
+/* { dg-final { scan-assembler-times "fmadd" 1 } } */
+/* { dg-final { scan-assembler-times "fmsub " 1 } } */
+/* { dg-final { scan-assembler-not "fmul" } } */
+/* { dg-final { scan-assembler-not "fadd " } } */
+
+/* Check whether the common FFT idiom (a*b)+c and (a*b)-c generates two fma
+   instructions, instead of a multiply, add, and subtract.  */
+
+void
+fft (double *result, double a, double b, double c)
+{
+  result[0] = (a*b) + c;
+  result[1] = (a*b) - c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c
new file mode 100644
index 000000000..ff959f2d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-1.c
@@ -0,0 +1,43 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-ffast-math -O2" } */
+/* { dg-final { scan-assembler-not "f(add|sub|mul|neg)" } } */
+
+void foo(double *a, double *b, double *c, double *d)
+{
+  a[0] =  b[0] + c[0] * d[0];		// fmadd
+  a[1] =  b[1] - c[1] * d[1];		// fnmsub with fast-math
+  a[2] = -b[2] + c[2] * d[2];   	// fmsub
+  a[3] = -b[3] - c[3] * d[3];		// fnmadd with fast-math
+  a[4] = -( b[4] + c[4] * d[4]);	// fnmadd
+  a[5] = -( b[5] - c[5] * d[5]);	// fmsub with fast-math
+  a[6] = -(-b[6] + c[6] * d[6]);	// fnmsub
+  a[7] = -(-b[7] - c[7] * d[7]);	// fmadd with fast-math
+  a[10] =  b[10] - c[10] * -d[10];	// fmadd
+  a[11] =  b[11] + c[11] * -d[11];	// fnmsub with fast-math
+  a[12] = -b[12] - c[12] * -d[12];   	// fmsub
+  a[13] = -b[13] + c[13] * -d[13];	// fnmadd with fast-math
+  a[14] = -( b[14] - c[14] * -d[14]);	// fnmadd
+  a[15] = -( b[15] + c[15] * -d[15]);	// fmsub with fast-math
+  a[16] = -(-b[16] - c[16] * -d[16]);	// fnmsub
+  a[17] = -(-b[17] + c[17] * -d[17]);	// fmadd with fast-math
+}
+
+void foos(float *a, float *b, float *c, float *d)
+{
+  a[0] =  b[0] + c[0] * d[0];		// fmadd
+  a[1] =  b[1] - c[1] * d[1];		// fnmsub with fast-math
+  a[2] = -b[2] + c[2] * d[2];   	// fmsub
+  a[3] = -b[3] - c[3] * d[3];		// fnmadd with fast-math
+  a[4] = -( b[4] + c[4] * d[4]);	// fnmadd
+  a[5] = -( b[5] - c[5] * d[5]);	// fmsub with fast-math
+  a[6] = -(-b[6] + c[6] * d[6]);	// fnmsub
+  a[7] = -(-b[7] - c[7] * d[7]);	// fmadd with fast-math
+  a[10] =  b[10] - c[10] * -d[10];	// fmadd
+  a[11] =  b[11] + c[11] * -d[11];	// fnmsub with fast-math
+  a[12] = -b[12] - c[12] * -d[12];   	// fmsub
+  a[13] = -b[13] + c[13] * -d[13];	// fnmadd with fast-math
+  a[14] = -( b[14] - c[14] * -d[14]);	// fnmadd
+  a[15] = -( b[15] + c[15] * -d[15]);	// fmsub with fast-math
+  a[16] = -(-b[16] - c[16] * -d[16]);	// fnmsub
+  a[17] = -(-b[17] + c[17] * -d[17]);	// fmadd with fast-math
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c
new file mode 100644
index 000000000..02ed811da
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "f(add|sub|mul|neg)" } } */
+
+void foo(double *a, double *b, double *c, double *d)
+{
+  a[0] =  b[0] + c[0] * d[0];		// fmadd
+  a[2] = -b[2] + c[2] * d[2];   	// fmsub
+  a[4] = -( b[4] + c[4] * d[4]);	// fnmadd
+  a[6] = -(-b[6] + c[6] * d[6]);	// fnmsub
+  a[10] =  b[10] - c[10] * -d[10];	// fmadd
+  a[12] = -b[12] - c[12] * -d[12];   	// fmsub
+  a[14] = -( b[14] - c[14] * -d[14]);	// fnmadd
+  a[16] = -(-b[16] - c[16] * -d[16]);	// fnmsub
+}
+
+void foos(float *a, float *b, float *c, float *d)
+{
+  a[0] =  b[0] + c[0] * d[0];		// fmadd
+  a[2] = -b[2] + c[2] * d[2];   	// fmsub
+  a[4] = -( b[4] + c[4] * d[4]);	// fnmadd
+  a[6] = -(-b[6] + c[6] * d[6]);	// fnmsub
+  a[10] =  b[10] - c[10] * -d[10];	// fmadd
+  a[12] = -b[12] - c[12] * -d[12];   	// fmsub
+  a[14] = -( b[14] - c[14] * -d[14]);	// fnmadd
+  a[16] = -(-b[16] - c[16] * -d[16]);	// fnmsub
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c
new file mode 100644
index 000000000..d4205225c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fmadd-3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "f(add|sub|mul)" } } */
+
+void foo(double *a, double *b, double *c, double *d)
+{
+#if 0
+  a[1] =  b[1] - c[1] * d[1];		// fneg, fmadd without fast-math
+#endif
+  a[3] = -b[3] - c[3] * d[3];		// fneg, fmsub without fast-math
+#if 0
+  a[5] = -( b[5] - c[5] * d[5]);	// fneg, fnmadd without fast-math
+#endif
+  a[7] = -(-b[7] - c[7] * d[7]);	// fneg, fnmsub without fast-math
+  a[11] =  b[11] + c[11] * -d[11];	// fneg, fmadd without fast-math
+  a[13] = -b[13] + c[13] * -d[13];	// fneg, fmsub without fast-math
+  a[15] = -( b[15] + c[15] * -d[15]);	// fneg, fnmadd without fast-math
+  a[17] = -(-b[17] + c[17] * -d[17]);	// fneg, fnmsub without fast-math
+}
+
+void foos(float *a, float *b, float *c, float *d)
+{
+#if 0
+  a[1] =  b[1] - c[1] * d[1];		// fneg, fmadd without fast-math
+#endif
+  a[3] = -b[3] - c[3] * d[3];		// fneg, fmsub without fast-math
+#if 0
+  a[5] = -( b[5] - c[5] * d[5]);	// fneg, fnmadd without fast-math
+#endif
+  a[7] = -(-b[7] - c[7] * d[7]);	// fneg, fnmsub without fast-math
+  a[11] =  b[11] + c[11] * -d[11];	// fneg, fmadd without fast-math
+  a[13] = -b[13] + c[13] * -d[13];	// fneg, fmsub without fast-math
+  a[15] = -( b[15] + c[15] * -d[15]);	// fneg, fnmadd without fast-math
+  a[17] = -(-b[17] + c[17] * -d[17]);	// fneg, fnmsub without fast-math
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c
new file mode 100644
index 000000000..8a6cc08b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-1.c
@@ -0,0 +1,50 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
+/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
+/* { dg-final { scan-assembler-times "fcfids" 3 } } */
+/* { dg-final { scan-assembler-times "fcfidus" 1 } } */
+/* { dg-final { scan-assembler-times "xscvsxddp" 3 } } */
+/* { dg-final { scan-assembler-times "xscvuxddp" 1 } } */
+
+void int_to_float (float *dest, int *src)
+{
+  *dest = (float) *src;
+}
+
+void int_to_double (double *dest, int *src)
+{
+  *dest = (double) *src;
+}
+
+void uint_to_float (float *dest, unsigned int *src)
+{
+  *dest = (float) *src;
+}
+
+void uint_to_double (double *dest, unsigned int *src)
+{
+  *dest = (double) *src;
+}
+
+void llong_to_float (float *dest, long long *src)
+{
+  *dest = (float) *src;
+}
+
+void llong_to_double (double *dest, long long *src)
+{
+  *dest = (double) *src;
+}
+
+void ullong_to_float (float *dest, unsigned long long *src)
+{
+  *dest = (float) *src;
+}
+
+void ullong_to_double (double *dest, unsigned long long *src)
+{
+  *dest = (double) *src;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c
new file mode 100644
index 000000000..59ba5f91f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-10.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler "xsrdpiz" } } */
+/* { dg-final { scan-assembler-not "friz" } } */
+
+double round_double_llong (double a)
+{
+  return (double)(long long)a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c
new file mode 100644
index 000000000..23b3d1e15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-11.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O2 -mcpu=power5+ -ffast-math" } */
+/* { dg-final { scan-assembler-not "xsrdpiz" } } */
+/* { dg-final { scan-assembler "friz" } } */
+
+double round_double_llong (double a)
+{
+  return (double)(long long)a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c
new file mode 100644
index 000000000..e0a834225
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-2.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power6 -ffast-math" } */
+/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
+/* { dg-final { scan-assembler-not "lfiwzx" } } */
+/* { dg-final { scan-assembler-times "fcfid " 10 } } */
+/* { dg-final { scan-assembler-not "fcfids" } } */
+/* { dg-final { scan-assembler-not "fcfidus" } } */
+/* { dg-final { scan-assembler-not "xscvsxddp" } } */
+/* { dg-final { scan-assembler-not "xscvuxddp" } } */
+
+void int_to_float (float *dest, int *src)
+{
+  *dest = (float) *src;
+}
+
+void int_to_double (double *dest, int *src)
+{
+  *dest = (double) *src;
+}
+
+void uint_to_float (float *dest, unsigned int *src)
+{
+  *dest = (float) *src;
+}
+
+void uint_to_double (double *dest, unsigned int *src)
+{
+  *dest = (double) *src;
+}
+
+void llong_to_float (float *dest, long long *src)
+{
+  *dest = (float) *src;
+}
+
+void llong_to_double (double *dest, long long *src)
+{
+  *dest = (double) *src;
+}
+
+void ullong_to_float (float *dest, unsigned long long *src)
+{
+  *dest = (float) *src;
+}
+
+void ullong_to_double (double *dest, unsigned long long *src)
+{
+  *dest = (double) *src;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c
new file mode 100644
index 000000000..bf12113d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-3.c
@@ -0,0 +1,52 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O2 -mcpu=power5 -ffast-math" } */
+/* { dg-final { scan-assembler-not "lfiwax" } } */
+/* { dg-final { scan-assembler-not "lfiwzx" } } */
+/* { dg-final { scan-assembler-times "fcfid " 10 } } */
+/* { dg-final { scan-assembler-not "fcfids" } } */
+/* { dg-final { scan-assembler-not "fcfidus" } } */
+/* { dg-final { scan-assembler-not "xscvsxddp" } } */
+/* { dg-final { scan-assembler-not "xscvuxddp" } } */
+
+void int_to_float (float *dest, int *src)
+{
+  *dest = (float) *src;
+}
+
+void int_to_double (double *dest, int *src)
+{
+  *dest = (double) *src;
+}
+
+void uint_to_float (float *dest, unsigned int *src)
+{
+  *dest = (float) *src;
+}
+
+void uint_to_double (double *dest, unsigned int *src)
+{
+  *dest = (double) *src;
+}
+
+void llong_to_float (float *dest, long long *src)
+{
+  *dest = (float) *src;
+}
+
+void llong_to_double (double *dest, long long *src)
+{
+  *dest = (double) *src;
+}
+
+void ullong_to_float (float *dest, unsigned long long *src)
+{
+  *dest = (float) *src;
+}
+
+void ullong_to_double (double *dest, unsigned long long *src)
+{
+  *dest = (double) *src;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c
new file mode 100644
index 000000000..c4b9ea69b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-4.c
@@ -0,0 +1,51 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O2 -mcpu=750 -ffast-math" } */
+/* { dg-final { scan-assembler-not "lfiwax" } } */
+/* { dg-final { scan-assembler-not "lfiwzx" } } */
+/* { dg-final { scan-assembler-not "fcfid " } } */
+/* { dg-final { scan-assembler-not "fcfids" } } */
+/* { dg-final { scan-assembler-not "fcfidus" } } */
+/* { dg-final { scan-assembler-not "xscvsxddp" } } */
+/* { dg-final { scan-assembler-not "xscvuxddp" } } */
+
+void int_to_float (float *dest, int *src)
+{
+  *dest = (float) *src;
+}
+
+void int_to_double (double *dest, int *src)
+{
+  *dest = (double) *src;
+}
+
+void uint_to_float (float *dest, unsigned int *src)
+{
+  *dest = (float) *src;
+}
+
+void uint_to_double (double *dest, unsigned int *src)
+{
+  *dest = (double) *src;
+}
+
+void llong_to_float (float *dest, long long *src)
+{
+  *dest = (float) *src;
+}
+
+void llong_to_double (double *dest, long long *src)
+{
+  *dest = (double) *src;
+}
+
+void ullong_to_float (float *dest, unsigned long long *src)
+{
+  *dest = (float) *src;
+}
+
+void ullong_to_double (double *dest, unsigned long long *src)
+{
+  *dest = (double) *src;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c
new file mode 100644
index 000000000..a071fc122
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-5.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-times "fctiwz" 2 } } */
+/* { dg-final { scan-assembler-times "fctiwuz" 2 } } */
+/* { dg-final { scan-assembler-times "fctidz" 1 } } */
+/* { dg-final { scan-assembler-times "fctiduz" 1 } } */
+/* { dg-final { scan-assembler-times "xscvdpsxds" 1 } } */
+/* { dg-final { scan-assembler-times "xscvdpuxds" 1 } } */
+
+void float_to_int  (int *dest, float  src) { *dest = (int) src; }
+void double_to_int (int *dest, double src) { *dest = (int) src; }
+
+void float_to_uint  (int *dest, float  src) { *dest = (unsigned int) src; }
+void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; }
+
+void float_to_llong  (long long *dest, float  src) { *dest = (long long) src; }
+void double_to_llong (long long *dest, double src) { *dest = (long long) src; }
+
+void float_to_ullong  (unsigned long long *dest, float  src) { *dest = (unsigned long long) src; }
+void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c
new file mode 100644
index 000000000..09ee1885a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-6.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power6 -ffast-math" } */
+/* { dg-final { scan-assembler-times "fctiwz" 2 } } */
+/* { dg-final { scan-assembler-not "fctiwuz" } } */
+/* { dg-final { scan-assembler-times "fctidz" 8 } } */
+/* { dg-final { scan-assembler-not "fctiduz" } } */
+/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
+/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+
+void float_to_int  (int *dest, float  src) { *dest = (int) src; }
+void double_to_int (int *dest, double src) { *dest = (int) src; }
+
+void float_to_uint  (int *dest, float  src) { *dest = (unsigned int) src; }
+void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; }
+
+void float_to_llong  (long long *dest, float  src) { *dest = (long long) src; }
+void double_to_llong (long long *dest, double src) { *dest = (long long) src; }
+
+void float_to_ullong  (unsigned long long *dest, float  src) { *dest = (unsigned long long) src; }
+void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c
new file mode 100644
index 000000000..808cbc390
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-7.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O3 -mcpu=power5 -ffast-math" } */
+/* { dg-final { scan-assembler-times "fctiwz" 2 } } */
+/* { dg-final { scan-assembler-not "fctiwuz" } } */
+/* { dg-final { scan-assembler-times "fctidz" 8 } } */
+/* { dg-final { scan-assembler-not "fctiduz" } } */
+/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
+/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+
+void float_to_int  (int *dest, float  src) { *dest = (int) src; }
+void double_to_int (int *dest, double src) { *dest = (int) src; }
+
+void float_to_uint  (int *dest, float  src) { *dest = (unsigned int) src; }
+void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; }
+
+void float_to_llong  (long long *dest, float  src) { *dest = (long long) src; }
+void double_to_llong (long long *dest, double src) { *dest = (long long) src; }
+
+void float_to_ullong  (unsigned long long *dest, float  src) { *dest = (unsigned long long) src; }
+void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c
new file mode 100644
index 000000000..f841d7ee0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O3 -mcpu=750 -ffast-math" } */
+/* { dg-final { scan-assembler-times "fctiwz" 6 } } */
+/* { dg-final { scan-assembler-not "fctiwuz" } } */
+/* { dg-final { scan-assembler-not "fctidz" } } */
+/* { dg-final { scan-assembler-not "fctiduz" } } */
+/* { dg-final { scan-assembler-not "xscvdpsxds" } } */
+/* { dg-final { scan-assembler-not "xscvdpuxds" } } */
+
+void float_to_int  (int *dest, float  src) { *dest = (int) src; }
+void double_to_int (int *dest, double src) { *dest = (int) src; }
+
+void float_to_uint  (int *dest, float  src) { *dest = (unsigned int) src; }
+void double_to_uint (int *dest, double src) { *dest = (unsigned int) src; }
+
+void float_to_llong  (long long *dest, float  src) { *dest = (long long) src; }
+void double_to_llong (long long *dest, double src) { *dest = (long long) src; }
+
+void float_to_ullong  (unsigned long long *dest, float  src) { *dest = (unsigned long long) src; }
+void double_to_ullong (unsigned long long *dest, double src) { *dest = (unsigned long long) src; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c
new file mode 100644
index 000000000..836c030ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fpconv-9.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler-not "lwz" } } */
+/* { dg-final { scan-assembler-not "stw" } } */
+/* { dg-final { scan-assembler-not "ld " } } */
+/* { dg-final { scan-assembler-not "std" } } */
+
+void float_to_llong  (long long *dest, float  src) { *dest = (long long) src; }
+void double_to_llong (long long *dest, double src) { *dest = (long long) src; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c
new file mode 100644
index 000000000..8d364352a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O -mpowerpc-gfxopt -fno-trapping-math" } */
+/* { dg-final { scan-assembler "fsel" } } */
+
+/* If the user doesn't care about signals, fsel can be used in many cases.  */
+
+double foo(double a, double b, double c, double d)
+{
+  return a < b ? c : d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c
new file mode 100644
index 000000000..9768b165c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-2.c
@@ -0,0 +1,80 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O -mpowerpc-gfxopt -g0 -ffinite-math-only" } */
+/* { dg-final { scan-assembler-not "^L" } } */
+
+/* Every single one of these should be compiled into straight-line
+   code using fsel (or, in a few cases, hardwired to 'true' or
+   'false'), no branches anywhere.  */
+
+double
+test_isunordered(double x, double y, double a, double b)
+{
+  return __builtin_isunordered(x, y) ? a : b;
+}
+
+double
+test_not_isunordered(double x, double y, double a, double b)
+{
+  return !__builtin_isunordered(x, y) ? a : b;
+}
+
+double
+test_isless(double x, double y, double a, double b)
+{
+  return __builtin_isless(x, y) ? a : b;
+}
+
+double
+test_not_isless(double x, double y, double a, double b)
+{
+  return !__builtin_isless(x, y) ? a : b;
+}
+
+double
+test_islessequal(double x, double y, double a, double b)
+{
+  return __builtin_islessequal(x, y) ? a : b;
+}
+
+double
+test_not_islessequal(double x, double y, double a, double b)
+{
+  return !__builtin_islessequal(x, y) ? a : b;
+}
+
+double
+test_isgreater(double x, double y, double a, double b)
+{
+  return __builtin_isgreater(x, y) ? a : b;
+}
+
+double
+test_not_isgreater(double x, double y, double a, double b)
+{
+  return !__builtin_isgreater(x, y) ? a : b;
+}
+
+double
+test_isgreaterequal(double x, double y, double a, double b)
+{
+  return __builtin_isgreaterequal(x, y) ? a : b;
+}
+
+double
+test_not_isgreaterequal(double x, double y, double a, double b)
+{
+  return !__builtin_isgreaterequal(x, y) ? a : b;
+}
+
+double
+test_islessgreater(double x, double y, double a, double b)
+{
+  return __builtin_islessgreater(x, y) ? a : b;
+}
+
+double
+test_not_islessgreater(double x, double y, double a, double b)
+{
+  return !__builtin_islessgreater(x, y) ? a : b;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c
new file mode 100644
index 000000000..1d07c528e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-fsel-3.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-O -mpowerpc-gfxopt" } */
+/* { dg-final { scan-assembler-not "fsub" } } */
+
+/* Check that an fsub isn't generated when no arithmetic was requested;
+   such an fsub might incorrectly set floating-point exception flags.  */
+
+double foo(double a, double b, double c, double d)
+{
+  return a < b ? c : d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-get-timebase.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-get-timebase.c
new file mode 100644
index 000000000..9de8929af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-get-timebase.c
@@ -0,0 +1,20 @@
+/* { dg-do run { target { powerpc*-*-* } } } */
+
+/* Test if __builtin_ppc_get_timebase () is compatible with the current
+   processor and if it's changing between reads.  A read failure might indicate
+   a Power ISA or binutils change.  */
+
+#include <inttypes.h>
+
+int
+main (void)
+{
+  uint64_t t = __builtin_ppc_get_timebase ();
+  int j;
+
+  for (j = 0; j < 1000000; j++)
+    if (t != __builtin_ppc_get_timebase ())
+      return 0;
+
+  return 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c
new file mode 100644
index 000000000..ffb426477
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-ldstruct.c
@@ -0,0 +1,21 @@
+/* { dg-do run { target powerpc*-*-eabi* powerpc*-*-elf* powerpc*-*-linux* powerpc*-*-rtems* } } */
+/* { dg-options "-O -mlong-double-128" } */
+
+#include <stdlib.h>
+
+/* SVR4 and EABI both specify that 'long double' is aligned to a 128-bit
+   boundary in structures.  */
+
+struct {
+  int x;
+  long double d;
+} s;
+
+int main(void)
+{
+  if (sizeof (s) != 32)
+    abort ();
+  if ((char *)&s.d - (char *)&s != 16)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-mftb.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-mftb.c
new file mode 100644
index 000000000..f64e45d1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-mftb.c
@@ -0,0 +1,18 @@
+/* { dg-do run { target { powerpc*-*-* } } } */
+
+/* Test if __builtin_ppc_mftb () is compatible with the current processor and
+   if it's changing between reads.  A read failure might indicate a Power
+   ISA or binutils change.  */
+
+int
+main (void)
+{
+  unsigned long t = __builtin_ppc_mftb ();
+  int j;
+
+  for (j = 0; j < 1000000; j++)
+    if (t != __builtin_ppc_mftb ())
+      return 0;
+
+  return 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c
new file mode 100644
index 000000000..3a79f9354
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c
@@ -0,0 +1,52 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "lfd \(f?\[0-9\]+\),\[^\n\r\]*\[\n\r\]+\[ \t]*fmr f?1,\\1\[\n\r\]+\[ \t]*blr" } } */
+
+/* Origin:Pete Steinmetz <steinmtz@us.ibm.com> */
+
+/* PR 16796: Extraneous move.  */
+
+static const double huge = 1.0e300;
+typedef int int64_t __attribute__ ((__mode__ (__DI__)));
+typedef unsigned int u_int64_t __attribute__ ((__mode__ (__DI__)));
+
+double __floor(double x)
+{
+  union {
+    double dbl_val;
+    long int long_val;
+  } temp;
+
+  int64_t i0,j0;
+  u_int64_t i;
+  temp.dbl_val = x;
+  i0 = temp.long_val;
+
+  j0 = ((i0>>52)&0x7ff)-0x3ff;
+  if(j0<52) {
+    if(j0<0) {
+      if(huge+x>0.0) {
+        if(i0>=0) {i0=0;}
+        else if((i0&0x7fffffffffffffff)!=0)
+        { i0=0xbff0000000000000;}
+      }
+    } else {
+      i = (0x000fffffffffffff)>>j0;
+      if((i0&i)==0) return x;
+      if(huge+x>0.0) {
+        if(i0<0) i0 += (0x0010000000000000)>>j0;
+        i0 &= (~i);
+      }
+    }
+  } else {
+    if (j0==0x400)
+      return x+x;
+    else
+      return x;
+  }
+  temp.long_val = i0;
+  x = temp.dbl_val;
+  return x;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
new file mode 100644
index 000000000..63c4b6087
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
@@ -0,0 +1,33 @@
+/* PR target/51274 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-isel" } */
+
+/* { dg-final { scan-assembler-times "addic" 4 } } */
+/* { dg-final { scan-assembler-times "subfe" 1 } } */
+/* { dg-final { scan-assembler-times "addze" 3 } } */
+
+long ne0(long a)
+{
+  return a != 0;
+}
+
+long plus_ne0(long a, long b)
+{
+  return (a != 0) + b;
+}
+
+void dummy(void);
+
+void cmp_plus_ne0(long a, long b)
+{
+  if ((a != 0) + b)
+    dummy();
+}
+
+long plus_ne0_cmp(long a, long b)
+{
+  a = (a != 0) + b;
+  if (a)
+    dummy();
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c
new file mode 100644
index 000000000..0386ecba7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+long foo(long x)
+{
+  return -(x == 0);
+}
+
+long bar(long x)
+{
+  long t = __builtin_clzl(x);
+  return -(t>>(sizeof(long) == 8 ? 6 : 5));
+}
+
+/* { dg-final { scan-assembler-not "cntlz" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-paired.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-paired.c
new file mode 100644
index 000000000..be84e431c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-paired.c
@@ -0,0 +1,45 @@
+/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */
+/* { dg-options "-mpaired -ffinite-math-only" } */
+
+/* Test PowerPC PAIRED extensions.  */
+
+#include <paired.h>
+
+vector float a, b, c, d;
+
+void
+test_api ()
+{
+  b = paired_msub (b, c, d);
+  b = paired_madd (b, c, d);
+  b = paired_nmadd (b, c, d);
+  b = paired_nmsub (b, c, d);
+  b = paired_sum0 (a, b, c);
+  b = paired_sum1 (a, b, c);
+  b = paired_div (b, c);
+  b = paired_add (a, c);
+  b = paired_sub (a, c);
+  b = paired_mul (a, c);
+  b = paired_neg (a);
+  b = paired_muls0 (a, c);
+  b = paired_muls1 (a, c);
+  b = paired_madds0 (a, c, d);
+  b = paired_madds1 (a, c, d);
+  b = paired_merge00 (a, c);
+  b = paired_merge01 (a, c);
+  b = paired_merge10 (a, c);
+  b = paired_merge11 (a, c);
+  b = paired_abs (a);
+  b = paired_nabs (a);
+  b = paired_sqrt (a);
+  b = paired_res (a);
+  b = paired_sel (a, b, c);
+}
+
+int
+main (void)
+{
+  test_api ();
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-pow.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-pow.c
new file mode 100644
index 000000000..041a34b09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-pow.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* Check for VSX here, even though we don't use VSX to eliminate SPE, PAIRED
+   and other ppc floating point varients.  However, we need to also eliminate
+   Darwin, since it doesn't like -mcpu=power6.  */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ffast-math -mcpu=power6 -mno-vsx -mno-altivec" } */
+/* { dg-final { scan-assembler-times "fsqrt" 3 } } */
+/* { dg-final { scan-assembler-times "fmul" 1 } } */
+/* { dg-final { scan-assembler-times "bl?\[\\. \]+pow" 1 } } */
+/* { dg-final { scan-assembler-times "bl?\[\\. \]+sqrt" 1 } } */
+
+double
+do_pow_0_75_default (double a)
+{
+  return __builtin_pow (a, 0.75);	/* should generate 2 fsqrts */
+}
+
+double
+do_pow_0_5_default (double a)
+{
+  return __builtin_pow (a, 0.5);	/* should generate fsqrt */
+}
+
+#pragma GCC target "no-powerpc-gpopt,no-powerpc-gfxopt"
+
+double
+do_pow_0_75_nosqrt (double a)
+{
+  return __builtin_pow (a, 0.75);	/* should call pow */
+}
+
+double
+do_pow_0_5_nosqrt (double a)
+{
+  return __builtin_pow (a, 0.5);	/* should call sqrt */
+}
+
+#pragma GCC reset_options
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-round.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-round.c
new file mode 100644
index 000000000..20262aa44
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-round.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler-times "stfiwx" 4 } } */
+/* { dg-final { scan-assembler-times "lfiwax" 2 } } */
+/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
+/* { dg-final { scan-assembler-times "fctiwz" 2 } } */
+/* { dg-final { scan-assembler-times "xscvsxddp" 2 } } */
+/* { dg-final { scan-assembler-times "fcfids" 2 } } */
+/* { dg-final { scan-assembler-not "lwz" } } */
+/* { dg-final { scan-assembler-not "stw" } } */
+
+/* Make sure we don't have loads/stores to the GPR unit.  */
+double
+round_double_int (double a)
+{
+  return (double)(int)a;
+}
+
+float
+round_float_int (float a)
+{
+  return (float)(int)a;
+}
+
+double
+round_double_uint (double a)
+{
+  return (double)(unsigned int)a;
+}
+
+float
+round_float_uint (float a)
+{
+  return (float)(unsigned int)a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c
new file mode 100644
index 000000000..efd5a5ec4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-common -G 8 -meabi -msdata=eabi" } */
+/* { dg-require-effective-target powerpc_eabi_ok } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */
+/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata2," } } */
+/* { dg-final { scan-assembler "sdat@sda21\\((13|0)\\)" } } */
+/* { dg-final { scan-assembler "sdat2@sda21\\((2|0)\\)" } } */
+
+
+int sdat = 2;
+const char sdat2[] = "1234";
+
+const char * test (void)
+{
+  return sdat ? sdat2 : 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c
new file mode 100644
index 000000000..570c81f7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-sdata-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* powerpc-*-rtems* } } } } */
+/* { dg-options "-O2 -fno-common -G 8 -msdata=sysv" } */
+/* { dg-require-effective-target nonpic } */
+/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */
+/* { dg-final { scan-assembler-not "\\.section\[ \t\]\\.sdata2," } } */
+/* { dg-final { scan-assembler "sdat@sdarel\\(13\\)" } } */
+/* { dg-final { scan-assembler "sdat2@sdarel\\(13\\)" } } */
+
+
+int sdat = 2;
+const char sdat2[] = "1234";
+
+const char * test (void)
+{
+  return sdat ? sdat2 : 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-spe.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-spe.c
new file mode 100644
index 000000000..b56439433
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-spe.c
@@ -0,0 +1,663 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+/* (Test with -O0 so we don't optimize any of them away).  */
+
+#include <spe.h>
+
+/* Test PowerPC SPE extensions.  */
+
+#define vector __attribute__((vector_size(8)))
+
+vector int a, b, c, *ap;
+vector float f, g, h;
+unsigned int *uip;
+unsigned short *usp;
+int i, j, *ip;
+uint64_t ull;
+int64_t sll;
+unsigned ui;
+float fl;
+uint16_t u16;
+int16_t s16;
+
+/* These are the only documented/supported accesor functions for the
+   SPE builtins.  */
+void
+test_api ()
+{
+  c = __ev_addw (a, b);
+  c = __ev_addiw (a, 8);
+  c = __ev_subfw (a, b);
+  c = __ev_subifw (8, a);
+  c = __ev_abs (a);
+  c = __ev_neg (a);
+  c = __ev_extsb (a);
+  c = __ev_extsh (a);
+  c = __ev_and (a, b);
+  c = __ev_or (a, b);
+  c = __ev_xor (a, b);
+  c = __ev_nand (a, b);
+  c = __ev_nor (a, b);
+  c = __ev_eqv (a, b);
+  c = __ev_andc (a, b);
+  c = __ev_orc (a, b);
+  c = __ev_rlw (a, b);
+  c = __ev_rlwi (a, 8);
+  c = __ev_slw (a, b);
+  c = __ev_slwi (a, 8);
+  c = __ev_srws (a, b);
+  c = __ev_srwu (a, b);
+  c = __ev_srwis (a, 8);
+  c = __ev_srwiu (a, 8);
+  c = __ev_cntlzw (a);
+  c = __ev_cntlsw (a);
+  c = __ev_rndw (a);
+  c = __ev_mergehi (a, b);
+  c = __ev_mergelo (a, b);
+  c = __ev_mergelohi (a, b);
+  c = __ev_mergehilo (a, b);
+  c = __ev_splati (5);
+  c = __ev_splatfi (6);
+  c = __ev_divws (a, b);
+  c = __ev_divwu (a, b);
+  c = __ev_mra (a);
+  i = __brinc (5, 6);
+
+  /* Loads.  */
+  c = __ev_lddx (ap, i);
+  c = __ev_ldwx (ap, i);
+  c = __ev_ldhx (ap, i);
+
+  c = __ev_lwhex (uip, i);
+  c = __ev_lwhoux (uip, i);
+  c = __ev_lwhosx (uip, i);
+  c = __ev_lwwsplatx (uip, i);
+  c = __ev_lwhsplatx (uip, i);
+
+  c = __ev_lhhesplatx (usp, i);
+  c = __ev_lhhousplatx (usp, i);
+  c = __ev_lhhossplatx (usp, i);
+
+  c = __ev_ldd (ap, 5);
+  c = __ev_ldw (ap, 6);
+  c = __ev_ldh (ap, 7);
+  c = __ev_lwhe (uip, 6);
+  c = __ev_lwhou (uip, 6);
+  c = __ev_lwhos (uip, 7);
+  c = __ev_lwwsplat (uip, 7);
+  c = __ev_lwhsplat (uip, 7);
+  c = __ev_lhhesplat (usp, 7);
+  c = __ev_lhhousplat (usp, 7);
+  c = __ev_lhhossplat (usp, 7);
+
+  /* Stores.  */
+  __ev_stddx (a, ap, 9);
+  __ev_stdwx (a, ap, 9);
+  __ev_stdhx (a, ap, 9);
+  __ev_stwwex (a, uip, 9);
+  __ev_stwwox (a, uip, 9);
+  __ev_stwhex (a, uip, 9);
+  __ev_stwhox (a, uip, 9);
+  __ev_stdd (a, ap, 9);
+  __ev_stdw (a, ap, 9);
+  __ev_stdh (a, ap, 9);
+  __ev_stwwe (a, uip, 9);
+  __ev_stwwo (a, uip, 9);
+  __ev_stwhe (a, uip, 9);
+  __ev_stwho (a, uip, 9);
+
+  /* Fixed point complex.  */
+  c = __ev_mhossf (a, b);
+  c = __ev_mhosmf (a, b);
+  c = __ev_mhosmi (a, b);
+  c = __ev_mhoumi (a, b);
+  c = __ev_mhessf (a, b);
+  c = __ev_mhesmf (a, b);
+  c = __ev_mhesmi (a, b);
+  c = __ev_mheumi (a, b);
+  c = __ev_mhossfa (a, b);
+  c = __ev_mhosmfa (a, b);
+  c = __ev_mhosmia (a, b);
+  c = __ev_mhoumia (a, b);
+  c = __ev_mhessfa (a, b);
+  c = __ev_mhesmfa (a, b);
+  c = __ev_mhesmia (a, b);
+  c = __ev_mheumia (a, b);
+
+  c = __ev_mhoumf (a, b);
+  c = __ev_mheumf (a, b);
+  c = __ev_mhoumfa (a, b);
+  c = __ev_mheumfa (a, b);
+
+  c = __ev_mhossfaaw (a, b);
+  c = __ev_mhossiaaw (a, b);
+  c = __ev_mhosmfaaw (a, b);
+  c = __ev_mhosmiaaw (a, b);
+  c = __ev_mhousiaaw (a, b);
+  c = __ev_mhoumiaaw (a, b);
+  c = __ev_mhessfaaw (a, b);
+  c = __ev_mhessiaaw (a, b);
+  c = __ev_mhesmfaaw (a, b);
+  c = __ev_mhesmiaaw (a, b);
+  c = __ev_mheusiaaw (a, b);
+  c = __ev_mheumiaaw (a, b);
+
+  c = __ev_mhousfaaw (a, b);
+  c = __ev_mhoumfaaw (a, b);
+  c = __ev_mheusfaaw (a, b);
+  c = __ev_mheumfaaw (a, b);
+
+  c = __ev_mhossfanw (a, b);
+  c = __ev_mhossianw (a, b);
+  c = __ev_mhosmfanw (a, b);
+  c = __ev_mhosmianw (a, b);
+  c = __ev_mhousianw (a, b);
+  c = __ev_mhoumianw (a, b);
+  c = __ev_mhessfanw (a, b);
+  c = __ev_mhessianw (a, b);
+  c = __ev_mhesmfanw (a, b);
+  c = __ev_mhesmianw (a, b);
+  c = __ev_mheusianw (a, b);
+  c = __ev_mheumianw (a, b);
+
+  c = __ev_mhousfanw (a, b);
+  c = __ev_mhoumfanw (a, b);
+  c = __ev_mheusfanw (a, b);
+  c = __ev_mheumfanw (a, b);
+
+  c = __ev_mhogsmfaa (a, b);
+  c = __ev_mhogsmiaa (a, b);
+  c = __ev_mhogumiaa (a, b);
+  c = __ev_mhegsmfaa (a, b);
+  c = __ev_mhegsmiaa (a, b);
+  c = __ev_mhegumiaa (a, b);
+
+  c = __ev_mhogumfaa (a, b);
+  c = __ev_mhegumfaa (a, b);
+
+  c = __ev_mhogsmfan (a, b);
+  c = __ev_mhogsmian (a, b);
+  c = __ev_mhogumian (a, b);
+  c = __ev_mhegsmfan (a, b);
+  c = __ev_mhegsmian (a, b);
+  c = __ev_mhegumian (a, b);
+
+  c = __ev_mhogumfan (a, b);
+  c = __ev_mhegumfan (a, b);
+
+  c = __ev_mwhssf (a, b);
+  c = __ev_mwhsmf (a, b);
+  c = __ev_mwhsmi (a, b);
+  c = __ev_mwhumi (a, b);
+  c = __ev_mwhssfa (a, b);
+  c = __ev_mwhsmfa (a, b);
+  c = __ev_mwhsmia (a, b);
+  c = __ev_mwhumia (a, b);
+
+  c = __ev_mwhumf (a, b);
+  c = __ev_mwhumfa (a, b);
+
+  c = __ev_mwlumi (a, b);
+  c = __ev_mwlumia (a, b);
+  c = __ev_mwlumiaaw (a, b);
+
+  c = __ev_mwlssiaaw (a, b);
+  c = __ev_mwlsmiaaw (a, b);
+  c = __ev_mwlusiaaw (a, b);
+  c = __ev_mwlusiaaw (a, b);
+
+  c = __ev_mwlssianw (a, b);
+  c = __ev_mwlsmianw (a, b);
+  c = __ev_mwlusianw (a, b);
+  c = __ev_mwlumianw (a, b);
+
+  c = __ev_mwssf (a, b);
+  c = __ev_mwsmf (a, b);
+  c = __ev_mwsmi (a, b);
+  c = __ev_mwumi (a, b);
+  c = __ev_mwssfa (a, b);
+  c = __ev_mwsmfa (a, b);
+  c = __ev_mwsmia (a, b);
+  c = __ev_mwumia (a, b);
+  c = __ev_mwumf (a, b);
+  c = __ev_mwumfa (a, b);
+  c = __ev_mwssfaa (a, b);
+  c = __ev_mwsmfaa (a, b);
+  c = __ev_mwsmiaa (a, b);
+  c = __ev_mwumiaa (a, b);
+  c = __ev_mwumfaa (a, b);
+  c = __ev_mwssfan (a, b);
+  c = __ev_mwsmfan (a, b);
+  c = __ev_mwsmian (a, b);
+  c = __ev_mwumian (a, b);
+  c = __ev_mwumfan (a, b);
+  c = __ev_addssiaaw (a);
+  c = __ev_addsmiaaw (a);
+  c = __ev_addusiaaw (a);
+  c = __ev_addumiaaw (a);
+  c = __ev_addusfaaw (a);
+  c = __ev_addumfaaw (a);
+  c = __ev_addsmfaaw (a);
+  c = __ev_addssfaaw (a);
+  c = __ev_subfssiaaw (a);
+  c = __ev_subfsmiaaw (a);
+  c = __ev_subfusiaaw (a);
+  c = __ev_subfumiaaw (a);
+  c = __ev_subfusfaaw (a);
+  c = __ev_subfumfaaw (a);
+  c = __ev_subfsmfaaw (a);
+  c = __ev_subfssfaaw (a);
+
+  /* Floating point SIMD instructions.  */
+  c = __ev_fsabs (a);
+  c = __ev_fsnabs (a);
+  c = __ev_fsneg (a);
+  c = __ev_fsadd (a, b);
+  c = __ev_fssub (a, b);
+  c = __ev_fsmul (a, b);
+  c = __ev_fsdiv (a, b);
+  c = __ev_fscfui (a);
+  c = __ev_fscfsi (a);
+  c = __ev_fscfuf (a);
+  c = __ev_fscfsf (a);
+  c = __ev_fsctui (a);
+  c = __ev_fsctsi (a);
+  c = __ev_fsctuf (a);
+  c = __ev_fsctsf (a);
+  c = __ev_fsctuiz (a);
+  c = __ev_fsctsiz (a);
+
+  /* Non supported sythetic instructions made from two instructions.  */
+
+  c = __ev_mwhssfaaw (a, b);
+  c = __ev_mwhssiaaw (a, b);
+  c = __ev_mwhsmfaaw (a, b);
+  c = __ev_mwhsmiaaw (a, b);
+  c = __ev_mwhusiaaw (a, b);
+  c = __ev_mwhumiaaw (a, b);
+  c = __ev_mwhusfaaw (a, b);
+  c = __ev_mwhumfaaw (a, b);
+  c = __ev_mwhssfanw (a, b);
+  c = __ev_mwhssianw (a, b);
+  c = __ev_mwhsmfanw (a, b);
+  c = __ev_mwhsmianw (a, b);
+  c = __ev_mwhusianw (a, b);
+  c = __ev_mwhumianw (a, b);
+  c = __ev_mwhusfanw (a, b);
+  c = __ev_mwhumfanw (a, b);
+
+  c = __ev_mwhgssfaa (a, b);
+  c = __ev_mwhgsmfaa (a, b);
+  c = __ev_mwhgsmiaa (a, b);
+  c = __ev_mwhgumiaa (a, b);
+  c = __ev_mwhgssfan (a, b);
+  c = __ev_mwhgsmfan (a, b);
+  c = __ev_mwhgsmian (a, b);
+  c = __ev_mwhgumian (a, b);
+
+  /* Creating, insertion, and extraction.  */
+
+  a = __ev_create_u64 ((uint64_t) 55);
+  a = __ev_create_s64 ((int64_t) 66);
+  a = __ev_create_fs (3.14F, 2.18F);
+  a = __ev_create_u32 ((uint32_t) 5, (uint32_t) i);
+  a = __ev_create_s32 ((int32_t) 5, (int32_t) 6);
+  a = __ev_create_u16 ((uint16_t) 6, (uint16_t) 6, (uint16_t) 7, (uint16_t) 1);
+  a = __ev_create_s16 ((int16_t) 6, (int16_t) 6, (int16_t) 7, (int16_t) 9);
+  a = __ev_create_sfix32_fs (3.0F, 2.0F);
+  a = __ev_create_ufix32_fs (3.0F, 2.0F);
+  a = __ev_create_ufix32_u32 (3U, 5U);
+  a = __ev_create_sfix32_s32 (6, 9);
+  ull = __ev_convert_u64 (a);
+  sll = __ev_convert_s64 (a);
+  i = __ev_get_upper_u32 (a);
+  ui = __ev_get_lower_u32 (a);
+  i = __ev_get_upper_s32 (a);
+  i = __ev_get_lower_s32 (a);
+  fl = __ev_get_upper_fs (a);
+  fl = __ev_get_lower_fs (a);
+  u16 = __ev_get_u16 (a, 5U);
+  s16 = __ev_get_s16 (a, 5U);
+  ui = __ev_get_upper_ufix32_u32 (a);
+  ui = __ev_get_lower_ufix32_u32 (a);
+  i = __ev_get_upper_sfix32_s32 (a);
+  i = __ev_get_lower_sfix32_s32 (a);
+  fl = __ev_get_upper_sfix32_fs (a);
+  fl = __ev_get_lower_sfix32_fs (a);
+  fl = __ev_get_upper_ufix32_fs (a);
+  fl = __ev_get_lower_ufix32_fs (a);
+  a = __ev_set_upper_u32 (a, 5U);
+  a = __ev_set_lower_u32 (a, 5U);
+  a = __ev_set_upper_s32 (a, 5U);
+  a = __ev_set_lower_s32 (a, 6U);
+  a = __ev_set_upper_fs (a, 6U);
+  a = __ev_set_lower_fs (a, fl);
+  a = __ev_set_upper_ufix32_u32 (a, 5U);
+  a = __ev_set_lower_ufix32_u32 (a, 5U);
+  a = __ev_set_upper_sfix32_s32 (a, 5);
+  a = __ev_set_lower_sfix32_s32 (a, 5);
+  a =  __ev_set_upper_sfix32_fs (a, fl);
+  a = __ev_set_lower_sfix32_fs (a, fl);
+  a = __ev_set_upper_ufix32_fs (a, fl);
+  a = __ev_set_lower_ufix32_fs (a, fl);
+  a = __ev_set_acc_u64 ((uint64_t) 640);
+  a = __ev_set_acc_s64 ((int64_t) 460);
+  a = __ev_set_acc_vec64 (b);
+  a = __ev_set_u32 (a, 5, 6);
+  a = __ev_set_s32 (a, 5, 6);
+  a = __ev_set_fs (a, fl, 5);
+  a = __ev_set_u16 (a, 5U, 3);
+  a = __ev_set_s16 (a, 5, 6);
+  a = __ev_set_ufix32_u32 (a, 5U, 6U);
+  a = __ev_set_sfix32_s32 (a, 3, 6);
+  a = __ev_set_ufix32_fs (a, fl, 5);
+  a = __ev_set_sfix32_fs (a, fl, 5);
+  ui = __ev_get_u32 (a, 1);
+  i = __ev_get_s32 (a, 0);
+  fl = __ev_get_fs (a, 1);
+  u16 = __ev_get_u16 (a, 2);
+  s16 = __ev_get_s16 (a, 2);
+  ui = __ev_get_ufix32_u32 (a, 1);
+  i = __ev_get_sfix32_s32 (a, 0);
+  fl = __ev_get_ufix32_fs (a, 1);
+  fl = __ev_get_sfix32_fs (a, 0);
+
+  /* Predicates.  */
+  i = __ev_any_gts (a, b);
+  i = __ev_all_gts (a, b);
+  i = __ev_upper_gts (a, b);
+  i = __ev_lower_gts (a, b);
+  a = __ev_select_gts (a, b, c, c);
+
+  i = __ev_any_gtu (a, b);
+  i = __ev_all_gtu (a, b);
+  i = __ev_upper_gtu (a, b);
+  i = __ev_lower_gtu (a, b);
+  a = __ev_select_gtu (a, b, c, c);
+
+  i = __ev_any_lts (a, b);
+  i = __ev_all_lts (a, b);
+  i = __ev_upper_lts (a, b);
+  i = __ev_lower_lts (a, b);
+  a = __ev_select_lts (a, b, c, c);
+
+  i = __ev_any_ltu (a, b);
+  i = __ev_all_ltu (a, b);
+  i = __ev_upper_ltu (a, b);
+  i = __ev_lower_ltu (a, b);
+  a = __ev_select_ltu (a, b, c, c);
+
+  i = __ev_any_eq (a, b);
+  i = __ev_all_eq (a, b);
+  i = __ev_upper_eq (a, b);
+  i = __ev_lower_eq (a, b);
+  a = __ev_select_eq (a, b, c, c);
+
+  i = __ev_any_fs_gt (a, b);
+  i = __ev_all_fs_gt (a, b);
+  i = __ev_upper_fs_gt (a, b);
+  i = __ev_lower_fs_gt (a, b);
+  a = __ev_select_fs_gt (a, b, c, c);
+
+  i = __ev_any_fs_lt (a, b);
+  i = __ev_all_fs_lt (a, b);
+  i = __ev_upper_fs_lt (a, b);
+  i = __ev_lower_fs_lt (a, b);
+  a = __ev_select_fs_lt (a, b, c, b);
+
+  i = __ev_any_fs_eq (a, b);
+  i = __ev_all_fs_eq (a, b);
+  i = __ev_upper_fs_eq (a, b);
+  i = __ev_lower_fs_eq (a, b);
+  a = __ev_select_fs_eq (a, b, c, c);
+
+  i = __ev_any_fs_tst_gt (a, b);
+  i = __ev_all_fs_tst_gt (a, b);
+  i = __ev_upper_fs_tst_gt (a, b);
+  i = __ev_lower_fs_tst_gt (a, b);
+  a = __ev_select_fs_tst_gt (a, b, c, c);
+
+  i = __ev_any_fs_tst_lt (a, b);
+  i = __ev_all_fs_tst_lt (a, b);
+  i = __ev_upper_fs_tst_lt (a, b);
+  i = __ev_lower_fs_tst_lt (a, b);
+  a = __ev_select_fs_tst_lt (a, b, c, c);
+
+  i = __ev_any_fs_tst_eq (a, b);
+  i = __ev_all_fs_tst_eq (a, b);
+  i = __ev_upper_fs_tst_eq (a, b);
+  i = __ev_lower_fs_tst_eq (a, b);
+  a = __ev_select_fs_tst_eq (a, b, c, c);
+}
+
+int
+main (void)
+{
+  /* Generic binary operations.  */
+  c = __builtin_spe_evaddw (a, b);
+  c = __builtin_spe_evand (a, b);
+  c = __builtin_spe_evandc (a, b);
+  c = __builtin_spe_evdivws (a, b);
+  c = __builtin_spe_evdivwu (a, b);
+  c = __builtin_spe_eveqv (a, b);
+  h = __builtin_spe_evfsadd (f, g);
+  h = __builtin_spe_evfsdiv (f, g);
+  h = __builtin_spe_evfsmul (f, g);
+  h = __builtin_spe_evfssub (f, g);
+  c = __builtin_spe_evlddx (ap, j);
+  c = __builtin_spe_evldhx (ap, j);
+  c = __builtin_spe_evldwx (ap, j);
+  c = __builtin_spe_evlhhesplatx (usp, j);
+  c = __builtin_spe_evlhhossplatx (usp, j);
+  c = __builtin_spe_evlhhousplatx (usp, j);
+  c = __builtin_spe_evlwhex (uip, j);
+  c = __builtin_spe_evlwhosx (uip, j);
+  c = __builtin_spe_evlwhoux (uip, j);
+  c = __builtin_spe_evlwhsplatx (uip, j);
+  c = __builtin_spe_evlwwsplatx (uip, j);
+  c = __builtin_spe_evmergehi (a, b);
+  c = __builtin_spe_evmergehilo (a, b);
+  c = __builtin_spe_evmergelo (a, b);
+  c = __builtin_spe_evmergelohi (a, b);
+  c = __builtin_spe_evmhegsmfaa (a, b);
+  c = __builtin_spe_evmhegsmfan (a, b);
+  c = __builtin_spe_evmhegsmiaa (a, b);
+  c = __builtin_spe_evmhegsmian (a, b);
+  c = __builtin_spe_evmhegumiaa (a, b);
+  c = __builtin_spe_evmhegumian (a, b);
+  c = __builtin_spe_evmhesmf (a, b);
+  c = __builtin_spe_evmhesmfa (a, b);
+  c = __builtin_spe_evmhesmfaaw (a, b);
+  c = __builtin_spe_evmhesmfanw (a, b);
+  c = __builtin_spe_evmhesmi (a, b);
+  c = __builtin_spe_evmhesmia (a, b);
+  c = __builtin_spe_evmhesmiaaw (a, b);
+  c = __builtin_spe_evmhesmianw (a, b);
+  c = __builtin_spe_evmhessf (a, b);
+  c = __builtin_spe_evmhessfa (a, b);
+  c = __builtin_spe_evmhessfaaw (a, b);
+  c = __builtin_spe_evmhessfanw (a, b);
+  c = __builtin_spe_evmhessiaaw (a, b);
+  c = __builtin_spe_evmhessianw (a, b);
+  c = __builtin_spe_evmheumi (a, b);
+  c = __builtin_spe_evmheumia (a, b);
+  c = __builtin_spe_evmheumiaaw (a, b);
+  c = __builtin_spe_evmheumianw (a, b);
+  c = __builtin_spe_evmheusiaaw (a, b);
+  c = __builtin_spe_evmheusianw (a, b);
+  c = __builtin_spe_evmhogsmfaa (a, b);
+  c = __builtin_spe_evmhogsmfan (a, b);
+  c = __builtin_spe_evmhogsmiaa (a, b);
+  c = __builtin_spe_evmhogsmian (a, b);
+  c = __builtin_spe_evmhogumiaa (a, b);
+  c = __builtin_spe_evmhogumian (a, b);
+  c = __builtin_spe_evmhosmf (a, b);
+  c = __builtin_spe_evmhosmfa (a, b);
+  c = __builtin_spe_evmhosmfaaw (a, b);
+  c = __builtin_spe_evmhosmfanw (a, b);
+  c = __builtin_spe_evmhosmi (a, b);
+  c = __builtin_spe_evmhosmia (a, b);
+  c = __builtin_spe_evmhosmiaaw (a, b);
+  c = __builtin_spe_evmhosmianw (a, b);
+  c = __builtin_spe_evmhossf (a, b);
+  c = __builtin_spe_evmhossfa (a, b);
+  c = __builtin_spe_evmhossfaaw (a, b);
+  c = __builtin_spe_evmhossfanw (a, b);
+  c = __builtin_spe_evmhossiaaw (a, b);
+  c = __builtin_spe_evmhossianw (a, b);
+  c = __builtin_spe_evmhoumi (a, b);
+  c = __builtin_spe_evmhoumia (a, b);
+  c = __builtin_spe_evmhoumiaaw (a, b);
+  c = __builtin_spe_evmhoumianw (a, b);
+  c = __builtin_spe_evmhousiaaw (a, b);
+  c = __builtin_spe_evmhousianw (a, b);
+  c = __builtin_spe_evmwhsmf (a, b);
+  c = __builtin_spe_evmwhsmfa (a, b);
+  c = __builtin_spe_evmwhsmi (a, b);
+  c = __builtin_spe_evmwhsmia (a, b);
+  c = __builtin_spe_evmwhssf (a, b);
+  c = __builtin_spe_evmwhssfa (a, b);
+  c = __builtin_spe_evmwhumi (a, b);
+  c = __builtin_spe_evmwhumia (a, b);
+  c = __builtin_spe_evmwlsmiaaw (a, b);
+  c = __builtin_spe_evmwlsmianw (a, b);
+  c = __builtin_spe_evmwlssiaaw (a, b);
+  c = __builtin_spe_evmwlssianw (a, b);
+  c = __builtin_spe_evmwlumi (a, b);
+  c = __builtin_spe_evmwlumia (a, b);
+  c = __builtin_spe_evmwlumiaaw (a, b);
+  c = __builtin_spe_evmwlumianw (a, b);
+  c = __builtin_spe_evmwlusiaaw (a, b);
+  c = __builtin_spe_evmwlusianw (a, b);
+  c = __builtin_spe_evmwsmf (a, b);
+  c = __builtin_spe_evmwsmfa (a, b);
+  c = __builtin_spe_evmwsmfaa (a, b);
+  c = __builtin_spe_evmwsmfan (a, b);
+  c = __builtin_spe_evmwsmi (a, b);
+  c = __builtin_spe_evmwsmia (a, b);
+  c = __builtin_spe_evmwsmiaa (a, b);
+  c = __builtin_spe_evmwsmian (a, b);
+  c = __builtin_spe_evmwssf (a, b);
+  c = __builtin_spe_evmwssfa (a, b);
+  c = __builtin_spe_evmwssfaa (a, b);
+  c = __builtin_spe_evmwssfan (a, b);
+  c = __builtin_spe_evmwumi (a, b);
+  c = __builtin_spe_evmwumia (a, b);
+  c = __builtin_spe_evmwumiaa (a, b);
+  c = __builtin_spe_evmwumian (a, b);
+  c = __builtin_spe_evnand (a, b);
+  c = __builtin_spe_evnor (a, b);
+  c = __builtin_spe_evor (a, b);
+  c = __builtin_spe_evorc (a, b);
+  c = __builtin_spe_evrlw (a, b);
+  c = __builtin_spe_evslw (a, b);
+  c = __builtin_spe_evsrws (a, b);
+  c = __builtin_spe_evsrwu (a, b);
+  c = __builtin_spe_evsubfw (a, b);
+  c = __builtin_spe_evxor (a, b);
+
+  c = __builtin_spe_evmwhssfaa (a, b);
+  c = __builtin_spe_evmwhssmaa (a, b);
+  c = __builtin_spe_evmwhsmfaa (a, b);
+  c = __builtin_spe_evmwhsmiaa (a, b);
+  c = __builtin_spe_evmwhusiaa (a, b);
+  c = __builtin_spe_evmwhumiaa (a, b);
+  c = __builtin_spe_evmwhssfan (a, b);
+  c = __builtin_spe_evmwhssian (a, b);
+  c = __builtin_spe_evmwhsmfan (a, b);
+  c = __builtin_spe_evmwhsmian (a, b);
+  c = __builtin_spe_evmwhusian (a, b);
+  c = __builtin_spe_evmwhumian (a, b);
+  c = __builtin_spe_evmwhgssfaa (a, b);
+  c = __builtin_spe_evmwhgsmfaa (a, b);
+  c = __builtin_spe_evmwhgsmiaa (a, b);
+  c = __builtin_spe_evmwhgumiaa (a, b);
+  c = __builtin_spe_evmwhgssfan (a, b);
+  c = __builtin_spe_evmwhgsmfan (a, b);
+  c = __builtin_spe_evmwhgsmian (a, b);
+  c = __builtin_spe_evmwhgumian (a, b);
+  i = __builtin_spe_brinc (i, j);
+
+  /* Generic unary operations.  */
+  a = __builtin_spe_evabs (b);
+  a = __builtin_spe_evaddsmiaaw (b);
+  a = __builtin_spe_evaddssiaaw (b);
+  a = __builtin_spe_evaddumiaaw (b);
+  a = __builtin_spe_evaddusiaaw (b);
+  a = __builtin_spe_evcntlsw (b);
+  a = __builtin_spe_evcntlzw (b);
+  a = __builtin_spe_evextsb (b);
+  a = __builtin_spe_evextsh (b);
+  f = __builtin_spe_evfsabs (g);
+  f = __builtin_spe_evfscfsf (g);
+  a = __builtin_spe_evfscfsi (g);
+  f = __builtin_spe_evfscfuf (g);
+  f = __builtin_spe_evfscfui (a);
+  f = __builtin_spe_evfsctsf (g);
+  a = __builtin_spe_evfsctsi (g);
+  a = __builtin_spe_evfsctsiz (g);
+  f = __builtin_spe_evfsctuf (g);
+  a = __builtin_spe_evfsctui (g);
+  a = __builtin_spe_evfsctuiz (g);
+  f = __builtin_spe_evfsnabs (g);
+  f = __builtin_spe_evfsneg (g);
+  a = __builtin_spe_evmra (b);
+  a = __builtin_spe_evneg (b);
+  a = __builtin_spe_evrndw (b);
+  a = __builtin_spe_evsubfsmiaaw (b);
+  a = __builtin_spe_evsubfssiaaw (b);
+  a = __builtin_spe_evsubfumiaaw (b);
+  a = __builtin_spe_evsubfusiaaw (b);
+
+  /* Unary operations of the form: X = foo (5_bit_signed_immediate).  */
+  a = __builtin_spe_evsplatfi (5);
+  a = __builtin_spe_evsplati (5);
+
+  /* Binary operations of the form: X = foo(Y, 5_bit_immediate).  */
+  a = __builtin_spe_evaddiw (b, 13);
+  a = __builtin_spe_evldd (ap, 13);
+  a = __builtin_spe_evldh (ap, 13);
+  a = __builtin_spe_evldw (ap, 13);
+  a = __builtin_spe_evlhhesplat (usp, 13);
+  a = __builtin_spe_evlhhossplat (usp, 13);
+  a = __builtin_spe_evlhhousplat (usp, 13);
+  a = __builtin_spe_evlwhe (uip, 13);
+  a = __builtin_spe_evlwhos (uip, 13);
+  a = __builtin_spe_evlwhou (uip, 13);
+  a = __builtin_spe_evlwhsplat (uip, 13);
+  a = __builtin_spe_evlwwsplat (uip, 13);
+
+  a = __builtin_spe_evrlwi (b, 13);
+  a = __builtin_spe_evslwi (b, 13);
+  a = __builtin_spe_evsrwis (b, 13);
+  a = __builtin_spe_evsrwiu (b, 13);
+  a = __builtin_spe_evsubifw (b, 13);
+
+  /* Store indexed builtins.  */
+  __builtin_spe_evstddx (b, ap, j);
+  __builtin_spe_evstdhx (b, ap, j);
+  __builtin_spe_evstdwx (b, ap, j);
+  __builtin_spe_evstwhex (b, uip, j);
+  __builtin_spe_evstwhox (b, uip, j);
+  __builtin_spe_evstwwex (b, uip, j);
+  __builtin_spe_evstwwox (b, uip, j);
+
+  /* Store indexed immediate builtins.  */
+  __builtin_spe_evstdd (b, ap, 5);
+  __builtin_spe_evstdh (b, ap, 5);
+  __builtin_spe_evstdw (b, ap, 5);
+  __builtin_spe_evstwhe (b, uip, 5);
+  __builtin_spe_evstwho (b, uip, 5);
+  __builtin_spe_evstwwe (b, uip, 5);
+  __builtin_spe_evstwwo (b, uip, 5);
+
+  /* SPEFSCR builtins.  */
+  i = __builtin_spe_mfspefscr ();
+  __builtin_spe_mtspefscr (j);
+
+  test_api ();
+  
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c
new file mode 100644
index 000000000..a9d632bf9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c
@@ -0,0 +1,7 @@
+/* Test that SPE targets do not permit -m64.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do compile { target powerpc-*-*spe } } */
+/* { dg-options "-m64" } */
+
+/* { dg-error "-m64 not supported in this configuration" "SPE not 64-bit" { target *-*-* } 0 } */
+/* { dg-error "64-bit SPE not supported" "64-bit SPE" { target *-*-* } 0 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c
new file mode 100644
index 000000000..59bd39fcf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c
@@ -0,0 +1,35 @@
+/* { dg-do run { target powerpc*-*-linux* powerpc*-*-eabi* powerpc-*-rtems* } } */
+/* { dg-options {} } */
+
+/* Test stack pointer alignment against variable alloca.  */
+/* Inspired by PR libgcj/10610.  */
+/* Origin: Franz Sirl <Franz.Sirl-kernel@lauterbach.com>.  */
+
+extern void abort (void);
+extern void exit (int);
+
+register unsigned long sp __asm__ ("r1");
+
+void g (int * val __attribute__ ((unused)))
+{
+  if (sp & 0xf)
+    abort ();
+}
+
+void f (int val)
+{
+  int *val1 = __builtin_alloca (val);
+
+  g (val1);
+  return;
+}
+
+int main (void)
+{
+  int i;
+
+  for (i = 1; i < 32; i++)
+    f (i);
+  
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c
new file mode 100644
index 000000000..47a29ed3f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-mpowerpc-gfxopt" } */
+/* { dg-final { scan-assembler "stfiwx" } } */
+
+int foo (double x)
+{
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c
new file mode 100644
index 000000000..ac1dac9fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 --param case-values-threshold=2" } */
+/* { dg-final { scan-assembler "mtctr" } } */
+/* { dg-final { scan-assembler "bctr" } } */
+
+/* Force using a dispatch table even though by default we would generate
+   ifs.  */
+
+extern long call (long);
+
+long
+test_switch (long a, long b)
+{
+  long c;
+
+  switch (a)
+    {
+    case 0:  c = -b;	break;
+    case 1:  c = ~b;	break;
+    case 2:  c = b+1;	break;
+    default: c = b & 9;	break;
+    }
+
+  return call (c) + 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c
new file mode 100644
index 000000000..4f2efccfb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-switch-2.c
@@ -0,0 +1,32 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 --param case-values-threshold=20" } */
+/* { dg-final { scan-assembler-not "mtctr" } } */
+/* { dg-final { scan-assembler-not "bctr" } } */
+
+/* Force using if tests, instead of a dispatch table.  */
+
+extern long call (long);
+
+long
+test_switch (long a, long b)
+{
+  long c;
+
+  switch (a)
+    {
+    case 0:  c = -b;	break;
+    case 1:  c = ~b;	break;
+    case 2:  c = b+1;	break;
+    case 3:  c = b-2;	break;
+    case 4:  c = b*3;	break;
+    case 5:  c = b/4;	break;
+    case 6:  c = b<<5;	break;
+    case 7:  c = b>>6;	break;
+    case 8:  c = b|7;	break;
+    case 9:  c = b^8;	break;
+    default: c = b&9;	break;
+    }
+
+  return call (c) + 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c
new file mode 100644
index 000000000..b39fe4115
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=altivec" } */
+/* { dg-final { scan-assembler-times "fabs" 3 } } */
+/* { dg-final { scan-assembler-times "fnabs" 3 } } */
+/* { dg-final { scan-assembler-times "fsel" 3 } } */
+/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */
+
+double normal1 (double, double);
+double power5  (double, double) __attribute__((__target__("cpu=power5")));
+double power6  (double, double) __attribute__((__target__("cpu=power6")));
+double power6x (double, double) __attribute__((__target__("cpu=power6x")));
+double power7  (double, double) __attribute__((__target__("cpu=power7")));
+double power7n (double, double) __attribute__((__target__("cpu=power7,no-vsx")));
+double normal2 (double, double);
+
+/* fabs/fnabs/fsel */
+double normal1 (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fabs/fnabs/fsel */
+double power5  (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fcpsgn */
+double power6  (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fcpsgn */
+double power6x (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* xscpsgndp */
+double power7  (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fcpsgn */
+double power7n (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fabs/fnabs/fsel */
+double normal2 (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c
new file mode 100644
index 000000000..e8a2de363
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-2.c
@@ -0,0 +1,40 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=altivec" } */
+/* { dg-final { scan-assembler-times "fabs" 3 } } */
+/* { dg-final { scan-assembler-times "fnabs" 3 } } */
+/* { dg-final { scan-assembler-times "fsel" 3 } } */
+/* { dg-final { scan-assembler-times "fcpsgn\|xscpsgndp" 4 } } */
+
+/* fabs/fnabs/fsel */
+double normal1 (double a, double b) { return __builtin_copysign (a, b); }
+
+#pragma GCC push_options
+#pragma GCC target ("cpu=power5")
+/* fabs/fnabs/fsel */
+double power5 (double a, double b) { return __builtin_copysign (a, b); }
+#pragma GCC pop_options
+
+#pragma GCC target ("cpu=power6")
+/* fcpsgn */
+double power6 (double a, double b) { return __builtin_copysign (a, b); }
+#pragma GCC reset_options
+
+#pragma GCC target ("cpu=power6x")
+/* fcpsgn */
+double power6x (double a, double b) { return __builtin_copysign (a, b); }
+#pragma GCC reset_options
+
+#pragma GCC target ("cpu=power7")
+/* xscpsgndp */
+double power7 (double a, double b) { return __builtin_copysign (a, b); }
+#pragma GCC reset_options
+
+#pragma GCC target ("cpu=power7,no-vsx")
+/* fcpsgn */
+double power7n (double a, double b) { return __builtin_copysign (a, b); }
+#pragma GCC reset_options
+
+/* fabs/fnabs/fsel */
+double normal2 (double a, double b) { return __builtin_copysign (a, b); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c
new file mode 100644
index 000000000..286f31f63
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-3.c
@@ -0,0 +1,62 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ffast-math -mcpu=power5 -mabi=no-altivec" } */
+/* { dg-final { scan-assembler-times "fabs" 3 } } */
+/* { dg-final { scan-assembler-times "fnabs" 3 } } */
+/* { dg-final { scan-assembler-times "fsel" 3 } } */
+/* { dg-final { scan-assembler-times "fcpsgn" 4 } } */
+/* { dg-final { scan-assembler-not "xscpsgndp" } } */
+
+/* Like ppc-target-1.c, but do not enable the altivec abi on 32-bit, so the
+   power7 code should generate fcpsgn and not xscpsgndp.  */
+
+double normal1 (double, double);
+double power5  (double, double) __attribute__((__target__("cpu=power5")));
+double power6  (double, double) __attribute__((__target__("cpu=power6")));
+double power6x (double, double) __attribute__((__target__("cpu=power6x")));
+double power7  (double, double) __attribute__((__target__("cpu=power7")));
+double power7n (double, double) __attribute__((__target__("cpu=power7,no-vsx")));
+double normal2 (double, double);
+
+/* fabs/fnabs/fsel */
+double normal1 (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fabs/fnabs/fsel */
+double power5  (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fcpsgn */
+double power6  (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fcpsgn */
+double power6x (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* xscpsgndp */
+double power7  (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fcpsgn */
+double power7n (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
+
+/* fabs/fnabs/fsel */
+double normal2 (double a, double b)
+{
+  return __builtin_copysign (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
new file mode 100644
index 000000000..ac728334c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-target-4.c
@@ -0,0 +1,84 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ffast-math -mcpu=power5 -mno-altivec -mabi=altivec -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "vaddfp" 1 } } */
+/* { dg-final { scan-assembler-times "xvaddsp" 1 } } */
+/* { dg-final { scan-assembler-times "fadds" 1 } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+#ifdef __ALTIVEC__
+#error "__ALTIVEC__ should not be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+#pragma GCC target("vsx")
+#include <altivec.h>
+#pragma GCC reset_options
+
+#pragma GCC push_options
+#pragma GCC target("altivec,no-vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+void
+av_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+    a[i] = vec_add (b[i], c[i]);
+}
+
+#pragma GCC target("vsx")
+
+#ifndef __ALTIVEC__
+#error "__ALTIVEC__ should be defined."
+#endif
+
+#ifndef __VSX__
+#error "__VSX__ should be defined."
+#endif
+
+void
+vsx_add (vector float *a, vector float *b, vector float *c)
+{
+  unsigned long i;
+  unsigned long n = SIZE / 4;
+
+  for (i = 0; i < n; i++)
+    a[i] = vec_add (b[i], c[i]);
+}
+
+#pragma GCC pop_options
+#pragma GCC target("no-vsx,no-altivec")
+
+#ifdef __ALTIVEC__
+#error "__ALTIVEC__ should not be defined."
+#endif
+
+#ifdef __VSX__
+#error "__VSX__ should not be defined."
+#endif
+
+void
+norm_add (float *a, float *b, float *c)
+{
+  unsigned long i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c
new file mode 100644
index 000000000..7d4207ff7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O -maltivec -mno-vsx" } */
+/* { dg-final { scan-assembler "lvx" } } */
+
+#include <string.h>
+
+void foo(void)
+{
+  extern int x[8] __attribute__((aligned(128)));
+  int y[8] __attribute__((aligned(128)));
+  memcpy (y, x, sizeof (x));
+  bar (y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c
new file mode 100644
index 000000000..ad7aadea9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O -maltivec -mno-vsx" } */
+/* { dg-final { scan-assembler "stvx" } } */
+
+#include <string.h>
+
+void foo(void)
+{
+  int x[8] __attribute__((aligned(128)));
+  memset (x, 0, sizeof (x));
+  bar (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
new file mode 100644
index 000000000..14908dba6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
@@ -0,0 +1,253 @@
+/* { dg-do run { target { powerpc_fprs && { ilp32 && dfprt } } } } */
+/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */
+
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC ELF ABI for decimal float values.  */
+
+extern void abort (void);
+int failcnt = 0;
+
+/* Support compiling the test to report individual failures; default is
+   to abort as soon as a check fails.  */
+#ifdef DBG
+#include <stdio.h>
+#define FAILURE { printf ("failed at line %d\n", __LINE__); failcnt++; }
+#else
+#define FAILURE abort ();
+#endif
+
+typedef struct
+{
+  int pad;
+  _Decimal32 d;
+} d32parm_t;
+
+typedef struct
+{
+  unsigned int gprs[8];
+  double fprs[8];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+typedef struct sf
+{
+  struct sf *backchain;
+  int a1;
+  unsigned int slot[200];
+} stack_frame_t;
+
+/* Wrapper to save the GPRs and FPRs and then jump to the real function.  */
+#define WRAPPER(NAME)							\
+__asm__ ("\t.globl\t" #NAME "_asm\n\t"					\
+	 ".text\n\t"							\
+	 ".type " #NAME "_asm, @function\n"				\
+	 #NAME "_asm:\n\t"						\
+	 "lis 11,gparms@ha\n\t"						\
+	 "la 11,gparms@l(11)\n\t"					\
+	 "st 3,0(11)\n\t"						\
+	 "st 4,4(11)\n\t"						\
+	 "st 5,8(11)\n\t"						\
+	 "st 6,12(11)\n\t"						\
+	 "st 7,16(11)\n\t"						\
+	 "st 8,20(11)\n\t"						\
+	 "st 9,24(11)\n\t"						\
+	 "st 10,28(11)\n\t"						\
+	 "stfd 1,32(11)\n\t"						\
+	 "stfd 2,40(11)\n\t"						\
+	 "stfd 3,48(11)\n\t"						\
+	 "stfd 4,56(11)\n\t"						\
+	 "stfd 5,64(11)\n\t"						\
+	 "stfd 6,72(11)\n\t"						\
+	 "stfd 7,80(11)\n\t"						\
+	 "stfd 8,88(11)\n\t"						\
+	 "b " #NAME "\n\t"						\
+	 ".size " #NAME ",.-" #NAME "\n")
+
+/* Fill up floating point registers with double arguments, forcing
+   decimal float arguments into the parameter save area.  */
+extern void func0_asm (double, double, double, double, double,
+		       double, double, double, _Decimal64, _Decimal128);
+
+WRAPPER(func0);
+
+void __attribute__ ((noinline))
+func0 (double a1, double a2, double a3, double a4, double a5,
+       double a6, double a7, double a8, _Decimal64 a9, _Decimal128 a10)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != gparms.fprs[0]) FAILURE
+  if (a2 != gparms.fprs[1]) FAILURE
+  if (a3 != gparms.fprs[2]) FAILURE
+  if (a4 != gparms.fprs[3]) FAILURE
+  if (a5 != gparms.fprs[4]) FAILURE
+  if (a6 != gparms.fprs[5]) FAILURE
+  if (a7 != gparms.fprs[6]) FAILURE
+  if (a8 != gparms.fprs[7]) FAILURE
+  if (a9 != *(_Decimal64 *)&sp->slot[0]) FAILURE
+  if (a10 != *(_Decimal128 *)&sp->slot[2]) FAILURE
+}
+
+/* Alternate 64-bit and 128-bit decimal float arguments, checking that
+   _Decimal128 is always passed in even/odd register pairs.  */
+extern void func1_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
+		       _Decimal64, _Decimal128, _Decimal64, _Decimal128);
+
+WRAPPER(func1);
+
+void __attribute__ ((noinline))
+func1 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
+       _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE	/* f1 */
+  if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE	/* f2 & f3 */
+  if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE	/* f4 */
+  if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE	/* f6 & f7 */
+  if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE	/* f8 */
+  if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE
+  if (a7 != *(_Decimal64 *)&sp->slot[4]) FAILURE
+  if (a8 != *(_Decimal128 *)&sp->slot[6]) FAILURE
+}
+
+extern void func2_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64,
+		       _Decimal128, _Decimal64, _Decimal128, _Decimal64);
+
+WRAPPER(func2);
+
+void __attribute__ ((noinline))
+func2 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4,
+       _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE	/* f2 & f3 */
+  if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE	/* f4 */
+  if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE	/* f6 & f7 */
+  if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE	/* f8 */
+  if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE
+  if (a6 != *(_Decimal64 *)&sp->slot[4]) FAILURE
+  if (a7 != *(_Decimal128 *)&sp->slot[6]) FAILURE
+  if (a8 != *(_Decimal64 *)&sp->slot[10]) FAILURE
+}
+
+extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
+		       _Decimal64);
+
+WRAPPER(func3);
+
+void __attribute__ ((noinline))
+func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
+       _Decimal64 a5)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE	/* f1 */
+  if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE	/* f2 & f3 */
+  if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE	/* f4 */
+  if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE	/* f6 & f7 */
+  if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE
+}
+
+extern void func4_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32,
+		       _Decimal32, _Decimal32, _Decimal32, _Decimal32,
+		       _Decimal32, _Decimal32, _Decimal32, _Decimal32,
+		       _Decimal32, _Decimal32, _Decimal32, _Decimal32);
+
+WRAPPER(func4);
+
+void __attribute__ ((noinline))
+func4 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4,
+       _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8,
+       _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12,
+       _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  /* _Decimal32 is passed in the lower half of an FPR, or in parameter slot.  */
+  if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE		/* f1  */
+  if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE		/* f2  */
+  if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE		/* f3  */
+  if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE		/* f4  */
+  if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE		/* f5  */
+  if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE		/* f6  */
+  if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE		/* f7  */
+  if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE		/* f8  */
+  if (a9 != *(_Decimal32 *)&sp->slot[0]) FAILURE
+  if (a10 != *(_Decimal32 *)&sp->slot[1]) FAILURE
+  if (a11 != *(_Decimal32 *)&sp->slot[2]) FAILURE
+  if (a12 != *(_Decimal32 *)&sp->slot[3]) FAILURE
+  if (a13 != *(_Decimal32 *)&sp->slot[4]) FAILURE
+  if (a14 != *(_Decimal32 *)&sp->slot[5]) FAILURE
+  if (a15 != *(_Decimal32 *)&sp->slot[6]) FAILURE
+  if (a16 != *(_Decimal32 *)&sp->slot[7]) FAILURE
+}
+
+extern void func5_asm (_Decimal32, _Decimal64, _Decimal128,
+		       _Decimal32, _Decimal64, _Decimal128,
+		       _Decimal32, _Decimal64, _Decimal128,
+		       _Decimal32, _Decimal64, _Decimal128);
+
+WRAPPER(func5);
+
+void __attribute__ ((noinline))
+func5 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3,
+       _Decimal32 a4, _Decimal64 a5, _Decimal128 a6,
+       _Decimal32 a7, _Decimal64 a8, _Decimal128 a9,
+       _Decimal32 a10, _Decimal64 a11, _Decimal128 a12)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE		/* f1      */
+  if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE		/* f2      */
+  if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE		/* f4 & f5 */
+  if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE		/* f6      */
+  if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE		/* f7      */
+
+  if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE
+  if (a7 != *(_Decimal32 *)&sp->slot[4]) FAILURE
+  if (a8 != *(_Decimal64 *)&sp->slot[6]) FAILURE
+  if (a9 != *(_Decimal128 *)&sp->slot[8]) FAILURE
+  if (a10 != *(_Decimal32 *)&sp->slot[12]) FAILURE
+  if (a11 != *(_Decimal64 *)&sp->slot[14]) FAILURE
+  if (a12 != *(_Decimal128 *)&sp->slot[16]) FAILURE
+}
+
+int
+main ()
+{
+  func0_asm (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl);
+  func1_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl);
+  func2_asm (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd);
+  func3_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dl);
+  func4_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
+	     508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
+	     515.2df, 516.2df);
+  func5_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
+	     607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
+
+  if (failcnt != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c
new file mode 100644
index 000000000..9dc730e0d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c
@@ -0,0 +1,366 @@
+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { *-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2" } */
+#include <stdarg.h>
+#include <signal.h>
+#include <stdio.h>
+
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC64 ABI.  
+   Parameter passing of integral and floating point is tested.  */
+
+extern void abort (void);
+
+typedef struct
+{
+  unsigned long gprs[8];
+  double fprs[13];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+
+/* Testcase could break on future gcc's, if parameter regs
+   are changed before this asm.  */
+
+#ifndef __MACH__
+#define save_parms(lparms)				\
+    asm volatile ("ld 11,gparms@got(2)\n\t"                \
+                  "std 3,0(11)\n\t"		        \
+	          "std 4,8(11)\n\t"			\
+	          "std 5,16(11)\n\t"			\
+	          "std 6,24(11)\n\t"			\
+	          "std 7,32(11)\n\t"			\
+	          "std 8,40(11)\n\t"			\
+	          "std 9,48(11)\n\t"			\
+	          "std 10,56(11)\n\t"                 \
+                  "stfd 1,64(11)\n\t"		        \
+	          "stfd 2,72(11)\n\t"			\
+	          "stfd 3,80(11)\n\t"			\
+	          "stfd 4,88(11)\n\t"			\
+	          "stfd 5,96(11)\n\t"			\
+	          "stfd 6,104(11)\n\t"			\
+	          "stfd 7,112(11)\n\t"			\
+	          "stfd 8,120(11)\n\t"			\
+	          "stfd 9,128(11)\n\t"			\
+	          "stfd 10,136(11)\n\t"			\
+	          "stfd 11,144(11)\n\t"			\
+	          "stfd 12,152(11)\n\t"                 \
+	          "stfd 13,160(11)\n\t":::"11", "memory");  \
+                  lparms = gparms;
+#else
+#define save_parms(lparms)				\
+    asm volatile ("ld r11,gparms@got(r2)\n\t"           \
+                  "std r3,0(r11)\n\t"		        \
+	          "std r4,8(r11)\n\t"			\
+	          "std r5,16(r11)\n\t"			\
+	          "std r6,24(r11)\n\t"			\
+	          "std r7,32(r11)\n\t"			\
+	          "std r8,40(r11)\n\t"			\
+	          "std r9,48(r11)\n\t"			\
+	          "std r10,56(r11)\n\t"                 \
+                  "stfd f1,64(r11)\n\t"		        \
+	          "stfd f2,72(r11)\n\t"			\
+	          "stfd f3,80(r11)\n\t"			\
+	          "stfd f4,88(r11)\n\t"			\
+	          "stfd f5,96(r11)\n\t"			\
+	          "stfd f6,104(r11)\n\t"		\
+	          "stfd f7,112(r11)\n\t"		\
+	          "stfd f8,120(r11)\n\t"		\
+	          "stfd f9,128(r11)\n\t"		\
+	          "stfd f10,136(r11)\n\t"		\
+	          "stfd f11,144(r11)\n\t"		\
+	          "stfd f12,152(r11)\n\t"               \
+	          "stfd f13,160(r11)\n\t":::"r11", "memory");  \
+                  lparms = gparms;
+#endif
+
+/* Stackframe structure relevant for parameter passing.  */
+typedef union
+{
+  double d;
+  unsigned long l;
+  unsigned int i[2];
+} parm_t;
+
+typedef struct sf
+{
+  struct sf *backchain;
+  long a1;
+  long a2;
+  long a3;
+#if _CALL_ELF != 2
+  long a4;
+  long a5;
+#endif
+  parm_t slot[100];
+} stack_frame_t;
+
+
+/* Paramter passing.
+   s : gpr 3
+   l : gpr 4
+   d : fpr 1
+*/
+void __attribute__ ((noinline)) fcld (char *s, long l, double d)
+{
+  reg_parms_t lparms;
+  save_parms (lparms);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  if (l != lparms.gprs[1])
+    abort ();
+
+  if (d != lparms.fprs[0])
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   l : gpr 4
+   d : fpr 2
+   i : gpr 5
+*/
+void __attribute__ ((noinline))
+fcldi (char *s, long l, double d, signed int i)
+{
+  reg_parms_t lparms;
+  save_parms (lparms);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  if (l != lparms.gprs[1])
+    abort ();
+
+  if (d != lparms.fprs[0])
+    abort ();
+
+  if ((signed long) i != lparms.gprs[3])
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   l : gpr 4
+   d : fpr 2
+   i : gpr 5
+*/
+void __attribute__ ((noinline))
+fcldu (char *s, long l, float d, unsigned int i)
+{
+  reg_parms_t lparms;
+  save_parms (lparms);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  if (l != lparms.gprs[1])
+    abort ();
+
+  if ((double) d != lparms.fprs[0])
+    abort ();
+
+  if ((unsigned long) i != lparms.gprs[3])
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   l : slot 1
+   d : slot 2
+*/
+
+void __attribute__ ((noinline)) fceld (char *s, ...)
+{
+  stack_frame_t *sp;
+  reg_parms_t lparms;
+  va_list arg;
+  double d;
+  long l;
+  save_parms (lparms);
+
+  va_start (arg, s);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  l = va_arg (arg, long);
+  d = va_arg (arg, double);
+
+  /* Go back one frame.  */
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (sp->slot[1].l != l)
+    abort ();
+
+  if (sp->slot[2].d != d)
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   i : gpr 4
+   j : gpr 5
+   d : slot 3
+   l : slot 4
+*/
+void __attribute__ ((noinline)) fciiedl (char *s, int i, int j, ...)
+{
+  stack_frame_t *sp;
+  reg_parms_t lparms;
+  va_list arg;
+  double d;
+  long l;
+  save_parms (lparms);
+
+  va_start (arg, j);
+
+  if (s != (char *) lparms.gprs[0])
+    abort ();
+
+  if ((long) i != lparms.gprs[1])
+    abort ();
+
+  if ((long) j != lparms.gprs[2])
+    abort ();
+
+  d = va_arg (arg, double);
+  l = va_arg (arg, long);
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (sp->slot[3].d != d)
+    abort ();
+
+  if (sp->slot[4].l != l)
+    abort ();
+}
+
+/* 
+Parameter     Register     Offset in parameter save area
+c             r3           0-7    (not stored in parameter save area)
+ff            f1           8-15   (not stored)
+d             r5           16-23  (not stored)
+ld            f2           24-31  (not stored)
+f             r7           32-39  (not stored)
+s             r8,r9        40-55  (not stored)
+gg            f3           56-63  (not stored)
+t             (none)       64-79  (stored in parameter save area)
+e             (none)       80-87  (stored)
+hh            f4           88-95  (stored)  
+
+*/
+
+typedef struct
+{
+  int a;
+  double dd;
+} sparm;
+
+typedef union
+{
+  int i[2];
+  long l;
+  double d;
+} double_t;
+
+/* Example from ABI documentation with slight changes.
+   Paramter passing. 
+   c  : gpr 3
+   ff : fpr 1
+   d  : gpr 5
+   ld : fpr 2
+   f  : gpr 7
+   s  : gpr 8 - 9
+   gg : fpr 3
+   t  : save area offset 64 - 79 
+   e  : save area offset 80 - 88
+   hh : fpr 4   
+*/
+
+void __attribute__ ((noinline))
+fididisdsid (int c, double ff, int d, double ld, int f,
+	     sparm s, double gg, sparm t, int e, double hh)
+{
+  stack_frame_t *sp;
+  reg_parms_t lparms;
+  double_t dx, dy;
+
+  save_parms (lparms);
+
+  /* Parm 0: int.  */
+  if ((long) c != lparms.gprs[0])
+    abort ();
+
+  /* Parm 1: double.  */
+  if (ff != lparms.fprs[0])
+    abort ();
+
+  /* Parm 2: int.  */
+  if ((long) d != lparms.gprs[2])
+    abort ();
+
+  /* Parm 3: double.  */
+  if (ld != lparms.fprs[1])
+    abort ();
+
+  /* Parm 4: int.  */
+  if ((long) f != lparms.gprs[4])
+    abort ();
+
+  /* Parm 5: struct sparm.  */
+  dx.l = lparms.gprs[5];
+  dy.l = lparms.gprs[6];
+
+  if (s.a != dx.i[0])
+    abort ();
+  if (s.dd != dy.d)
+    abort ();
+
+  /* Parm 6: double.  */
+  if (gg != lparms.fprs[2])
+    abort ();
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  /* Parm 7: struct sparm.  */
+  dx.l = sp->slot[8].l;
+  dy.l = sp->slot[9].l;
+  if (t.a != dx.i[0])
+    abort ();
+  if (t.dd != dy.d)
+    abort ();
+
+  /* Parm 8: int.  */
+  if (e != sp->slot[10].l)
+    abort ();
+
+  /* Parm 9: double.  */
+
+  if (hh != lparms.fprs[3])
+    abort ();
+}
+
+int
+main ()
+{
+  char *s = "ii";
+
+  fcld (s, 1, 1.0);
+  fcldi (s, 1, 1.0, -2);
+  fcldu (s, 1, 1.0, 2);
+  fceld (s, 1, 1.0);
+  fciiedl (s, 1, 2, 1.0, 3);
+  fididisdsid (1, 1.0, 2, 2.0, -1, (sparm)
+	       {
+	       3, 3.0}, 4.0, (sparm)
+	       {
+	       5, 5.0}, 6, 7.0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c
new file mode 100644
index 000000000..e4825973b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c
@@ -0,0 +1,411 @@
+/* { dg-do run { target { { powerpc*-*-linux* && lp64 } && powerpc_altivec_ok } } } */
+/* { dg-options "-O2 -fprofile -mprofile-kernel -maltivec -mabi=altivec" } */
+#include <stdarg.h>
+#include <signal.h>
+#include <altivec.h>
+#include <stdlib.h>
+
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC64 ABI.  */
+
+void __attribute__((no_instrument_function))
+sig_ill_handler (int sig)
+{
+    exit(0);
+}
+
+extern void abort (void);
+
+typedef struct
+{
+  unsigned long gprs[8];
+  double fprs[13];
+  long pad;
+  vector int vrs[12];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+/* _mcount call is done on Linux ppc64 early in the prologue.
+   my_mcount will provide a entry point _mcount,
+   which will save all register to gparms. 
+   Note that _mcount need to restore lr to original value,
+   therefor use ctr to return.  
+*/
+
+void __attribute__((no_instrument_function))
+my_mcount() 
+{
+  asm volatile (".type	_mcount,@function\n\t"
+		".globl	_mcount\n\t"
+		"_mcount:\n\t"
+                "mflr 0\n\t"
+                "mtctr 0\n\t"
+                "ld 0,16(1)\n\t"
+		"mtlr 0\n\t"
+		"ld 11,gparms@got(2)\n\t" 
+		"std 3,0(11)\n\t"		
+		"std 4,8(11)\n\t"
+		"std 5,16(11)\n\t"	
+		"std 6,24(11)\n\t"	
+		"std 7,32(11)\n\t"	
+		"std 8,40(11)\n\t"	
+		"std 9,48(11)\n\t"	
+		"std 10,56(11)\n\t"   
+		"stfd 1,64(11)\n\t"	
+		"stfd 2,72(11)\n\t"	
+		"stfd 3,80(11)\n\t"	
+		"stfd 4,88(11)\n\t"	
+		"stfd 5,96(11)\n\t"	
+		"stfd 6,104(11)\n\t"	
+		"stfd 7,112(11)\n\t"	
+		"stfd 8,120(11)\n\t"	
+		"stfd 9,128(11)\n\t"	
+		"stfd 10,136(11)\n\t"	
+		"stfd 11,144(11)\n\t"	
+		"stfd 12,152(11)\n\t" 
+		"stfd 13,160(11)\n\t" 
+		"li 3,176\n\t"        
+		"stvx 2,3,11\n\t"	
+		"addi 3,3,16\n\t" 
+		"stvx 3,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 4,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 5,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 6,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 7,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 8,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 9,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 10,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 11,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 12,3,11\n\t"	
+		"addi 3,3,16\n\t"     
+		"stvx 13,3,11\n\t"	
+		"ld 3,0(11)\n\t"
+		"bctr");
+}
+
+/* Stackframe structure relevant for parameter passing.  */
+typedef union
+{
+  double d;
+  unsigned long l;
+  unsigned int i[2];
+} parm_t;
+
+typedef struct sf
+{
+  struct sf *backchain;
+  long a1;
+  long a2;
+  long a3;
+#if _CALL_ELF != 2
+  long a4;
+  long a5;
+#endif
+  parm_t slot[100];
+} stack_frame_t;
+
+typedef union
+{
+  unsigned int i[4];
+  unsigned long l[2];
+  vector int v;
+} vector_int_t;
+
+#ifdef __LITTLE_ENDIAN__
+#define MAKE_SLOT(x, y) ((long)x | ((long)y << 32))
+#else
+#define MAKE_SLOT(x, y) ((long)y | ((long)x << 32))
+#endif
+
+/* Paramter passing.
+   s : gpr 3
+   v : vpr 2
+   i : gpr 7
+*/
+void __attribute__ ((noinline))
+fcvi (char *s, vector int v, int i)
+{
+  reg_parms_t lparms = gparms;
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if (!vec_all_eq (v, lparms.vrs[0]))
+    abort ();
+
+  if ((long) i != lparms.gprs[4])
+    abort();
+}
+/* Paramter passing.
+   s : gpr 3
+   v : vpr 2
+   w : vpr 3
+*/
+
+void __attribute__ ((noinline))
+fcvv (char *s, vector int v, vector int w)
+{
+  vector int a, c = {6, 8, 10, 12};
+  reg_parms_t lparms = gparms;
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if (!vec_all_eq (v, lparms.vrs[0]))
+    abort ();
+
+  if (!vec_all_eq (w, lparms.vrs[1]))
+    abort ();
+
+  a = vec_add (v,w);
+
+  if (!vec_all_eq (a, c))
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   i : gpr 4
+   v : vpr 2
+   w : vpr 3
+*/
+void __attribute__ ((noinline))
+fcivv (char *s, int i, vector int v, vector int w)
+{
+  vector int a, c = {6, 8, 10, 12};
+  reg_parms_t lparms = gparms;
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if ((long) i != lparms.gprs[1])
+    abort();
+
+  if (!vec_all_eq (v, lparms.vrs[0]))
+    abort ();
+
+  if (!vec_all_eq (w, lparms.vrs[1]))
+    abort ();
+
+  a = vec_add (v,w);
+  
+  if (!vec_all_eq (a, c))
+    abort ();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   v : slot 2-3
+   w : slot 4-5
+*/
+
+void __attribute__ ((noinline))
+fcevv (char *s, ...)
+{
+  vector int a, c = {6, 8, 10, 12};
+  vector int v,w;
+  stack_frame_t *sp;
+  reg_parms_t lparms = gparms;
+  va_list arg;
+
+  va_start (arg, s);
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  v = va_arg(arg, vector int);
+  w = va_arg(arg, vector int);
+  a = vec_add (v,w);
+  
+  if (!vec_all_eq (a, c))
+    abort ();
+
+  /* Go back one frame.  */
+  sp = __builtin_frame_address(0);
+  sp = sp->backchain;
+  
+  if (sp->slot[2].l != MAKE_SLOT (1, 2)
+      || sp->slot[4].l !=  MAKE_SLOT (5, 6))
+    abort();
+}
+
+/* Paramter passing.
+   s : gpr 3
+   i : gpr 4
+   j : gpr 5
+   v : slot 4-5
+   w : slot 6-7
+*/
+void __attribute__ ((noinline))
+fciievv (char *s, int i, int j, ...)
+{
+  vector int a, c = {6, 8, 10, 12};
+  vector int v,w;
+  stack_frame_t *sp;
+  reg_parms_t lparms = gparms;
+  va_list arg;
+
+  va_start (arg, j);
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if ((long) i != lparms.gprs[1])
+    abort();
+
+  if ((long) j != lparms.gprs[2])
+    abort();
+  
+  v = va_arg(arg, vector int);
+  w = va_arg(arg, vector int);
+  a = vec_add (v,w);
+  
+  if (!vec_all_eq (a, c))
+    abort ();
+
+  sp = __builtin_frame_address(0);
+  sp = sp->backchain;
+  
+  if (sp->slot[4].l != MAKE_SLOT (1, 2)
+      || sp->slot[6].l !=  MAKE_SLOT (5, 6))
+    abort();
+}
+
+void __attribute__ ((noinline))
+fcvevv (char *s, vector int x, ...)
+{
+  vector int a, c = {7, 10, 13, 16};
+  vector int v,w;
+  stack_frame_t *sp;
+  reg_parms_t lparms = gparms;
+  va_list arg;
+
+  va_start (arg, x);
+  
+  v = va_arg(arg, vector int);
+  w = va_arg(arg, vector int);
+
+  a = vec_add (v,w);
+  a = vec_add (a, x);
+ 
+  if (!vec_all_eq (a, c))
+    abort ();
+
+  sp = __builtin_frame_address(0);
+  sp = sp->backchain;
+  
+  if (sp->slot[4].l != MAKE_SLOT (1, 2)
+      || sp->slot[6].l !=  MAKE_SLOT (5, 6))
+    abort();
+}
+
+int __attribute__((no_instrument_function, noinline))
+main1() 
+{   
+  char *s = "vv";
+  vector int v = {1, 2, 3, 4};
+  vector int w = {5, 6, 7, 8};
+ 
+  fcvi (s, v, 2);
+  fcvv (s, v, w);
+  fcivv (s, 1, v, w);
+  fcevv (s, v, w);
+  fciievv (s, 1, 2, v, w);
+  fcvevv (s, v, v, w);
+  return 0;
+}
+
+int __attribute__((no_instrument_function)) 
+main()
+{
+  /* Exit on systems without altivec.  */
+  signal (SIGILL, sig_ill_handler);
+  /* Altivec instruction, 'vor %v0,%v0,%v0'.  */
+  asm volatile (".long 0x10000484");
+  signal (SIGILL, SIG_DFL);
+
+  return main1 ();
+}
+
+/* Paramter passing.
+   Function called with no prototype.
+   s : gpr 3
+   v : vpr 2 gpr 5-6
+   w : vpr 3 gpr 7-8
+   x : vpr 4 gpr 9-10
+   y : vpr 5 slot 8-9
+*/
+void
+fnp_cvvvv (char *s, vector int v, vector int w,
+	   vector int x, vector int y)
+{
+  vector int a, c = {12, 16, 20, 24};
+  reg_parms_t lparms = gparms;
+  stack_frame_t *sp;
+  vector_int_t v0, v1, v2, v3;
+
+  if (s != (char *) lparms.gprs[0])
+    abort();
+
+  if (!vec_all_eq (v, lparms.vrs[0]))
+    abort ();
+
+  if (!vec_all_eq (w, lparms.vrs[1]))
+    abort ();
+
+  if (!vec_all_eq (x, lparms.vrs[2]))
+    abort ();
+
+  if (!vec_all_eq (y, lparms.vrs[3]))
+    abort ();
+
+  a = vec_add (v,w);
+  a = vec_add (a,x);  
+  a = vec_add (a,y);  
+  
+  if (!vec_all_eq (a, c))
+    abort ();
+  
+  v0.v = lparms.vrs[0];
+  v1.v = lparms.vrs[1];
+  v2.v = lparms.vrs[2];
+  v3.v = lparms.vrs[3];
+
+  if (v0.l[0] != lparms.gprs[2])
+    abort ();
+
+  if (v0.l[1] != lparms.gprs[3])
+    abort ();
+
+  if (v1.l[0] != lparms.gprs[4])
+    abort ();
+
+  if (v1.l[1] != lparms.gprs[5])
+    abort ();
+
+  if (v2.l[0] != lparms.gprs[6])
+    abort ();
+
+  if (v2.l[1] != lparms.gprs[7])
+    abort ();
+
+  sp = __builtin_frame_address(0);
+  sp = sp->backchain;
+  
+  if (sp->slot[8].l != v3.l[0])
+    abort ();
+
+  if (sp->slot[9].l != v3.l[1])
+    abort ();
+}  
+  
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c
new file mode 100644
index 000000000..8c78c9e2b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-options "-Wall" } */
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC64 ABI.  */
+
+typedef int __attribute__((vector_size(16))) v4si;
+typedef int __attribute__((vector_size(8))) v2si;
+
+v4si 
+f(v4si v)
+{ /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */
+    return v;
+}
+
+v2si 
+g(v2si v)
+{
+    return v;
+}
+
+int 
+main()
+{
+    v4si v = { 1, 2, 3, 4 };
+    v2si w = { 5, 6 };
+    v = f (v); /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */
+    w = g (w);
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c
new file mode 100644
index 000000000..4e91b1bba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c
@@ -0,0 +1,345 @@
+/* { dg-do run { target { powerpc64-*-* && { lp64 && dfprt } } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */
+
+/* Testcase to check for ABI compliance of parameter passing
+   for the PowerPC64 ELF ABI for decimal float values.  */
+
+extern void abort (void);
+int failcnt = 0;
+
+/* Support compiling the test to report individual failures; default is
+   to abort as soon as a check fails.  */
+#ifdef DBG
+#include <stdio.h>
+#define FAILURE { printf ("failed at line %d\n", __LINE__); failcnt++; }
+#else
+#define FAILURE abort ();
+#endif
+
+typedef struct
+{
+  int pad;
+  _Decimal32 d;
+} d32parm_t;
+
+typedef struct
+{
+  unsigned long gprs[8];
+  double fprs[13];
+} reg_parms_t;
+
+reg_parms_t gparms;
+
+
+/* Wrapper to save the GPRs and FPRs and then jump to the real function.  */
+#if _CALL_ELF != 2
+#define FUNC_START(NAME)						\
+	"\t.globl\t" NAME "\n\t"					\
+         ".section \".opd\",\"aw\"\n\t"					\
+         ".align 3\n"							\
+         NAME ":\n\t"							\
+         ".quad .L." NAME ",.TOC.@tocbase,0\n\t"			\
+         ".text\n\t"							\
+         ".type " NAME ", @function\n"					\
+         ".L." NAME ":\n\t"
+#else
+#define FUNC_START(NAME)						\
+	"\t.globl\t" NAME "\n\t"					\
+         ".text\n\t"							\
+         NAME ":\n"							\
+	"0:\taddis 2,12,(.TOC.-0b)@ha\n\t"				\
+	"addi 2,2,(.TOC.-0b)@l\n\t"					\
+	".localentry " NAME ",.-" NAME "\n\t"
+#endif
+#define WRAPPER(NAME)							\
+__asm__ (FUNC_START (#NAME "_asm")					\
+	 "ld 11,gparms@got(2)\n\t"					\
+	 "std 3,0(11)\n\t"						\
+	 "std 4,8(11)\n\t"						\
+	 "std 5,16(11)\n\t"						\
+	 "std 6,24(11)\n\t"						\
+	 "std 7,32(11)\n\t"						\
+	 "std 8,40(11)\n\t"						\
+	 "std 9,48(11)\n\t"						\
+	 "std 10,56(11)\n\t"						\
+	 "stfd 1,64(11)\n\t"						\
+	 "stfd 2,72(11)\n\t"						\
+	 "stfd 3,80(11)\n\t"						\
+	 "stfd 4,88(11)\n\t"						\
+	 "stfd 5,96(11)\n\t"						\
+	 "stfd 6,104(11)\n\t"						\
+	 "stfd 7,112(11)\n\t"						\
+	 "stfd 8,120(11)\n\t"						\
+	 "stfd 9,128(11)\n\t"						\
+	 "stfd 10,136(11)\n\t"						\
+	 "stfd 11,144(11)\n\t"						\
+	 "stfd 12,152(11)\n\t"						\
+	 "stfd 13,160(11)\n\t"						\
+	 "b " #NAME "\n\t"						\
+	 ".long 0\n\t"							\
+	 ".byte 0,0,0,0,0,0,0,0\n\t"					\
+	 ".size " #NAME ",.-" #NAME "\n")
+
+typedef struct sf
+{
+  struct sf *backchain;
+  long a1;
+  long a2;
+  long a3;
+#if _CALL_ELF != 2
+  long a4;
+  long a5;
+#endif
+  unsigned long slot[100];
+} stack_frame_t;
+
+extern void func0_asm (double, double, double, double, double, double,
+		       double, double, double, double, double, double,
+		       double, double, 
+		       _Decimal64, _Decimal128, _Decimal64);
+
+WRAPPER(func0);
+
+/* Fill up floating point registers with double arguments, forcing
+   decimal float arguments into the parameter save area.  */
+void __attribute__ ((noinline))
+func0 (double a1, double a2, double a3, double a4, double a5, double a6,
+       double a7, double a8, double a9, double a10, double a11, double a12,
+       double a13, double a14, 
+       _Decimal64 a15, _Decimal128 a16, _Decimal64 a17)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != gparms.fprs[0]) FAILURE
+  if (a2 != gparms.fprs[1]) FAILURE
+  if (a3 != gparms.fprs[2]) FAILURE
+  if (a4 != gparms.fprs[3]) FAILURE
+  if (a5 != gparms.fprs[4]) FAILURE
+  if (a6 != gparms.fprs[5]) FAILURE
+  if (a7 != gparms.fprs[6]) FAILURE
+  if (a8 != gparms.fprs[7]) FAILURE
+  if (a9 != gparms.fprs[8]) FAILURE
+  if (a10 != gparms.fprs[9]) FAILURE
+  if (a11 != gparms.fprs[10]) FAILURE
+  if (a12 != gparms.fprs[11]) FAILURE
+  if (a13 != gparms.fprs[12]) FAILURE
+  if (a14 != *(double *)&sp->slot[13]) FAILURE
+  if (a15 != *(_Decimal64 *)&sp->slot[14]) FAILURE
+  if (a16 != *(_Decimal128 *)&sp->slot[15]) FAILURE
+  if (a17 != *(_Decimal64 *)&sp->slot[17]) FAILURE
+}
+
+extern void func1_asm (double, double, double, double, double, double,
+		       double, double, double, double, double, double,
+		       double, _Decimal128 );
+
+WRAPPER(func1);
+
+void __attribute__ ((noinline))
+func1 (double a1, double a2, double a3, double a4, double a5, double a6,
+       double a7, double a8, double a9, double a10, double a11, double a12,
+       double a13, _Decimal128 a14)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != gparms.fprs[0]) FAILURE
+  if (a2 != gparms.fprs[1]) FAILURE
+  if (a3 != gparms.fprs[2]) FAILURE
+  if (a4 != gparms.fprs[3]) FAILURE
+  if (a5 != gparms.fprs[4]) FAILURE
+  if (a6 != gparms.fprs[5]) FAILURE
+  if (a7 != gparms.fprs[6]) FAILURE
+  if (a8 != gparms.fprs[7]) FAILURE
+  if (a9 != gparms.fprs[8]) FAILURE
+  if (a10 != gparms.fprs[9]) FAILURE
+  if (a11 != gparms.fprs[10]) FAILURE
+  if (a12 != gparms.fprs[11]) FAILURE
+  if (a13 != gparms.fprs[12]) FAILURE
+  if (a14 != *(_Decimal128 *)&sp->slot[13]) FAILURE
+}
+
+extern void func2_asm (double, double, double, double, double, double,
+		       double, double, double, double, double, double,
+		       _Decimal128);
+
+WRAPPER(func2);
+
+void __attribute__ ((noinline))
+func2 (double a1, double a2, double a3, double a4, double a5, double a6,
+       double a7, double a8, double a9, double a10, double a11, double a12,
+       _Decimal128 a13)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != gparms.fprs[0]) FAILURE
+  if (a2 != gparms.fprs[1]) FAILURE
+  if (a3 != gparms.fprs[2]) FAILURE
+  if (a4 != gparms.fprs[3]) FAILURE
+  if (a5 != gparms.fprs[4]) FAILURE
+  if (a6 != gparms.fprs[5]) FAILURE
+  if (a7 != gparms.fprs[6]) FAILURE
+  if (a8 != gparms.fprs[7]) FAILURE
+  if (a9 != gparms.fprs[8]) FAILURE
+  if (a10 != gparms.fprs[9]) FAILURE
+  if (a11 != gparms.fprs[10]) FAILURE
+  if (a12 != gparms.fprs[11]) FAILURE
+  if (a13 != *(_Decimal128 *)&sp->slot[12]) FAILURE
+}
+
+extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
+		       _Decimal64, _Decimal128, _Decimal64, _Decimal128,
+		       _Decimal64, _Decimal128);
+
+WRAPPER(func3);
+
+void __attribute__ ((noinline))
+func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
+       _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8,
+       _Decimal64 a9, _Decimal128 a10)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE	/* f1        */
+  if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE	/* f2 & f3   */
+  if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE	/* f4        */
+  if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE	/* f6 & f7   */
+  if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE	/* f8        */
+  if (a6 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE	/* f10 & f11 */
+  if (a7 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE	/* f12       */
+  if (a8 != *(_Decimal128 *)&sp->slot[10]) FAILURE
+  if (a9 != *(_Decimal64 *)&sp->slot[12]) FAILURE
+  if (a10 != *(_Decimal128 *)&sp->slot[13]) FAILURE
+}
+
+extern void func4_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64,
+		       _Decimal128, _Decimal64, _Decimal128, _Decimal64);
+
+WRAPPER(func4);
+
+void __attribute__ ((noinline))
+func4 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4,
+       _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE	/* f2 & f3   */
+  if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE	/* f4        */
+  if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE	/* f6 & f7   */
+  if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE	/* f8        */
+  if (a5 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE	/* f10 & f11 */
+  if (a6 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE	/* f12       */
+  if (a7 != *(_Decimal128 *)&sp->slot[9]) FAILURE
+  if (a8 != *(_Decimal64 *)&sp->slot[11]) FAILURE
+}
+
+extern void func5_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32,
+		       _Decimal32, _Decimal32, _Decimal32, _Decimal32,
+		       _Decimal32, _Decimal32, _Decimal32, _Decimal32,
+		       _Decimal32, _Decimal32, _Decimal32, _Decimal32);
+
+WRAPPER(func5);
+
+void __attribute__ ((noinline))
+func5 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4,
+       _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8,
+       _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12,
+       _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  /* _Decimal32 is passed in the lower half of an FPR or parameter slot.  */
+  if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE		/* f1  */
+  if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE		/* f2  */
+  if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE		/* f3  */
+  if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE		/* f4  */
+  if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE		/* f5  */
+  if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE		/* f6  */
+  if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE		/* f7  */
+  if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE		/* f8  */
+  if (a9 != ((d32parm_t *)&gparms.fprs[8])->d) FAILURE		/* f9  */
+  if (a10 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE		/* f10 */
+  if (a11 != ((d32parm_t *)&gparms.fprs[10])->d) FAILURE	/* f11 */
+  if (a12 != ((d32parm_t *)&gparms.fprs[11])->d) FAILURE	/* f12 */
+  if (a13 != ((d32parm_t *)&gparms.fprs[12])->d) FAILURE	/* f13 */
+  if (a14 != ((d32parm_t *)&sp->slot[13])->d) FAILURE
+  if (a15 != ((d32parm_t *)&sp->slot[14])->d) FAILURE
+  if (a16 != ((d32parm_t *)&sp->slot[15])->d) FAILURE
+}
+
+extern void func6_asm (_Decimal32, _Decimal64, _Decimal128,
+		       _Decimal32, _Decimal64, _Decimal128,
+		       _Decimal32, _Decimal64, _Decimal128,
+		       _Decimal32, _Decimal64, _Decimal128);
+
+WRAPPER(func6);
+
+void __attribute__ ((noinline))
+func6 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3,
+       _Decimal32 a4, _Decimal64 a5, _Decimal128 a6,
+       _Decimal32 a7, _Decimal64 a8, _Decimal128 a9,
+       _Decimal32 a10, _Decimal64 a11, _Decimal128 a12)
+{
+  stack_frame_t *sp;
+
+  sp = __builtin_frame_address (0);
+  sp = sp->backchain;
+
+  if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE		/* f1        */
+  if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE		/* f2        */
+  if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE		/* f4 & f5   */
+  if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE		/* f6        */
+  if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE		/* f7        */
+  if (a6 != *(_Decimal128 *)&gparms.fprs[7]) FAILURE		/* f8 & f9   */
+  if (a7 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE		/* f10       */
+  if (a8 != *(_Decimal64 *)&gparms.fprs[10]) FAILURE		/* f11       */
+  if (a9 != *(_Decimal128 *)&gparms.fprs[11]) FAILURE		/* f12 & f13 */
+  if (a10 != ((d32parm_t *)&sp->slot[12])->d) FAILURE
+  if (a11 != *(_Decimal64 *)&sp->slot[13]) FAILURE
+}
+
+int
+main (void)
+{
+  func0_asm (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5,
+	     14.5, 15.2dd, 16.2dl, 17.2dd);
+  func1_asm (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5,
+	     110.5, 111.5, 112.5, 113.5, 114.2dd);
+  func2_asm (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5,
+	     210.5, 211.5, 212.5, 213.2dd);
+  func3_asm (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd,
+	     308.2dl, 309.2dd, 310.2dl);
+  func4_asm (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl,
+	     408.2dd);
+#if 0
+  /* _Decimal32 doesn't yet follow the ABI; enable this when it does.  */
+  func5_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
+	     508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
+	     515.2df, 516.2df);
+  func6_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
+	     607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
+#endif
+
+  if (failcnt != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c
new file mode 100644
index 000000000..f9d4dda9c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c
@@ -0,0 +1,12 @@
+// { dg-do compile }
+/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */
+// { dg-options "-O2 -mpowerpc64" }
+// { dg-final { scan-assembler-not "stfd"  }  }
+
+// The register allocator should have allocated the temporary long long value in a floating point register.
+
+double
+d2ll2d (double d)
+{
+        return (double)(long long)d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c
new file mode 100644
index 000000000..21090af23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c
@@ -0,0 +1,22 @@
+/* { dg-do link } */
+/* { dg-options "-mminimal-toc" { target { powerpc*-*-* && lp64 } } } */
+
+char *strchr (const char *, int);
+
+int
+foo (int a)
+{
+  int b;
+
+  b = 0;
+  if ("/"[1] != '\0')
+    if (strchr ("/", a))
+      b = 1;
+  return b;
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c
new file mode 100644
index 000000000..8efaeaba3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/ppu-intrinsics.c
@@ -0,0 +1,43 @@
+/* { dg-do link { target { *-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-W -Wall -Wno-uninitialized -Wno-unused-but-set-variable -mcpu=cell" } */
+/* Test some PPU intrinsics from <ppu_intrinsics.h>.  */
+
+#include <ppu_intrinsics.h>
+
+int main ()
+{
+  double d, d1, d2;
+  float f, f1, f2;
+  unsigned long long ull, a, b;
+  long long ll;
+  int i;
+
+#ifdef __powerpc64__
+  ull = __rldcl (a, b, 3);
+  ull = __rldcr (a, b, 3);
+  ull = __rldic (a, 3, 4);
+  ull = __rldicl (a, 4, 5);
+  ull = __rldicr (a, 2, 3);
+  ull = __rldimi (a, b, 4, 6);
+#endif
+  ull = __rlwimi (a, b, 6, 9, 12);
+  ull = __rlwnm (a, b, 3, 5);
+  d = __fmul (d1, d2);
+  f = __fmuls (f1, f2);
+  f = __frsp (f);
+  d = __fcfid (ll);
+  d = __frsqrte (d1);
+  ll = __fctid (d);
+  ll = __fctidz (d);
+  i = __fctiw (d);
+  i = __fctiwz (d);
+
+  __protected_stream_count (1, 2);
+  __protected_stream_go ();
+  __protected_stream_set (1, 0x1000, 3);
+  __protected_stream_stop (3);
+  __protected_stream_stop_all ();
+  __protected_unlimited_stream_set (3, 0x1000, 1);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16155.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16155.c
new file mode 100644
index 000000000..fffe957dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16155.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -ansi" } */
+
+/* PR 16155
+ * Compilation of a simple altivec test program fails if the -ansi flag is
+ * given to gcc, when compiling with -maltivec.
+ */
+
+#include <altivec.h>
+
+void foo(void)
+{
+  vector unsigned short a, b;
+  a = vec_splat(b, 0);
+}
+
+/* { dg-bogus "parse error before \"typeof\"" "-maltivec -mansi" { target powerpc*-*-* } 0 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16286.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16286.c
new file mode 100644
index 000000000..790b6409f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16286.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* PR 16286
+   Compilation of a simple Altivec test program fails if vector, pixel
+   and/or bool are #undefined when compiling with -maltivec.  This may be
+   done for building C++ programs that use the STL <vector>.  */
+
+#include <altivec.h>
+#undef vector
+#undef pixel
+#undef bool
+
+void test(void)
+{
+        __vector unsigned int a, b;
+	__vector __pixel v0;
+	__vector __bool v1;
+
+        a = vec_and(a, b);
+	vec_step (b);
+}
+
+/* { dg-bogus "(syntax|parse) error before \"vector\"" "-maltivec" { target powerpc*-*-* } 0 } */
+/* { dg-bogus "(syntax|parse) error before \"pixel\"" "-maltivec" { target powerpc*-*-* } 0 } */
+/* { dg-bogus "(syntax|parse) error before \"bool\"" "-maltivec" { target powerpc*-*-* } 0 } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-1.c
new file mode 100644
index 000000000..45b8c75c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-1.c
@@ -0,0 +1,18 @@
+/* Test cse'ing of unsigned compares.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "cmpw" } } */
+/* { dg-final { scan-assembler-times "cmplw" 1 } } */
+
+unsigned int a, b;
+
+int
+foo (void)
+{
+  if (a == b) return 1;
+  if (a > b)  return 2;
+  if (a < b)  return 3;
+  if (a != b) return 4;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-2.c
new file mode 100644
index 000000000..95e97de55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-2.c
@@ -0,0 +1,18 @@
+/* Test cse'ing of unsigned compares.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* { dg-final { scan-assembler-not "cmpw" } } */
+/* { dg-final { scan-assembler-times "cmplw" 1 } } */
+
+unsigned int *a, *b;
+
+int
+foo (void)
+{
+  if (*a == *b) return 1;
+  if (*a > *b)  return 2;
+  if (*a < *b)  return 3;
+  if (*a != *b) return 4;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-3.c
new file mode 100644
index 000000000..740d61dcc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-3.c
@@ -0,0 +1,41 @@
+/* Test cse'ing of unsigned compares.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-jump-tables" } */
+
+/* { dg-final { scan-assembler-not "cmpwi" } } */
+/* { dg-final { scan-assembler-times "cmplwi" 5 } } */
+
+extern int case0 (void);
+extern int case1 (void);
+extern int case2 (void);
+extern int case3 (void);
+extern int case4 (void);
+
+enum CASE_VALUES
+{
+  CASE0 = 1,
+  CASE1,
+  CASE2,
+  CASE3,
+  CASE4
+};
+
+int
+foo (enum CASE_VALUES index)
+{
+  switch (index)
+    {
+    case CASE0:
+      return case0 ();
+    case CASE1:
+      return case1 ();
+    case CASE2:
+      return case2 ();
+    case CASE3:
+      return case3 ();
+    case CASE4:
+      return case4 ();
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-4.c
new file mode 100644
index 000000000..8db43e823
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr16458-4.c
@@ -0,0 +1,44 @@
+/* Test cse'ing of unsigned compares.  */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-jump-tables" } */
+
+/* The following tests fail due to an issue in expand not
+   attaching an type expression information on *index's reg rtx.  */
+
+/* { dg-final { scan-assembler-not "cmpwi" } } */
+/* { dg-final { scan-assembler-times "cmplwi" 5 } } */
+
+extern int case0 (void);
+extern int case1 (void);
+extern int case2 (void);
+extern int case3 (void);
+extern int case4 (void);
+
+enum CASE_VALUES
+{
+  CASE0 = 1,
+  CASE1,
+  CASE2,
+  CASE3,
+  CASE4
+};
+
+int
+foo (enum CASE_VALUES *index)
+{
+  switch (*index)
+    {
+    case CASE0:
+      return case0 ();
+    case CASE1:
+      return case1 ();
+    case CASE2:
+      return case2 ();
+    case CASE3:
+      return case3 ();
+    case CASE4:
+      return case4 ();
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr18096-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr18096-1.c
new file mode 100644
index 000000000..74612f393
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr18096-1.c
@@ -0,0 +1,12 @@
+/* PR middle-end/18096  */
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-options "-O2" } */
+
+void f(char*);
+
+void mkcatdefs(char *fname) /* { dg-error "too large" "stack frame too large" } */
+{
+  char line [2147483647];
+  f(line);
+} 
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr25960.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr25960.c
new file mode 100644
index 000000000..9ab9a10a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr25960.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */
+/* { dg-options "-O2 -mlong-double-128" } */
+
+extern void abort (void);
+
+volatile long double l, m, n;
+
+int
+main (void)
+{
+  l = __builtin_copysignl (0.0L, -1.0L);
+  m = __builtin_copysignl (0.0L, -1.0L);
+  n = l + m;
+  if (__builtin_copysignl (1.0L, n) >= 0.0L)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr26350.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr26350.c
new file mode 100644
index 000000000..6b4b20627
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr26350.c
@@ -0,0 +1,29 @@
+/* { dg-do compile { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */
+/* { dg-options "-O2 -mlong-double-128 -fpic" } */
+
+typedef int int32_t __attribute__ ((__mode__ (__SI__)));
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+typedef struct REGS REGS;
+typedef union { uint32_t F; } FW;
+typedef union { struct { FW L; } F; } DW;
+typedef struct _PSW {
+  DW ia;
+} PSW;
+struct REGS {
+  PSW psw;
+  DW cr[16];
+};
+struct ebfp {
+  long double v;
+};
+
+void s390_convert_fix32_to_bfp_ext_reg (REGS *regs)
+{
+  struct ebfp op1;
+  int32_t op2;
+  ((regs))->psw.ia.F.L.F += (4);
+  if(!((regs)->cr[(0)].F.L.F & 0x00040000))
+    op1.v = (long double)op2;
+  put_ebfp(&op1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr27158.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr27158.c
new file mode 100644
index 000000000..5476577a9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr27158.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec" } */
+#define REGLIST                                                              \
+         "77",  "78",  "79",  "80",  "81",  "82",  "83",  "84",  "85",  "86",\
+         "87",  "88",  "89",  "90",  "91",  "92",  "93",  "94",  "95",  "96",\
+         "97",  "98",  "99", "100", "101", "102", "103", "104", "105", "106",\
+        "107", "108"
+
+typedef __attribute__ ((vector_size (16))) float v4sf;
+
+void
+foo (int H)
+{
+  volatile v4sf tmp;
+  while (H-- > 0)
+    {
+      asm ("" : : : REGLIST);
+      tmp = (v4sf) __builtin_altivec_vspltisw (1);
+    }
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr35907.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr35907.c
new file mode 100644
index 000000000..7d5465ea1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr35907.c
@@ -0,0 +1,57 @@
+/* PR target/35907 */
+/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
+/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec" } */
+
+#define vector __attribute__((vector_size (16)))
+union
+{
+  vector int k;
+  int c[16];
+} u, v, w;
+vector int m;
+
+void __attribute__((noinline))
+bar (void *i, vector int j)
+{
+  asm volatile ("" : : "r" (i), "r" (&j) : "memory");
+}
+
+int __attribute__((noinline))
+foo (int i, vector int j)
+{
+  char *p = __builtin_alloca (64 + i);
+  m += u.k;
+  v.k = m;
+  w.k = j;
+  if (__builtin_memcmp (&v.c, &w.c, 16) != 0)
+    __builtin_abort ();
+  j += u.k;
+  bar (p, j);
+  j += u.k;
+  bar (p, j);
+  return 0;
+}
+
+void
+test (void)
+{
+  vector int l;
+  int i;
+  for (i = 0; i < 4; i++)
+    u.c[i] = i;
+  l = u.k;
+  if (foo (64, l))
+    __builtin_abort ();
+  l += u.k;
+  if (foo (64, l))
+    __builtin_abort ();
+}
+
+int
+main ()
+{
+  test ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr37168.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr37168.c
new file mode 100644
index 000000000..8d35157d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr37168.c
@@ -0,0 +1,14 @@
+/* PR target/37168 */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -maltivec" } */
+
+#define C 3.68249351546114573519399405666776E-44f
+#define vector __attribute__ ((altivec (vector__)))
+
+vector float
+foo (vector float a)
+{
+  vector float b = __builtin_vec_madd (b, a, (vector float) { C, C, C, C });
+  return b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr39457.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr39457.c
new file mode 100644
index 000000000..c4828bbb0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr39457.c
@@ -0,0 +1,56 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-options "-O2 -mminimal-toc" } */
+
+/* PR 39457 -- fix breakage because the compiler ran out of registers and
+   wanted to stash a floating point value to the LR/CTR register.  */
+
+/* -O2 -m64 -mminimal-toc */
+typedef struct { void *s; } S;
+typedef void (*T1) (void);
+typedef void (*T2) (void *, void *, int, void *);
+char *fn1 (const char *, ...);
+void *fn2 (void);
+int fn3 (char *, int);
+int fn4 (const void *);
+int fn5 (const void *);
+long fn6 (void) __attribute__ ((__const__));
+int fn7 (void *, void *, void *);
+void *fn8 (void *, long);
+void *fn9 (void *, long, const char *, ...);
+void *fn10 (void *);
+long fn11 (void) __attribute__ ((__const__));
+long fn12 (void *, const char *, T1, T2, void *);
+void *fn13 (void *);
+long fn14 (void) __attribute__ ((__const__));
+extern void *v1;
+extern char *v2;
+extern int v3;
+
+void
+foo (void *x, char *z)
+{
+  void *i1, *i2;
+  int y;
+  if (v1)
+    return;
+  v1 = fn9 (fn10 (fn2 ()), fn6 (), "x", 0., "y", 0., 0);
+  y = 520 - (520 - fn4 (x)) / 2;
+  fn9 (fn8 (v1, fn6 ()), fn6 (), "wig", fn8 (v1, fn14 ()), "x", 18.0,
+       "y", 16.0, "wid", 80.0, "hi", 500.0, 0);
+  fn9 (fn10 (v1), fn6 (), "x1", 0., "y1", 0., "x2", 80.0, "y2",
+       500.0, "f", fn3 ("fff", 0x0D0DFA00), 0);
+  fn13 (((S *) fn8 (v1, fn6 ()))->s);
+  fn12 (fn8 (v1, fn11 ()), "ev", (T1) fn7, 0, fn8 (v1, fn6 ()));
+  fn9 (fn8 (v1, fn6 ()), fn6 (), "wig",
+       fn8 (v1, fn14 ()), "x", 111.0, "y", 14.0, "wid", 774.0, "hi",
+       500.0, 0);
+  v1 = fn9 (fn10 (v1), fn6 (), "x1", 0., "y1", 0., "x2", 774.0, "y2",
+            500.0, "f", fn3 ("gc", 0x0D0DFA00), 0);
+  fn1 (z, 0);
+  i1 = fn9 (fn8 (v1, fn6 ()), fn6 (), "pixbuf", x, "x",
+            800 - fn5 (x) / 2, "y", y - fn4 (x), 0);
+  fn12 (fn8 (i1, fn11 ()), "ev", (T1) fn7, 0, "/ok/");
+  fn12 (fn8 (i1, fn11 ()), "ev", (T1) fn7, 0, 0);
+  i2 = fn9 (fn8 (v1, fn6 ()), fn6 (), "txt", "OK", "fnt", v2, "x",
+            800, "y", y - fn4 (x) + 15, "ar", 0, "f", v3, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr39902-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr39902-2.c
new file mode 100644
index 000000000..463a36c1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr39902-2.c
@@ -0,0 +1,28 @@
+/* Check that simplification "x*(-1)" -> "-x" is not performed for decimal
+   float types.  */
+
+/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */
+/* { dg-options "-std=gnu99 -O -mcpu=power6" } */
+/* { dg-final { scan-assembler-not "fneg" } } */
+
+extern _Decimal32 a32, b32;
+extern _Decimal64 a64, b64;
+extern _Decimal128 a128, b128;
+
+void
+foo32 (void)
+{
+  b32 = a32 * -1.0DF;
+}
+
+void
+foo64 (void)
+{
+  b64 = a64 * -1.0DD;
+}
+
+void
+foo128 (void)
+{
+  b128 = a128 * -1.0DL;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr41175.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr41175.c
new file mode 100644
index 000000000..2f0137962
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr41175.c
@@ -0,0 +1,461 @@
+/* PR target/41175 */
+/* { dg-do run } */
+/* { dg-options "-Os" } */
+
+#define X2(n) X1(n##0) X1(n##1)
+#define X4(n) X2(n##0) X2(n##1)
+#define X8(n) X4(n##0) X4(n##1)
+
+#ifndef __SPE__
+#define FLOAT_REG_CONSTRAINT "f"
+#else
+#define FLOAT_REG_CONSTRAINT "r"
+#endif
+
+volatile int ll;
+
+__attribute__((noinline)) void
+foo (void)
+{
+  asm volatile ("" : : : "memory");
+}
+
+__attribute__((noinline)) void
+bar (char *p)
+{
+  asm volatile ("" : : "r" (p) : "memory");
+}
+
+__attribute__((noinline)) void
+f1 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+  foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f2 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+  char *pp = __builtin_alloca (ll);
+  bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f3 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+}
+
+#ifndef __NO_FPRS__
+__attribute__((noinline)) void
+f4 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X4(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X4(d) "=m" (mem) : : "memory");
+  foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X4(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f5 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X4(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X4(d) "=m" (mem) : : "memory");
+  char *pp = __builtin_alloca (ll);
+  bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X4(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f6 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X4(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X4(d) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X4(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f7 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X2(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X2(d) "=m" (mem) : : "memory");
+  foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X2(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f8 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X2(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X2(d) "=m" (mem) : : "memory");
+  char *pp = __builtin_alloca (ll);
+  bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X2(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f9 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X8(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X2(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X2(d) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X8(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X2(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f10 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X4(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X1(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X4(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X1(d) "=m" (mem) : : "memory");
+  foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X4(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X1(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f11 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X4(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X1(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X4(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X1(d) "=m" (mem) : : "memory");
+  char *pp = __builtin_alloca (ll);
+  bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X4(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X1(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f12 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X4(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X1(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X4(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X1(d) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X4(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X1(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f13 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X2(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X8(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X2(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X8(d) "=m" (mem) : : "memory");
+  foo ();
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X2(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X8(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f14 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X2(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X8(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X2(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X8(d) "=m" (mem) : : "memory");
+  char *pp = __builtin_alloca (ll);
+  bar (pp);
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X2(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X8(d) "m" (mem) : "memory");
+}
+
+__attribute__((noinline)) void
+f15 (void)
+{
+  int mem;
+#undef X1
+#define X1(n) int gpr##n = 0;
+  X8(a) X8(b) X2(c)
+#undef X1
+#define X1(n) double fpr##n = 0.0;
+  X8(d)
+#undef X1
+#define X1(n) "+r" (gpr##n),
+  asm volatile ("" : X8(a) "=m" (mem) : : "memory");
+  asm volatile ("" : X8(b) "=m" (mem) : : "memory");
+  asm volatile ("" : X2(c) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : X8(d) "=m" (mem) : : "memory");
+#undef X1
+#define X1(n) "r" (gpr##n),
+  asm volatile ("" : : X8(a) "m" (mem) : "memory");
+  asm volatile ("" : : X8(b) "m" (mem) : "memory");
+  asm volatile ("" : : X2(c) "m" (mem) : "memory");
+#undef X1
+#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n),
+  asm volatile ("" : : X8(d) "m" (mem) : "memory");
+}
+#endif
+
+int
+main ()
+{
+  ll = 60;
+  f1 ();
+  f2 ();
+  f3 ();
+#ifndef __NO_FPRS__
+  f4 ();
+  f5 ();
+  f6 ();
+  f7 ();
+  f8 ();
+  f9 ();
+  f10 ();
+  f11 ();
+  f12 ();
+  f13 ();
+  f14 ();
+  f15 ();
+#endif
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr42747.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr42747.c
new file mode 100644
index 000000000..41362db17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr42747.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+
+double foo (double x) { return __builtin_sqrt (x); }
+
+/* { dg-final { scan-assembler "xssqrtdp\|fsqrt" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr43154.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr43154.c
new file mode 100644
index 000000000..eb1919743
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr43154.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Make sure that vec_mergel and vec_mergeh are supported for V2DF/V2DI types.  */
+/* { dg-final { scan-assembler-times "xxpermdi" 4 } } */
+
+#include <altivec.h>
+
+void vec_high_v2df (vector double *a, vector double *b, vector double *c)
+{
+  *a = vec_mergeh (*b, *c);
+}
+
+void vec_low_v2df (vector double *a, vector double *b, vector double *c)
+{
+  *a = vec_mergel (*b, *c);
+}
+
+void vec_high_v2di (vector long long *a, vector long long *b, vector long long *c)
+{
+  *a = vec_mergeh (*b, *c);
+}
+
+void vec_low_v2di (vector long long *a, vector long long *b, vector long long *c)
+{
+  *a = vec_mergel (*b, *c);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
new file mode 100644
index 000000000..fc2cd7d7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt -fno-ident" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it (double x)
+{
+  return pow (x, 0.5);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    if (convert_it (values[i]) != sqrt (values[i]))
+      abort ();
+
+  return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "fsqrt|xssqrtdp" 2 { target powerpc*-*-* } } } */
+/* { dg-final { scan-assembler-not "bl\[\\. \]+pow" { target powerpc*-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-10.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
new file mode 100644
index 000000000..3be4728d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-10.c
@@ -0,0 +1,29 @@
+/* { dg-do run } */
+/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it (double x)
+{
+  return pow (x, 0.25);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    if (convert_it (values[i]) != sqrt (sqrt (values[i])))
+      abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-11.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
new file mode 100644
index 000000000..43b6728a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-11.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it (double x)
+{
+  return pow (x, 0.75);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  double PREC = 0.999999;
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    {
+      volatile double x, y;
+      x = sqrt (values[i]);
+      y = sqrt (sqrt (values[i]));
+  
+      if (fabs (convert_it (values[i]) / (x * y)) < PREC)
+	abort ();
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-13.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
new file mode 100644
index 000000000..b9fd63973
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-13.c
@@ -0,0 +1,28 @@
+/* { dg-do run } */
+/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it (double x)
+{
+  return pow (x, 1.0 / 6.0);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 729.0, 64.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    if (convert_it (values[i]) != cbrt (sqrt (values[i])))
+      abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-14.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
new file mode 100644
index 000000000..5affff13b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-14.c
@@ -0,0 +1,79 @@
+/* { dg-do run } */
+/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it_1 (double x)
+{
+  return pow (x, 1.5);
+}
+
+static double
+convert_it_2 (double x)
+{
+  return pow (x, 2.5);
+}
+
+static double
+convert_it_3 (double x)
+{
+  return pow (x, -0.5);
+}
+
+static double
+convert_it_4 (double x)
+{
+  return pow (x, 10.5);
+}
+
+static double
+convert_it_5 (double x)
+{
+  return pow (x, -3.5);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  double PREC = .999999;
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    {
+      volatile double x, y;
+
+      x = sqrt (values[i]);
+      y = __builtin_powi (values[i], 1);
+      if (fabs (convert_it_1 (values[i]) / (x * y)) < PREC)
+	abort ();
+
+      x = sqrt (values[i]);
+      y = __builtin_powi (values[i], 2);
+      if (fabs (convert_it_2 (values[i]) / (x * y)) < PREC)
+	abort ();
+
+      x = sqrt (values[i]);
+      y = __builtin_powi (values[i], -1);
+      if (fabs (convert_it_3 (values[i]) / (x * y)) < PREC)
+	abort ();
+
+      x = sqrt (values[i]);
+      y = __builtin_powi (values[i], 10);
+      if (fabs (convert_it_4 (values[i]) / (x * y)) < PREC)
+	abort ();
+
+      x = sqrt (values[i]);
+      y = __builtin_powi (values[i], -4);
+      if (fabs (convert_it_5 (values[i]) / (x * y)) < PREC)
+	abort ();
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-15.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-15.c
new file mode 100644
index 000000000..b4c966062
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-15.c
@@ -0,0 +1,68 @@
+/* { dg-do run } */
+/* { dg-skip-if "-mpowerpc-gpopt not supported" { powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it_1 (double x)
+{
+  return pow (x, 10.0 / 3.0);
+}
+
+static double
+convert_it_2 (double x)
+{
+  return pow (x, 11.0 / 3.0);
+}
+
+static double
+convert_it_3 (double x)
+{
+  return pow (x, -7.0 / 3.0);
+}
+
+static double
+convert_it_4 (double x)
+{
+  return pow (x, -8.0 / 3.0);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  double PREC = .999999;
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    {
+      volatile double x, y;
+
+      x = __builtin_powi (values[i], 3);
+      y = __builtin_powi (cbrt (values[i]), 1);
+      if (fabs (convert_it_1 (values[i]) / (x * y)) < PREC)
+	abort ();
+
+      x = __builtin_powi (values[i], 3);
+      y = __builtin_powi (cbrt (values[i]), 2);
+      if (fabs (convert_it_2 (values[i]) / (x * y)) < PREC)
+	abort ();
+
+      x = __builtin_powi (values[i], -3);
+      y = __builtin_powi (cbrt (values[i]), 2);
+      if (fabs (convert_it_3 (values[i]) / (x * y)) < PREC)
+	abort ();
+
+      x = __builtin_powi (values[i], -3);
+      y = __builtin_powi (cbrt (values[i]), 1);
+      if (fabs (convert_it_4 (values[i]) / (x * y)) < PREC)
+	abort ();
+    }
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-16.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-16.c
new file mode 100644
index 000000000..d9488e3b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -mcpu=power6" } */
+
+double foo (double x, double y)
+{
+  return __builtin_pow (x, 0.75) + y;
+}
+
+
+/* { dg-final { scan-assembler "fmadd" { target powerpc*-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-2.c
new file mode 100644
index 000000000..77679873b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-2.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt -fno-ident" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it (double x)
+{
+  return pow (x, 0.25);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    if (convert_it (values[i]) != sqrt (sqrt (values[i])))
+      abort ();
+
+  return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "fsqrt|xssqrtdp" 4 { target powerpc*-*-* } } } */
+/* { dg-final { scan-assembler-not "bl\[\\. \]+pow" { target powerpc*-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-3.c
new file mode 100644
index 000000000..db972168c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt -fno-ident" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it (double x)
+{
+  return pow (x, 0.75);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    if (convert_it (values[i]) != sqrt(values[i]) * sqrt (sqrt (values[i])))
+      abort ();
+
+  return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "sqrt" 4 { target powerpc*-*-* } } } */
+/* { dg-final { scan-assembler-not "bl\[\\. \]+pow" { target powerpc*-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-4.c
new file mode 100644
index 000000000..249898ac0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-4.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-skip-if "No __builtin_cbrt" { powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt -fno-ident" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it (double x)
+{
+  return pow (x, 1.0 / 3.0);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 729.0, 64.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    if (convert_it (values[i]) != cbrt (values[i]))
+      abort ();
+
+  return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "cbrt" 2 { target powerpc*-*-* } } } */
+/* { dg-final { scan-assembler-not "bl\[\\. \]+pow" { target powerpc*-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-5.c
new file mode 100644
index 000000000..e15e7c097
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-5.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-skip-if "No __builtin_cbrt" { powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt -fno-ident" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it (double x)
+{
+  return pow (x, 1.0 / 6.0);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 729.0, 64.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    if (convert_it (values[i]) != cbrt (sqrt (values[i])))
+      abort ();
+
+  return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "cbrt" 2 { target powerpc*-*-* } } } */
+/* { dg-final { scan-assembler-not "bl\[\\. \]+pow" { target powerpc*-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-7.c
new file mode 100644
index 000000000..2b7d0940a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-7.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt -fno-ident" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it_1 (double x)
+{
+  return pow (x, 1.5);
+}
+
+static double
+convert_it_2 (double x)
+{
+  return pow (x, 2.5);
+}
+
+static double
+convert_it_3 (double x)
+{
+  return pow (x, -0.5);
+}
+
+static double
+convert_it_4 (double x)
+{
+  return pow (x, 10.5);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    {
+      if (convert_it_1 (values[i]) != sqrt (values[i]) * __builtin_powi (values[i], 1))
+	abort ();
+      if (convert_it_2 (values[i]) != sqrt (values[i]) * __builtin_powi (values[i], 2))
+	abort ();
+      if (convert_it_3 (values[i]) != sqrt (values[i]) * __builtin_powi (values[i], -1))
+	abort ();
+      if (convert_it_4 (values[i]) != sqrt (values[i]) * __builtin_powi (values[i], 10))
+	abort ();
+    }
+
+  return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "sqrt" 5 { target powerpc*-*-* } } } */
+/* { dg-final { scan-assembler-not "bl\[\\. \]+pow" { target powerpc*-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-8.c
new file mode 100644
index 000000000..7d2af12db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr46728-8.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-skip-if "No __builtin_cbrt" { powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -ffast-math -fno-inline -fno-unroll-loops -lm -mpowerpc-gpopt -fno-ident" } */
+
+#include <math.h>
+
+extern void abort (void);
+
+#define NVALS 6
+
+static double
+convert_it_1 (double x)
+{
+  return pow (x, 10.0 / 3.0);
+}
+
+static double
+convert_it_2 (double x)
+{
+  return pow (x, 11.0 / 3.0);
+}
+
+static double
+convert_it_3 (double x)
+{
+  return pow (x, -7.0 / 3.0);
+}
+
+static double
+convert_it_4 (double x)
+{
+  return pow (x, -8.0 / 3.0);
+}
+
+int
+main (int argc, char *argv[])
+{
+  double values[NVALS] = { 3.0, 1.95, 2.227, 4.0, 256.0, .0008797 };
+  unsigned i;
+
+  for (i = 0; i < NVALS; i++)
+    {
+      if (convert_it_1 (values[i]) != 
+	  __builtin_powi (values[i], 3) * __builtin_powi (cbrt (values[i]), 1))
+	abort ();
+      if (convert_it_2 (values[i]) != 
+	  __builtin_powi (values[i], 3) * __builtin_powi (cbrt (values[i]), 2))
+	abort ();
+      if (convert_it_3 (values[i]) != 
+	  __builtin_powi (values[i], -3) * __builtin_powi (cbrt (values[i]), 2))
+	abort ();
+      if (convert_it_4 (values[i]) !=
+	  __builtin_powi (values[i], -3) * __builtin_powi (cbrt (values[i]), 1))
+	abort ();
+    }
+
+  return 0;
+}
+
+
+/* { dg-final { scan-assembler-times "cbrt" 5 { target powerpc*-*-* } } } */
+/* { dg-final { scan-assembler-not "bl\[\\. \]+pow" { target powerpc*-*-* } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47197.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47197.c
new file mode 100644
index 000000000..a8930f2a5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47197.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Compile-only test to ensure that expressions can be passed to
+   Altivec builtins without error.  */
+
+#include <altivec.h>
+
+void func(unsigned char *buf, unsigned len)
+{
+        vec_dst(buf, (len >= 256 ? 0 : len) | 512, 2);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47251.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47251.c
new file mode 100644
index 000000000..6cb9f492e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47251.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -msoft-float -mcpu=power7" } */
+
+/* PR 47151: libgcc fails to build when using --with-cpu=power7 due to a missed
+   TARGET_HARD_FLOAT test.  */
+unsigned long long
+func (float a)
+{
+  const float dfa = a;
+  const unsigned int hi = dfa / 0x1p32f;
+  const unsigned int lo = dfa - (float) hi * 0x1p32f;
+  return ((unsigned long long) hi << (4 * 8)) | lo;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47755-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47755-2.c
new file mode 100644
index 000000000..5edcc118e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47755-2.c
@@ -0,0 +1,134 @@
+/* { dg-do run { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target vsx_hw } */
+/* { dg-options "-O3 -mcpu=power7" } */
+
+/* PR 47755: Make sure compiler generates correct code for various
+   V2DI constants.  */
+
+#ifdef DEBUG
+#include <stdio.h>
+
+static int num_errors;
+#define FAIL_LL(A, B) \
+  (num_errors++, printf ("Fail (%i, %i)\n", (int)(A), (int)(B)))
+#define FAIL_I(A, B, C, D) \
+  (num_errors++, \
+  printf ("Fail (%i, %i, %i, %i)\n", (int)(A), (int)(B), (int)(C), (int)(D)))
+
+#else
+extern void abort (void) __attribute__((__noreturn__));
+#define FAIL_LL(A, B) abort ()
+#define FAIL_I(A, B, C, D) abort ()
+#endif
+
+static test_ll (vector long long, long long, long long) __attribute__((__noinline__));
+
+static
+test_ll (vector long long v, long long a, long long b)
+{
+  union {
+    vector long long v;
+    long long ll[2];
+  } u;
+
+  u.v = v;
+  if (u.ll[0] != a && u.ll[1] != b)
+    FAIL_LL (a, b);
+}
+
+#define TEST_LL(A,B) test_ll ((vector long long){ (A), (B) }, (A), (B))
+
+static test_i (vector int, int, int, int, int) __attribute__((__noinline__));
+
+static
+test_i (vector int v, int a, int b, int c, int d)
+{
+  union {
+    vector int v;
+    int i[4];
+  } u;
+
+  u.v = v;
+  if (u.i[0] != a && u.i[1] != b && u.i[2] != c && u.i[3] != d)
+    FAIL_I (a, b, c, d);
+}
+
+#define TEST_I(A,B,C,D) \
+  test_i ((vector int){ (A), (B), (C), (D) }, (A), (B), (C), (D))
+
+int
+main (void)
+{
+  TEST_LL (-2LL, -2LL);
+  TEST_LL (-2LL, -1LL);
+  TEST_LL (-2LL,  0LL);
+  TEST_LL (-2LL,  1LL);
+  TEST_LL (-2LL,  2LL);
+
+  TEST_LL (-1LL, -2LL);
+  TEST_LL (-1LL, -1LL);
+  TEST_LL (-1LL,  0LL);
+  TEST_LL (-1LL,  1LL);
+  TEST_LL (-1LL,  2LL);
+
+  TEST_LL (0LL, -2LL);
+  TEST_LL (0LL, -1LL);
+  TEST_LL (0LL,  0LL);
+  TEST_LL (0LL,  1LL);
+  TEST_LL (0LL,  2LL);
+
+  TEST_LL (1LL, -2LL);
+  TEST_LL (1LL, -1LL);
+  TEST_LL (1LL,  0LL);
+  TEST_LL (1LL,  1LL);
+  TEST_LL (1LL,  2LL);
+
+  TEST_LL (2LL, -2LL);
+  TEST_LL (2LL, -1LL);
+  TEST_LL (2LL,  0LL);
+  TEST_LL (2LL,  1LL);
+  TEST_LL (2LL,  2LL);
+
+  /* We could use VSPLTI instructions for these tests.  */
+  TEST_LL (0x0101010101010101LL, 0x0101010101010101LL);
+  TEST_LL (0x0001000100010001LL, 0x0001000100010001LL);
+  TEST_LL (0x0000000100000001LL, 0x0000000100000001LL);
+
+  TEST_LL (0x0404040404040404LL, 0x0404040404040404LL);
+  TEST_LL (0x0004000400040004LL, 0x0004000400040004LL);
+  TEST_LL (0x0000000400000004LL, 0x0000000400000004LL);
+
+  TEST_LL (0xf8f8f8f8f8f8f8f8LL, 0xf8f8f8f8f8f8f8f8LL);
+  TEST_LL (0xfff8fff8fff8fff8LL, 0xfff8fff8fff8fff8LL);
+  TEST_LL (0xfffffff8fffffff8LL, 0xfffffff8fffffff8LL);
+
+  /* We could use VSPLTI instructions for these tests.  */
+  TEST_I (-2, -2, -2, -2);
+  TEST_I (-1, -1, -1, -1);
+  TEST_I ( 0,  0,  0,  0);
+  TEST_I ( 1,  1,  1,  1);
+  TEST_I ( 2,  2,  2,  2);
+
+  TEST_I (0x01010101, 0x01010101, 0x01010101, 0x01010101);
+  TEST_I (0x00010001, 0x00010001, 0x00010001, 0x00010001);
+
+  TEST_I (0x02020202, 0x02020202, 0x02020202, 0x02020202);
+  TEST_I (0x00020002, 0x00020002, 0x00020002, 0x00020002);
+
+  TEST_I (0xf8f8f8f8, 0xf8f8f8f8, 0xf8f8f8f8, 0xf8f8f8f8);
+  TEST_I (0xfff8fff8, 0xfff8fff8, 0xfff8fff8, 0xfff8fff8);
+
+  /* non-easy constants.  */
+  TEST_I (-2, -1,  0,  1);
+  TEST_I ( 1,  0, -1, -2);
+
+  TEST_I (-1, -1,  0,  0);
+  TEST_I ( 0,  0, -1, -1);
+
+#ifdef DEBUG
+  printf ("%d error%s\n", num_errors, (num_errors == 1) ? "" : "s");
+#endif
+
+  return 0;
+};
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47755.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47755.c
new file mode 100644
index 000000000..6dbd1fe02
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47755.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxlxor" } } */
+/* { dg-final { scan-assembler-not "lxvd2x" } } */
+/* { dg-final { scan-assembler-not "lxvw4x" } } */
+/* { dg-final { scan-assembler-not "lvx" } } */
+
+/* PR 47755: Compiler loads vector constant of 0 from TOC instead of using
+   xxlxor.  */
+void
+func (vector long long *p)
+{
+  *p = (vector long long) { 0LL, 0LL };
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47862.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47862.c
new file mode 100644
index 000000000..528cace38
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr47862.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler-not "stfd" } } */
+
+/* PR 47862: Verify caller-save spill of vectors in FP regs do not use
+   legacy FP insns, which spill only half the vector.  */
+extern vector double dd[15];
+
+vector double foo() {
+  vector double a,b,c,d,e,f,g,h,i,j,k,l,m,n;
+
+  a=dd[1]; b=dd[2]; c=dd[3]; d=dd[4]; e=dd[5]; f=dd[6]; g=dd[7]; h=dd[8]; i=dd[9];
+  j=dd[10]; k=dd[11]; l=dd[12]; m=dd[13]; n=dd[14];
+  bar();
+  return (a+b+c+d+e+f+g+h+i+j+k+l+m+n);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-1.c
new file mode 100644
index 000000000..fd7cd3d9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-1.c
@@ -0,0 +1,30 @@
+/* Test for ICE arising from VSX code generation.  */
+/* { dg-do compile } */
+/* { dg-options "-O3 -mcpu=power7 -funroll-loops" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+int sourcenode;
+int ARCHelems;
+int *source_elms;
+void
+foo (int argc, char **argv)
+{
+  int i, j;
+  int cor[4];
+  double Ke[12][12], Me[12], Ce[12], Mexv[12], Cexv[12], v[12];
+  for (i = 0; i < ARCHelems; i++)
+    {
+      for (j = 0; j < 12; j++)
+	Me[j] = 0.0;
+      if (cor[j] == sourcenode)
+	vv12x12 (Me, v, Mexv);
+      vv12x12 (Ce, v, Cexv);
+      if (source_elms[i] == 3)
+	for (j = 0; j < 12; j++)
+	  {
+	    v[j] = -v[j];
+	    Mexv[j] = -Mexv[j];
+	    Cexv[j] = -Cexv[j];
+	  }
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-2.c
new file mode 100644
index 000000000..2cdec6a68
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-2.c
@@ -0,0 +1,38 @@
+/* Test for ICE arising from VSX code generation.  */
+/* { dg-do compile } */
+/* { dg-options "-O3 -mcpu=power7" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+struct timeval
+{
+  long tv_sec;
+  long tv_usec;
+};
+
+extern char *bar (struct timeval *);
+int *error;
+
+void
+foo (void *ptr)
+{
+  struct timeval tm;
+  long n1, n2;
+
+  if (!ptr)
+    {
+      *error = 1;
+      n1 = -1;
+      n2 = -1;
+    }
+  else
+    {
+      n1 = 0;
+      n2 = *error;
+    }
+
+  tm.tv_sec = n1;
+  tm.tv_usec = n2;
+
+  if (*error)
+    bar (&tm);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-3.c
new file mode 100644
index 000000000..399b3d3ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48053-3.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7" } */
+
+/* Cut down example from s_scalbnl that aborted on 32-bit when the fix for
+   48053 went in to allow creating DImode 0's in VSX registers.  */
+
+typedef union
+{
+  long double value;
+  struct
+  {
+    unsigned long long msw;
+    unsigned long long lsw;
+  } parts64;
+  struct
+  {
+    unsigned int w0, w1, w2, w3;
+  } parts32;
+} ieee854_long_double_shape_type;
+
+static const long double twolm54 = 5.55111512312578270212e-17;
+
+long double foo (long double x, int n)
+{
+  long long k, hx, lx;
+  ieee854_long_double_shape_type qw_u;
+
+  qw_u.value = x;
+  hx = qw_u.parts64.msw;
+  lx = qw_u.parts64.lsw;
+
+  k = ((hx >> 52) & 0x7ff) + n + 54;
+
+  qw_u.parts64.msw = ((hx & 0x800fffffffffffffULL) | (k << 52));
+  qw_u.parts64.lsw = lx;
+  x = qw_u.value;
+
+  return x*twolm54;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48192.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48192.c
new file mode 100644
index 000000000..515926085
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48192.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7 -std=gnu89" } */
+
+/* Make sure that the conditional macros vector, bool, and pixel are not
+   considered as being defined.  */
+
+#ifdef bool
+#error "bool is considered defined"
+#endif
+
+#ifdef vector
+#error "vector is considered defined"
+#endif
+
+#ifdef pixel
+#error "pixel is condsidered defined"
+#endif
+
+#if defined(bool)
+#error "bool is considered defined"
+#endif
+
+#if defined(vector)
+#error "vector is considered defined"
+#endif
+
+#if defined(pixel)
+#error "pixel is condsidered defined"
+#endif
+
+#ifndef bool
+#else
+#error "bool is considered defined"
+#endif
+
+#ifndef vector
+#else
+#error "vector is considered defined"
+#endif
+
+#ifndef pixel
+#else
+#error "pixel is condsidered defined"
+#endif
+
+#define bool long double
+bool pixel = 0;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48226.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48226.c
new file mode 100644
index 000000000..a436f1da5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48226.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7" } */
+
+/* The bug shows up if you compile with -maltivec or -mcpu=power7, due to one
+   of the vector's being eliminated due to rs6000_macro_to_expand being called
+   recursively.  */
+
+struct vector {
+  float v[4];
+};
+
+struct vector vector = { 1.0, 2.0, 3.0, 4.0 };
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48258-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48258-1.c
new file mode 100644
index 000000000..3ccbf7693
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48258-1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "xvaddsp" 3 } } */
+/* { dg-final { scan-assembler-times "xvminsp" 3 } } */
+/* { dg-final { scan-assembler-times "xvmaxsp" 3 } } */
+/* { dg-final { scan-assembler-times "xxsldwi" 6 } } */
+/* { dg-final { scan-assembler-times "xscvspdp" 3 } } */
+/* { dg-final { scan-assembler-not "stvewx" } } */
+/* { dg-final { scan-assembler-not "stvx" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "stxvw4x" } } */
+
+#include <stddef.h>
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+float values[SIZE] __attribute__((__aligned__(32)));
+
+float
+vector_sum (void)
+{
+  size_t i;
+  float sum = 0.0f;
+
+  for (i = 0; i < SIZE; i++)
+    sum += values[i];
+
+  return sum;
+}
+
+float
+vector_min (void)
+{
+  size_t i;
+  float min = values[0];
+
+  for (i = 0; i < SIZE; i++)
+    min = __builtin_fminf (min, values[i]);
+
+  return min;
+}
+
+float
+vector_max (void)
+{
+  size_t i;
+  float max = values[0];
+
+  for (i = 0; i < SIZE; i++)
+    max = __builtin_fmaxf (max, values[i]);
+
+  return max;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48258-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48258-2.c
new file mode 100644
index 000000000..23ed9f26d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48258-2.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7 -mabi=altivec -ffast-math" } */
+/* { dg-final { scan-assembler "xvadddp" } } */
+/* { dg-final { scan-assembler "xvmindp" } } */
+/* { dg-final { scan-assembler "xvmaxdp" } } */
+
+#include <stddef.h>
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+double values[SIZE] __attribute__((__aligned__(32)));
+
+double
+vector_sum (void)
+{
+  size_t i;
+  double sum = 0.0;
+
+  for (i = 0; i < SIZE; i++)
+    sum += values[i];
+
+  return sum;
+}
+
+double
+vector_min (void)
+{
+  size_t i;
+  double min = values[0];
+
+  for (i = 0; i < SIZE; i++)
+    min = __builtin_fmin (min, values[i]);
+
+  return min;
+}
+
+double
+vector_max (void)
+{
+  size_t i;
+  double max = values[0];
+
+  for (i = 0; i < SIZE; i++)
+    max = __builtin_fmax (max, values[i]);
+
+  return max;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48857.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48857.c
new file mode 100644
index 000000000..e8201c037
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr48857.c
@@ -0,0 +1,25 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7 -mabi=altivec" } */
+/* { dg-final { scan-assembler-times "lxvd2x" 1 } } */
+/* { dg-final { scan-assembler-times "stxvd2x" 1 } } */
+/* { dg-final { scan-assembler-not "ld" } } */
+/* { dg-final { scan-assembler-not "lwz" } } */
+/* { dg-final { scan-assembler-not "stw" } } */
+/* { dg-final { scan-assembler-not "addi" } } */
+
+typedef vector long long v2di_type;
+
+v2di_type
+return_v2di (v2di_type *ptr)
+{
+  return *ptr;		/* should generate lxvd2x 34,0,3.  */
+}
+
+void
+pass_v2di (v2di_type arg, v2di_type *ptr)
+{
+  *ptr = arg;		/* should generate stxvd2x 34,0,{3,5}.  */
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr51623.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr51623.c
new file mode 100644
index 000000000..2ac118c7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr51623.c
@@ -0,0 +1,123 @@
+/* PR target/51623 */
+/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* powerpc-*-rtems* } } } } */
+/* { dg-options "-mrelocatable -ffreestanding" } */
+
+/* This generated an error, since the compiler was calling
+   unlikely_text_section_p in a context where it wasn't valid.  */
+
+typedef long long loff_t;
+typedef unsigned size_t;
+
+
+struct mtd_info {
+  unsigned writesize;
+  unsigned oobsize;
+  const char *name;
+};
+
+extern int strcmp(const char *,const char *);
+extern char * strchr(const char *,int);
+
+struct cmd_tbl_s {
+  char *name;
+};
+
+
+int printf(const char *fmt, ...) __attribute__ ((format (__printf__, 1, 2)));
+void* malloc(size_t);
+void free(void*);
+
+
+extern int nand_curr_device;
+extern struct mtd_info nand_info[];
+
+static int nand_dump(struct mtd_info *nand, unsigned long off, int only_oob)
+{
+  int i;
+  unsigned char *datbuf, *oobbuf, *p;
+
+  datbuf = malloc(nand->writesize + nand->oobsize);
+  oobbuf = malloc(nand->oobsize);
+  off &= ~(nand->writesize - 1);
+
+  printf("Page %08lx dump:\n", off);
+  i = nand->writesize >> 4;
+  p = datbuf;
+
+  while (i--) {
+    if (!only_oob)
+      printf("\t%02x %02x %02x %02x %02x %02x %02x %02x"
+	     "  %02x %02x %02x %02x %02x %02x %02x %02x\n",
+	     p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
+	     p[8], p[9], p[10], p[11], p[12], p[13], p[14],
+	     p[15]);
+    p += 16;
+  }
+
+  i = nand->oobsize >> 3;
+  free(datbuf);
+  free(oobbuf);
+
+  return 0;
+}
+
+int do_nand(struct cmd_tbl_s * cmdtp, int flag, int argc, char *argv[])
+{
+  int dev;
+  unsigned long  off;
+  char *cmd, *s;
+  struct mtd_info *nand;
+
+  if (argc < 2)
+    goto usage;
+
+  cmd = argv[1];
+
+  if (strcmp(cmd, "info") == 0) {
+    putc('\n');
+    return 0;
+  }
+
+  if (strcmp(cmd, "device") == 0) {
+    if (argc < 3) {
+      putc('\n');
+    }
+    dev = (int)simple_strtoul(argv[2], ((void *)0), 10);
+    nand_curr_device = dev;
+    return 0;
+  }
+
+  if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0  )
+    goto usage;
+  
+  if (nand_curr_device < 0 ) {
+    return 1;
+  }
+  nand = &nand_info[nand_curr_device];
+
+  if (strcmp(cmd, "erase") == 0 || strcmp(cmd, "scrub") == 0) {
+    int clean = argc > 2 && !strcmp("clean", argv[2]);
+    int scrub = !strcmp(cmd, "scrub");
+    return 0;
+  }
+
+  if (strncmp(cmd, "dump", 4) == 0) {
+    if (argc < 3)
+      goto usage;
+
+    s = strchr(cmd, '.');
+    off = (int)simple_strtoul(argv[2], ((void *)0), 16);
+    
+    if (s != ((void *)0) && strcmp(s, ".oob") == 0)
+      nand_dump(nand, off, 1);
+    else
+      nand_dump(nand, off, 0);
+    
+    return 0;
+  }
+usage:
+  cmd_usage(cmdtp);
+  return 1;
+}
+
+void *ptr = do_nand;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52199.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52199.c
new file mode 100644
index 000000000..e22319388
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52199.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7 -fmerge-all-constants" } */
+
+struct locale_time_t
+{
+  const char *abday[7];
+  const unsigned int *wabday[7];
+};
+
+static const unsigned int empty_wstr[1] = { 0 };
+
+void
+time_read (struct locale_time_t *time)
+{
+  int cnt;
+
+  for (cnt=0; cnt < 7; cnt++)
+    {
+      time->abday[cnt] = "";
+      time->wabday[cnt] = empty_wstr;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52457.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52457.c
new file mode 100644
index 000000000..4470e5502
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52457.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target vsx_hw } */
+/* { dg-options "-O1 -mcpu=power7" } */
+
+extern void abort (void);
+
+typedef long long T;
+typedef T vl_t __attribute__((vector_size(2 * sizeof (T))));
+
+vl_t
+buggy_func (T x)
+{
+  vl_t w;
+  T *p = (T *)&w;
+  p[0] = p[1] = x;
+  return w;
+}
+
+int
+main(void)
+{
+  vl_t rval;
+  T *pl;
+
+  pl = (T *) &rval;
+  rval = buggy_func (2);
+
+  if (pl[0] != 2 || pl[1] != 2)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52775.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52775.c
new file mode 100644
index 000000000..4027819ee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr52775.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O1 -mcpu=power4" } */
+/* { dg-final { scan-assembler-times "fcfid" 2 } } */
+
+double
+int_to_double (int *p)
+{
+  return (double)*p;
+}
+
+double
+long_long_to_double (long long *p)
+{
+  return (double)*p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr53199.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr53199.c
new file mode 100644
index 000000000..89a0cad06
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr53199.c
@@ -0,0 +1,50 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power6 -mavoid-indexed-addresses" } */
+/* { dg-final { scan-assembler-times "lwbrx" 6 } } */
+/* { dg-final { scan-assembler-times "stwbrx" 6 } } */
+
+/* PR 51399: bswap gets an error if -mavoid-indexed-addresses was used in
+   creating the two lwbrx instructions.  */
+
+long long
+load64_reverse_1 (long long *p)
+{
+  return __builtin_bswap64 (*p);
+}
+
+long long
+load64_reverse_2 (long long *p)
+{
+  return __builtin_bswap64 (p[1]);
+}
+
+long long
+load64_reverse_3 (long long *p, int i)
+{
+  return __builtin_bswap64 (p[i]);
+}
+
+void
+store64_reverse_1 (long long *p, long long x)
+{
+  *p = __builtin_bswap64 (x);
+}
+
+void
+store64_reverse_2 (long long *p, long long x)
+{
+  p[1] = __builtin_bswap64 (x);
+}
+
+void
+store64_reverse_3 (long long *p, long long x, int i)
+{
+  p[i] = __builtin_bswap64 (x);
+}
+
+long long
+reg_reverse (long long x)
+{
+  return __builtin_bswap64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr53487.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr53487.c
new file mode 100644
index 000000000..3e8265b37
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr53487.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7 -misel -ffast-math" } */
+
+struct phylo_s {
+  int left;
+};
+
+int Cluster(float **dmx, int N, struct phylo_s *tree)
+{
+  float **mx;
+  int *coord;
+  int i;
+  int Np;
+  int row, col;
+  float min;
+  for (col = 0; col < N; Np--)
+    {
+      for (row = 0; row < Np; row++)
+	for (col = row+1; col < Np; col++)
+	  if (mx[row][col] < min)
+	    i = row;
+      tree[Np-2].left = coord[i];
+    }
+  Free2DArray((void **) mx, N);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr54009.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr54009.c
new file mode 100644
index 000000000..9af98ab6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr54009.c
@@ -0,0 +1,43 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\[\+\]32768" } } */
+
+/* -O2 -m32 store to x.d in w was
+    lis 9,x+32764@ha
+    stw 10,x+32764@l(9)
+    stw 11,x+32768@l(9)  <--  wrap!  */
+
+struct big {
+  char a[32764];
+  double d __attribute__ ((aligned (4)));
+} __attribute__ ((packed));
+
+extern struct big x;
+double y;
+
+void r (void)
+{
+  double tmp = x.d;
+#if 1
+  asm ("#": "+r" (tmp)
+       : : "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
+           "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
+           "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
+           "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31");
+#endif
+  y = tmp;
+}
+
+void w (void)
+{
+  double tmp = y;
+#if 1
+  asm ("#": "+r" (tmp)
+       : : "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
+           "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
+           "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
+           "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31");
+#endif
+  x.d = tmp;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr54240.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr54240.c
new file mode 100644
index 000000000..3e67fd578
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr54240.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -misel -fdump-tree-phiopt-details" } */
+
+typedef struct s {
+  int v;
+  int b;
+  struct s *l;
+  struct s *r;
+} S;
+
+
+int foo(S *s)
+{
+  S *this;
+  S *next;
+
+  this = s;
+  if (this->b)
+    next = this->l;
+  else
+    next = this->r;
+
+  return next->v;
+}
+
+/* { dg-final { scan-tree-dump "Hoisting adjacent loads" "phiopt1" } } */
+/* { dg-final { cleanup-tree-dump "phiopt1" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr55033.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr55033.c
new file mode 100644
index 000000000..fcc6bfced
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr55033.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_eabi_ok } */
+/* { dg-options "-mcpu=8540 -msoft-float -meabi -msdata=eabi -G 8 -fno-common" } */
+
+extern void f (void);
+
+struct s
+{
+  int *p;
+  int *q;
+};
+
+extern int a;
+
+extern const struct s c;
+
+const struct s c = { &a, 0 };
+
+void
+f (void)
+{
+  char buf[4] = { 0, 1, 2, 3 };
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr56256.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr56256.c
new file mode 100644
index 000000000..6c9501a86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr56256.c
@@ -0,0 +1,11 @@
+/* PR target/56256 */
+/* { dg-do assemble } */
+/* { dg-options "-O2" } */
+
+int
+foo (void)
+{
+  int a;
+  __asm__ ("{lil|li} %0,%1" : "=r" (a) : "I" (26));
+  return a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr56605.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr56605.c
new file mode 100644
index 000000000..7e5af449d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr56605.c
@@ -0,0 +1,13 @@
+/* PR rtl-optimization/56605 */
+/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */
+/* { dg-options "-O3 -mvsx -mcpu=power7 -fno-unroll-loops -fdump-rtl-loop2_doloop" } */
+
+void foo (short* __restrict sb, int* __restrict ia)
+{
+  int i;
+  for (i = 0; i < 4000; i++)
+    ia[i] = (int) sb[i];
+}
+
+/* { dg-final { scan-rtl-dump-times "\\\(compare:CC \\\(subreg:SI \\\(reg:DI" 1 "loop2_doloop" } } */
+/* { dg-final { cleanup-rtl-dump "loop2_doloop" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57150.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57150.c
new file mode 100644
index 000000000..119bc4c52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57150.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7 -fcaller-saves" } */
+/* { dg-final { scan-assembler-not "lxvd2x" } } */
+/* { dg-final { scan-assembler-not "lxvw4x" } } */
+/* { dg-final { scan-assembler-not "lvx" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+/* { dg-final { scan-assembler-not "stxvw4x" } } */
+/* { dg-final { scan-assembler-not "stvx" } } */
+
+/* Insure caller save on long double does not use VSX instructions.  */
+
+extern long double modify (long double);
+
+void
+sum (long double *ptr, long double value, unsigned long n)
+{
+  unsigned long i;
+
+  for (i = 0; i < n; i++)
+    ptr[i] += modify (value);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57363.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57363.c
new file mode 100644
index 000000000..45ea3f3fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57363.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { powerpc*-*-linux* } } } */
+/* { dg-options "-mlong-double-128" } */
+
+/* Check if adding a qNAN and a normal long double does not generate a
+   inexact exception.  */
+
+#define _GNU_SOURCE
+#include <fenv.h>
+
+int main(void)
+{
+  double x = __builtin_nan ("");
+  long double y = 1.1L;
+
+  feenableexcept (FE_INEXACT);
+  feclearexcept (FE_ALL_EXCEPT);
+  x = x + y;
+  return fetestexcept(FE_INEXACT);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57744.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57744.c
new file mode 100644
index 000000000..222fd6abd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57744.c
@@ -0,0 +1,39 @@
+/* { dg-do run { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+void abort (void);
+
+typedef unsigned U_16 __attribute__((mode(TI)));
+
+extern int libat_compare_exchange_16 (U_16 *, U_16 *, U_16, int, int)
+  __attribute__((__noinline__));
+
+/* PR 57744: lqarx/stqcx needs even/odd register pairs.  The assembler will
+   complain if the compiler gets an odd/even register pair.  Create a function
+   which has the 16 byte compare and exchange instructions, but don't actually
+   execute it, so that we can detect these failures on older machines. */
+
+int
+libat_compare_exchange_16 (U_16 *mptr, U_16 *eptr, U_16 newval,
+         int smodel, int fmodel __attribute__((unused)))
+{
+  if (((smodel) == 0))
+    return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 0, 0);
+  else if (((smodel) != 5))
+    return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 4, 0);
+  else
+    return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 5, 0);
+}
+
+U_16 a = 1, b = 1, c = -2;
+volatile int do_test = 0;
+
+int main (void)
+{
+  if (do_test && !libat_compare_exchange_16 (&a, &b, c, 0, 0))
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57949-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57949-1.c
new file mode 100644
index 000000000..c2eecea1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57949-1.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Verify that vs is 16-byte aligned in the absence of -mcompat-align-parm.  */
+
+typedef float v4sf __attribute__ ((vector_size (16)));
+struct s { long m; v4sf v; };
+long n;
+v4sf ve;
+
+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,
+	      long d7, long d8, long d9, struct s vs) {
+  n = vs.m;
+  ve = vs.v;
+}
+
+/* { dg-final { scan-assembler "li \.\*,144" } } */
+/* { dg-final { scan-assembler "ld \.\*,128\\(1\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57949-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57949-2.c
new file mode 100644
index 000000000..e5ad212f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr57949-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */
+/* { dg-options "-O2 -mcpu=power7 -mcompat-align-parm" } */
+
+/* Verify that vs is not 16-byte aligned with -mcompat-align-parm.  */
+
+typedef float v4sf __attribute__ ((vector_size (16)));
+struct s { long m; v4sf v; };
+long n;
+v4sf ve;
+
+void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6,
+	      long d7, long d8, long d9, struct s vs) {
+  n = vs.m;
+  ve = vs.v;
+}
+
+/* { dg-final { scan-assembler "ld .\*,136\\(1\\)" } } */
+/* { dg-final { scan-assembler "ld .\*,120\\(1\\)" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58330.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58330.c
new file mode 100644
index 000000000..76983dd55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58330.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O -mno-popcntb" } */
+/* { dg-final { scan-assembler-not "stwbrx" } } */
+
+void
+write_reverse (unsigned long *addr, unsigned long val)
+{
+  unsigned long reverse = __builtin_bswap64 (val);
+  __atomic_store_n (addr, reverse, __ATOMIC_RELAXED);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58673-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58673-1.c
new file mode 100644
index 000000000..6f7838f8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58673-1.c
@@ -0,0 +1,78 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -m64 -O1" } */
+
+enum typecode
+{
+  QIcode, QUcode, HIcode, HUcode, SIcode, SUcode, DIcode, DUcode, SFcode,
+    DFcode, XFcode, Pcode, Tcode, LAST_AND_UNUSED_TYPECODE
+};
+enum bytecode_opcode
+{
+  neverneverland, drop, duplicate, over, setstackSI, adjstackSI, constQI,
+    constHI, constSI, constDI, constSF, constDF, constXF, constP, loadQI,
+    loadHI, loadSI, loadDI, loadSF, loadDF, loadXF, loadP, storeQI, storeHI,
+    storeSI, storeDI, storeSF, storeDF, storeXF, storeP, storeBLK, clearBLK,
+    addconstPSI, newlocalSI, localP, argP, convertQIHI, convertHISI,
+    convertSIDI, convertQISI, convertQUHU, convertHUSU, convertSUDU,
+    convertQUSU, convertSFDF, convertDFXF, convertHIQI, convertSIHI,
+    convertDISI, convertSIQI, convertSUQU, convertDFSF, convertXFDF,
+    convertSISF, convertSIDF, convertSIXF, convertSUSF, convertSUDF,
+    convertSUXF, convertDISF, convertDIDF, convertDIXF, convertDUSF,
+    convertDUDF, convertDUXF, convertSFSI, convertDFSI, convertXFSI,
+    convertSFSU, convertDFSU, convertXFSU, convertSFDI, convertDFDI,
+    convertXFDI, convertSFDU, convertDFDU, convertXFDU, convertPSI,
+    convertSIP, convertSIT, convertDIT, convertSFT, convertDFT, convertXFT,
+    convertPT, zxloadBI, sxloadBI, sstoreBI, addSI, addDI, addSF, addDF,
+    addXF, addPSI, subSI, subDI, subSF, subDF, subXF, subPP, mulSI, mulDI,
+    mulSU, mulDU, mulSF, mulDF, mulXF, divSI, divDI, divSU, divDU, divSF,
+    divDF, divXF, modSI, modDI, modSU, modDU, andSI, andDI, iorSI, iorDI,
+    xorSI, xorDI, lshiftSI, lshiftSU, lshiftDI, lshiftDU, rshiftSI, rshiftSU,
+    rshiftDI, rshiftDU, ltSI, ltSU, ltDI, ltDU, ltSF, ltDF, ltXF, ltP, leSI,
+    leSU, leDI, leDU, leSF, leDF, leXF, leP, geSI, geSU, geDI, geDU, geSF,
+    geDF, geXF, geP, gtSI, gtSU, gtDI, gtDU, gtSF, gtDF, gtXF, gtP, eqSI,
+    eqDI, eqSF, eqDF, eqXF, eqP, neSI, neDI, neSF, neDF, neXF, neP, negSI,
+    negDI, negSF, negDF, negXF, notSI, notDI, notT, predecQI, predecHI,
+    predecSI, predecDI, predecP, predecSF, predecDF, predecXF, predecBI,
+    preincQI, preincHI, preincSI, preincDI, preincP, preincSF, preincDF,
+    preincXF, preincBI, postdecQI, postdecHI, postdecSI, postdecDI, postdecP,
+    postdecSF, postdecDF, postdecXF, postdecBI, postincQI, postincHI,
+    postincSI, postincDI, postincP, postincSF, postincDF, postincXF,
+    postincBI, xjumpif, xjumpifnot, jump, jumpP, caseSI, caseSU, caseDI,
+    caseDU, call, returnP, ret, linenote, LAST_AND_UNUSED_OPCODE
+};
+struct binary_operator
+{
+  enum bytecode_opcode opcode;
+  enum typecode arg0;
+};
+static struct conversion_recipe
+{
+  unsigned char *opcodes;
+  int cost;
+}
+conversion_recipe[((int) LAST_AND_UNUSED_TYPECODE)][((int)
+						     LAST_AND_UNUSED_TYPECODE)];
+static struct conversion_recipe
+deduce_conversion (from, to)
+     enum typecode from, to;
+{
+  (conversion_recipe[(int) from][(int) to].
+   opcodes ? 0 : (conversion_recipe[(int) from][(int) to] =
+		  deduce_conversion (from, to), 0));
+}
+
+void
+bc_expand_binary_operation (optab, resulttype, arg0, arg1)
+     struct binary_operator optab[];
+{
+  int i, besti, cost, bestcost;
+  enum typecode resultcode, arg0code;
+  for (i = 0; optab[i].opcode != -1; ++i)
+    {
+      (conversion_recipe[(int) arg0code][(int) optab[i].arg0].
+       opcodes ? 0 : (conversion_recipe[(int) arg0code][(int) optab[i].arg0] =
+		      deduce_conversion (arg0code, optab[i].arg0), 0));
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58673-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58673-2.c
new file mode 100644
index 000000000..b70d2eed8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr58673-2.c
@@ -0,0 +1,217 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3 -m64 -funroll-loops" } */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include <math.h>
+#include <string.h>
+
+typedef long unsigned int size_t;
+typedef struct _IO_FILE FILE;
+typedef float real;
+typedef real rvec[3];
+typedef real matrix[3][3];
+typedef real tensor[3][3];
+enum
+{
+  F_BONDS, F_G96BONDS, F_MORSE, F_CUBICBONDS, F_CONNBONDS, F_HARMONIC,
+    F_ANGLES, F_G96ANGLES, F_PDIHS, F_RBDIHS, F_IDIHS, F_LJ14, F_COUL14, F_LJ,
+    F_BHAM, F_LJLR, F_DISPCORR, F_SR, F_LR, F_WPOL, F_POSRES, F_DISRES,
+    F_DISRESVIOL, F_ORIRES, F_ORIRESDEV, F_ANGRES, F_ANGRESZ, F_SHAKE,
+    F_SHAKENC, F_SETTLE, F_DUMMY2, F_DUMMY3, F_DUMMY3FD, F_DUMMY3FAD,
+    F_DUMMY3OUT, F_DUMMY4FD, F_EQM, F_EPOT, F_EKIN, F_ETOT, F_TEMP, F_PRES,
+    F_DVDL, F_DVDLKIN, F_NRE
+};
+typedef union
+{
+  struct
+  {
+  }
+  bham;
+  struct
+  {
+    real rA, krA, rB, krB;
+  }
+  harmonic;
+}
+t_iparams;
+typedef struct
+{
+  t_iparams *iparams;
+}
+t_idef;
+typedef struct
+{
+}
+t_inputrec;
+typedef struct
+{
+}
+t_commrec;
+typedef struct
+{
+}
+t_forcerec;
+typedef struct
+{
+}
+t_mdatoms;
+typedef struct
+{
+}
+t_filenm;
+enum
+{
+  eoPres, eoEpot, eoVir, eoDist, eoMu, eoForce, eoFx, eoFy, eoFz, eoPx, eoPy,
+    eoPz, eoPolarizability, eoDipole, eoObsNR, eoMemory =
+    eoObsNR, eoInter, eoUseVirial, eoNR
+};
+extern char *eoNames[eoNR];
+typedef struct
+{
+  int bPrint;
+}
+t_coupl_LJ;
+typedef struct
+{
+  int eObs;
+  t_iparams xi;
+}
+t_coupl_iparams;
+typedef struct
+{
+  real act_value[eoObsNR];
+  real av_value[eoObsNR];
+  real ref_value[eoObsNR];
+  int bObsUsed[eoObsNR];
+  int nLJ, nBU, nQ, nIP;
+  t_coupl_LJ *tcLJ;
+}
+t_coupl_rec;
+static void
+pr_ff (t_coupl_rec * tcr, real time, t_idef * idef, t_commrec * cr, int nfile,
+       t_filenm fnm[])
+{
+  static FILE *prop;
+  static FILE **out = ((void *) 0);
+  static FILE **qq = ((void *) 0);
+  static FILE **ip = ((void *) 0);
+  char buf[256];
+  char *leg[] = {
+    "C12", "C6"
+  };
+  char **raleg;
+  int i, j, index;
+  if ((prop == ((void *) 0)) && (out == ((void *) 0)) && (qq == ((void *) 0))
+      && (ip == ((void *) 0)))
+    {
+      for (i = j = 0; (i < eoObsNR); i++)
+	{
+	  if (tcr->bObsUsed[i])
+	    {
+	      raleg[j++] =
+		(__extension__
+		 (__builtin_constant_p (eoNames[i])
+		  && ((size_t) (const void *) ((eoNames[i]) + 1) -
+		      (size_t) (const void *) (eoNames[i]) ==
+		      1) ? (((const char *) (eoNames[i]))[0] ==
+			    '\0' ? (char *) calloc ((size_t) 1,
+						    (size_t) 1) : (
+									   {
+									   size_t
+									   __len
+									   =
+									   strlen
+									   (eoNames
+									    [i])
+									   +
+									   1;
+									   char
+									   *__retval
+									   =
+									   (char
+									    *)
+									   malloc
+									   (__len);
+									   __retval;}
+	    )):	    __strdup (eoNames[i])));
+	      raleg[j++] =
+		(__extension__
+		 (__builtin_constant_p (buf)
+		  && ((size_t) (const void *) ((buf) + 1) -
+		      (size_t) (const void *) (buf) ==
+		      1) ? (((const char *) (buf))[0] ==
+			    '\0' ? (char *) calloc ((size_t) 1,
+						    (size_t) 1) : (
+									   {
+									   size_t
+									   __len
+									   =
+									   strlen
+									   (buf)
+									   +
+									   1;
+									   char
+									   *__retval
+									   =
+									   (char
+									    *)
+									   malloc
+									   (__len);
+									   __retval;}
+	    )):	    __strdup (buf)));
+	    }
+	}
+      if (tcr->nLJ)
+	{
+	  for (i = 0; (i < tcr->nLJ); i++)
+	    {
+	      if (tcr->tcLJ[i].bPrint)
+		{
+		  xvgr_legend (out[i], (sizeof (leg) / sizeof ((leg)[0])),
+			       leg);
+		}
+	    }
+	}
+    }
+}
+
+void
+do_coupling (FILE * log, int nfile, t_filenm fnm[], t_coupl_rec * tcr, real t,
+	     int step, real ener[], t_forcerec * fr, t_inputrec * ir,
+	     int bMaster, t_mdatoms * md, t_idef * idef, real mu_aver,
+	     int nmols, t_commrec * cr, matrix box, tensor virial,
+	     tensor pres, rvec mu_tot, rvec x[], rvec f[], int bDoIt)
+{
+  int i, j, ati, atj, atnr2, type, ftype;
+  real deviation[eoObsNR], prdev[eoObsNR], epot0, dist, rmsf;
+  real ff6, ff12, ffa, ffb, ffc, ffq, factor, dt, mu_ind;
+  int bTest, bPrint;
+  t_coupl_iparams *tip;
+  if (bPrint)
+    {
+      pr_ff (tcr, t, idef, cr, nfile, fnm);
+    }
+  for (i = 0; (i < eoObsNR); i++)
+    {
+      deviation[i] =
+	calc_deviation (tcr->av_value[i], tcr->act_value[i],
+			tcr->ref_value[i]);
+      prdev[i] = tcr->ref_value[i] - tcr->act_value[i];
+    }
+  if (bPrint)
+    pr_dev (tcr, t, prdev, cr, nfile, fnm);
+  for (i = 0; (i < atnr2); i++)
+    {
+      factor = dt * deviation[tip->eObs];
+      switch (ftype)
+	{
+	case F_BONDS:
+	  if (fabs (tip->xi.harmonic.krA) > 1.2e-38)
+	    idef->iparams[type].harmonic.krA *=
+	      (1 + factor / tip->xi.harmonic.krA);
+	}
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr59054.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr59054.c
new file mode 100644
index 000000000..052f238ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr59054.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O0 -m64" } */
+
+long foo (void) { return 0; }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60032.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60032.c
new file mode 100644
index 000000000..e1115b817
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60032.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O2" } */
+
+void foo (void)
+{
+  register float __attribute__ ((mode(SD))) r31 __asm__ ("r31");
+  register float __attribute__ ((mode(SD))) fr1 __asm__ ("fr1");
+
+  __asm__ ("#" : "=d" (fr1));
+  r31 = fr1;
+  __asm__ ("#" : : "r" (r31));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60137.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60137.c
new file mode 100644
index 000000000..4777a5382
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60137.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */
+
+/* target/60137, compiler got a 'could not split insn error'.  */
+
+extern int target_flags;
+extern char fixed_regs[53];
+extern char call_used_regs[53];
+
+void init_reg_sets_1(void)
+{
+  int i;
+  for (i = 0; i < 53; i++)
+    fixed_regs[i] = call_used_regs[i] = (call_used_regs[i] &((target_flags & 0x02000000) ? 2 : 1)) != 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60203.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60203.c
new file mode 100644
index 000000000..6a4b4fa1d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/pr60203.c
@@ -0,0 +1,40 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -O3" } */
+
+union u_ld { long double ld; double d[2]; };
+
+long double
+pack (double a, double aa)
+{
+  union u_ld u;
+  u.d[0] = a;
+  u.d[1] = aa;
+  return u.ld;
+}
+
+double
+unpack_0 (long double x)
+{
+  union u_ld u;
+  u.ld = x;
+  return u.d[0];
+}
+
+double
+unpack_1 (long double x)
+{
+  union u_ld u;
+  u.ld = x;
+  return u.d[1];
+}
+
+/* { dg-final { scan-assembler-not "stfd"   } } */
+/* { dg-final { scan-assembler-not "lfd"    } } */
+/* { dg-final { scan-assembler-not "lxsdx"  } } */
+/* { dg-final { scan-assembler-not "stxsdx" } } */
+/* { dg-final { scan-assembler-not "mfvsrd" } } */
+/* { dg-final { scan-assembler-not "mtvsrd" } } */
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/quad-atomic.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/quad-atomic.c
new file mode 100644
index 000000000..6cf278852
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/quad-atomic.c
@@ -0,0 +1,67 @@
+/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target p8vector_hw } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+/* Test whether we get the right bits for quad word atomic instructions.  */
+#include <stdlib.h>
+
+static __int128_t quad_fetch_and (__int128_t *, __int128_t value) __attribute__((__noinline__));
+static __int128_t quad_fetch_or  (__int128_t *, __int128_t value) __attribute__((__noinline__));
+static __int128_t quad_fetch_add (__int128_t *, __int128_t value) __attribute__((__noinline__));
+
+static __int128_t
+quad_fetch_and (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+static __int128_t
+quad_fetch_or (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_or (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+static __int128_t
+quad_fetch_add (__int128_t *ptr, __int128_t value)
+{
+  return __atomic_fetch_add (ptr, value, __ATOMIC_ACQUIRE);
+}
+
+int
+main (void)
+{
+  __int128_t result;
+  __int128_t value;
+  __int128_t and_input	= ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));
+  __int128_t and_value	= ((((__int128_t) 0xfffffffffffffff0ULL) << 64) | ((__int128_t) 0xfffffffffffffff0ULL));
+  __int128_t and_exp	= ((((__int128_t) 0x1234567890abcde0ULL) << 64) | ((__int128_t) 0xfedcba0987654320ULL));
+
+  __int128_t or_input	= ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));
+  __int128_t or_value	= ((((__int128_t) 0x0000000000000010ULL) << 64) | ((__int128_t) 0x000000000000000eULL));
+  __int128_t or_exp	= ((((__int128_t) 0x1234567890abcdffULL) << 64) | ((__int128_t) 0xfedcba098765432fULL));
+
+  __int128_t add_input	= ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL));
+  __int128_t add_value	= ((((__int128_t) 0x0000000001000000ULL) << 64) | ((__int128_t) 0x0000001000000000ULL));
+  __int128_t add_exp	= ((((__int128_t) 0x1234567891abcdefULL) << 64) | ((__int128_t) 0xfedcba1987654321ULL));
+
+
+  value = and_input;
+  result = quad_fetch_and (&value, and_value);
+  if (result != and_input || value != and_exp)
+    abort ();
+
+  value = or_input;
+  result = quad_fetch_or (&value, or_value);
+  if (result != or_input || value != or_exp)
+    abort ();
+
+  value = add_input;
+  result = quad_fetch_add (&value, add_value);
+  if (result != add_input || value != add_exp)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-1.c
new file mode 100644
index 000000000..59660e35b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power6" } */
+/* { dg-final { scan-assembler-times "frsqrte" 2 } } */
+/* { dg-final { scan-assembler-times "fmsub" 2 } } */
+/* { dg-final { scan-assembler-times "fmul" 6 } } */
+/* { dg-final { scan-assembler-times "fnmsub" 3 } } */
+
+double
+rsqrt_d (double a)
+{
+  return 1.0 / __builtin_sqrt (a);
+}
+
+float
+rsqrt_f (float a)
+{
+  return 1.0f / __builtin_sqrtf (a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-2.c
new file mode 100644
index 000000000..5c9fbbda5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-2.c
@@ -0,0 +1,22 @@
+/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power5" } */
+/* { dg-final { scan-assembler-times "frsqrtes" 1 } } */
+/* { dg-final { scan-assembler-times "fmsubs" 1 } } */
+/* { dg-final { scan-assembler-times "fmuls" 6 } } */
+/* { dg-final { scan-assembler-times "fnmsubs" 3 } } */
+/* { dg-final { scan-assembler-times "fsqrt" 1 } } */
+
+/* power5 resqrte is not accurate enough, and should not be generated by
+   default for -mrecip.  */
+double
+rsqrt_d (double a)
+{
+  return 1.0 / __builtin_sqrt (a);
+}
+
+float
+rsqrt_f (float a)
+{
+  return 1.0f / __builtin_sqrtf (a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-3.c
new file mode 100644
index 000000000..1f8e30572
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-3.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target { { powerpc*-*-* } && { ! powerpc*-apple-darwin* } } } } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O2 -mrecip -ffast-math -mcpu=power7" } */
+/* { dg-final { scan-assembler-times "xsrsqrtedp\|frsqrte\ " 1 } } */
+/* { dg-final { scan-assembler-times "xsmsub.dp\|fmsub\ " 1 } } */
+/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 4 } } */
+/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 2 } } */
+/* { dg-final { scan-assembler-times "xsrsqrtesp\|frsqrtes" 1 } } */
+/* { dg-final { scan-assembler-times "xsmsub.sp\|fmsubs" 1 } } */
+/* { dg-final { scan-assembler-times "xsmulsp\|fmuls" 2 } } */
+/* { dg-final { scan-assembler-times "xsnmsub.sp\|fnmsubs" 1 } } */
+
+double
+rsqrt_d (double a)
+{
+  return 1.0 / __builtin_sqrt (a);
+}
+
+float
+rsqrt_f (float a)
+{
+  return 1.0f / __builtin_sqrtf (a);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-4.c
new file mode 100644
index 000000000..a62b60db2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-4.c
@@ -0,0 +1,37 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_fprs } */
+/* { dg-options "-O3 -ftree-vectorize -mrecip -ffast-math -mcpu=power7 -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "xvrsqrtedp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsub.dp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmuldp" 4 } } */
+/* { dg-final { scan-assembler-times "xvnmsub.dp" 2 } } */
+/* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsub.sp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmulsp" 2 } } */
+/* { dg-final { scan-assembler-times "xvnmsub.sp" 1 } } */
+
+#define SIZE 1024
+
+extern double a_d[SIZE] __attribute__((__aligned__(32)));
+extern double b_d[SIZE] __attribute__((__aligned__(32)));
+
+void
+vectorize_rsqrt_d (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a_d[i] = 1.0 / __builtin_sqrt (b_d[i]);
+}
+
+extern float a_f[SIZE] __attribute__((__aligned__(32)));
+extern float b_f[SIZE] __attribute__((__aligned__(32)));
+
+void
+vectorize_rsqrt_f (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a_f[i] = 1.0f / __builtin_sqrtf (b_f[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-5.c
new file mode 100644
index 000000000..11d125c11
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-5.c
@@ -0,0 +1,104 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -ftree-vectorize -mrecip=all -ffast-math -mcpu=power7 -fno-unroll-loops" } */
+/* { dg-final { scan-assembler-times "xvredp" 4 } } */
+/* { dg-final { scan-assembler-times "xvresp" 5 } } */
+/* { dg-final { scan-assembler-times "xsredp\|fre\ " 2 } } */
+/* { dg-final { scan-assembler-times "fres\|xsresp" 2 } } */
+/* { dg-final { scan-assembler-times "fmuls\|xsmulsp" 2 } } */
+/* { dg-final { scan-assembler-times "fnmsubs\|xsnmsub.sp" 2 } } */
+/* { dg-final { scan-assembler-times "xsmuldp\|fmul\ " 2 } } */
+/* { dg-final { scan-assembler-times "xsnmsub.dp\|fnmsub\ " 4 } } */
+/* { dg-final { scan-assembler-times "xvmulsp" 7 } } */
+/* { dg-final { scan-assembler-times "xvnmsub.sp" 5 } } */
+/* { dg-final { scan-assembler-times "xvmuldp" 6 } } */
+/* { dg-final { scan-assembler-times "xvnmsub.dp" 8 } } */
+
+#include <altivec.h>
+
+float f_recip (float a, float b) { return __builtin_recipdivf (a, b); }
+double d_recip (double a, double b) { return __builtin_recipdiv (a, b); }
+
+float f_div (float a, float b) { return a / b; }
+double d_div (double a, double b) { return a / b; }
+
+#define SIZE 1024
+
+double d_a[SIZE] __attribute__((__aligned__(32)));
+double d_b[SIZE] __attribute__((__aligned__(32)));
+double d_c[SIZE] __attribute__((__aligned__(32)));
+
+float f_a[SIZE] __attribute__((__aligned__(32)));
+float f_b[SIZE] __attribute__((__aligned__(32)));
+float f_c[SIZE] __attribute__((__aligned__(32)));
+
+void vec_f_recip (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f_a[i] = __builtin_recipdivf (f_b[i], f_c[i]);
+}
+
+void vec_d_recip (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d_a[i] = __builtin_recipdiv (d_b[i], d_c[i]);
+}
+
+void vec_f_div (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f_a[i] = f_b[i] / f_c[i];
+}
+
+void vec_f_div2 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f_a[i] = f_b[i] / 2.0f;
+}
+
+void vec_f_div53 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f_a[i] = f_b[i] / 53.0f;
+}
+
+void vec_d_div (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d_a[i] = d_b[i] / d_c[i];
+}
+
+void vec_d_div2 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d_a[i] = d_b[i] / 2.0;
+}
+
+void vec_d_div53 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d_a[i] = d_b[i] / 53.0;
+}
+
+vector float v4sf_recip1 (vector float a, vector float b) { return vec_recipdiv (a, b); }
+vector float v4sf_recip2 (vector float a, vector float b) { return __builtin_altivec_vrecipdivfp (a, b); }
+vector double v2df_recip1 (vector double a, vector double b) { return vec_recipdiv (a, b); }
+vector float v4sf_recip3 (vector float a, vector float b) { return __builtin_vsx_xvrecipdivsp (a, b); }
+vector double v2df_recip2 (vector double a, vector double b) { return __builtin_vsx_xvrecipdivdp (a, b); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-6.c
new file mode 100644
index 000000000..7d71df670
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-6.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target vsx_hw } */
+/* { dg-options "-mcpu=power7 -O3 -ftree-vectorize -ffast-math -mrecip=all -mrecip-precision" } */
+
+/* Check reciprocal estimate functions for accuracy.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <math.h>
+#include <float.h>
+#include <string.h>
+
+#include "recip-test.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-7.c
new file mode 100644
index 000000000..7b32ba076
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-7.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */
+/* { dg-require-effective-target ppc_recip_hw } */
+/* { dg-options "-O3 -ftree-vectorize -ffast-math -mrecip -mpowerpc-gfxopt -mpowerpc-gpopt -mpopcntb" } */
+
+/* Check reciprocal estimate functions for accuracy.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <math.h>
+#include <float.h>
+#include <string.h>
+
+#include "recip-test.h"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-test.h b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-test.h
new file mode 100644
index 000000000..7a42df575
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-test.h
@@ -0,0 +1,149 @@
+/* Check reciprocal estimate functions for accuracy.  */
+
+#ifdef _ARCH_PPC64
+typedef unsigned long uns64_t;
+#define UNUM64(x) x ## L
+
+#else
+typedef unsigned long long uns64_t;
+#define UNUM64(x) x ## LL
+#endif
+
+typedef unsigned int uns32_t;
+
+#define TNAME2(x) #x
+#define TNAME(x) TNAME2(x)
+
+/*
+ * Float functions.
+ */
+
+#define TYPE float
+#define NAME(PREFIX) PREFIX ## _float
+#define UNS_TYPE uns32_t
+#define UNS_ABS __builtin_abs
+#define EXP_SIZE 8
+#define MAN_SIZE 23
+#define FABS __builtin_fabsf
+#define FMAX __builtin_fmaxf
+#define FMIN __builtin_fminf
+#define SQRT __builtin_sqrtf
+#define RMIN 1.0e-10
+#define RMAX 1.0e+10
+#define BDIV 1
+#define BRSQRT 2
+#define ASMDIV "fdivs"
+#define ASMSQRT "fsqrts"
+
+#define INIT_DIV							\
+{									\
+  { 0x4fffffff },	/* 8589934080 */				\
+  { 0x4effffff },	/* 2147483520 */				\
+  { 0x40ffffff },	/* 7.99999952316284 */				\
+  { 0x3fffffff },	/* 1.99999988079071 */				\
+  { 0x417fffff },	/* 15.9999990463257 */				\
+  { 0x42ffffff },	/* 127.999992370605 */				\
+  { 0x3dffffff },	/* 0.124999992549419 */				\
+  { 0x3effffff },	/* 0.499999970197678 */				\
+}
+
+#define INIT_RSQRT							\
+{									\
+  { 0x457ffffe },	/* 4096 - small amount */			\
+  { 0x4c7fffff },	/* 6.71089e+07 */				\
+  { 0x3d7fffff },	/* 0.0625 - small amount */			\
+  { 0x307ffffe },	/* 9.31322e-10 */				\
+  { 0x4c7ffffe },	/* 6.71089e+07 */				\
+  { 0x397ffffe },	/* 0.000244141 */				\
+  { 0x2e7fffff },	/* 5.82077e-11 */				\
+  { 0x2f7fffff },	/* 2.32831e-10 */				\
+}
+
+
+#include "recip-test2.h"
+
+/*
+ * Double functions.
+ */
+
+#undef TYPE
+#undef NAME
+#undef UNS_TYPE
+#undef UNS_ABS
+#undef EXP_SIZE
+#undef MAN_SIZE
+#undef FABS
+#undef FMAX
+#undef FMIN
+#undef SQRT
+#undef RMIN
+#undef RMAX
+#undef BDIV
+#undef BRSQRT
+#undef ASMDIV
+#undef ASMSQRT
+#undef INIT_DIV
+#undef INIT_RSQRT
+
+#define TYPE double
+#define NAME(PREFIX) PREFIX ## _double
+#define UNS_TYPE uns64_t
+#define UNS_ABS __builtin_imaxabs
+#define EXP_SIZE 11
+#define MAN_SIZE 52
+#define FABS __builtin_fabs
+#define FMAX __builtin_fmax
+#define FMIN __builtin_fmin
+#define SQRT __builtin_sqrt
+#define RMIN 1.0e-100
+#define RMAX 1.0e+100
+#define BDIV 1
+#define BRSQRT 2
+#define ASMDIV "fdiv"
+#define ASMSQRT "fsqrt"
+
+#define INIT_DIV							\
+{									\
+  { UNUM64 (0x2b57be53f2a2f3a0) },	/* 6.78462e-100 */		\
+  { UNUM64 (0x2b35f8e8ea553e52) },	/* 1.56963e-100 */		\
+  { UNUM64 (0x2b5b9d861d2fe4fb) },	/* 7.89099e-100 */		\
+  { UNUM64 (0x2b45dc44a084e682) },	/* 3.12327e-100 */		\
+  { UNUM64 (0x2b424ce16945d777) },	/* 2.61463e-100 */		\
+  { UNUM64 (0x2b20b5023d496b50) },	/* 5.96749e-101 */		\
+  { UNUM64 (0x2b61170547f57caa) },	/* 9.76678e-100 */		\
+  { UNUM64 (0x2b543b9d498aac37) },	/* 5.78148e-100 */		\
+}
+
+#define INIT_RSQRT							\
+{									\
+  { UNUM64 (0x2b616f2d8cbbc646) },	/* 9.96359e-100 */		\
+  { UNUM64 (0x2b5c4db2da0a011d) },	/* 8.08764e-100 */		\
+  { UNUM64 (0x2b55a82d5735b262) },	/* 6.1884e-100 */		\
+  { UNUM64 (0x2b50b52908258cb8) },	/* 4.77416e-100 */		\
+  { UNUM64 (0x2b363989a4fb29af) },	/* 1.58766e-100 */		\
+  { UNUM64 (0x2b508b9f6f4180a9) },	/* 4.7278e-100 */		\
+  { UNUM64 (0x2b4f7a1d48accb40) },	/* 4.49723e-100 */		\
+  { UNUM64 (0x2b1146a37372a81f) },	/* 3.08534e-101 */		\
+  { UNUM64 (0x2b33f876a8c48050) },	/* 1.42663e-100 */		\
+}
+
+#include "recip-test2.h"
+
+int
+main (int argc __attribute__((__unused__)),
+      char *argv[] __attribute__((__unused__)))
+{
+  srand48 (1);
+  run_float ();
+
+#ifdef VERBOSE
+  printf ("\n");
+#endif
+
+  run_double ();
+
+  if (error_count_float != 0 || error_count_double != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-test2.h b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-test2.h
new file mode 100644
index 000000000..3ec356cdf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/recip-test2.h
@@ -0,0 +1,432 @@
+/*
+ * Included file to common source float/double checking
+ * The following macros should be defined:
+ *	TYPE	   -- floating point type
+ *	NAME	   -- convert a name to include the type
+ *	UNS_TYPE   -- type to hold TYPE as an unsigned number
+ *	EXP_SIZE   -- size in bits of the exponent
+ *	MAN_SIZE   -- size in bits of the mantissa
+ *	UNS_ABS	   -- absolute value for UNS_TYPE
+ *	FABS	   -- absolute value function for TYPE
+ *	FMAX	   -- maximum function for TYPE
+ *	FMIN	   -- minimum function for TYPE
+ *	SQRT	   -- square root function for TYPE
+ *	RMIN	   -- minimum random number to generate
+ *	RMAX	   -- maximum random number to generate
+ *	ASMDIV	   -- assembler instruction to do divide
+ *	ASMSQRT	   -- assembler instruction to do square root
+ *	BDIV	   -- # of bits of inaccuracy to allow for division
+ *	BRSQRT	   -- # of bits of inaccuracy to allow for 1/sqrt
+ *	INIT_DIV   -- Initial values to test 1/x against
+ *	INIT_RSQRT -- Initial values to test 1/sqrt(x) against
+ */
+
+typedef union
+{
+  UNS_TYPE i;
+  TYPE x;
+} NAME (union);
+
+/*
+ * Input/output arrays.
+ */
+
+static NAME (union) NAME (div_input)  [] __attribute__((__aligned__(32))) = INIT_DIV;
+static NAME (union) NAME (rsqrt_input)[] __attribute__((__aligned__(32))) = INIT_RSQRT;
+
+#define DIV_SIZE   (sizeof (NAME (div_input))   / sizeof (TYPE))
+#define RSQRT_SIZE (sizeof (NAME (rsqrt_input)) / sizeof (TYPE))
+
+static TYPE NAME (div_expected)[DIV_SIZE] __attribute__((__aligned__(32)));
+static TYPE NAME (div_output)  [DIV_SIZE] __attribute__((__aligned__(32)));
+
+static TYPE NAME (rsqrt_expected)[RSQRT_SIZE] __attribute__((__aligned__(32)));
+static TYPE NAME (rsqrt_output)  [RSQRT_SIZE] __attribute__((__aligned__(32)));
+
+
+/*
+ * Crack a floating point number into sign bit, exponent, and mantissa.
+ */
+
+static void
+NAME (crack) (TYPE number, unsigned int *p_sign, unsigned *p_exponent, UNS_TYPE *p_mantissa)
+{
+  NAME (union) u;
+  UNS_TYPE bits;
+
+  u.x = number;
+  bits = u.i;
+
+  *p_sign = (unsigned int)((bits >> (EXP_SIZE + MAN_SIZE)) & 0x1);
+  *p_exponent = (unsigned int)((bits >> MAN_SIZE) & ((((UNS_TYPE)1) << EXP_SIZE) - 1));
+  *p_mantissa = bits & ((((UNS_TYPE)1) << MAN_SIZE) - 1);
+  return;
+}
+
+
+/*
+ * Prevent optimizer from eliminating + 0.0 to remove -0.0.
+ */
+
+volatile TYPE NAME (math_diff_0) = ((TYPE) 0.0);
+
+/*
+ * Return negative if two numbers are significanly different or return the
+ * number of bits that are different in the mantissa.
+ */
+
+static int
+NAME (math_diff) (TYPE a, TYPE b, int bits)
+{
+  TYPE zero = NAME (math_diff_0);
+  unsigned int sign_a, sign_b;
+  unsigned int exponent_a, exponent_b;
+  UNS_TYPE mantissa_a, mantissa_b, diff;
+  int i;
+
+  /* eliminate signed zero.  */
+  a += zero;
+  b += zero;
+
+  /* special case Nan.  */
+  if (__builtin_isnan (a))
+    return (__builtin_isnan (b) ? 0 : -1);
+
+  if (a == b)
+    return 0;
+
+  /* special case infinity.  */
+  if (__builtin_isinf (a))
+    return (__builtin_isinf (b) ? 0 : -1);
+
+  /* punt on denormal numbers.  */
+  if (!__builtin_isnormal (a) || !__builtin_isnormal (b))
+    return -1;
+
+  NAME (crack) (a, &sign_a, &exponent_a, &mantissa_a);
+  NAME (crack) (b, &sign_b, &exponent_b, &mantissa_b);
+
+  /* If the sign is different, there is no hope.  */
+  if (sign_a != sign_b)
+    return -1;
+
+  /* If the exponent is off by 1, see if the values straddle the power of two,
+     and adjust things to do the mantassa check if we can.  */
+  if ((exponent_a == (exponent_b+1)) || (exponent_a == (exponent_b-1)))
+    {
+      TYPE big = FMAX (a, b);
+      TYPE small = FMIN (a, b);
+      TYPE diff = FABS (a - b);
+      unsigned int sign_big, sign_small, sign_test;
+      unsigned int exponent_big, exponent_small, exponent_test;
+      UNS_TYPE mantissa_big, mantissa_small, mantissa_test;
+
+      NAME (crack) (big, &sign_big, &exponent_big, &mantissa_big);
+      NAME (crack) (small, &sign_small, &exponent_small, &mantissa_small);
+
+      NAME (crack) (small - diff, &sign_test, &exponent_test, &mantissa_test);
+      if ((sign_test == sign_small) && (exponent_test == exponent_small))
+	{
+	  mantissa_a = mantissa_small;
+	  mantissa_b = mantissa_test;
+	}
+
+      else
+	{
+	  NAME (crack) (big + diff, &sign_test, &exponent_test, &mantissa_test);
+	  if ((sign_test == sign_big) && (exponent_test == exponent_big))
+	    {
+	      mantissa_a = mantissa_big;
+	      mantissa_b = mantissa_test;
+	    }
+
+	  else
+	    return -1;
+	}
+    }
+
+  else if (exponent_a != exponent_b)
+    return -1;
+
+  diff = UNS_ABS (mantissa_a - mantissa_b);
+  for (i = MAN_SIZE; i > 0; i--)
+    {
+      if ((diff & ((UNS_TYPE)1) << (i-1)) != 0)
+	return i;
+    }
+
+  return -1;
+}
+
+
+/*
+ * Turn off inlining to make code inspection easier.
+ */
+
+static void NAME (asm_div) (void) __attribute__((__noinline__));
+static void NAME (vector_div) (void) __attribute__((__noinline__));
+static void NAME (scalar_div) (void) __attribute__((__noinline__));
+static void NAME (asm_rsqrt) (void) __attribute__((__noinline__));
+static void NAME (vector_rsqrt) (void) __attribute__((__noinline__));
+static void NAME (scalar_rsqrt) (void) __attribute__((__noinline__));
+static void NAME (check_div) (const char *) __attribute__((__noinline__));
+static void NAME (check_rsqrt) (const char *) __attribute__((__noinline__));
+static void NAME (run) (void) __attribute__((__noinline__));
+
+
+/*
+ * Division function that might be vectorized.
+ */
+
+static void
+NAME (vector_div) (void)
+{
+  size_t i;
+
+  for (i = 0; i < DIV_SIZE; i++)
+    NAME (div_output)[i] = ((TYPE) 1.0) / NAME (div_input)[i].x;
+}
+
+/*
+ * Division function that is not vectorized.
+ */
+
+static void
+NAME (scalar_div) (void)
+{
+  size_t i;
+
+  for (i = 0; i < DIV_SIZE; i++)
+    {
+      TYPE x = ((TYPE) 1.0) / NAME (div_input)[i].x;
+      TYPE y;
+      __asm__ ("" : "=d" (y) : "0" (x));
+      NAME (div_output)[i] = y;
+    }
+}
+
+/*
+ * Generate the division instruction via asm.
+ */
+
+static void
+NAME (asm_div) (void)
+{
+  size_t i;
+
+  for (i = 0; i < DIV_SIZE; i++)
+    {
+      TYPE x;
+      __asm__ (ASMDIV " %0,%1,%2"
+	       : "=d" (x)
+	       : "d" ((TYPE) 1.0), "d" (NAME (div_input)[i].x));
+      NAME (div_expected)[i] = x;
+    }
+}
+
+/*
+ * Reciprocal square root function that might be vectorized.
+ */
+
+static void
+NAME (vector_rsqrt) (void)
+{
+  size_t i;
+
+  for (i = 0; i < RSQRT_SIZE; i++)
+    NAME (rsqrt_output)[i] = ((TYPE) 1.0) / SQRT (NAME (rsqrt_input)[i].x);
+}
+
+/*
+ * Reciprocal square root function that is not vectorized.
+ */
+
+static void
+NAME (scalar_rsqrt) (void)
+{
+  size_t i;
+
+  for (i = 0; i < RSQRT_SIZE; i++)
+    {
+      TYPE x = ((TYPE) 1.0) / SQRT (NAME (rsqrt_input)[i].x);
+      TYPE y;
+      __asm__ ("" : "=d" (y) : "0" (x));
+      NAME (rsqrt_output)[i] = y;
+    }
+}
+
+/*
+ * Generate the 1/sqrt instructions via asm.
+ */
+
+static void
+NAME (asm_rsqrt) (void)
+{
+  size_t i;
+
+  for (i = 0; i < RSQRT_SIZE; i++)
+    {
+      TYPE x;
+      TYPE y;
+      __asm__ (ASMSQRT " %0,%1" : "=d" (x) : "d" (NAME (rsqrt_input)[i].x));
+      __asm__ (ASMDIV " %0,%1,%2" : "=d" (y) : "d" ((TYPE) 1.0), "d" (x));
+      NAME (rsqrt_expected)[i] = y;
+    }
+}
+
+
+/*
+ * Functions to abort or report errors.
+ */
+
+static int NAME (error_count) = 0;
+
+#ifdef VERBOSE
+static int NAME (max_bits_div)   = 0;
+static int NAME (max_bits_rsqrt) = 0;
+#endif
+
+
+/*
+ * Compare the expected value with the value we got.
+ */
+
+static void
+NAME (check_div) (const char *test)
+{
+  size_t i;
+  int b;
+
+  for (i = 0; i < DIV_SIZE; i++)
+    {
+      TYPE exp = NAME (div_expected)[i];
+      TYPE out = NAME (div_output)[i];
+      b = NAME (math_diff) (exp, out, BDIV);
+
+#ifdef VERBOSE
+      if (b != 0)
+	{
+	  NAME (union) u_in = NAME (div_input)[i];
+	  NAME (union) u_exp;
+	  NAME (union) u_out;
+	  char explanation[64];
+	  const char *p_exp;
+
+	  if (b < 0)
+	    p_exp = "failed";
+	  else
+	    {
+	      p_exp = explanation;
+	      sprintf (explanation, "%d bit error%s", b, (b > BDIV) ? ", failed" : "");
+	    }
+
+	  u_exp.x = exp;
+	  u_out.x = out;
+	  printf ("%s %s %s for 1.0 / %g [0x%llx], expected %g [0x%llx], got %g [0x%llx]\n",
+		  TNAME (TYPE), test, p_exp,
+		  (double) u_in.x, (unsigned long long) u_in.i,
+		  (double) exp,    (unsigned long long) u_exp.i,
+		  (double) out,    (unsigned long long) u_out.i);
+	}
+#endif
+
+      if (b < 0 || b > BDIV)
+	NAME (error_count)++;
+
+#ifdef VERBOSE
+      if (b > NAME (max_bits_div))
+	NAME (max_bits_div) = b;
+#endif
+    }
+}
+
+static void
+NAME (check_rsqrt) (const char *test)
+{
+  size_t i;
+  int b;
+
+  for (i = 0; i < RSQRT_SIZE; i++)
+    {
+      TYPE exp = NAME (rsqrt_expected)[i];
+      TYPE out = NAME (rsqrt_output)[i];
+      b = NAME (math_diff) (exp, out, BRSQRT);
+
+#ifdef VERBOSE
+      if (b != 0)
+	{
+	  NAME (union) u_in = NAME (rsqrt_input)[i];
+	  NAME (union) u_exp;
+	  NAME (union) u_out;
+	  char explanation[64];
+	  const char *p_exp;
+
+	  if (b < 0)
+	    p_exp = "failed";
+	  else
+	    {
+	      p_exp = explanation;
+	      sprintf (explanation, "%d bit error%s", b, (b > BDIV) ? ", failed" : "");
+	    }
+
+	  u_exp.x = exp;
+	  u_out.x = out;
+	  printf ("%s %s %s for 1 / sqrt (%g) [0x%llx], expected %g [0x%llx], got %g [0x%llx]\n",
+		  TNAME (TYPE), test, p_exp,
+		  (double) u_in.x, (unsigned long long) u_in.i,
+		  (double) exp,    (unsigned long long) u_exp.i,
+		  (double) out,    (unsigned long long) u_out.i);
+	}
+#endif
+
+      if (b < 0 || b > BRSQRT)
+	NAME (error_count)++;
+
+#ifdef VERBOSE
+      if (b > NAME (max_bits_rsqrt))
+	NAME (max_bits_rsqrt) = b;
+#endif
+    }
+}
+
+
+/*
+ * Now do everything.
+ */
+
+static void
+NAME (run) (void)
+{
+#ifdef VERBOSE
+  printf ("start run_%s, divide size = %ld, rsqrt size = %ld, %d bit%s for a/b, %d bit%s for 1/sqrt(a)\n",
+	  TNAME (TYPE),
+	  (long)DIV_SIZE,
+	  (long)RSQRT_SIZE,
+	  BDIV, (BDIV == 1) ? "" : "s",
+	  BRSQRT, (BRSQRT == 1) ? "" : "s");
+#endif
+
+  NAME (asm_div) ();
+
+  NAME (scalar_div) ();
+  NAME (check_div) ("scalar");
+
+  NAME (vector_div) ();
+  NAME (check_div) ("vector");
+
+  NAME (asm_rsqrt) ();
+
+  NAME (scalar_rsqrt) ();
+  NAME (check_rsqrt) ("scalar");
+
+  NAME (vector_rsqrt) ();
+  NAME (check_rsqrt) ("vector");
+
+#ifdef VERBOSE
+  printf ("end run_%s, errors = %d, max div bits = %d, max rsqrt bits = %d\n",
+	  TNAME (TYPE),
+	  NAME (error_count),
+	  NAME (max_bits_div),
+	  NAME (max_bits_rsqrt));
+#endif
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/regnames-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/regnames-1.c
new file mode 100644
index 000000000..e34e6241d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/regnames-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target powerpc*-*-linux* } } */
+/* { dg-options "-mregnames" } */
+
+register double f17 asm ("f17");
+double foo (void)
+{
+  return f17;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rotate.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rotate.c
new file mode 100644
index 000000000..5d47215d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rotate.c
@@ -0,0 +1,6 @@
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "slwi" } } */
+unsigned int foo (unsigned int x)
+{
+  return ((x >> 16) & 0xffff) | ((x & 0xffff) << 16);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c
new file mode 100644
index 000000000..66bb61d25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-darwin* powerpc*-*-linux* } } */
+/* { dg-options "-mno-powerpc-gfxopt -mpowerpc64" } */
+extern void bar (void *);
+extern double x;
+void
+foo (void)
+{
+  char buf2 [32][1024];
+  bar (buf2 [(int) x]);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c
new file mode 100644
index 000000000..410f780de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* rs6000-*-* } } */
+/* { dg-options "-mno-powerpc-gfxopt" } */
+/* { dg-final { scan-assembler-not "stfiwx" } } */
+
+/* A basic test of the old-style (not stfiwx) fp -> int conversion.  */
+int f(double a, double b)
+{
+  int a1 = a;
+  int b1 = b;
+  return a1+b1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c
new file mode 100644
index 000000000..8d474f076
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-1.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } || { powerpc*-*-linux* && lp64 } } } } */
+/* { dg-options "-mlong-double-128" } */
+
+/* Check that long double values are rounded correctly when being converted
+   to 32-bit integers.  All these values are of the form +/- 2 +/- 2^-60.  */
+
+extern void abort(void);
+extern void exit(int);
+
+int main(void)
+{
+  long double l1 = 1.9999999999999999991326382620115964527941L;
+  long double l2 = 2.0000000000000000008673617379884035472059L;
+  long double l3 = -2.0000000000000000008673617379884035472059L;
+  long double l4 = -1.9999999999999999991326382620115964527941L;
+  
+  if ((int) l1 != 1)
+    abort ();
+  if ((int) l2 != 2)
+    abort ();
+  if ((int) l3 != -2)
+    abort ();
+  if ((int) l4 != -1)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c
new file mode 100644
index 000000000..5dc74cd2d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-2.c
@@ -0,0 +1,22 @@
+/* { dg-do run { target { { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } || { powerpc*-*-linux* && lp64 } } } } */
+/* { dg-options "-mlong-double-128" } */
+
+/* Check that LDBL_EPSILON is right for 'long double'.  */
+
+#include <float.h>
+
+extern void abort (void);
+
+int main(void)
+{
+  volatile long double ee = 1.0;
+  long double eps = ee;
+  while (ee + 1.0 != 1.0)
+    {
+      eps = ee;
+      ee = eps / 2;
+    }
+  if (eps != LDBL_EPSILON)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c
new file mode 100644
index 000000000..1c78052e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c
@@ -0,0 +1,21 @@
+/* Test accuracy of long double division (glibc bug 15396).  */
+/* { dg-do run { target powerpc*-*-linux* powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } } */
+/* { dg-options "-mlong-double-128" } */
+
+extern void exit (int);
+extern void abort (void);
+
+volatile long double a = 0x1p-1024L;
+volatile long double b = 0x3p-53L;
+volatile long double r;
+volatile long double expected = 0x1.55555555555555555555555555p-973L;
+
+int
+main (void)
+{
+  r = a / b;
+  /* Allow error up to 2ulp.  */
+  if (__builtin_fabsl (r - expected) > 0x1p-1073L)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/savres.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/savres.c
new file mode 100644
index 000000000..f10c99a4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/savres.c
@@ -0,0 +1,1228 @@
+/* { dg-do run } */
+/* { dg-options "-fno-inline -fomit-frame-pointer" } */
+/* { dg-additional-options "-mdynamic-no-pic" { target *-*-darwin* } } */
+
+/* -fno-inline -maltivec -m32/-m64 -mmultiple/no-multiple -Os/-O2.  */
+#ifndef NO_BODY
+#define abort() __builtin_abort ()
+#define vec_all_eq(v1,v2) __builtin_vec_vcmpeq_p (2, v1, v2)
+#define SET(T,R,V) register T R __asm__ (#R) = V
+#define SET_GPR(R,V) SET (long, R, V)
+#define SET_FPR(R,V) SET (double, R, V)
+#define SET_VR(R,V) SET (__attribute__ ((vector_size (16))) int, R, V)
+#define SET_CR(R,V) __asm__ __volatile__ ("mtcrf %0,%1" : : "n" (1<<(7-R)), "r" (V<<(4*(7-R))) : "cr" #R)
+#define TRASH_GPR(R) SET_GPR (R, 0)
+#define TRASH_FPR(R) SET_FPR (R, 0)
+#define TRASH_VR(R) SET_VR (R, val0)
+#define TRASH_CR(R) SET_CR (R, 0)
+#define TRASH_SOME_GPR TRASH_GPR (r30); TRASH_GPR (r31)
+#define TRASH_SOME_FPR TRASH_FPR (fr28); TRASH_FPR (fr31)
+#define TRASH_SOME_VR TRASH_VR (v26); TRASH_VR (v27); TRASH_VR (v31)
+#define TRASH_SOME_CR TRASH_CR (2)
+#define TRASH_ALL_GPR TRASH_GPR (r14); TRASH_GPR (r15); TRASH_GPR (r16); TRASH_GPR (r17); TRASH_GPR (r18); TRASH_GPR (r19); TRASH_GPR (r20); TRASH_GPR (r21); TRASH_GPR (r22); TRASH_GPR (r23); TRASH_GPR (r24); TRASH_GPR (r25); TRASH_GPR (r26); TRASH_GPR (r27); TRASH_GPR (r28); TRASH_GPR (r29); TRASH_GPR (r30); TRASH_GPR (r31)
+#define TRASH_ALL_FPR TRASH_FPR (fr14); TRASH_FPR (fr15); TRASH_FPR (fr16); TRASH_FPR (fr17); TRASH_FPR (fr18); TRASH_FPR (fr19); TRASH_FPR (fr20); TRASH_FPR (fr21); TRASH_FPR (fr22); TRASH_FPR (fr23); TRASH_FPR (fr24); TRASH_FPR (fr25); TRASH_FPR (fr26); TRASH_FPR (fr27); TRASH_FPR (fr28); TRASH_FPR (fr29); TRASH_FPR (fr30); TRASH_FPR (fr31)
+#define TRASH_ALL_VR TRASH_VR (v20); TRASH_VR (v21); TRASH_VR (v22); TRASH_VR (v23); TRASH_VR (v24); TRASH_VR (v25); TRASH_VR (v26); TRASH_VR (v27); TRASH_VR (v28); TRASH_VR (v29); TRASH_VR (v30); TRASH_VR (v31)
+#define TRASH_ALL_CR TRASH_CR (2); TRASH_CR (3); TRASH_CR (4)
+#define USE_SOME_GPR __asm__ __volatile__ ("#%0 %1" : : "r" (r30), "r" (r31))
+#define USE_SOME_FPR __asm__ __volatile__ ("#%0 %1" : : "f" (fr28), "f" (fr31))
+#define USE_SOME_VR __asm__ __volatile__ ("#%0 %1 %2" : : "v" (v26), "v" (v27), "v" (v31))
+#define USE_SOME_CR
+#define USE_ALL_GPR __asm__ __volatile__ ("#%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17" : : "r" (r14), "r" (r15), "r" (r16), "r" (r17), "r" (r18), "r" (r19), "r" (r20), "r" (r21), "r" (r22), "r" (r23), "r" (r24), "r" (r25), "r" (r26), "r" (r27), "r" (r28), "r" (r29), "r" (r30), "r" (r31))
+#define USE_ALL_FPR __asm__ __volatile__ ("#%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16 %17" : : "f" (fr14), "f" (fr15), "f" (fr16), "f" (fr17), "f" (fr18), "f" (fr19), "f" (fr20), "f" (fr21), "f" (fr22), "f" (fr23), "f" (fr24), "f" (fr25), "f" (fr26), "f" (fr27), "f" (fr28), "f" (fr29), "f" (fr30), "f" (fr31))
+#define USE_ALL_VR __asm__ __volatile__ ("#%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11" : : "v" (v20), "v" (v21), "v" (v22), "v" (v23), "v" (v24), "v" (v25), "v" (v26), "v" (v27), "v" (v28), "v" (v29), "v" (v30), "v" (v31))
+#define USE_ALL_CR
+
+#define INIT_GPR SET_GPR (r14, 14); SET_GPR (r15, 15); SET_GPR (r16, 16); SET_GPR (r17, 17); SET_GPR (r18, 18); SET_GPR (r19, 19); SET_GPR (r20, 20); SET_GPR (r21, 21); SET_GPR (r22, 22); SET_GPR (r23, 23); SET_GPR (r24, 24); SET_GPR (r25, 25); SET_GPR (r26, 26); SET_GPR (r27, 27); SET_GPR (r28, 28); SET_GPR (r29, 29); SET_GPR (r30, 30); SET_GPR (r31, 31)
+#define INIT_FPR SET_FPR (fr14, 140.0); SET_FPR (fr15, 150.0); SET_FPR (fr16, 160.0); SET_FPR (fr17, 170.0); SET_FPR (fr18, 180.0); SET_FPR (fr19, 190.0); SET_FPR (fr20, 200.0); SET_FPR (fr21, 210.0); SET_FPR (fr22, 220.0); SET_FPR (fr23, 230.0); SET_FPR (fr24, 240.0); SET_FPR (fr25, 250.0); SET_FPR (fr26, 260.0); SET_FPR (fr27, 270.0); SET_FPR (fr28, 280.0); SET_FPR (fr29, 290.0); SET_FPR (fr30, 300.0); SET_FPR (fr31, 310.0)
+#define INIT_VR SET_VR (v20, val20); SET_VR (v21, val21); SET_VR (v22, val22); SET_VR (v23, val23); SET_VR (v24, val24); SET_VR (v25, val25); SET_VR (v26, val26); SET_VR (v27, val27); SET_VR (v28, val28); SET_VR (v29, val29); SET_VR (v30, val30); SET_VR (v31, val31)
+#define INIT_CR SET_CR (2, 6); SET_CR (3, 7); SET_CR (4, 8)
+#ifdef __ALTIVEC__
+__attribute__ ((vector_size (16))) int val0 = {0,0,0,0};
+__attribute__ ((vector_size (16))) int val20 = {-201,-202,-203,-204};
+__attribute__ ((vector_size (16))) int val21 = {-211,-212,-213,-214};
+__attribute__ ((vector_size (16))) int val22 = {-221,-222,-223,-224};
+__attribute__ ((vector_size (16))) int val23 = {-231,-232,-233,-234};
+__attribute__ ((vector_size (16))) int val24 = {-241,-242,-243,-244};
+__attribute__ ((vector_size (16))) int val25 = {-251,-252,-253,-254};
+__attribute__ ((vector_size (16))) int val26 = {-261,-262,-263,-264};
+__attribute__ ((vector_size (16))) int val27 = {-271,-272,-273,-274};
+__attribute__ ((vector_size (16))) int val28 = {-281,-282,-283,-284};
+__attribute__ ((vector_size (16))) int val29 = {-291,-292,-293,-294};
+__attribute__ ((vector_size (16))) int val30 = {-301,-302,-303,-304};
+__attribute__ ((vector_size (16))) int val31 = {-311,-312,-313,-314};
+#define INIT_REGS INIT_VR; INIT_FPR; INIT_GPR; INIT_CR
+#else
+#ifndef __NO_FPRS__
+#define INIT_REGS INIT_FPR; INIT_GPR; INIT_CR
+#else
+#define INIT_REGS INIT_GPR; INIT_CR
+#endif
+#endif
+#define VERIFY_GPR if (r14 != 14 || r15 != 15 || r16 != 16 || r17 != 17 || r18 != 18 || r19 != 19 || r20 != 20 || r21 != 21 || r22 != 22 || r23 != 23 || r24 != 24 || r25 != 25 || r26 != 26 || r27 != 27 || r28 != 28 || r29 != 29 || r30 != 30 || r31 != 31) abort ()
+#define VERIFY_FPR if (fr14 != 140.0 || fr15 != 150.0 || fr16 != 160.0 || fr17 != 170.0 || fr18 != 180.0 || fr19 != 190.0 || fr20 != 200.0 || fr21 != 210.0 || fr22 != 220.0 || fr23 != 230.0 || fr24 != 240.0 || fr25 != 250.0 || fr26 != 260.0 || fr27 != 270.0 || fr28 != 280.0 || fr29 != 290.0 || fr30 != 300.0 || fr31 != 310.0) abort ()
+#define VERIFY_VR if (!vec_all_eq (v20, val20) || !vec_all_eq (v21, val21) || !vec_all_eq (v22, val22) || !vec_all_eq (v23, val23) || !vec_all_eq (v24, val24) || !vec_all_eq (v25, val25) || !vec_all_eq (v26, val26) || !vec_all_eq (v27, val27) || !vec_all_eq (v28, val28) || !vec_all_eq (v29, val29) || !vec_all_eq (v30, val30) || !vec_all_eq (v31, val31)) abort ()
+#define VERIFY_CR ({ int tmp; __asm__ __volatile__ ("mfcr %0" : "=r" (tmp)); if ((tmp & ((15 << 20) | (15 << 16) | (15 << 12))) != ((6 << 20) | (7 << 16) | (8 << 12))) abort (); })
+#ifdef __ALTIVEC__
+#define VERIFY_REGS VERIFY_VR; VERIFY_FPR; VERIFY_GPR; VERIFY_CR
+#else
+#ifndef __NO_FPRS__
+#define VERIFY_REGS VERIFY_FPR; VERIFY_GPR; VERIFY_CR
+#else
+#define VERIFY_REGS VERIFY_GPR; VERIFY_CR
+#endif
+#endif
+
+#else /* NO_BODY */
+/* For looking at prologue and epilogue code without distractions.  */
+#define abort()
+#define TRASH_ALL_CR
+#define TRASH_ALL_VR
+#define TRASH_ALL_FPR
+#define TRASH_ALL_GPR
+#define USE_ALL_CR
+#define USE_ALL_VR
+#define USE_ALL_FPR
+#define USE_ALL_GPR
+#define TRASH_SOME_CR
+#define TRASH_SOME_VR
+#define TRASH_SOME_FPR
+#define TRASH_SOME_GPR
+#define USE_SOME_CR
+#define USE_SOME_VR
+#define USE_SOME_FPR
+#define USE_SOME_GPR
+#define INIT_REGS
+#define VERIFY_REGS
+#endif
+
+#ifdef __ALTIVEC__
+#ifndef __NO_FPRS__
+void b_all (void)
+{
+  char a[33000];
+  TRASH_ALL_CR;
+  TRASH_ALL_VR;
+  TRASH_ALL_FPR;
+  TRASH_ALL_GPR;
+  USE_ALL_CR;
+  USE_ALL_VR;
+  USE_ALL_FPR;
+  USE_ALL_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "cr3", "cr4", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "fr14", "fr15", "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31");
+}
+
+void b_cvfr (void)
+{
+  char a[33000];
+  TRASH_SOME_CR;
+  TRASH_SOME_VR;
+  TRASH_SOME_FPR;
+  TRASH_SOME_GPR;
+  USE_SOME_CR;
+  USE_SOME_VR;
+  USE_SOME_FPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "v26", "v27", "v31", "fr28", "fr31", "r30", "r31");
+}
+
+void b_vfr (void)
+{
+  char a[33000];
+  TRASH_SOME_VR;
+  TRASH_SOME_FPR;
+  TRASH_SOME_GPR;
+  USE_SOME_VR;
+  USE_SOME_FPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "v26", "v27", "v31", "fr28", "fr31", "r30", "r31");
+}
+
+void b_cvf (void)
+{
+  char a[33000];
+  TRASH_SOME_CR;
+  TRASH_SOME_VR;
+  TRASH_SOME_FPR;
+  USE_SOME_CR;
+  USE_SOME_VR;
+  USE_SOME_FPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "v26", "v27", "v31", "fr28", "fr31");
+}
+
+void b_vf (void)
+{
+  char a[33000];
+  TRASH_SOME_VR;
+  TRASH_SOME_FPR;
+  USE_SOME_VR;
+  USE_SOME_FPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "v26", "v27", "v31", "fr28", "fr31");
+}
+#endif
+
+void b_cvr (void)
+{
+  char a[33000];
+  TRASH_SOME_CR;
+  TRASH_SOME_VR;
+  TRASH_SOME_GPR;
+  USE_SOME_CR;
+  USE_SOME_VR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "v26", "v27", "v31", "r30", "r31");
+}
+
+void b_vr (void)
+{
+  char a[33000];
+  TRASH_SOME_VR;
+  TRASH_SOME_GPR;
+  USE_SOME_VR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "v26", "v27", "v31", "r30", "r31");
+}
+
+void b_cv (void)
+{
+  char a[33000];
+  TRASH_SOME_CR;
+  TRASH_SOME_VR;
+  USE_SOME_CR;
+  USE_SOME_VR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "v26", "v27", "v31");
+}
+
+void b_v (void)
+{
+  char a[33000];
+  TRASH_SOME_VR;
+  USE_SOME_VR;
+  __asm __volatile ("#%0" : "=m" (a) : : "v26", "v27", "v31");
+}
+#endif
+
+#ifndef __NO_FPRS__
+void b_cfr (void)
+{
+  char a[33000];
+  TRASH_SOME_CR;
+  TRASH_SOME_FPR;
+  TRASH_SOME_GPR;
+  USE_SOME_CR;
+  USE_SOME_FPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "fr28", "fr31", "r30", "r31");
+}
+
+void b_fr (void)
+{
+  char a[33000];
+  TRASH_SOME_FPR;
+  TRASH_SOME_GPR;
+  USE_SOME_FPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "fr28", "fr31", "r30", "r31");
+}
+
+void b_cf (void)
+{
+  char a[33000];
+  TRASH_SOME_CR;
+  TRASH_SOME_FPR;
+  USE_SOME_CR;
+  USE_SOME_FPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "fr28", "fr31");
+}
+
+void b_f (void)
+{
+  char a[33000];
+  TRASH_SOME_FPR;
+  USE_SOME_FPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "fr28", "fr31");
+}
+#endif
+
+void b_cr (void)
+{
+  char a[33000];
+  TRASH_SOME_CR;
+  TRASH_SOME_GPR;
+  USE_SOME_CR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "r30", "r31");
+}
+
+void b_r (void)
+{
+  char a[33000];
+  TRASH_SOME_GPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "r30", "r31");
+}
+
+void b_c (void)
+{
+  char a[33000];
+  TRASH_SOME_CR;
+  USE_SOME_CR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2");
+}
+
+void b_0 (void)
+{
+  char a[33000];
+  __asm __volatile ("#%0" : "=m" (a) );
+}
+
+#ifdef __ALTIVEC__
+#ifndef __NO_FPRS__
+void s_all (void)
+{
+  char a[33];
+  TRASH_ALL_CR;
+  TRASH_ALL_VR;
+  TRASH_ALL_FPR;
+  TRASH_ALL_GPR;
+  USE_ALL_CR;
+  USE_ALL_VR;
+  USE_ALL_FPR;
+  USE_ALL_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "cr3", "cr4", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "fr14", "fr15", "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31");
+}
+
+void s_cvfr (void)
+{
+  char a[33];
+  TRASH_SOME_CR;
+  TRASH_SOME_VR;
+  TRASH_SOME_FPR;
+  TRASH_SOME_GPR;
+  USE_SOME_CR;
+  USE_SOME_VR;
+  USE_SOME_FPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "v26", "v27", "v31", "fr28", "fr31", "r30", "r31");
+}
+
+void s_vfr (void)
+{
+  char a[33];
+  TRASH_SOME_VR;
+  TRASH_SOME_FPR;
+  TRASH_SOME_GPR;
+  USE_SOME_VR;
+  USE_SOME_FPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "v26", "v27", "v31", "fr28", "fr31", "r30", "r31");
+}
+
+void s_cvf (void)
+{
+  char a[33];
+  TRASH_SOME_CR;
+  TRASH_SOME_VR;
+  TRASH_SOME_FPR;
+  USE_SOME_CR;
+  USE_SOME_VR;
+  USE_SOME_FPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "v26", "v27", "v31", "fr28", "fr31");
+}
+
+void s_vf (void)
+{
+  char a[33];
+  TRASH_SOME_VR;
+  TRASH_SOME_FPR;
+  USE_SOME_VR;
+  USE_SOME_FPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "v26", "v27", "v31", "fr28", "fr31");
+}
+#endif
+
+void s_cvr (void)
+{
+  char a[33];
+  TRASH_SOME_CR;
+  TRASH_SOME_VR;
+  TRASH_SOME_GPR;
+  USE_SOME_CR;
+  USE_SOME_VR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "v26", "v27", "v31", "r30", "r31");
+}
+
+void s_vr (void)
+{
+  char a[33];
+  TRASH_SOME_VR;
+  TRASH_SOME_GPR;
+  USE_SOME_VR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "v26", "v27", "v31", "r30", "r31");
+}
+
+void s_cv (void)
+{
+  char a[33];
+  TRASH_SOME_CR;
+  TRASH_SOME_VR;
+  USE_SOME_CR;
+  USE_SOME_VR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "v26", "v27", "v31");
+}
+
+void s_v (void)
+{
+  char a[33];
+  TRASH_SOME_VR;
+  USE_SOME_VR;
+  __asm __volatile ("#%0" : "=m" (a) : : "v26", "v27", "v31");
+}
+#endif
+
+#ifndef __NO_FPRS__
+void s_cfr (void)
+{
+  char a[33];
+  TRASH_SOME_CR;
+  TRASH_SOME_FPR;
+  TRASH_SOME_GPR;
+  USE_SOME_CR;
+  USE_SOME_FPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "fr28", "fr31", "r30", "r31");
+}
+
+void s_fr (void)
+{
+  char a[33];
+  TRASH_SOME_FPR;
+  TRASH_SOME_GPR;
+  USE_SOME_FPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "fr28", "fr31", "r30", "r31");
+}
+
+void s_cf (void)
+{
+  char a[33];
+  TRASH_SOME_CR;
+  TRASH_SOME_FPR;
+  USE_SOME_CR;
+  USE_SOME_FPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "fr28", "fr31");
+}
+
+void s_f (void)
+{
+  char a[33];
+  TRASH_SOME_FPR;
+  USE_SOME_FPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "fr28", "fr31");
+}
+#endif
+
+void s_cr (void)
+{
+  char a[33];
+  TRASH_SOME_CR;
+  TRASH_SOME_GPR;
+  USE_SOME_CR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2", "r30", "r31");
+}
+
+void s_r (void)
+{
+  char a[33];
+  TRASH_SOME_GPR;
+  USE_SOME_GPR;
+  __asm __volatile ("#%0" : "=m" (a) : : "r30", "r31");
+}
+
+void s_c (void)
+{
+  char a[33];
+  TRASH_SOME_CR;
+  USE_SOME_CR;
+  __asm __volatile ("#%0" : "=m" (a) : : "cr2");
+}
+
+void s_0 (void)
+{
+  char a[33];
+  __asm __volatile ("#%0" : "=m" (a) );
+}
+
+#ifdef __ALTIVEC__
+#ifndef __NO_FPRS__
+void wb_all (void)
+{
+  char b[10];
+  char *nb_all (void)
+  {
+    char a[33000];
+    TRASH_ALL_CR;
+    TRASH_ALL_VR;
+    TRASH_ALL_FPR;
+    TRASH_ALL_GPR;
+    USE_ALL_CR;
+    USE_ALL_VR;
+    USE_ALL_FPR;
+    USE_ALL_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "cr3", "cr4", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "fr14", "fr15", "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31");
+    return b;
+  }
+  if (nb_all() != b)
+    abort ();
+}
+
+void wb_cvfr (void)
+{
+  char b[10];
+  char *nb_cvfr (void)
+  {
+    char a[33000];
+    TRASH_SOME_CR;
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    TRASH_SOME_GPR;
+    USE_SOME_CR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", "v31", "fr28", "fr31", "r30", "r31");
+    return b;
+  }
+  if (nb_cvfr () != b)
+    abort ();
+}
+
+void wb_vfr (void)
+{
+  char b[10];
+  char *nb_vfr (void)
+  {
+    char a[33000];
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    TRASH_SOME_GPR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31", "fr28", "fr31", "r30", "r31");
+    return b;
+  }
+  if (nb_vfr () != b)
+    abort ();
+}
+
+void wb_cvf (void)
+{
+  char b[10];
+  char *nb_cvf (void)
+  {
+    char a[33000];
+    TRASH_SOME_CR;
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    USE_SOME_CR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", "v31", "fr28", "fr31");
+    return b;
+  }
+  if (nb_cvf () != b)
+    abort ();
+}
+
+void wb_vf (void)
+{
+  char b[10];
+  char *nb_vf (void)
+  {
+    char a[33000];
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31", "fr28", "fr31");
+    return b;
+  }
+  if (nb_vf () != b)
+    abort ();
+}
+#endif
+
+void wb_cvr (void)
+{
+  char b[10];
+  char *nb_cvr (void)
+  {
+    char a[33000];
+    TRASH_SOME_CR;
+    TRASH_SOME_VR;
+    TRASH_SOME_GPR;
+    USE_SOME_CR;
+    USE_SOME_VR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", "v31", "r30", "r31");
+    return b;
+  }
+  if (nb_cvr () != b)
+    abort ();
+}
+
+void wb_vr (void)
+{
+  char b[10];
+  char *nb_vr (void)
+  {
+    char a[33000];
+    TRASH_SOME_VR;
+    TRASH_SOME_GPR;
+    USE_SOME_VR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31", "r30", "r31");
+    return b;
+  }
+  if (nb_vr () != b)
+    abort ();
+}
+
+void wb_cv (void)
+{
+  char b[10];
+  char *nb_cv (void)
+  {
+    char a[33000];
+    TRASH_SOME_CR;
+    TRASH_SOME_VR;
+    USE_SOME_CR;
+    USE_SOME_VR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", "v31");
+    return b;
+  }
+  if (nb_cv () != b)
+    abort ();
+}
+
+void wb_v (void)
+{
+  char b[10];
+  char *nb_v (void)
+  {
+    char a[33000];
+    TRASH_SOME_VR;
+    USE_SOME_VR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31");
+    return b;
+  }
+  if (nb_v () != b)
+    abort ();
+}
+#endif
+
+#ifndef __NO_FPRS__
+void wb_cfr (void)
+{
+  char b[10];
+  char *nb_cfr (void)
+  {
+    char a[33000];
+    TRASH_SOME_CR;
+    TRASH_SOME_FPR;
+    TRASH_SOME_GPR;
+    USE_SOME_CR;
+    USE_SOME_FPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "fr28", "fr31", "r30", "r31");
+    return b;
+  }
+  if (nb_cfr () != b)
+    abort ();
+}
+
+void wb_fr (void)
+{
+  char b[10];
+  char *nb_fr (void)
+  {
+    char a[33000];
+    TRASH_SOME_FPR;
+    TRASH_SOME_GPR;
+    USE_SOME_FPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "fr28", "fr31", "r30", "r31");
+    return b;
+  }
+  if (nb_fr () != b)
+    abort ();
+}
+
+void wb_cf (void)
+{
+  char b[10];
+  char *nb_cf (void)
+  {
+    char a[33000];
+    TRASH_SOME_CR;
+    TRASH_SOME_FPR;
+    USE_SOME_CR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "fr28", "fr31");
+    return b;
+  }
+  if (nb_cf () != b)
+    abort ();
+}
+
+void wb_f (void)
+{
+  char b[10];
+  char *nb_f (void)
+  {
+    char a[33000];
+    TRASH_SOME_FPR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "fr28", "fr31");
+    return b;
+  }
+  if (nb_f () != b)
+    abort ();
+}
+#endif
+
+void wb_cr (void)
+{
+  char b[10];
+  char *nb_cr (void)
+  {
+    char a[33000];
+    TRASH_SOME_CR;
+    TRASH_SOME_GPR;
+    USE_SOME_CR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "r30", "r31");
+    return b;
+  }
+  if (nb_cr () != b)
+    abort ();
+}
+
+void wb_r (void)
+{
+  char b[10];
+  char *nb_r (void)
+  {
+    char a[33000];
+    TRASH_SOME_GPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "r30", "r31");
+    return b;
+  }
+  if (nb_r () != b)
+    abort ();
+}
+
+void wb_c (void)
+{
+  char b[10];
+  char *nb_c (void)
+  {
+    char a[33000];
+    TRASH_SOME_CR;
+    USE_SOME_CR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2");
+    return b;
+  }
+  if (nb_c () != b)
+    abort ();
+}
+
+void wb_0 (void)
+{
+  char b[10];
+  char *nb_0 (void)
+  {
+    char a[33000];
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) );
+    return b;
+  }
+  if (nb_0 () != b)
+    abort ();
+}
+
+#ifdef __ALTIVEC__
+#ifndef __NO_FPRS__
+void ws_all (void)
+{
+  char b[10];
+  char *ns_all (void)
+  {
+    char a[33];
+    TRASH_ALL_CR;
+    TRASH_ALL_VR;
+    TRASH_ALL_FPR;
+    TRASH_ALL_GPR;
+    USE_ALL_CR;
+    USE_ALL_VR;
+    USE_ALL_FPR;
+    USE_ALL_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "cr3", "cr4", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "fr14", "fr15", "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31");
+    return b;
+  }
+  if (ns_all() != b)
+    abort ();
+}
+
+void ws_cvfr (void)
+{
+  char b[10];
+  char *ns_cvfr (void)
+  {
+    char a[33];
+    TRASH_SOME_CR;
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    TRASH_SOME_GPR;
+    USE_SOME_CR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", "v31", "fr28", "fr31", "r30", "r31");
+    return b;
+  }
+  if (ns_cvfr () != b)
+    abort ();
+}
+
+void ws_vfr (void)
+{
+  char b[10];
+  char *ns_vfr (void)
+  {
+    char a[33];
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    TRASH_SOME_GPR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31", "fr28", "fr31", "r30", "r31");
+    return b;
+  }
+  if (ns_vfr () != b)
+    abort ();
+}
+
+void ws_cvf (void)
+{
+  char b[10];
+  char *ns_cvf (void)
+  {
+    char a[33];
+    TRASH_SOME_CR;
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    USE_SOME_CR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", "v31", "fr28", "fr31");
+    return b;
+  }
+  if (ns_cvf () != b)
+    abort ();
+}
+
+void ws_vf (void)
+{
+  char b[10];
+  char *ns_vf (void)
+  {
+    char a[33];
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31", "fr28", "fr31");
+    return b;
+  }
+  if (ns_vf () != b)
+    abort ();
+}
+#endif
+
+void ws_cvr (void)
+{
+  char b[10];
+  char *ns_cvr (void)
+  {
+    char a[33];
+    TRASH_SOME_CR;
+    TRASH_SOME_VR;
+    TRASH_SOME_GPR;
+    USE_SOME_CR;
+    USE_SOME_VR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", "v31", "r30", "r31");
+    return b;
+  }
+  if (ns_cvr () != b)
+    abort ();
+}
+
+void ws_vr (void)
+{
+  char b[10];
+  char *ns_vr (void)
+  {
+    char a[33];
+    TRASH_SOME_VR;
+    TRASH_SOME_FPR;
+    USE_SOME_VR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31", "r30", "r31");
+    return b;
+  }
+  if (ns_vr () != b)
+    abort ();
+}
+
+void ws_cv (void)
+{
+  char b[10];
+  char *ns_cv (void)
+  {
+    char a[33];
+    TRASH_SOME_CR;
+    TRASH_SOME_VR;
+    USE_SOME_CR;
+    USE_SOME_VR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "v26", "v27", "v31");
+    return b;
+  }
+  if (ns_cv () != b)
+    abort ();
+}
+
+void ws_v (void)
+{
+  char b[10];
+  char *ns_v (void)
+  {
+    char a[33];
+    TRASH_SOME_VR;
+    USE_SOME_VR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "v26", "v27", "v31");
+    return b;
+  }
+  if (ns_v () != b)
+    abort ();
+}
+#endif
+
+#ifndef __NO_FPRS__
+void ws_cfr (void)
+{
+  char b[10];
+  char *ns_cfr (void)
+  {
+    char a[33];
+    TRASH_SOME_CR;
+    TRASH_SOME_FPR;
+    TRASH_SOME_GPR;
+    USE_SOME_CR;
+    USE_SOME_FPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "fr28", "fr31", "r30", "r31");
+    return b;
+  }
+  if (ns_cfr () != b)
+    abort ();
+}
+
+void ws_fr (void)
+{
+  char b[10];
+  char *ns_fr (void)
+  {
+    char a[33];
+    TRASH_SOME_FPR;
+    TRASH_SOME_GPR;
+    USE_SOME_FPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "fr28", "fr31", "r30", "r31");
+    return b;
+  }
+  if (ns_fr () != b)
+    abort ();
+}
+
+void ws_cf (void)
+{
+  char b[10];
+  char *ns_cf (void)
+  {
+    char a[33];
+    TRASH_SOME_CR;
+    TRASH_SOME_FPR;
+    USE_SOME_CR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "fr28", "fr31");
+    return b;
+  }
+  if (ns_cf () != b)
+    abort ();
+}
+
+void ws_f (void)
+{
+  char b[10];
+  char *ns_f (void)
+  {
+    char a[33];
+    TRASH_SOME_FPR;
+    USE_SOME_FPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "fr28", "fr31");
+    return b;
+  }
+  if (ns_f () != b)
+    abort ();
+}
+#endif
+
+void ws_cr (void)
+{
+  char b[10];
+  char *ns_cr (void)
+  {
+    char a[33];
+    TRASH_SOME_CR;
+    TRASH_SOME_GPR;
+    USE_SOME_CR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2", "r30", "r31");
+    return b;
+  }
+  if (ns_cr () != b)
+    abort ();
+}
+
+void ws_r (void)
+{
+  char b[10];
+  char *ns_r (void)
+  {
+    char a[33];
+    TRASH_SOME_GPR;
+    USE_SOME_GPR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "r30", "r31");
+    return b;
+  }
+  if (ns_r () != b)
+    abort ();
+}
+
+void ws_c (void)
+{
+  char b[10];
+  char *ns_c (void)
+  {
+    char a[33];
+    TRASH_SOME_CR;
+    USE_SOME_CR;
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) : : "cr2");
+    return b;
+  }
+  if (ns_c () != b)
+    abort ();
+}
+
+void ws_0 (void)
+{
+  char b[10];
+  char *ns_0 (void)
+  {
+    char a[33];
+    __asm __volatile ("#%0 %1" : "=m" (a), "=m" (b) );
+    return b;
+  }
+  if (ns_0 () != b)
+    abort ();
+}
+
+int main (void)
+{
+  INIT_REGS;
+  USE_ALL_CR;
+#ifdef __ALTIVEC__
+  USE_ALL_VR;
+#ifndef __NO_FPRS__
+  USE_ALL_FPR;
+#endif
+#endif
+  USE_ALL_GPR;
+#ifdef __ALTIVEC__
+#ifndef __NO_FPRS__
+  b_all ();
+  VERIFY_REGS;
+  b_cvfr ();
+  VERIFY_REGS;
+  b_vfr ();
+  VERIFY_REGS;
+  b_cvf ();
+  VERIFY_REGS;
+  b_vf ();
+  VERIFY_REGS;
+#endif
+  b_cvr ();
+  VERIFY_REGS;
+  b_vr ();
+  VERIFY_REGS;
+  b_cv ();
+  VERIFY_REGS;
+  b_v ();
+  VERIFY_REGS;
+#endif
+#ifndef __NO_FPRS__
+  b_cfr ();
+  VERIFY_REGS;
+  b_fr ();
+  VERIFY_REGS;
+  b_cf ();
+  VERIFY_REGS;
+  b_f ();
+  VERIFY_REGS;
+#endif
+  b_cr ();
+  VERIFY_REGS;
+  b_r ();
+  VERIFY_REGS;
+  b_c ();
+  VERIFY_REGS;
+  b_0 ();
+  VERIFY_REGS;
+#ifdef __ALTIVEC__
+#ifndef __NO_FPRS__
+  s_all ();
+  VERIFY_REGS;
+  s_cvfr ();
+  VERIFY_REGS;
+  s_vfr ();
+  VERIFY_REGS;
+  s_cvf ();
+  VERIFY_REGS;
+  s_vf ();
+  VERIFY_REGS;
+#endif
+  s_cvr ();
+  VERIFY_REGS;
+  s_vr ();
+  VERIFY_REGS;
+  s_cv ();
+  VERIFY_REGS;
+  s_v ();
+  VERIFY_REGS;
+#endif
+#ifndef __NO_FPRS__
+  s_cfr ();
+  VERIFY_REGS;
+  s_fr ();
+  VERIFY_REGS;
+  s_cf ();
+  VERIFY_REGS;
+  s_f ();
+  VERIFY_REGS;
+#endif
+  s_cr ();
+  VERIFY_REGS;
+  s_r ();
+  VERIFY_REGS;
+  s_c ();
+  VERIFY_REGS;
+  s_0 ();
+  VERIFY_REGS;
+#ifdef __ALTIVEC__
+#ifndef __NO_FPRS__
+  wb_all ();
+  VERIFY_REGS;
+  wb_cvfr ();
+  VERIFY_REGS;
+  wb_vfr ();
+  VERIFY_REGS;
+  wb_cvf ();
+  VERIFY_REGS;
+  wb_vf ();
+  VERIFY_REGS;
+#endif
+  wb_cvr ();
+  VERIFY_REGS;
+  wb_vr ();
+  VERIFY_REGS;
+  wb_cv ();
+  VERIFY_REGS;
+  wb_v ();
+  VERIFY_REGS;
+#endif
+#ifndef __NO_FPRS__
+  wb_cfr ();
+  VERIFY_REGS;
+  wb_fr ();
+  VERIFY_REGS;
+  wb_cf ();
+  VERIFY_REGS;
+  wb_f ();
+  VERIFY_REGS;
+#endif
+  wb_cr ();
+  VERIFY_REGS;
+  wb_r ();
+  VERIFY_REGS;
+  wb_c ();
+  VERIFY_REGS;
+  wb_0 ();
+  VERIFY_REGS;
+#ifdef __ALTIVEC__
+#ifndef __NO_FPRS__
+  ws_all ();
+  VERIFY_REGS;
+  ws_cvfr ();
+  VERIFY_REGS;
+  ws_vfr ();
+  VERIFY_REGS;
+  ws_cvf ();
+  VERIFY_REGS;
+  ws_vf ();
+  VERIFY_REGS;
+#endif
+  ws_cvr ();
+  VERIFY_REGS;
+  ws_vr ();
+  VERIFY_REGS;
+  ws_cv ();
+  VERIFY_REGS;
+  ws_v ();
+  VERIFY_REGS;
+#endif
+#ifndef __NO_FPRS__
+  ws_cfr ();
+  VERIFY_REGS;
+  ws_fr ();
+  VERIFY_REGS;
+  ws_cf ();
+  VERIFY_REGS;
+  ws_f ();
+  VERIFY_REGS;
+#endif
+  ws_cr ();
+  VERIFY_REGS;
+  ws_r ();
+  VERIFY_REGS;
+  ws_c ();
+  VERIFY_REGS;
+  ws_0 ();
+  VERIFY_REGS;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c
new file mode 100644
index 000000000..59b68ee36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O2 -mcpu=power6 -mhard-dfp" } */
+/* { dg-final { scan-assembler-not   "lfiwzx"   } } */
+/* { dg-final { scan-assembler-times "lfd"    2 } } */
+/* { dg-final { scan-assembler-times "dctdp"  2 } } */
+/* { dg-final { scan-assembler-times "dadd"   1 } } */
+/* { dg-final { scan-assembler-times "drsp"   1 } } */
+
+/* Test that for power6 we need to use a bounce buffer on the stack to load
+   SDmode variables because the power6 does not have a way to directly load
+   32-bit values from memory.  */
+_Decimal32 a;
+
+void inc_dec32 (void)
+{
+  a += (_Decimal32) 1.0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/sd-vsx.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/sd-vsx.c
new file mode 100644
index 000000000..c7cb75112
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/sd-vsx.c
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-require-effective-target dfp } */
+/* { dg-options "-O2 -mcpu=power7 -mhard-dfp" } */
+/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */
+/* { dg-final { scan-assembler-times "stfiwx" 1 } } */
+/* { dg-final { scan-assembler-not   "lfd"      } } */
+/* { dg-final { scan-assembler-not   "stfd"     } } */
+/* { dg-final { scan-assembler-times "dctdp"  2 } } */
+/* { dg-final { scan-assembler-times "dadd"   1 } } */
+/* { dg-final { scan-assembler-times "drsp"   1 } } */
+
+/* Test that power7 can directly load/store SDmode variables without using a
+   bounce buffer.  */
+_Decimal32 a;
+
+void inc_dec32 (void)
+{
+  a += (_Decimal32) 1.0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c
new file mode 100644
index 000000000..8bdb154e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-small-data-1.c
@@ -0,0 +1,14 @@
+/* Verify that we don't ICE trying to put SPE data in .sdata2.  */
+/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */
+/* { dg-options "-msdata=eabi -mcall-eabi -G 8" } */
+
+#include <spe.h>
+
+__ev64_fs__ x;
+
+int main(void)
+{
+  x = __ev_fsabs (x);
+  return(0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c
new file mode 100644
index 000000000..5354e49f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-small-data-2.c
@@ -0,0 +1,13 @@
+/* Verify that we don't ICE trying to put float data in .sdata2.  */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_eabi_ok } */
+/* { dg-options "-msdata=eabi -mcall-eabi -G 8" } */
+
+double x;
+
+int main(void)
+{
+  x = x * 2;
+  return(0);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c
new file mode 100644
index 000000000..84d4bf288
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c
@@ -0,0 +1,116 @@
+/* Verify that unwinding can find SPE registers in signal frames.  */
+/* Origin: Joseph Myers <joseph@codesourcery.com> */
+/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */
+/* { dg-options "-fexceptions -fnon-call-exceptions -O2" } */
+
+#include <unwind.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <string.h>
+
+int count;
+char *null;
+int found_reg;
+
+typedef int v2si __attribute__((__vector_size__(8)));
+
+v2si v1 = { 123, 234 };
+v2si v2 = { 345, 456 };
+
+static _Unwind_Reason_Code
+force_unwind_stop (int version, _Unwind_Action actions,
+                   _Unwind_Exception_Class exc_class,
+                   struct _Unwind_Exception *exc_obj,
+                   struct _Unwind_Context *context,
+                   void *stop_parameter)
+{
+  unsigned int reg;
+  if (actions & _UA_END_OF_STACK)
+    abort ();
+  if (_Unwind_GetGR (context, 1215) == 123)
+    found_reg = 1;
+  return _URC_NO_REASON;
+}
+
+static void force_unwind ()
+{
+  struct _Unwind_Exception *exc = malloc (sizeof (*exc));
+  memset (&exc->exception_class, 0, sizeof (exc->exception_class));
+  exc->exception_cleanup = 0;
+
+#ifndef __USING_SJLJ_EXCEPTIONS__
+  _Unwind_ForcedUnwind (exc, force_unwind_stop, 0);
+#else
+  _Unwind_SjLj_ForcedUnwind (exc, force_unwind_stop, 0);
+#endif
+
+  abort ();
+}
+
+static void counter (void *p __attribute__((unused)))
+{
+  ++count;
+}
+
+static void handler (void *p __attribute__((unused)))
+{
+  if (count != 2)
+    abort ();
+  if (!found_reg)
+    abort ();
+  exit (0);
+}
+
+static int __attribute__((noinline)) fn5 ()
+{
+  char dummy __attribute__((cleanup (counter)));
+  force_unwind ();
+  return 0;
+}
+
+static void fn4 (int sig)
+{
+  char dummy __attribute__((cleanup (counter)));
+  /* Clobber high part without compiler's knowledge so the only saved
+     copy is from the signal frame.  */
+  asm volatile ("evmergelo 15,15,15");
+  fn5 ();
+  null = NULL;
+}
+
+static void fn3 ()
+{
+  abort ();
+}
+
+static int __attribute__((noinline)) fn2 ()
+{
+  register v2si r15 asm("r15");
+  r15 = v1;
+  asm volatile ("" : "+r" (r15));
+  *null = 0;
+  fn3 ();
+  return 0;
+}
+
+static int __attribute__((noinline)) fn1 ()
+{
+  signal (SIGSEGV, fn4);
+  signal (SIGBUS, fn4);
+  fn2 ();
+  return 0;
+}
+
+static int __attribute__((noinline)) fn0 ()
+{
+  char dummy __attribute__((cleanup (handler)));
+  fn1 ();
+  null = 0;
+  return 0;
+}
+
+int main()
+{ 
+  fn0 ();
+  abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c
new file mode 100644
index 000000000..09f813482
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+/* { dg-final { scan-assembler "evstdd" } } */
+
+void foo(void)
+{
+  int x[8] __attribute__((aligned(64))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
+  bar (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c
new file mode 100644
index 000000000..7ecaf1037
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe-vector-memset.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_spe } */
+/* { dg-options "-O -mspe=yes" } */
+/* { dg-final { scan-assembler "evstdd" } } */
+
+#include <string.h>
+
+void foo(void)
+{
+  int x[8] __attribute__((aligned(64)));
+  memset (x, 0, sizeof (x));
+  bar (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe1.c
new file mode 100644
index 000000000..ddbb5a6e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/spe1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+
+/* (Test with -O0 so we don't optimize any of them away).  */
+
+
+typedef float __attribute__((vector_size(8))) __ev64_fs__;
+
+__ev64_opaque__ Foo (void);
+
+void Bar ()
+{
+  __ev64_fs__ fs = Foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c
new file mode 100644
index 000000000..3c52287b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/stabs-attrib-vect-darwin.c
@@ -0,0 +1,11 @@
+/* Test Attribute Vector associated with vector type stabs.  */
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-gstabs+ -fno-eliminate-unused-debug-types -faltivec" } */
+
+int main ()
+{
+  vector int vi = { 6,7,8,9 };
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".stabs.*vi\:\\(0,\[0-9\]+\\)=\@V" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/tfmode_off.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/tfmode_off.c
new file mode 100644
index 000000000..e6578ef31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/tfmode_off.c
@@ -0,0 +1,51 @@
+/* { dg-do assemble } */
+/* { dg-skip-if "" { powerpc-ibm-aix* } { "*" } { "" } } */
+/* { dg-skip-if "no TFmode" { powerpc-*-eabi* } { "*" } { "" } } */
+/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps" } */
+
+typedef float TFmode __attribute__ ((mode (TF)));
+
+void w1 (void *x, TFmode y) { *(TFmode *) (x + 32767) = y; }
+void w2 (void *x, TFmode y) { *(TFmode *) (x + 32766) = y; }
+void w3 (void *x, TFmode y) { *(TFmode *) (x + 32765) = y; }
+void w4 (void *x, TFmode y) { *(TFmode *) (x + 32764) = y; }
+void w5 (void *x, TFmode y) { *(TFmode *) (x + 32763) = y; }
+void w6 (void *x, TFmode y) { *(TFmode *) (x + 32762) = y; }
+void w7 (void *x, TFmode y) { *(TFmode *) (x + 32761) = y; }
+void w8 (void *x, TFmode y) { *(TFmode *) (x + 32760) = y; }
+void w9 (void *x, TFmode y) { *(TFmode *) (x + 32759) = y; }
+void w10 (void *x, TFmode y) { *(TFmode *) (x + 32758) = y; }
+void w11 (void *x, TFmode y) { *(TFmode *) (x + 32757) = y; }
+void w12 (void *x, TFmode y) { *(TFmode *) (x + 32756) = y; }
+void w13 (void *x, TFmode y) { *(TFmode *) (x + 32755) = y; }
+void w14 (void *x, TFmode y) { *(TFmode *) (x + 32754) = y; }
+void w15 (void *x, TFmode y) { *(TFmode *) (x + 32753) = y; }
+void w16 (void *x, TFmode y) { *(TFmode *) (x + 32752) = y; }
+void w17 (void *x, TFmode y) { *(TFmode *) (x + 32751) = y; }
+void w18 (void *x, TFmode y) { *(TFmode *) (x + 32750) = y; }
+void w19 (void *x, TFmode y) { *(TFmode *) (x + 32749) = y; }
+void w20 (void *x, TFmode y) { *(TFmode *) (x + 32748) = y; }
+
+TFmode r1 (void *x) { return *(TFmode *) (x + 32767); }
+TFmode r2 (void *x) { return *(TFmode *) (x + 32766); }
+TFmode r3 (void *x) { return *(TFmode *) (x + 32765); }
+TFmode r4 (void *x) { return *(TFmode *) (x + 32764); }
+TFmode r5 (void *x) { return *(TFmode *) (x + 32763); }
+TFmode r6 (void *x) { return *(TFmode *) (x + 32762); }
+TFmode r7 (void *x) { return *(TFmode *) (x + 32761); }
+TFmode r8 (void *x) { return *(TFmode *) (x + 32760); }
+TFmode r9 (void *x) { return *(TFmode *) (x + 32759); }
+TFmode r10 (void *x) { return *(TFmode *) (x + 32758); }
+TFmode r11 (void *x) { return *(TFmode *) (x + 32757); }
+TFmode r12 (void *x) { return *(TFmode *) (x + 32756); }
+TFmode r13 (void *x) { return *(TFmode *) (x + 32755); }
+TFmode r14 (void *x) { return *(TFmode *) (x + 32754); }
+TFmode r15 (void *x) { return *(TFmode *) (x + 32753); }
+TFmode r16 (void *x) { return *(TFmode *) (x + 32752); }
+TFmode r17 (void *x) { return *(TFmode *) (x + 32751); }
+TFmode r18 (void *x) { return *(TFmode *) (x + 32750); }
+TFmode r19 (void *x) { return *(TFmode *) (x + 32749); }
+TFmode r20 (void *x) { return *(TFmode *) (x + 32748); }
+
+/* { dg-final { object-size text == 544 } } */
+/* { dg-final { cleanup-saved-temps "tfmode_off" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/timode_off.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/timode_off.c
new file mode 100644
index 000000000..c169e503e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/timode_off.c
@@ -0,0 +1,57 @@
+/* { dg-do assemble { target { lp64 } } } */
+/* { dg-options "-O2 -fno-align-functions -mtraceback=no -save-temps -mcpu=power5" } */
+
+typedef int TImode __attribute__ ((mode (TI)));
+
+void w1 (void *x, TImode y) { *(TImode *) (x + 32767) = y; }
+void w2 (void *x, TImode y) { *(TImode *) (x + 32766) = y; }
+void w3 (void *x, TImode y) { *(TImode *) (x + 32765) = y; }
+void w4 (void *x, TImode y) { *(TImode *) (x + 32764) = y; }
+void w5 (void *x, TImode y) { *(TImode *) (x + 32763) = y; }
+void w6 (void *x, TImode y) { *(TImode *) (x + 32762) = y; }
+void w7 (void *x, TImode y) { *(TImode *) (x + 32761) = y; }
+void w8 (void *x, TImode y) { *(TImode *) (x + 32760) = y; }
+void w9 (void *x, TImode y) { *(TImode *) (x + 32759) = y; }
+void w10 (void *x, TImode y) { *(TImode *) (x + 32758) = y; }
+void w11 (void *x, TImode y) { *(TImode *) (x + 32757) = y; }
+void w12 (void *x, TImode y) { *(TImode *) (x + 32756) = y; }
+void w13 (void *x, TImode y) { *(TImode *) (x + 32755) = y; }
+void w14 (void *x, TImode y) { *(TImode *) (x + 32754) = y; }
+void w15 (void *x, TImode y) { *(TImode *) (x + 32753) = y; }
+void w16 (void *x, TImode y) { *(TImode *) (x + 32752) = y; }
+void w17 (void *x, TImode y) { *(TImode *) (x + 32751) = y; }
+void w18 (void *x, TImode y) { *(TImode *) (x + 32750) = y; }
+void w19 (void *x, TImode y) { *(TImode *) (x + 32749) = y; }
+void w20 (void *x, TImode y) { *(TImode *) (x + 32748) = y; }
+
+TImode r1 (void *x) { return *(TImode *) (x + 32767); }
+TImode r2 (void *x) { return *(TImode *) (x + 32766); }
+TImode r3 (void *x) { return *(TImode *) (x + 32765); }
+TImode r4 (void *x) { return *(TImode *) (x + 32764); }
+TImode r5 (void *x) { return *(TImode *) (x + 32763); }
+TImode r6 (void *x) { return *(TImode *) (x + 32762); }
+TImode r7 (void *x) { return *(TImode *) (x + 32761); }
+TImode r8 (void *x) { return *(TImode *) (x + 32760); }
+TImode r9 (void *x) { return *(TImode *) (x + 32759); }
+TImode r10 (void *x) { return *(TImode *) (x + 32758); }
+TImode r11 (void *x) { return *(TImode *) (x + 32757); }
+TImode r12 (void *x) { return *(TImode *) (x + 32756); }
+TImode r13 (void *x) { return *(TImode *) (x + 32755); }
+TImode r14 (void *x) { return *(TImode *) (x + 32754); }
+TImode r15 (void *x) { return *(TImode *) (x + 32753); }
+TImode r16 (void *x) { return *(TImode *) (x + 32752); }
+TImode r17 (void *x) { return *(TImode *) (x + 32751); }
+TImode r18 (void *x) { return *(TImode *) (x + 32750); }
+TImode r19 (void *x) { return *(TImode *) (x + 32749); }
+TImode r20 (void *x) { return *(TImode *) (x + 32748); }
+
+/* test should really be == 616, see pr54110 */
+/* When TImode is allowed in VSX registers, the allowable address modes for
+   TImode is just a single indirect address in order for the value to be loaded
+   and store in either GPR or VSX registers.  This affects the generated code,
+   and it would cause this test to fail, when such an option is used.  Fall
+   back to power5 to test the code.  */
+
+/* { dg-final { object-size text <= 700 } } */
+/* { dg-final { scan-assembler-not "(st|l)fd" } } */
+/* { dg-final { cleanup-saved-temps "timode_off" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c
new file mode 100644
index 000000000..42d5b6056
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c
@@ -0,0 +1,38 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xvadddp" } } */
+/* { dg-final { scan-assembler "xvsubdp" } } */
+/* { dg-final { scan-assembler "xvmuldp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+/* { dg-final { scan-assembler "xvnmadd" } } */
+/* { dg-final { scan-assembler "xvnmsub" } } */
+/* { dg-final { scan-assembler "xvdivdp" } } */
+/* { dg-final { scan-assembler "xvmaxdp" } } */
+/* { dg-final { scan-assembler "xvmindp" } } */
+/* { dg-final { scan-assembler "xvsqrtdp" } } */
+/* { dg-final { scan-assembler "xvrsqrtedp" } } */
+/* { dg-final { scan-assembler "xvabsdp" } } */
+/* { dg-final { scan-assembler "xvnabsdp" } } */
+/* { dg-final { scan-assembler "xvredp" } } */
+
+void use_builtins (__vector double *p, __vector double *q, __vector double *r, __vector double *s)
+{
+  p[0] = __builtin_vsx_xvadddp (q[0], r[0]);
+  p[1] = __builtin_vsx_xvsubdp (q[1], r[1]);
+  p[2] = __builtin_vsx_xvmuldp (q[2], r[2]);
+  p[3] = __builtin_vsx_xvdivdp (q[3], r[3]);
+  p[4] = __builtin_vsx_xvmaxdp (q[4], r[4]);
+  p[5] = __builtin_vsx_xvmindp (q[5], r[5]);
+  p[6] = __builtin_vsx_xvabsdp (q[6]);
+  p[7] = __builtin_vsx_xvnabsdp (q[7]);
+  p[8] = __builtin_vsx_xvsqrtdp (q[8]);
+  p[9] = __builtin_vsx_xvmadddp (q[9], r[9], s[9]);
+  p[10] = __builtin_vsx_xvmsubdp (q[10], r[10], s[10]);
+  p[11] = __builtin_vsx_xvnmadddp (q[11], r[11], s[11]);
+  p[12] = __builtin_vsx_xvnmsubdp (q[12], r[12], s[12]);
+  p[13] = __builtin_vsx_xvredp (q[13]);
+  p[14] = __builtin_vsx_xvrsqrtedp (q[14]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c
new file mode 100644
index 000000000..6d883dc90
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c
@@ -0,0 +1,38 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xvaddsp" } } */
+/* { dg-final { scan-assembler "xvsubsp" } } */
+/* { dg-final { scan-assembler "xvmulsp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+/* { dg-final { scan-assembler "xvnmadd" } } */
+/* { dg-final { scan-assembler "xvnmsub" } } */
+/* { dg-final { scan-assembler "xvdivsp" } } */
+/* { dg-final { scan-assembler "xvmaxsp" } } */
+/* { dg-final { scan-assembler "xvminsp" } } */
+/* { dg-final { scan-assembler "xvsqrtsp" } } */
+/* { dg-final { scan-assembler "xvabssp" } } */
+/* { dg-final { scan-assembler "xvnabssp" } } */
+/* { dg-final { scan-assembler "xvresp" } } */
+/* { dg-final { scan-assembler "xvrsqrtesp" } } */
+
+void use_builtins (__vector float *p, __vector float *q, __vector float *r, __vector float *s)
+{
+  p[0] = __builtin_vsx_xvaddsp (q[0], r[0]);
+  p[1] = __builtin_vsx_xvsubsp (q[1], r[1]);
+  p[2] = __builtin_vsx_xvmulsp (q[2], r[2]);
+  p[3] = __builtin_vsx_xvdivsp (q[3], r[3]);
+  p[4] = __builtin_vsx_xvmaxsp (q[4], r[4]);
+  p[5] = __builtin_vsx_xvminsp (q[5], r[5]);
+  p[6] = __builtin_vsx_xvabssp (q[6]);
+  p[7] = __builtin_vsx_xvnabssp (q[7]);
+  p[8] = __builtin_vsx_xvsqrtsp (q[8]);
+  p[9] = __builtin_vsx_xvmaddsp (q[9], r[9], s[9]);
+  p[10] = __builtin_vsx_xvmsubsp (q[10], r[10], s[10]);
+  p[11] = __builtin_vsx_xvnmaddsp (q[11], r[11], s[11]);
+  p[12] = __builtin_vsx_xvnmsubsp (q[12], r[12], s[12]);
+  p[13] = __builtin_vsx_xvresp (q[13]);
+  p[14] = __builtin_vsx_xvrsqrtesp (q[14]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
new file mode 100644
index 000000000..7aeba6cb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -0,0 +1,212 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxsel" } } */
+/* { dg-final { scan-assembler "vperm" } } */
+/* { dg-final { scan-assembler "xvrdpi" } } */
+/* { dg-final { scan-assembler "xvrdpic" } } */
+/* { dg-final { scan-assembler "xvrdpim" } } */
+/* { dg-final { scan-assembler "xvrdpip" } } */
+/* { dg-final { scan-assembler "xvrdpiz" } } */
+/* { dg-final { scan-assembler "xvrspi" } } */
+/* { dg-final { scan-assembler "xvrspic" } } */
+/* { dg-final { scan-assembler "xvrspim" } } */
+/* { dg-final { scan-assembler "xvrspip" } } */
+/* { dg-final { scan-assembler "xvrspiz" } } */
+/* { dg-final { scan-assembler "xsrdpi" } } */
+/* { dg-final { scan-assembler "xsrdpic" } } */
+/* { dg-final { scan-assembler "xsrdpim\|frim" } } */
+/* { dg-final { scan-assembler "xsrdpip\|frip" } } */
+/* { dg-final { scan-assembler "xsrdpiz\|friz" } } */
+/* { dg-final { scan-assembler "xsmaxdp" } } */
+/* { dg-final { scan-assembler "xsmindp" } } */
+/* { dg-final { scan-assembler "xxland" } } */
+/* { dg-final { scan-assembler "xxlandc" } } */
+/* { dg-final { scan-assembler "xxlnor" } } */
+/* { dg-final { scan-assembler "xxlor" } } */
+/* { dg-final { scan-assembler "xxlxor" } } */
+/* { dg-final { scan-assembler "xvcmpeqdp" } } */
+/* { dg-final { scan-assembler "xvcmpgtdp" } } */
+/* { dg-final { scan-assembler "xvcmpgedp" } } */
+/* { dg-final { scan-assembler "xvcmpeqsp" } } */
+/* { dg-final { scan-assembler "xvcmpgtsp" } } */
+/* { dg-final { scan-assembler "xvcmpgesp" } } */
+/* { dg-final { scan-assembler "xxsldwi" } } */
+/* { dg-final { scan-assembler-not "call" } } */
+
+extern __vector int si[][4];
+extern __vector short ss[][4];
+extern __vector signed char sc[][4];
+extern __vector float f[][4];
+extern __vector unsigned int ui[][4];
+extern __vector unsigned short us[][4];
+extern __vector unsigned char uc[][4];
+extern __vector __bool int bi[][4];
+extern __vector __bool short bs[][4];
+extern __vector __bool char bc[][4];
+extern __vector __pixel p[][4];
+#ifdef __VSX__
+extern __vector double d[][4];
+extern __vector long sl[][4];
+extern __vector unsigned long ul[][4];
+extern __vector __bool long bl[][4];
+#endif
+
+int do_sel(void)
+{
+  int i = 0;
+
+  si[i][0] = __builtin_vsx_xxsel_4si (si[i][1], si[i][2], si[i][3]); i++;
+  ss[i][0] = __builtin_vsx_xxsel_8hi (ss[i][1], ss[i][2], ss[i][3]); i++;
+  sc[i][0] = __builtin_vsx_xxsel_16qi (sc[i][1], sc[i][2], sc[i][3]); i++;
+  f[i][0] = __builtin_vsx_xxsel_4sf (f[i][1], f[i][2], f[i][3]); i++;
+  d[i][0] = __builtin_vsx_xxsel_2df (d[i][1], d[i][2], d[i][3]); i++;
+
+  si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], bi[i][3]); i++;
+  ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], bs[i][3]); i++;
+  sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], bc[i][3]); i++;
+  f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], bi[i][3]); i++;
+  d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], bl[i][3]); i++;
+
+  si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], ui[i][3]); i++;
+  ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], us[i][3]); i++;
+  sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], uc[i][3]); i++;
+  f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], ui[i][3]); i++;
+  d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], ul[i][3]); i++;
+
+  return i;
+}
+
+int do_perm(void)
+{
+  int i = 0;
+
+  si[i][0] = __builtin_vsx_vperm_4si (si[i][1], si[i][2], uc[i][3]); i++;
+  ss[i][0] = __builtin_vsx_vperm_8hi (ss[i][1], ss[i][2], uc[i][3]); i++;
+  sc[i][0] = __builtin_vsx_vperm_16qi (sc[i][1], sc[i][2], uc[i][3]); i++;
+  f[i][0] = __builtin_vsx_vperm_4sf (f[i][1], f[i][2], uc[i][3]); i++;
+  d[i][0] = __builtin_vsx_vperm_2df (d[i][1], d[i][2], uc[i][3]); i++;
+
+  si[i][0] = __builtin_vsx_vperm (si[i][1], si[i][2], uc[i][3]); i++;
+  ss[i][0] = __builtin_vsx_vperm (ss[i][1], ss[i][2], uc[i][3]); i++;
+  sc[i][0] = __builtin_vsx_vperm (sc[i][1], sc[i][2], uc[i][3]); i++;
+  f[i][0] = __builtin_vsx_vperm (f[i][1], f[i][2], uc[i][3]); i++;
+  d[i][0] = __builtin_vsx_vperm (d[i][1], d[i][2], uc[i][3]); i++;
+
+  return i;
+}
+
+int do_xxperm (void)
+{
+  int i = 0;
+
+  d[i][0] = __builtin_vsx_xxpermdi_2df (d[i][1], d[i][2], 0); i++;
+  d[i][0] = __builtin_vsx_xxpermdi (d[i][1], d[i][2], 1); i++;
+  return i;
+}
+
+double x, y;
+void do_concat (void)
+{
+  d[0][0] = __builtin_vsx_concat_2df (x, y);
+}
+
+void do_set (void)
+{
+  d[0][0] = __builtin_vsx_set_2df (d[0][1], x, 0);
+  d[1][0] = __builtin_vsx_set_2df (d[1][1], y, 1);
+}
+
+extern double z[][4];
+
+int do_math (void)
+{
+  int i = 0;
+
+  d[i][0] = __builtin_vsx_xvrdpi  (d[i][1]); i++;
+  d[i][0] = __builtin_vsx_xvrdpic (d[i][1]); i++;
+  d[i][0] = __builtin_vsx_xvrdpim (d[i][1]); i++;
+  d[i][0] = __builtin_vsx_xvrdpip (d[i][1]); i++;
+  d[i][0] = __builtin_vsx_xvrdpiz (d[i][1]); i++;
+
+  f[i][0] = __builtin_vsx_xvrspi  (f[i][1]); i++;
+  f[i][0] = __builtin_vsx_xvrspic (f[i][1]); i++;
+  f[i][0] = __builtin_vsx_xvrspim (f[i][1]); i++;
+  f[i][0] = __builtin_vsx_xvrspip (f[i][1]); i++;
+  f[i][0] = __builtin_vsx_xvrspiz (f[i][1]); i++;
+
+  z[i][0] = __builtin_vsx_xsrdpi  (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsrdpic (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsrdpim (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsrdpip (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsrdpiz (z[i][1]); i++;
+  z[i][0] = __builtin_vsx_xsmaxdp (z[i][1], z[i][0]); i++;
+  z[i][0] = __builtin_vsx_xsmindp (z[i][1], z[i][0]); i++;
+  return i;
+}
+
+int do_cmp (void)
+{
+  int i = 0;
+
+  d[i][0] = __builtin_vsx_xvcmpeqdp (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xvcmpgtdp (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xvcmpgedp (d[i][1], d[i][2]); i++;
+
+  f[i][0] = __builtin_vsx_xvcmpeqsp (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xvcmpgtsp (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xvcmpgesp (f[i][1], f[i][2]); i++;
+  return i;
+}
+
+int do_logical (void)
+{
+  int i = 0;
+
+  si[i][0] = __builtin_vsx_xxland (si[i][1], si[i][2]); i++;
+  si[i][0] = __builtin_vsx_xxlandc (si[i][1], si[i][2]); i++;
+  si[i][0] = __builtin_vsx_xxlnor (si[i][1], si[i][2]); i++;
+  si[i][0] = __builtin_vsx_xxlor (si[i][1], si[i][2]); i++;
+  si[i][0] = __builtin_vsx_xxlxor (si[i][1], si[i][2]); i++;
+
+  ss[i][0] = __builtin_vsx_xxland (ss[i][1], ss[i][2]); i++;
+  ss[i][0] = __builtin_vsx_xxlandc (ss[i][1], ss[i][2]); i++;
+  ss[i][0] = __builtin_vsx_xxlnor (ss[i][1], ss[i][2]); i++;
+  ss[i][0] = __builtin_vsx_xxlor (ss[i][1], ss[i][2]); i++;
+  ss[i][0] = __builtin_vsx_xxlxor (ss[i][1], ss[i][2]); i++;
+
+  sc[i][0] = __builtin_vsx_xxland (sc[i][1], sc[i][2]); i++;
+  sc[i][0] = __builtin_vsx_xxlandc (sc[i][1], sc[i][2]); i++;
+  sc[i][0] = __builtin_vsx_xxlnor (sc[i][1], sc[i][2]); i++;
+  sc[i][0] = __builtin_vsx_xxlor (sc[i][1], sc[i][2]); i++;
+  sc[i][0] = __builtin_vsx_xxlxor (sc[i][1], sc[i][2]); i++;
+
+  d[i][0] = __builtin_vsx_xxland (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xxlandc (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xxlnor (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xxlor (d[i][1], d[i][2]); i++;
+  d[i][0] = __builtin_vsx_xxlxor (d[i][1], d[i][2]); i++;
+
+  f[i][0] = __builtin_vsx_xxland (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xxlandc (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xxlnor (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xxlor (f[i][1], f[i][2]); i++;
+  f[i][0] = __builtin_vsx_xxlxor (f[i][1], f[i][2]); i++;
+  return i;
+}
+
+int do_xxsldwi (void)
+{
+  int i = 0;
+
+  si[i][0] = __builtin_vsx_xxsldwi (si[i][1], si[i][2], 0); i++;
+  ss[i][0] = __builtin_vsx_xxsldwi (ss[i][1], ss[i][2], 1); i++;
+  sc[i][0] = __builtin_vsx_xxsldwi (sc[i][1], sc[i][2], 2); i++;
+  ui[i][0] = __builtin_vsx_xxsldwi (ui[i][1], ui[i][2], 3); i++;
+  us[i][0] = __builtin_vsx_xxsldwi (us[i][1], us[i][2], 0); i++;
+  uc[i][0] = __builtin_vsx_xxsldwi (uc[i][1], uc[i][2], 1); i++;
+  f[i][0] = __builtin_vsx_xxsldwi (f[i][1], f[i][2], 2); i++;
+  d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c
new file mode 100644
index 000000000..bcf486377
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c
@@ -0,0 +1,142 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xvcmpeqdp." } } */
+/* { dg-final { scan-assembler "xvcmpgtdp." } } */
+/* { dg-final { scan-assembler "xvcmpgedp." } } */
+/* { dg-final { scan-assembler "xvcmpeqsp." } } */
+/* { dg-final { scan-assembler "xvcmpgtsp." } } */
+/* { dg-final { scan-assembler "xvcmpgesp." } } */
+/* { dg-final { scan-assembler "vcmpbfp." } } */
+/* { dg-final { scan-assembler "vcmpequb." } } */
+/* { dg-final { scan-assembler "vcmpequh." } } */
+/* { dg-final { scan-assembler "vcmpequw." } } */
+/* { dg-final { scan-assembler "vcmpgtub." } } */
+/* { dg-final { scan-assembler "vcmpgtuh." } } */
+/* { dg-final { scan-assembler "vcmpgtuw." } } */
+/* { dg-final { scan-assembler "vcmpgtsb." } } */
+/* { dg-final { scan-assembler "vcmpgtsh." } } */
+/* { dg-final { scan-assembler "vcmpgtsw." } } */
+/* { dg-final { scan-assembler-not "vcmpeqfp" } } */
+/* { dg-final { scan-assembler-not "vcmpgtfp" } } */
+/* { dg-final { scan-assembler-not "vcmpgefp" } } */
+
+/* check that Altivec builtins generate VSX if -mvsx.  */
+
+#include <altivec.h>
+
+int *v16qi_s (vector signed char *a, vector signed char *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v16qi_u (vector unsigned char *a, vector unsigned char *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v8hi_s (vector short *a, vector short *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v8hi_u (vector unsigned short *a, vector unsigned short *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v4si_s (vector int *a, vector int *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v4si_u (vector unsigned int *a, vector unsigned int *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 2;
+
+  return p;
+}
+
+int *v4sf (vector float *a, vector float *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 3;
+
+  if (vec_all_in (*a, *b))	/* veccmpbfp. */
+    *p++ = 4;
+
+  return p;
+}
+
+int *v2df (vector double *a, vector double *b, int *p)
+{
+  if (vec_all_eq (*a, *b))
+    *p++ = 1;
+
+  if (vec_all_gt (*a, *b))
+    *p++ = 2;
+
+  if (vec_all_ge (*a, *b))
+    *p++ = 3;
+
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c
new file mode 100644
index 000000000..5c24dc618
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxpermdi" } } */
+/* { dg-final { scan-assembler-not "stxvd2x" } } */
+
+/* Make sure double extract doesn't use a store instruction.  */
+
+double d0(__vector double v){ return __builtin_vec_extract (v, 0); }
+double d1(__vector double v){ return __builtin_vec_extract (v, 1); }
+
+double e0(vector double v){ return __builtin_vec_ext_v2df (v, 0); }
+double e1(vector double v){ return __builtin_vec_ext_v2df (v, 1); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c
new file mode 100644
index 000000000..a722b83b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c
@@ -0,0 +1,146 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Check whether tdiv and tsqrt instructions generate the correct code.  */
+/* Each of the *tdiv* and *tsqrt* instructions should be generated exactly 3
+   times (the two calls in the _1 function should be combined).  */
+/* { dg-final { scan-assembler-times "xstdivdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtdivdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtdivsp" 3 } } */
+/* { dg-final { scan-assembler-times "xstsqrtdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtsqrtdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtsqrtsp" 3 } } */
+
+void test_div_df_1 (double a, double b, int *p)
+{
+  p[0] = __builtin_vsx_xstdivdp_fe (a, b);
+  p[1] = __builtin_vsx_xstdivdp_fg (a, b);
+}
+
+int *test_div_df_2 (double a, double b, int *p)
+{
+  if (__builtin_vsx_xstdivdp_fe (a, b))
+    *p++ = 1;
+  
+  return p;
+}
+
+int *test_div_df_3 (double a, double b, int *p)
+{
+  if (__builtin_vsx_xstdivdp_fg (a, b))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_sqrt_df_1 (double a, int *p)
+{
+  p[0] = __builtin_vsx_xstsqrtdp_fe (a);
+  p[1] = __builtin_vsx_xstsqrtdp_fg (a);
+}
+
+int *test_sqrt_df_2 (double a, int *p)
+{
+  if (__builtin_vsx_xstsqrtdp_fe (a))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_sqrt_df_3 (double a, int *p)
+{
+  if (__builtin_vsx_xstsqrtdp_fg (a))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_div_v2df_1 (__vector double *a, __vector double *b, int *p)
+{
+  p[0] = __builtin_vsx_xvtdivdp_fe (*a, *b);
+  p[1] = __builtin_vsx_xvtdivdp_fg (*a, *b);
+}
+
+int *test_div_v2df_2 (__vector double *a, __vector double *b, int *p)
+{
+  if (__builtin_vsx_xvtdivdp_fe (*a, *b))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_div_v2df_3 (__vector double *a, __vector double *b, int *p)
+{
+  if (__builtin_vsx_xvtdivdp_fg (*a, *b))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_sqrt_v2df_1 (__vector double *a, int *p)
+{
+  p[0] = __builtin_vsx_xvtsqrtdp_fe (*a);
+  p[1] = __builtin_vsx_xvtsqrtdp_fg (*a);
+}
+
+int *test_sqrt_v2df_2 (__vector double *a, int *p)
+{
+  if (__builtin_vsx_xvtsqrtdp_fe (*a))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_sqrt_v2df_3 (__vector double *a, int *p)
+{
+  if (__builtin_vsx_xvtsqrtdp_fg (*a))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_div_v4sf_1 (__vector float *a, __vector float *b, int *p)
+{
+  p[0] = __builtin_vsx_xvtdivsp_fe (*a, *b);
+  p[1] = __builtin_vsx_xvtdivsp_fg (*a, *b);
+}
+
+int *test_div_v4sf_2 (__vector float *a, __vector float *b, int *p)
+{
+  if (__builtin_vsx_xvtdivsp_fe (*a, *b))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_div_v4sf_3 (__vector float *a, __vector float *b, int *p)
+{
+  if (__builtin_vsx_xvtdivsp_fg (*a, *b))
+    *p++ = 1;
+
+  return p;
+}
+
+void test_sqrt_v4sf_1 (__vector float *a, int *p)
+{
+  p[0] = __builtin_vsx_xvtsqrtsp_fe (*a);
+  p[1] = __builtin_vsx_xvtsqrtsp_fg (*a);
+}
+
+int *test_sqrt_v4sf_2 (__vector float *a, int *p)
+{
+  if (__builtin_vsx_xvtsqrtsp_fe (*a))
+    *p++ = 1;
+
+  return p;
+}
+
+int *test_sqrt_v4sf_3 (__vector float *a, int *p)
+{
+  if (__builtin_vsx_xvtsqrtsp_fg (*a))
+    *p++ = 1;
+
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
new file mode 100644
index 000000000..55e999d38
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
@@ -0,0 +1,150 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Test simple extract/insert/slat operations.  Make sure all types are
+   supported with various options.  */
+
+#include <altivec.h>
+
+double extract_df_0_reg (vector double p) { return vec_extract (p, 0); }
+double extract_df_1_reg (vector double p) { return vec_extract (p, 1); }
+double extract_df_n_reg (vector double p, int n) { return vec_extract (p, n); }
+
+double extract_df_0_mem (vector double *p) { return vec_extract (*p, 0); }
+double extract_df_1_mem (vector double *p) { return vec_extract (*p, 1); }
+double extract_df_n_mem (vector double *p, int n) { return vec_extract (*p, n); }
+
+vector double insert_df_0 (vector double p, double x) { return vec_insert (x, p, 0); }
+vector double insert_df_1 (vector double p, double x) { return vec_insert (x, p, 1); }
+vector double insert_df_n (vector double p, double x, int n) { return vec_insert (x, p, n); }
+
+vector double splat_df_reg (double x) { return vec_splats (x); }
+vector double splat_df_mem (double *x) { return vec_splats (*x); }
+
+#ifdef _ARCH_PPC64
+#define ll long
+#else
+#define ll long long
+#endif
+
+ll extract_di_0_reg (vector ll p) { return vec_extract (p, 0); }
+ll extract_di_1_reg (vector ll p) { return vec_extract (p, 1); }
+ll extract_di_n_reg (vector ll p, int n) { return vec_extract (p, n); }
+
+ll extract_di_0_mem (vector ll *p) { return vec_extract (*p, 0); }
+ll extract_di_1_mem (vector ll *p) { return vec_extract (*p, 1); }
+ll extract_di_n_mem (vector ll *p, int n) { return vec_extract (*p, n); }
+
+vector ll insert_di_0 (vector ll p, ll x) { return vec_insert (x, p, 0); }
+vector ll insert_di_1 (vector ll p, ll x) { return vec_insert (x, p, 1); }
+vector ll insert_di_n (vector ll p, ll x, int n) { return vec_insert (x, p, n); }
+
+vector ll splat_di_reg (ll x) { return vec_splats (x); }
+vector ll splat_di_mem (ll *x) { return vec_splats (*x); }
+
+float extract_sf_0_reg (vector float p) { return vec_extract (p, 0); }
+float extract_sf_3_reg (vector float p) { return vec_extract (p, 3); }
+float extract_sf_n_reg (vector float p, int n) { return vec_extract (p, n); }
+
+float extract_sf_0_mem (vector float *p) { return vec_extract (*p, 0); }
+float extract_sf_3_mem (vector float *p) { return vec_extract (*p, 3); }
+float extract_sf_n_mem (vector float *p, int n) { return vec_extract (*p, n); }
+
+vector float insert_sf_0 (vector float p, float x) { return vec_insert (x, p, 0); }
+vector float insert_sf_3 (vector float p, float x) { return vec_insert (x, p, 3); }
+vector float insert_sf_n (vector float p, float x, int n) { return vec_insert (x, p, n); }
+
+vector float splat_sf_reg (float x) { return vec_splats (x); }
+vector float splat_sf_mem (float *x) { return vec_splats (*x); }
+
+int extract_si_0_reg (vector int p) { return vec_extract (p, 0); }
+int extract_si_3_reg (vector int p) { return vec_extract (p, 3); }
+int extract_si_n_reg (vector int p, int n) { return vec_extract (p, n); }
+
+int extract_si_0_mem (vector int *p) { return vec_extract (*p, 0); }
+int extract_si_3_mem (vector int *p) { return vec_extract (*p, 3); }
+int extract_si_n_mem (vector int *p, int n) { return vec_extract (*p, n); }
+
+vector int insert_si_0 (vector int p, int x) { return vec_insert (x, p, 0); }
+vector int insert_si_3 (vector int p, int x) { return vec_insert (x, p, 3); }
+vector int insert_si_n (vector int p, int x, int n) { return vec_insert (x, p, n); }
+
+vector int splat_si_reg (int x) { return vec_splats (x); }
+vector int splat_si_mem (int *x) { return vec_splats (*x); }
+
+unsigned int extract_usi_0_reg (vector unsigned int p) { return vec_extract (p, 0); }
+unsigned int extract_usi_3_reg (vector unsigned int p) { return vec_extract (p, 3); }
+unsigned int extract_usi_n_reg (vector unsigned int p, int n) { return vec_extract (p, n); }
+
+unsigned int extract_usi_0_mem (vector unsigned int *p) { return vec_extract (*p, 0); }
+unsigned int extract_usi_3_mem (vector unsigned int *p) { return vec_extract (*p, 3); }
+unsigned int extract_usi_n_mem (vector unsigned int *p, int n) { return vec_extract (*p, n); }
+
+vector unsigned int insert_usi_0 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, 0); }
+vector unsigned int insert_usi_3 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, 3); }
+vector unsigned int insert_usi_n (vector unsigned int p, unsigned int x, int n) { return vec_insert (x, p, n); }
+
+vector unsigned int splat_usi_reg (unsigned int x) { return vec_splats (x); }
+vector unsigned int splat_usi_mem (unsigned int *x) { return vec_splats (*x); }
+
+short extract_hi_0_reg (vector short p) { return vec_extract (p, 0); }
+short extract_hi_7_reg (vector short p) { return vec_extract (p, 7); }
+short extract_hi_n_reg (vector short p, int n) { return vec_extract (p, n); }
+
+short extract_hi_0_mem (vector short *p) { return vec_extract (*p, 0); }
+short extract_hi_7_mem (vector short *p) { return vec_extract (*p, 7); }
+short extract_hi_n_mem (vector short *p, int n) { return vec_extract (*p, n); }
+
+vector short insert_hi_0 (vector short p, short x) { return vec_insert (x, p, 0); }
+vector short insert_hi_7 (vector short p, short x) { return vec_insert (x, p, 7); }
+vector short insert_hi_n (vector short p, short x, int n) { return vec_insert (x, p, n); }
+
+vector short splat_hi_reg (short x) { return vec_splats (x); }
+vector short splat_hi_mem (short *x) { return vec_splats (*x); }
+
+unsigned short extract_uhi_0_reg (vector unsigned short p) { return vec_extract (p, 0); }
+unsigned short extract_uhi_7_reg (vector unsigned short p) { return vec_extract (p, 7); }
+unsigned short extract_uhi_n_reg (vector unsigned short p, int n) { return vec_extract (p, n); }
+
+unsigned short extract_uhi_0_mem (vector unsigned short *p) { return vec_extract (*p, 0); }
+unsigned short extract_uhi_7_mem (vector unsigned short *p) { return vec_extract (*p, 7); }
+unsigned short extract_uhi_n_mem (vector unsigned short *p, int n) { return vec_extract (*p, n); }
+
+vector unsigned short insert_uhi_0 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, 0); }
+vector unsigned short insert_uhi_7 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, 7); }
+vector unsigned short insert_uhi_n (vector unsigned short p, unsigned short x, int n) { return vec_insert (x, p, n); }
+
+vector unsigned short splat_uhi_reg (unsigned short x) { return vec_splats (x); }
+vector unsigned short splat_uhi_mem (unsigned short *x) { return vec_splats (*x); }
+
+signed char extract_qi_0_reg (vector signed char p) { return vec_extract (p, 0); }
+signed char extract_qi_1_reg5 (vector signed char p) { return vec_extract (p, 15); }
+signed char extract_qi_n_reg (vector signed char p, int n) { return vec_extract (p, n); }
+
+signed char extract_qi_0_mem (vector signed char *p) { return vec_extract (*p, 0); }
+signed char extract_qi_1_mem5 (vector signed char *p) { return vec_extract (*p, 15); }
+signed char extract_qi_n_mem (vector signed char *p, int n) { return vec_extract (*p, n); }
+
+vector signed char insert_qi_0 (vector signed char p, signed char x) { return vec_insert (x, p, 0); }
+vector signed char insert_qi_15 (vector signed char p, signed char x) { return vec_insert (x, p, 15); }
+vector signed char insert_qi_n (vector signed char p, signed char x, int n) { return vec_insert (x, p, n); }
+
+vector signed char splat_qi_reg (signed char x) { return vec_splats (x); }
+vector signed char splat_qi_mem (signed char *x) { return vec_splats (*x); }
+
+unsigned char extract_uqi_0_reg (vector unsigned char p) { return vec_extract (p, 0); }
+unsigned char extract_uqi_1_reg5 (vector unsigned char p) { return vec_extract (p, 15); }
+unsigned char extract_uqi_n_reg (vector unsigned char p, int n) { return vec_extract (p, n); }
+
+unsigned char extract_uqi_0_mem (vector unsigned char *p) { return vec_extract (*p, 0); }
+unsigned char extract_uqi_1_mem5 (vector unsigned char *p) { return vec_extract (*p, 15); }
+unsigned char extract_uqi_n_mem (vector unsigned char *p, int n) { return vec_extract (*p, n); }
+
+vector unsigned char insert_uqi_0 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, 0); }
+vector unsigned char insert_uqi_15 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, 15); }
+vector unsigned char insert_uqi_n (vector unsigned char p, unsigned char x, int n) { return vec_insert (x, p, n); }
+
+vector unsigned char splat_uqi_reg (unsigned char x) { return vec_splats (x); }
+vector unsigned char splat_uqi_mem (unsigned char *x) { return vec_splats (*x); }
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c
new file mode 100644
index 000000000..836b3851c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c
@@ -0,0 +1,97 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -mcpu=power7" } */
+
+/* Test the various load/store varients.  */
+
+#include <altivec.h>
+
+#define TEST_COPY(NAME, TYPE)						\
+void NAME ## _copy_native (vector TYPE *a, vector TYPE *b)		\
+{									\
+  *a = *b;								\
+}									\
+									\
+void NAME ## _copy_vec (vector TYPE *a, vector TYPE *b)			\
+{									\
+  vector TYPE x = vec_ld (0, b);					\
+  vec_st (x, 0, a);							\
+}									\
+
+#define TEST_COPYL(NAME, TYPE)						\
+void NAME ## _lvxl (vector TYPE *a, vector TYPE *b)			\
+{									\
+  vector TYPE x = vec_ldl (0, b);					\
+  vec_stl (x, 0, a);							\
+}									\
+
+#define TEST_VSX_COPY(NAME, TYPE)					\
+void NAME ## _copy_vsx (vector TYPE *a, vector TYPE *b)			\
+{									\
+  vector TYPE x = vec_vsx_ld (0, b);					\
+  vec_vsx_st (x, 0, a);							\
+}									\
+
+#define TEST_ALIGN(NAME, TYPE)						\
+void NAME ## _align (vector unsigned char *a, TYPE *b)			\
+{									\
+  vector unsigned char x = vec_lvsl (0, b);				\
+  vector unsigned char y = vec_lvsr (0, b);				\
+  vec_st (x, 0, a);							\
+  vec_st (y, 8, a);							\
+}
+
+#ifndef NO_COPY
+TEST_COPY(uchar,  unsigned char)
+TEST_COPY(schar,  signed   char)
+TEST_COPY(bchar,  bool     char)
+TEST_COPY(ushort, unsigned short)
+TEST_COPY(sshort, signed   short)
+TEST_COPY(bshort, bool     short)
+TEST_COPY(uint,   unsigned int)
+TEST_COPY(sint,   signed   int)
+TEST_COPY(bint,   bool     int)
+TEST_COPY(float,  float)
+TEST_COPY(double, double)
+#endif	/* NO_COPY */
+
+#ifndef NO_COPYL
+TEST_COPYL(uchar,  unsigned char)
+TEST_COPYL(schar,  signed   char)
+TEST_COPYL(bchar,  bool     char)
+TEST_COPYL(ushort, unsigned short)
+TEST_COPYL(sshort, signed   short)
+TEST_COPYL(bshort, bool     short)
+TEST_COPYL(uint,   unsigned int)
+TEST_COPYL(sint,   signed   int)
+TEST_COPYL(bint,   bool     int)
+TEST_COPYL(float,  float)
+TEST_COPYL(double, double)
+#endif	/* NO_COPYL */
+
+#ifndef NO_ALIGN
+TEST_ALIGN(uchar,  unsigned char)
+TEST_ALIGN(schar,  signed   char)
+TEST_ALIGN(ushort, unsigned short)
+TEST_ALIGN(sshort, signed   short)
+TEST_ALIGN(uint,   unsigned int)
+TEST_ALIGN(sint,   signed   int)
+TEST_ALIGN(float,  float)
+TEST_ALIGN(double, double)
+#endif	/* NO_ALIGN */
+
+
+#ifndef NO_VSX_COPY
+TEST_VSX_COPY(uchar,  unsigned char)
+TEST_VSX_COPY(schar,  signed   char)
+TEST_VSX_COPY(bchar,  bool     char)
+TEST_VSX_COPY(ushort, unsigned short)
+TEST_VSX_COPY(sshort, signed   short)
+TEST_VSX_COPY(bshort, bool     short)
+TEST_VSX_COPY(uint,   unsigned int)
+TEST_VSX_COPY(sint,   signed   int)
+TEST_VSX_COPY(bint,   bool     int)
+TEST_VSX_COPY(float,  float)
+TEST_VSX_COPY(double, double)
+#endif	/* NO_VSX_COPY */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-float0.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-float0.c
new file mode 100644
index 000000000..7e4fea689
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-float0.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler "xxlxor" } } */
+
+/* Test that we generate xxlor to clear a SFmode register.  */
+
+float sum (float *p, unsigned long n)
+{
+  float sum = 0.0f;	/* generate xxlxor instead of load */
+  while (n-- > 0)
+    sum += *p++;
+
+  return sum;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c
new file mode 100644
index 000000000..adb5c9fae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-mass-1.c
@@ -0,0 +1,554 @@
+/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O3 -ftree-vectorize -mcpu=power7 -ffast-math -mveclibabi=mass" } */
+/* { dg-final { scan-assembler "bl\[\\. \]+atan2d2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+atan2f4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+hypotd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+hypotf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+powd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+powf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+acosd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+acosf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+acoshd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+acoshf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+asind2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+asinf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+asinhd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+asinhf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+atand2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+atanf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+atanhd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+atanhf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+cbrtd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+cbrtf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+cosd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+cosf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+coshd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+coshf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+erfd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+erff4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+erfcd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+erfcf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+exp2d2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+exp2f4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+expd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+expf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+expm1d2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+expm1f4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+lgamma" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+lgammaf" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+log10d2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+log10f4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+log1pd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+log1pf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+log2d2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+log2f4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+logd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+logf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+sind2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+sinf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+sinhd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+sinhf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+tand2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+tanf4" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+tanhd2" } } */
+/* { dg-final { scan-assembler "bl\[\\. \]+tanhf4" } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+double d1[SIZE] __attribute__((__aligned__(32)));
+double d2[SIZE] __attribute__((__aligned__(32)));
+double d3[SIZE] __attribute__((__aligned__(32)));
+
+float f1[SIZE] __attribute__((__aligned__(32)));
+float f2[SIZE] __attribute__((__aligned__(32)));
+float f3[SIZE] __attribute__((__aligned__(32)));
+
+void
+test_double_atan2 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_atan2 (d2[i], d3[i]);
+}
+
+void
+test_float_atan2 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_atan2f (f2[i], f3[i]);
+}
+
+void
+test_double_hypot (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_hypot (d2[i], d3[i]);
+}
+
+void
+test_float_hypot (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_hypotf (f2[i], f3[i]);
+}
+
+void
+test_double_pow (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_pow (d2[i], d3[i]);
+}
+
+void
+test_float_pow (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_powf (f2[i], f3[i]);
+}
+
+void
+test_double_acos (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_acos (d2[i]);
+}
+
+void
+test_float_acos (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_acosf (f2[i]);
+}
+
+void
+test_double_acosh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_acosh (d2[i]);
+}
+
+void
+test_float_acosh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_acoshf (f2[i]);
+}
+
+void
+test_double_asin (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_asin (d2[i]);
+}
+
+void
+test_float_asin (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_asinf (f2[i]);
+}
+
+void
+test_double_asinh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_asinh (d2[i]);
+}
+
+void
+test_float_asinh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_asinhf (f2[i]);
+}
+
+void
+test_double_atan (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_atan (d2[i]);
+}
+
+void
+test_float_atan (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_atanf (f2[i]);
+}
+
+void
+test_double_atanh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_atanh (d2[i]);
+}
+
+void
+test_float_atanh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_atanhf (f2[i]);
+}
+
+void
+test_double_cbrt (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_cbrt (d2[i]);
+}
+
+void
+test_float_cbrt (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_cbrtf (f2[i]);
+}
+
+void
+test_double_cos (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_cos (d2[i]);
+}
+
+void
+test_float_cos (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_cosf (f2[i]);
+}
+
+void
+test_double_cosh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_cosh (d2[i]);
+}
+
+void
+test_float_cosh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_coshf (f2[i]);
+}
+
+void
+test_double_erf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_erf (d2[i]);
+}
+
+void
+test_float_erf (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_erff (f2[i]);
+}
+
+void
+test_double_erfc (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_erfc (d2[i]);
+}
+
+void
+test_float_erfc (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_erfcf (f2[i]);
+}
+
+void
+test_double_exp2 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_exp2 (d2[i]);
+}
+
+void
+test_float_exp2 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_exp2f (f2[i]);
+}
+
+void
+test_double_exp (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_exp (d2[i]);
+}
+
+void
+test_float_exp (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_expf (f2[i]);
+}
+
+void
+test_double_expm1 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_expm1 (d2[i]);
+}
+
+void
+test_float_expm1 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_expm1f (f2[i]);
+}
+
+void
+test_double_lgamma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_lgamma (d2[i]);
+}
+
+void
+test_float_lgamma (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_lgammaf (f2[i]);
+}
+
+void
+test_double_log10 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_log10 (d2[i]);
+}
+
+void
+test_float_log10 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_log10f (f2[i]);
+}
+
+void
+test_double_log1p (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_log1p (d2[i]);
+}
+
+void
+test_float_log1p (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_log1pf (f2[i]);
+}
+
+void
+test_double_log2 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_log2 (d2[i]);
+}
+
+void
+test_float_log2 (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_log2f (f2[i]);
+}
+
+void
+test_double_log (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_log (d2[i]);
+}
+
+void
+test_float_log (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_logf (f2[i]);
+}
+
+void
+test_double_sin (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_sin (d2[i]);
+}
+
+void
+test_float_sin (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_sinf (f2[i]);
+}
+
+void
+test_double_sinh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_sinh (d2[i]);
+}
+
+void
+test_float_sinh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_sinhf (f2[i]);
+}
+
+void
+test_double_sqrt (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_sqrt (d2[i]);
+}
+
+void
+test_float_sqrt (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_sqrtf (f2[i]);
+}
+
+void
+test_double_tan (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_tan (d2[i]);
+}
+
+void
+test_float_tan (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_tanf (f2[i]);
+}
+
+void
+test_double_tanh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    d1[i] = __builtin_tanh (d2[i]);
+}
+
+void
+test_float_tanh (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    f1[i] = __builtin_tanhf (f2[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c
new file mode 100644
index 000000000..d05ee19d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-sfminmax.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler "xsmaxdp" } } */
+/* { dg-final { scan-assembler "xsmindp" } } */
+
+float
+do_fmin (float a, float b)
+{
+  return __builtin_fminf (a, b);
+}
+
+float
+do_fmax (float a, float b)
+{
+  return __builtin_fmaxf (a, b);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
new file mode 100644
index 000000000..5d23c0ae3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c
@@ -0,0 +1,152 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler "xvadddp" } } */
+/* { dg-final { scan-assembler "xvsubdp" } } */
+/* { dg-final { scan-assembler "xvmuldp" } } */
+/* { dg-final { scan-assembler "xvdivdp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+/* { dg-final { scan-assembler "xvsqrtdp" } } */
+/* { dg-final { scan-assembler "xvcpsgndp" } } */
+/* { dg-final { scan-assembler "xvrdpim" } } */
+/* { dg-final { scan-assembler "xvrdpip" } } */
+/* { dg-final { scan-assembler "xvrdpiz" } } */
+/* { dg-final { scan-assembler "xvrdpic" } } */
+/* { dg-final { scan-assembler "xvrdpi " } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+double a[SIZE] __attribute__((__aligned__(32)));
+double b[SIZE] __attribute__((__aligned__(32)));
+double c[SIZE] __attribute__((__aligned__(32)));
+double d[SIZE] __attribute__((__aligned__(32)));
+double e[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
+
+void
+vector_subtract (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] - c[i];
+}
+
+void
+vector_multiply (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] * c[i];
+}
+
+void
+vector_multiply_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = (b[i] * c[i]) + d[i];
+}
+
+void
+vector_multiply_subtract (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = (b[i] * c[i]) - d[i];
+}
+
+void
+vector_divide (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] / c[i];
+}
+
+extern double sqrt (double);
+extern double floor (double);
+extern double ceil (double);
+extern double trunc (double);
+extern double nearbyint (double);
+extern double rint (double);
+extern double copysign (double, double);
+
+void
+vector_sqrt (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = sqrt (b[i]);
+}
+
+void
+vector_floor (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = floor (b[i]);
+}
+
+void
+vector_ceil (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = ceil (b[i]);
+}
+
+void
+vector_trunc (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = trunc (b[i]);
+}
+
+void
+vector_nearbyint (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = nearbyint (b[i]);
+}
+
+void
+vector_rint (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = rint (b[i]);
+}
+
+void
+vector_copysign (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = copysign (b[i], c[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
new file mode 100644
index 000000000..404e0403f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c
@@ -0,0 +1,152 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -ffast-math" } */
+/* { dg-final { scan-assembler "xvaddsp" } } */
+/* { dg-final { scan-assembler "xvsubsp" } } */
+/* { dg-final { scan-assembler "xvmulsp" } } */
+/* { dg-final { scan-assembler "xvdivsp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+/* { dg-final { scan-assembler "xvsqrtsp" } } */
+/* { dg-final { scan-assembler "xvcpsgnsp" } } */
+/* { dg-final { scan-assembler "xvrspim" } } */
+/* { dg-final { scan-assembler "xvrspip" } } */
+/* { dg-final { scan-assembler "xvrspiz" } } */
+/* { dg-final { scan-assembler "xvrspic" } } */
+/* { dg-final { scan-assembler "xvrspi " } } */
+
+#ifndef SIZE
+#define SIZE 1024
+#endif
+
+float a[SIZE] __attribute__((__aligned__(32)));
+float b[SIZE] __attribute__((__aligned__(32)));
+float c[SIZE] __attribute__((__aligned__(32)));
+float d[SIZE] __attribute__((__aligned__(32)));
+float e[SIZE] __attribute__((__aligned__(32)));
+
+void
+vector_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] + c[i];
+}
+
+void
+vector_subtract (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] - c[i];
+}
+
+void
+vector_multiply (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] * c[i];
+}
+
+void
+vector_multiply_add (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = (b[i] * c[i]) + d[i];
+}
+
+void
+vector_multiply_subtract (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = (b[i] * c[i]) - d[i];
+}
+
+void
+vector_divide (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = b[i] / c[i];
+}
+
+extern float sqrtf (float);
+extern float floorf (float);
+extern float ceilf (float);
+extern float truncf (float);
+extern float nearbyintf (float);
+extern float rintf (float);
+extern float copysignf (float, float);
+
+void
+vector_sqrt (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = sqrtf (b[i]);
+}
+
+void
+vector_floor (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = floorf (b[i]);
+}
+
+void
+vector_ceil (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = ceilf (b[i]);
+}
+
+void
+vector_trunc (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = truncf (b[i]);
+}
+
+void
+vector_nearbyint (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = nearbyintf (b[i]);
+}
+
+void
+vector_rint (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = rintf (b[i]);
+}
+
+void
+vector_copysign (void)
+{
+  int i;
+
+  for (i = 0; i < SIZE; i++)
+    a[i] = copysignf (b[i], c[i]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c
new file mode 100644
index 000000000..25cf376f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power7" } */
+/* { dg-final { scan-assembler "xvadddp" } } */
+/* { dg-final { scan-assembler "xvsubdp" } } */
+/* { dg-final { scan-assembler "xvmuldp" } } */
+/* { dg-final { scan-assembler "xvdivdp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+
+__vector double a, b, c, d;
+
+void
+vector_add (void)
+{
+  a = b + c;
+}
+
+void
+vector_subtract (void)
+{
+  a = b - c;
+}
+
+void
+vector_multiply (void)
+{
+  a = b * c;
+}
+
+void
+vector_multiply_add (void)
+{
+  a = (b * c) + d;
+}
+
+void
+vector_multiply_subtract (void)
+{
+  a = (b * c) - d;
+}
+
+void
+vector_divide (void)
+{
+  a = b / c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c
new file mode 100644
index 000000000..f2a9c59df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -ftree-vectorize -mcpu=power7" } */
+/* { dg-final { scan-assembler "xvaddsp" } } */
+/* { dg-final { scan-assembler "xvsubsp" } } */
+/* { dg-final { scan-assembler "xvmulsp" } } */
+/* { dg-final { scan-assembler "xvdivsp" } } */
+/* { dg-final { scan-assembler "xvmadd" } } */
+/* { dg-final { scan-assembler "xvmsub" } } */
+
+__vector float a, b, c, d;
+
+void
+vector_add (void)
+{
+  a = b + c;
+}
+
+void
+vector_subtract (void)
+{
+  a = b - c;
+}
+
+void
+vector_multiply (void)
+{
+  a = b * c;
+}
+
+void
+vector_multiply_add (void)
+{
+  a = (b * c) + d;
+}
+
+void
+vector_multiply_subtract (void)
+{
+  a = (b * c) - d;
+}
+
+void
+vector_divide (void)
+{
+  a = b / c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
new file mode 100644
index 000000000..65843e93f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -0,0 +1,392 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+/* This will run, and someday we should add the support to test whether we are
+   running on VSX hardware.  */
+
+#include <altivec.h>
+#include <stdlib.h>
+
+#ifdef DEBUG
+#include <stdio.h>
+
+static int errors = 0;
+#endif
+
+union args {
+  double scalar[2];
+  vector double vect;
+};
+
+union largs {
+  unsigned long scalar[2];
+  vector bool long vect;
+};
+
+static void
+do_test (union args *expected, union args *got, const char *name)
+{
+  if (expected->scalar[0] != got->scalar[0]
+      || expected->scalar[1] != got->scalar[1])
+    {
+#ifdef DEBUG
+      printf ("%s failed!\n", name);
+      errors++;
+#else
+      abort ();
+#endif
+    }
+}
+
+static void
+do_ltest (union largs *expected, union largs *got, const char *name)
+{
+  if (expected->scalar[0] != got->scalar[0]
+      || expected->scalar[1] != got->scalar[1])
+    {
+#ifdef DEBUG
+      printf ("%s failed!\n", name);
+      errors++;
+#else
+      abort ();
+#endif
+    }
+}
+
+
+/* Vec functions taking a single argument.  */
+static vector double
+vabs (vector double arg)
+{
+  return vec_abs (arg);
+}
+
+static vector double
+vceil (vector double arg)
+{
+  return vec_ceil (arg);
+}
+
+static vector double
+vfloor (vector double arg)
+{
+  return vec_floor (arg);
+}
+
+static vector double
+vnearbyint (vector double arg)
+{
+  return vec_nearbyint (arg);
+}
+
+static vector double
+vrint (vector double arg)
+{
+  return vec_rint (arg);
+}
+
+static vector double
+vsqrt (vector double arg)
+{
+  return vec_sqrt (arg);
+}
+
+/* Single argument tests.  */
+static struct
+{
+  union args result;
+  union args input;
+  vector double (*func) (vector double);
+  const char *name;
+} arg1_tests[] = {
+  /* result		input			function	name */
+  { {  1.0,  2.0 },	{ -1.0,  2.0 },		vabs,		"vabs" },
+  { {  1.0,  2.0 },	{  1.0, -2.0 },		vabs,		"vabs" },
+  { {  2.0,  2.0 },	{  1.1,  1.7 },		vceil,		"vceil" },
+  { { -1.0, -1.0 },	{ -1.1, -1.7 },		vceil,		"vceil" },
+  { { -1.0,  2.0 },	{ -1.5,  1.5 },		vceil,		"vceil" },
+  { {  1.0,  1.0 },	{  1.1,  1.7 },		vfloor,		"vfloor" },
+  { { -2.0, -2.0 },	{ -1.1, -1.7 },		vfloor,		"vfloor" },
+  { { -2.0,  1.0 },	{ -1.5,  1.5 },		vfloor,		"vfloor" },
+  { {  1.0,  2.0 },	{  1.1,  1.7 },		vnearbyint,	"vnearbyint" },
+  { { -1.0, -2.0 },	{ -1.1, -1.7 },		vnearbyint,	"vnearbyint" },
+  { { -2.0,  2.0 },	{ -1.5,  1.5 },		vnearbyint,	"vnearbyint" },
+  { {  1.0,  2.0 },	{  1.1,  1.7 },		vrint,		"vrint" },
+  { { -1.0, -2.0 },	{ -1.1, -1.7 },		vrint,		"vrint" },
+  { { -2.0,  2.0 },	{ -1.5,  1.5 },		vrint,		"vrint" },
+  { {  2.0,  4.0 },	{  4.0, 16.0 },		vsqrt,		"vsqrt" },
+};
+
+static void
+test_arg1 (void)
+{
+  unsigned i;
+
+#ifdef DEBUG
+  printf ("Single argument tests:\n");
+#endif
+
+  for (i = 0; i < sizeof (arg1_tests) / sizeof (arg1_tests[0]); i++)
+    {
+      union args u;
+      u.vect = arg1_tests[i].func (arg1_tests[i].input.vect);
+
+#ifdef DEBUG
+      printf ("test %-16s: expected { %4g, %4g }, got { %4g, %4g }, input { %4g, %4g }\n",
+	      arg1_tests[i].name,
+	      arg1_tests[i].result.scalar[0],
+	      arg1_tests[i].result.scalar[1],
+	      u.scalar[0],
+	      u.scalar[1],
+	      arg1_tests[i].input.scalar[0],
+	      arg1_tests[i].input.scalar[1]);
+#endif
+
+      do_test (&arg1_tests[i].result, &u, arg1_tests[i].name);
+    }
+
+  return;
+}
+
+
+/* Vect functions taking 2 arguments.  */
+static vector double
+vadd (vector double arg1, vector double arg2)
+{
+  return vec_add (arg1, arg2);
+}
+
+static vector double
+vadd2 (vector double arg1, vector double arg2)
+{
+  return arg1 + arg2;
+}
+
+static vector double
+vsub (vector double arg1, vector double arg2)
+{
+  return vec_sub (arg1, arg2);
+}
+
+static vector double
+vsub2 (vector double arg1, vector double arg2)
+{
+  return arg1 - arg2;
+}
+
+static vector double
+vmul (vector double arg1, vector double arg2)
+{
+  return vec_mul (arg1, arg2);
+}
+
+static vector double
+vmul2 (vector double arg1, vector double arg2)
+{
+  return arg1 * arg2;
+}
+
+static vector double
+vdiv (vector double arg1, vector double arg2)
+{
+  return vec_div (arg1, arg2);
+}
+
+static vector double
+vdiv2 (vector double arg1, vector double arg2)
+{
+  return arg1 / arg2;
+}
+
+static vector double
+vmax (vector double arg1, vector double arg2)
+{
+  return vec_max (arg1, arg2);
+}
+
+static vector double
+vmin (vector double arg1, vector double arg2)
+{
+  return vec_min (arg1, arg2);
+}
+
+/* 2 argument tests.  */
+static struct
+{
+  union args result;
+  union args input[2];
+  vector double (*func) (vector double, vector double);
+  const char *name;
+} arg2_tests[] = {
+  /* result */
+  { {  4.0,  6.0 },	{ {  1.0,  2.0 }, {  3.0,  4.0 } },	vadd,	"vadd"  },
+  { {  4.0, -6.0 },	{ {  1.0, -2.0 }, {  3.0, -4.0 } },	vadd,	"vadd"  },
+  { {  4.0,  6.0 },	{ {  1.0,  2.0 }, {  3.0,  4.0 } },	vadd2,	"vadd2" },
+  { {  4.0, -6.0 },	{ {  1.0, -2.0 }, {  3.0, -4.0 } },	vadd2,	"vadd2" },
+  { { -2.0, -2.0 },	{ {  1.0,  2.0 }, {  3.0,  4.0 } },	vsub,	"vsub"  },
+  { { -2.0,  2.0 },	{ {  1.0, -2.0 }, {  3.0, -4.0 } },	vsub,	"vsub"  },
+  { { -2.0, -2.0 },	{ {  1.0,  2.0 }, {  3.0,  4.0 } },	vsub2,	"vsub2" },
+  { { -2.0,  2.0 },	{ {  1.0, -2.0 }, {  3.0, -4.0 } },	vsub2,	"vsub2" },
+  { {  6.0,  4.0 },	{ {  2.0,  8.0 }, {  3.0,  0.5 } },	vmul,	"vmul"  },
+  { {  6.0,  4.0 },	{ {  2.0,  8.0 }, {  3.0,  0.5 } },	vmul2,	"vmul2" },
+  { {  2.0,  0.5 },	{ {  6.0,  4.0 }, {  3.0,  8.0 } },	vdiv,	"vdiv"  },
+  { {  2.0,  0.5 },	{ {  6.0,  4.0 }, {  3.0,  8.0 } },	vdiv2,	"vdiv2" },
+  { {  3.0,  4.0 },	{ {  1.0,  2.0 }, {  3.0,  4.0 } },	vmax,	"vmax"  },
+  { {  1.0,  4.0 },	{ {  1.0, -2.0 }, { -3.0,  4.0 } },	vmax,	"vmax"  },
+  { {  1.0,  2.0 },	{ {  1.0,  2.0 }, {  3.0,  4.0 } },	vmin,	"vmin"  },
+  { { -3.0, -2.0 },	{ {  1.0, -2.0 }, { -3.0,  4.0 } },	vmin,	"vmin"  },
+};
+
+static void
+test_arg2 (void)
+{
+  unsigned i;
+
+#ifdef DEBUG
+  printf ("\nTwo argument tests:\n");
+#endif
+
+  for (i = 0; i < sizeof (arg2_tests) / sizeof (arg2_tests[0]); i++)
+    {
+      union args u;
+      u.vect = arg2_tests[i].func (arg2_tests[i].input[0].vect,
+				   arg2_tests[i].input[1].vect);
+
+#ifdef DEBUG
+      printf ("test %-16s: expected { %4g, %4g }, got { %4g, %4g }, input { %4g, %4g }, { %4g, %4g }\n",
+	      arg2_tests[i].name,
+	      arg2_tests[i].result.scalar[0],
+	      arg2_tests[i].result.scalar[1],
+	      u.scalar[0],
+	      u.scalar[1],
+	      arg2_tests[i].input[0].scalar[0],
+	      arg2_tests[i].input[0].scalar[1],
+	      arg2_tests[i].input[1].scalar[0],
+	      arg2_tests[i].input[1].scalar[1]);
+#endif
+
+      do_test (&arg2_tests[i].result, &u, arg2_tests[i].name);
+    }
+
+  return;
+}
+
+
+/* Comparisons, returnning a boolean vector.  */
+static vector bool long
+vcmpeq (vector double arg1, vector double arg2)
+{
+  return vec_cmpeq (arg1, arg2);
+}
+
+static vector bool long
+vcmplt (vector double arg1, vector double arg2)
+{
+  return vec_cmplt (arg1, arg2);
+}
+
+static vector bool long
+vcmple (vector double arg1, vector double arg2)
+{
+  return vec_cmple (arg1, arg2);
+}
+
+static vector bool long
+vcmpgt (vector double arg1, vector double arg2)
+{
+  return vec_cmpgt (arg1, arg2);
+}
+
+static vector bool long
+vcmpge (vector double arg1, vector double arg2)
+{
+  return vec_cmpge (arg1, arg2);
+}
+
+#define ONE  0xffffffffffffffffUL
+#define ZERO 0x0000000000000000UL
+
+/* comparison tests.  */
+static struct
+{
+  union largs result;
+  union args input[2];
+  vector bool long (*func) (vector double, vector double);
+  const char *name;
+} argcmp_tests[] = {
+  { { ONE,  ZERO }, { {  1.0,  2.0 }, {  1.0, -2.0 } },	vcmpeq,	"vcmpeq" },
+  { { ZERO, ONE  }, { { -1.0,  2.0 }, {  1.0,  2.0 } },	vcmpeq,	"vcmpeq" },
+
+  { { ONE,  ONE  }, { {  1.0, -2.0 }, {  1.0, -2.0 } },	vcmple,	"vcmple" },
+  { { ONE,  ONE  }, { {  1.0, -2.0 }, {  2.0, -1.0 } },	vcmple,	"vcmple" },
+  { { ZERO, ZERO }, { {  2.0, -1.0 }, {  1.0, -2.0 } },	vcmple,	"vcmple" },
+
+  { { ZERO, ZERO }, { {  1.0, -2.0 }, {  1.0, -2.0 } },	vcmplt,	"vcmplt" },
+  { { ONE,  ONE  }, { {  1.0, -2.0 }, {  2.0, -1.0 } },	vcmplt,	"vcmplt" },
+  { { ZERO, ZERO }, { {  2.0, -1.0 }, {  1.0, -2.0 } },	vcmplt,	"vcmplt" },
+
+  { { ZERO, ZERO }, { {  1.0, -2.0 }, {  1.0, -2.0 } },	vcmpgt,	"vcmpgt" },
+  { { ZERO, ZERO }, { {  1.0, -2.0 }, {  2.0, -1.0 } },	vcmpgt,	"vcmpgt" },
+  { { ONE,  ONE  }, { {  2.0, -1.0 }, {  1.0, -2.0 } },	vcmpgt,	"vcmpgt" },
+
+  { { ONE,  ONE  }, { {  1.0, -2.0 }, {  1.0, -2.0 } },	vcmpge,	"vcmpge" },
+  { { ZERO, ZERO }, { {  1.0, -2.0 }, {  2.0, -1.0 } },	vcmpge,	"vcmpge" },
+  { { ONE,  ONE  }, { {  2.0, -1.0 }, {  1.0, -2.0 } },	vcmpge,	"vcmpge" },
+};
+
+static void
+test_argcmp (void)
+{
+  unsigned i;
+
+#ifdef DEBUG
+  printf ("\nComparison tests:\n");
+#endif
+
+  for (i = 0; i < sizeof (argcmp_tests) / sizeof (argcmp_tests[0]); i++)
+    {
+      union largs u;
+      u.vect = argcmp_tests[i].func (argcmp_tests[i].input[0].vect,
+				     argcmp_tests[i].input[1].vect);
+
+#ifdef DEBUG
+      printf ("test %-16s: expected { 0x%016lx, 0x%016lx }, got { 0x%016lx, 0x%016lx }, input { %4g, %4g }, { %4g, %4g }\n",
+	      argcmp_tests[i].name,
+	      argcmp_tests[i].result.scalar[0],
+	      argcmp_tests[i].result.scalar[1],
+	      u.scalar[0],
+	      u.scalar[1],
+	      argcmp_tests[i].input[0].scalar[0],
+	      argcmp_tests[i].input[0].scalar[1],
+	      argcmp_tests[i].input[1].scalar[0],
+	      argcmp_tests[i].input[1].scalar[1]);
+#endif
+
+      do_ltest (&argcmp_tests[i].result, &u, argcmp_tests[i].name);
+    }
+
+  return;
+}
+
+
+int
+main (int argc, char *argv[])
+{
+  test_arg1 ();
+  test_arg2 ();
+  test_argcmp ();
+
+#ifdef DEBUG
+  if (errors)
+    {
+      printf ("There were %d error(s)\n", errors);
+      return errors;
+    }
+  else
+    printf ("There were no errors\n");
+#endif
+  
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c
new file mode 100644
index 000000000..f8e644bb5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.c
@@ -0,0 +1,81 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2" } */
+
+#include <altivec.h>
+
+void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b, vector unsigned char *p_uc, int *i)
+{
+  vector double in0 = in[0];
+  vector double in1 = in[1];
+  vector double in2 = in[2];
+  vector long inl = *p_l;
+  vector bool long inb = *p_b;
+  vector unsigned char uc = *p_uc;
+
+  *out++ = vec_abs (in0);
+  *out++ = vec_add (in0, in1);
+  *out++ = vec_and (in0, in1);
+  *out++ = vec_and (in0, inb);
+  *out++ = vec_and (inb, in0);
+  *out++ = vec_andc (in0, in1);
+  *out++ = vec_andc (in0, inb);
+  *out++ = vec_andc (inb, in0);
+  *out++ = vec_ceil (in0);
+  *p_b++ = vec_cmpeq (in0, in1);
+  *p_b++ = vec_cmpgt (in0, in1);
+  *p_b++ = vec_cmpge (in0, in1);
+  *p_b++ = vec_cmplt (in0, in1);
+  *p_b++ = vec_cmple (in0, in1);
+  *out++ = vec_div (in0, in1);
+  *out++ = vec_floor (in0);
+  *out++ = vec_madd (in0, in1, in2);
+  *out++ = vec_msub (in0, in1, in2);
+  *out++ = vec_max (in0, in1);
+  *out++ = vec_min (in0, in1);
+  *out++ = vec_msub (in0, in1, in2);
+  *out++ = vec_mul (in0, in1);
+  *out++ = vec_nearbyint (in0);
+  *out++ = vec_nmadd (in0, in1, in2);
+  *out++ = vec_nmsub (in0, in1, in2);
+  *out++ = vec_nor (in0, in1);
+  *out++ = vec_or (in0, in1);
+  *out++ = vec_or (in0, inb);
+  *out++ = vec_or (inb, in0);
+  *out++ = vec_perm (in0, in1, uc);
+  *out++ = vec_rint (in0);
+  *out++ = vec_sel (in0, in1, inl);
+  *out++ = vec_sel (in0, in1, inb);
+  *out++ = vec_sub (in0, in1);
+  *out++ = vec_sqrt (in0);
+  *out++ = vec_trunc (in0);
+  *out++ = vec_xor (in0, in1);
+  *out++ = vec_xor (in0, inb);
+  *out++ = vec_xor (inb, in0);
+
+  *i++ = vec_all_eq (in0, in1);
+  *i++ = vec_all_ge (in0, in1);
+  *i++ = vec_all_gt (in0, in1);
+  *i++ = vec_all_le (in0, in1);
+  *i++ = vec_all_lt (in0, in1);
+  *i++ = vec_all_nan (in0);
+  *i++ = vec_all_ne (in0, in1);
+  *i++ = vec_all_nge (in0, in1);
+  *i++ = vec_all_ngt (in0, in1);
+  *i++ = vec_all_nle (in0, in1);
+  *i++ = vec_all_nlt (in0, in1);
+  *i++ = vec_all_numeric (in0);
+  *i++ = vec_any_eq (in0, in1);
+  *i++ = vec_any_ge (in0, in1);
+  *i++ = vec_any_gt (in0, in1);
+  *i++ = vec_any_le (in0, in1);
+  *i++ = vec_any_lt (in0, in1);
+  *i++ = vec_any_nan (in0);
+  *i++ = vec_any_ne (in0, in1);
+  *i++ = vec_any_nge (in0, in1);
+  *i++ = vec_any_ngt (in0, in1);
+  *i++ = vec_any_nle (in0, in1);
+  *i++ = vec_any_nlt (in0, in1);
+  *i++ = vec_any_numeric (in0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c
new file mode 100644
index 000000000..2538ad987
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-1.c
@@ -0,0 +1,54 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */
+
+/* Taken from vect/vect-align-1.c.  */
+#include <stdlib.h>
+#include <stdarg.h>
+
+/* Compile time known misalignment. Cannot use loop peeling to align
+   the store.  */
+
+#define N 16
+
+struct foo {
+  char x;
+  int y[N];
+} __attribute__((packed));
+
+int x[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
+
+__attribute__ ((noinline)) int
+main1 (struct foo * __restrict__ p)
+{
+  int i;
+
+  for (i = 0; i < N; i++)
+    {
+      p->y[i] = x[i];
+    }
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (p->y[i] != x[i])
+	abort ();
+    }
+  return 0;
+}
+
+
+int main (void)
+{
+  int i;
+  struct foo *p = malloc (2*sizeof (struct foo));
+  
+  main1 (p);
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c
new file mode 100644
index 000000000..7bb7db0fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-2.c
@@ -0,0 +1,64 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */
+
+/* Taken from vect/vect-95.c.  */
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define N 256
+
+__attribute__ ((noinline))
+void bar (float *pd, float *pa, float *pb, float *pc) 
+{
+  int i;
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (pa[i] != (pb[i] * pc[i]))
+	abort ();
+      if (pd[i] != 5.0)
+	abort ();
+    }
+
+  return;
+}
+
+
+__attribute__ ((noinline)) int
+main1 (int n, float * __restrict__ pd, float * __restrict__ pa, float * __restrict__ pb, float * __restrict__ pc)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      pa[i] = pb[i] * pc[i];
+      pd[i] = 5.0;
+    }
+
+  bar (pd,pa,pb,pc);
+
+  return 0;
+}
+
+int main (void)
+{
+  int i;
+  float a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  float d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  float b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57};
+  float c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19};
+
+  main1 (N,&d[1],a,b,c);
+  main1 (N-2,&d[1],a,b,c);
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" {xfail {! vect_hw_misalign } } } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c
new file mode 100644
index 000000000..b99bcca49
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-3.c
@@ -0,0 +1,60 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */
+
+/* Taken from vect/vect-95.c.  */
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define N 256
+
+__attribute__ ((noinline))
+void bar (short *pa, short *pb, short *pc) 
+{
+  int i;
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (pa[i] != (pb[i] * pc[i]))
+	abort ();
+    }
+
+  return;
+}
+
+
+__attribute__ ((noinline)) int
+main1 (int n, short * __restrict__ pa, short * __restrict__ pb, short * __restrict__ pc)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      pa[i] = pb[i] * pc[i];
+    }
+
+  bar (pa,pb,pc);
+
+  return 0;
+}
+
+int main (void)
+{
+  int i;
+  short a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  short b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57};
+  short c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19};
+
+  main1 (N,a,b,c);
+  main1 (N-2,a,b,c);
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c
new file mode 100644
index 000000000..ad6f8f0fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c
@@ -0,0 +1,60 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */
+
+/* Taken from vect/vect-95.c.  */
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define N 256
+
+__attribute__ ((noinline))
+void bar (double *pa, double *pb, double *pc) 
+{
+  int i;
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (pa[i] != (pb[i] * pc[i]))
+	abort ();
+    }
+
+  return;
+}
+
+
+__attribute__ ((noinline)) int
+main1 (int n, double * __restrict__ pa, double * __restrict__ pb, double * __restrict__ pc)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      pa[i] = pb[i] * pc[i];
+    }
+
+  bar (pa,pb,pc);
+
+  return 0;
+}
+
+int main (void)
+{
+  int i;
+  double a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  double b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57};
+  double c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19};
+
+  main1 (N,a,b,c);
+  main1 (N-2,a,b,c);
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 3 "vect" {xfail {! vect_hw_misalign } } } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c
new file mode 100644
index 000000000..32d05b298
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c
@@ -0,0 +1,60 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */
+
+/* Taken from vect/vect-95.c.  */
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define N 256
+
+__attribute__ ((noinline))
+void bar (char *pa, char *pb, char *pc) 
+{
+  int i;
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (pa[i] != (pb[i] + pc[i]))
+	abort ();
+    }
+
+  return;
+}
+
+
+__attribute__ ((noinline)) int
+main1 (int n, char * __restrict__ pa, char * __restrict__ pb, char * __restrict__ pc)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      pa[i] = pb[i] + pc[i];
+    }
+
+  bar (pa,pb,pc);
+
+  return 0;
+}
+
+int main (void)
+{
+  int i;
+  char a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  char b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57};
+  char c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19};
+
+  main1 (N,a,b,c);
+  main1 (N-2,a,b,c);
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c
new file mode 100644
index 000000000..8e6e288b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c
@@ -0,0 +1,64 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */
+
+/* Taken from vect/vect-95.c.  */
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define N 256
+
+__attribute__ ((noinline))
+void bar (double *pd, double *pa, double *pb, double *pc) 
+{
+  int i;
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (pa[i] != (pb[i] * pc[i]))
+	abort ();
+      if (pd[i] != 5.0)
+	abort ();
+    }
+
+  return;
+}
+
+
+__attribute__ ((noinline)) int
+main1 (int n, double * __restrict__ pd, double * __restrict__ pa, double * __restrict__ pb, double * __restrict__ pc)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      pa[i] = pb[i] * pc[i];
+      pd[i] = 5.0;
+    }
+
+  bar (pd,pa,pb,pc);
+
+  return 0;
+}
+
+int main (void)
+{
+  int i;
+  double a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  double d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  double b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57};
+  double c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19};
+
+  main1 (N,&d[1],a,b,c);
+  main1 (N-2,&d[1],a,b,c);
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" {xfail {! vect_hw_misalign } } } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c
new file mode 100644
index 000000000..c09583535
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c
@@ -0,0 +1,64 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */
+
+/* Taken from vect/vect-95.c.  */
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define N 256
+
+__attribute__ ((noinline))
+void bar (int *pd, int *pa, int *pb, int *pc) 
+{
+  int i;
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (pa[i] != (pb[i] * pc[i]))
+	abort ();
+      if (pd[i] != 5.0)
+	abort ();
+    }
+
+  return;
+}
+
+
+__attribute__ ((noinline)) int
+main1 (int n, int * __restrict__ pd, int * __restrict__ pa, int * __restrict__ pb, int * __restrict__ pc)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      pa[i] = pb[i] * pc[i];
+      pd[i] = 5.0;
+    }
+
+  bar (pd,pa,pb,pc);
+
+  return 0;
+}
+
+int main (void)
+{
+  int i;
+  int a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  int d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  int b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57};
+  int c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19};
+
+  main1 (N,&d[1],a,b,c);
+  main1 (N-2,&d[1],a,b,c);
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" {xfail {! vect_hw_misalign } } } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c
new file mode 100644
index 000000000..af671ee79
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-8.c
@@ -0,0 +1,64 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */
+
+/* Taken from vect/vect-95.c.  */
+#include <stdlib.h>
+#include <stdarg.h>
+
+#define N 256
+
+__attribute__ ((noinline))
+void bar (short *pd, short *pa, short *pb, short *pc) 
+{
+  int i;
+
+  /* check results:  */
+  for (i = 0; i < N; i++)
+    {
+      if (pa[i] != (pb[i] * pc[i]))
+	abort ();
+      if (pd[i] != 5.0)
+	abort ();
+    }
+
+  return;
+}
+
+
+__attribute__ ((noinline)) int
+main1 (int n, short * __restrict__ pd, short * __restrict__ pa, short * __restrict__ pb, short * __restrict__ pc)
+{
+  int i;
+
+  for (i = 0; i < n; i++)
+    {
+      pa[i] = pb[i] * pc[i];
+      pd[i] = 5.0;
+    }
+
+  bar (pd,pa,pb,pc);
+
+  return 0;
+}
+
+int main (void)
+{
+  int i;
+  short a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  short d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__)));
+  short b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57};
+  short c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19};
+
+  main1 (N,&d[1],a,b,c);
+  main1 (N-2,&d[1],a,b,c);
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-1.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-1.c
new file mode 100644
index 000000000..f4cb4372f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O -mvsx -mno-altivec" } */
+
+/* { dg-warning "-mvsx and -mno-altivec are incompatible" "" { target *-*-* } 1 } */
+
+double
+foo (double *x, double *y)
+{
+  double z[2];
+  int i;
+
+  for (i = 0; i < 2; i++)
+    z[i] = x[i] + y[i];
+  return z[0] * z[1];
+}
+
+/* { dg-final { scan-assembler-not "xsadddp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-2.c b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-2.c
new file mode 100644
index 000000000..e8c9096f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/powerpc/warn-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O -mcpu=power7 -mno-altivec" } */
+
+/* { dg-warning "-mno-altivec disables vsx" "" { target *-*-* } 1 } */
+
+double
+foo (double *x, double *y)
+{
+  double z[2];
+  int i;
+
+  for (i = 0; i < 2; i++)
+    z[i] = x[i] + y[i];
+  return z[0] * z[1];
+}
+
+/* { dg-final { scan-assembler-not "xsadddp" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/rx/builtins.c b/gcc-4.9/gcc/testsuite/gcc.target/rx/builtins.c
new file mode 100644
index 000000000..d503ed3ef
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/rx/builtins.c
@@ -0,0 +1,144 @@
+/* { dg-do run } */
+
+/* Verify that the RX specific builtin functions work.  */
+   
+#include <stdlib.h>
+#include <stdio.h>
+
+/* We need to prevent these functions from being inlined
+   as otherwise gcc will attempt to optimize away their
+   arguments and we need the operations on them in order
+   to correctly set the psw flags.  */
+
+int saturate_add         (int, int)      __attribute__((__noinline__));
+int exchange             (int, int)      __attribute__((__noinline__));
+
+int
+half_word_swap (int arg)
+{
+  return __builtin_rx_revw (arg);
+}
+
+long
+multiply_and_accumulate (long arg1, long arg2, long arg3)
+{
+  __builtin_rx_mvtaclo (0);
+  __builtin_rx_mvtachi (0);
+
+  __builtin_rx_mullo (arg1, arg2);
+  __builtin_rx_mulhi (arg1, arg2);
+  __builtin_rx_maclo (arg1, arg3);
+  __builtin_rx_machi (arg1, arg3);
+
+  __builtin_rx_racw (1);
+  
+  arg1 = __builtin_rx_mvfachi ();
+  arg1 += __builtin_rx_mvfacmi ();
+
+  return arg1;
+}
+
+int
+rxround (float arg)
+{
+  return __builtin_rx_round (arg);
+}
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define CHECK_0ARG(func, result)					\
+  if (func () != result)						\
+    {									\
+      printf (#func " () fails: %x not %x\n", func (), result);		\
+      abort ();								\
+    }
+
+#define CHECK_1ARG(func, arg, result)					\
+  if (func (arg) != result)						\
+    {									\
+      printf (#func " (" #arg ") fails: %x not %x\n", func (arg), result); \
+      abort ();								\
+    }
+
+#define CHECK_2ARG(func, arg1, arg2, result)				\
+  if (func (arg1, arg2) != result)					\
+    {									\
+      printf (#func " (" #arg1 "," #arg2 ") fails: %x not %x\n",	\
+	      func (arg1, arg2), result);				\
+      abort ();								\
+    }
+
+#define CHECK_3ARG(func, arg1, arg2, arg3, result)			\
+  if (func (arg1, arg2, arg3) != result)				\
+    {									\
+      printf (#func " (" #arg1 "," #arg2 "," #arg3 ") fails: %x not %x\n",	\
+	      func (arg1, arg2, arg3), result);				\
+      abort ();								\
+    }
+#else
+#define CHECK_0ARG(func, result)					\
+  if (func () != result)						\
+    abort ();
+
+#define CHECK_1ARG(func, arg, result)					\
+  if (func (arg) != result)						\
+    abort ();
+
+#define CHECK_2ARG(func, arg1, arg2, result)				\
+  if (func (arg1, arg2) != result)					\
+    abort ();
+
+#define CHECK_3ARG(func, arg1, arg2, arg3, result)			\
+  if (func (arg1, arg2, arg3) != result)				\
+    abort ();
+#endif
+
+int
+main (void)
+{
+  CHECK_1ARG (half_word_swap, 0x12345678, 0x34127856);
+  CHECK_3ARG (multiply_and_accumulate, 0x111, 0x222, 0x333, 0x70007);
+  CHECK_1ARG (rxround, 0.5, 1);
+  return 0;
+}
+
+/* The following builtins are compiled but
+   not executed because they need OS support.  */
+
+void
+rxbreak (void)
+{
+  __builtin_rx_brk ();
+}
+
+void
+interrupt (void)
+{
+  __builtin_rx_int (0x12);
+}
+
+int
+get_stack_pointer (void)
+{
+  return __builtin_rx_mvfc (2);
+}
+
+void
+set_stack_pointer (int value)
+{
+  __builtin_rx_mvtc (2, value);
+  __builtin_rx_mvtc (2, 0x1234);
+}
+
+void
+wait (void)
+{
+  __builtin_rx_wait ();
+}
+
+void
+rmpa (int * multiplicand, int * multiplier, int num)
+{
+  __builtin_rx_rmpa ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/rx/i272091.c b/gcc-4.9/gcc/testsuite/gcc.target/rx/i272091.c
new file mode 100644
index 000000000..39da57632
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/rx/i272091.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */

+/* { dg-options "-msmall-data-limit=100" } */

+

+double a=6.76,b=7.34,c=0.54;

+double x_1= 45.46;

+static double SD_1;

+static double SD_init = 45.54;

+double DD_1;

+double DD_init=769.0;

+

+

+int main()

+{

+   volatile double x,y,z;

+   

+   x = 56.76;

+   y = 4.5645;

+

+   z = x + y;

+   z = x - 4.65;

+   z = 4.566 - x;

+   z = x * y;

+   b = 8;

+   c = 34;

+   return 0;

+}

+

diff --git a/gcc-4.9/gcc/testsuite/gcc.target/rx/interrupts.c b/gcc-4.9/gcc/testsuite/gcc.target/rx/interrupts.c
new file mode 100644
index 000000000..cdc4903de
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/rx/interrupts.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-mint-register=3 -msave-acc-in-interrupts" } */
+
+/* Verify that the RX specific function attributes work.  */
+
+void fast_interrupt (void) __attribute__((__fast_interrupt__));
+void interrupt (void) __attribute__((__interrupt__));
+int naked (int) __attribute__((__naked__));
+
+int flag = 0;
+
+/* Fast interrupt handler.  Only uses registers marked as fixed
+   by the -fixed-xxx gcc command line option.  Returns via RTFI.  */
+
+void
+fast_interrupt (void)
+{
+  flag = 1;
+}
+
+/* Interrupt handler.  Must preserve any register it uses, even
+   call clobbered ones.  Returns via RTE.  */
+
+void
+interrupt (void)
+{
+  switch (flag)
+    {
+    case 0:
+      flag = -1;
+      break;
+    case 1:
+    case 2:
+    case 4:
+      flag = flag - 2;
+      break;
+    case 5:
+    case 7:
+    case 6:
+      flag ^= 3;
+      break;
+    default:
+      naked (flag * 2);
+      break;
+    }
+}
+
+/* Naked function.  The programmer must supply the function's
+   prologue and epilogue instructions.  */
+
+int
+naked (int arg)
+{
+  flag = arg;
+}
+
+/* { dg-final { scan-assembler "rtfi" } } */
+/* { dg-final { scan-assembler "rte" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/rx/pack.c b/gcc-4.9/gcc/testsuite/gcc.target/rx/pack.c
new file mode 100644
index 000000000..ce13b5021
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/rx/pack.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+
+typedef unsigned short	INT16U;
+
+typedef struct tst_2
+{
+  INT16U	f0;	/* [+0] */
+  INT16U *	f1;	/* [+2] */
+  INT16U	f2;	/* [+6] */
+  INT16U *	f3;	/* [+8] */
+} __attribute__ ((__packed__)) t2;
+
+#include <stddef.h>
+#include <stdlib.h>
+
+int main (void)
+{
+  if (offsetof (t2, f1) != 2)
+    abort ();
+  if (offsetof (t2, f2) != 6)
+    abort ();
+  if (offsetof (t2, f3) != 8)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/rx/packed-struct.c b/gcc-4.9/gcc/testsuite/gcc.target/rx/packed-struct.c
new file mode 100644
index 000000000..8c2a4345b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/rx/packed-struct.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+
+struct unpacked
+{
+  int i;
+  char c;
+};
+
+#pragma pack(1)
+
+struct packed
+{
+  int i;
+  char c;
+};
+
+struct packed_contains_unpacked
+{
+  char c;
+  struct unpacked uuuu;  /* This should generate an error message.  */
+}; 			/* { dg-error "unpacked structure/union inside a packed struct" "XFAILed until patch for generic GCC structure layout code is accepted" { xfail rx-*-* } } */
+
+union contains_unpacked
+{
+  char c;
+  struct unpacked uuuu;  /* This should not.  */
+};
+
+struct packed_contains_packed
+{
+  char c;
+  struct packed ppppp;   /* This should not.  */
+};
+
+#pragma pack()
+
+struct unpacked_contains_packed
+{
+  char c;
+  struct packed p;
+};
+
+struct unpacked_contains_unpacked
+{
+  char c;
+  struct unpacked u;
+};
+
+
+int s1 = sizeof (struct unpacked);
+int s2 = sizeof (struct packed);
+int s3 = sizeof (struct packed_contains_unpacked);
+int s4 = sizeof (struct packed_contains_packed);
+int s5 = sizeof (struct unpacked_contains_packed);
+int s6 = sizeof (struct unpacked_contains_unpacked);
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/rx/rx-abi-function-tests.c b/gcc-4.9/gcc/testsuite/gcc.target/rx/rx-abi-function-tests.c
new file mode 100644
index 000000000..e07ff71a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/rx/rx-abi-function-tests.c
@@ -0,0 +1,159 @@
+/* { dg-do run } */
+/* { dg-options "-msim" } */
+/* Note: The -msim above is actually there to override the default
+   options which include -ansi -pendantic and -Wlong-long...   */
+
+extern int printf (const char *, ...);
+extern void exit (int);
+extern void abort (void);
+
+extern signed long        _COM_CONVf32s (float);
+extern unsigned long      _COM_CONVf32u (float);
+extern float              _COM_CONV32sf (signed long);
+extern float              _COM_CONV32uf (unsigned long);
+extern float              _COM_ADDf (float, float);
+extern float              _COM_SUBf (float, float);
+extern float              _COM_MULf (float, float);
+extern float              _COM_DIVf (float, float);
+extern int                _COM_CMPLTf (float, float);
+
+extern long long          _COM_MUL64 (long long, long long);
+extern signed long long   _COM_DIV64s (long long, long long);
+extern unsigned long long _COM_DIV64u (unsigned long long, unsigned long long);
+extern long long          _COM_SHLL64 (long long, int);
+extern long long          _COM_SHLR64 (long long, int);
+extern long long          _COM_SHAR64 (long long, int);
+extern signed long long   _COM_CONVf64s (float);
+extern unsigned long long _COM_CONVf64u (float);
+extern signed long long   _COM_CONVd64s (double);
+extern unsigned long long _COM_CONVd64u (double);
+extern float              _COM_CONV64sf (signed long long);
+extern float              _COM_CONV64uf (unsigned long long);
+extern double             _COM_CONV64sd (signed long long);
+extern double             _COM_CONV64ud (unsigned long long);
+extern signed long long   _COM_MOD64s (long long, long long);
+extern unsigned long long _COM_MOD64u (unsigned long long, unsigned long long);
+extern int                _COM_CMPLT64s (long long, long long);
+extern int                _COM_CMPLT64u (unsigned long long, unsigned long long);
+extern int                _COM_CMPGT64s (long long, long long);
+extern int                _COM_CMPGT64u (unsigned long long, unsigned long long);
+extern int                _COM_CMPLE64s (long long, long long);
+extern int                _COM_CMPLE64u (unsigned long long, unsigned long long);
+extern int                _COM_CMPGE64s (long long, long long);
+extern int                _COM_CMPGE64u (unsigned long long, unsigned long long);
+extern int                _COM_CMPEQ64 (long long, long long);
+extern int                _COM_CMPNE64 (long long, long long);
+
+extern double             _COM_ADDd (double, double);
+extern double             _COM_SUBd (double, double);
+extern double             _COM_MULd (double, double);
+extern double             _COM_DIVd (double, double);
+extern signed long        _COM_CONVd32s (double);
+extern unsigned long      _COM_CONVd32u (double);
+extern double             _COM_CONV32sd (signed long);
+extern double             _COM_CONV32ud (unsigned long);
+extern double             _COM_CONVfd (float);
+extern float              _COM_CONVdf (double);
+extern double             _COM_NEGd (double);
+
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+# define TEST1(func,arg1,result)	if (func (arg1) != result) printf ("fail: " #func " (" #arg1 ") returns %x rather than " #result "\n", func (arg1))
+# define TEST2(func,arg1,arg2,result)	if (func (arg1, arg2) != result) printf ("fail: " #func " (" #arg1 ", " #arg2 ") returns %x rather than " #result "\n", func (arg1, arg2))
+# define TEST_CMP(func, low_arg, high_arg, lt_result, eq_result, gt_result)	\
+  do									\
+    {									\
+      int res;								\
+									\
+      if ((res = func (low_arg, high_arg)) != lt_result)   printf ("fail: " #func " (" #low_arg ", " #high_arg ") returns %d rather than %d\n", res, lt_result); \
+      if ((res = func (high_arg, low_arg)) != gt_result)   printf ("fail: " #func " (" #high_arg ", " #low_arg ") returns %d rather than %d\n", res, gt_result); \
+      if ((res = func (low_arg, low_arg))  != eq_result)   printf ("fail: " #func " (" #low_arg ", " #low_arg ") returns %d rather than %d\n", res, eq_result); \
+    } \
+  while (0)
+#else
+# define TEST1(func,arg1,result)	if (func (arg1) != result) abort ()
+# define TEST2(func,arg1,arg2,result)	if (func (arg1, arg2) != result) abort ()
+# define TEST_CMP(func,low,high,lt_res,eq_res,gt_res)	\
+  if (   (func (low, high) != lt_res)			\
+      || (func (high, low) != gt_res)			\
+      || (func (low, low)  != eq_res))			\
+    abort ();
+#endif
+
+
+int
+main (void)
+{
+#ifdef DEBUG
+  printf ("Tests starting\n");
+#endif
+
+  TEST1 (_COM_CONVf32s, -2.0f, -2);
+  TEST1 (_COM_CONVf32u, -2.0f, (unsigned) -2);
+  TEST1 (_COM_CONV32sf, -2, -2.0f);
+  TEST1 (_COM_CONV32uf, 2, 2.0f);
+  TEST2 (_COM_ADDf, 1.0f, 2.0f, 3.0f);
+  TEST2 (_COM_SUBf, 3.0f, 2.0f, 1.0f);
+  TEST2 (_COM_MULf, 2.0f, 3.0f, 6.0f);
+  TEST2 (_COM_DIVf, 6.0f, 2.0f, 3.0f);
+  TEST_CMP (_COM_CMPLTf, 1.0f, 2.0f, 1, 0, 0);
+  TEST_CMP (_COM_CMPGTf, 1.0f, 2.0f, 0, 0, 1);
+  TEST_CMP (_COM_CMPLEf, 1.0f, 2.0f, 1, 1, 0);
+  TEST_CMP (_COM_CMPGEf, 1.0f, 2.0f, 0, 1, 1);
+  TEST_CMP (_COM_CMPEQf, 1.0f, 2.0f, 0, 1, 0);
+  TEST_CMP (_COM_CMPNEf, 1.0f, 2.0f, 1, 0, 1);
+
+
+  TEST2 (_COM_MUL64, 2LL, 4LL, 8LL);
+  TEST2 (_COM_DIV64s, 6LL, 3LL, 2LL);
+  TEST2 (_COM_DIV64u, 6ULL, 3ULL, 2ULL);
+  TEST2 (_COM_SHLL64, 6LL, 3, 48LL);
+  TEST2 (_COM_SHLR64, 8LL, 2, 2LL);
+  TEST2 (_COM_SHAR64, -1LL, 2, -1LL);  
+  TEST1 (_COM_CONVf64s, -2.0f, -2LL);
+  TEST1 (_COM_CONVf64u, 2.0f, 2ULL);
+  TEST1 (_COM_CONVd64s, -2.0, -2LL);
+  TEST1 (_COM_CONVd64u, 2.0, 2ULL);
+  TEST1 (_COM_CONV64sf, -2LL, -2.0f);
+  TEST1 (_COM_CONV64uf, 2ULL, 2.0f);
+  TEST1 (_COM_CONV64sd, -2LL, -2.0);
+  TEST1 (_COM_CONV64ud, 2ULL, 2.0);
+  TEST2 (_COM_MOD64s, 4LL, 3LL, 1LL);
+  TEST2 (_COM_MOD64u, 4ULL, 3ULL, 1ULL);
+  TEST_CMP (_COM_CMPLT64s, 1LL, 2LL, 1, 0, 0);
+  TEST_CMP (_COM_CMPLT64u, 1ULL, 2ULL, 1, 0, 0);
+  TEST_CMP (_COM_CMPGT64s, 1LL, 2LL, 0, 0, 1);
+  TEST_CMP (_COM_CMPGT64u, 1ULL, 2ULL, 0, 0, 1);
+  TEST_CMP (_COM_CMPLE64s, 1LL, 2LL, 1, 1, 0);
+  TEST_CMP (_COM_CMPLE64u, 1ULL, 2ULL, 1, 1, 0);
+  TEST_CMP (_COM_CMPGE64s, 1LL, 2LL, 0, 1, 1);
+  TEST_CMP (_COM_CMPGE64u, 1ULL, 2ULL, 0, 1, 1);
+  TEST_CMP (_COM_CMPEQ64, 1LL, 2LL, 0, 1, 0);
+  TEST_CMP (_COM_CMPNE64, 1LL, 2LL, 1, 0, 1);
+
+
+  TEST2 (_COM_ADDd, 1.0, 2.0, 3.0);
+  TEST2 (_COM_SUBd, 3.0, 2.0, 1.0);
+  TEST2 (_COM_MULd, 2.0, 3.0, 6.0);
+  TEST2 (_COM_DIVd, 6.0, 2.0, 3.0);
+  TEST1 (_COM_CONVd32s, -2.0, -2);
+  TEST1 (_COM_CONVd32u, -2.0, (unsigned) -2);
+  TEST1 (_COM_CONV32sd, -2, -2.0);
+  TEST1 (_COM_CONV32ud, 2, 2.0);
+  TEST1 (_COM_CONVfd, 2.0f, 2.0);
+  TEST1 (_COM_CONVdf, 2.0, 2.0f);
+  TEST1 (_COM_NEGd, -2.0, 2.0);
+  TEST_CMP (_COM_CMPLTd, 1.0, 2.0, 1, 0, 0);
+  TEST_CMP (_COM_CMPGTd, 1.0, 2.0, 0, 0, 1);
+  TEST_CMP (_COM_CMPLEd, 1.0, 2.0, 1, 1, 0);
+  TEST_CMP (_COM_CMPGEd, 1.0, 2.0, 0, 1, 1);
+  TEST_CMP (_COM_CMPEQd, 1.0, 2.0, 0, 1, 0);
+  TEST_CMP (_COM_CMPNEd, 1.0, 2.0, 1, 0, 1);
+  
+#ifdef DEBUG
+  printf ("Tests finished\n");
+#endif
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/rx/rx.exp b/gcc-4.9/gcc/testsuite/gcc.target/rx/rx.exp
new file mode 100644
index 000000000..159add18b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/rx/rx.exp
@@ -0,0 +1,43 @@
+# Copyright (C) 2008-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.  
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't the right target.
+if { ![istarget rx-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS ""
+}
+
+# Initialize `dg'.
+dg-init
+
+# Find all tests
+set tests [lsort [find $srcdir/$subdir *.\[cS\]]]
+
+# Main loop.
+gcc-dg-runtest $tests $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/rx/zero-width-bitfield.c b/gcc-4.9/gcc/testsuite/gcc.target/rx/zero-width-bitfield.c
new file mode 100644
index 000000000..26cf5a2b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/rx/zero-width-bitfield.c
@@ -0,0 +1,32 @@
+/* { dg-do run { xfail rx-*-* } } */
+/* { dg-skip-if "skipped until patch for generic zero=width bit-field handling is accepted" { rx-*-* } { "*" } { "" } } */
+/* { dg-options "-msim" } */
+/* Note: The -msim abiove is actually there to override the default
+   options which do not allow the GCC extension of zero-width bitfields.  */
+
+extern void abort (void);
+extern void exit  (int);
+
+struct S_zero
+{
+  int   f1: 4;
+  int   f2: 0;
+  short f3: 4;
+} S_zero;
+
+struct S_norm
+{
+  int   f1: 4;
+  short f3: 4;
+} S_norm;
+ 
+ 
+int
+main (void)
+{
+  if (sizeof (S_zero) != 4 || sizeof (S_norm) != 8)
+    abort ();
+
+  exit (0);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20020926-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20020926-1.c
new file mode 100644
index 000000000..aaa134276
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20020926-1.c
@@ -0,0 +1,14 @@
+/* Make sure that LEGITIMIZE_ADDRESS is called to handle
+   negative displacements.  */
+
+/* { dg-do compile { target { s390-*-* } } } */
+/* { dg-options "-O2 -mesa" } */
+
+int test (int *addr)
+{
+  return *(addr - 1);
+}
+
+/* { dg-final { scan-assembler "-4096" } } */
+/* { dg-final { scan-assembler-not "ahi" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20030123-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20030123-1.c
new file mode 100644
index 000000000..c426866fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20030123-1.c
@@ -0,0 +1,19 @@
+/* This used to ICE due to a reload bug on s390*.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+
+extern void *alloca (__SIZE_TYPE__);
+
+void func (char *p);
+
+void test (void)
+{
+   char *p = alloca (4096);
+   long idx;
+
+   asm volatile ("" : "=r" (idx) : : "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "12");
+
+   func (p + idx + 1);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20030129-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20030129-1.c
new file mode 100644
index 000000000..1cbd8b482
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20030129-1.c
@@ -0,0 +1,37 @@
+/* This used to ICE due to a reload bug on s390*.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int f (unsigned int);
+void g (void *);
+
+void test (void *p, void *dummy)
+{
+  unsigned int flags = 0;
+
+  if (dummy)
+    g (dummy);
+
+  if (p)
+    flags |= 0x80000000;
+
+  asm volatile ("" : : : "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12");
+
+  if (dummy)
+    g (dummy);
+
+  if (p) 
+    {
+      flags |= 0x20000000|0x80000000;
+
+      if (!f (0))
+        flags &= ~0x80000000;
+    }
+
+  f (flags);
+
+  if (dummy)
+    g (dummy);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20040305-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20040305-1.c
new file mode 100644
index 000000000..a241f041c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20040305-1.c
@@ -0,0 +1,53 @@
+
+/* The testcase failed due to corrupted alias information.
+   During the crossjump analyzing step the mem alias info of the
+   st instructions are merged and get copied during basic block
+   reordering which leads to an insn with wrong alias info.
+   The scheduler afterwards exchanges the mvc and st instructions 
+   not recognizing the anti dependence.  */
+/* { dg-do run } */
+/* { dg-options "-O3 -mtune=z990 -fno-inline" } */
+
+extern void exit (int);
+extern void abort (void);
+
+int f;
+int g;
+int h;
+
+int* x  = &f;
+int* p1 = &g;
+int* p2 = &h;
+
+int
+foo(void)
+{
+
+  if (*x == 0)
+    {
+      x = p1;         /* mvc - memory to memory */
+      p1 = (int*)0;   /* st  - register to memory */
+      return 1;
+    }
+  if (*x == 5)
+    {
+      f = 1;
+      g = 2;
+
+      p2 = (int*)0;   /* st */   
+      return 1;
+    }
+}
+
+int
+main (int argc, char** argv)
+{
+  foo ();
+
+  /* If the scheduler has exchanged the mvc and st instructions,
+     x is 0. The expected result is &g.  */
+  if (x == &g)
+    exit (0);
+  else
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20041109-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20041109-1.c
new file mode 100644
index 000000000..bf768439c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20041109-1.c
@@ -0,0 +1,21 @@
+/* This used to ICE due to a literal pool handling bug on s390x.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-omit-frame-pointer" } */
+
+static struct table { int x; } table[3];
+
+int test (void)
+{
+  struct table *t;
+
+  for (t = table; t < &table[3]; t++)
+    asm volatile ("" : : : "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "12");
+
+  for (t = table; t < &table[3]; t++)
+    if (t->x)
+      return 1;
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20041216-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20041216-1.c
new file mode 100644
index 000000000..492ee6c18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20041216-1.c
@@ -0,0 +1,23 @@
+/* This test case would get an unresolved symbol during link
+   because stabs referred to an optimized-away literal pool
+   entry.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-omit-frame-pointer -gstabs" } */
+
+int main (void)
+{
+  static char buf[4096];
+  char *p;
+
+  do
+    {
+      p = buf;
+      asm volatile ("" : : : "memory", "0", "1", "2", "3", "4", "5", "6",
+				       "7", "8", "9", "10", "12");
+    }
+  while (*p);
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20050409-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20050409-1.c
new file mode 100644
index 000000000..4763afad3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20050409-1.c
@@ -0,0 +1,18 @@
+/* This used to ICE due to a regmove problem on s390.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+
+extern void abort (void);
+extern void **alloc (void);
+
+void *test (void)
+{
+  void **p = alloc ();
+  if (!p) abort ();
+
+  __builtin_set_thread_pointer (p);
+  return *p;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20050524-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20050524-1.c
new file mode 100644
index 000000000..7b94fd0f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20050524-1.c
@@ -0,0 +1,34 @@
+/* This test case used to abort due to a reload bug with
+   elimination offsets.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -mpacked-stack" } */
+
+extern void abort (void);
+
+double bar (double) __attribute__ ((noinline));
+double bar (double x) { return x; }
+
+double
+foo (int j, double f0, double f2, double f4, double f6, double x) __attribute__ ((noinline));
+
+double
+foo (int j, double f0, double f2, double f4, double f6, double x)
+{
+  if (j)
+    return bar (x) + 4.0;
+  else
+    return bar (x);
+}
+
+int
+main (void)
+{
+  if (foo (0, 0, 0, 0, 0, 10) != 10)
+    abort ();
+  if (foo (1, 0, 0, 0, 0, 10) != 14)
+    abort ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20050824-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20050824-1.c
new file mode 100644
index 000000000..c24e1e26f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20050824-1.c
@@ -0,0 +1,34 @@
+/* Make sure that the S/390 specific shift_count_operand
+   predicate work properly.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+unsigned long long
+f (unsigned long long a, unsigned long b)
+{
+  asm ("" : : : 
+#ifdef __s390x__
+		"r13", "r14",
+#endif
+		"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 
+                "r8", "r9", "r10", "r11", "r12");
+
+  return a << ((b + 3) & 63);
+}
+
+unsigned long long
+g (unsigned long long a, char **b , int c, int d, int e, int f)
+{
+  char buffer [4096];
+
+  *b = &buffer[0];
+
+  return a << ((unsigned long)&f & 63);
+}
+
+unsigned long long
+h (unsigned long long a, int b, int c, int d, int e, int f)
+{
+  return a << (((unsigned long)&f + 3));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20071212-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20071212-1.c
new file mode 100644
index 000000000..e5d05ad41
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20071212-1.c
@@ -0,0 +1,11 @@
+/* This used to fail due to bug in the On constraint causing a slgfi
+   to be emitted with an immediate not fitting into 32bit.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=z9-109" } */
+
+long
+foo (long a)
+{
+  return a - (1ULL << 32);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/20090223-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/20090223-1.c
new file mode 100644
index 000000000..1bf0f2fe8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/20090223-1.c
@@ -0,0 +1,60 @@
+/* The RTL loop optimizer used to replace the output register of the
+   inline assembly with a pseudo although the variable is declared as
+   register asm ("0").  */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -Wno-attributes" } */
+
+extern void abort (void);
+
+static unsigned char __attribute__ ((always_inline))
+mytoupper (unsigned char c)
+{
+  if (c >= 'a' && c <= 'z')
+    c -= 'a' - 'A';
+  return c;
+}
+
+static unsigned long __attribute__ ((always_inline))
+strlen (const char *s)
+{
+  register unsigned long r0 asm ("0");
+  const char *tmp = s;
+
+  asm (
+#ifdef __s390x__
+       "  lghi  %0, 0\n"
+#else
+       "  lhi   %0, 0\n"
+#endif
+       "0:srst  %0,%1\n"
+       "  jo    0b"
+       : "=d" (r0), "+a" (tmp)
+       :
+       :"cc");
+  return r0 - (unsigned long) s;
+}
+
+char boot_command_line[] = "this is a test";
+
+void __attribute__ ((noinline))
+foo (char *str)
+{
+  if (strcmp (str, "THIS IS A TEST") != 0)
+    abort ();
+}
+
+int
+main ()
+{
+  char upper_command_line[1024];
+  int i;
+
+  for (i = 0; i < strlen (boot_command_line); i++)
+    upper_command_line[i] = mytoupper (boot_command_line[i]);
+
+  upper_command_line[strlen (boot_command_line)] = 0;
+  foo (upper_command_line);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/addr-constraints-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/addr-constraints-1.c
new file mode 100644
index 000000000..fbb48f282
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/addr-constraints-1.c
@@ -0,0 +1,70 @@
+/* { dg-compile } */
+/* { dg-options "-O2" } */
+
+static inline unsigned long
+lay_uw(unsigned long addr)
+{
+  unsigned long result;
+
+  __asm__ ("lay    %[result],%a[addr]"
+	   : [result] "=d" (result)
+	   : [addr] "UW" (addr));
+  return result;
+}
+
+static inline unsigned long
+la_u(unsigned long addr)
+{
+  unsigned long result;
+
+  __asm__ ("la    %[result],%a[addr]"
+	   : [result] "=d" (result)
+	   : [addr] "U" (addr));
+  return result;
+}
+
+static inline unsigned long
+lay_zqzrzszt(unsigned long addr)
+{
+  unsigned long result;
+
+  __asm__ ("lay    %[result],%a[addr]"
+	   : [result] "=d" (result)
+	   : [addr] "ZQZRZSZT" (addr));
+  return result;
+}
+
+static inline unsigned long
+la_zqzr(unsigned long addr)
+{
+  unsigned long result;
+
+  __asm__ ("la    %[result],%a[addr]"
+	   : [result] "=d" (result)
+	   : [addr] "ZQZR" (addr));
+  return result;
+}
+
+
+extern unsigned long a[15];
+
+int main(void)
+{
+  a[1] = lay_uw(3333);
+  a[2] = lay_uw(4444);
+  a[3] = lay_uw(1000000);
+  a[4] = lay_uw(a[0]);
+
+  a[5] = la_u(2222);
+  a[6] = la_u(5555);
+  a[7] = la_u(a[0]);
+
+  a[8] = lay_zqzrzszt(3333);
+  a[9] = lay_zqzrzszt(4444);
+  a[10] = lay_zqzrzszt(1000000);
+  a[11] = lay_zqzrzszt(a[0]);
+
+  a[12] = la_zqzr(2222);
+  a[13] = la_zqzr(5555);
+  a[14] = la_zqzr(a[0]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/fp2int1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/fp2int1.c
new file mode 100644
index 000000000..4a90a8b91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/fp2int1.c
@@ -0,0 +1,95 @@
+/* Test for the 32 bit fp to 64 bit int conversion routines.
+   
+   On S/390 32 bit we use our own implementations in order to be IEEE
+   complaint as we are with our machine instructions.  These missed to
+   throw FE_INVALID exceptions in a bunch of cases.  */
+
+/* { dg-do run { target s390-*-* } } */
+/* { dg-options "-O3 -mesa" } */
+/* { dg-require-effective-target fenv_exceptions } */
+
+#define _GNU_SOURCE
+#include <stdlib.h>
+#include <stdio.h>
+#include <fenv.h>
+
+#define INFINITYf       (__builtin_inff())
+#define INFINITY        (__builtin_inf())
+#define INFINITYl       (__builtin_infl())
+#define NANf            (__builtin_nanf (""))
+#define NAN             (__builtin_nan (""))
+#define NANl            (__builtin_nanl (""))
+
+#define TESTEXCEPT_FUNC(FUNC, TYPE_FROM, TYPE_TO)			\
+  TYPE_TO								\
+  __attribute__((noinline)) FUNC (TYPE_FROM a)				\
+  {									\
+    asm volatile ("" : : "f" (a));					\
+    return (TYPE_TO)a;							\
+  }
+
+#define TESTEXCEPT(FUNC, EXCEPT, EXPECT, VALUE, TYPE_TO)		\
+  {									\
+    TYPE_TO b;								\
+    feclearexcept (FE_ALL_EXCEPT);					\
+    b = FUNC (VALUE);							\
+    if ((fetestexcept (EXCEPT) & (EXCEPT)) != EXPECT)			\
+      {									\
+	printf ("FAIL in line: %d\n", __LINE__);			\
+	abort ();							\
+      }									\
+  }
+
+#define TESTEXCEPT_FUNC_ALLFLOATS(FUNC, TYPE_TO)		\
+  TESTEXCEPT_FUNC (FUNC##_f, float, TYPE_TO);			\
+  TESTEXCEPT_FUNC (FUNC##_d, double, TYPE_TO);			\
+  TESTEXCEPT_FUNC (FUNC##_l, long double, TYPE_TO);		\
+
+#define TESTEXCEPT_ALLFLOATS(FUNC, EXCEPT, EXPECT, VALUE, TYPE_TO)	\
+  TESTEXCEPT (FUNC##_f, EXCEPT, EXPECT, VALUE##f, TYPE_TO);		\
+  TESTEXCEPT (FUNC##_d, EXCEPT, EXPECT, VALUE, TYPE_TO);		\
+  TESTEXCEPT (FUNC##_l, EXCEPT, EXPECT, VALUE##l, TYPE_TO);		\
+
+TESTEXCEPT_FUNC_ALLFLOATS (a, unsigned long long);
+TESTEXCEPT_FUNC_ALLFLOATS (u, long long);
+
+
+int
+main ()
+{
+  /* Prevent getting signals.  */
+  fedisableexcept (FE_INVALID);
+
+  /* To unsigned long long */
+
+  TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, INFINITY, unsigned long long);
+  TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, -INFINITY, unsigned long long);
+  TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, NAN, unsigned long long);
+  TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, -NAN, unsigned long long);
+
+  /* Negative values >-1.0 must not cause FE_INVALID.  */
+  TESTEXCEPT_ALLFLOATS (a, FE_INVALID, 0, -0x0.ffffffp0, unsigned long long);
+  /* -1.0 instead must.  */
+  TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, -0x1.0p+0, unsigned long long);
+  TESTEXCEPT_ALLFLOATS (a, FE_INVALID, 0, 0x1.0p+63, unsigned long long);
+  TESTEXCEPT_ALLFLOATS (a, FE_INVALID, FE_INVALID, 0x1.0p+64, unsigned long long);
+
+  /* To signed long long */
+
+  TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, INFINITY, long long);
+  TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, -INFINITY, long long);
+  TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, NAN, long long);
+  TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, -NAN, long long);
+
+  TESTEXCEPT_ALLFLOATS (u, FE_INVALID, 0, -0x1.0p+63, long long);
+  TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, -0x1.1p+63, long long);
+  TESTEXCEPT_ALLFLOATS (u, FE_INVALID, 0, 0x0.fffffp+63, long long);
+  TESTEXCEPT_ALLFLOATS (u, FE_INVALID, FE_INVALID, 0x1.0p+63, long long);
+
+  /* If there are additional bits which would not make it into the
+     integer value no exception is supposed to occur.  */
+  TESTEXCEPT (u_l, FE_INVALID,          0, -0x1.000000000000000123p+63l, long long);
+  TESTEXCEPT (u_l, FE_INVALID, FE_INVALID, -0x1.000000000000000223p+63l, long long);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/frame-addr1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/frame-addr1.c
new file mode 100644
index 000000000..fda419ff0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/frame-addr1.c
@@ -0,0 +1,53 @@
+/* builtin_frame_address(n) with n>0 has always been troublesome ...
+   especially when the S/390 packed stack layout comes into play.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-optimize-sibling-calls -mbackchain -mpacked-stack -msoft-float" } */
+
+#ifdef __s390x__
+/* 64bit: 3 words to be saved: backchain, r14 and r15  */
+#define SAVE_AREA_SIZE 3*8
+#else
+/* 32bit: 4 words to be saved: backchain, r13, r14 and r15  */
+#define SAVE_AREA_SIZE 4*4
+#endif
+extern void abort(void);
+
+#define EXPAND_CHECK(n)						\
+  void __attribute__((noinline))				\
+    foo1_##n (void *p)						\
+  {								\
+    if (p - __builtin_frame_address (n) != SAVE_AREA_SIZE)	\
+      abort ();							\
+  }								\
+  void __attribute__((noinline))				\
+    foo2_##n (void *p)						\
+  {								\
+    if (p - __builtin_frame_address (n) != SAVE_AREA_SIZE)	\
+      abort ();							\
+    foo1_##n (__builtin_frame_address (n));			\
+  }								\
+  void __attribute__((noinline))				\
+    foo3_##n ()							\
+  {								\
+    foo2_##n (__builtin_frame_address (n));			\
+  }								\
+  void __attribute__((noinline))				\
+    foo4_##n ()							\
+  {								\
+    foo3_##n ();						\
+  }
+
+EXPAND_CHECK (0)
+EXPAND_CHECK (1)
+EXPAND_CHECK (2)
+
+int
+main ()
+{
+  foo4_0 ();
+  foo4_1 ();
+  foo4_2 ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/frame-addr2.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/frame-addr2.c
new file mode 100644
index 000000000..f6f9687a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/frame-addr2.c
@@ -0,0 +1,50 @@
+/* builtin_frame_address(n) with n>0 has always been troublesome.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-optimize-sibling-calls -mbackchain" } */
+
+#ifdef __s390x__
+#define SAVE_AREA_SIZE 160
+#else
+#define SAVE_AREA_SIZE 96
+#endif
+extern void abort(void);
+
+#define EXPAND_CHECK(n)						\
+  void __attribute__((noinline))				\
+    foo1_##n (void *p)						\
+  {								\
+    if (p - __builtin_frame_address (n) != SAVE_AREA_SIZE)	\
+      abort ();							\
+  }								\
+  void __attribute__((noinline))				\
+    foo2_##n (void *p)						\
+  {								\
+    if (p - __builtin_frame_address (n) != SAVE_AREA_SIZE)	\
+      abort ();							\
+    foo1_##n (__builtin_frame_address (n));			\
+  }								\
+  void __attribute__((noinline))				\
+    foo3_##n ()							\
+  {								\
+    foo2_##n (__builtin_frame_address (n));			\
+  }								\
+  void __attribute__((noinline))				\
+    foo4_##n ()							\
+  {								\
+    foo3_##n ();						\
+  }
+
+EXPAND_CHECK (0)
+EXPAND_CHECK (1)
+EXPAND_CHECK (2)
+
+int
+main ()
+{
+  foo4_0 ();
+  foo4_1 ();
+  foo4_2 ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-1.c
new file mode 100644
index 000000000..b9d6139b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-1.c
@@ -0,0 +1,20 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-times "nopr\t%r7" 12 } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-10.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-10.c
new file mode 100644
index 000000000..b91b3478e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-10.c
@@ -0,0 +1,21 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mno-hotpatch --save-temps" } */
+
+#include <stdio.h>
+
+__attribute__ ((hotpatch(2)))
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-times "nopr\t%r7" 2 } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-11.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-11.c
new file mode 100644
index 000000000..491677342
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-11.c
@@ -0,0 +1,20 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch -mno-hotpatch --save-temps" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
+/* { dg-final { scan-assembler-not "nop\t0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-12.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-12.c
new file mode 100644
index 000000000..b3e9427d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-12.c
@@ -0,0 +1,20 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mno-hotpatch -mhotpatch=1 --save-temps" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-2.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-2.c
new file mode 100644
index 000000000..6cc29447d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-2.c
@@ -0,0 +1,20 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch=1 --save-temps" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-3.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-3.c
new file mode 100644
index 000000000..9f0b2b756
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-3.c
@@ -0,0 +1,20 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch=0 --save-temps" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-4.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-4.c
new file mode 100644
index 000000000..c1dba20a3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-4.c
@@ -0,0 +1,26 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
+
+#include <stdio.h>
+
+inline void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((always_inline))
+void hp2(void) /* { dg-warning "always_inline function might not be inlinable" } */
+{
+  printf("hello, world!\n");
+} /* { dg-warning "function 'hp2' with the 'always_inline' attribute is not hotpatchable" } */
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
+/* { dg-final { scan-assembler-not "nop\t0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-5.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-5.c
new file mode 100644
index 000000000..ec267d65a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-5.c
@@ -0,0 +1,21 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
+
+#include <stdio.h>
+
+__attribute__ ((hotpatch))
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-times "nopr\t%r7" 12 } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-6.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-6.c
new file mode 100644
index 000000000..5af090d03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-6.c
@@ -0,0 +1,21 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
+
+#include <stdio.h>
+
+__attribute__ ((hotpatch(1)))
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-times "nopr\t%r7" 1 } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-7.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-7.c
new file mode 100644
index 000000000..e73a510b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-7.c
@@ -0,0 +1,21 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
+
+#include <stdio.h>
+
+__attribute__ ((hotpatch(0)))
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-8.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-8.c
new file mode 100644
index 000000000..399aa7260
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-8.c
@@ -0,0 +1,28 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch --save-temps" } */
+
+#include <stdio.h>
+
+__attribute__ ((hotpatch))
+inline void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch))
+__attribute__ ((always_inline))
+void hp2(void) /* { dg-warning "always_inline function might not be inlinable" } */
+{
+  printf("hello, world!\n");
+} /* { dg-warning "function 'hp2' with the 'always_inline' attribute is not hotpatchable" } */
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-not "nopr\t%r7" } } */
+/* { dg-final { scan-assembler-not "nop\t0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-9.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-9.c
new file mode 100644
index 000000000..5da675866
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-9.c
@@ -0,0 +1,21 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch=1 --save-temps" } */
+
+#include <stdio.h>
+
+__attribute__ ((hotpatch(2)))
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
+
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-times "nopr\t%r7" 2 } } */
+/* { dg-final { scan-assembler-times "nop\t0" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c
new file mode 100644
index 000000000..45a2cc5dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c
@@ -0,0 +1,27 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+inline void hp2(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((always_inline))
+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */
+{
+  printf("hello, world!\n");
+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */
+
+int main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c
new file mode 100644
index 000000000..5947f564f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c
@@ -0,0 +1,27 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch=0" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+inline void hp2(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((always_inline))
+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */
+{
+  printf("hello, world!\n");
+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */
+
+int main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c
new file mode 100644
index 000000000..e0c7f6f52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c
@@ -0,0 +1,27 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch=1" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+inline void hp2(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((always_inline))
+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */
+{
+  printf("hello, world!\n");
+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */
+
+int main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c
new file mode 100644
index 000000000..d9f13425a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c
@@ -0,0 +1,11 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -mhotpatch=-1" } */
+
+int main (void)
+{
+  return 0;
+}
+
+/* { dg-excess-errors "argument to '-mhotpatch=' should be a non-negative integer" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c
new file mode 100644
index 000000000..53f7eac9e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c
@@ -0,0 +1,28 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -mhotpatch=1000000" } */
+
+#include <stdio.h>
+
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch(1000000)))
+void hp2(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch(1000001)))
+void hp3(void)
+{ /* { dg-error "requested 'hotpatch' attribute is not a non-negative integer constant or too large .max. 1000000." } */
+  printf("hello, world!\n");
+}
+
+int main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c
new file mode 100644
index 000000000..cb10b66f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c
@@ -0,0 +1,11 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -mhotpatch=1000001" } */
+
+int main (void)
+{
+  return 0;
+}
+
+/* { dg-excess-errors "argument to '-mhotpatch=' is too large .max. 1000000." } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c
new file mode 100644
index 000000000..98ccb42c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c
@@ -0,0 +1,68 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mno-hotpatch" } */
+
+#include <stdio.h>
+
+__attribute__ ((hotpatch))
+void hp1(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch))
+inline void hp2(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch))
+__attribute__ ((always_inline))
+void hp3(void) /* { dg-warning "always_inline function might not be inlinable" } */
+{
+  printf("hello, world!\n");
+} /* { dg-warning "function 'hp3' with the 'always_inline' attribute is not hotpatchable" } */
+
+__attribute__ ((hotpatch(0)))
+void hp4(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch(0)))
+inline void hp5(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch(0)))
+__attribute__ ((always_inline))
+void hp6(void) /* { dg-warning "always_inline function might not be inlinable" } */
+{
+  printf("hello, world!\n");
+} /* { dg-warning "function 'hp6' with the 'always_inline' attribute is not hotpatchable" } */
+
+__attribute__ ((hotpatch(1)))
+void hp7(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch(1)))
+inline void hp8(void)
+{
+  printf("hello, world!\n");
+}
+
+__attribute__ ((hotpatch(1)))
+__attribute__ ((always_inline))
+void hp9(void) /* { dg-warning "always_inline function might not be inlinable" } */
+{
+  printf("hello, world!\n");
+} /* { dg-warning "function 'hp9' with the 'always_inline' attribute is not hotpatchable" } */
+
+int main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c
new file mode 100644
index 000000000..489fc5dd9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c
@@ -0,0 +1,23 @@
+/* Functional tests for the function hotpatching feature.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -mhotpatch" } */
+
+#include <stdio.h>
+
+int hp1(void)
+{
+  int nested1(void) /* { dg-warning "hotpatching is not compatible with nested functions" } */
+  { return 1; }
+
+  __attribute__ ((hotpatch))
+  int nested2(void) /* { dg-warning "hotpatching is not compatible with nested functions" } */
+  { return 1; }
+
+  return nested1() - nested2();
+}
+
+int main (void)
+{
+  return hp1();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-1.c
new file mode 100644
index 000000000..c90490faa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-1.c
@@ -0,0 +1,1073 @@
+/* Functional tests of the htm __builtin_... macros.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target htm } */
+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
+
+/* ---------------------------- included header files ---------------------- */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+#include <htmintrin.h>
+
+/* ---------------------------- local definitions -------------------------- */
+
+#define DEFAULT_MAX_REPETITIONS 5
+#define DEFAULT_REQUIRED_QUORUM ((DEFAULT_MAX_REPETITIONS) - 1)
+#define NUM_WARMUP_RUNS 10
+
+/* ---------------------------- local macros ------------------------------- */
+
+#define TEST_DF_REP(name) \
+  { #name, name, DEFAULT_MAX_REPETITIONS, DEFAULT_REQUIRED_QUORUM }
+#define TEST_NO_REP(name) { #name, name, 1, 1 }
+
+/* ---------------------------- local types -------------------------------- */
+
+typedef int (*test_func_t)(void);
+
+typedef struct
+{
+  const char *name;
+  test_func_t test_func;
+  int max_repetitions;
+  int required_quorum;
+} test_table_entry_t;
+
+/* ---------------------------- local variables ---------------------------- */
+
+__attribute__ ((aligned(256))) static struct __htm_tdb local_tdb256;
+static struct __htm_tdb local_tdb;
+static int do_dump_tdb = 0;
+
+/* ---------------------------- exported variables (globals) --------------- */
+
+__attribute__ ((aligned(256))) struct
+{
+  float float_1;
+  float float_2;
+  float float_3;
+} global = { 1.0, 2.5, 0.0 };
+
+__attribute__ ((aligned(256))) struct
+{
+  volatile uint64_t c1;
+  volatile uint64_t c2;
+  volatile uint64_t c3;
+} counters = { 0, 0, 0 };
+
+/* ---------------------------- local helper functions --------------------- */
+
+static void dump_tdb (struct __htm_tdb *tdb)
+{
+  unsigned char *p;
+  int i;
+  int j;
+
+  if (do_dump_tdb == 0)
+    {
+      return;
+    }
+  p = (unsigned char *)tdb;
+  for (i = 0; i < 16; i++)
+    {
+      fprintf (stderr, "0x%02x  ", i * 16);
+      for (j = 0; j < 16; j++)
+	{
+	  fprintf (stderr, "%02x", (int)p[i * 16 + j]);
+	  if (j < 15)
+	    {
+	      fprintf (stderr, " ");
+	    }
+	  if (j == 7)
+	    {
+	      fprintf (stderr, " ");
+	    }
+	}
+      fprintf (stderr, "\n");
+    }
+
+  return;
+}
+
+/* ---------------------------- local test functions ----------------------- */
+
+/* Check values of the constants defined in htmintrin.h.  */
+static int test_constants (void)
+{
+  if (_HTM_TBEGIN_STARTED != 0)
+    {
+      return 100 * _HTM_TBEGIN_STARTED + 1;
+    }
+  if (_HTM_TBEGIN_INDETERMINATE != 1)
+    {
+      return 100 * _HTM_TBEGIN_INDETERMINATE + 2;
+    }
+  if (_HTM_TBEGIN_TRANSIENT != 2)
+    {
+      return 100 * _HTM_TBEGIN_TRANSIENT + 3;
+    }
+  if (_HTM_TBEGIN_PERSISTENT != 3)
+    {
+      return 100 * _HTM_TBEGIN_PERSISTENT + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_ntstg_tend (void)
+{
+  int rc;
+
+  counters.c1 = 0;
+  counters.c2 = 0;
+  if ((rc = __builtin_tbegin ((void *)0)) == 0)
+    {
+      __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);
+      counters.c2 = 2;
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 100 * rc + 5;
+	}
+      if (counters.c1 != 1)
+	{
+	  return 100 * counters.c1 + 2;
+	}
+      if (counters.c2 != 2)
+	{
+	  return 100 * counters.c2 + 3;
+	}
+    }
+  else
+    {
+      return 100 * rc + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_ntstg_tabort (void)
+{
+  float f;
+
+  counters.c1 = 0;
+  counters.c2 = 0;
+  f = 0;
+  if (__builtin_tbegin ((void *)0) == 0)
+    {
+      __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);
+      counters.c2 = 2;
+      f = 1;
+      __builtin_tabort (256);
+      return 1;
+    }
+  if (counters.c1 != 1)
+    {
+      return 100 * counters.c1 + 2;
+    }
+  if (counters.c2 != 0)
+    {
+      return 100 * counters.c2 + 3;
+    }
+  if (f != 0)
+    {
+      return 100 * f + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_nofloat (void)
+{
+  int rc;
+
+  counters.c1 = 0;
+  counters.c2 = 0;
+  if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
+    {
+      __builtin_non_tx_store ((uint64_t *)&counters.c1, 1);
+      counters.c2 = 2;
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 100 * rc + 5;
+	}
+      if (counters.c1 != 1)
+	{
+	  return 100 * counters.c1 + 2;
+	}
+      if (counters.c2 != 2)
+	{
+	  return 100 * counters.c2 + 3;
+	}
+    }
+  else
+    {
+      return 100 * rc + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_retry (void)
+{
+  int rc;
+
+  counters.c1 = 0;
+  counters.c2 = 0;
+  counters.c3 = 0;
+  if ((rc = __builtin_tbegin_retry ((void *)0, 5)) == 0)
+    {
+      int do_abort;
+
+      do_abort = (counters.c1 == 0) ? 1 : 0;
+      __builtin_non_tx_store (
+			     (uint64_t *)&counters.c1, counters.c1 + 1);
+      if (do_abort == 1)
+	{
+	  __builtin_tabort (256);
+	}
+      counters.c2 = counters.c2 + 10;
+      __builtin_non_tx_store ((uint64_t *)&counters.c3, 3);
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 100 * rc + 5;
+	}
+      if (counters.c1 != 2)
+	{
+	  return 100 * counters.c1 + 2;
+	}
+      if (counters.c2 != 10)
+	{
+	  return 100 * counters.c2 + 3;
+	}
+      if (counters.c3 != 3)
+	{
+	  return 100 * counters.c3 + 6;
+	}
+    }
+  else
+    {
+      return 100 * rc + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_retry_nofloat (void)
+{
+  int rc;
+
+  counters.c1 = 0;
+  counters.c2 = 0;
+  counters.c3 = 0;
+  if ((rc = __builtin_tbegin_retry_nofloat ((void *)0, 5)) == 0)
+    {
+      int do_abort;
+
+      do_abort = (counters.c1 == 0) ? 1 : 0;
+      __builtin_non_tx_store (
+			     (uint64_t *)&counters.c1, counters.c1 + 1);
+      if (do_abort == 1)
+	{
+	  __builtin_tabort (256);
+	}
+      counters.c2 = counters.c2 + 10;
+      __builtin_non_tx_store ((uint64_t *)&counters.c3, 3);
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 100 * rc + 5;
+	}
+      if (counters.c1 != 2)
+	{
+	  return 100 * counters.c1 + 2;
+	}
+      if (counters.c2 != 10)
+	{
+	  return 100 * counters.c2 + 3;
+	}
+      if (counters.c3 != 3)
+	{
+	  return 100 * counters.c3 + 6;
+	}
+    }
+  else
+    {
+      return 100 * rc + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_aborts (void)
+{
+  float f;
+  int rc;
+
+  f = 77;
+  if ((rc = __builtin_tbegin ((void *)0)) == 0)
+    {
+      f = 88;
+      __builtin_tabort (256);
+      return 2;
+    }
+  else if (rc != 2)
+    {
+      return 3;
+    }
+  if (f != 77)
+    {
+      return 4;
+    }
+  f = 66;
+  if ((rc = __builtin_tbegin ((void *)0)) == 0)
+    {
+      f = 99;
+      __builtin_tabort (257);
+      return 5;
+    }
+  else if (rc != 3)
+    {
+      return 100 * rc + 6;
+    }
+  if (f != 66)
+    {
+      return 100 * f + 7;
+    }
+  if ((rc = __builtin_tbegin ((void *)0)) == 0)
+    {
+      global.float_3 = global.float_1 + global.float_2;
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 100 * rc + 8;
+	}
+    }
+  else
+    {
+      return 100 * rc + 9;
+    }
+  if (global.float_3 != global.float_1 + global.float_2)
+    {
+      return 100 * rc + 10;
+    }
+
+  return 0;
+}
+
+static __attribute__((noinline)) void indirect_abort(int abort_code)
+{
+  __builtin_tabort (abort_code);
+
+  return;
+}
+
+static int test_tbegin_indirect_aborts (void)
+{
+  float f;
+  int rc;
+
+  f = 77;
+  if ((rc = __builtin_tbegin ((void *)0)) == 0)
+    {
+      f = 88;
+      indirect_abort(256);
+      return 2;
+    }
+  else if (rc != 2)
+    {
+      return 100 * rc + 3;
+    }
+  if (f != 77)
+    {
+      return 100 * rc + 4;
+    }
+  f = 66;
+  if ((rc = __builtin_tbegin ((void *)0)) == 0)
+    {
+      f = 99;
+      indirect_abort(257);
+      return 5;
+    }
+  else if (rc != 3)
+    {
+      return 100 * rc + 6;
+    }
+  if (f != 66)
+    {
+      return 100 * f + 7;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_nofloat_aborts (void)
+{
+  int rc;
+
+  if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
+    {
+      __builtin_tabort (256);
+      return 2;
+    }
+  if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
+    {
+      __builtin_tabort (257);
+      return 1005;
+    }
+  else if (rc != 3)
+    {
+      return 1000 * rc + 6;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_nofloat_indirect_aborts (void)
+{
+  int rc;
+
+  if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
+    {
+      indirect_abort (256);
+      return 2;
+    }
+  if ((rc = __builtin_tbegin_nofloat ((void *)0)) == 0)
+    {
+      indirect_abort (257);
+      return 1005;
+    }
+  else if (rc != 3)
+    {
+      return 1000 * rc + 6;
+    }
+
+  return 0;
+}
+
+static
+int _test_tbegin_retry_aborts (int retries, uint64_t abort_code)
+{
+  int rc;
+
+  counters.c1 = 0;
+  if ((rc = __builtin_tbegin_retry ((void *)0, retries)) == 0)
+    {
+      __builtin_non_tx_store ((uint64_t *)&counters.c1, counters.c1 + 1);
+      __builtin_tabort (abort_code);
+      return 2;
+    }
+  else
+    {
+      if ((abort_code & 1) == 0)
+	{
+	  if (rc != 2)
+	    {
+	      return 100 * rc + 2003;
+	    }
+	  else if (counters.c1 != (uint64_t)retries + 1)
+	    {
+	      return 1000 * counters.c1 + 100 * retries + 4;
+	    }
+	}
+      else
+	{
+	  if (rc != 3)
+	    {
+	      return 100 * rc + 3005;
+	    }
+	  else if (counters.c1 != 1)
+	    {
+	      return 1000 * counters.c1 + 100 * retries + 6;
+	    }
+	}
+    }
+
+  return 0;
+}
+
+static int test_tbegin_retry_aborts (void)
+{
+  int rc;
+  int retries;
+
+  for (retries = 1; retries <= 3; retries++)
+    {
+      rc = _test_tbegin_retry_aborts (retries, 256);
+      if (rc != 0)
+	{
+	  return 10000 + rc;
+	}
+    }
+  for (retries = 1; retries <= 3; retries++)
+    {
+      rc = _test_tbegin_retry_aborts (retries, 257);
+      if (rc != 0)
+	{
+	  return 20000 + rc;
+	}
+    }
+  if ((rc = __builtin_tbegin_retry ((void *)0, 5)) == 0)
+    {
+      global.float_3 = global.float_1 + global.float_2;
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 30000 + 100 * rc + 6;
+	}
+    }
+  else
+    {
+      return 30000 + 100 * rc + 7;
+    }
+
+  return 0;
+}
+
+static int _test_tbegin_retry_nofloat_aborts (int retries, uint64_t abort_code)
+{
+  int rc;
+
+  counters.c1 = 0;
+  if ((rc = __builtin_tbegin_retry_nofloat ((void *)0, retries)) == 0)
+    {
+      __builtin_non_tx_store ((uint64_t *)&counters.c1, counters.c1 + 1);
+      __builtin_tabort (abort_code);
+      return 2;
+    }
+  else
+    {
+      if ((abort_code & 1) == 0)
+	{
+	  if (rc != 2)
+	    {
+	      return 100 * rc + 2003;
+	    }
+	  else if (counters.c1 != (uint64_t)retries + 1)
+	    {
+	      return 1000 * counters.c1 + 100 * retries + 4;
+	    }
+	}
+      else
+	{
+	  if (rc != 3)
+	    {
+	      return 100 * rc + 3005;
+	    }
+	  else if (counters.c1 != 1)
+	    {
+	      return 1000 * counters.c1 + 100 * retries + 6;
+	    }
+	}
+    }
+
+  return 0;
+}
+
+static int test_tbegin_retry_nofloat_aborts (void)
+{
+  int rc;
+  int retries;
+
+  for (retries = 1; retries <= 3; retries++)
+    {
+      rc = _test_tbegin_retry_nofloat_aborts (retries, 256);
+      if (rc != 0)
+	{
+	  return 10 * retries + rc;
+	}
+    }
+  for (retries = 1; retries <= 3; retries++)
+    {
+      rc = _test_tbegin_retry_nofloat_aborts (retries, 257);
+      if (rc != 0)
+	{
+	  return 10000 + 10 * retries + rc;
+	}
+    }
+
+  return 0;
+}
+
+static int test_tbegin_tdb (void)
+{
+  int rc;
+
+  local_tdb.format = 0;
+  if ((rc = __builtin_tbegin (&local_tdb)) == 0)
+    {
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 100 * rc + 1;
+	}
+      if (local_tdb.format != 0)
+	{
+	  dump_tdb (&local_tdb);
+	  return 100 * local_tdb.format + 2;
+	}
+    }
+  else
+    {
+      return 100 * rc + 3;
+    }
+  local_tdb.format = 0;
+  if ((rc = __builtin_tbegin (&local_tdb)) == 0)
+    {
+      __builtin_tabort (257);
+      return 4;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 100 * rc + 5;
+	}
+      if (local_tdb.format != 1)
+	{
+	  dump_tdb (&local_tdb);
+	  return 100 * local_tdb.format + 6;
+	}
+    }
+  local_tdb256.format = 0;
+  if ((rc = __builtin_tbegin (&local_tdb256)) == 0)
+    {
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 1100 * rc + 1;
+	}
+      if (local_tdb256.format != 0)
+	{
+	  dump_tdb (&local_tdb256);
+	  return 1100 * local_tdb256.format + 2;
+	}
+    }
+  else
+    {
+      return 1100 * rc + 3;
+    }
+  local_tdb256.format = 0;
+  if ((rc = __builtin_tbegin (&local_tdb256)) == 0)
+    {
+      __builtin_tabort (257);
+      return 2004;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 2100 * rc + 5;
+	}
+      if (local_tdb256.format != 1)
+	{
+	  dump_tdb (&local_tdb256);
+	  return 2100 * local_tdb256.format + 6;
+	}
+    }
+
+  return 0;
+}
+
+static int test_tbegin_nofloat_tdb (void)
+{
+  int rc;
+
+  local_tdb.format = 0;
+  if ((rc = __builtin_tbegin_nofloat (&local_tdb)) == 0)
+    {
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 100 * rc + 1;
+	}
+      if (local_tdb.format != 0)
+	{
+	  dump_tdb (&local_tdb);
+	  return 100 * local_tdb.format + 2;
+	}
+    }
+  else
+    {
+      return 3;
+    }
+  local_tdb.format = 0;
+  if ((rc = __builtin_tbegin_nofloat (&local_tdb)) == 0)
+    {
+      __builtin_tabort (257);
+      return 4;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 100 * rc + 5;
+	}
+      if (local_tdb.format != 1)
+	{
+	  dump_tdb (&local_tdb);
+	  return 100 * local_tdb.format + 6;
+	}
+    }
+  local_tdb256.format = 0;
+  if ((rc = __builtin_tbegin_nofloat (&local_tdb256)) == 0)
+    {
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 1100 * rc + 1;
+	}
+      if (local_tdb256.format != 0)
+	{
+	  dump_tdb (&local_tdb256);
+	  return 1100 * local_tdb256.format + 2;
+	}
+    }
+  else
+    {
+      return 1003;
+    }
+  local_tdb256.format = 0;
+  if ((rc = __builtin_tbegin_nofloat (&local_tdb256)) == 0)
+    {
+      __builtin_tabort (257);
+      return 2004;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 2100 * rc + 5;
+	}
+      if (local_tdb256.format != 1)
+	{
+	  dump_tdb (&local_tdb256);
+	  return 2100 * local_tdb256.format + 6;
+	}
+    }
+
+  return 0;
+}
+
+static int test_tbegin_retry_tdb (void)
+{
+  int rc;
+
+  local_tdb256.format = 0;
+  if ((rc = __builtin_tbegin_retry (&local_tdb256, 2)) == 0)
+    {
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 1100 * rc + 1;
+	}
+      if (local_tdb256.format != 0)
+	{
+	  dump_tdb (&local_tdb256);
+	  return 1100 * local_tdb256.format + 2;
+	}
+    }
+  else
+    {
+      return 1003;
+    }
+  local_tdb256.format = 0;
+  if ((rc = __builtin_tbegin_retry (&local_tdb256, 2)) == 0)
+    {
+      __builtin_tabort (257);
+      return 2004;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 2100 * rc + 5;
+	}
+      if (local_tdb256.format != 1)
+	{
+	  dump_tdb (&local_tdb256);
+	  return 2100 * local_tdb256.format + 6;
+	}
+    }
+
+  return 0;
+}
+
+static int test_tbegin_retry_nofloat_tdb (void)
+{
+  int rc;
+
+  local_tdb.format = 0;
+  if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb, 2)) == 0)
+    {
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 100 * rc + 1;
+	}
+      if (local_tdb.format != 0)
+	{
+	  dump_tdb (&local_tdb);
+	  return 100 * local_tdb.format + 2;
+	}
+    }
+  else
+    {
+      return 100 * rc + 3;
+    }
+  local_tdb.format = 0;
+  if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb, 2)) == 0)
+    {
+      __builtin_tabort (257);
+      return 4;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 100 * rc + 5;
+	}
+      if (local_tdb.format != 1)
+	{
+	  dump_tdb (&local_tdb);
+	  return 100 * local_tdb.format + 6;
+	}
+    }
+  local_tdb256.format = 0;
+  if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb256, 2)) == 0)
+    {
+      rc = __builtin_tend ();
+      if (rc != 0)
+	{
+	  return 1100 * rc + 1;
+	}
+      if (local_tdb256.format != 0)
+	{
+	  dump_tdb (&local_tdb256);
+	  return 1100 * local_tdb256.format + 2;
+	}
+    }
+  else
+    {
+      return 1100 * rc + 3;
+    }
+  local_tdb256.format = 0;
+  if ((rc = __builtin_tbegin_retry_nofloat (&local_tdb256, 2)) == 0)
+    {
+      __builtin_tabort (257);
+      return 2004;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 2100 * rc + 5;
+	}
+      if (local_tdb256.format != 1)
+	{
+	  dump_tdb (&local_tdb256);
+	  return 2100 * local_tdb256.format + 6;
+	}
+    }
+
+  return 0;
+}
+
+static int test_etnd (void)
+{
+  int rc;
+
+  counters.c1 = 0;
+  counters.c2 = 0;
+  counters.c3 = 0;
+  if ((rc = __builtin_tbegin ((void *)0)) == 0)
+    {
+      counters.c1 = __builtin_tx_nesting_depth ();
+      if (__builtin_tbegin ((void *)0) == 0)
+	{
+	  counters.c2 = __builtin_tx_nesting_depth ();
+	  if (__builtin_tbegin ((void *)0) == 0)
+	    {
+	      counters.c3 = __builtin_tx_nesting_depth ();
+	      __builtin_tend ();
+	    }
+	  __builtin_tend ();
+	}
+      __builtin_tend ();
+    }
+  else
+    {
+      return 100 * rc + 1;
+    }
+  if (counters.c1 != 1)
+    {
+      return 100 * counters.c1 + 2;
+    }
+  if (counters.c2 != 2)
+    {
+      return 100 * counters.c2 + 3;
+    }
+  if (counters.c3 != 3)
+    {
+      return 100 * counters.c3 + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbeginc (void)
+{
+  int rc;
+
+  counters.c1 = 0;
+  __builtin_tbeginc ();
+  counters.c1 = 1;
+  rc = __builtin_tend ();
+  if (rc != 0)
+    {
+      return 10000 * rc + 1;
+    }
+  if (counters.c1 != 1)
+    {
+      return 100000 * counters.c1 + 3;
+    }
+
+  return 0;
+}
+
+/* ---------------------------- local testing framework functions ---------- */
+
+static int run_one_test (const test_table_entry_t *test_entry)
+{
+  int do_print_passes;
+  int succeeded;
+  int rc;
+  int i;
+
+  /* Warmup run to get all necessary data and instruction pages into the page
+   * tables.  */
+  {
+    int run;
+
+    do_dump_tdb = 0;
+    for (run = 0; run < NUM_WARMUP_RUNS; run++)
+      {
+	test_entry->test_func ();
+      }
+    do_dump_tdb = 1;
+  }
+  do_print_passes = (
+		     test_entry->required_quorum != 1 ||
+		     test_entry->max_repetitions != 1);
+  printf ("RRR RUN  %s\n", test_entry->name);
+  if (do_print_passes == 1)
+    {
+      printf (
+	     "         (requires %d successful out of %d runs)\n",
+	     test_entry->required_quorum,
+	     test_entry->max_repetitions);
+    }
+  succeeded = 0;
+  rc = 0;
+  for (rc = 0, i = 0; i < test_entry->max_repetitions; i++)
+    {
+      if (do_print_passes == 1)
+	{
+	  if (i == 0)
+	    {
+	      printf ("        ");
+	    }
+	  else
+	    {
+	      printf (",");
+	    }
+	}
+      rc = test_entry->test_func ();
+      if (rc == 0)
+	{
+	  if (do_print_passes == 1)
+	    {
+	      printf (" success");
+	    }
+	  succeeded++;
+	  if (succeeded >= test_entry->required_quorum)
+	    {
+	      break;
+	    }
+	}
+      else
+	{
+	  printf (" failed (rc = %d)", rc);
+	}
+    }
+  if (do_print_passes == 1 || rc != 0)
+    {
+      printf ("\n");
+    }
+  if (succeeded >= test_entry->required_quorum)
+    {
+      printf ("+++ OK   %s\n", test_entry->name);
+
+      return 0;
+    }
+  else
+    {
+      printf ("--- FAIL %s\n", test_entry->name);
+
+      return (rc != 0) ? rc : -1;
+    }
+}
+
+static int run_all_tests (const test_table_entry_t *test_table)
+{
+  const test_table_entry_t *test;
+  int rc;
+
+  for (
+       rc = 0, test = &test_table[0];
+       test->test_func != NULL && rc == 0; test++)
+    {
+      rc = run_one_test (test);
+    }
+
+  return rc;
+}
+
+/* ---------------------------- interface functions ------------------------ */
+
+int main (void)
+{
+  const test_table_entry_t test_table[] = {
+    TEST_NO_REP (test_constants),
+    TEST_DF_REP (test_tbegin_ntstg_tend),
+    TEST_DF_REP (test_tbegin_ntstg_tabort),
+    TEST_DF_REP (test_tbegin_nofloat),
+    TEST_NO_REP (test_tbegin_retry),
+    TEST_NO_REP (test_tbegin_retry_nofloat),
+    TEST_DF_REP (test_tbegin_aborts),
+    TEST_DF_REP (test_tbegin_indirect_aborts),
+    TEST_DF_REP (test_tbegin_nofloat_aborts),
+    TEST_DF_REP (test_tbegin_nofloat_indirect_aborts),
+    TEST_NO_REP (test_tbegin_retry_aborts),
+    TEST_NO_REP (test_tbegin_retry_nofloat_aborts),
+    TEST_DF_REP (test_tbegin_tdb),
+    TEST_DF_REP (test_tbegin_nofloat_tdb),
+    TEST_NO_REP (test_tbegin_retry_tdb),
+    TEST_NO_REP (test_tbegin_retry_nofloat_tdb),
+    TEST_DF_REP (test_etnd),
+    TEST_DF_REP (test_tbeginc),
+    { (void *)0, 0, 0 }
+  };
+
+  {
+    int rc;
+
+    rc = run_all_tests (test_table);
+
+    return rc;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-2.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-2.c
new file mode 100644
index 000000000..15b0d12ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-2.c
@@ -0,0 +1,682 @@
+/* Functional tests of the htm __TM_... macros.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target htm } */
+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
+
+/* ---------------------------- included header files ---------------------- */
+
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+#include <htmxlintrin.h>
+
+/* ---------------------------- local definitions -------------------------- */
+
+#define DEFAULT_MAX_REPETITIONS 5
+#define DEFAULT_REQUIRED_QUORUM ((DEFAULT_MAX_REPETITIONS) - 1)
+#define DEFAULT_ABORT_ADDRESS (0x12345678u)
+
+/* ---------------------------- local macros ------------------------------- */
+
+#define TEST_DF_REP(name) \
+  { #name, name, DEFAULT_MAX_REPETITIONS, DEFAULT_REQUIRED_QUORUM }
+#define TEST_NO_REP(name) { #name, name, 1, 1 }
+
+/* ---------------------------- local types -------------------------------- */
+
+typedef int (*test_func_t)(void);
+
+typedef struct
+{
+  const char *name;
+  test_func_t test_func;
+  int max_repetitions;
+  int required_quorum;
+} test_table_entry_t;
+
+typedef enum
+{
+  ABORT_T_SYSTEM = 0,
+  ABORT_T_USER = 1,
+} abort_user_t;
+
+typedef enum
+{
+  ABORT_T_NONE = 0,
+  ABORT_T_ILLEGAL,
+  ABORT_T_FOOTPRINT_EXCEEDED,
+  ABORT_T_NESTED_TOO_DEEP,
+  ABORT_T_CONFLICT,
+
+  ABORT_T_INVALID_ABORT_CODE
+} abort_t;
+
+/* ---------------------------- local variables ---------------------------- */
+
+__attribute__ ((aligned(256))) static struct __htm_tdb local_tdb256;
+static struct __htm_tdb local_tdb;
+
+static abort_t const abort_classes[] =
+{
+  ABORT_T_INVALID_ABORT_CODE,
+  ABORT_T_NONE,
+  ABORT_T_NONE,
+  ABORT_T_NONE,
+
+  ABORT_T_ILLEGAL,
+  ABORT_T_NONE,
+  ABORT_T_NONE,
+  ABORT_T_FOOTPRINT_EXCEEDED,
+
+  ABORT_T_FOOTPRINT_EXCEEDED,
+  ABORT_T_CONFLICT,
+  ABORT_T_CONFLICT,
+  ABORT_T_ILLEGAL,
+
+  ABORT_T_NONE,
+  ABORT_T_NESTED_TOO_DEEP,
+  ABORT_T_NONE,
+  ABORT_T_NONE,
+
+  ABORT_T_NONE
+};
+
+static size_t num_abort_classes = sizeof(abort_classes) / sizeof(abort_t);
+
+/* ---------------------------- exported variables (globals) --------------- */
+
+int global_int = 0;
+uint64_t global_u64 = 0;
+float global_float_1 = 1.0;
+float global_float_2 = 2.5;
+float global_float_3 = 0.0;
+__attribute__ ((aligned(256))) struct
+{
+  volatile uint64_t c1;
+  volatile uint64_t c2;
+  volatile uint64_t c3;
+} counters = { 0, 0, 0 };
+
+/* ---------------------------- local helper functions --------------------- */
+
+static void dump_tdb(struct __htm_tdb *tdb)
+{
+  unsigned char *p;
+  int i;
+  int j;
+
+  p = (unsigned char *)tdb;
+  for (i = 0; i < 16; i++)
+    {
+      fprintf(stderr, "0x%02x  ", i * 16);
+      for (j = 0; j < 16; j++)
+	{
+	  fprintf(stderr, "%02x", (int)p[i * 16 + j]);
+	  if (j < 15)
+	    {
+	      fprintf(stderr, " ");
+	    }
+	  if (j == 7)
+	    {
+	      fprintf(stderr, " ");
+	    }
+	}
+      fprintf(stderr, "\n");
+    }
+
+  return;
+}
+
+static void make_fake_tdb(struct __htm_tdb *tdb)
+{
+  memset(tdb, 0, sizeof(*tdb));
+  tdb->format = 1;
+  tdb->nesting_depth = 1;
+  tdb->atia = DEFAULT_ABORT_ADDRESS;
+  tdb->abort_code = 11;
+
+  return;
+}
+
+static int check_abort_code_in_tdb(struct __htm_tdb *tdb, uint64_t abort_code)
+{
+  long expect_rc;
+  long rc;
+
+  if (abort_code != 0)
+    {
+      long addr;
+
+      addr = __TM_failure_address(&local_tdb);
+      if (addr != DEFAULT_ABORT_ADDRESS)
+	{
+	  return 11;
+	}
+    }
+  {
+    long long tdb_abort_code;
+
+    tdb_abort_code = __TM_failure_code(tdb);
+    if ((uint64_t)tdb_abort_code != abort_code)
+      {
+	fprintf(
+		stderr, "tm_ac %" PRIu64 ", ac %" PRIu64
+		", tdb_ac %" PRIu64 "\n",
+		(uint64_t)tdb_abort_code, abort_code,
+		(uint64_t)tdb->abort_code);
+	return 10;
+      }
+  }
+  expect_rc = (abort_code >= 256) ? 1 : 0;
+  rc = __TM_is_user_abort(tdb);
+  if (rc != expect_rc)
+    {
+      fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
+      return 1;
+    }
+  {
+    unsigned char code;
+
+    code = 0xffu;
+    rc = __TM_is_named_user_abort(tdb, &code);
+    if (rc != expect_rc)
+      {
+	fprintf(
+		stderr, "rc %ld, expect_rc %ld\n", rc,
+		expect_rc);
+	return 2;
+      }
+    if (expect_rc == 1 && code != abort_code - 256)
+      {
+	return 3;
+      }
+  }
+  if (abort_code > (uint64_t)num_abort_classes)
+    {
+      abort_code = (uint64_t)num_abort_classes;
+    }
+  expect_rc = (abort_classes[abort_code] == ABORT_T_ILLEGAL) ? 1 : 0;
+  rc = __TM_is_illegal(tdb);
+  if (rc != expect_rc)
+    {
+      dump_tdb(tdb);
+      fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
+      return 4;
+    }
+  expect_rc =
+    (abort_classes[abort_code] == ABORT_T_FOOTPRINT_EXCEEDED) ?
+    1 : 0;
+  rc = __TM_is_footprint_exceeded(tdb);
+  if (rc != expect_rc)
+    {
+      dump_tdb(tdb);
+      fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
+      return 5;
+    }
+  expect_rc =
+    (abort_classes[abort_code] == ABORT_T_NESTED_TOO_DEEP) ? 1 : 0;
+  rc = __TM_is_nested_too_deep(tdb);
+  if (rc != expect_rc)
+    {
+      dump_tdb(tdb);
+      fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
+      return 6;
+    }
+  expect_rc = (abort_classes[abort_code] == ABORT_T_CONFLICT) ? 1 : 0;
+  rc = __TM_is_conflict(tdb);
+  if (rc != expect_rc)
+    {
+      dump_tdb(tdb);
+      fprintf(stderr, "rc %ld, expect_rc %ld\n", rc, expect_rc);
+      return 7;
+    }
+
+  return 0;
+}
+
+/* ---------------------------- local test functions ----------------------- */
+
+/* Not a test; make sure that the involved global cachelines are reserved for
+ * writing.  */
+static int init_cache(void)
+{
+  make_fake_tdb(&local_tdb);
+  make_fake_tdb(&local_tdb256);
+  global_int = 0;
+  global_u64 = 0;
+  global_float_1 = 1.0;
+  global_float_2 = 2.5;
+  global_float_3 = 0.0;
+  counters.c1 = 0;
+  counters.c2 = 0;
+  counters.c3 = 0;
+
+  return 0;
+}
+
+static int test_abort_classification(void)
+{
+  int i;
+
+  make_fake_tdb(&local_tdb);
+  for (i = 0; i <= 256; i++)
+    {
+      int rc;
+
+      local_tdb.abort_code = (uint64_t)i;
+      rc = check_abort_code_in_tdb(&local_tdb, (uint64_t)i);
+      if (rc != 0)
+	{
+	  return 100 * i + rc;
+	}
+    }
+
+  return 0;
+}
+
+static int test_cc_classification(void)
+{
+  long rc;
+
+  rc = __TM_is_failure_persistent(0);
+  if (rc != 0)
+    {
+      return 1;
+    }
+  rc = __TM_is_failure_persistent(1);
+  if (rc != 0)
+    {
+      return 2;
+    }
+  rc = __TM_is_failure_persistent(2);
+  if (rc != 0)
+    {
+      return 3;
+    }
+  rc = __TM_is_failure_persistent(3);
+  if (rc != 1)
+    {
+      return 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_ntstg_tend(void)
+{
+  long rc;
+
+  counters.c1 = 0;
+  counters.c2 = 0;
+  if ((rc = __TM_simple_begin()) == 0)
+    {
+      __TM_non_transactional_store((uint64_t *)&counters.c1, 1);
+      counters.c2 = 2;
+      rc = __TM_end();
+      if (rc != 0)
+	{
+	  return 100 * rc + 5;
+	}
+      if (counters.c1 != 1)
+	{
+	  return 100 * counters.c1 + 2;
+	}
+      if (counters.c2 != 2)
+	{
+	  return 100 * counters.c2 + 3;
+	}
+    }
+  else
+    {
+      return 100 * rc + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_ntstg_tabort(void)
+{
+  register float f;
+
+  counters.c1 = 0;
+  counters.c2 = 0;
+  f = 0;
+  if (__TM_simple_begin() == 0)
+    {
+      __TM_non_transactional_store((uint64_t *)&counters.c1, 1);
+      counters.c2 = 2;
+      f = 1;
+      __TM_named_abort(0);
+      return 1;
+    }
+  if (counters.c1 != 1)
+    {
+      return 100 * counters.c1 + 2;
+    }
+  if (counters.c2 != 0)
+    {
+      return 100 * counters.c2 + 3;
+    }
+  if (f != 0)
+    {
+      return 100 * f + 4;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_aborts(void)
+{
+  float f;
+  long rc;
+
+  f = 77;
+  if ((rc = __TM_simple_begin()) == 0)
+    {
+      f = 88;
+      __TM_abort();
+      return 2;
+    }
+  else if (rc != 2)
+    {
+      return 3;
+    }
+  if (f != 77)
+    {
+      return 4;
+    }
+  f = 66;
+  if ((rc = __TM_simple_begin()) == 0)
+    {
+      f = 99;
+      __TM_named_abort(3);
+      return 5;
+    }
+  else if (rc != 3)
+    {
+      return 100 * rc + 6;
+    }
+  if (f != 66)
+    {
+      return 100 * f + 7;
+    }
+  if ((rc = __TM_simple_begin()) == 0)
+    {
+      global_float_3 = global_float_1 + global_float_2;
+      rc = __TM_end();
+      if (rc != 0)
+	{
+	  return 100 * rc + 8;
+	}
+    }
+  else
+    {
+      return 100 * rc + 9;
+    }
+  if (global_float_3 != global_float_1 + global_float_2)
+    {
+      return 100 * rc + 10;
+    }
+
+  return 0;
+}
+
+static int test_tbegin_tdb(void)
+{
+  long rc;
+
+  local_tdb.format = 0;
+  if ((rc = __TM_begin(&local_tdb)) == 0)
+    {
+      rc = __TM_end();
+      if (rc != 0)
+	{
+	  return 100 * rc + 1;
+	}
+      if (local_tdb.format != 0)
+	{
+	  dump_tdb(&local_tdb);
+	  return 100 * local_tdb.format + 2;
+	}
+    }
+  else
+    {
+      return 100 * rc + 3;
+    }
+  local_tdb.format = 0;
+  if ((rc = __TM_begin(&local_tdb)) == 0)
+    {
+      __TM_named_abort(1);
+      return 4;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 100 * rc + 5;
+	}
+      if (local_tdb.format != 1)
+	{
+	  dump_tdb(&local_tdb);
+	  return 100 * local_tdb.format + 6;
+	}
+    }
+  local_tdb256.format = 0;
+  if ((rc = __TM_begin(&local_tdb256)) == 0)
+    {
+      rc = __TM_end();
+      if (rc != 0)
+	{
+	  return 1100 * rc + 1;
+	}
+      if (local_tdb256.format != 0)
+	{
+	  dump_tdb(&local_tdb256);
+	  return 1100 * local_tdb256.format + 2;
+	}
+    }
+  else
+    {
+      return 1100 * rc + 3;
+    }
+#if 1 /*!!!does not work*/
+  local_tdb256.format = 0;
+  if ((rc = __TM_begin(&local_tdb256)) == 0)
+    {
+      __TM_named_abort(1);
+      return 2004;
+    }
+  else
+    {
+      if (rc != 3)
+	{
+	  return 2100 * rc + 5;
+	}
+      if (local_tdb256.format != 1)
+	{
+	  dump_tdb(&local_tdb256);
+	  return 2100 * local_tdb256.format + 6;
+	}
+    }
+#endif
+
+  return 0;
+}
+
+static int test_etnd(void)
+{
+  long rc;
+
+  {
+    long nd;
+
+    make_fake_tdb(&local_tdb);
+    local_tdb.nesting_depth = 0;
+    nd = __TM_nesting_depth(&local_tdb);
+    if (nd != 0)
+      {
+	return 1;
+      }
+    local_tdb.nesting_depth = 7;
+    nd = __TM_nesting_depth(&local_tdb);
+    if (nd != 7)
+      {
+	return 7;
+      }
+    local_tdb.format = 0;
+    nd = __TM_nesting_depth(&local_tdb);
+    if (nd != 0)
+      {
+	return 2;
+      }
+  }
+  counters.c1 = 0;
+  counters.c1 = 0;
+  counters.c2 = 0;
+  counters.c3 = 0;
+  if ((rc = __TM_simple_begin()) == 0)
+    {
+      counters.c1 = __TM_nesting_depth(0);
+      if (__TM_simple_begin() == 0)
+	{
+	  counters.c2 = __TM_nesting_depth(0);
+	  if (__TM_simple_begin() == 0)
+	    {
+	      counters.c3 = __TM_nesting_depth(0);
+	      __TM_end();
+	    }
+	  __TM_end();
+	}
+      __TM_end();
+    }
+  else
+    {
+      return 100 * rc + 1;
+    }
+  if (counters.c1 != 1)
+    {
+      return 100 * counters.c1 + 2;
+    }
+  if (counters.c2 != 2)
+    {
+      return 100 * counters.c2 + 3;
+    }
+  if (counters.c3 != 3)
+    {
+      return 100 * counters.c3 + 4;
+    }
+
+  return 0;
+}
+
+/* ---------------------------- local testing framework functions ---------- */
+
+static int run_one_test(const test_table_entry_t *test_entry)
+{
+  int do_print_passes;
+  int succeeded;
+  int rc;
+  int i;
+
+  do_print_passes = (
+		     test_entry->required_quorum != 1 ||
+		     test_entry->max_repetitions != 1);
+  printf("RRR RUN  %s\n", test_entry->name);
+  if (do_print_passes == 1)
+    {
+      printf(
+	     "         (requires %d successful out of %d runs)\n",
+	     test_entry->required_quorum,
+	     test_entry->max_repetitions);
+    }
+  succeeded = 0;
+  rc = 0;
+  for (rc = 0, i = 0; i < test_entry->max_repetitions; i++)
+    {
+      if (do_print_passes == 1)
+	{
+	  if (i == 0)
+	    {
+	      printf("        ");
+	    }
+	  else
+	    {
+	      printf(",");
+	    }
+	}
+      rc = test_entry->test_func();
+      if (rc == 0)
+	{
+	  if (do_print_passes == 1)
+	    {
+	      printf(" success");
+	    }
+	  succeeded++;
+	  if (succeeded >= test_entry->required_quorum)
+	    {
+	      break;
+	    }
+	}
+      else
+	{
+	  printf(" failed (rc = %d)", rc);
+	}
+    }
+  if (do_print_passes == 1 || rc != 0)
+    {
+      printf("\n");
+    }
+  if (succeeded >= test_entry->required_quorum)
+    {
+      printf("+++ OK   %s\n", test_entry->name);
+
+      return 0;
+    }
+  else
+    {
+      printf("--- FAIL %s\n", test_entry->name);
+
+      return (rc != 0) ? rc : -1;
+    }
+}
+
+static int run_all_tests(const test_table_entry_t *test_table)
+{
+  const test_table_entry_t *test;
+  int rc;
+
+  for (
+       rc = 0, test = &test_table[0];
+       test->test_func != NULL && rc == 0; test++)
+    {
+      rc = run_one_test(test);
+    }
+
+  return rc;
+}
+
+/* ---------------------------- interface functions ------------------------ */
+
+int main(void)
+{
+  const test_table_entry_t test_table[] = {
+    TEST_NO_REP(init_cache),
+    TEST_NO_REP(test_abort_classification),
+    TEST_NO_REP(test_cc_classification),
+    TEST_DF_REP(test_tbegin_ntstg_tend),
+    TEST_DF_REP(test_tbegin_ntstg_tabort),
+    TEST_DF_REP(test_tbegin_aborts),
+    TEST_DF_REP(test_tbegin_tdb),
+    TEST_DF_REP(test_etnd),
+    { (void *)0, 0, 0 }
+  };
+
+  {
+    int rc;
+
+    rc = run_all_tests(test_table);
+
+    return rc;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c
new file mode 100644
index 000000000..c1b98e2bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c
@@ -0,0 +1,164 @@
+/* This checks the availability of the low-level builtins introduced
+   for transactional execution.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
+
+#include <stdint.h>
+#include <htmintrin.h>
+
+int global = 0;
+uint64_t g;
+struct __htm_tdb global_tdb;
+
+int
+foo (struct __htm_tdb* tdb, int reg, int *mem, uint64_t *mem64)
+{
+
+  int cc;
+  int n;
+
+  __builtin_tbegin ((void *)0);
+  __builtin_tbegin ((void *)-99999);
+  __builtin_tbegin ((void *)99999);
+  while (__builtin_tbegin ((void *)0) != 0)
+  {
+  }
+  cc = __builtin_tbegin ((void *)0x12345678);
+  cc = __builtin_tbegin (tdb);
+  cc = __builtin_tbegin (&global_tdb);
+  cc = __builtin_tbegin ((void *)(long long)(reg + 0x12345678));
+  cc = __builtin_tbegin ((void *)(long long)(reg));
+
+  __builtin_tbegin_nofloat ((void *)0);
+  __builtin_tbegin_nofloat ((void *)-99999);
+  __builtin_tbegin_nofloat ((void *)99999);
+  cc = __builtin_tbegin_nofloat ((void *)0x12345678);
+  cc = __builtin_tbegin_nofloat (tdb);
+  cc = __builtin_tbegin_nofloat (&global_tdb);
+  cc = __builtin_tbegin_nofloat ((void *)(long long)(reg + 0x12345678));
+  cc = __builtin_tbegin_nofloat ((void *)(long long)(reg));
+
+  __builtin_tbegin_retry ((void *)0, 0);
+  cc = __builtin_tbegin_retry ((void *)0, 1);
+  cc = __builtin_tbegin_retry ((void *)0, -1);
+  cc = __builtin_tbegin_retry ((void *)0, 42);
+  cc = __builtin_tbegin_retry ((void *)0, reg);
+  cc = __builtin_tbegin_retry ((void *)0, *mem);
+  cc = __builtin_tbegin_retry ((void *)0, global);
+  cc = __builtin_tbegin_retry (tdb, 42);
+  cc = __builtin_tbegin_retry (&global_tdb, 42);
+  cc = __builtin_tbegin_retry ((void *)0x12345678, global);
+  cc = __builtin_tbegin_retry (
+	  (void *)(long long) (reg + 0x12345678), global + 1);
+  cc = __builtin_tbegin_retry (
+	  (void *)(long long)(reg), global - 1);
+
+  __builtin_tbegin_retry_nofloat ((void *)0, 0);
+  cc = __builtin_tbegin_retry_nofloat ((void *)0, 1);
+  cc = __builtin_tbegin_retry_nofloat ((void *)0, -1);
+  cc = __builtin_tbegin_retry_nofloat ((void *)0, 42);
+  cc = __builtin_tbegin_retry_nofloat ((void *)0, reg);
+  cc = __builtin_tbegin_retry_nofloat ((void *)0, *mem);
+  cc = __builtin_tbegin_retry_nofloat ((void *)0, global);
+  cc = __builtin_tbegin_retry_nofloat (tdb, 42);
+  cc = __builtin_tbegin_retry_nofloat (&global_tdb, 42);
+  cc = __builtin_tbegin_retry_nofloat ((void *)0x12345678, global);
+  cc = __builtin_tbegin_retry_nofloat (
+	  (void *)(long long) (reg + 0x12345678), global + 1);
+  cc = __builtin_tbegin_retry_nofloat (
+	  (void *)(long long)(reg), global - 1);
+
+  __builtin_tbeginc ();
+
+  __builtin_tx_nesting_depth ();
+  n = __builtin_tx_nesting_depth ();
+
+  __builtin_non_tx_store (mem64, 0);
+  {
+	  const uint64_t val_var = 0x1122334455667788;
+
+	  __builtin_non_tx_store (mem64, val_var);
+  }
+  __builtin_non_tx_store (mem64, (uint64_t)reg);
+  __builtin_non_tx_store (mem64, g);
+  __builtin_non_tx_store ((uint64_t *)0, 0);
+  __builtin_non_tx_store ((uint64_t *)0x12345678, 0);
+  __builtin_non_tx_store (&g, 23);
+  __builtin_non_tx_store (&g, reg);
+  __builtin_non_tx_store (&g, *mem);
+  __builtin_non_tx_store (&g, global);
+
+  __builtin_tend();
+
+  __builtin_tx_assist (0);
+  __builtin_tx_assist (1);
+  __builtin_tx_assist (reg);
+  __builtin_tx_assist (*mem);
+  __builtin_tx_assist (global);
+}
+
+/* The taborts must go into separate function since they are
+   "noreturn".  */
+
+void
+tabort1 ()
+{
+  __builtin_tabort (256);
+}
+
+void
+tabort2 (int reg)
+{
+  __builtin_tabort (reg);
+}
+
+void
+tabort3 (int reg)
+{
+  /* { dg-final { scan-assembler-times "tabort\t255" 1 } } */
+  __builtin_tabort (reg + 255);
+}
+
+void
+tabort4 (int *mem)
+{
+  __builtin_tabort (*mem);
+}
+
+void
+tabort5 ()
+{
+  __builtin_tabort (global);
+}
+
+void
+tabort6 (int *mem)
+{
+  /* Here global + 255 gets reloaded into a reg.  Better would be to
+     just reload global or *mem and get the +255 for free as address
+     arithmetic.  */
+  __builtin_tabort (*mem + 255);
+}
+
+void
+tabort7 ()
+{
+  __builtin_tabort (global + 255);
+}
+
+void
+tabort8 ()
+{
+  __builtin_tabort (-1);
+}
+
+
+/* Make sure the tdb NULL argument ends up as immediate value in the
+   instruction.  */
+/* { dg-final { scan-assembler-times "tbegin\t0," 17 } } */
+/* { dg-final { scan-assembler-times "tbegin\t" 41 } } */
+/* Check number of occurences of certain instructions.  */
+/* { dg-final { scan-assembler-times "tbeginc\t" 1 } } */
+/* { dg-final { scan-assembler-times "tabort\t" 8 } } */
+/* { dg-final { scan-assembler "ppa\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c
new file mode 100644
index 000000000..67d76a6d3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
+
+void must_not_compile1 (void)
+{
+  __builtin_tabort (0); /* { dg-error "Invalid transaction abort code:" } */
+}
+
+void must_not_compile2 (void)
+{
+  __builtin_tabort (255); /* { dg-error "Invalid transaction abort code:" } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c
new file mode 100644
index 000000000..77ceeb770
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c
@@ -0,0 +1,37 @@
+/* This checks the availability of the XL compiler intrinsics for
+   transactional execution with the expected prototypes.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
+
+#include <htmxlintrin.h>
+
+int a = 0;
+unsigned long g;
+
+int
+foo ()
+{
+  struct __htm_tdb *tdb_struct;
+  void * const tdb = tdb_struct;
+  long result;
+  unsigned char code;
+
+  result = __TM_simple_begin ();
+  result = __TM_begin (tdb);
+  result = __TM_end ();
+  __TM_abort ();
+  __TM_named_abort (42);
+  __TM_non_transactional_store (&g, 42);
+  result = __TM_nesting_depth (tdb);
+
+  result = __TM_is_user_abort (tdb);
+  result = __TM_is_named_user_abort (tdb, &code);
+  result = __TM_is_illegal (tdb);
+  result = __TM_is_footprint_exceeded (tdb);
+  result = __TM_is_nested_too_deep (tdb);
+  result = __TM_is_conflict (tdb);
+  result = __TM_is_failure_persistent (result);
+  result = __TM_failure_address (tdb);
+  result = __TM_failure_code (tdb);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c
new file mode 100644
index 000000000..df7e2bac8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=zEC12 -mzarch" } */
+
+int
+foo ()
+{
+  __builtin_tbegin_nofloat (0);
+  __builtin_tbegin_retry_nofloat (0, 42);
+}
+/* Make sure no FPR saves/restores are emitted.  */
+/* { dg-final { scan-assembler-not "std" } } */
+/* { dg-final { scan-assembler-not "ld" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c
new file mode 100644
index 000000000..59621a4c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c
@@ -0,0 +1,55 @@
+/* { dg-do run } */
+/* { dg-options "-O3 -mhtm -Wa,-march=zEC12,-mzarch --save-temps" } */
+
+/* __builtin_tbegin has to emit clobbers for all FPRs since the tbegin
+   instruction does not automatically preserves them.  If the
+   transaction body is fully contained in a function the backend tries
+   after reload to get rid of the FPR save/restore operations
+   triggered by the clobbers.  This testcase failed since the backend
+   was able to get rid of all FPR saves/restores and since these were
+   the only stack operations also of the entire stack space.  So even
+   the save/restore of the stack pointer was omitted in the end.
+   However, since the frame layout has been fixed before, the prologue
+   still generated the stack pointer decrement making foo return with
+   a modified stack pointer.  */
+
+void abort(void);
+
+void __attribute__((noinline))
+foo (int a)
+{
+  /* This is just to prevent the tbegin code from actually being
+     executed.  That way the test may even run on machines prior to
+     zEC12.  */
+  if (a == 42)
+    return;
+
+  if (__builtin_tbegin (0) == 0)
+    __builtin_tend ();
+}
+
+#ifdef __s390x__
+#define GET_STACK_POINTER(SP)			\
+  asm volatile ("stg %%r15, %0" : "=QRST" (SP));
+#else
+#define GET_STACK_POINTER(SP)			\
+  asm volatile ("st %%r15, %0" : "=QR" (SP));
+#endif
+
+int main(void)
+{
+  unsigned long new_sp, old_sp;
+
+  GET_STACK_POINTER (old_sp);
+  foo(42);
+  GET_STACK_POINTER (new_sp);
+
+  if (old_sp != new_sp)
+    abort ();
+
+  return 0;
+}
+
+/* Make sure no FPR saves/restores are emitted.  */
+/* { dg-final { scan-assembler-not "\tstd\t" } } */
+/* { dg-final { scan-assembler-not "\tld\t" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/nearestint-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/nearestint-1.c
new file mode 100644
index 000000000..1d9a753b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/nearestint-1.c
@@ -0,0 +1,48 @@
+/* Since z196 the nearest integer functions can be expanded to single
+   instructions.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=z196 -mzarch" } */
+
+extern float ceilf (float x);
+extern double ceil (double x);
+extern long double ceill (long double x);
+extern float floorf (float x);
+extern double floor (double x);
+extern long double floorl (long double x);
+extern float truncf (float x);
+extern double trunc (double x);
+extern long double truncl (long double x);
+extern float nearbyintf (float x);
+extern double nearbyint (double x);
+extern long double nearbyintl (long double x);
+extern float rintf (float x);
+extern double rint (double x);
+extern long double rintl (long double x);
+
+float my_ceilf (float x) { return ceilf (x); }
+double my_ceil (double x) { return ceil (x); }
+long double my_ceill (long double x) { return ceill (x); }
+
+float my_floorf (float x) { return floorf (x); }
+double my_floor (double x) { return floor (x); }
+long double my_floorl (long double x) { return floorl (x); }
+
+float my_truncf (float x) { return truncf (x); }
+double my_trunc (double x) { return trunc (x); }
+long double my_truncl (long double x) { return truncl (x); }
+
+float my_nearbyintf (float x) { return nearbyintf (x); }
+double my_nearbyint (double x) { return nearbyint (x); }
+long double my_nearbyintl (long double x) { return nearbyintl (x); }
+
+float my_rintf (float x) { return rintf (x); }
+double my_rint (double x) { return rint (x); }
+long double my_rintl (long double x) { return rintl (x); }
+
+/* { dg-final { scan-assembler-times "fiebr\t" 1 } } */
+/* { dg-final { scan-assembler-times "fidbr\t" 1 } } */
+/* { dg-final { scan-assembler-times "fixbr\t" 1 } } */
+/* { dg-final { scan-assembler-times "fiebra\t" 4 } } */
+/* { dg-final { scan-assembler-times "fidbra\t" 4 } } */
+/* { dg-final { scan-assembler-times "fixbra\t" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/pr20927.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr20927.c
new file mode 100644
index 000000000..dbc990f15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr20927.c
@@ -0,0 +1,23 @@
+/* This caused an ICE on s390x due to a reload inheritance bug.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+struct point { double x, y; };
+extern void use (struct point);
+
+void test (struct point *pc, struct point p1)
+{
+  struct point p0 = *pc;
+
+  if (p0.x == p1.x && p0.y == p1.y)
+    use (p0);
+
+  asm ("" : : : "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10");
+
+  p1.y -= p0.y;
+
+  use (p0);
+  use (p1);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/pr24624.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr24624.c
new file mode 100644
index 000000000..bc2070c4b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr24624.c
@@ -0,0 +1,67 @@
+/* This used to ICE due to a backend problem on s390.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O1 -mpacked-stack" } */
+
+typedef unsigned int __u32;
+typedef struct
+{
+  volatile int counter;
+} __attribute__ ((aligned (4))) atomic_t;
+static __inline__ __attribute__ ((always_inline))
+     void atomic_inc (volatile atomic_t * v)
+{
+  (
+    {
+    typeof (v->counter) old_val, new_val;
+  __asm__ __volatile__ (
+	"   l     %0,0(%3)\n" 
+	"0: lr    %1,%0\n" 
+	"   ar    %1,%4\n" 
+	"   cs    %0,%1,0(%3)\n" 
+	"   jl    0b": 
+	"=&d" (old_val), "=&d" (new_val), "=m" (((atomic_t *) (v))->counter): 
+	"a" (v), "d" (1), "m" (((atomic_t *) (v))->counter):
+	"cc", "memory");
+    });
+}
+extern unsigned long volatile __attribute__ ((section (".data"))) jiffies;
+struct inet_peer
+{
+  unsigned long dtime;
+  atomic_t refcnt;
+};
+static volatile int peer_total;
+int inet_peer_threshold = 65536 + 128;
+int inet_peer_minttl = 120 * 100;
+int inet_peer_maxttl = 10 * 60 * 100;
+static int
+cleanup_once (unsigned long ttl)
+{
+  struct inet_peer *p;
+  if (p != ((void *) 0))
+    {
+      if (((
+	     {
+	     1;}
+	   ) && ((long) (jiffies) - (long) (p->dtime + ttl) < 0)))
+	{
+	  return -1;
+	}
+      atomic_inc (&p->refcnt);
+    }
+}
+struct inet_peer *
+inet_getpeer (__u32 daddr, int create)
+{
+  int i;
+  int ttl;
+  if (peer_total >= inet_peer_threshold)
+    ttl = inet_peer_minttl;
+  else
+    ttl =
+      inet_peer_maxttl - (inet_peer_maxttl -
+			  inet_peer_minttl) / 100 * peer_total /
+      inet_peer_threshold * 100;
+  for (i = 0; i < 30 && !cleanup_once (ttl); i++);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/pr27661.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr27661.c
new file mode 100644
index 000000000..1ff6dcc7c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr27661.c
@@ -0,0 +1,25 @@
+/* This used to ICE on s390 due to a reload bug.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=z990 -ftracer" } */
+
+extern int memcmp (const void *s1, const void *s2, unsigned long n);
+extern int printf (__const char *__restrict __format, ...);
+
+struct test
+{
+  char tmp[4096];
+  char msgtype[2];
+};
+
+void test (struct test *testtb)
+{
+  if (testtb)
+    printf ("a");
+
+  if (memcmp(testtb->msgtype, "a", 2))
+    printf ("a");
+
+  printf ("b");
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/pr36822.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr36822.c
new file mode 100644
index 000000000..fb021f214
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr36822.c
@@ -0,0 +1,16 @@
+/* This used to ICE on s390 due to bug in the definition of the 'R'
+   constraint which replaced the 'm' constraint (together with 'T')
+   while adding z10 support.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+int boo()
+{
+  struct {
+    unsigned char pad[4096];
+    unsigned long bar;
+  } *foo;
+  asm volatile( "" : "=m" (*(unsigned long long*)(foo->bar))
+		: "a" (&foo->bar));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/pr42224.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr42224.c
new file mode 100644
index 000000000..c1ccf28d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr42224.c
@@ -0,0 +1,36 @@
+
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+typedef char* __char_ptr32 __attribute__ (( mode (SI) ));
+typedef __char_ptr32 *__char_ptr_char_ptr32 __attribute__ ((mode (SI)));
+
+void to_ptr32 (int x)
+{
+  __char_ptr32 ptr = (__char_ptr32) x;
+}
+
+void to_int (__char_ptr32 ptr)
+{
+  int x = (int) ptr;
+}
+
+__char_ptr_char_ptr32
+to_ptr32_ptr32 (char **ptr64)
+{
+  int argc;
+  __char_ptr_char_ptr32 short_argv;
+
+  for (argc=0; ptr64[argc]; argc++);
+
+  short_argv = (__char_ptr_char_ptr32) malloc32
+    (sizeof (__char_ptr32) * (argc + 1));
+
+  for (argc=0; ptr64[argc]; argc++)
+    short_argv[argc] = (__char_ptr32) strdup32 (ptr64[argc]);
+
+  short_argv[argc] = (__char_ptr32) 0;
+  return short_argv;
+
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/pr55718.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr55718.c
new file mode 100644
index 000000000..a82d43522
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr55718.c
@@ -0,0 +1,29 @@
+/* PR target/55717  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=z10 -fPIC" } */
+
+extern char temp[];
+short ansi_value[256];
+void terminal_state(void)
+{
+  static const char *puc[] = { "", "<", "=", ">", "?", 0};
+  int i, j, k, l, modes_found;
+  char buf[256];
+  k = (int) __builtin_strlen(temp);
+  for (j = l = 0; j < 255 && j - l < 50; j++)
+    {
+      __builtin_sprintf(temp, "\033[%s%d$p", puc[i], j);
+      if (ansi_value[1])
+        {
+          l = j;
+          buf[k] = '\0';
+          put_crlf();
+          ptextln(buf);
+          buf[k++] = ' ';
+          k = (int) __builtin_strlen(temp);
+        }
+    }
+  for (i = j = 0; j < modes_found; j = ++i >> 1)
+    ;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/pr57559.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr57559.c
new file mode 100644
index 000000000..15c3878c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr57559.c
@@ -0,0 +1,24 @@
+/* PR rtl-optimization/57559  */
+
+/* { dg-do compile } */
+/* { dg-options "-march=z10 -m64 -mzarch  -O1" } */
+
+typedef int int32_t;
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+struct _IO_marker
+{
+};
+static const int32_t mfcone = 1;
+static const uint8_t *mfctop = (const uint8_t *) &mfcone;
+int32_t
+decContextTestEndian (uint8_t quiet)
+{
+  int32_t res = 0;
+  uint32_t dle = (uint32_t) 0;
+  if (*(int *) 10 != 0)
+    {
+      res = (int32_t) * mfctop - dle;
+    }
+  return res;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/pr57960.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr57960.c
new file mode 100644
index 000000000..ee751edc8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/pr57960.c
@@ -0,0 +1,30 @@
+/* PR rtl-optimization/57960  */
+
+/* { dg-do compile } */
+/* { dg-options "-march=z10 -m64 -mzarch  -O1" } */
+
+typedef union
+{
+  long double value;
+  struct
+  {
+    unsigned int w0, w1, w2, w3;
+  }
+    parts32;
+}
+  ieee854_long_double_shape_type;
+static const long double one = 1.0L;
+long double
+__ieee754_acosl (long double x)
+{
+  long double z, w;
+  int ix;
+  ieee854_long_double_shape_type u;
+
+  z = (one - u.value) * 0.5;
+  u.parts32.w2 = 0;
+  u.parts32.w3 = 0;
+  w = z - u.value * u.value;
+  return 2.0 * w;
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/return-addr1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/return-addr1.c
new file mode 100644
index 000000000..8872b89b7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/return-addr1.c
@@ -0,0 +1,46 @@
+/* builtin_return_address(n) with n>0 has always been troublesome ...
+   especially when the S/390 packed stack layout comes into play.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-optimize-sibling-calls -mbackchain -mpacked-stack -msoft-float" } */
+
+void *addr1;
+
+extern void abort (void);
+
+void * __attribute__((noinline))
+foo1 ()
+{
+  addr1 = __builtin_return_address (2);
+}
+
+void * __attribute__((noinline))
+foo2 ()
+{
+  foo1 ();
+}
+
+void * __attribute__((noinline))
+foo3 ()
+{
+  foo2 ();
+}
+
+void __attribute__((noinline))
+bar ()
+{
+  void *addr2;
+
+  foo3 ();
+  asm volatile ("basr  %0,0\n\t" : "=d" (addr2));
+  /* basr is two bytes in length.  */
+  if (addr2 - addr1 != 2)
+    abort ();
+}
+
+int
+main ()
+{
+  bar();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/return-addr2.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/return-addr2.c
new file mode 100644
index 000000000..c94d05284
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/return-addr2.c
@@ -0,0 +1,45 @@
+/* builtin_return_address(n) with n>0 has always been troublesome.  */
+
+/* { dg-do run } */
+/* { dg-options "-O3 -fno-optimize-sibling-calls -mbackchain" } */
+
+void *addr1;
+
+extern void abort (void);
+
+void * __attribute__((noinline))
+foo1 ()
+{
+  addr1 = __builtin_return_address (2);
+}
+
+void * __attribute__((noinline))
+foo2 ()
+{
+  foo1 ();
+}
+
+void * __attribute__((noinline))
+foo3 ()
+{
+  foo2 ();
+}
+
+void __attribute__((noinline))
+bar ()
+{
+  void *addr2;
+
+  foo3 ();
+  asm volatile ("basr  %0,0\n\t" : "=d" (addr2));
+  /* basr is two bytes in length.  */
+  if (addr2 - addr1 != 2)
+    abort ();
+}
+
+int
+main ()
+{
+  bar();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/s390.exp b/gcc-4.9/gcc/testsuite/gcc.target/s390/s390.exp
new file mode 100644
index 000000000..1b6d94a23
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/s390.exp
@@ -0,0 +1,54 @@
+# Copyright (C) 2007-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a s390 target.
+if ![istarget s390*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Return 1 if htm (etnd - extract nesting depth) instructions can be
+# compiled.
+proc check_effective_target_htm { } {
+    if { ![check_runtime s390_check_htm [subst {
+	int main (void)
+	{
+	    unsigned int nd = 77;
+	    asm (".insn rre,0xb2ec0000,%0,0" : "=d" (nd));
+	    return nd;
+	}
+    }]] } { return 0 } else { return 1 }
+}
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/stackcheck1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/stackcheck1.c
new file mode 100644
index 000000000..ab46a92d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/stackcheck1.c
@@ -0,0 +1,14 @@
+/* The automatically chosen stack guard value caused an ICE in that
+   case.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mstack-size=4096" } */
+
+extern void bar (char *);
+
+void
+foo ()
+{
+  char a[2500];
+  bar (a);
+}	/* { dg-warning "more than half" } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/s390/tf_to_di-1.c b/gcc-4.9/gcc/testsuite/gcc.target/s390/tf_to_di-1.c
new file mode 100644
index 000000000..d79e6f350
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/s390/tf_to_di-1.c
@@ -0,0 +1,46 @@
+/* { dg-options "-O0 -mlong-double-128" } */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+void
+check_ll (long double ld, long long ll)
+{
+  if ((long long)ld != ll)
+    {
+      printf ("ld: %Lf expect: %lld result: %lld\n",
+	      ld, ll, (long long)ld);
+      abort ();
+    }
+}
+
+void
+check_ull (long double ld, unsigned long long ull)
+{
+  if ((unsigned long long)ld != ull)
+    {
+      printf ("ld: %Lf expect: %llu result: %llu\n",
+	      ld, ull, (unsigned long long)ld);
+      abort ();
+    }
+}
+
+int
+main ()
+{
+  const long long ll_max = (long long)((1ULL << 63) - 1);
+  const long long ll_min = -ll_max - 1;
+
+  check_ll (206.23253, 206LL);
+  check_ull (206.23253, 206ULL);
+  check_ll ((long double)ll_max, ll_max);
+  check_ull ((long double)ll_max, ll_max);
+  check_ll ((long double)ll_min, ll_min);
+  check_ll (0.0, 0);
+  check_ull (0.0, 0);
+  check_ll (-1.0, -1);
+  check_ll ((long double)0xffffffffffffffffULL, ll_max);
+  check_ull ((long double)0xffffffffffffffffULL, 0xffffffffffffffffULL);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/20080410-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/20080410-1.c
new file mode 100644
index 000000000..c398674c2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/20080410-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile }  */
+/* { dg-options "-O0" } */
+/* { dg-skip-if "" { "sh*-*-*" } "-mb" "" }  */
+/* { dg-final { scan-assembler-not "add\tr0,r0" } } */
+
+/* This test checks chain reloads conflicts.  If they don't
+   conflict, the same hard register R0 is used for the both reloads
+   but in this case the second reload needs an intermediate register
+   (which is the reload register).  As the result we have the
+   following code
+
+   	mov	#4,r0   -- first reload
+	mov	r14,r0  -- second reload
+	add	r0,r0   -- second reload
+
+   The right code should be
+
+   	mov	#4,r0   -- first reload
+	mov	r14,r1  -- second reload
+	add	r0,r1   -- second reload
+
+*/
+
+_Complex float foo_float ();
+
+void bar_float ()
+{
+  __real foo_float ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c
new file mode 100644
index 000000000..2f1d51801
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c
@@ -0,0 +1,32 @@
+/* A call will clobber all call-saved registers.
+   If #pragma nosave_low_regs is specified, do not save/restore r0..r7.
+   (On SH3* and SH4* r0..r7 are banked)
+   One of these registers will also do fine to hold the function address.
+   Call-saved registers r8..r13 also don't need to be restored.  */
+/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1*" "-m2*" "-m5*" } { "" } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler-times "rte" 1 } }  */
+/* { dg-final { scan-assembler-not "\[^f\]r\[0-9\]\[ \t\]*," } }  */
+/* { dg-final { scan-assembler-not "\[^f\]r\[89\]" } }  */
+/* { dg-final { scan-assembler-not "\[^f\]r1\[,0-3\]" } }  */
+/* { dg-final { scan-assembler-times "macl" 2 } }  */
+
+extern void bar (void);
+
+void
+foo (void)
+{
+}
+
+#pragma interrupt
+void
+( __attribute__ ((nosave_low_regs)) isr) (void)
+{
+  bar ();
+}
+
+void
+delay (int a)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c
new file mode 100644
index 000000000..a45e92f8c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-trap_exit.c
@@ -0,0 +1,31 @@
+/* Check that trapa / interrput_handler attributes can paired in
+   either order.  */
+/* { dg-do compile }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler "trapa\[ \t\]\[ \t\]*#4"} }  */
+/* { dg-final { scan-assembler-times "trapa" 1 } }  */
+
+void h0 (void) __attribute__ ((trap_exit (4))) __attribute__ ((interrupt_handler));
+void h1 (void) __attribute__ ((interrupt_handler)) __attribute__ ((trap_exit (5)));
+
+void
+foo (void)
+{
+}
+
+void
+h0 (void)
+{
+}
+
+void delay
+(int a)
+{
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-trapa.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-trapa.c
new file mode 100644
index 000000000..e1bc8a4af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/attr-isr-trapa.c
@@ -0,0 +1,18 @@
+/* Check that no interrupt-specific register saves are generated.  */
+/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler-times "rte" 1 } }  */
+/* { dg-final { scan-assembler-not "r\[0-7\]\[ \t,\]\[^\n\]*r15" } }  */
+/* { dg-final { scan-assembler-not "@r15\[^\n\]*r\[0-7\]\n" } }  */
+/* { dg-final { scan-assembler-not "r\[8-9\]" } }  */
+/* { dg-final { scan-assembler-not "r1\[,0-3\]" } }  */
+/* { dg-final { scan-assembler-not "macl" } }  */
+
+extern void foo (void);
+
+void
+(__attribute__ ((trapa_handler)) isr) (void)
+{
+  foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/cmpstr.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/cmpstr.c
new file mode 100644
index 000000000..4d638cc3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/cmpstr.c
@@ -0,0 +1,27 @@
+/* Check that the __builtin_strcmp function is inlined with cmp/str
+   when optimizing for speed.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "jmp" } } */
+/* { dg-final { scan-assembler-times "cmp/str" 3 } } */
+/* { dg-final { scan-assembler-times "tst\t#3" 2 } } */
+
+test00 (const char *s1, const char *s2)
+{
+  return __builtin_strcmp (s1, s2);
+}
+
+/* NB: This might change as further optimisation might detect the
+   max length and fallback to cmpstrn.  */
+test01(const char *s2)
+{
+  return __builtin_strcmp ("abc", s2);
+}
+
+/* Check that no test for alignment is needed.  */
+test03(const char *s1, const char *s2)
+{
+  return __builtin_strcmp (__builtin_assume_aligned (s1, 4),
+			   __builtin_assume_aligned (s2, 4));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/cmpstrn.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/cmpstrn.c
new file mode 100644
index 000000000..3a1d0d151
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/cmpstrn.c
@@ -0,0 +1,28 @@
+/* Check that the __builtin_strncmp function is inlined
+   when optimizing for speed.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "jmp" } } */
+/* { dg-final { scan-assembler-times "cmp/str" 1 } } */
+
+/* Test that cmp/str is not used for small lengths.  */
+test01(const char *s1)
+{
+  return __builtin_strncmp (s1, "abcde", 3);
+}
+
+/* Test that the cmp/str loop is used.  */
+test02(const char *s1)
+{
+  return __builtin_strncmp (s1, "abcdefghi", 8);
+}
+
+/* Test that no call is generated  */
+test03(const char *s1, int n)
+{
+  return __builtin_strncmp (s1, "abcde", n);
+}
+
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/fpul-usage-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/fpul-usage-1.c
new file mode 100644
index 000000000..5c3bb196d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/fpul-usage-1.c
@@ -0,0 +1,24 @@
+/* Check that the FPUL register is used when reading a float as an int and
+   vice versa, as opposed to pushing and popping the values over the stack.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler "fpul" } } */
+/* { dg-final { scan-assembler-not "r15" } } */
+
+int
+float_as_int (float val)
+{
+  union { float f; int i; } u;
+  u.f = val;
+  return u.i;
+}
+
+float
+int_as_float (int val)
+{
+  union { float f; int i; } u;
+  u.i = val;
+  return u.f;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/mfmovd.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/mfmovd.c
new file mode 100644
index 000000000..ce3e99332
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/mfmovd.c
@@ -0,0 +1,22 @@
+/* Verify that we generate fmov.d instructions to move doubles when -mfmovd 
+   option is enabled.  */
+/* { dg-do compile }  */
+/* { dg-require-effective-target hard_float } */
+/* { dg-options "-mfmovd" } */
+/* { dg-skip-if "" { *-*-* }  { "*-single-only" } { "" } } */
+/* { dg-final { scan-assembler "fmov.d" } } */
+
+extern double g;
+
+void
+f (double d)
+{
+  g = d;
+}
+
+extern float h;
+
+void f2 ()
+{
+  h = g;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-1.c
new file mode 100644
index 000000000..3e9b78515
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile }  */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+/* { dg-final { scan-assembler "mov fr4,fr.; mov fr5,fr." { target sh-*-* } } } */
+/* { dg-final { scan-assembler "mov fr4,fr.; mov fr5,fr." { target sh[1234lb]*-*-* } } } */
+/* { dg-final { scan-assembler "mov fr0,fr.; mov fr1,fr." { target sh[56]*-*-* } } } */
+double
+f (double d)
+{
+  double r;
+
+#if defined (__SH_FPU_DOUBLE__)
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=f" (r) : "f" (d));
+#else
+  asm ("mov fr4,fr4; mov fr5,fr5");
+#endif
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c
new file mode 100644
index 000000000..531ed3979
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-2-mb.c
@@ -0,0 +1,19 @@
+/* { dg-do compile }  */
+/* { dg-options "-mb -O2 -fomit-frame-pointer" } */
+/* { dg-final { scan-assembler "mov @r.,r.; mov @\\(4,r.\\),r." } } */
+double d;
+
+double
+f (void)
+{
+  double r;
+
+/* If -ml from the target options is passed after -mb from dg-options, we
+   end up with th reverse endianness.  */
+#if TARGET_SHMEDIA || defined (__LITTLE_ENDIAN__)
+  asm ("mov @r1,r3; mov @(4,r1),r4");
+#else
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=&r" (r) : "m" (d));
+#endif
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c
new file mode 100644
index 000000000..6948f475e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-2-ml.c
@@ -0,0 +1,13 @@
+/* { dg-do compile }  */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-mb" && "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler "mov @\\(4,r.\\),r.; mov @r.,r." } } */
+double d;
+
+double
+f (void)
+{
+  double r;
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=&r" (r) : "m" (d));
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-3.c
new file mode 100644
index 000000000..a67278418
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile }  */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m2e" "-m3e" "*single-only" } { "" } }  */
+/* { dg-final { scan-assembler "mov #?0,r.*; mov #?20,r" } } */
+/* { dg-final { scan-assembler "mov #?1077149696,r.*; mov #?0,r" } } */
+double
+f ()
+{
+  double r;
+
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=r" (r) : "i" (20));
+  asm ("mov %S1,%S0; mov %R1,%R0" : "+r" (r) : "i" (20.));
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-4.c
new file mode 100644
index 000000000..c848c26c0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr21255-4.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { sh*-*-* && nonpic } } } */
+/* { dg-options "-O2 -fomit-frame-pointer" } */
+
+double
+f ()
+{
+  double r;
+
+  asm ("mov %S1,%S0; mov %R1,%R0" : "=r" (r) : "i" (f));
+/* { dg-error "invalid operand to %S" "" {target "sh*-*-*" }  9 } */
+/* { dg-error "invalid operand to %R" "" {target "sh*-*-*" }  9 } */
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-1.c
new file mode 100644
index 000000000..cc6a3f984
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-1.c
@@ -0,0 +1,32 @@
+/* Check that fcmp/eq and fcmp/gt instructions are generated by default
+   (implicit -mieee).  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fcmp/eq" 4 } } */
+/* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */
+
+int
+test_00 (float a, float b)
+{
+  return a <= b;
+}
+
+int
+test_01 (float a, float b)
+{
+  return a >= b;
+}
+
+int
+test_02 (double a, double b)
+{
+  return a <= b;
+}
+
+int
+test_03 (double a, double b)
+{
+  return a >= b;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-2.c
new file mode 100644
index 000000000..b93ecb81e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-2.c
@@ -0,0 +1,32 @@
+/* Check that only the fcmp/gt instruction is generated when specifying
+   -ffinite-math-only (implicit -mno-ieee).  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -ffinite-math-only" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-not "fcmp/eq" } } */
+/* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */
+
+int
+test_00 (float a, float b)
+{
+  return a <= b;
+}
+
+int
+test_01 (float a, float b)
+{
+  return a >= b;
+}
+
+int
+test_02 (double a, double b)
+{
+  return a <= b;
+}
+
+int
+test_03 (double a, double b)
+{
+  return a >= b;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-3.c
new file mode 100644
index 000000000..f5f9a5b92
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-3.c
@@ -0,0 +1,32 @@
+/* Check that fcmp/eq and fcmp/gt instructions are generated when specifying
+   -ffinite-math-only and -mieee.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -ffinite-math-only -mieee" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fcmp/eq" 4 } } */
+/* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */
+
+int
+test_00 (float a, float b)
+{
+  return a <= b;
+}
+
+int
+test_01 (float a, float b)
+{
+  return a >= b;
+}
+
+int
+test_02 (double a, double b)
+{
+  return a <= b;
+}
+
+int
+test_03 (double a, double b)
+{
+  return a >= b;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-4.c
new file mode 100644
index 000000000..20178d7e4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr33135-4.c
@@ -0,0 +1,32 @@
+/* Check that only the fcmp/gt instruction is generated when specifying
+   -fno-finite-math-only and -mno-ieee.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -fno-finite-math-only -mno-ieee" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-not "fcmp/eq" } } */
+/* { dg-final { scan-assembler-times "fcmp/gt" 4 } } */
+
+int
+test_00 (float a, float b)
+{
+  return a <= b;
+}
+
+int
+test_01 (float a, float b)
+{
+  return a >= b;
+}
+
+int
+test_02 (double a, double b)
+{
+  return a <= b;
+}
+
+int
+test_03 (double a, double b)
+{
+  return a >= b;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr39423-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr39423-1.c
new file mode 100644
index 000000000..1e02937cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr39423-1.c
@@ -0,0 +1,48 @@
+/* Check that displacement addressing is used for indexed addresses with a
+   small offset, instead of re-calculating the index.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-not "add\t#1" } } */
+
+int
+test_00 (int tab[], int index)
+{
+  return tab[index + 1];
+}
+
+int
+test_01 (short tab[], int index)
+{
+  return tab[index + 1];
+}
+
+int
+test_02 (unsigned short tab[], int index)
+{
+  return tab[index + 1];
+}
+
+int
+test_03 (long long tab[], int index)
+{
+  return (int)tab[index + 1];
+}
+
+void
+test_04 (int tab[], int index, int val)
+{
+  tab[index + 1] = val;
+}
+
+void
+test_05 (short tab[], int index, int val)
+{
+  tab[index + 1] = (short)val;
+}
+
+void
+test_06 (unsigned short tab[], int index, int val)
+{
+  tab[index + 1] = (unsigned short)val;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr39423-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr39423-2.c
new file mode 100644
index 000000000..702384dc2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr39423-2.c
@@ -0,0 +1,14 @@
+/* Check that displacement addressing is used for indexed addresses with a
+   small offset, instead of re-calculating the index and that the movu.w
+   instruction is used on SH2A.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-not "add\t#1" } } */
+/* { dg-final { scan-assembler "movu.w" } } */
+
+int
+test_00 (unsigned short tab[], int index)
+{
+  return tab[index + 1];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr43417.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr43417.c
new file mode 100644
index 000000000..081ff46b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr43417.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -m4" } */
+
+int pid_count = 0;
+main (int argc, char *argv[])
+{
+  unsigned int c;
+  unsigned long long maxbytes = 0;
+  extern char *optarg;
+  int i;
+  int pid_cntr;
+  int pid;
+  int pid_list[1000];
+  while ((c = getopt (argc, argv, "c:b:p:wvh")) != (-1))
+    {
+      switch ((char) c)
+	{
+	case 'b':
+	  maxbytes = atoll (optarg);
+	}
+    }
+  pid = fork ();
+  while ((pid != 0) && (maxbytes > 1024 * 1024 * 1024))
+    {
+      maxbytes = maxbytes - (1024 * 1024 * 1024);
+      pid = fork ();
+      if (pid != 0)
+	pid_cntr++;
+      pid_list[i] = pid;
+    }
+  while ((pid_count < pid_cntr))
+    {
+    }
+  kill (pid_list[i], 9);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49263.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49263.c
new file mode 100644
index 000000000..783d86559
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49263.c
@@ -0,0 +1,86 @@
+/* Verify that TST #imm, R0 instruction is generated if the constant
+   allows it.  Under some circumstances another compare instruction might
+   be selected, which is also fine.  Any AND instructions are considered
+   counter productive and fail the test.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+#define make_func(__valtype__, __valget__, __tstval__, __suff__)\
+  int test_imm_##__tstval__##__suff__ (__valtype__ val) \
+    {\
+      return ((__valget__) & (0x##__tstval__  << 0)) ? -20 : -40;\
+    }
+
+#define make_func_0_F(__valtype__, __valget__, __y__, __suff__)\
+  make_func (__valtype__, __valget__, __y__##0, __suff__)\
+  make_func (__valtype__, __valget__, __y__##1, __suff__)\
+  make_func (__valtype__, __valget__, __y__##2, __suff__)\
+  make_func (__valtype__, __valget__, __y__##3, __suff__)\
+  make_func (__valtype__, __valget__, __y__##4, __suff__)\
+  make_func (__valtype__, __valget__, __y__##5, __suff__)\
+  make_func (__valtype__, __valget__, __y__##6, __suff__)\
+  make_func (__valtype__, __valget__, __y__##7, __suff__)\
+  make_func (__valtype__, __valget__, __y__##8, __suff__)\
+  make_func (__valtype__, __valget__, __y__##9, __suff__)\
+  make_func (__valtype__, __valget__, __y__##A, __suff__)\
+  make_func (__valtype__, __valget__, __y__##B, __suff__)\
+  make_func (__valtype__, __valget__, __y__##C, __suff__)\
+  make_func (__valtype__, __valget__, __y__##D, __suff__)\
+  make_func (__valtype__, __valget__, __y__##E, __suff__)\
+  make_func (__valtype__, __valget__, __y__##F, __suff__)\
+
+#define make_funcs_0_FF(__valtype__, __valget__, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 0, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 1, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 2, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 3, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 4, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 5, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 6, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 7, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 8, __suff__)\
+  make_func_0_F (__valtype__, __valget__, 9, __suff__)\
+  make_func_0_F (__valtype__, __valget__, A, __suff__)\
+  make_func_0_F (__valtype__, __valget__, B, __suff__)\
+  make_func_0_F (__valtype__, __valget__, C, __suff__)\
+  make_func_0_F (__valtype__, __valget__, D, __suff__)\
+  make_func_0_F (__valtype__, __valget__, E, __suff__)\
+  make_func_0_F (__valtype__, __valget__, F, __suff__)\
+
+make_funcs_0_FF (signed char*, *val, int8_mem)
+make_funcs_0_FF (signed char, val, int8_reg)
+
+make_funcs_0_FF (unsigned char*, *val, uint8_mem)
+make_funcs_0_FF (unsigned char, val, uint8_reg)
+
+make_funcs_0_FF (short*, *val, int16_mem)
+make_funcs_0_FF (short, val, int16_reg)
+
+make_funcs_0_FF (unsigned short*, *val, uint16_mem)
+make_funcs_0_FF (unsigned short, val, uint16_reg)
+
+make_funcs_0_FF (int*, *val, int32_mem)
+make_funcs_0_FF (int, val, int32_reg)
+
+make_funcs_0_FF (unsigned int*, *val, uint32_mem)
+make_funcs_0_FF (unsigned int, val, uint32_reg)
+
+make_funcs_0_FF (long long*, *val, int64_lowword_mem)
+make_funcs_0_FF (long long, val, int64_lowword_reg)
+
+make_funcs_0_FF (unsigned long long*, *val, uint64_lowword_mem)
+make_funcs_0_FF (unsigned long long, val, uint64_lowword_reg)
+
+make_funcs_0_FF (long long*, *val >> 32, int64_highword_mem)
+make_funcs_0_FF (long long, val >> 32, int64_highword_reg)
+
+make_funcs_0_FF (unsigned long long*, *val >> 32, uint64_highword_mem)
+make_funcs_0_FF (unsigned long long, val >> 32, uint64_highword_reg)
+
+make_funcs_0_FF (long long*, *val >> 16, int64_midword_mem)
+make_funcs_0_FF (long long, val >> 16, int64_midword_reg)
+
+make_funcs_0_FF (unsigned long long*, *val >> 16, uint64_midword_mem)
+make_funcs_0_FF (unsigned long long, val >> 16, uint64_midword_reg)
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49468-di.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49468-di.c
new file mode 100644
index 000000000..4b17fce30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49468-di.c
@@ -0,0 +1,23 @@
+/* Check that 64 bit integer abs is generated as negc instruction pairs
+   and conditional branch instead of default branch-free code.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "negc" 4 } } */
+
+
+/* Normal integer absolute value.  */
+long long
+abs_0 (long long i)
+{
+  return (i < 0) ? -i : i;
+}
+
+/*  Negated integer absolute value.
+    The generated code should be the same, except that the branch 
+    condition is inverted.  */
+long long
+abs_1 (long long i)
+{
+  return (i > 0) ? -i : i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49468-si.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49468-si.c
new file mode 100644
index 000000000..8c771ed20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49468-si.c
@@ -0,0 +1,23 @@
+/* Check that 32 bit integer abs is generated as neg instruction and
+   conditional branch instead of default branch-free code.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "neg" 2 } } */
+
+
+/* Normal integer absolute value.  */
+int
+abs_0 (int i)
+{
+  return (i < 0) ? -i : i;
+}
+
+/*  Negated integer absolute value.
+    The generated code should be the same, except that the branch 
+    condition is inverted.  */
+int
+abs_1 (int i)
+{
+  return (i > 0) ? -i : i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-1.c
new file mode 100644
index 000000000..249fae002
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-1.c
@@ -0,0 +1,22 @@
+/* Check that the option -mdiv=call-div1 works.  */
+/* { dg-do link }  */
+/* { dg-options "-mdiv=call-div1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+
+int
+test00 (int a, int b)
+{
+  return a / b;
+}
+
+unsigned int
+test01 (unsigned int a, unsigned b)
+{
+  return a / b;
+}
+
+int
+main (int argc, char** argv)
+{
+  return test00 (argc, 123) + test01 (argc, 123);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-2.c
new file mode 100644
index 000000000..35e23dec4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-2.c
@@ -0,0 +1,22 @@
+/* Check that the option -mdiv=call-fp works.  */
+/* { dg-do link }  */
+/* { dg-options "-mdiv=call-fp" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+
+int
+test00 (int a, int b)
+{
+  return a / b;
+}
+
+unsigned int
+test01 (unsigned int a, unsigned b)
+{
+  return a / b;
+}
+
+int
+main (int argc, char** argv)
+{
+  return test00 (argc, 123) + test01 (argc, 123);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-3.c
new file mode 100644
index 000000000..be6ea523c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-3.c
@@ -0,0 +1,22 @@
+/* Check that the option -mdiv=call-table works.  */
+/* { dg-do link }  */
+/* { dg-options "-mdiv=call-table" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+
+int
+test00 (int a, int b)
+{
+  return a / b;
+}
+
+unsigned int
+test01 (unsigned int a, unsigned b)
+{
+  return a / b;
+}
+
+int
+main (int argc, char** argv)
+{
+  return test00 (argc, 123) + test01 (argc, 123);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-4.c
new file mode 100644
index 000000000..5b5af1e40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-4.c
@@ -0,0 +1,19 @@
+/* Check that the option -mdiv=call-fp does not produce calls to the
+   library function that uses FPU to implement integer division if FPU insns
+   are not supported or are disabled.  */
+/* { dg-do compile }  */
+/* { dg-options "-mdiv=call-fp" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" } }  */
+/* { dg-final { scan-assembler-not "sdivsi3_i4\n|udivsi3_i4\n" } }  */
+
+int
+test00 (int a, int b)
+{
+  return a / b;
+}
+
+unsigned int
+test01 (unsigned int a, unsigned b)
+{
+  return a / b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-5.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-5.c
new file mode 100644
index 000000000..bff9f331f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr49880-5.c
@@ -0,0 +1,19 @@
+/* Check that the option -mdiv=call-fp results in the corresponding library
+   function calls on targets that have a double precision FPU.  */
+/* { dg-do compile }  */
+/* { dg-options "-mdiv=call-fp" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m2a" "-m4" "-m4a" "*single-only" } }  */
+/* { dg-final { scan-assembler "sdivsi3_i4\n" } }  */
+/* { dg-final { scan-assembler "udivsi3_i4\n" } }  */
+
+int
+test00 (int a, int b)
+{
+  return a / b;
+}
+
+unsigned int
+test01 (unsigned int a, unsigned b)
+{
+  return a / b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-1.c
new file mode 100644
index 000000000..90db97a27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-1.c
@@ -0,0 +1,34 @@
+/* PR target/50749: Verify that post-increment addressing is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "mov.b\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
+/* { dg-final { scan-assembler-times "mov.w\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
+/* { dg-final { scan-assembler-times "mov.l\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
+
+char*
+test_func_00 (char* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
+short*
+test_func_01 (short* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
+int*
+test_func_02 (int* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-2.c
new file mode 100644
index 000000000..b695db173
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-2.c
@@ -0,0 +1,70 @@
+/* PR target/50749: Verify that subsequent post-increment addressings
+   are generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "mov.b\t@r\[0-9]\+\\+,r\[0-9]\+" 5 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.w\t@r\[0-9]\+\\+,r\[0-9]\+" 5 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.l\t@r\[0-9]\+\\+,r\[0-9]\+" 5 { xfail *-*-*} } } */
+
+char*
+test_func_00 (char* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
+char*
+test_func_01 (char* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  r += *p++;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
+short*
+test_func_02 (short* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
+short*
+test_func_03 (short* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  r += *p++;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
+int*
+test_func_04 (int* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
+int*
+test_func_05 (int* p, int* x)
+{
+  int r = 0;
+  r += *p++;
+  r += *p++;
+  r += *p++;
+  *x = r;
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-3.c
new file mode 100644
index 000000000..6e54d4dd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-3.c
@@ -0,0 +1,40 @@
+/* PR target/50749: Verify that post-increment addressing is generated
+   inside a loop.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "mov.b\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
+/* { dg-final { scan-assembler-times "mov.w\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
+/* { dg-final { scan-assembler-times "mov.l\t@r\[0-9]\+\\+,r\[0-9]\+" 1 } } */
+
+int
+test_func_00 (char* p, int c)
+{
+  int r = 0;
+  do
+  {
+    r += *p++;
+  } while (--c);
+  return r;
+}
+
+int
+test_func_01 (short* p, int c)
+{
+  int r = 0;
+  do
+  {
+    r += *p++;
+  } while (--c);
+  return r;
+}
+
+int
+test_func_02 (int* p, int c)
+{
+  int r = 0;
+  do
+  {
+    r += *p++;
+  } while (--c);
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-4.c
new file mode 100644
index 000000000..fc6fa8da0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-postinc-4.c
@@ -0,0 +1,46 @@
+/* PR target/50749: Verify that post-increment addressing is generated
+   inside a loop.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "mov.b\t@r\[0-9]\+\\+,r\[0-9]\+" 3 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.w\t@r\[0-9]\+\\+,r\[0-9]\+" 3 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.l\t@r\[0-9]\+\\+,r\[0-9]\+" 3 { xfail *-*-*} } } */
+
+int
+test_func_00 (char* p, int c)
+{
+  int r = 0;
+  do
+  {
+    r += *p++;
+    r += *p++;
+    r += *p++;
+  } while (--c);
+  return r;
+}
+
+int
+test_func_01 (short* p, int c)
+{
+  int r = 0;
+  do
+  {
+    r += *p++;
+    r += *p++;
+    r += *p++;
+  } while (--c);
+  return r;
+}
+
+int
+test_func_02 (int* p, int c)
+{
+  int r = 0;
+  do
+  {
+    r += *p++;
+    r += *p++;
+    r += *p++;
+  } while (--c);
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-1.c
new file mode 100644
index 000000000..4f455743c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-1.c
@@ -0,0 +1,28 @@
+/* PR target/50749: Verify that pre-decrement addressing is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "mov.b\tr\[0-9]\+,@-r\[0-9]\+" 1 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.w\tr\[0-9]\+,@-r\[0-9]\+" 1 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.l\tr\[0-9]\+,@-r\[0-9]\+" 1 { xfail *-*-*} } } */
+
+char*
+test_func_00 (char* p, int c)
+{
+  *--p = (char)c;
+  return p;
+}
+
+short*
+test_func_01 (short* p, int c)
+{
+  *--p = (short)c;
+  return p;
+}
+
+int*
+test_func_02 (int* p, int c)
+{
+  *--p = c;
+  return p;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-2.c
new file mode 100644
index 000000000..beda957fa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-2.c
@@ -0,0 +1,58 @@
+/* PR target/50749: Verify that subsequent pre-decrement addressings
+   are generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "mov.b\tr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.w\tr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.l\tr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */
+
+char*
+test_func_00 (char* p, int c)
+{
+  *--p = (char)c;
+  *--p = (char)c;
+  return p;
+}
+
+char*
+test_func_01 (char* p, int c)
+{
+  *--p = (char)c;
+  *--p = (char)c;
+  *--p = (char)c;
+  return p;
+}
+
+short*
+test_func_02 (short* p, int c)
+{
+  *--p = (short)c;
+  *--p = (short)c;
+  return p;
+}
+
+short*
+test_func_03 (short* p, int c)
+{
+  *--p = (short)c;
+  *--p = (short)c;
+  *--p = (short)c;
+  return p;
+}
+
+int*
+test_func_04 (int* p, int c)
+{
+  *--p = c;
+  *--p = c;
+  return p;
+}
+
+int*
+test_func_05 (int* p, int c)
+{
+  *--p = c;
+  *--p = c;
+  *--p = c;
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-3.c
new file mode 100644
index 000000000..541749750
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-3.c
@@ -0,0 +1,37 @@
+/* PR target/50749: Verify that pre-decrement addressing is generated
+   inside a loop.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "mov.b\tr\[0-9]\+,@-r\[0-9]\+" 1 } } */
+/* { dg-final { scan-assembler-times "mov.w\tr\[0-9]\+,@-r\[0-9]\+" 1 } } */
+/* { dg-final { scan-assembler-times "mov.l\tr\[0-9]\+,@-r\[0-9]\+" 1 } } */
+
+char*
+test_func_00 (char* p, int c, int x)
+{
+  do
+  {
+    *--p = (char)x;
+  } while (--c);
+  return p;
+}
+
+short*
+test_func_01 (short* p, int c, int x)
+{
+  do
+  {
+    *--p = (short)x;
+  } while (--c);
+  return p;
+}
+
+int*
+test_func_02 (int* p, int c, int x)
+{
+  do
+  {
+    *--p = x;
+  } while (--c);
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-4.c
new file mode 100644
index 000000000..e8c03481e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-qihisi-predec-4.c
@@ -0,0 +1,43 @@
+/* PR target/50749: Verify that pre-decrement addressing is generated
+   inside a loop.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "mov.b\tr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.w\tr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */
+/* { dg-final { scan-assembler-times "mov.l\tr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */
+
+char*
+test_func_00 (char* p, int c, int x)
+{
+  do
+  {
+    *--p = (char)x;
+    *--p = (char)x;
+    *--p = (char)x;
+  } while (--c);
+  return p;
+}
+
+short*
+test_func_01 (short* p, int c, int x)
+{
+  do
+  {
+    *--p = (short)x;
+    *--p = (short)x;
+    *--p = (short)x;
+  } while (--c);
+  return p;
+}
+
+int*
+test_func_02 (int* p, int c, int x)
+{
+  do
+  {
+    *--p = x;
+    *--p = x;
+    *--p = x;
+  } while (--c);
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c
new file mode 100644
index 000000000..41e3bdd28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-1.c
@@ -0,0 +1,15 @@
+/* PR target/50749: Verify that post-increment addressing is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 1 } } */
+
+float*
+test_func_00 (float* p, float* x)
+{
+  float r = 0;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c
new file mode 100644
index 000000000..304ed11c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-2.c
@@ -0,0 +1,27 @@
+/* PR target/50749: Verify that subsequent post-increment addressings
+   are generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 5 { xfail *-*-*} } } */
+
+float*
+test_func_00 (float* p, float* x)
+{
+  float r = 0;
+  r += *p++;
+  r += *p++;
+  *x = r;
+  return p;
+}
+
+float*
+test_func_01 (float* p, float* x)
+{
+  float r = 0;
+  r += *p++;
+  r += *p++;
+  r += *p++;
+  *x = r;
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c
new file mode 100644
index 000000000..7461bedb4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-3.c
@@ -0,0 +1,17 @@
+/* PR target/50749: Verify that post-increment addressing is generated
+   inside a loop.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 1 } } */
+
+float
+test_func_00 (float* p, int c)
+{
+  float r = 0;
+  do
+  {
+    r += *p++;
+  } while (--c);
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c
new file mode 100644
index 000000000..b6dce42fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-postinc-4.c
@@ -0,0 +1,19 @@
+/* PR target/50749: Verify that post-increment addressing is generated
+   inside a loop.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmov.s\t@r\[0-9]\+\\+,fr\[0-9]\+" 3 { xfail *-*-*} } } */
+
+float
+test_func_00 (float* p, int c)
+{
+  float r = 0;
+  do
+  {
+    r += *p++;
+    r += *p++;
+    r += *p++;
+  } while (--c);
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c
new file mode 100644
index 000000000..d51aa9e09
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-1.c
@@ -0,0 +1,13 @@
+/* PR target/50749: Verify that pre-decrement addressing is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 1 } } */
+
+float*
+test_func_00 (float* p, float c)
+{
+  *--p = c;
+  return p;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c
new file mode 100644
index 000000000..cd87ce95f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-2.c
@@ -0,0 +1,23 @@
+/* PR target/50749: Verify that subsequent pre-decrement addressings
+   are generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 5 { xfail *-*-*} } } */
+
+float*
+test_func_00 (float* p, float c)
+{
+  *--p = c;
+  *--p = c;
+  return p;
+}
+
+float*
+test_func_01 (float* p, float c)
+{
+  *--p = c;
+  *--p = c;
+  *--p = c;
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c
new file mode 100644
index 000000000..a772b23a4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-3.c
@@ -0,0 +1,16 @@
+/* PR target/50749: Verify that pre-decrement addressing is generated
+   inside a loop.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 1 } } */
+
+float*
+test_func_00 (float* p, int c, float x)
+{
+  do
+  {
+    *--p = x;
+  } while (--c);
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c
new file mode 100644
index 000000000..9d080387d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50749-sf-predec-4.c
@@ -0,0 +1,18 @@
+/* PR target/50749: Verify that pre-decrement addressing is generated
+   inside a loop.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmov.s\tfr\[0-9]\+,@-r\[0-9]\+" 3 { xfail *-*-*} } } */
+
+float*
+test_func_00 (float* p, int c, float x)
+{
+  do
+  {
+    *--p = x;
+    *--p = x;
+    *--p = x;
+  } while (--c);
+  return p;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-1.c
new file mode 100644
index 000000000..80c63fb36
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-1.c
@@ -0,0 +1,30 @@
+/* Check that the mov.b displacement addressing insn is generated.
+   If the insn is generated as expected, there should be no address 
+   calculations outside the mov insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-not "add|sub" } } */
+
+void
+testfunc_00 (const char* ap, char* bp, char val)
+{
+  bp[0] = ap[15];
+  bp[2] = ap[5];
+  bp[9] = ap[7];
+  bp[0] = ap[15];
+  bp[4] = val;
+  bp[14] = val;
+}
+
+void
+testfunc_01 (volatile const char* ap, volatile char* bp, char val)
+{
+  bp[0] = ap[15];
+  bp[2] = ap[5];
+  bp[9] = ap[7];
+  bp[0] = ap[15];
+  bp[4] = val;
+  bp[14] = val;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-2.c
new file mode 100644
index 000000000..cd7164261
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-2.c
@@ -0,0 +1,27 @@
+/* Check that the mov.b displacement addressing insn is generated and the 
+   base address is adjusted only once.  On SH2A this test is skipped because
+   there is a 4 byte mov.b insn that can handle larger displacements.  Thus
+   on SH2A the base address will not be adjusted in this case.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
+/* { dg-final { scan-assembler-times "add" 2 } } */
+
+void
+testfunc_00 (const char* ap, char* bp)
+{
+  bp[0] = ap[15];
+  bp[2] = ap[5];
+  bp[9] = ap[7];
+  bp[0] = ap[25];
+}
+
+void
+testfunc_01 (volatile const char* ap, volatile char* bp)
+{
+  bp[0] = ap[15];
+  bp[2] = ap[5];
+  bp[9] = ap[7];
+  bp[0] = ap[25];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-3.c
new file mode 100644
index 000000000..5b8d3514e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-3.c
@@ -0,0 +1,26 @@
+/* Check that on SH2A the 4 byte mov.b displacement insn is generated to
+   handle larger displacements.  If it is generated correctly, there should
+   be no base address adjustments outside the mov.b insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-not "add|sub" } } */
+
+void
+testfunc_00 (const char* ap, char* bp)
+{
+  bp[100] = ap[15];
+  bp[200] = ap[50];
+  bp[900] = ap[71];
+  bp[0] = ap[25];
+}
+
+void
+testfunc_01 (volatile const char* ap, volatile char* bp)
+{
+  bp[100] = ap[15];
+  bp[200] = ap[50];
+  bp[900] = ap[71];
+  bp[0] = ap[25];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-4.c
new file mode 100644
index 000000000..e0f3ab799
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-4.c
@@ -0,0 +1,30 @@
+/* Check that the mov.w displacement addressing insn is generated.
+   If the insn is generated as expected, there should be no address 
+   calculations outside the mov insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-not "add|sub" } } */
+
+void
+testfunc_00 (const short* ap, short* bp, short val)
+{
+  bp[0] = ap[15];
+  bp[2] = ap[5];
+  bp[9] = ap[7];
+  bp[0] = ap[15];
+  bp[4] = val;
+  bp[14] = val;
+}
+
+void
+testfunc_01 (volatile const short* ap, volatile short* bp, short val)
+{
+  bp[0] = ap[15];
+  bp[2] = ap[5];
+  bp[9] = ap[7];
+  bp[0] = ap[15];
+  bp[4] = val;
+  bp[14] = val;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-5.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-5.c
new file mode 100644
index 000000000..5da9ac2a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-5.c
@@ -0,0 +1,27 @@
+/* Check that the mov.w displacement addressing insn is generated and the 
+   base address is adjusted only once.  On SH2A this test is skipped because
+   there is a 4 byte mov.w insn that can handle larger displacements.  Thus
+   on SH2A the base address will not be adjusted in this case.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
+/* { dg-final { scan-assembler-times "add" 2 } } */
+
+void
+testfunc_00 (const short* ap, short* bp)
+{
+  bp[0] = ap[15];
+  bp[2] = ap[5];
+  bp[9] = ap[7];
+  bp[0] = ap[25];
+}
+
+void
+testfunc_01 (volatile const short* ap, volatile short* bp)
+{
+  bp[0] = ap[15];
+  bp[2] = ap[5];
+  bp[9] = ap[7];
+  bp[0] = ap[25];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-6.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-6.c
new file mode 100644
index 000000000..129729037
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-6.c
@@ -0,0 +1,26 @@
+/* Check that on SH2A the 4 byte mov.w displacement insn is generated to
+   handle larger displacements.  If it is generated correctly, there should
+   be no base address adjustments outside the mov.w insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-not "add|sub" } } */
+
+void
+testfunc_00 (const short* ap, short* bp)
+{
+  bp[100] = ap[15];
+  bp[200] = ap[50];
+  bp[900] = ap[71];
+  bp[0] = ap[25];
+}
+
+void
+testfunc_01 (volatile const short* ap, volatile short* bp)
+{
+  bp[100] = ap[15];
+  bp[200] = ap[50];
+  bp[900] = ap[71];
+  bp[0] = ap[25];
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-7.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-7.c
new file mode 100644
index 000000000..014575ad0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-7.c
@@ -0,0 +1,35 @@
+/* Check that mov.b and mov.w displacement insns are generated.
+   If this is working properly, there should be no base address adjustments
+   outside the mov insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-not "add|sub" } } */
+
+typedef struct 
+{
+  char	a;
+  char	b;
+  char	c;
+  char	d;
+
+  short e;
+  short f;
+
+  int g;
+  int h;
+} X;
+
+void
+testfunc_00 (X* x)
+{
+  x->g = x->b | x->c;
+  x->h = x->e | x->f;
+  x->d = x->g;
+  x->f = x->h;
+}
+
+int testfunc_01 (X* x)
+{
+  return x->b | x->e | x->g;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-8.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-8.c
new file mode 100644
index 000000000..d9eda44f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr50751-8.c
@@ -0,0 +1,100 @@
+/* Check that on SH2A the 4 byte movu.b and movu.w displacement insns are
+   generated.  This has to be checked with -O2 because some of the patterns
+   rely on peepholes.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "movu.b" 4 } } */
+/* { dg-final { scan-assembler-times "movu.w" 3 } } */
+
+int
+test_00 (unsigned char* x)
+{
+  /* 1x movu.b  */
+  return x[0];
+}
+
+int
+test_01 (unsigned short* x)
+{
+  /* 1x movu.w  */
+  return x[0];
+}
+
+int
+test_02 (unsigned char* x)
+{
+  /* 1x movu.b  */
+  return x[1];
+}
+
+int
+test_03 (unsigned char* x)
+{
+  /* 1x movu.b  */
+  return x[32];
+}
+
+int
+test_04 (unsigned char* x)
+{
+  /* 1x movu.b  */
+  return x[9000];
+}
+
+int
+test_05 (unsigned short* x)
+{
+  /* 1x movu.w  */
+  return x[9000];
+}
+
+int
+test_06 (unsigned char* x, int i)
+{
+  /* No movu.b expected here.  Should use mov.b (r0,r4) + extu.b instead.  */
+  return x[i];
+}
+
+int
+test_07 (unsigned short* x, int i)
+{
+  /* No movu.w expected here.  Should use mov.w (r0,r4) + extu.w instead.  */
+  return x[i];
+}
+
+int
+test_08 (unsigned char* x, int c)
+{
+  /* No movu.b expected here.  Should use post-inc addressing instead.  */
+  int s = 0;
+  int i;
+  for (i = 0; i < c; ++i)
+    s += x[i];
+  return s;
+}
+
+void
+test_09 (unsigned char* x, unsigned char* y)
+{
+  /* No movu.b expected here, since the zero-extension is irrelevant.  */
+  x[1] = y[1];
+  x[2] = y[2];
+}
+
+void
+test_10 (unsigned char* x, unsigned short* y)
+{
+  /* No movu.w expected here, since the zero-extension is irrelevant.  */
+  x[1] = y[1];
+  x[2] = y[2];
+}
+
+int
+test_11 (unsigned char* x, unsigned short* y)
+{
+  /* 1x movu.w  */
+  int yy = y[1];
+  x[1] = yy;
+  return yy;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-1.c
new file mode 100644
index 000000000..15e2ebd1b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-1.c
@@ -0,0 +1,32 @@
+/* Check that inverted conditional branch logic does not generate
+   unnecessary explicit T bit extractions, inversions and 
+   test instructions.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mbranch-cost=2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-not "movt|tst|negc|extu" } } */
+
+int
+testfunc_00 (int a, int b, int c, int d)
+{
+  return (a != b || a != d) ? b : c;
+}
+
+int
+testfunc_01 (int a, int b, int c, int d)
+{
+  return (a == b || a == d) ? b : c;
+}
+
+int
+testfunc_02 (int a, int b, int c, int d)
+{
+  return (a == b && a == d) ? b : c;
+}
+
+int
+testfunc_03 (int a, int b, int c, int d)
+{
+  return (a != b && a != d) ? b : c;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-10.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-10.c
new file mode 100644
index 000000000..ef16b75ff
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-10.c
@@ -0,0 +1,27 @@
+/* Check that compare-branch is inverted properly.
+   In this case the improved bit test is a side effect of compare-branch
+   inversion patterns, even though the branch condition does not get
+   inverted here.
+   Example:
+	mov.b	@(14,r9),r0	->	mov.b	@(14,r9),r0
+	shll	r0			cmp/pz	r0
+	subc	r0,r0			bt	.L192
+	and	#1,r0
+	tst	r0,r0
+	bt	.L195
+*/
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "shll|subc|and" } } */
+int
+test_00 (int* p)
+{
+  int nr = 15;
+  volatile char* addr = (volatile char*)&p[1];
+
+  if ((addr[(nr >> 3) ^ 7] & (1 << (nr & 7))) == 0)
+    return 40;
+  else
+    return 50;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-11.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-11.c
new file mode 100644
index 000000000..b673e9ac4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-11.c
@@ -0,0 +1,24 @@
+/* Check that zero-displacement branches are used instead of branch-free
+   execution patterns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mzdcbranch" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "subc|and" } } */
+
+int*
+test_00 (int* s)
+{
+  if (s[0] == 0)
+    if (!s[3])
+      s = 0;
+  return s;
+}
+
+int*
+test_01 (int* s)
+{
+  if (s[0] == 0)
+    if (s[3])
+      s = 0;
+  return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-12.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-12.c
new file mode 100644
index 000000000..da941015c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-12.c
@@ -0,0 +1,68 @@
+/* Check that the negc instruction is generated as expected for the cases
+   below.  If we see a movrt or #-1 negc sequence it means that the pattern
+   which handles the inverted case does not work properly.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-times "negc" 10 } } */
+/* { dg-final { scan-assembler-not "movrt|#-1|add|sub" } } */
+
+int
+test00 (int a, int b, int* x)
+{
+  return (a == b) ? 0x7FFFFFFF : 0x80000000;
+}
+
+int
+test00_inv (int a, int b)
+{
+  return (a != b) ? 0x80000000 : 0x7FFFFFFF;
+}
+
+int
+test01 (int a, int b)
+{
+  return (a >= b) ? 0x7FFFFFFF : 0x80000000;
+}
+
+int
+test01_inv (int a, int b)
+{
+  return (a < b) ? 0x80000000 : 0x7FFFFFFF;
+}
+
+int
+test02 (int a, int b)
+{
+  return (a > b) ? 0x7FFFFFFF : 0x80000000;
+}
+
+int
+test02_inv (int a, int b)
+{
+  return (a <= b) ? 0x80000000 : 0x7FFFFFFF;
+}
+
+int
+test03 (int a, int b)
+{
+  return ((a & b) == 0) ? 0x7FFFFFFF : 0x80000000;
+}
+
+int
+test03_inv (int a, int b)
+{
+  return ((a & b) != 0) ? 0x80000000 : 0x7FFFFFFF;
+}
+
+int
+test04 (int a)
+{
+  return ((a & 0x55) == 0) ? 0x7FFFFFFF : 0x80000000;
+}
+
+int
+test04_inv (int a)
+{
+  return ((a & 0x55) != 0) ? 0x80000000 : 0x7FFFFFFF;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-13.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-13.c
new file mode 100644
index 000000000..41d23eb94
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-13.c
@@ -0,0 +1,85 @@
+/* This is a case extracted from CSiBE which contained the following
+   sequence:
+	shll	r0
+	movt	r0
+	tst	r0,r0
+	bf	.L11
+   where the 'tst r0,r0' before the branch can be omitted by inverting the
+   branch condition.  The tested function contains two other tst insns.  If
+   everything goes as expected we will be seeing only those other two tst
+   insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-times "tst" 2 } } */
+
+static __inline__ int
+__test_bit (unsigned long nr, volatile void * addr)
+{
+  /*  This is on purpose.  */
+  int oldbit;
+  return oldbit & 1;
+}
+
+static __inline__ int
+__constant_test_bit (unsigned long nr, volatile void * addr)
+{
+  return (((volatile char *) addr)[(nr>>3)^7] & (1<<(nr&7))) != 0;
+}
+
+struct list_head
+{
+  struct list_head *next, *prev;
+};
+
+static inline void
+__list_del (struct list_head *prev, struct list_head *next)
+{
+  next->prev = prev;
+  prev->next = next;
+}
+
+static inline void
+list_del (struct list_head *entry)
+{
+ __list_del(entry->prev, entry->next);
+ entry->next = 0;
+ entry->prev = 0;
+}
+
+extern int nr_active_pages;
+extern int nr_inactive_pages;
+extern struct list_head active_list;
+
+typedef struct page
+{
+ unsigned long flags;
+ struct list_head lru;
+} mem_map_t;
+
+void
+activate_page_nolock (struct page * page)
+{
+ if ((__builtin_constant_p((6))
+      ? __constant_test_bit((6),(&(page)->flags))
+      : __test_bit((6),(&(page)->flags)) )
+     && !(__builtin_constant_p((7))
+          ? __constant_test_bit((7),(&(page)->flags))
+          : __test_bit((7),(&(page)->flags)) ))
+    {
+      list_del(&(page)->lru);
+      nr_inactive_pages--;
+      if (!(__builtin_constant_p(6) ? __constant_test_bit((6),(&(page)->flags))
+				    : __test_bit((6),(&(page)->flags))))
+	printk("", "", 43);
+
+      if ((__builtin_constant_p(7) ? __constant_test_bit((7),(&(page)->flags))
+				   : __test_bit((7),(&(page)->flags))))
+	printk("", "", 43);
+
+      (__builtin_constant_p(7) ? __constant_set_bit((7),(&(page)->flags))
+			        : __set_bit((7),(&(page)->flags)) );
+      list_add(&(page)->lru, &active_list);
+      nr_active_pages++;
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-14.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-14.c
new file mode 100644
index 000000000..844eb3a56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-14.c
@@ -0,0 +1,107 @@
+/* This is a case extracted from CSiBE which would sometimes contain the
+   following sequence:
+	cmp/eq	r12,r13
+	movt	r0
+	xor	#1,r0
+	extu.b	r0,r0
+	movt	r3
+	tst	r0,r0
+	bf/s	.L35
+   where the negated T bit store did not combine properly.  Since there are
+   other movt insns we only check for the xor and the extu.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "xor|extu" } } */
+
+typedef struct transaction_s transaction_t;
+
+struct journal_head
+{
+  transaction_t * b_transaction;
+  struct journal_head *b_cpnext, *b_cpprev;
+};
+
+struct transaction_s
+{
+  struct journal_head * t_checkpoint_list;
+  transaction_t *t_cpnext, *t_cpprev;
+};
+
+struct journal_s
+{
+  transaction_t * j_checkpoint_transactions;
+  unsigned long j_first, j_last;
+};
+
+typedef struct journal_s journal_t;
+
+extern int __try_to_free_cp_buf (struct journal_head *jh);
+extern int __cleanup_transaction (journal_t *journal, transaction_t *transaction);
+extern void __flush_batch (void **bhs, int *batch_count);
+extern void* jh2bh (void*);
+
+static int
+__flush_buffer (journal_t *journal, struct journal_head *jh,
+		void **bhs, int *batch_count, int *drop_count)
+{
+  void *bh = jh2bh (jh);
+  int ret = 0;
+  if (bh)
+    {
+      bhs[*batch_count] = bh;
+      (*batch_count)++;
+      if (*batch_count == 64)
+	  ret = 1;
+    }
+  else
+    {
+      int last_buffer = 0;
+      if (jh->b_cpnext == jh)
+	last_buffer = 1;
+      if (__try_to_free_cp_buf (jh))
+	{
+	  (*drop_count)++;
+	  ret = last_buffer;
+	}
+    }
+  return ret;
+}
+
+int
+log_do_checkpoint (journal_t *journal, int nblocks)
+{
+  transaction_t *transaction, *last_transaction, *next_transaction;
+  int batch_count = 0;
+  void *bhs[64];
+
+repeat:
+  transaction = journal->j_checkpoint_transactions;
+  if (transaction == ((void *)0))
+    return 0;
+  last_transaction = transaction->t_cpprev;
+  next_transaction = transaction;
+  do
+    {
+      struct journal_head *jh, *last_jh, *next_jh;
+      int drop_count = 0;
+      int cleanup_ret, retry = 0;
+      transaction = next_transaction;
+      next_transaction = transaction->t_cpnext;
+      jh = transaction->t_checkpoint_list;
+      last_jh = jh->b_cpprev;
+      next_jh = jh;
+      do
+	{
+	  jh = next_jh;
+	  next_jh = jh->b_cpnext;
+	  retry = __flush_buffer(journal, jh, bhs, &batch_count, &drop_count);
+	} while (jh != last_jh && !retry);
+
+      if (retry)
+	goto repeat;
+
+      cleanup_ret = __cleanup_transaction(journal, transaction);
+      goto repeat;
+    } while (transaction != last_transaction);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-15.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-15.c
new file mode 100644
index 000000000..e99963f8f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-15.c
@@ -0,0 +1,71 @@
+/* Check that the redundant test removal code in the *cbranch_t split works
+   as expected on non-SH2A targets.  Because on SH2A the movrt instruction
+   is used, this test is re-used and checked differently in pr51244-16.c.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
+/* { dg-final { scan-assembler-times "tst" 6 } } */
+/* { dg-final { scan-assembler-times "movt" 6 } } */
+/* { dg-final { scan-assembler-times "xor" 3 } } */
+/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
+
+typedef char bool;
+
+int
+test_0 (int a, int b, int c, int* d)
+{
+  /* non SH2A: 1x tst, 1x movt, 1x xor
+         SH2A: 1x tst, 1x movrt  */
+  bool x = a == 0;
+  d[2] = !x;
+  return x ? b : c;
+}
+
+int
+test_1 (int a, int b, int c, int* d)
+{
+  /* 1x tst, 1x movt  */
+  bool x = a != 0;
+  d[2] = !x;
+  return x ? b : c;
+}
+
+int
+test_2 (int a, int b, int c, char* d)
+{
+  /* Check that there is no sign/zero-extension before the store.
+     non SH2A: 1x tst, 1x movt, 1x xor
+         SH2A: 1x tst, 1x movrt  */
+  bool x = a == 0;
+  d[2] = !x;
+  return x ? b : c;
+}
+
+int
+test_3 (int a, int b, int c, char* d)
+{
+  /* Check that there is no sign/zero-extension before the store.
+     1x tst, 1x movt  */
+  bool x = a != 0;
+  d[2] = !x;
+  return x ? b : c;
+}
+
+int
+test_4 (int a, int b, int c, char* d)
+{
+  /* 1x tst, 1x movt  */
+  bool x = a != 0;
+  d[2] = !x;
+  return !x ? b : c;
+}
+
+int
+test_5 (int a, int b, int c, char* d)
+{
+  /* non SH2A: 1x tst, 1x movt, 1x xor
+         SH2A: 1x tst, 1x movrt  */
+  bool x = a == 0;
+  d[2] = !x;
+  return !x ? b : c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-16.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-16.c
new file mode 100644
index 000000000..5132f7433
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-16.c
@@ -0,0 +1,11 @@
+/* Check that the redundant test removal code in the *cbranch_t split works
+   as expected on SH2A targets.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "tst" 6 } } */
+/* { dg-final { scan-assembler-times "movt" 3 } } */
+/* { dg-final { scan-assembler-times "movrt" 3 } } */
+/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
+
+#include "pr51244-15.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-17.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-17.c
new file mode 100644
index 000000000..621abb788
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-17.c
@@ -0,0 +1,297 @@
+/* Check that no unnecessary zero extensions are done on values that are
+   results of arithmetic with T bit inputs.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "extu|exts" } } */
+
+int
+test00 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == 0;
+  return x == y;
+}
+
+int
+test01 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == d;
+  return x == y;
+}
+
+int
+test02 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c == d;
+  return x == y;
+}
+
+int
+test03 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c != d;
+  return x == y;
+}
+
+int
+test04 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c != d;
+  return x == y;
+}
+
+int
+test05 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == 0;
+  return x != y;
+}
+
+int
+test06 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == 0;
+  return x ^ y;
+}
+
+int
+test07 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == 0;
+  return x | y;
+}
+
+int
+test08 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == 0;
+  return x & y;
+}
+
+int
+test09 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == d;
+  return x != y;
+}
+
+int
+test10 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c == d;
+  return x != y;
+}
+
+int
+test11 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c != d;
+  return x != y;
+}
+
+int
+test12 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c != d;
+  return x != y;
+}
+
+int
+test13 (int a, int b, int c, int d, int e, int f)
+{
+  int x = a == b;
+  int y = c == 0;
+  int z = d == e;
+  return x == y || x == z;
+}
+
+int
+test14 (int a, int b, int c, int d, int e, int f)
+{
+  int x = a == b;
+  int y = c == 0;
+  int z = d == e;
+  return x == y && x == z;
+}
+
+int
+test15 (int a, int b, int c, int d, int e, int f)
+{
+  int x = a != b;
+  int y = c == 0;
+  int z = d == e;
+  return x == y || x == z;
+}
+
+int
+test16 (int a, int b, int c, int d, int e, int f)
+{
+  int x = a != b;
+  int y = c == 0;
+  int z = d == e;
+  return x == y && x == z;
+}
+
+int
+test17 (int a, int b, int c, int d, int e, int f)
+{
+  int x = a != b;
+  int y = c != 0;
+  int z = d == e;
+  return x == y || x == z;
+}
+
+int
+test18 (int a, int b, int c, int d, int e, int f)
+{
+  int x = a != b;
+  int y = c != 0;
+  int z = d == e;
+  return x == y && x == z;
+}
+
+int
+test19 (int a, int b, int c, int d, int e, int f)
+{
+  int x = a != b;
+  int y = c != 0;
+  int z = d == e;
+  return x == y || x == z;
+}
+
+int
+test20 (int a, int b, int c, int d, int e, int f)
+{
+  int x = a != b;
+  int y = c != 0;
+  int z = d != e;
+  return x == y && x == z;
+}
+
+int
+test21 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == 0;
+  return x + y;
+}
+
+int
+test22 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c == 0;
+  return x + y;
+}
+
+int
+test23 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c != 0;
+  return x + y;
+}
+
+int
+test24 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == 0;
+  return x - y;
+}
+
+int
+test25 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c == 0;
+  return x - y;
+}
+
+int
+test26 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c != 0;
+  return x - y;
+}
+
+int
+test27 (int a, int b, int c, int d)
+{
+  int x = a == b;
+  int y = c == 0;
+  return x * y;
+}
+
+int
+test28 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c == 0;
+  return x * y;
+}
+
+int
+test29 (int a, int b, int c, int d)
+{
+  int x = a != b;
+  int y = c != 0;
+  return x * y;
+}
+
+int
+test30 (int a, int b)
+{
+  return ((a & 0x7F) == 1)
+	  | ((a & 0xFF00) == 0x0200)
+	  | ((a & 0xFF0000) == 0x030000);
+}
+
+int
+test31 (int a, int b)
+{
+  return ((a & 0x7F) == 1)
+	  | ((a & 0xFF00) == 0x0200)
+	  | ((a & 0xFF0000) == 0x030000)
+	  | ((a & 0xFF000000) == 0x04000000);
+}
+
+int
+test32 (int* a, int b, int c, volatile char* d)
+{
+  d[1] = a[0] != 0;
+  return b;
+}
+
+int
+test33 (int* a, int b, int c, volatile char* d)
+{
+  d[1] = a[0] == 0;
+  return b;
+}
+
+char
+test34 (int a, int* b)
+{
+  return (b[4] & b[0] & a) == a;
+}
+
+unsigned char
+test35 (int a, int* b)
+{
+  return (b[4] & b[0] & a) == a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-18.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-18.c
new file mode 100644
index 000000000..19b244cea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-18.c
@@ -0,0 +1,102 @@
+/* Check that no unnecessary T bit stores are done before conditional
+   branches.
+   This case was extracted from the CSiBE set and contained the following
+   sequence:
+	cmp/hi	r1,r0
+	movt	r1
+	tst	r1,r1
+	bt	.L12
+	mov.l	@r10,r1
+   In this reduced code the movt and tst insns were only present in the
+   unwanted sequence.  Thus, if we see any tst or movt insns, something is
+   not working as expected.  This test requires -O2 because the T bit stores
+   in question will be eliminated in additional insn split passes after
+   reload.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "movt|tst" } } */
+
+typedef char Char;
+typedef unsigned char Bool;
+typedef unsigned char UChar;
+typedef int Int32;
+typedef unsigned int UInt32;
+typedef short Int16;
+typedef unsigned short UInt16;
+
+static inline Bool
+mainGtU (UInt32 i1, UInt32 i2, UChar* block, UInt16* quadrant, UInt32 nblock,
+	 Int32* budget)
+{
+  Int32 k;
+  UChar c1, c2;
+  UInt16 s1, s2;
+  k = nblock + 8;
+  do
+    {
+      c1 = block[i1];
+      c2 = block[i2];
+      if (c1 != c2)
+	return (c1 > c2);
+      s1 = quadrant[i1];
+      s2 = quadrant[i2];
+      if (s1 != s2)
+	return (s1 > s2);
+
+      i1++; i2++;
+      k -= 8;
+   } while (k >= 0);
+
+  return 0;
+}
+
+static inline void
+mainSimpleSort (UInt32* ptr, UChar* block, UInt16* quadrant, Int32 nblock,
+		Int32 lo, Int32 hi, Int32 d, Int32* budget)
+{
+  Int32 i, j, h, bigN, hp;
+  UInt32 v;
+  bigN = hi - lo + 1;
+  hp = 0;
+  h = 1;
+  j = lo + h;
+  v = ptr[j];
+
+  while (mainGtU (ptr[j-h]+d, v+d, block, quadrant, nblock, budget))
+    {
+      ptr[j] = ptr[j-h];
+      j = j - h;
+    }
+}
+
+static inline void
+mainQSort3 (UInt32* ptr, UChar* block, UInt16* quadrant, Int32 nblock,
+	    Int32 loSt, Int32 hiSt, Int32 dSt, Int32* budget)
+{
+  Int32 unLo, unHi, ltLo, gtHi;
+  Int32 sp, lo, hi, d;
+
+  Int32 stackLo[100];
+  Int32 stackHi[100];
+  Int32 stackD [100];
+
+  sp = 0;
+  stackLo[sp] = loSt;
+  stackHi[sp] = hiSt;
+  stackD [sp] = dSt;
+  lo = stackLo[sp];
+  hi = stackHi[sp];
+  d = stackD [sp];
+  mainSimpleSort (ptr, block, quadrant, nblock, lo, hi, d, budget);
+}
+
+void
+mainSort (UInt32* ptr, UChar* block, UInt16* quadrant, UInt32* ftab,
+	  Int32 nblock, Int32 verb, Int32* budget)
+{
+  Int32 sb = 0;
+  Int32 lo = ftab[sb] & (~((1 << 21)));
+  Int32 hi = (ftab[sb+1] & (~((1 << 21)))) - 1;
+  mainQSort3 (ptr, block, quadrant, nblock, lo, hi, 2, budget);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-19.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-19.c
new file mode 100644
index 000000000..5845d93f6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-19.c
@@ -0,0 +1,75 @@
+/* Check that no unnecessary T bit stores are done before conditional
+   branches.
+   This case was extracted from the CSiBE set and contained the following
+   sequence:
+	mov.l	@(8,r4),r2
+	mov.l	@(4,r4),r3
+	cmp/gt	r2,r3
+	movt	r2
+.L3:
+	tst	r2,r2
+	bt/s	.L12
+	mov	#-1,r0
+
+	.....
+
+	mov.l	@r4,r2
+	tst	r2,r2
+	bra	.L3
+	movt	r2
+
+   In this reduced code the movt insns were only present in the
+   unwanted sequences.  Thus, if we see any movt insns, something is not
+   working as expected.  This test requires -O2 because the T bit stores
+   in question will be eliminated in additional insn split passes after
+   reload.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "movt" } } */
+
+struct request
+{
+ unsigned long nr_sectors;
+};
+
+struct request_list
+{
+ int count;
+};
+
+struct request_queue
+{
+ struct request_list rq;
+ volatile int nr_sectors;
+ int max_queue_sectors;
+ int can_throttle;
+ unsigned long bounce_pfn;
+};
+
+typedef struct request_queue request_queue_t;
+
+static inline int
+blk_oversized_queue (request_queue_t* q)
+{
+  if (q->can_throttle)
+    return q->nr_sectors > q->max_queue_sectors;
+  return q->rq.count == 0;
+}
+
+struct request*
+get_request (request_queue_t* q, int rw)
+{
+  struct request* rq = ((void*)0);
+  struct request_list *rl = &q->rq;
+
+  if (blk_oversized_queue (q))
+    {
+      if ((rw == 1) || (rw == 0))
+	return ((void*)0);
+      if (blk_oversized_queue (q))
+	return ((void*)0);
+    }
+
+  return (void*)-100;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-2.c
new file mode 100644
index 000000000..a81ee7ed9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-2.c
@@ -0,0 +1,18 @@
+/* Check that when taking the complement of the T bit using the negc
+   instruction pattern, the constant -1 is loaded only once.
+   On SH2A this test is skipped because the movrt instruction is used
+   to get the complement of the T bit.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mbranch-cost=2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
+/* { dg-final { scan-assembler-times "mov\t#-1" 1 } } */
+
+void
+testfunc_00 (int* a, int* b, int c, int d)
+{
+  b[0] = a[0] != c;
+  b[1] = a[1] != d;
+  b[2] = a[2] != c;
+  b[3] = a[3] != d;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c
new file mode 100644
index 000000000..f2cd2de04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c
@@ -0,0 +1,14 @@
+/* Check that the SH specific sh_treg_combine RTL optimization pass works as
+   expected.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "tst" 5 } } */
+/* { dg-final { scan-assembler-times "movt" 0 } } */
+/* { dg-final { scan-assembler-times "nott" 1 } } */
+/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
+/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
+/* { dg-final { scan-assembler-times "cmp/gt" 3 } } */
+/* { dg-final { scan-assembler-times "not\t" 1 } } */
+
+#include "pr51244-20.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20.c
new file mode 100644
index 000000000..a9ded4635
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-20.c
@@ -0,0 +1,103 @@
+/* Check that the SH specific sh_treg_combine RTL optimization pass works as
+   expected.  On SH2A the expected insns are slightly different, see
+   pr51244-21.c.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
+/* { dg-final { scan-assembler-times "tst" 6 } } */
+/* { dg-final { scan-assembler-times "movt" 1 } } */
+/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
+/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
+/* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
+/* { dg-final { scan-assembler-times "not\t" 1 } } */
+
+
+/* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi
+   SH2A: 1x tst, 1x nott, 2x cmp/eq, 1x cmp/hi  */
+static inline int
+blk_oversized_queue_0 (int* q)
+{
+  if (q[2])
+    return q[1] == 5; 
+  return (q[0] != 5);
+}
+
+int __attribute__ ((noinline))
+get_request_0 (int* q, int rw)
+{
+  if (blk_oversized_queue_0 (q))
+    {
+      if ((rw == 1) || (rw == 0))
+	return -33;
+      return 0;
+    }
+  return -100;
+}
+
+
+/* 1x tst, 1x cmp/gt, 1x cmp/hi
+   On SH2A mem loads/stores have a wrong length of 4 bytes and thus will
+   not be placed in a delay slot.  This introduces an extra cmp/gt insn.  */
+static inline int
+blk_oversized_queue_1 (int* q)
+{
+  if (q[2])
+    return q[1] > 5; 
+  return (q[0] > 5);
+}
+
+int __attribute__ ((noinline))
+get_request_1 (int* q, int rw)
+{
+  if (blk_oversized_queue_1 (q))
+    {
+      if ((rw == 1) || (rw == 0))
+	return -33;
+      return 0;
+    }
+  return -100;
+}
+
+
+/* 1x tst, 1x cmp/gt, 1x cmp/hi, 1x cmp/hi  */
+static inline int
+blk_oversized_queue_2 (int* q)
+{
+  if (q[2])
+    return q[1] > 5; 
+  return (q[0] < 5);
+}
+
+int __attribute__ ((noinline))
+get_request_2 (int* q, int rw)
+{
+  if (blk_oversized_queue_2 (q))
+    {
+      if ((rw == 1) || (rw == 0))
+	return -33;
+      return 0;
+    }
+  return -100;
+}
+
+
+/* 2x tst, 1x cmp/hi, 1x not  */
+static inline int
+blk_oversized_queue_5 (int* q)
+{
+  if (q[2])
+    return q[1] != 0; 
+  return q[0] == 0;
+}
+
+int __attribute__ ((noinline))
+get_request_5 (int* q, int rw)
+{
+  if (blk_oversized_queue_5 (q))
+    {
+      if ((rw == 1) || (rw == 0))
+	return -33;
+      return 0;
+    }
+  return -100;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-3.c
new file mode 100644
index 000000000..92963c4be
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-3.c
@@ -0,0 +1,16 @@
+/* Check that when taking the complement of the T bit on SH2A, 
+   the movrt instruction is being generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mbranch-cost=2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "movrt" 4 } } */
+
+void
+testfunc_00 (int* a, int* b, int c, int d)
+{
+  b[0] = a[0] != c;
+  b[1] = a[1] != d;
+  b[2] = a[2] != c;
+  b[3] = a[3] != d;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-4.c
new file mode 100644
index 000000000..a11429b15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-4.c
@@ -0,0 +1,19 @@
+/* Check that storing the (negated) T bit as all ones or zeros in a reg
+   uses the subc instruction.  On SH2A a sequence with the movrt instruction
+   is also OK instead of subc.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mbranch-cost=2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-not "movt|tst|negc" } } */
+/* { dg-final { scan-assembler "subc|movrt|neg|not" } } */
+
+int test_00 (int x, int y)
+{
+  return x != y ? -1 : 0;
+}
+
+int test_01 (int x, int y)
+{
+  return x == y ? -1 : 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-5.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-5.c
new file mode 100644
index 000000000..c0f05a105
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-5.c
@@ -0,0 +1,50 @@
+/* Check that no unnecessary sign or zero extension insn is generated after
+   a negc or movrt insn that stores the inverted T bit in a reg.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "extu|exts" } } */
+
+int
+test_00 (int a, int b, int* c, short* d, int x)
+{
+  *d = x != 0;
+  *c = -1;
+
+  if (x != 0)
+    return a > 0;
+
+  return 0;
+}
+
+unsigned char
+test_01 (int x)
+{
+  if (x < 58 && x > 47)
+    return 1;
+  return 0;
+}
+
+char
+test_02 (int x)
+{
+  if (x < 58 && x > 47)
+    return 1;
+  return 0;
+}
+
+unsigned short
+test_03 (int x)
+{
+  if (x < 58 && x > 47)
+    return 1;
+  return 0;
+}
+
+short
+test_04 (int x)
+{
+  if (x < 58 && x > 47)
+    return 1;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-6.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-6.c
new file mode 100644
index 000000000..3f9aafb7d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-6.c
@@ -0,0 +1,15 @@
+/* Check that no unnecessary sign or zero extension insn is generated after
+   a negc or movrt insn that stores the inverted T bit in a reg.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-not "extu|exts" } } */
+
+float
+test_00 (float q[4], float m[9])
+{
+  float s0 = m[0] + m[1];
+  float s1 = m[0] - m[1];
+
+  return q[s0 > s1 ?  0 : 1];
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-7.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-7.c
new file mode 100644
index 000000000..d4d39745d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-7.c
@@ -0,0 +1,26 @@
+/* Check that compare-branch is inverted properly.
+   Example:
+	clrt		->	clrt
+	subc	r0,r6		subc	r0,r6
+	mov	r3,r7		mov	r3,r7
+	subc	r1,r7		subc	r1,r7
+	mov	#0,r1		tst	r7,r7
+	cmp/hi	r1,r7		bf	.L111
+	bt	.L111		bra	.L197
+	bra	.L197
+	nop
+*/
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "cmp/hi" } } */
+/* { dg-final { scan-assembler-not "mov\t#0" } } */
+
+int other_func (long long);
+int
+test_00 (unsigned long long a, unsigned long long b)
+{
+  if ((a - b) > 0xFFFFFFFFLL)
+    return other_func (a - b);
+  return 20;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-8.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-8.c
new file mode 100644
index 000000000..d8c1269bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-8.c
@@ -0,0 +1,27 @@
+/* Check that compare-branch is inverted properly.
+   Example:
+	mov	#1,r0	->	tst	r8,r8
+	neg	r8,r1		bt	.L47
+	shad	r1,r0
+	tst	#1,r0
+	bf	.L47
+*/
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "shad|neg" } } */
+
+int test_01_00 (int*, void*);
+int
+test_01 (int* m, void* v)
+{
+  unsigned long n = (unsigned long)v - 1;
+
+  if (!n)
+    return 50;
+  
+  if (1 & (1 << n))	/* if n == 0: 1 & (1 << 0) -> true  */
+    return 60;		
+  else			/* if n != 0: 1 & (1 << n) -> false  */
+    return -8;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-9.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-9.c
new file mode 100644
index 000000000..cca90a843
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51244-9.c
@@ -0,0 +1,35 @@
+/* Check that compare-branch is inverted properly.
+   Example:
+	mov.w	.L566,r2	->	mov.w	.L566,r2
+	add	r11,r2			add	r11,r2
+	mov.l	@(12,r2),r7		mov.l	@(8,r2),r5
+	mov.l	@(8,r2),r5		mov.l	@(12,r2),r2
+	mov	#0,r2			tst	r2,r2
+	cmp/hi	r2,r7			bt	.L534
+	bf	.L534
+*/
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "mov\t#0" } } */
+static inline unsigned int
+test_03_00 (unsigned int x)
+{
+  /* Return unassigned value on purpose.  */
+  unsigned int res;
+  return res;
+}
+
+struct S
+{
+  unsigned int a;
+  unsigned int b;
+};
+
+int test_03 (struct S* i)
+{
+ if ((i->a != 2 && i->a != 3) || i->a > test_03_00 (i->b))
+   return -5;
+
+ return -55;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51697.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51697.c
new file mode 100644
index 000000000..d63e329bf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr51697.c
@@ -0,0 +1,21 @@
+/* Check that DImode comparisons are optimized as expected when compiling
+   with -Os.  */
+/* { dg-do compile }  */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "tst" 2 } }  */
+/* { dg-final { scan-assembler-not "cmp" } }  */
+
+int
+test_00 (long long* x)
+{
+  /* 1x tst, no cmp/* insns.  */
+  return *x & 0xFFFFFFFF ? -20 : -40;
+}
+
+int
+test_01 (unsigned long long x)
+{
+  /* 1x tst, no cmp/* insns.  */
+  return x >= 0x100000000LL ? -20 : -40;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-1.c
new file mode 100644
index 000000000..ca64a0a2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-1.c
@@ -0,0 +1,54 @@
+/* Check that loads/stores from/to volatile mems don't result in redundant
+   sign/zero extensions.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-not "exts|extu" } } */
+
+int
+test_00 (volatile char* x)
+{
+  return *x;
+}
+
+void
+test_100 (volatile char* x, char y)
+{
+  *x = y;
+}
+
+int
+test_01 (volatile short* x)
+{
+  return *x;
+}
+
+void
+test_101 (volatile unsigned char* x, unsigned char y)
+{
+  *x = y;
+}
+
+int
+test_02 (volatile unsigned char* x)
+{
+  return *x == 0x80;
+}
+
+void
+test_102 (volatile short* x, short y)
+{
+  *x = y;
+}
+
+int
+test_03 (volatile unsigned short* x)
+{
+  return *x == 0xFF80;
+}
+
+void
+test_103 (volatile unsigned short* x, unsigned short y)
+{
+  *x = y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-2.c
new file mode 100644
index 000000000..68e7f8e25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-2.c
@@ -0,0 +1,110 @@
+/* Check that loads/stores from/to volatile mems utilize displacement
+   addressing modes and do not result in redundant sign/zero extensions. */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "@\\(5," 4 } } */
+/* { dg-final { scan-assembler-times "@\\(10," 4 } } */
+/* { dg-final { scan-assembler-times "@\\(20," 4 } } */
+/* { dg-final { scan-assembler-times "@\\(40," 4 } } */
+/* { dg-final { scan-assembler-times "@\\(44," 4 } } */
+/* { dg-final { scan-assembler-not "exts" } } */
+/* { dg-final { scan-assembler-times "extu|movu" 2 } } */
+
+int
+test_00 (volatile char* x)
+{
+  return x[5];
+}
+
+void
+test_100 (volatile char* x, char y)
+{
+  x[5] = y;
+}
+
+int
+test_01 (volatile short* x)
+{
+  return x[5];
+}
+
+void
+test_101 (volatile short* x, short y)
+{
+  x[5] = y;
+}
+
+int
+test_02 (volatile int* x)
+{
+  return x[5];
+}
+
+void
+test_102 (volatile int* x, int y)
+{
+  x[5] = y;
+}
+
+long long
+test_03 (volatile long long* x)
+{
+  return x[5];
+}
+
+void
+test_103 (volatile long long* x, long long y)
+{
+  x[5] = y;
+}
+
+unsigned int
+test_04 (volatile unsigned char* x)
+{
+  // expected 1x extu.b or movu.b
+  return x[5];
+}
+
+void
+test_104 (volatile unsigned char* x, unsigned char y)
+{
+  x[5] = y;
+}
+
+unsigned int
+test_05 (volatile unsigned short* x)
+{
+  // expected 1x extu.w or movu.w
+  return x[5];
+}
+
+void
+test_105 (volatile unsigned short* x, unsigned short y)
+{
+  x[5] = y;
+}
+ 
+unsigned int
+test_06 (volatile unsigned int* x)
+{
+  return x[5];
+}
+
+void
+test_106 (volatile unsigned int* x, unsigned int y)
+{
+  x[5] = y;
+}
+
+unsigned long long
+test_07 (volatile unsigned long long* x)
+{
+  return x[5];
+}
+
+void
+test_107 (volatile unsigned long long* x, unsigned long long y)
+{
+  x[5] = y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-3.c
new file mode 100644
index 000000000..baeec3343
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-3.c
@@ -0,0 +1,43 @@
+/* Check that loads/stores from/to volatile mems utilize indexed addressing
+   modes and do not result in redundant sign/zero extensions. */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "@\\(r0," 6 } } */
+/* { dg-final { scan-assembler-not "exts|extu" } } */
+
+int
+test_00 (volatile char* x, unsigned int y)
+{
+  return x[y];
+}
+
+void
+test_100 (volatile char* x, unsigned int y, char z)
+{
+  x[y] = z;
+}
+
+int
+test_01 (volatile short* x, unsigned int y)
+{
+  return x[y];
+}
+
+void
+test_101 (volatile short* x, unsigned int y, short z)
+{
+  x[y] = z;
+}
+
+int
+test_02 (volatile int* x, unsigned int y)
+{
+  return x[y];
+}
+
+int
+test_102 (volatile int* x, unsigned int y, int z)
+{
+  x[y] = z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-4.c
new file mode 100644
index 000000000..743e8dc54
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-4.c
@@ -0,0 +1,18 @@
+/* Check that loads/stores from/to volatile floating point mems utilize
+   indexed addressing modes. */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "@\\(r0," 2 } } */
+
+float
+test_00 (volatile float* x, unsigned int y)
+{
+  return x[y];
+}
+
+void
+test_100 (volatile float* x, unsigned int y, float z)
+{
+  x[y] = z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-5.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-5.c
new file mode 100644
index 000000000..50aefe2cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52483-5.c
@@ -0,0 +1,28 @@
+/* Check that loads from volatile mems utilize post-increment addressing
+   modes and do not result in redundant sign extensions. */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "@r\[0-9\]\+\\+," 3 } } */
+/* { dg-final { scan-assembler-not "exts" } } */
+
+volatile char*
+test_00 (volatile char* x)
+{
+  int xx = *x++;
+  return x;
+}
+
+volatile short*
+test_01 (volatile short* x)
+{
+  int xx = *x++;
+  return x;
+}
+
+volatile int*
+test_02 (volatile int* x)
+{
+  int xx = *x++;
+  return x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52933-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52933-1.c
new file mode 100644
index 000000000..b65707ee4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52933-1.c
@@ -0,0 +1,168 @@
+/* Check that the div0s instruction is used for integer sign comparisons.
+   Each test case is expected to emit at least one div0s insn.
+   Problems when combining the div0s comparison result with surrounding
+   logic usually show up as redundant tst insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-times "div0s" 25 } } */
+/* { dg-final { scan-assembler-not "tst" } } */
+
+typedef unsigned char bool;
+
+int other_func_a (int, int);
+int other_func_b (int, int);
+
+bool
+test_00 (int a, int b)
+{
+  return (a ^ b) >= 0;
+}
+
+bool
+test_01 (int a, int b)
+{
+  return (a ^ b) < 0;
+}
+
+int
+test_02 (int a, int b, int c, int d)
+{
+  if ((a ^ b) < 0)
+    return other_func_a (a, c);
+  else
+    return other_func_b (d, b);
+}
+
+int
+test_03 (int a, int b, int c, int d)
+{
+  if ((a ^ b) >= 0)
+    return other_func_a (a, c);
+  else
+    return other_func_b (d, b);
+}
+
+int
+test_04 (int a, int b)
+{
+  return (a ^ b) >= 0 ? -20 : -40;
+}
+
+bool
+test_05 (int a, int b)
+{
+  return (a ^ b) < 0;
+}
+
+int
+test_06 (int a, int b)
+{
+  return (a ^ b) < 0 ? -20 : -40;
+}
+
+bool
+test_07 (int a, int b)
+{
+  return (a < 0) == (b < 0);
+}
+
+int
+test_08 (int a, int b)
+{
+  return (a < 0) == (b < 0) ? -20 : -40;
+}
+
+bool
+test_09 (int a, int b)
+{
+  return (a < 0) != (b < 0);
+}
+
+int
+test_10 (int a, int b)
+{
+  return (a < 0) != (b < 0) ? -20 : -40;
+}
+
+bool
+test_11 (int a, int b)
+{
+  return (a >= 0) ^ (b < 0);
+}
+
+int
+test_12 (int a, int b)
+{
+  return (a >= 0) ^ (b < 0) ? -20 : -40;
+}
+
+bool
+test_13 (int a, int b)
+{
+  return !((a >= 0) ^ (b < 0));
+}
+
+int
+test_14 (int a, int b)
+{
+  return !((a >= 0) ^ (b < 0)) ? -20 : -40;
+}
+
+bool
+test_15 (int a, int b)
+{
+ return (a & 0x80000000) == (b & 0x80000000);
+}
+
+int
+test_16 (int a, int b)
+{
+  return (a & 0x80000000) == (b & 0x80000000) ? -20 : -40;
+}
+
+bool
+test_17 (int a, int b)
+{
+  return (a & 0x80000000) != (b & 0x80000000);
+}
+
+int
+test_18 (int a, int b)
+{
+  return (a & 0x80000000) != (b & 0x80000000) ? -20 : -40;
+}
+
+int
+test_19 (unsigned int a, unsigned int b)
+{
+  return (a ^ b) >> 31;
+}
+
+int
+test_20 (unsigned int a, unsigned int b)
+{
+  return (a >> 31) ^ (b >> 31);
+}
+
+int
+test_21 (int a, int b)
+{
+  return ((a & 0x80000000) ^ (b & 0x80000000)) >> 31 ? -30 : -10;
+}
+
+int
+test_22 (int a, int b, int c, int d)
+{
+  if ((a < 0) == (b < 0))
+    return other_func_a (a, b);
+  else
+    return other_func_b (c, d);
+}
+
+bool
+test_23 (int a, int b, int c, int d)
+{
+  /* Should emit 2x div0s.  */
+  return ((a < 0) == (b < 0)) | ((c < 0) == (d < 0));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52933-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52933-2.c
new file mode 100644
index 000000000..865cb3709
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr52933-2.c
@@ -0,0 +1,12 @@
+/* Check that the div0s instruction is used for integer sign comparisons
+   when -mpretend-cmove is enabled.
+   Each test case is expected to emit at least one div0s insn.
+   Problems when combining the div0s comparison result with surrounding
+   logic usually show up as redundant tst insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2 -mpretend-cmove" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-times "div0s" 25 } } */
+/* { dg-final { scan-assembler-not "tst" } } */
+
+#include "pr52933-1.c"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53511-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53511-1.c
new file mode 100644
index 000000000..d58a72c3b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53511-1.c
@@ -0,0 +1,14 @@
+/* Verify that the fmac insn is used for the standard fmaf function.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler "fmac" } } */
+
+#include <math.h>
+
+float
+test_func_00 (float a, float b, float c)
+{
+  return fmaf (a, b, c);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-1.c
new file mode 100644
index 000000000..c54671bd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-1.c
@@ -0,0 +1,26 @@
+/* Verify that the fsca insn is used when specifying -mfsca and
+  -funsafe-math-optimizations.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mfsca -funsafe-math-optimizations" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fsca" 3 } } */
+
+#include <math.h>
+
+float
+test_func_00 (float x)
+{
+  return sinf (x) + cosf (x);
+}
+
+float
+test_func_01 (float x)
+{
+  return sinf (x);
+}
+
+float
+test_func_02 (float x)
+{
+  return cosf (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-2.c
new file mode 100644
index 000000000..ed410116c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-2.c
@@ -0,0 +1,26 @@
+/* Verify that the fsca insn is not used when specifying -mno-fsca and
+  -funsafe-math-optimizations.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mno-fsca -funsafe-math-optimizations" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-not "fsca" } } */
+
+#include <math.h>
+
+float
+test_func_00 (float x)
+{
+  return sinf (x) + cosf (x);
+}
+
+float
+test_func_01 (float x)
+{
+  return sinf (x);
+}
+
+float
+test_func_02 (float x)
+{
+  return cosf (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-3.c
new file mode 100644
index 000000000..71522c8d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-3.c
@@ -0,0 +1,15 @@
+/* Verify that the fsrra insn is used when specifying -mfsrra and
+  -funsafe-math-optimizations and -ffinite-math-only.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mfsrra -funsafe-math-optimizations -ffinite-math-only" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler "fsrra" } } */
+
+#include <math.h>
+
+float
+test_func_00 (float x)
+{
+  return 1 / sqrtf (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-4.c
new file mode 100644
index 000000000..1645eed52
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53512-4.c
@@ -0,0 +1,15 @@
+/* Verify that the fsrra insn is not used when specifying -mno-fsrra and
+  -funsafe-math-optimizations and -ffinite-math-only.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -mno-fsrra -funsafe-math-optimizations -ffinite-math-only" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-not "fsrra" } } */
+
+#include <math.h>
+
+float
+test_func_00 (float x)
+{
+  return 1 / sqrtf (x);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53568-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53568-1.c
new file mode 100644
index 000000000..e274170fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53568-1.c
@@ -0,0 +1,82 @@
+/* Check that the bswap32 pattern is generated as swap.b and swap.w
+   instructions.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "swap.w" 7 } } */
+/* { dg-final { scan-assembler-times "swap.b" 16 } } */
+/* { dg-final { scan-assembler-times "extu.w" 2 } } */
+/* { dg-final { scan-assembler-times "mov" 1 } } */
+/* { dg-final { scan-assembler-not "{shll8|shlr8|shld|shad}" } } */
+
+int
+test_func_00 (int a)
+{
+  /* 1x swap.w
+     2x swap.b  */
+  return __builtin_bswap32 (a);
+}
+
+unsigned int
+test_func_01 (unsigned int a)
+{
+  /* 1x swap.w
+     2x swap.b  */
+  return __builtin_bswap32 (a);
+}
+
+int
+test_func_02 (int a)
+{
+  /* 1x swap.w
+     2x swap.b  */
+  return (((a >> 0) & 0xFF) << 24)
+	 | (((a >> 8) & 0xFF) << 16)
+	 | (((a >> 16) & 0xFF) << 8)
+	 | (((a >> 24) & 0xFF) << 0);
+}
+
+unsigned int
+test_func_03 (unsigned int a)
+{
+  /* 1x swap.w
+     2x swap.b  */
+  return (((a >> 0) & 0xFF) << 24)
+	 | (((a >> 8) & 0xFF) << 16)
+	 | (((a >> 16) & 0xFF) << 8)
+	 | (((a >> 24) & 0xFF) << 0);
+}
+
+int
+test_func_04 (int a)
+{
+  /* 1x swap.b
+     1x extu.w  */
+  return __builtin_bswap32 (a) >> 16;
+}
+
+unsigned short
+test_func_05 (unsigned short a)
+{
+  /* 1x swap.b
+     1x extu.w  */
+  return __builtin_bswap32 (a) >> 16;
+}
+
+long long
+test_func_06 (long long a)
+{
+  /* 2x swap.w
+     4x swap.b  */
+  return __builtin_bswap64 (a);
+}
+
+long long
+test_func_07 (long long a)
+{
+  /* 1x swap.w
+     2x swap.b
+     1x mov #0,Rn  */
+  return __builtin_bswap64 (a) >> 32;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53976-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53976-1.c
new file mode 100644
index 000000000..4893b0668
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53976-1.c
@@ -0,0 +1,41 @@
+/* Check that the SH specific sh_optimize_sett_clrt RTL optimization pass
+   works as expected.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-times "clrt" 2 } } */
+/* { dg-final { scan-assembler-times "sett" 1 } } */
+
+long long
+test_00 (long long a, long long b, long long c, int d)
+{
+  /* One of the blocks should have a clrt and the other one should not.  */
+  if (d > 5)
+    return a + b;
+  else
+    return a + c;
+}
+
+long long
+test_01 (long long a, long long b)
+{
+  /* Must see a clrt because T bit is undefined at function entry.  */
+  return a + b;
+}
+
+int
+test_02 (const char* a)
+{
+  /* Must not see a sett after the inlined strlen.  */
+  return __builtin_strlen (a);
+}
+
+int
+test_03 (int a, int b, int c, int d)
+{
+  /* One of the blocks should have a sett and the other one should not.  */
+  if (d > 4)
+    return a + b + 1;
+  else
+    return a + c + 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53988.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53988.c
new file mode 100644
index 000000000..a2e7213cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr53988.c
@@ -0,0 +1,74 @@
+/* Check that the tst Rm,Rn instruction is generated for QImode and HImode
+   values loaded from memory.  If everything goes as expected we won't see
+   any sign/zero extensions or and ops.  On SH2A we don't expect to see the
+   movu insn.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "tst\tr" 8 } } */
+/* { dg-final { scan-assembler-not "tst\t#255" } } */
+/* { dg-final { scan-assembler-not "exts|extu|and|movu" } } */
+
+int
+test00 (char* a, char* b, int c, int d)
+{
+  if (*a & *b)
+    return c;
+  return d;
+}
+
+int
+test01 (unsigned char* a, unsigned char* b, int c, int d)
+{
+  if (*a & *b)
+    return c;
+  return d;
+}
+
+int
+test02 (short* a, short* b, int c, int d)
+{
+  if (*a & *b)
+    return c;
+  return d;
+}
+
+int
+test03 (unsigned short* a, unsigned short* b, int c, int d)
+{
+  if (*a & *b)
+    return c;
+  return d;
+}
+
+int
+test04 (char* a, short* b, int c, int d)
+{
+  if (*a & *b)
+    return c;
+  return d;
+}
+
+int
+test05 (short* a, char* b, int c, int d)
+{
+  if (*a & *b)
+    return c;
+  return d;
+}
+
+int
+test06 (int* a, char* b, int c, int d)
+{
+  if (*a & *b)
+    return c;
+  return d;
+}
+
+int
+test07 (int* a, short* b, int c, int d)
+{
+  if (*a & *b)
+    return c;
+  return d;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-1.c
new file mode 100644
index 000000000..3eb700ad2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-1.c
@@ -0,0 +1,174 @@
+/* Check that the rotcr instruction is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "rotcr" 24 } } */
+/* { dg-final { scan-assembler-times "shll\t" 1 } } */
+
+typedef char bool;
+
+long long
+test_00 (long long a)
+{
+  return a >> 1;
+}
+
+unsigned int
+test_01 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 1) | (r << 31));
+}
+
+unsigned int
+test_02 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 2) | (r << 31));
+}
+
+unsigned int
+test_03 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 3) | (r << 31));
+}
+
+unsigned int
+test_04 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 4) | (r << 31));
+}
+
+unsigned int
+test_05 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 5) | (r << 31));
+}
+
+unsigned int
+test_06 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 6) | (r << 31));
+}
+
+unsigned int
+test_07 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 7) | (r << 31));
+}
+
+unsigned int
+test_08 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 8) | (r << 31));
+}
+
+unsigned int
+test_09 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a >> 31) | (r << 31));
+}
+
+int
+test_10 (int a, int b)
+{
+  bool r = a == b;
+  return r << 31;
+}
+
+unsigned int
+test_11 (unsigned int a, int b)
+{
+  /* 1x shlr, 1x rotcr  */
+  return (a >> 1) | (b << 31);
+}
+
+unsigned int
+test_12 (unsigned int a, int b)
+{
+  return (a >> 2) | (b << 31);
+}
+
+unsigned int
+test_13 (unsigned int a, int b)
+{
+  return (a >> 3) | (b << 31);
+}
+
+unsigned int
+test_14 (unsigned int a, int b)
+{
+  /* 1x shll, 1x rotcr  */
+  bool r = b < 0;
+  return ((a >> 1) | (r << 31));
+}
+
+unsigned int
+test_15 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 1) | (r << 31));
+}
+
+unsigned int
+test_16 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 2) | (r << 31));
+}
+
+unsigned int
+test_17 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 3) | (r << 31));
+}
+
+unsigned int
+test_18 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 4) | (r << 31));
+}
+
+unsigned int
+test_19 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 5) | (r << 31));
+}
+
+unsigned int
+test_20 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 6) | (r << 31));
+}
+
+unsigned int
+test_21 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 7) | (r << 31));
+}
+
+unsigned int
+test_22 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 8) | (r << 31));
+}
+
+unsigned int
+test_23 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a >> 31) | (r << 31));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-2.c
new file mode 100644
index 000000000..17466f3e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-2.c
@@ -0,0 +1,22 @@
+/* Check that for dynamic logical right shifts with a constant the negated
+   constant is loaded directly, instead of loading the postitive constant
+   and negating it separately.  This was a case that happened at optimization
+   level -O2 and looked like:
+	cmp/eq	r6,r5
+	mov	#30,r1
+	neg	r1,r1
+	shld	r1,r4
+	mov	r4,r0
+	rts
+	rotcr	r0  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*"} { "-m3* -m2a* -m4*" } }  */
+/* { dg-final { scan-assembler-not "neg" } } */
+
+unsigned int
+test (unsigned int a, int b, int c)
+{
+  unsigned char r = b == c;
+  return ((a >> 31) | (r << 31));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-3.c
new file mode 100644
index 000000000..abdb021ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-3.c
@@ -0,0 +1,40 @@
+/* The dynamic shift library functions truncate the shift count to 5 bits.
+   Verify that this is taken into account and no extra shift count
+   truncations are generated before the library call.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2" "-m2e*" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+/* { dg-final { scan-assembler-not "#31" } } */
+
+int
+test00 (unsigned int a, int* b, int c, int* d, unsigned int e)
+{
+  int s = 0;
+  int i;
+  for (i = 0; i < c; ++i)
+    s += d[i] + b[i] + (e << (i & 31));
+  return s;  
+}
+
+int
+test01 (unsigned int a, int* b, int c, int* d, unsigned int e)
+{
+  int s = 0;
+  int i;
+  for (i = 0; i < c; ++i)
+    s += d[i] + b[i] + (e >> (i & 31));
+  return s;  
+}
+
+int
+test03 (unsigned int a, unsigned int b)
+{
+  return b << (a & 31);
+}
+
+unsigned int
+test04 (unsigned int a, int b)
+{
+  return a >> (b & 31);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-4.c
new file mode 100644
index 000000000..e01e51c0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-4.c
@@ -0,0 +1,15 @@
+/* Check that the rotcr instruction is generated when shifting the
+   negated T bit on non-SH2A.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } }  */
+/* { dg-final { scan-assembler-times "rotcr" 1 } } */
+/* { dg-final { scan-assembler-times "tst" 1 } } */
+/* { dg-final { scan-assembler-times "movt" 1 } } */
+
+int
+test_00 (int a, int b)
+{
+  int r = a != b;
+  return r << 31;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-5.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-5.c
new file mode 100644
index 000000000..decb9db95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-5.c
@@ -0,0 +1,14 @@
+/* Check that the movrt rotr instruction sequence is generated when shifting
+   the negated T bit on SH2A.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "movrt" 1 } } */
+/* { dg-final { scan-assembler-times "rotr" 1 } } */
+
+int
+test_00 (int a, int b)
+{
+  int r = a != b;
+  return r << 31;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-6.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-6.c
new file mode 100644
index 000000000..577690dd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-6.c
@@ -0,0 +1,36 @@
+/* Check that the rotr and rotl instructions are generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "rotr" 2 } } */
+/* { dg-final { scan-assembler-times "rotl" 3 } } */
+
+int
+test_00 (int a)
+{
+  return (a << 1) | ((a >> 31) & 1);
+}
+
+int
+test_01 (int a)
+{
+  return (a << 1) | ((unsigned int)a >> 31);
+}
+
+int
+test_02 (int a)
+{
+  return ((unsigned int)a >> 1) | (a << 31);
+}
+
+int
+test_03 (int a)
+{
+  return ((a >> 1) & 0x7FFFFFFF) | (a << 31);
+}
+
+int
+test_04 (int a)
+{
+  return a + a + ((a >> 31) & 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-7.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-7.c
new file mode 100644
index 000000000..0476f75d1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-7.c
@@ -0,0 +1,63 @@
+/* Check that the rotcr instruction is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "rotcr" 4 } } */
+/* { dg-final { scan-assembler-not "movt" } } */
+/* { dg-final { scan-assembler-not "or\t" } } */
+/* { dg-final { scan-assembler-not "rotr" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+typedef char bool;
+
+int
+test_00 (int* a, int* b)
+{
+  int i;
+  unsigned int r = 0;
+  for (i = 0; i < 16; ++i)
+    {
+      bool t = a[i] == b[i];
+      r = (t << 31) | (r >> 1);
+    }
+  return r;
+}
+
+int
+test_01 (int* a, int* b)
+{
+  int i;
+  unsigned int r = 0;
+  for (i = 0; i < 16; ++i)
+    {
+      bool t = a[i] == b[i];
+      r = (t << 31) | (r >> 2);
+    }
+  return r;
+}
+
+int
+test_02 (int* a, int* b)
+{
+  int i;
+  unsigned int r = 0;
+  for (i = 0; i < 16; ++i)
+    {
+      bool t = a[i] == b[i];
+      r = (t << 31) | (r >> 3);
+    }
+  return r;
+}
+
+unsigned int
+test_03 (const bool* a)
+{
+  int i;
+  unsigned int r = 0;
+  for (i = 0; i < 32; ++i)
+    {
+      bool t = a[i];
+      r = (t << 31) | (r >> 1);
+    }
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-8.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-8.c
new file mode 100644
index 000000000..d2cced75a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-8.c
@@ -0,0 +1,203 @@
+/* Check that the rotcl instruction is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "rotcl" 28 } } */
+
+typedef char bool;
+
+long long
+test_00 (long long a)
+{
+  return a << 1;
+}
+
+unsigned int
+test_01 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 1) | r);
+}
+
+unsigned int
+test_02 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 2) | r);
+}
+
+unsigned int
+test_03 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 3) | r);
+}
+
+unsigned int
+test_04 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 4) | r);
+}
+
+unsigned int
+test_05 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 5) | r);
+}
+
+unsigned int
+test_06 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 6) | r);
+}
+
+unsigned int
+test_07 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 7) | r);
+}
+
+unsigned int
+test_08 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 8) | r);
+}
+
+unsigned int
+test_09 (unsigned int a, int b, int c)
+{
+  bool r = b == c;
+  return ((a << 31) | r);
+}
+
+unsigned int
+test_10 (unsigned int a, int b)
+{
+  /* 1x shlr, 1x rotcl  */
+  return (a << 1) | (b & 1);
+}
+
+unsigned int
+test_11 (unsigned int a, int b)
+{
+  /* 1x shlr, 1x rotcl (+1x add as shll)  */
+  return (a << 2) | (b & 1);
+}
+
+unsigned int
+test_12 (unsigned int a, int b)
+{
+  /* 1x shlr, 1x shll2, 1x rotcl  */
+  return (a << 3) | (b & 1);
+}
+
+unsigned int
+test_13 (unsigned int a, int b)
+{
+  /* 1x shll, 1x rotcl  */
+  bool r = b < 0;
+  return (a << 1) | r;
+}
+
+unsigned int
+test_14 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 1) | r);
+}
+
+unsigned int
+test_15 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 11) | r);
+}
+
+unsigned int
+test_16 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 3) | r);
+}
+
+unsigned int
+test_17 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 4) | r);
+}
+
+unsigned int
+test_18 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 5) | r);
+}
+
+unsigned int
+test_19 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 6) | r);
+}
+
+unsigned int
+test_20 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 7) | r);
+}
+
+unsigned int
+test_21 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 8) | r);
+}
+
+unsigned int
+test_22 (unsigned int a, int b, int c)
+{
+  bool r = b != c;
+  return ((a << 31) | r);
+}
+
+unsigned int
+test_23 (unsigned int a, int b, int c)
+{
+  /* 1x shll, 1x rotcl  */
+  return (a >> 31) | (b << 13);
+}
+
+unsigned int
+test_24 (unsigned int a, unsigned int b)
+{
+  /* 1x shll, 1x rotcl  */
+  return (a >> 31) | (b << 1);
+}
+
+unsigned int
+test_25 (unsigned int a, unsigned int b)
+{
+  /* 1x shll, 1x rotcl  */
+  return (a >> 31) | (b << 3);
+}
+
+unsigned int
+test_26 (unsigned int a, unsigned int b)
+{
+  /* 1x shll, 1x rotcl  */
+  return (b << 3) | (a >> 31);
+}
+
+unsigned int
+test_27 (unsigned int a, unsigned int b)
+{
+  /* 1x shlr, 1x rotcl  */
+  return (a << 1) | ((b >> 4) & 1);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-9.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-9.c
new file mode 100644
index 000000000..8aa15df86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54089-9.c
@@ -0,0 +1,63 @@
+/* Check that the rotcr instruction is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "rotcl" 4 } } */
+/* { dg-final { scan-assembler-not "movt" } } */
+/* { dg-final { scan-assembler-not "or\t" } } */
+/* { dg-final { scan-assembler-not "rotl" } } */
+/* { dg-final { scan-assembler-not "and" } } */
+
+typedef char bool;
+
+int
+test_00 (int* a, int* b)
+{
+  int i;
+  int r = 0;
+  for (i = 0; i < 16; ++i)
+    {
+      bool t = a[i] == b[i];
+      r = (r << 1) | t;
+    }
+  return r;
+}
+
+int
+test_01 (int* a, int* b)
+{
+  int i;
+  int r = 0;
+  for (i = 0; i < 16; ++i)
+    {
+      bool t = a[i] == b[i];
+      r = (r << 2) | t;
+    }
+  return r;
+}
+
+int
+test_02 (int* a, int* b)
+{
+  int i;
+  int r = 0;
+  for (i = 0; i < 16; ++i)
+    {
+      bool t = a[i] == b[i];
+      r = (r << 3) | t;
+    }
+  return r;
+}
+
+int
+test_03 (const bool* a)
+{
+  int i;
+  int r = 0;
+  for (i = 0; i < 16; ++i)
+    {
+      bool t = a[i];
+      r = (r << 1) | (t & 1);
+    }
+  return r;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54236-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54236-1.c
new file mode 100644
index 000000000..f7568a92c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54236-1.c
@@ -0,0 +1,83 @@
+/* Tests to check the utilization of addc, subc and negc instructions in
+   special cases.  If everything works as expected we won't see any
+   movt instructions in these cases.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-times "addc" 4 } } */
+/* { dg-final { scan-assembler-times "subc" 3 } } */
+/* { dg-final { scan-assembler-times "sett" 5 } } */
+/* { dg-final { scan-assembler-times "negc" 1 } } */
+/* { dg-final { scan-assembler-not "movt" } } */
+
+int
+test_00 (int a, int b, int c, int d)
+{
+  /* 1x addc, 1x sett  */
+  return a + b + 1;
+}
+
+int
+test_01 (int a, int b, int c, int d)
+{
+  /* 1x addc  */
+  return a + (c == d);
+}
+
+int
+test_02 (int a, int b, int c, int d)
+{
+  /* 1x subc, 1x sett  */
+  return a - b - 1;
+}
+
+int
+test_03 (int a, int b, int c, int d)
+{
+  /* 1x subc  */
+  return a - (c == d);
+}
+
+int
+test_04 (int a, int b, int c, int d)
+{
+  /* 1x addc, 1x sett  */
+  return a + b + c + 1;
+}
+
+int
+test_05 (int a, int b, int c, int d)
+{
+  /* 1x subc, 1x sett  */
+  return a - b - c - 1;
+}
+
+int
+test_06 (int a, int b, int c, int d)
+{
+  /* 1x negc  */
+  return 0 - a - (b == c);
+}
+
+int
+test_07 (int *vec)
+{
+  /* Must not see a 'sett' or 'addc' here.
+     This is a case where combine tries to produce
+     'a + (0 - b) + 1' out of 'a - b + 1'.  */
+  int z = vec[0];
+  int vi = vec[1];
+  int zi = vec[2];
+
+  if (zi != 0 && z < -1)
+    vi -= (((vi >> 7) & 0x01) << 1) - 1;
+
+  return vi;
+}
+
+int
+test_08 (int a)
+{
+  /* 1x addc, 1x sett  */
+  return (a << 1) + 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54236-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54236-2.c
new file mode 100644
index 000000000..b3cf48c9d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54236-2.c
@@ -0,0 +1,270 @@
+/* Tests to check the utilization of the addc instruction in special cases.
+   If everything works as expected we won't see any movt instructions in
+   these cases.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-times "addc" 37 } } */
+/* { dg-final { scan-assembler-times "shlr" 23 } } */
+/* { dg-final { scan-assembler-times "shll" 14 } } */
+/* { dg-final { scan-assembler-times "add\t" 12 } } */
+/* { dg-final { scan-assembler-not "movt" } } */
+
+int
+test_000 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x addc
+  return a + (b & 1);
+}
+
+int
+test_001 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x addc
+  return a + b + (c & 1);
+}
+
+int
+test_002 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x add, 1x addc
+  return a + b + c + (d & 1);
+}
+
+int
+test_003 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x addc
+  return (b & 1) + a;
+}
+
+int
+test_004 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x addc
+  return a + (c & 1) + b;
+}
+
+int
+test_005 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x add, 1x addc
+  return a + b + (d & 1) + c;
+}
+
+int
+test_006 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x addc
+  return (c & 1) + a + b;
+}
+
+int
+test_007 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x add, 1x addc
+  return a + (d & 1) + b + c;
+}
+
+int
+test_008 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x add, 1x addc
+  return (d & 1) + a + b + c;
+}
+
+int
+test_009 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x addc
+  return a + b + (b & 1);
+}
+
+int
+test_010 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x addc
+  return a + (b & 1) + b;
+}
+
+int
+test_011 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x addc
+  return (b & 1) + a + b;
+}
+
+int
+test_012 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x add, 1x addc
+  return a + b + d + (b & 1);
+}
+
+int
+test_013 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x add, 1x addc
+  return a + d + (b & 1) + b;
+}
+
+int
+test_014 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x add, 1x addc
+  return a + (b & 1) + d + b;
+}
+
+int
+test_015 (int a, int c, int b, int d)
+{
+  // 1x shlr, 1x add, 1x addc
+  return (b & 1) + a + d + b;
+}
+
+int
+test_016 (int a, int b, int c, int d)
+{
+  // 1x shlr, 1x addc
+  return a + (a & 1);
+}
+
+int
+test_017 (int a, int b, int c, int d)
+{
+  // 1x shlr, 1x addc
+  return a + a + (a & 1);
+}
+
+int
+test_018 (int a, int b, int c, int d)
+{
+  // 1x shlr, 1x addc
+  return a + (a & 1) + a;
+}
+
+int
+test_019 (int a, int b, int c, int d)
+{
+  // 1x shlr, 1x addc
+  return (a & 1) + a + a;
+}
+
+int
+test_020 (int a, int b, int c, int d)
+{
+  // 1x shlr, 1x addc
+  return b + b + (a & 1);
+}
+
+int
+test_021 (int a, int b, int c, int d)
+{
+  // 1x shlr, 1x addc
+  return b + (a & 1) + b;
+}
+
+int
+test_022 (int a, int b, int c, int d)
+{
+  // 1x shlr, 1x addc
+  return (a & 1) + b + b;
+}
+
+int
+test_023 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return a + ((b >> 31) & 1);
+}
+
+int
+test_024 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return ((b >> 31) & 1) + a;
+}
+
+int
+test_025 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return ((a >> 31) & 1) + a;
+}
+
+int
+test_026 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return a + ((a >> 31) & 1);
+}
+
+int
+test_027 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return a + b + ((c >> 31) & 1);
+}
+
+int
+test_028 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return a + ((c >> 31) & 1) + b;
+}
+
+int
+test_029 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return ((c >> 31) & 1) + a + b;
+}
+
+int
+test_030 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc, 1x add
+  return a + b + c + ((d >> 31) & 1);
+}
+
+int
+test_031 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc, 1x add
+  return a + b + ((d >> 31) & 1) + c;
+}
+
+int
+test_032 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc, 1x add
+  return a + ((d >> 31) & 1) + b + c;
+}
+
+int
+test_033 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc, 1x add
+  return ((d >> 31) & 1) + a + b + c;
+}
+
+int
+test_034 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return a + a + ((d >> 31) & 1);
+}
+
+int
+test_035 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return a + ((d >> 31) & 1) + a;
+}
+
+int
+test_036 (int a, int b, int c, int d)
+{
+  // 1x shll, 1x addc
+  return ((d >> 31) & 1) + a + a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54386.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54386.c
new file mode 100644
index 000000000..ec52d8940
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54386.c
@@ -0,0 +1,41 @@
+/* Check that the inlined mem load is not handled as unaligned load.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-not "shll|extu|or" } } */
+
+static inline int
+readint0 (int* x)
+{
+  return *x;
+}
+
+int
+test0 (int* x)
+{
+  return readint0 (x);
+}
+
+inline int
+readint1 (int* x)
+{
+  return *x;
+}
+
+int
+test1 (int* x)
+{
+  return readint1 (x);
+}
+
+static int
+readint2 (int* x)
+{
+  return *x;
+}
+
+int
+test2 (int* x)
+{
+  return readint2 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-1.c
new file mode 100644
index 000000000..bd402b3a0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-1.c
@@ -0,0 +1,15 @@
+/* Verify that the delay slot is stuffed with register pop insns for normal
+   (i.e. not interrupt handler) function returns.  If everything goes as
+   expected we won't see any nop insns.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-not "nop" } } */
+
+int test00 (int a, int b);
+
+int
+test01 (int a, int b, int c, int d)
+{
+  return test00 (a, b) + c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-2.c
new file mode 100644
index 000000000..05592ddbf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-2.c
@@ -0,0 +1,15 @@
+/* Verify that the delay slot is not stuffed with register pop insns for
+   interrupt handler function returns on SH1* and SH2* targets, where the
+   rte insn uses the stack pointer.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2*" } }  */
+/* { dg-final { scan-assembler-times "nop" 1 } } */
+
+int test00 (int a, int b);
+
+int __attribute__ ((interrupt_handler))
+test01 (int a, int b, int c, int d)
+{
+  return test00 (a, b) + c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-3.c
new file mode 100644
index 000000000..5d6a75a70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-3.c
@@ -0,0 +1,12 @@
+/* Verify that the rte delay slot is not stuffed with register pop insns
+   which touch the banked registers r0..r7 on SH3* and SH4* targets.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } }  */
+/* { dg-final { scan-assembler-times "nop" 1 } } */
+
+int __attribute__ ((interrupt_handler))
+test00 (int a, int b, int c, int d)
+{
+  return a + b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-4.c
new file mode 100644
index 000000000..78fb9096e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54602-4.c
@@ -0,0 +1,15 @@
+/* Verify that the delay slot is stuffed with register pop insns on SH3* and
+   SH4* targets, where the stack pointer is not used by the rte insn.  If
+   everything works out, we won't see a nop insn.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } }  */
+/* { dg-final { scan-assembler-not "nop" } } */
+
+int test00 (int a, int b);
+
+int __attribute__ ((interrupt_handler))
+test01 (int a, int b, int c, int d)
+{
+  return test00 (a, b) + c;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54680.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54680.c
new file mode 100644
index 000000000..9171eeaf6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54680.c
@@ -0,0 +1,66 @@
+/* Verify that the fsca input value is not converted to float and then back
+   to int.  Notice that we can't count just "lds" insns because mode switches
+   use "lds.l".  */
+/* { dg-do compile }  */
+/* { dg-options "-O2 -mfsca -funsafe-math-optimizations" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fsca" 7 } } */
+/* { dg-final { scan-assembler-times "shad" 1 } } */
+/* { dg-final { scan-assembler-times "lds\t" 6 } } */
+/* { dg-final { scan-assembler-times "fmul" 2 } } */
+/* { dg-final { scan-assembler-times "ftrc" 1 } } */
+
+#include <math.h>
+
+static const float pi = 3.14159265359f;
+
+float
+test00 (int x)
+{
+  /* 1x shad, 1x lds, 1x fsca  */
+  return sinf ( (x >> 8) * (2*pi) / (1 << 16));
+}
+
+float
+test01 (int x)
+{
+  /* 1x lds, 1x fsca  */
+  return sinf (x * (2*pi) / 65536);
+}
+
+float
+test02 (int x)
+{
+  /* 1x lds, 1x fsca  */
+  return sinf (x * (2*pi / 65536));
+}
+
+float
+test03 (int x)
+{
+  /* 1x lds, 1x fsca  */
+  float scale = 2*pi / 65536;
+  return sinf (x * scale);
+}
+
+float
+test04 (int x)
+{
+  /* 1x lds, 1x fsca  */
+  return cosf (x / 65536.0f * 2*pi);
+}
+
+float
+test05 (int x)
+{
+  /* 1x lds, 1x fsca, 1x fmul  */
+  float scale = 2*pi / 65536;
+  return sinf (x * scale) * cosf (x * scale);
+}
+
+float
+test_06 (float x)
+{
+  /* 1x fmul, 1x ftrc, 1x fsca  */
+  return sinf (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54685.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54685.c
new file mode 100644
index 000000000..111a12013
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54685.c
@@ -0,0 +1,58 @@
+/* Check that a comparison 'unsigned int <= 0x7FFFFFFF' results in code
+   utilizing the cmp/pz instruction.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-not "not\[ \t\]" } } */
+/* { dg-final { scan-assembler-times "cmp/pz" 7 } } */
+/* { dg-final { scan-assembler-times "shll" 1 } } */
+/* { dg-final { scan-assembler-times "movt" 4 } } */
+
+int
+test_00 (unsigned int a)
+{
+  return !(a > 0x7FFFFFFF);
+}
+
+int
+test_01 (unsigned int a)
+{
+  return !(a > 0x7FFFFFFF) ? -5 : 10;
+}
+
+int
+test_02 (unsigned int a)
+{
+  /* 1x shll, 1x movt  */
+  return a >= 0x80000000;
+}
+
+int
+test_03 (unsigned int a)
+{
+  return a >= 0x80000000 ? -5 : 10;
+}
+
+int
+test_04 (unsigned int a)
+{
+  return a <= 0x7FFFFFFF;
+}
+
+int
+test_05 (unsigned int a)
+{
+  return a <= 0x7FFFFFFF ? -5 : 10;
+}
+
+int
+test_06 (unsigned int a)
+{
+  return a < 0x80000000;
+}
+
+int
+test_07 (unsigned int a)
+{
+  return a < 0x80000000 ? -5 : 10;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-1.c
new file mode 100644
index 000000000..4437511cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-1.c
@@ -0,0 +1,20 @@
+/* Check that the __builtin_thread_pointer and __builtin_set_thread_pointer
+   built-in functions result in gbr store / load instructions.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "ldc" 1 } } */
+/* { dg-final { scan-assembler-times "stc" 1 } } */
+/* { dg-final { scan-assembler-times "gbr" 2 } } */
+
+void*
+test00 (void)
+{
+  return __builtin_thread_pointer ();
+}
+
+void
+test01 (void* p)
+{
+  __builtin_set_thread_pointer (p);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-2.c
new file mode 100644
index 000000000..4a3561a56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-2.c
@@ -0,0 +1,259 @@
+/* Check that thread pointer relative memory accesses are converted to
+   gbr displacement address modes.  If we see a gbr register store
+   instruction something is not working properly.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "stc\tgbr" 0 } } */
+
+/* ---------------------------------------------------------------------------
+  Simple GBR load.
+*/
+#define func(name, rettype, type, disp)\
+  rettype \
+  name ## _tp_load (void) \
+  { \
+    type* tp = (type*)__builtin_thread_pointer (); \
+    return tp[disp]; \
+  }
+
+func (test00, int, int, 0)
+func (test01, int, int, 5)
+func (test02, int, int, 255)
+
+func (test03, int, short, 0)
+func (test04, int, short, 5)
+func (test05, int, short, 255)
+
+func (test06, int, char, 0)
+func (test07, int, char, 5)
+func (test08, int, char, 255)
+
+func (test09, int, unsigned int, 0)
+func (test10, int, unsigned int, 5)
+func (test11, int, unsigned int, 255)
+
+func (test12, int, unsigned short, 0)
+func (test13, int, unsigned short, 5)
+func (test14, int, unsigned short, 255)
+
+func (test15, int, unsigned char, 0)
+func (test16, int, unsigned char, 5)
+func (test17, int, unsigned char, 255)
+
+func (test18, long long, long long, 0)
+func (test19, long long, long long, 5)
+func (test20, long long, long long, 127)
+
+func (test21, long long, unsigned long long, 0)
+func (test22, long long, unsigned long long, 5)
+func (test23, long long, unsigned long long, 127)
+
+#undef func
+
+/* ---------------------------------------------------------------------------
+  Simple GBR store.
+*/
+#define func(name, argtype, type, disp)\
+  void \
+  name ## _tp_store (argtype a) \
+  { \
+    type* tp = (type*)__builtin_thread_pointer (); \
+    tp[disp] = (type)a; \
+  }
+
+func (test00, int, int, 0)
+func (test01, int, int, 5)
+func (test02, int, int, 255)
+
+func (test03, int, short, 0)
+func (test04, int, short, 5)
+func (test05, int, short, 255)
+
+func (test06, int, char, 0)
+func (test07, int, char, 5)
+func (test08, int, char, 255)
+
+func (test09, int, unsigned int, 0)
+func (test10, int, unsigned int, 5)
+func (test11, int, unsigned int, 255)
+
+func (test12, int, unsigned short, 0)
+func (test13, int, unsigned short, 5)
+func (test14, int, unsigned short, 255)
+
+func (test15, int, unsigned char, 0)
+func (test16, int, unsigned char, 5)
+func (test17, int, unsigned char, 255)
+
+func (test18, long long, long long, 0)
+func (test19, long long, long long, 5)
+func (test20, long long, long long, 127)
+
+func (test21, long long, unsigned long long, 0)
+func (test22, long long, unsigned long long, 5)
+func (test23, long long, unsigned long long, 127)
+
+#undef func
+
+/* ---------------------------------------------------------------------------
+  Arithmetic on the result of a GBR load.
+*/
+#define func(name, retargtype, type, disp, op, opname)\
+  retargtype \
+  name ## _tp_load_arith_ ##opname (retargtype a) \
+  { \
+    type* tp = (type*)__builtin_thread_pointer (); \
+    return tp[disp] op a; \
+  }
+
+#define funcs(op, opname) \
+  func (test00, int, int, 0, op, opname) \
+  func (test01, int, int, 5, op, opname) \
+  func (test02, int, int, 255, op, opname) \
+  func (test03, int, short, 0, op, opname) \
+  func (test04, int, short, 5, op, opname) \
+  func (test05, int, short, 255, op, opname) \
+  func (test06, int, char, 0, op, opname) \
+  func (test07, int, char, 5, op, opname) \
+  func (test08, int, char, 255, op, opname) \
+  func (test09, int, unsigned int, 0, op, opname) \
+  func (test10, int, unsigned int, 5, op, opname) \
+  func (test11, int, unsigned int, 255, op, opname) \
+  func (test12, int, unsigned short, 0, op, opname) \
+  func (test13, int, unsigned short, 5, op, opname) \
+  func (test14, int, unsigned short, 255, op, opname) \
+  func (test15, int, unsigned char, 0, op, opname) \
+  func (test16, int, unsigned char, 5, op, opname) \
+  func (test17, int, unsigned char, 255, op, opname) \
+  func (test18, long long, long long, 0, op, opname) \
+  func (test19, long long, long long, 5, op, opname) \
+  func (test20, long long, long long, 127, op, opname) \
+  func (test21, long long, unsigned long long, 0, op, opname) \
+  func (test22, long long, unsigned long long, 5, op, opname) \
+  func (test23, long long, unsigned long long, 127, op, opname) \
+
+funcs (+, plus)
+funcs (-, minus)
+funcs (*, mul)
+funcs (&, and)
+funcs (|, or)
+funcs (^, xor)
+
+#undef funcs
+#undef func
+
+/* ---------------------------------------------------------------------------
+  Arithmetic of the result of two GBR loads.
+*/
+#define func(name, rettype, type, disp0, disp1, op, opname)\
+  rettype \
+  name ## _tp_load_load_arith_ ##opname (void) \
+  { \
+    type* tp = (type*)__builtin_thread_pointer (); \
+    return tp[disp0] op tp[disp1]; \
+  }
+
+#define funcs(op, opname) \
+  func (test00, int, int, 0, 5, op, opname) \
+  func (test02, int, int, 1, 255, op, opname) \
+  func (test03, int, short, 0, 5, op, opname) \
+  func (test05, int, short, 1, 255, op, opname) \
+  func (test06, int, char, 0, 5, op, opname) \
+  func (test08, int, char, 1, 255, op, opname) \
+  func (test09, int, unsigned int, 0, 5, op, opname) \
+  func (test11, int, unsigned int, 1, 255, op, opname) \
+  func (test12, int, unsigned short, 0, 5, op, opname) \
+  func (test14, int, unsigned short, 1, 255, op, opname) \
+  func (test15, int, unsigned char, 0, 5, op, opname) \
+  func (test17, int, unsigned char, 1, 255, op, opname) \
+  func (test18, long long, long long, 0, 5, op, opname) \
+  func (test19, long long, long long, 1, 127, op, opname) \
+  func (test20, long long, unsigned long long, 0, 5, op, opname) \
+  func (test21, long long, unsigned long long, 1, 127, op, opname) \
+
+funcs (+, plus)
+funcs (-, minus)
+funcs (*, mul)
+funcs (&, and)
+funcs (|, or)
+funcs (^, xor)
+
+#undef funcs
+#undef func
+
+/* ---------------------------------------------------------------------------
+  GBR load GBR store copy.
+*/
+
+#define func(name, type, disp0, disp1)\
+  void \
+  name ## _tp_copy (void) \
+  { \
+    type* tp = (type*)__builtin_thread_pointer (); \
+    tp[disp0] = tp[disp1]; \
+  }
+
+func (test00, int, 0, 5)
+func (test02, int, 1, 255)
+func (test03, short, 0, 5)
+func (test05, short, 1, 255)
+func (test06, char, 0, 5)
+func (test08, char, 1, 255)
+func (test09, unsigned int, 0, 5)
+func (test11, unsigned int, 1, 255)
+func (test12, unsigned short, 0, 5)
+func (test14, unsigned short, 1, 255)
+func (test15, unsigned char, 0, 5)
+func (test17, unsigned char, 1, 255)
+func (test18, long long, 0, 5)
+func (test19, long long, 1, 127)
+func (test20, unsigned long long, 0, 5)
+func (test21, unsigned long long, 1, 127)
+
+#undef func
+
+/* ---------------------------------------------------------------------------
+  GBR load, arithmetic, GBR store
+*/
+
+#define func(name, argtype, type, disp, op, opname)\
+  void \
+  name ## _tp_load_arith_store_ ##opname (argtype a) \
+  { \
+    type* tp = (type*)__builtin_thread_pointer (); \
+    tp[disp] op a; \
+  }
+
+#define funcs(op, opname) \
+  func (test00, int, int, 0, op, opname) \
+  func (test01, int, int, 5, op, opname) \
+  func (test02, int, int, 255, op, opname) \
+  func (test03, int, short, 0, op, opname) \
+  func (test04, int, short, 5, op, opname) \
+  func (test05, int, short, 255, op, opname) \
+  func (test06, int, char, 0, op, opname) \
+  func (test07, int, char, 5, op, opname) \
+  func (test08, int, char, 255, op, opname) \
+  func (test09, int, unsigned int, 0, op, opname) \
+  func (test10, int, unsigned int, 5, op, opname) \
+  func (test11, int, unsigned int, 255, op, opname) \
+  func (test12, int, unsigned short, 0, op, opname) \
+  func (test13, int, unsigned short, 5, op, opname) \
+  func (test14, int, unsigned short, 255, op, opname) \
+  func (test15, int, unsigned char, 0, op, opname) \
+  func (test16, int, unsigned char, 5, op, opname) \
+  func (test17, int, unsigned char, 255, op, opname) \
+  func (test18, long long, long long, 0, op, opname) \
+  func (test19, long long, long long, 5, op, opname) \
+  func (test20, long long, long long, 127, op, opname) \
+  func (test21, long long, unsigned long long, 0, op, opname) \
+  func (test22, long long, unsigned long long, 5, op, opname) \
+  func (test23, long long, unsigned long long, 127, op, opname) \
+
+funcs (+=, plus)
+funcs (-=, minus)
+funcs (*=, mul)
+funcs (&=, and)
+funcs (|=, or)
+funcs (^=, xor)
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-3.c
new file mode 100644
index 000000000..678fb3954
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-3.c
@@ -0,0 +1,69 @@
+/* Check that these thread relative memory accesses play along with
+   surrounding code.
+   These should be moved to C torture tests once there are target
+   independent thread_pointer built-in functions available.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+
+int
+test00 (void* p, int x)
+{
+  int* tcb = (int*)__builtin_thread_pointer ();
+  int r = tcb[4];
+
+  __builtin_set_thread_pointer (p);
+
+  tcb = (int*)__builtin_thread_pointer ();
+  return tcb[255] + r;
+}
+
+int
+test01 (void)
+{
+  unsigned short* tcb = (unsigned short*)__builtin_thread_pointer ();
+  return tcb[500];
+}
+
+void
+test02 (int* x, int a, int b)
+{
+  int* tcb = (int*)__builtin_thread_pointer ();
+  tcb[50] = a;
+
+  __builtin_set_thread_pointer (x);
+  
+  tcb = (int*)__builtin_thread_pointer ();
+  tcb[40] = b;
+}
+
+int
+test03 (const int* x, int c)
+{
+  volatile int* tcb = (volatile int*)__builtin_thread_pointer ();
+
+  int s = 0;
+  int i;
+  for (i = 0; i < c; ++i)
+    s ^= x[i] + tcb[40];
+
+  return s;
+}
+
+int
+test04 (const int* x, int c, int** xx, int d)
+{
+  int s = 0;
+  int i;
+  for (i = 0; i < c; ++i)
+  {
+    volatile int* tcb = (volatile int*)__builtin_thread_pointer ();
+    tcb[20] = s;
+ 
+   __builtin_set_thread_pointer (xx[i]);
+
+    tcb = (volatile int*)__builtin_thread_pointer ();
+    s ^= x[i] + tcb[40] + d;
+  }
+  return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-4.c
new file mode 100644
index 000000000..d21828196
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr54760-4.c
@@ -0,0 +1,19 @@
+/* Check that the GBR address optimization does not combine a gbr store
+   and its use when a function call is in between, when GBR is a call used
+   register, i.e. it is invalidated by function calls.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -fcall-used-gbr" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler "stc\tgbr" } } */
+
+extern int test00 (void);
+int
+test01 (int x)
+{
+  /* We must see a stc gbr,rn before the function call, because
+     a function call could modify the gbr.  In this case the user requests
+     the old gbr value, before the function call.  */
+  int* p = (int*)__builtin_thread_pointer ();
+  p[5] = test00 ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55146.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55146.c
new file mode 100644
index 000000000..91f09359d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55146.c
@@ -0,0 +1,50 @@
+/* Check that the 'extu.b' instruction is generated for short jump tables.  */
+/* { dg-do compile }  */
+/* { dg-options "-Os" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler "extu.b" } } */
+
+int
+test (int arg)
+{
+  int rc;
+  switch (arg)
+    {
+    case 0:
+      asm ("nop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "nop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "mov r4,%0"
+	   : "=r" (rc)
+	   : "r" (arg));
+      break;
+    case 1:
+      asm ("nop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "nop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "mov r5,%0"
+	   : "=r" (rc)
+	   : "r" (arg));
+      break;
+    case 2:
+      asm ("nop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "nop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "mov r6,%0"
+	   : "=r" (rc)
+	   : "r" (arg));
+      break;
+    case 3:
+      asm ("nop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "nop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "mov r7,%0"
+	   : "=r" (rc)
+	   : "r" (arg));
+      break;
+    case 4:
+      asm ("nop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "nop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\tnop\n\t"
+	   "mov r8,%0"
+	   : "=r" (rc)
+	   : "r" (arg));
+      break;
+    }
+  return rc;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55160.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55160.c
new file mode 100644
index 000000000..dca15c9b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55160.c
@@ -0,0 +1,25 @@
+/* Check that the decrement-and-test instruction is generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } }  */
+/* { dg-final { scan-assembler-times "dt\tr" 2 } } */
+
+int
+test_00 (int* x, int c)
+{
+  int s = 0;
+  int i;
+  for (i = 0; i < c; ++i)
+    s += x[i];
+  return s;
+}
+
+int
+test_01 (int* x, int c)
+{
+  int s = 0;
+  int i;
+  for (i = 0; i < c; ++i)
+    s += *--x;
+  return s;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-1.c
new file mode 100644
index 000000000..b77c5e10e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-1.c
@@ -0,0 +1,87 @@
+/* Verify that the SH2A clips and clipu instructions are generated as
+   expected.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "clips.b" 2 } } */
+/* { dg-final { scan-assembler-times "clips.w" 2 } } */
+/* { dg-final { scan-assembler-times "clipu.b" 2 } } */
+/* { dg-final { scan-assembler-times "clipu.w" 2 } } */
+
+static inline int
+min (int a, int b)
+{
+  return a < b ? a : b;
+}
+
+static inline int
+max (int a, int b)
+{
+  return a < b ? b : a;
+}
+
+int
+test_00 (int a)
+{
+  /* 1x clips.b  */
+  return max (-128, min (127, a));
+}
+
+int
+test_01 (int a)
+{
+  /* 1x clips.b  */
+  return min (127, max (-128, a));
+}
+
+int
+test_02 (int a)
+{
+  /* 1x clips.w  */
+  return max (-32768, min (32767, a));
+}
+
+int
+test_03 (int a)
+{
+  /* 1x clips.w  */
+  return min (32767, max (-32768, a));
+}
+
+unsigned int
+test_04 (unsigned int a)
+{
+  /* 1x clipu.b  */
+  return a > 255 ? 255 : a;
+}
+
+unsigned int
+test_05 (unsigned int a)
+{
+  /* 1x clipu.b  */
+  return a >= 255 ? 255 : a;
+}
+
+unsigned int
+test_06 (unsigned int a)
+{
+  /* 1x clipu.w  */
+  return a > 65535 ? 65535 : a;
+}
+
+unsigned int
+test_07 (unsigned int a)
+{
+  /* 1x clipu.w  */
+  return a >= 65535 ? 65535 : a;
+}
+
+void
+test_08 (unsigned short a, unsigned short b, unsigned int* r)
+{
+  /* Must not see a clip insn here -- it is not needed.  */
+  unsigned short x = a + b;
+  if (x > 65535)
+    x = 65535;
+  *r = x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-2.c
new file mode 100644
index 000000000..34f706327
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-2.c
@@ -0,0 +1,35 @@
+/* Verify that for SH2A smax/smin -> cbranch conversion is done properly
+   if the clips insn is not used and the expected comparison insns are
+   generated.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "cmp/pl" 4 } } */
+
+int
+test_00 (int a)
+{
+  /* 1x cmp/pl  */
+  return a >= 0 ? a : 0;
+}
+
+int
+test_01 (int a)
+{
+  /* 1x cmp/pl  */
+  return a <= 0 ? a : 0;
+}
+
+int
+test_02 (int a)
+{
+  /* 1x cmp/pl  */
+  return a < 1 ? 1 : a;
+}
+
+int
+test_03 (int a)
+{
+  /* 1x cmp/pl  */
+  return a < 1 ? a : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-3.c
new file mode 100644
index 000000000..57c2f403e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr55303-3.c
@@ -0,0 +1,15 @@
+/* Verify that the special case (umin (reg const_int 1)) results in the
+   expected instruction sequence on SH2A.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "tst" 1 } } */
+/* { dg-final { scan-assembler-times "movrt" 1 } } */
+
+unsigned int
+test_00 (unsigned int a)
+{
+  /* 1x tst
+     1x movrt  */
+  return a > 1 ? 1 : a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr56547-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr56547-1.c
new file mode 100644
index 000000000..0c7c97e81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr56547-1.c
@@ -0,0 +1,19 @@
+/* Verify that the fmac insn is used for the expression 'a * b + a' and
+   'a * a + a'.
+   This assumes that the default compiler setting is -ffp-contract=fast.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmac" 2 } } */
+
+float
+test_00 (float a, float b)
+{
+  return a * b + a;
+}
+
+float
+test_01 (float a)
+{
+  return a * a + a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr56547-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr56547-2.c
new file mode 100644
index 000000000..2d36fa9c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr56547-2.c
@@ -0,0 +1,18 @@
+/* Verify that the fmac insn is used for the expression 'a * b + a' and
+   'a * a + a' when -ffast-math is specified.  */
+/* { dg-do compile }  */
+/* { dg-options "-O1 -ffast-math" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "fmac" 2 } } */
+
+float
+test_00 (float a, float b)
+{
+  return a * b + a;
+}
+
+float
+test_01 (float a)
+{
+  return a * a + a;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pr6526.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr6526.c
new file mode 100644
index 000000000..a49b877b5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pr6526.c
@@ -0,0 +1,64 @@
+/* Check that the XF registers are not clobbered by an integer division
+   that is done using double precision FPU division.  */
+/* { dg-do run }  */
+/* { dg-options "-O1 -mdiv=call-fp" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4*-single" "-m4*-single-only" } }  */
+
+#include <assert.h>
+#include <stdlib.h>
+
+extern void __set_fpscr (int);
+
+void
+write_xf0 (float* f)
+{
+  __asm__ __volatile__ ("frchg; fmov.s @%0,fr0; frchg" : : "r" (f) : "memory");
+}
+ 
+void
+read_xf0 (float* f)
+{
+  __asm__ __volatile__ ("frchg; fmov.s fr0,@%0; frchg" : : "r" (f) : "memory");
+}
+
+int __attribute__ ((noinline))
+test_00 (int a, int b)
+{
+  return a / b;
+}
+
+unsigned int __attribute__ ((noinline))
+test_01 (unsigned a, unsigned b)
+{
+  return a / b;
+}
+
+int __attribute__ ((noinline))
+test_02 (int x)
+{
+  return x & 0;
+}
+
+int
+main (void)
+{
+  float test_value;
+  int r = 0;
+
+  /* Set FPSCR.FR to 1.  */
+  __set_fpscr (0x200000);
+
+  test_value = 123;
+  write_xf0 (&test_value);
+  r += test_00 (40, 4);
+  read_xf0 (&test_value);
+  assert (test_value == 123);
+
+  test_value = 321;
+  write_xf0 (&test_value);
+  r += test_01 (50, 5);
+  read_xf0 (&test_value);
+  assert (test_value == 321);
+
+  return test_02 (r);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c
new file mode 100644
index 000000000..e1d880d33
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c
@@ -0,0 +1,23 @@
+/* A call will clobber all call-saved registers.
+   If #pragma nosave_low_regs is specified, do not save/restore r0..r7.
+   (On SH3* and SH4* r0..r7 are banked)
+   One of these registers will also do fine to hold the function address.
+   Call-saved registers r8..r13 also don't need to be restored.  */
+/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1*" "-m2*" "-m5*" } { "" } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler-times "rte" 1 } }  */
+/* { dg-final { scan-assembler-not "\[^f\]r\[0-9\]\[ \t\]*," } }  */
+/* { dg-final { scan-assembler-not "\[^f\]r\[89\]" } }  */
+/* { dg-final { scan-assembler-not "\[^f\]r1\[,0-3\]" } }  */
+/* { dg-final { scan-assembler-times "macl" 2 } }  */
+
+extern void foo (void);
+
+#pragma interrupt
+#pragma nosave_low_regs
+void
+isr (void)
+{
+  foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c
new file mode 100644
index 000000000..6dbd8e7c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trap-exit.c
@@ -0,0 +1,24 @@
+/* Check whether trapa is generated only for an ISR.  */
+/* { dg-do compile }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler-times "trapa\[ \t\]\[ \t\]*#4" 1 } }  */
+
+#pragma interrupt
+void isr (void) __attribute__ ((trap_exit (4)));
+
+void
+isr (void)
+{
+}
+
+void
+delay (int a)
+{
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c
new file mode 100644
index 000000000..cc57014dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c
@@ -0,0 +1,19 @@
+/* Check that no interrupt-specific register saves are generated.  */
+/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler-times "rte" 1 } }  */
+/* { dg-final { scan-assembler-not "r\[0-7\]\[ \t,\]\[^\n\]*r15" } }  */
+/* { dg-final { scan-assembler-not "@r15\[^\n\]*r\[0-7\]\n" } }  */
+/* { dg-final { scan-assembler-not "r\[8-9\]" } }  */
+/* { dg-final { scan-assembler-not "r1\[,0-3\]" } }  */
+/* { dg-final { scan-assembler-not "macl" } }  */
+
+extern void foo (void);
+
+#pragma trapa
+void
+isr (void)
+{
+  foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c
new file mode 100644
index 000000000..9a23b976f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c
@@ -0,0 +1,24 @@
+/* Check that no interrupt-specific register saves are generated.
+   The function call will require to load the address first into a register,
+   then use that for a jsr or jmp.  It will also need to load a constant
+   address in order to load fpscr.  */
+/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-options "-O" }  */
+/* { dg-final { scan-assembler-times "rte" 1 } }  */
+/* { dg-final { scan-assembler-times "r\[0-7\]\n" 3 } }  */
+/* { dg-final { scan-assembler-not "r\[8-9\]" } }  */
+/* { dg-final { scan-assembler-not "r1\[,0-3\]" } }  */
+/* { dg-final { scan-assembler-not "macl" } }  */
+
+/* Expect that fpscr needs to be saved, loaded and restored.  */
+/* { dg-final { scan-assembler-times "\[^_\]fpscr" 3 } }  */
+
+extern void foo (void);
+
+#pragma trapa
+void
+isr (void)
+{
+  foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/prefetch.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/prefetch.c
new file mode 100644
index 000000000..fb580bde8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/prefetch.c
@@ -0,0 +1,35 @@
+/* Testcase to check generation of a SH4 and SH2A operand cache prefetch
+   instruction PREF @Rm.  */
+/* { dg-do assemble }  */
+/* { dg-options "-O0" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m3*" "-m4*" } }  */
+/* { dg-final { scan-assembler "pref"} }  */
+
+void
+opt (void)
+{
+  int *p, wk;
+  int data[100];
+
+  /* data prefetch , instructions hit the cache. */
+
+  __builtin_prefetch (&data[0], 0, 0);
+  __builtin_prefetch (&data[0], 0, 1);
+  __builtin_prefetch (&data[0], 0, 2);
+  __builtin_prefetch (&data[0], 0, 3);
+  __builtin_prefetch (&data[0], 1, 0);
+  __builtin_prefetch (&data[0], 1, 1);
+  __builtin_prefetch (&data[0], 1, 2);
+  __builtin_prefetch (&data[0], 1, 3);
+
+
+  for (p = &data[0]; p < &data[9]; p++)
+    {
+      if (*p > *(p + 1))
+        {
+          wk = *p;
+          *p = *(p + 1);
+          *(p + 1) = wk;
+        }
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/rte-delay-slot.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/rte-delay-slot.c
new file mode 100644
index 000000000..48f1b13b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/rte-delay-slot.c
@@ -0,0 +1,33 @@
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m1 -m2*" }  */
+/* { dg-final { scan-assembler-not "\trte\t\n\tmov.l\t@r15\\+" } } */
+
+/* This test checks if the compiler generates a pop instruction
+   in the delay slot after rte.  For the sh and sh2, the rte
+   instruction reads the return pc from the stack and any pop
+   in the delay slot crashes the hardware.
+
+   Incorrect code generated
+        mov.l   @r15+,r1
+        rte
+        mov.l   @r15+,r14
+
+   The right code should be
+
+        mov.l   @r15+,r1
+        mov.l   @r15+,r14
+        rte
+        nop
+*/
+void INT_MTU2_1_TGIA1 (void)
+  __attribute__ ((interrupt_handler));
+void
+INT_MTU2_1_TGIA1 (void)
+{
+  volatile int i = 0;
+  volatile int x, y;
+
+  for (i = 0; i < 10; i++)
+    y = y + x;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c
new file mode 100644
index 000000000..f8c2ffef4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh-relax-vxworks.c
@@ -0,0 +1,5 @@
+/* Check that -mrelax produces the correct error message.  */
+/* { dg-do compile { target { sh-*-vxworks* && nonpic } } } */
+/* { dg-error "-mrelax is only supported for RTP PIC" "" { target *-*-* } 0 } */
+/* { dg-options "-O1 -mrelax" } */
+int x;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh-relax.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh-relax.c
new file mode 100644
index 000000000..54422de46
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh-relax.c
@@ -0,0 +1,41 @@
+/* Check that -mrelax works.  */
+/* { dg-do run { target { { sh-*-* sh?-*-* } && { ! { sh*-*-vxworks* && nonpic } } } } } */
+/* { dg-options "-O1 -mrelax" } */
+
+extern void abort (void);
+extern int qwerty (int);
+
+int
+f (int i)
+{
+  return qwerty (i) + 1;
+}
+
+int
+qwerty (int i)
+{
+  switch (i)
+    {
+    case 1:
+      return 'q';
+    case 2:
+      return 'w';
+    case 3:
+      return 'e';
+    case 4:
+      return 'r';
+    case 5:
+      return 't';
+    case 6:
+      return 'y';
+    }
+}
+
+int
+main ()
+{
+  if (f (1) != 'q' + 1 || f (2) != 'w' + 1 || f (3) != 'e' + 1
+      || f(4) != 'r' + 1 || f (5) != 't' + 1 || f (6) != 'y' + 1)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh.exp b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh.exp
new file mode 100644
index 000000000..ac428cde5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2007-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a sh target.
+if ![istarget sh*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-band.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-band.c
new file mode 100644
index 000000000..a5096262c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-band.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BAND.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble }  */
+/* { dg-options "-O1 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "band.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BAND.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 & USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 & USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 & USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 & USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  &  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  &  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  &  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 &  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  &  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  &  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 &  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 &= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  &= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  &= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a & USRSTR.ICR0.BIT.BIT1;
+  a = a & USRSTR.ICR0.BIT.BIT4;
+  a = a & USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bclr.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bclr.c
new file mode 100644
index 000000000..ab1e3ddab
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bclr.c
@@ -0,0 +1,57 @@
+/* Testcase to check generation of a SH2A specific instruction
+   'BCLR #imm3,Rn'.  */
+/* { dg-do assemble }  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BCLR #imm3,Rn" only
+   on using optimization option "-O1" and above.  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b & ~1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b & ~2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b & ~4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b & ~8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b & ~16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b & ~32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b & ~64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b & ~128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x &= 0xFE;
+  x &= 0xFD;
+  x &= 0xFB;
+  x &= 0xF7;
+  x &= 0xEF;
+  x &= 0xDF;
+  x &= 0xBF;
+  x &= 0x7F;
+
+  if (!a2 ())
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c
new file mode 100644
index 000000000..9c99c5929
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bclrmem.c
@@ -0,0 +1,55 @@
+/* Testcase to check generation of a SH2A specific instruction
+   "BCLR #imm3,@(disp12,Rn)".  */
+/* { dg-do assemble }  */
+/* { dg-options "-O2 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bclr"} }  */
+/* { dg-final { scan-assembler "bclr.b"} }  */
+
+volatile union un_paddr
+{
+  unsigned char BYTE;
+  struct
+  {
+    unsigned char B15:1;
+    unsigned char B14:1;
+    unsigned char B13:1;
+    unsigned char B12:1;
+    unsigned char B11:1;
+    unsigned char B10:1;
+    unsigned char B9:1;
+    unsigned char B8:1;
+    unsigned char B7:1;
+    unsigned char B6:1;
+    unsigned char B5:1;
+    unsigned char B4:1;
+    unsigned char B3:1;
+    unsigned char B2:1;
+    unsigned char B1:1;
+    unsigned char B0:1;
+  }
+  BIT;
+}
+PADDR;
+
+int
+main ()
+{
+  PADDR.BIT.B0 = 0;
+  PADDR.BIT.B3 = 0;
+  PADDR.BIT.B6 = 0;
+
+  PADDR.BIT.B1 &= 0;
+  PADDR.BIT.B4 &= 0;
+  PADDR.BIT.B7 &= 0;
+
+  PADDR.BIT.B10 = 0;
+  PADDR.BIT.B13 = 0;
+  PADDR.BIT.B15 = 0;
+
+  PADDR.BIT.B9 &= 0;
+  PADDR.BIT.B12 &= 0;
+  PADDR.BIT.B14 &= 0;
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bld.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bld.c
new file mode 100644
index 000000000..d0c74c9c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bld.c
@@ -0,0 +1,43 @@
+/* A testcase to check generation of the following SH2A specific
+   instructions.
+
+    BLD #imm3, Rn
+    BLD.B #imm3, @(disp12, Rn)
+ */
+/* { dg-do assemble }  */
+/* { dg-options "-Os -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bld"} }  */
+/* { dg-final { scan-assembler "bld.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+int
+main ()
+{
+  volatile unsigned char a, b, c;
+  USRSTR.ICR0.BIT.BIT6 &= a;
+  USRSTR.ICR0.BIT.BIT5 |= b;
+  USRSTR.ICR0.BIT.BIT4 ^= c;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bor.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bor.c
new file mode 100644
index 000000000..8db437709
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bor.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BOR.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble }  */
+/* { dg-options "-O1 -mbitops" } */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bor.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BOR.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 | USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 | USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 | USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 | USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  |  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  |  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  |  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 |  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  |  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  |  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 |  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 |= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  |= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  |= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a & USRSTR.ICR0.BIT.BIT1;
+  a = a & USRSTR.ICR0.BIT.BIT4;
+  a = a & USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bset.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bset.c
new file mode 100644
index 000000000..322821b5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bset.c
@@ -0,0 +1,57 @@
+/* Testcase to check generation of a SH2A specific instruction
+  'BSET #imm3,Rn'.  */
+/* { dg-do assemble }  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bset"} }  */
+
+struct a
+{
+  char a, b;
+  short c;
+};
+
+/* This function generates the instruction "BSET #imm3,Rn" only
+   on using optimization option "-O1" and above.  */
+
+int
+a2 ()
+{
+  volatile int j;
+  volatile static struct a x = {1, 66, ~1}, y = {1, 2, ~2};
+
+  if (j > 1)
+    return (x.a == y.a && (x.b | 1) == y.b);
+  if (j > 2)
+    return (x.a == y.a && (x.b | 2) == y.b);
+  if (j > 3)
+    return (x.a == y.a && (x.b | 4) == y.b);
+  if (j > 4)
+    return (x.a == y.a && (x.b | 8) == y.b);
+  if (j > 5)
+    return (x.a == y.a && (x.b | 16) == y.b);
+  if (j > 6)
+    return (x.a == y.a && (x.b | 32) == y.b);
+  if (j > 7)
+    return (x.a == y.a && (x.b | 64) == y.b);
+  if (j > 8)
+    return (x.a == y.a && (x.b | 128) == y.b);
+}
+
+int
+main ()
+{
+  volatile unsigned char x;
+
+  x |= 0x1;
+  x |= 0x2;
+  x |= 0x4;
+  x |= 0x8;
+  x |= 0x16;
+  x |= 0x32;
+  x |= 0x64;
+  x |= 0x128;
+
+  if (!a2 ())
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c
new file mode 100644
index 000000000..cf35ed632
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bsetmem.c
@@ -0,0 +1,55 @@
+/* Testcase to check generation of a SH2A specific instruction
+   "BSET #imm3,@(disp12,Rn)".  */
+/* { dg-do assemble }  */
+/* { dg-options "-O2 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bset"} }  */
+/* { dg-final { scan-assembler "bset.b"} }  */
+
+volatile union un_paddr
+{
+  unsigned char BYTE;
+  struct
+  {
+    unsigned char B15:1;
+    unsigned char B14:1;
+    unsigned char B13:1;
+    unsigned char B12:1;
+    unsigned char B11:1;
+    unsigned char B10:1;
+    unsigned char B9:1;
+    unsigned char B8:1;
+    unsigned char B7:1;
+    unsigned char B6:1;
+    unsigned char B5:1;
+    unsigned char B4:1;
+    unsigned char B3:1;
+    unsigned char B2:1;
+    unsigned char B1:1;
+    unsigned char B0:1;
+  }
+  BIT;
+}
+PADDR;
+
+int
+main ()
+{
+  PADDR.BIT.B0 = 1;
+  PADDR.BIT.B3 = 1;
+  PADDR.BIT.B6 = 1;
+
+  PADDR.BIT.B1 |= 1;
+  PADDR.BIT.B4 |= 1;
+  PADDR.BIT.B7 |= 1;
+
+  PADDR.BIT.B10 = 1;
+  PADDR.BIT.B13 = 1;
+  PADDR.BIT.B15 = 1;
+
+  PADDR.BIT.B9  |= 1;
+  PADDR.BIT.B12 |= 1;
+  PADDR.BIT.B14 |= 1;
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bxor.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bxor.c
new file mode 100644
index 000000000..6cca825e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-bxor.c
@@ -0,0 +1,91 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   "BXOR.B #imm3, @(disp12, Rn)".  */
+/* { dg-do assemble }  */
+/* { dg-options "-O1 -mbitops" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "bxor.b"} }  */
+
+volatile struct
+{
+  union
+  {
+    unsigned char BYTE;
+    struct
+    {
+      unsigned char BIT7:1;
+      unsigned char BIT6:1;
+      unsigned char BIT5:1;
+      unsigned char BIT4:1;
+      unsigned char BIT3:1;
+      unsigned char BIT2:1;
+      unsigned char BIT1:1;
+      unsigned char BIT0:1;
+    }
+    BIT;
+  }
+  ICR0;
+}
+USRSTR;
+
+volatile union t_IOR
+{
+  unsigned short WORD;
+  struct
+  {
+    unsigned char IOR15:1;
+    unsigned char IOR14:1;
+    unsigned char IOR13:1;
+    unsigned char IOR12:1;
+    unsigned char IOR11:1;
+    unsigned char IOR10:1;
+    unsigned char IOR9:1;
+    unsigned char IOR8:1;
+    unsigned char IOR7:1;
+    unsigned char IOR6:1;
+    unsigned char IOR5:1;
+    unsigned char IOR4:1;
+    unsigned char IOR3:1;
+    unsigned char IOR2:1;
+    unsigned char IOR1:1;
+    unsigned char IOR0:1;
+  }
+  BIT;
+}
+PORT;
+
+int
+main ()
+{
+  volatile unsigned char a;
+
+  /* Instruction generated is BXOR.B #imm3, @(disp12, Rn)  */
+  USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 ^ USRSTR.ICR0.BIT.BIT1;
+  USRSTR.ICR0.BIT.BIT2 = USRSTR.ICR0.BIT.BIT6 ^ USRSTR.ICR0.BIT.BIT6;
+  USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT4;
+  USRSTR.ICR0.BIT.BIT6 = USRSTR.ICR0.BIT.BIT1 ^ USRSTR.ICR0.BIT.BIT3;
+
+  a = USRSTR.ICR0.BIT.BIT0 ^ USRSTR.ICR0.BIT.BIT1;
+  a = USRSTR.ICR0.BIT.BIT5 ^ USRSTR.ICR0.BIT.BIT7;
+  a = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT6;
+
+  PORT.BIT.IOR13 = PORT.BIT.IOR0  ^  USRSTR.ICR0.BIT.BIT7;
+  PORT.BIT.IOR15 = PORT.BIT.IOR6  ^  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR3  = PORT.BIT.IOR2  ^  USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR1  = PORT.BIT.IOR13 ^  USRSTR.ICR0.BIT.BIT1;
+
+  PORT.BIT.IOR1  = PORT.BIT.IOR2  ^  USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR11 = PORT.BIT.IOR9  ^  USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR8  = PORT.BIT.IOR14 ^  USRSTR.ICR0.BIT.BIT5;
+
+  PORT.BIT.IOR10 ^= USRSTR.ICR0.BIT.BIT1;
+  PORT.BIT.IOR1  ^= USRSTR.ICR0.BIT.BIT2;
+  PORT.BIT.IOR5  ^= USRSTR.ICR0.BIT.BIT5;
+  PORT.BIT.IOR14 ^= USRSTR.ICR0.BIT.BIT4;
+
+  /* Instruction generated on using size optimization option "-Os".  */
+  a = a ^ USRSTR.ICR0.BIT.BIT1;
+  a = a ^ USRSTR.ICR0.BIT.BIT4;
+  a = a ^ USRSTR.ICR0.BIT.BIT0;
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c
new file mode 100644
index 000000000..3f55327f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-jsrn.c
@@ -0,0 +1,15 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   'JSR/N @Rm'.  */
+/* { dg-do assemble }  */
+/* { dg-options "-O0" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "jsr/n"} }  */
+
+void foo(void)
+{
+}
+
+void bar()
+{
+  foo();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c
new file mode 100644
index 000000000..fe3226e25
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-movi20s.c
@@ -0,0 +1,14 @@
+/* Testcase to check generation of 'MOVI20S #imm20, Rn'.  */
+/* { dg-do assemble }  */
+/* { dg-options "-O0" } */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "movi20s"} }  */
+
+volatile long la;
+
+void
+testfun (void)
+{
+  la = -134217728;
+  la = 134217216;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-movrt.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-movrt.c
new file mode 100644
index 000000000..3e72930ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-movrt.c
@@ -0,0 +1,15 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   'MOVRT Rn'.  */
+/* { dg-do assemble }  */
+/* { dg-options "-O1" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "movrt"} }  */
+
+int
+foo (void)
+{
+  int a, b, g, stop;
+  if (stop = ((a + b) % 2 != g))
+    ;
+  return stop;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-resbank.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-resbank.c
new file mode 100644
index 000000000..a12a711af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-resbank.c
@@ -0,0 +1,12 @@
+/* Test for resbank attribute.  */
+/* { dg-do assemble }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
+/* { dg-final { scan-assembler "resbank" } } */
+ 
+extern void bar(void);
+ 
+void foo(void) __attribute__((interrupt_handler, resbank));
+void foo(void)
+{
+  bar();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c
new file mode 100644
index 000000000..612c3032d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-rtsn.c
@@ -0,0 +1,11 @@
+/* Testcase to check generation of a SH2A specific instruction for
+   'RTS/N'.  */
+/* { dg-do assemble }  */
+/* { dg-options "-O0" }  */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" }  */
+/* { dg-final { scan-assembler "rts/n"} }  */
+
+void
+bar (void)
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c
new file mode 100644
index 000000000..24b57febe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh2a-tbr-jump.c
@@ -0,0 +1,22 @@
+/* Testcase to check generation of a SH2A specific,
+   TBR relative jump instruction - 'JSR @@(disp8,TBR)'.  */
+/* { dg-do assemble }  */
+/* { dg-options "" } */
+/* { dg-skip-if "" { "sh*-*-*" } "*" "-m2a -m2a-nofpu -m2a-single -m2a-single-only" } */
+/* { dg-final { scan-assembler-times "jsr/n\\t@@\\(40,tbr\\)" 1} } */
+/* { dg-final { scan-assembler-times "jsr/n\\t@@\\(72,tbr\\)" 1} } */
+ 
+extern void foo1 (void) __attribute__ ((function_vector(10)));
+extern void foo2 (void);
+extern int bar1 (void) __attribute__ ((function_vector(18)));
+extern int bar2 (void);
+
+int
+bar()
+{
+  foo1();
+  foo2();
+
+  bar1();
+  bar2();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c
new file mode 100644
index 000000000..35ebf5cd3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c
@@ -0,0 +1,91 @@
+/* Verify that we generate movua to load unaligned 32-bit values on SH4A.  */
+/* { dg-do run }  */
+/* { dg-options "-O1 -save-temps -fno-inline" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a*" } }  */
+/* { dg-final { scan-assembler-times "movua.l" 6 } } */
+
+/* Aligned.  */
+struct s0 { long long d : 32; } x0;
+long long f0() {
+  return x0.d;
+}
+
+/* Unaligned load.  */
+struct s1 { long long c : 8; long long d : 32; } x1;
+long long f1() {
+  return x1.d;
+}
+
+/* Unaligned load.  */
+struct s2 { long long c : 16; long long d : 32; } x2;
+long long f2() {
+  return x2.d;
+}
+
+/* Unaligned load.  */
+struct s3 { long long c : 24; long long d : 32; } x3;
+long long f3() {
+  return x3.d;
+}
+
+/* Aligned.  */
+struct s4 { long long c : 32; long long d : 32; } x4;
+long long f4() {
+  return x4.d;
+}
+
+/* Aligned.  */
+struct u0 { unsigned long long d : 32; } y_0;
+unsigned long long g0() {
+  return y_0.d;
+}
+
+/* Unaligned load.  */
+struct u1 { long long c : 8; unsigned long long d : 32; } y_1;
+unsigned long long g1() {
+  return y_1.d;
+}
+
+/* Unaligned load.  */
+struct u2 { long long c : 16; unsigned long long d : 32; } y2;
+unsigned long long g2() {
+  return y2.d;
+}
+
+/* Unaligned load.  */
+struct u3 { long long c : 24; unsigned long long d : 32; } y3;
+unsigned long long g3() {
+  return y3.d;
+}
+
+/* Aligned.  */
+struct u4 { long long c : 32; unsigned long long d : 32; } y4;
+unsigned long long g4() {
+  return y4.d;
+}
+
+#include <assert.h>
+
+int
+main (void)
+{
+  x1.d = 0x12345678;
+  assert (f1 () == 0x12345678);
+
+  x2.d = 0x12345678;
+  assert (f2 () == 0x12345678);
+
+  x3.d = 0x12345678;
+  assert (f3 () == 0x12345678);
+
+  y_1.d = 0x12345678;
+  assert (g1 () == 0x12345678);
+
+  y2.d = 0x12345678;
+  assert (g2 () == 0x12345678);
+
+  y3.d = 0x12345678;
+  assert (g3 () == 0x12345678);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-cosf.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-cosf.c
new file mode 100644
index 000000000..d6277da7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-cosf.c
@@ -0,0 +1,11 @@
+/* Verify that we generate single-precision sine and cosine approximate
+   (fsca) in fast math mode on SH4A with FPU.  */
+/* { dg-do compile }  */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
+/* { dg-final { scan-assembler "fsca" } } */
+
+#include <math.h>
+
+float test(float f) { return cosf(f); }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-fprun.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-fprun.c
new file mode 100644
index 000000000..e5fbc4aca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-fprun.c
@@ -0,0 +1,55 @@
+/* Verify that fsca and fssra yield reasonable results.  */
+/* This test calls the sinf and cosf library functions for targets other
+   than sh4a, but the VxWorks kernel doesn't have those functions.  */
+/* { dg-do run { target { "sh*-*-*" && { ! vxworks_kernel } } } } */
+/* { dg-options "-O -ffast-math" } */
+
+#include <math.h>
+#include <stdlib.h>
+
+float sqrt_arg = 4.0f, sqrt_res = 2.0f;
+float dg2rad_f;
+double dg2rad_d;
+
+float __attribute__ ((noinline))
+test_sinf (float x)
+{
+  return sinf (x);
+}
+
+float __attribute ((noinline))
+test_cosf (float x)
+{
+  return cosf (x);
+}
+
+void
+check_f (float res, float expected)
+{
+  if (res >= expected - 0.001f && res <= expected + 0.001f)
+    return;
+
+  abort ();
+}
+
+void
+check_d (double res, double expected)
+{
+  if (res >= expected - 0.001 && res <= expected + 0.001)
+    return;
+
+  abort ();
+}
+
+int
+main()
+{
+  check_f (sqrtf(sqrt_arg), sqrt_res);
+  dg2rad_f = dg2rad_d = atan(1) / 45;
+  check_f (test_sinf(90*dg2rad_f), 1);
+  check_f (test_cosf(90*dg2rad_f), 0);
+  check_d (sin(-90*dg2rad_d), -1);
+  check_d (cos(180*dg2rad_d), -1);
+  check_d (sin(-45*dg2rad_d) * cosf(135*dg2rad_f), 0.5);
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c
new file mode 100644
index 000000000..0bd7d8773
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-fsrra.c
@@ -0,0 +1,11 @@
+/* Verify that we generate single-precision square root reciprocal
+   approximate (fsrra) in fast math mode on SH4A with FPU.  */
+/* { dg-do compile }  */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
+/* { dg-final { scan-assembler "fsrra" } } */
+
+#include <math.h>
+
+float test(float f) { return 1 / sqrtf(f); }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c
new file mode 100644
index 000000000..7e817c4c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c
@@ -0,0 +1,14 @@
+/* Verify that we generate movua to copy unaligned memory regions to
+   32-bit-aligned addresses on SH4A.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" "-m4a-nofpu" } }  */
+/* { dg-final { scan-assembler-times "movua.l" 2 } } */
+
+#include <string.h>
+
+struct s { int i; char a[10], b[10]; } x;
+int f() {
+  memcpy(x.a, x.b, 10);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c
new file mode 100644
index 000000000..b85fa86a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-sincosf.c
@@ -0,0 +1,12 @@
+/* Verify that we generate a single single-precision sine and cosine
+   approximate (fsca) in fast math mode when a function computes both
+   sine and cosine.  */
+/* { dg-do compile }  */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
+/* { dg-final { scan-assembler-times "fsca" 1 } } */
+
+#include <math.h>
+
+float test(float f) { return sinf(f) + cosf(f); }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-sinf.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-sinf.c
new file mode 100644
index 000000000..0ce13263e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sh4a-sinf.c
@@ -0,0 +1,11 @@
+/* Verify that we generate single-precision sine and cosine approximate
+   (fsca) in fast math mode on SH4A with FPU.  */
+/* { dg-do compile }  */
+/* { dg-options "-O -ffast-math" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m4a" "-m4a-single" "-m4a-single-only" } }  */
+/* { dg-final { scan-assembler "fsca" } } */
+
+#include <math.h>
+
+float test(float f) { return sinf(f); }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/sp-switch.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/sp-switch.c
new file mode 100644
index 000000000..aad6ba001
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/sp-switch.c
@@ -0,0 +1,10 @@
+/* { dg-do compile }  */
+/* { dg-final { scan-assembler "mov\tr0,r15" } } */
+/* { dg-final { scan-assembler ".long\t_alt_stack" } } */
+
+void *alt_stack;
+void f() __attribute__ ((interrupt_handler, sp_switch ("alt_stack")));
+
+void f()
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/strlen.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/strlen.c
new file mode 100644
index 000000000..115baba99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/strlen.c
@@ -0,0 +1,19 @@
+/* Check that the __builtin_strlen function is inlined with cmp/str
+   when optimizing for speed.  */
+/* { dg-do compile }  */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "jmp" } } */
+/* { dg-final { scan-assembler-times "cmp/str" 2 } } */
+/* { dg-final { scan-assembler-times "tst\t#3" 1 } } */
+
+test00 (const char *s1)
+{
+  return __builtin_strlen (s1);
+}
+
+/* Check that no test for alignment is needed.  */
+test03(const char *s1)
+{
+  return __builtin_strlen (__builtin_assume_aligned (s1, 4));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c
new file mode 100644
index 000000000..50c8f34c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/struct-arg-dw2.c
@@ -0,0 +1,26 @@
+/* Verify that we don't generate frame related insn against stack adjustment
+   for the object sent partially in registers. */
+/* { dg-do compile }  */
+/* { dg-options "-g" } */
+/* { dg-final { scan-assembler-not "\t.cfi_def_cfa_offset 16" } } */
+
+typedef struct
+{
+  unsigned short A1;
+  unsigned short A2;
+} A_t;
+
+typedef struct
+{
+  A_t C13[10];
+} C_t;
+
+void
+Store (C_t Par)
+{
+  unsigned char *ptr;
+  unsigned int test;
+
+  ptr = (unsigned char*) 0x12345678;
+  ptr++;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr30807.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr30807.c
new file mode 100644
index 000000000..c9cc771b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr30807.c
@@ -0,0 +1,218 @@
+/* { dg-do compile }  */
+/* { dg-additional-options "-fpic -std=c99" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+
+typedef unsigned int size_t;
+typedef struct
+{
+  unsigned long __val[(1024 / (8 * sizeof (unsigned long)))];
+}  __sigset_t;
+struct __jmp_buf_tag
+{
+  __sigset_t __saved_mask;
+};
+typedef struct __jmp_buf_tag sigjmp_buf[1];
+struct stat
+{
+  long long st_dev;
+  unsigned short int __pad1;
+  int tm_isdst;
+  long int tm_gmtoff;
+  char *tm_zone;
+};
+
+typedef size_t STRLEN;
+typedef struct op OP;
+typedef struct cop COP;
+typedef struct interpreter PerlInterpreter;
+typedef struct sv SV;
+typedef struct av AV;
+typedef struct cv CV;
+typedef struct gp GP;
+typedef struct gv GV;
+typedef struct xpv XPV;
+typedef struct xpvio XPVIO;
+typedef union any ANY;
+typedef unsigned char U8;
+typedef long I32;
+typedef unsigned long U32;
+typedef U32 line_t;
+typedef struct _PerlIO PerlIOl;
+typedef PerlIOl *PerlIO;
+struct sv
+{
+  void *sv_any;
+  U32 sv_flags;
+  union
+  {
+    char *svu_pv;
+  } sv_u;
+};
+struct gv
+{
+  U32 sv_flags;
+  union
+  {
+    GP *svu_gp;
+  } sv_u;
+};
+struct io
+{
+  XPVIO *sv_any;
+};
+struct xpv
+{
+  STRLEN xpv_cur;
+};
+struct xpvio
+{
+  PerlIO *xio_ofp;
+};
+struct gp
+{
+  SV *gp_sv;
+  struct io *gp_io;
+};
+struct jmpenv
+{
+  struct jmpenv *je_prev;
+  sigjmp_buf je_buf;
+  int je_ret;
+};
+typedef struct jmpenv JMPENV;
+struct cop
+{
+  line_t cop_line;
+  struct refcounted_he *cop_hints_hash;
+};
+struct interpreter
+{
+  SV **Istack_sp;
+  OP *Iop;
+  SV **Icurpad;
+  SV **Istack_base;
+  SV **Istack_max;
+  I32 *Iscopestack;
+  I32 Iscopestack_ix;
+  I32 Iscopestack_max;
+  ANY *Isavestack;
+  I32 Isavestack_ix;
+  I32 Isavestack_max;
+  SV **Itmps_stack;
+  I32 Itmps_ix;
+  I32 Itmps_floor;
+  I32 Itmps_max;
+  I32 Imodcount;
+  I32 *Imarkstack;
+  I32 *Imarkstack_ptr;
+  I32 *Imarkstack_max;
+  SV *ISv;
+  XPV *IXpv;
+  STRLEN Ina;
+  struct stat Istatbuf;
+  struct stat Istatcache;
+  OP *Irestartop;
+  COP *volatile Icurcop;
+  JMPENV *Itop_env;
+  U8 Iexit_flags;
+  I32 Istatusvalue;
+  I32 Istatusvalue_posix;
+  GV *Istderrgv;
+  GV *Ierrgv;
+  AV *Ibeginav;
+  AV *Iunitcheckav;
+  COP Icompiling;
+  char Isavebegin;
+  volatile U32 Idebug;
+  AV *Ibeginav_save;
+  AV *Icheckav_save;
+  AV *Iunitcheckav_save;
+};
+
+void S_my_exit_jump (PerlInterpreter *my_perl __attribute__((unused)))
+  __attribute__((noreturn));
+
+int Perl_av_len (PerlInterpreter*, AV*);
+void Perl_av_create_and_push (PerlInterpreter*, AV**, SV*);
+int __sigsetjmp (sigjmp_buf env, int savemask);
+void Perl_sv_2pv_flags (PerlInterpreter*, SV*, STRLEN*, int);
+void Perl_deb (PerlInterpreter*,
+	       const char*, const char*, int, const char*, int);
+void Perl_croak (PerlInterpreter*, const char*, void*);
+void foo (void);
+
+void
+Perl_call_list (PerlInterpreter *my_perl __attribute__((unused)),
+		I32 oldscope, AV *paramList)
+{
+  SV *atsv;
+  CV *cv;
+  STRLEN len;
+  int ret;
+  JMPENV cur_env;
+  GV *shplep;
+  volatile line_t oldline;
+
+  oldline = (my_perl->Icurcop) ? my_perl->Icurcop->cop_line : 0;
+
+  while (Perl_av_len (my_perl, paramList) >= 0)
+    {
+      if (my_perl->Isavebegin)
+	{
+	  if (paramList == my_perl->Ibeginav)
+	    {
+	      Perl_av_create_and_push (my_perl, &my_perl->Ibeginav_save,
+				       (SV*) cv);
+	      Perl_av_create_and_push(my_perl, &my_perl->Icheckav_save,
+				      (SV*) cv);
+	    }
+	  else if (paramList == my_perl->Iunitcheckav)
+	    Perl_av_create_and_push(my_perl, &my_perl->Iunitcheckav_save,
+				    (SV*) cv);
+	}
+
+      cur_env.je_ret = __sigsetjmp (cur_env.je_buf, 0);
+
+      switch (ret)
+	{
+	case 0:
+	  shplep = (GV *) my_perl->Ierrgv;
+	  *my_perl->Imarkstack_ptr = my_perl->Istack_sp - my_perl->Istack_base;
+	  atsv = shplep->sv_u.svu_gp->gp_sv;
+	  if (atsv->sv_flags & 0x00000400 == 0x00000400)
+	    len = ((XPV*) ((SV *) atsv)->sv_any)->xpv_cur;
+	  else
+	    Perl_sv_2pv_flags (my_perl, atsv, &len, 2|32);
+
+	  if (len)
+	    {
+	      my_perl->Icurcop = &my_perl->Icompiling;
+	      while (my_perl->Iscopestack_ix > oldscope)
+		{
+		  if (my_perl->Idebug & 0x00000004)
+		    Perl_deb (my_perl, "scope", "LEAVE",
+			      my_perl->Iscopestack_ix, "perl.c", 5166);
+		  (my_perl->Itop_env) = cur_env.je_prev;
+		}
+
+	      Perl_croak (my_perl, "%""-p""", (void*) atsv);
+	    }
+
+	case 1:
+	  my_perl->Istatusvalue = 1;
+	  my_perl->Istatusvalue_posix = 1;
+	case 2:
+	  while (my_perl->Iscopestack_ix > oldscope)
+	    if (my_perl->Idebug & 0x00000004)
+	      foo ();
+	  my_perl->Icurcop = &my_perl->Icompiling;
+	  my_perl->Icurcop->cop_line = oldline;
+	  if (my_perl->Idebug & 0x00000004)
+	    foo ();
+	  S_my_exit_jump (my_perl);
+	case 3:
+	  if (my_perl->Irestartop)
+	    foo ();
+	}
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr34777.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr34777.c
new file mode 100644
index 000000000..de6ba028c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr34777.c
@@ -0,0 +1,30 @@
+/* { dg-do compile }  */
+/* { dg-additional-options "-fschedule-insns -fPIC -mprefergot" }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+
+static __inline __attribute__ ((__always_inline__)) void *
+_dl_mmap (void * start, int length, int prot, int flags, int fd,
+	  int offset)
+{
+  register long __sc3 __asm__ ("r3") = 90;
+  register long __sc4 __asm__ ("r4") = (long) start;
+  register long __sc5 __asm__ ("r5") = (long) length;
+  register long __sc6 __asm__ ("r6") = (long) prot;
+  register long __sc7 __asm__ ("r7") = (long) flags;
+  register long __sc0 __asm__ ("r0") = (long) fd;
+  register long __sc1 __asm__ ("r1") = (long) offset;
+  __asm__ __volatile__ ("trapa	%1"
+			: "=z" (__sc0)
+			: "i" (0x10 + 6), "0" (__sc0), "r" (__sc4),
+			  "r" (__sc5), "r" (__sc6), "r" (__sc7),
+			  "r" (__sc3), "r" (__sc1)
+			: "memory" );
+}
+
+extern int _dl_pagesize;
+void
+_dl_dprintf(int fd, const char *fmt, ...)
+{
+  static char *buf;
+  buf = _dl_mmap ((void *) 0, _dl_pagesize, 0x1 | 0x2, 0x02 | 0x20, -1, 0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr58314.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr58314.c
new file mode 100644
index 000000000..7a1150840
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr58314.c
@@ -0,0 +1,102 @@
+/* { dg-do compile }  */
+/* { dg-options "-Os" } */
+
+typedef unsigned short __u16;
+typedef unsigned int __u32;
+
+typedef signed short s16;
+
+
+static inline __attribute__((always_inline)) __attribute__((__const__)) __u16 __arch_swab16(__u16 x)
+{
+ __asm__(
+  "swap.b		%1, %0"
+  : "=r" (x)
+  : "r" (x));
+ return x;
+}
+
+void u16_add_cpu(__u16 *var)
+{
+  *var = __arch_swab16(*var);
+}
+
+typedef struct xfs_mount {
+ int m_attr_magicpct;
+} xfs_mount_t;
+
+typedef struct xfs_da_args {
+ struct xfs_mount *t_mountp;
+ int index;
+} xfs_da_args_t;
+
+typedef struct xfs_dabuf {
+ void *data;
+} xfs_dabuf_t;
+
+typedef struct xfs_attr_leaf_map {
+ __u16 base;
+ __u16 size;
+} xfs_attr_leaf_map_t;
+typedef struct xfs_attr_leaf_hdr {
+ __u16 count;
+ xfs_attr_leaf_map_t freemap[3];
+} xfs_attr_leaf_hdr_t;
+
+typedef struct xfs_attr_leaf_entry {
+  __u16 nameidx;
+} xfs_attr_leaf_entry_t;
+
+typedef struct xfs_attr_leafblock {
+ xfs_attr_leaf_hdr_t hdr;
+ xfs_attr_leaf_entry_t entries[1];
+} xfs_attr_leafblock_t;
+
+int
+xfs_attr_leaf_remove(xfs_attr_leafblock_t *leaf, xfs_da_args_t *args)
+{
+ xfs_attr_leaf_hdr_t *hdr;
+ xfs_attr_leaf_map_t *map;
+ xfs_attr_leaf_entry_t *entry;
+ int before, after, smallest, entsize;
+ int tablesize, tmp, i;
+ xfs_mount_t *mp;
+ hdr = &leaf->hdr;
+ mp = args->t_mountp;
+
+ entry = &leaf->entries[args->index];
+
+ tablesize = __arch_swab16(hdr->count);
+
+ map = &hdr->freemap[0];
+ tmp = map->size;
+ before = after = -1;
+ smallest = 3 - 1;
+ entsize = xfs_attr_leaf_entsize(leaf, args->index);
+
+ for (i = 0; i < 2; map++, i++) {
+
+  if (map->base == tablesize)
+    u16_add_cpu(&map->base);
+
+  if (__arch_swab16(map->base)  + __arch_swab16(map->size)  == __arch_swab16(entry->nameidx))
+   before = i;
+  else if (map->base == entsize)
+   after = i;
+  else if (__arch_swab16(map->size) < tmp)
+   smallest = i;
+ }
+
+ if (before >= 0)
+  {
+   map = &hdr->freemap[after];
+   map->base = entry->nameidx;
+
+  }
+
+  map = &hdr->freemap[smallest];
+
+  map->base = __arch_swab16(entry->nameidx);
+
+ return(tmp < mp->m_attr_magicpct);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr58475.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr58475.c
new file mode 100644
index 000000000..f44780d29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pr58475.c
@@ -0,0 +1,15 @@
+/* { dg-do compile }  */
+
+int
+kerninfo(int __bsx, double tscale)
+{
+ return (
+	 (int)(__extension__
+	       ({
+		 ((((__bsx) & 0xff000000u) >> 24)
+		  | (((__bsx) & 0x00ff0000) >> 8)
+		  | (((__bsx) & 0x0000ff00) << 8)
+		  | (((__bsx) & 0x000000ff) << 24)
+		  ); }))
+	       * tscale);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pragma-isr.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pragma-isr.c
new file mode 100644
index 000000000..9e665bafb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pragma-isr.c
@@ -0,0 +1,20 @@
+/* Check whether rte is generated for two ISRs.  */
+/* { dg-do compile }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "rte" 2 } }  */
+
+extern void foo (void);
+
+#pragma interrupt
+void
+isr1 (void)
+{
+  foo ();
+}
+
+#pragma interrupt
+void
+isr2 (void)
+{
+  foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c
new file mode 100644
index 000000000..ce984e73f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/pragma-isr2.c
@@ -0,0 +1,21 @@
+/* Check whether rte is generated only for an ISRs.  */
+/* { dg-do compile }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-times "rte" 1 } }  */
+
+#pragma interrupt
+void
+isr (void)
+{
+}
+
+void
+delay (int a)
+{
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/sh-torture.exp b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/sh-torture.exp
new file mode 100644
index 000000000..8fef587f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/sh-torture.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2012-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `gcc-dg.exp' driver, looping over
+# optimization options.
+
+# Exit immediately if this isn't a SH target.
+if { ![istarget sh*-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/strncmp.c b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/strncmp.c
new file mode 100644
index 000000000..cd50f5c05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sh/torture/strncmp.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+
+extern void abort (void);
+
+const char *s="astc";
+const char *s1="-----BEGIN RSA PRIVATE KEY-----";
+const char *s2="atextaac";
+
+main()
+{
+  if (! __builtin_strncmp ("astb", s, 4))
+    abort();
+
+  if (__builtin_strncmp(s1, "-----BEGIN ", 11))
+    abort();
+
+  if (! __builtin_strncmp ("atextaacb", s2, 9))
+    abort();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001013-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001013-1.c
new file mode 100644
index 000000000..891ccab0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001013-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int l;
+
+int baz (double x)
+{
+  return l == 0;
+}
+
+double bar (double x)
+{
+  return 1.0;
+}
+
+double foo (double x)
+{
+  if (l == -1 || baz (x)) return x;
+  if (x < 0.0)
+    return bar (x);
+  else
+    return 0.0;
+}
+
+union {
+  double d;
+  long long l;
+} x = { l: 0x7ff8000000000000LL }, y;
+
+main ()
+{
+  unsigned int fsr = 0;
+  __asm __volatile ("ld %0, %%fsr" : : "m" (fsr));
+  y.d = foo (x.d);
+  __asm __volatile ("st %%fsr, %0" : "=m" (fsr));
+  if (x.l != y.l || (fsr & 0x3ff))
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001101-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001101-1.c
new file mode 100644
index 000000000..ec67e115f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001101-1.c
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int foo(double a, int b, int c, double *d, int h)
+{
+  int f, g;
+  double e;
+
+l:
+  f = (int) a;
+  a -= (double) f;
+  if (b == 1)
+    {
+      g = c;
+      f += g;
+      c -= g;
+    }
+  if (b == 2)
+    {
+      f++;
+      h = c;
+    }
+  if (!h)
+    {
+      for (g = 0; g <= 10; g++)
+        for (h = 0; h <= 10; h++)
+          e += d [10 + g - h];
+      goto l;
+    }
+  return f & 7;
+}
+
+int main()
+{
+  if (foo(0.1, 1, 3, 0, 1) != 3)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001102-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001102-1.c
new file mode 100644
index 000000000..b4ce8a0e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20001102-1.c
@@ -0,0 +1,43 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+extern void abort (void);
+extern void exit (int);
+
+int foo(double a, int b, int c, double *d, int h)
+{
+  int f, g;
+  double e;
+
+l:
+  f = (int) a;
+  a -= (double) f;
+  if (b == 1)
+    {
+      g = c;
+      f += g;
+      c -= g;
+    }
+  if (b == 2)
+    {
+      f++;
+      h = c;
+      goto l;
+    }
+
+  asm volatile ("" : : :
+		"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+		"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+		"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+		"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");
+
+  return f & 7;
+}
+
+int main()
+{
+  if (foo(0.1, 1, 3, 0, 1) != 3)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/20020116-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20020116-2.c
new file mode 100644
index 000000000..828ffff26
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20020116-2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=supersparc" } */
+
+/* This testcase ICEd on sparc64 because -mcpu=supersparc and implicit
+   -m64 resulted in MASK_V8 and MASK_V9 to be set at the same time.  */
+
+void bar (long *x, long *y);
+
+void foo (int x, long *y, long *z)
+{
+  int i;
+
+  for (i = x - 1; i >= 0; i--)
+    {
+      bar (z + i * 3 + 1, y);
+      bar (z + i * 3 + 2, y);
+    }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/20020416-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20020416-1.c
new file mode 100644
index 000000000..05f0ee655
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20020416-1.c
@@ -0,0 +1,15 @@
+/* PR bootstrap/6315 */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mhard-quad-float" } */
+
+void bar (const char *, ...);
+
+void
+foo (const char *x, long double y, int z)
+{
+  if (z >= 0)
+    bar (x, z, y);
+  else
+    bar (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/20111102-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20111102-1.c
new file mode 100644
index 000000000..d33f103e3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/20111102-1.c
@@ -0,0 +1,17 @@
+/* PR target/50945 */
+/* { dg-do compile } */
+/* { dg-options "-O -msoft-float" } */
+
+double
+__powidf2 (double x, int m)
+{
+  unsigned int n = m < 0 ? -m : m;
+  double y = n % 2 ? x : 1;
+  while (n >>= 1)
+    {
+      x = x * x;
+      if (n % 2)
+	y = y * x;
+    }
+  return m < 0 ? 1/y : y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/align.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/align.c
new file mode 100644
index 000000000..804ca9397
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/align.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef long long int64_t;
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec16 foo1 (vec16 a, vec16 b) {
+  return __builtin_vis_faligndatav4hi (a, b);
+}
+
+vec32 foo2 (vec32 a, vec32 b) {
+  return __builtin_vis_faligndatav2si (a, b);
+}
+
+vec8 foo3 (vec8 a, vec8 b) {
+  return __builtin_vis_faligndatav8qi (a, b);
+}
+
+int64_t foo4 (int64_t a, int64_t b) {
+  return __builtin_vis_faligndatadi (a, b);
+}
+
+unsigned char * foo5 (unsigned char *data) {
+  return __builtin_vis_alignaddr (data, 0);
+}
+
+/* { dg-final { scan-assembler-times "faligndata" 4 } } */
+/* { dg-final { scan-assembler "alignaddr.*%g0" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/array.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/array.c
new file mode 100644
index 000000000..e382e22f3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/array.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+
+long test_array8 (long a, long b)
+{
+  return __builtin_vis_array8 (a, b);
+}
+
+long test_array16 (long a, long b)
+{
+  return __builtin_vis_array16 (a, b);
+}
+
+long test_array32 (long a, long b)
+{
+  return __builtin_vis_array32 (a, b);
+}
+
+/* { dg-final { scan-assembler "array8\t%" } } */
+/* { dg-final { scan-assembler "array16\t%" } } */
+/* { dg-final { scan-assembler "array32\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c
new file mode 100644
index 000000000..22809b5f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/bmaskbshuf.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mvis2" } */
+
+typedef long long int64_t;
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+long test_bmask (long x, long y)
+{
+  return __builtin_vis_bmask (x, y);
+}
+
+vec16 test_bshufv4hi (vec16 x, vec16 y)
+{
+  return __builtin_vis_bshufflev4hi (x, y);
+}
+
+vec32 test_bshufv2si (vec32 x, vec32 y)
+{
+  return __builtin_vis_bshufflev2si (x, y);
+}
+
+vec8 test_bshufv8qi (vec8 x, vec8 y)
+{
+  return __builtin_vis_bshufflev8qi (x, y);
+}
+
+int64_t test_bshufdi (int64_t x, int64_t y)
+{
+  return __builtin_vis_bshuffledi (x, y);
+}
+
+/* { dg-final { scan-assembler "bmask\t%" } } */
+/* { dg-final { scan-assembler "bshuffle\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/cas64.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/cas64.c
new file mode 100644
index 000000000..ed27cd7cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/cas64.c
@@ -0,0 +1,15 @@
+/* PR target/49660 */
+
+/* { dg-do compile { target sparc*-*-solaris2.* } } */
+
+#include <stdint.h>
+
+extern int64_t *val, old, new;
+
+int
+cas64 (void)
+{
+  return __sync_bool_compare_and_swap (val, old, new);
+}
+
+/* { dg-final { scan-assembler-not "compare_and_swap_8" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/cmask.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/cmask.c
new file mode 100644
index 000000000..d1be910f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/cmask.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
+
+void test_cm8 (long x)
+{
+  __builtin_vis_cmask8 (x);
+}
+
+void test_cm16 (long x)
+{
+  __builtin_vis_cmask16 (x);
+}
+
+void test_cm32 (long x)
+{
+  __builtin_vis_cmask32 (x);
+}
+
+/* { dg-final { scan-assembler "cmask8\t%" } } */
+/* { dg-final { scan-assembler "cmask16\t%" } } */
+/* { dg-final { scan-assembler "cmask32\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/combined-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/combined-1.c
new file mode 100644
index 000000000..5f19db3b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/combined-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec16 fun16(vec16 a, vec16 b)
+{
+  return (~a & b) + (b | a) - (a ^ b);
+}
+
+vec32 fun32(vec32 a, vec32 b)
+{
+  return (~a & b) + (b | a) - (a ^ b);
+}
+
+/* This should be transformed into ~b & a.  */
+vec16 fun16b(vec16 a, vec16 b)
+{
+  return (a & ~b) + (b | a) - (a ^ b);
+}
+
+vec32 fun32b(vec32 a, vec32 b)
+{
+  return (a & ~b) + (b | a) - (a ^ b);
+}
+
+/* { dg-final { scan-assembler-times "fandnot1\t%" 4 } } */
+/* { dg-final { scan-assembler-times "for\t%" 4 } } */
+/* { dg-final { scan-assembler-times "fpadd" 4 } } */
+/* { dg-final { scan-assembler-times "fxor\t%" 4 } } */
+/* { dg-final { scan-assembler-times "fpsub" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/combined-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/combined-2.c
new file mode 100644
index 000000000..c4b70a55a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/combined-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo (pixel a, pixel b) {
+  vec8 c = __builtin_vis_fpmerge (a, b);
+  vec16 d = { -1, -1, -1, -1 };
+  vec16 e = __builtin_vis_fmul8x16 (a, d);
+
+  return e;
+}
+
+vec16 bar (pixel a) {
+  vec16 d = { 0, 0, 0, 0 };
+  vec16 e = __builtin_vis_fmul8x16 (a, d);  /* Mulitplication by 0 = 0.  */
+
+  return e;
+}
+
+/* { dg-final { scan-assembler "fmul8x16" } } */
+/* { dg-final { scan-assembler "fzero" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/edge.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/edge.c
new file mode 100644
index 000000000..81d8d8856
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/edge.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+
+long test_edge8 (void *p1, void *p2)
+{
+  return __builtin_vis_edge8 (p1, p2);
+}
+
+long test_edge8l (void *p1, void *p2)
+{
+  return __builtin_vis_edge8l (p1, p2);
+}
+
+long test_edge16 (void *p1, void *p2)
+{
+  return __builtin_vis_edge16 (p1, p2);
+}
+
+long test_edge16l (void *p1, void *p2)
+{
+  return __builtin_vis_edge16l (p1, p2);
+}
+
+long test_edge32 (void *p1, void *p2)
+{
+  return __builtin_vis_edge32 (p1, p2);
+}
+
+long test_edge32l (void *p1, void *p2)
+{
+  return __builtin_vis_edge32l (p1, p2);
+}
+
+/* { dg-final { scan-assembler "edge8\t%" } } */
+/* { dg-final { scan-assembler "edge8l\t%" } } */
+/* { dg-final { scan-assembler "edge16\t%" } } */
+/* { dg-final { scan-assembler "edge16l\t%" } } */
+/* { dg-final { scan-assembler "edge32\t%" } } */
+/* { dg-final { scan-assembler "edge32l\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/edgen.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/edgen.c
new file mode 100644
index 000000000..11973b58c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/edgen.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc3 -mvis" } */
+
+long test_edge8n (void *p1, void *p2)
+{
+  return __builtin_vis_edge8n (p1, p2);
+}
+
+long test_edge8ln (void *p1, void *p2)
+{
+  return __builtin_vis_edge8ln (p1, p2);
+}
+
+long test_edge16n (void *p1, void *p2)
+{
+  return __builtin_vis_edge16n (p1, p2);
+}
+
+long test_edge16ln (void *p1, void *p2)
+{
+  return __builtin_vis_edge16ln (p1, p2);
+}
+
+long test_edge32n (void *p1, void *p2)
+{
+  return __builtin_vis_edge32n (p1, p2);
+}
+
+long test_edge32ln (void *p1, void *p2)
+{
+  return __builtin_vis_edge32ln (p1, p2);
+}
+
+/* { dg-final { scan-assembler "edge8n\t%" } } */
+/* { dg-final { scan-assembler "edge8ln\t%" } } */
+/* { dg-final { scan-assembler "edge16n\t%" } } */
+/* { dg-final { scan-assembler "edge16ln\t%" } } */
+/* { dg-final { scan-assembler "edge32n\t%" } } */
+/* { dg-final { scan-assembler "edge32ln\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fand.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fand.c
new file mode 100644
index 000000000..b0589bdbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fand.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () & foo2_8 ();
+}
+
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a & b;
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () & foo2_16 ();
+}
+
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a & b;
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () & foo2_32 ();
+}
+
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a & b;
+}
+
+/* { dg-final { scan-assembler-times "fand\t%" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fandnot.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fandnot.c
new file mode 100644
index 000000000..005486385
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fandnot.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () & foo2_8 ();
+}
+
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~a & b;
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () & foo2_16 ();
+}
+
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~a & b;
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 () & foo2_32 ();
+}
+
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~a & b;
+}
+
+
+/* This should be transformed into ~b & a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () & ~foo2_8 ();
+}
+
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a & ~b;
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () & ~foo2_16 ();
+}
+
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a & ~b;
+}
+
+vec32 fun32b(void)
+{
+  return foo1_32 () & ~foo2_32 ();
+}
+
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a & ~b;
+}
+
+/* { dg-final { scan-assembler-times "fandnot1\t%" 12 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fandnots.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fandnots.c
new file mode 100644
index 000000000..7a5ed2414
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fandnots.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () & foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () & foo1_16 ();
+}
+
+
+/* This should be transformed into ~b & a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () & ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () & ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fandnot1s\t%" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fands.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fands.c
new file mode 100644
index 000000000..f924f4531
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fands.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () & foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () & foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fands\t%" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fcmp.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fcmp.c
new file mode 100644
index 000000000..959a674e1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fcmp.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+
+long test_fcmple16 (vec16 a, vec16 b)
+{
+  return __builtin_vis_fcmple16 (a, b);
+}
+
+long test_fcmple32 (vec32 a, vec32 b)
+{
+  return __builtin_vis_fcmple32 (a, b);
+}
+
+long test_fcmpne16 (vec16 a, vec16 b)
+{
+  return __builtin_vis_fcmpne16 (a, b);
+}
+
+long test_fcmpne32 (vec32 a, vec32 b)
+{
+  return __builtin_vis_fcmpne32 (a, b);
+}
+
+long test_fcmpgt16 (vec16 a, vec16 b)
+{
+  return __builtin_vis_fcmpgt16 (a, b);
+}
+
+long test_fcmpgt32 (vec32 a, vec32 b)
+{
+  return __builtin_vis_fcmpgt32 (a, b);
+}
+
+long test_fcmpeq16 (vec16 a, vec16 b)
+{
+  return __builtin_vis_fcmpeq16 (a, b);
+}
+
+long test_fcmpeq32 (vec32 a, vec32 b)
+{
+  return __builtin_vis_fcmpeq32 (a, b);
+}
+
+/* { dg-final { scan-assembler "fcmple16\t%" } } */
+/* { dg-final { scan-assembler "fcmple32\t%" } } */
+/* { dg-final { scan-assembler "fcmpne16\t%" } } */
+/* { dg-final { scan-assembler "fcmpne32\t%" } } */
+/* { dg-final { scan-assembler "fcmpgt16\t%" } } */
+/* { dg-final { scan-assembler "fcmpgt32\t%" } } */
+/* { dg-final { scan-assembler "fcmpeq16\t%" } } */
+/* { dg-final { scan-assembler "fcmpeq32\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fexpand-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fexpand-2.c
new file mode 100644
index 000000000..c37b806c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fexpand-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O1 -mcpu=ultrasparc -mvis -fdump-tree-optimized" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec16 foo () {
+  vec8 a = {(unsigned char)1,(unsigned char)2,(unsigned char)4,(unsigned char)8};
+  return __builtin_vis_fexpand (a);
+}
+
+/* { dg-final { scan-tree-dump "{ 16, 32, 64, 128 }" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fexpand.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fexpand.c
new file mode 100644
index 000000000..21aeafff0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fexpand.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec16 foo (vec8 a) {
+  return __builtin_vis_fexpand (a);
+}
+
+/* { dg-final { scan-assembler "fexpand\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fhalve.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fhalve.c
new file mode 100644
index 000000000..b8f0745af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fhalve.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
+
+float test_fhadds (float x, float y)
+{
+  return __builtin_vis_fhadds (x, y);
+}
+
+double test_fhaddd (double x, double y)
+{
+  return __builtin_vis_fhaddd (x, y);
+}
+
+float test_fhsubs (float x, float y)
+{
+  return __builtin_vis_fhsubs (x, y);
+}
+
+double test_fhsubd (double x, double y)
+{
+  return __builtin_vis_fhsubd (x, y);
+}
+
+float test_fnhadds (float x, float y)
+{
+  return __builtin_vis_fnhadds (x, y);
+}
+
+double test_fnhaddd (double x, double y)
+{
+  return __builtin_vis_fnhaddd (x, y);
+}
+
+/* { dg-final { scan-assembler "fhadds\t%" } } */
+/* { dg-final { scan-assembler "fhaddd\t%" } } */
+/* { dg-final { scan-assembler "fhsubs\t%" } } */
+/* { dg-final { scan-assembler "fhsubd\t%" } } */
+/* { dg-final { scan-assembler "fnhadds\t%" } } */
+/* { dg-final { scan-assembler "fnhaddd\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fmaf-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fmaf-1.c
new file mode 100644
index 000000000..948b9269e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fmaf-1.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfmaf" } */
+
+float fmadds (float a, float b, float c)
+{
+  return a * b + c;
+}
+
+float fmsubs (float a, float b, float c)
+{
+  return a * b - c;
+}
+
+float fnmadds (float a, float b, float c)
+{
+  return -(a * b + c);
+}
+
+float fnmsubs (float a, float b, float c)
+{
+  return -(a * b - c);
+}
+
+double fmaddd (double a, double b, double c)
+{
+  return a * b + c;
+}
+
+double fmsubd (double a, double b, double c)
+{
+  return a * b - c;
+}
+
+double fnmaddd (double a, double b, double c)
+{
+  return -(a * b + c);
+}
+
+double fnmsubd (double a, double b, double c)
+{
+  return -(a * b - c);
+}
+
+/* { dg-final { scan-assembler "fmadds\t%" } } */
+/* { dg-final { scan-assembler "fmsubs\t%" } } */
+/* { dg-final { scan-assembler "fnmadds\t%" } } */
+/* { dg-final { scan-assembler "fnmsubs\t%" } } */
+/* { dg-final { scan-assembler "fmaddd\t%" } } */
+/* { dg-final { scan-assembler "fmsubd\t%" } } */
+/* { dg-final { scan-assembler "fnmaddd\t%" } } */
+/* { dg-final { scan-assembler "fnmsubd\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnand.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnand.c
new file mode 100644
index 000000000..89fe8694d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnand.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo2_16 ());
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () & foo2_32 ());
+}
+
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo2_16 ();
+}
+
+vec32 fun32b(void)
+{
+  return ~foo1_32 () | ~foo2_32 ();
+}
+
+/* { dg-final { scan-assembler-times "fnand\t%" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnands.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnands.c
new file mode 100644
index 000000000..05d6c4733
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnands.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () & foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () & foo1_16 ());
+}
+
+/* DeMorgan's Law's at work.  */
+vec8 fun8b(void)
+{
+  return ~foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return ~foo1_16 () | ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fnands\t%" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnegop.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnegop.c
new file mode 100644
index 000000000..cbdf28f4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnegop.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mvis3" } */
+
+float test_fnadds(float x, float y)
+{
+  return -(x + y);
+}
+
+double test_fnaddd(double x, double y)
+{
+  return -(x + y);
+}
+
+float test_fnmuls(float x, float y)
+{
+  return -(x * y);
+}
+
+double test_fnmuld(double x, double y)
+{
+  return -(x * y);
+}
+
+double test_fnsmuld(float x, float y)
+{
+  return -((double)x * (double)y);
+}
+
+/* { dg-final { scan-assembler "fnadds\t%" } } */
+/* { dg-final { scan-assembler "fnaddd\t%" } } */
+/* { dg-final { scan-assembler "fnmuls\t%" } } */
+/* { dg-final { scan-assembler "fnmuld\t%" } } */
+/* { dg-final { scan-assembler "fnsmuld\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnot.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnot.c
new file mode 100644
index 000000000..c0ddc931f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnot.c
@@ -0,0 +1,47 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern void foo2_8(vec8);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 ();
+}
+
+vec8 fun8_2(vec8 a)
+{
+  foo2_8 (~a);
+}
+
+extern vec16 foo1_16(void);
+extern void foo2_16(vec16);
+
+
+vec16 fun16(void)
+{
+  return ~foo1_16 ();
+}
+
+vec16 fun16_2(vec16 a)
+{
+  foo2_16 (~a);
+}
+
+extern vec32 foo1_32(void);
+extern void foo2_32(vec32);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 ();
+}
+
+vec32 fun32_2(vec32 a)
+{
+  foo2_32 (~a);
+}
+
+/* { dg-final { scan-assembler-times "fnot1\t%" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnots.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnots.c
new file mode 100644
index 000000000..f50eb0b3a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fnots.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 ();
+}
+
+extern vec16 foo1_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fnot1s\t%" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/for.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/for.c
new file mode 100644
index 000000000..3da4bc237
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/for.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () | foo2_8 ();
+}
+
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a | b;
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () | foo2_16 ();
+}
+
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a | b;
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () | foo2_32 ();
+}
+
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a | b;
+}
+
+/* { dg-final { scan-assembler-times "for\t%" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fornot.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fornot.c
new file mode 100644
index 000000000..2daa96e0a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fornot.c
@@ -0,0 +1,77 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () | foo2_8 ();
+}
+
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~a | b;
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () | foo2_16 ();
+}
+
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~a | b;
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~foo1_32 () | foo2_32 ();
+}
+
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~a | b;
+}
+
+/* This should be transformed into ~b | a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () | ~foo2_8 ();
+}
+
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a | ~b;
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () | ~foo2_16 ();
+}
+
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a | ~b;
+}
+
+vec32 fun32b(void)
+{
+  return foo1_32 () | ~foo2_32 ();
+}
+
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a | ~b;
+}
+
+/* { dg-final { scan-assembler-times "fornot1\t%" 12 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fornots.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fornots.c
new file mode 100644
index 000000000..db29a9926
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fornots.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~foo1_8 () | foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~foo1_16 () | foo1_16 ();
+}
+
+
+/* This should be transformed into ~b | a.  */
+vec8 fun8b(void)
+{
+  return foo1_8 () | ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () | ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fornot1s\t%" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fors.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fors.c
new file mode 100644
index 000000000..0afdd4bbc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fors.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () | foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () | foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fors\t%" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpack16.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpack16.c
new file mode 100644
index 000000000..79e0c4c15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpack16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+vec8 foo (vec16 a) {
+  return __builtin_vis_fpack16 (a);
+}
+
+/* { dg-final { scan-assembler "fpack16\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpack32.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpack32.c
new file mode 100644
index 000000000..031372e21
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpack32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec8 foo (vec32 a, vec8 b) {
+  return __builtin_vis_fpack32 (a, b);
+}
+
+/* { dg-final { scan-assembler "fpack32\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpackfix.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpackfix.c
new file mode 100644
index 000000000..815bec0cf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpackfix.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo (vec32 a) {
+  return __builtin_vis_fpackfix (a);
+}
+
+/* { dg-final { scan-assembler "fpackfix\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd16.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd16.c
new file mode 100644
index 000000000..071282d2e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd16\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd16s.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd16s.c
new file mode 100644
index 000000000..7f65a7a93
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd16s.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd16s\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd32.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd32.c
new file mode 100644
index 000000000..7c57018a7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec32 foo(vec32 a, vec32 b)
+{
+  return a + b;
+}
+
+/* { dg-final { scan-assembler "fpadd32\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd32s.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd32s.c
new file mode 100644
index 000000000..709ad83c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadd32s.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(4)));
+
+extern vec32 foo1(void);
+extern vec32 foo2(void);
+
+vec32 bar(void)
+{
+  return foo1 () + foo2 ();
+}
+
+/* { dg-final { scan-assembler "fpadd32s\t%" }  } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadds.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadds.c
new file mode 100644
index 000000000..9b1027d5f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpadds.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
+typedef int __v2si __attribute__((vector_size(8)));
+typedef int __v1si __attribute__((vector_size(4)));
+typedef short __v4hi __attribute__((vector_size(8)));
+typedef short __v2hi __attribute__((vector_size(4)));
+
+__v4hi test_fpadds16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fpadds16 (x, y);
+}
+
+__v2hi test_fpadds16s (__v2hi x, __v2hi y)
+{
+  return __builtin_vis_fpadds16s (x, y);
+}
+
+__v4hi test_fpsubs16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fpsubs16 (x, y);
+}
+
+__v2hi test_fpsubs16s (__v2hi x, __v2hi y)
+{
+  return __builtin_vis_fpsubs16s (x, y);
+}
+
+__v2si test_fpadds32 (__v2si x, __v2si y)
+{
+  return __builtin_vis_fpadds32 (x, y);
+}
+
+__v1si test_fpadds32s (__v1si x, __v1si y)
+{
+  return __builtin_vis_fpadds32s (x, y);
+}
+
+__v2si test_fpsubs32 (__v2si x, __v2si y)
+{
+  return __builtin_vis_fpsubs32 (x, y);
+}
+
+__v1si test_fpsubs32s (__v1si x, __v1si y)
+{
+  return __builtin_vis_fpsubs32s (x, y);
+}
+
+/* { dg-final { scan-assembler "fpadds16\t%" } } */
+/* { dg-final { scan-assembler "fpadds16s\t%" } } */
+/* { dg-final { scan-assembler "fpsubs16\t%" } } */
+/* { dg-final { scan-assembler "fpsubs16s\t%" } } */
+/* { dg-final { scan-assembler "fpadds32\t%" } } */
+/* { dg-final { scan-assembler "fpadds32s\t%" } } */
+/* { dg-final { scan-assembler "fpsubs32\t%" } } */
+/* { dg-final { scan-assembler "fpsubs32s\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpaddsubi.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpaddsubi.c
new file mode 100644
index 000000000..a36108e70
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpaddsubi.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int __v2si __attribute__((vector_size(8)));
+typedef int __v1si __attribute__((vector_size(4)));
+typedef short __v4hi __attribute__((vector_size(8)));
+typedef short __v2hi __attribute__((vector_size(4)));
+
+extern __v1si foo_x (void);
+extern __v1si foo_y (void);
+
+__v4hi test_fpadd16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fpadd16 (x, y);
+}
+
+__v2hi test_fpadd16s (__v2hi x, __v2hi y)
+{
+  return __builtin_vis_fpadd16s (x, y);
+}
+
+__v4hi test_fpsub16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fpsub16 (x, y);
+}
+
+__v2hi test_fpsub16s (__v2hi x, __v2hi y)
+{
+  return __builtin_vis_fpsub16s (x, y);
+}
+
+__v2si test_fpadd32 (__v2si x, __v2si y)
+{
+  return __builtin_vis_fpadd32 (x, y);
+}
+
+__v1si test_fpadd32s (void)
+{
+  return __builtin_vis_fpadd32s (foo_x (), foo_y ());
+}
+
+__v2si test_fpsub32 (__v2si x, __v2si y)
+{
+  return __builtin_vis_fpsub32 (x, y);
+}
+
+__v1si test_fpsub32s (__v1si x, __v1si y)
+{
+  return __builtin_vis_fpsub32s (foo_x (), foo_y ());
+}
+
+/* { dg-final { scan-assembler "fpadd16\t%" }  } */
+/* { dg-final { scan-assembler "fpadd16s\t%" }  } */
+/* { dg-final { scan-assembler "fpsub16\t%" }  } */
+/* { dg-final { scan-assembler "fpsub16s\t%" }  } */
+/* { dg-final { scan-assembler "fpadd32\t%" }  } */
+/* { dg-final { scan-assembler "fpadd32s\t%" }  } */
+/* { dg-final { scan-assembler "fpsub32\t%" }  } */
+/* { dg-final { scan-assembler "fpsub32s\t%" }  } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmerge-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmerge-2.c
new file mode 100644
index 000000000..524c736f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmerge-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-optimized" } */
+typedef unsigned char pixel __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+#define _(ARG) (unsigned char)ARG
+
+pixel foo () {
+  vec8 a = { _(1), _(3), _(5), _(7) };
+  vec8 b = { _(2), _(4), _(6), _(8) };
+  return __builtin_vis_fpmerge (a, b);
+}
+
+/* { dg-final { scan-assembler-not "fpmerge\t%" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 3, 4, 5, 6, 7, 8 }" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmerge.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmerge.c
new file mode 100644
index 000000000..4d6a9c023
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmerge.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef unsigned char pixel __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(4)));
+
+pixel foo (vec8 a, vec8 b) {
+  return __builtin_vis_fpmerge (a, b);
+}
+
+/* { dg-final { scan-assembler "fpmerge\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmul-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmul-2.c
new file mode 100644
index 000000000..e04673e5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmul-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-optimized" } */
+
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef short pixel16 __attribute__((vector_size(4)));
+
+vec16 foo1 () {
+  pixel a = { (unsigned char)1, (unsigned char)2, (unsigned char)3, (unsigned char)4 };
+  vec16 b = { (short)1, (short)2, (short)3, (short)4 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo1_1 () {
+  pixel a = { (unsigned char)1, (unsigned char)1, (unsigned char)1, (unsigned char)1 };
+  vec16 b = { (short)256, (short)512, (short)1024, (short)2048 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo1_2 () {
+  pixel a = { (unsigned char)255, (unsigned char)255, (unsigned char)255, (unsigned char)255 };
+  vec16 b = { (short)256, (short)512, (short)1024, (short)32767 };
+  return __builtin_vis_fmul8x16 (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16\t%" } } */
+/* { dg-final { scan-tree-dump "{ 0, 0, 0, 0 }" "optimized" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 4, 8 }" "optimized" } } */
+/* { dg-final { scan-tree-dump "{ 255, 510, 1020, 32639 }" "optimized" } } */
+
+vec16 foo2 () {
+  pixel a = { 1, 2, 3, 4 };
+  pixel16 b = { 256, 512 };
+  return __builtin_vis_fmul8x16au (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16au\t%" } } */
+/* { dg-final { scan-tree-dump "{ 1, 2, 3, 4 }" "optimized" } } */
+
+vec16 foo3 () {
+  pixel a = { 1, 2, 3, 4 };
+  pixel16 b = { 256, 512 };
+  return __builtin_vis_fmul8x16al (a, b);
+}
+/* { dg-final { scan-assembler-not "fmul8x16al\t%" } } */
+/* { dg-final { scan-tree-dump "{ 2, 4, 6, 8 }" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmul.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmul.c
new file mode 100644
index 000000000..71b3b17ac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpmul.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef unsigned char pixel __attribute__((vector_size(4)));
+typedef short pixel16 __attribute__((vector_size(4)));
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+vec16 foo1 (pixel a, vec16 b) {
+  return __builtin_vis_fmul8x16 (a, b);
+}
+
+vec16 foo2 (pixel a, pixel16 b) {
+  return __builtin_vis_fmul8x16au (a, b);
+}
+
+vec16 foo3 (pixel a, pixel16 b) {
+  return __builtin_vis_fmul8x16al (a, b);
+}
+
+vec16 foo4 (vec8 a, vec16 b) {
+  return __builtin_vis_fmul8sux16 (a, b);
+}
+
+vec16 foo5 (vec8 a, vec16 b) {
+  return __builtin_vis_fmul8ulx16 (a, b);
+}
+
+vec32 foo6 (pixel a, pixel16 b) {
+  return __builtin_vis_fmuld8sux16 (a, b);
+}
+
+vec32 foo7 (pixel a, pixel16 b) {
+  return __builtin_vis_fmuld8ulx16 (a, b);
+}
+
+/* { dg-final { scan-assembler "fmul8x16\t%" } } */
+/* { dg-final { scan-assembler "fmul8x16au\t%" } } */
+/* { dg-final { scan-assembler "fmul8x16al\t%" } } */
+/* { dg-final { scan-assembler "fmul8sux16\t%" } } */
+/* { dg-final { scan-assembler "fmul8ulx16\t%" } } */
+/* { dg-final { scan-assembler "fmuld8sux16\t%" } } */
+/* { dg-final { scan-assembler "fmuld8ulx16\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub16.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub16.c
new file mode 100644
index 000000000..05642dec1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub16\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub16s.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub16s.c
new file mode 100644
index 000000000..29e0d3e18
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub16s.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(4)));
+
+vec16 foo(vec16 a, vec16 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub16s\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub32.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub32.c
new file mode 100644
index 000000000..e1813f491
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(8)));
+
+vec32 foo(vec32 a, vec32 b)
+{
+  return a - b;
+}
+
+/* { dg-final { scan-assembler "fpsub32\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub32s.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub32s.c
new file mode 100644
index 000000000..c9d4ccc6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fpsub32s.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef int vec32 __attribute__((vector_size(4)));
+
+extern vec32 foo1(void);
+extern vec32 foo2(void);
+
+vec32 bar(void)
+{
+  return foo1 () - foo2 ();
+}
+
+/* { dg-final { scan-assembler "fpsub32s\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fshift.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fshift.c
new file mode 100644
index 000000000..1f032151c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fshift.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
+typedef int __v2si __attribute__((vector_size(8)));
+typedef short __v4hi __attribute__((vector_size(8)));
+
+__v4hi test_fsll16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fsll16 (x, y);
+}
+
+__v4hi test_fslas16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fslas16 (x, y);
+}
+
+__v4hi test_fsrl16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fsrl16 (x, y);
+}
+
+__v4hi test_fsra16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fsra16 (x, y);
+}
+
+__v2si test_fsll32 (__v2si x, __v2si y)
+{
+  return __builtin_vis_fsll32 (x, y);
+}
+
+__v2si test_fslas32 (__v2si x, __v2si y)
+{
+  return __builtin_vis_fslas32 (x, y);
+}
+
+__v2si test_fsrl32 (__v2si x, __v2si y)
+{
+  return __builtin_vis_fsrl32 (x, y);
+}
+
+__v2si test_fsra32 (__v2si x, __v2si y)
+{
+  return __builtin_vis_fsra32 (x, y);
+}
+
+/* { dg-final { scan-assembler "fsll16\t%" } } */
+/* { dg-final { scan-assembler "fslas16\t%" } } */
+/* { dg-final { scan-assembler "fsrl16\t%" } } */
+/* { dg-final { scan-assembler "fsra16\t%" } } */
+/* { dg-final { scan-assembler "fsll32\t%" } } */
+/* { dg-final { scan-assembler "fslas32\t%" } } */
+/* { dg-final { scan-assembler "fsrl32\t%" } } */
+/* { dg-final { scan-assembler "fsra32\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fucmp.c
new file mode 100644
index 000000000..6e8f1b341
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fucmp.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+long test_fucmple8 (vec8 a, vec8 b)
+{
+  return __builtin_vis_fucmple8 (a, b);
+}
+
+long test_fucmpne8 (vec8 a, vec8 b)
+{
+  return __builtin_vis_fucmpne8 (a, b);
+}
+
+long test_fucmpgt8 (vec8 a, vec8 b)
+{
+  return __builtin_vis_fucmpgt8 (a, b);
+}
+
+long test_fucmpeq8 (vec8 a, vec8 b)
+{
+  return __builtin_vis_fucmpeq8 (a, b);
+}
+
+/* { dg-final { scan-assembler "fucmple8\t%" } } */
+/* { dg-final { scan-assembler "fucmpne8\t%" } } */
+/* { dg-final { scan-assembler "fucmpgt8\t%" } } */
+/* { dg-final { scan-assembler "fucmpeq8\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxnor.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxnor.c
new file mode 100644
index 000000000..e635d65fd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxnor.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () ^ foo2_8 ());
+}
+
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return ~(a ^ b);
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () ^ foo2_16 ());
+}
+
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return ~(a ^ b);
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return ~(foo1_32 () ^ foo2_32 ());
+}
+
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return ~(a ^ b);
+}
+
+
+/* This should be transformed into ~(b ^ a).  */
+vec8 fun8b(void)
+{
+  return foo1_8 () ^ ~foo2_8 ();
+}
+
+vec8 fun8_2b(vec8 a, vec8 b)
+{
+  return a ^ ~b;
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () ^ ~foo2_16 ();
+}
+
+vec16 fun16_2b(vec16 a, vec16 b)
+{
+  return a ^ ~b;
+}
+
+vec32 fun32b(void)
+{
+  return foo1_32 () ^ ~foo2_32 ();
+}
+
+vec32 fun32_2b(vec32 a, vec32 b)
+{
+  return a ^ ~b;
+}
+
+/* { dg-final { scan-assembler-times "fxnor\t%" 12 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxnors.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxnors.c
new file mode 100644
index 000000000..29775cffe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxnors.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return ~(foo1_8 () ^ foo2_8 ());
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return ~(foo1_16 () ^ foo1_16 ());
+}
+
+
+/* This should be transformed into ~(b ^ a).  */
+vec8 fun8b(void)
+{
+  return foo1_8 () ^ ~foo2_8 ();
+}
+
+vec16 fun16b(void)
+{
+  return foo1_16 () ^ ~foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fxnors\t%" 4 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxor.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxor.c
new file mode 100644
index 000000000..6ca2f76a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxor.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char  vec8 __attribute__((vector_size(8)));
+typedef short vec16 __attribute__((vector_size(8)));
+typedef int   vec32 __attribute__((vector_size(8)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () ^ foo2_8 ();
+}
+
+vec8 fun8_2(vec8 a, vec8 b)
+{
+  return a ^ b;
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () ^ foo2_16 ();
+}
+
+vec16 fun16_2(vec16 a, vec16 b)
+{
+  return a ^ b;
+}
+
+extern vec32 foo1_32(void);
+extern vec32 foo2_32(void);
+
+vec32 fun32(void)
+{
+  return foo1_32 () ^ foo2_32 ();
+}
+
+vec32 fun32_2(vec32 a, vec32 b)
+{
+  return a ^ b;
+}
+
+/* { dg-final { scan-assembler-times "fxor\t%" 6 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxors.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxors.c
new file mode 100644
index 000000000..5da017a28
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/fxors.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+typedef char vec8 __attribute__((vector_size(4)));
+typedef short vec16 __attribute__((vector_size(4)));
+
+extern vec8 foo1_8(void);
+extern vec8 foo2_8(void);
+
+vec8 fun8(void)
+{
+  return foo1_8 () ^ foo2_8 ();
+}
+
+extern vec16 foo1_16(void);
+extern vec16 foo2_16(void);
+
+vec16 fun16(void)
+{
+  return foo1_16 () ^ foo1_16 ();
+}
+
+/* { dg-final { scan-assembler-times "fxors\t%" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/globalreg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/globalreg-1.c
new file mode 100644
index 000000000..3839d9f13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/globalreg-1.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -Os" } */
+
+/* This is a massively distilled test case based upon
+   mm/memory.c:unmap_vmas() in the Linux kernel when compiled
+   on sparc64 for SMP which uses a global register as the
+   base of the per-cpu variable area.
+
+   Because of a bug in global register handling in the dataflow
+   code, the loop-invariant pass would move 'expression(regval)'
+   outside of the loop.  */
+
+extern void exit(int);
+extern void abort(void);
+
+register unsigned long regval __asm__("g6");
+
+extern void cond_resched(void);
+
+unsigned int var;
+
+static unsigned long expression(unsigned long v)
+{
+  unsigned long ret;
+
+  __asm__("" : "=r" (ret) : "0" (0));
+  return ret + v;
+}
+
+void func(unsigned long *pp)
+{
+  int i;
+
+  for (i = 0; i < 56; i++) {
+    cond_resched();
+    *pp = expression(regval);
+  }
+}
+
+void __attribute__((noinline)) cond_resched(void)
+{
+	regval++;
+}
+
+int main(void)
+{
+  unsigned long val;
+
+  regval = 100;
+  func(&val);
+  if (val != 156)
+    abort();
+  exit(0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/lzd.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/lzd.c
new file mode 100644
index 000000000..bc2b8522b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/lzd.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
+int test_clz(int a)
+{
+  return __builtin_clz(a);
+}
+
+long test_clzl(long a)
+{
+  return __builtin_clzl(a);
+}
+
+long long test_clzll(long long a)
+{
+  return __builtin_clzll(a);
+}
+
+/* { dg-final { scan-assembler-times "lzd\t%" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/mfpu.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/mfpu.c
new file mode 100644
index 000000000..e95754c5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/mfpu.c
@@ -0,0 +1,11 @@
+/* Reported by Peter A. Krauss <peter.a.krauss@web.de> */
+
+/* { dg-do compile } */
+/* { dg-options "-mfpu" } */
+
+float square(float x)
+{
+  return x * x;
+}
+
+/* { dg-final { scan-assembler "fmuls" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/mnofpu.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/mnofpu.c
new file mode 100644
index 000000000..351585dd7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/mnofpu.c
@@ -0,0 +1,90 @@
+/* PR target/35664 */
+/* Tetstcase by Mike Stein <mstein.lists@googlemail.com> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-fpu" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+typedef unsigned int u32;
+typedef unsigned long long u64;
+struct pt_regs {
+};
+static inline __attribute__((always_inline)) struct task_struct *__get_current(void)
+{
+}
+static inline __attribute__((always_inline)) u32 flip_dword (u32 l)
+{
+ return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
+}
+static inline __attribute__((always_inline)) u32 __readl(const volatile void *addr)
+{
+ return flip_dword(*( volatile u32 *)addr);
+}
+enum e1e_registers {
+ E1000_PRC64 = 0x0405C,
+ E1000_PRC127 = 0x04060,
+ E1000_PRC255 = 0x04064,
+ E1000_PTC511 = 0x040E4,
+ E1000_PTC1023 = 0x040E8,
+ E1000_PTC1522 = 0x040EC,
+ E1000_MPTC = 0x040F0,
+};
+enum e1000_media_type {
+ e1000_media_type_copper = 1,
+};
+struct e1000_rx_desc {
+ struct {
+ } wb;
+};
+struct e1000_hw_stats {
+ u64 prc64;
+ u64 prc127;
+ u64 prc255;
+ u64 ptc511;
+ u64 ptc1023;
+ u64 ptc1522;
+ u64 mptc;
+};
+struct e1000_shadow_ram {
+ u16 value;
+};
+struct e1000_dev_spec_ich8lan {
+ struct e1000_shadow_ram shadow_ram[2048];
+};
+struct e1000_hw {
+ u8 *hw_addr;
+ union {
+  struct e1000_dev_spec_ich8lan ich8lan;
+ } dev_spec;
+ enum e1000_media_type media_type;
+};
+struct e1000_adapter {
+ u16 link_speed;
+ struct e1000_hw hw;
+ struct e1000_hw_stats stats;
+ unsigned int flags;
+};
+static inline __attribute__((always_inline)) u32 __er32(struct e1000_hw *hw, unsigned long reg)
+{
+ return __readl(hw->hw_addr + reg);
+}
+void e1000e_update_stats(struct e1000_adapter *adapter)
+{
+ struct e1000_hw *hw = &adapter->hw;
+ u16 phy_tmp;
+ if (adapter->flags & (1 << 10)) {
+  adapter->stats.prc64 += __er32(hw, E1000_PRC64);
+  adapter->stats.prc127 += __er32(hw, E1000_PRC127);
+  adapter->stats.prc255 += __er32(hw, E1000_PRC255);
+  adapter->stats.ptc511 += __er32(hw, E1000_PTC511);
+  adapter->stats.ptc1023 += __er32(hw, E1000_PTC1023);
+  adapter->stats.ptc1522 += __er32(hw, E1000_PTC1522);
+ }
+ adapter->stats.mptc += __er32(hw, E1000_MPTC);
+ if (hw->media_type == e1000_media_type_copper) {
+  if ((adapter->link_speed == 1000) &&
+     (!e1e_rphy(hw, 0x0A, &phy_tmp))) {
+  }
+ }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/noresult.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/noresult.c
new file mode 100644
index 000000000..1be7458d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/noresult.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef short vec16 __attribute__((vector_size(8)));
+
+void foo (vec16 a) {
+  __builtin_vis_fpack16 (a);
+}
+
+/* { dg-final { scan-assembler-not "fpack16\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist-2.c
new file mode 100644
index 000000000..b9cbb3461
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist-2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1 -fdump-tree-optimized" } */
+
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+#define _(A) (unsigned char)A
+
+int64_t foo () {
+  int64_t d = 2;
+  vec8 a = { _(1), _(2), _(3), _(4), _(5), _(6), _(7), _(255) };
+  vec8 b = { _(2), _(4), _(8), _(16), _(32), _(64), _(128), _(8) };
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+/* { dg-final { scan-assembler-not "pdist\t%" } } */
+/* { dg-final { scan-tree-dump "return 475" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist-3.c
new file mode 100644
index 000000000..03df4d96d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist-3.c
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O1" } */
+
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+extern void abort ();
+extern void exit (int);
+
+#define _(A) (unsigned char)A
+
+int64_t foo (vec8 a, vec8 b) {
+  int64_t d = 2;
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+int64_t bar () {
+  int64_t d = 2;
+  vec8 a = { _(1), _(2), _(3), _(4), _(5), _(6), _(7), _(255) };
+  vec8 b = { _(2), _(4), _(8), _(16), _(32), _(64), _(128), _(8) };
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+
+static vec8 a = { 1, 2, 3, 4, 5, 6, 7, 255 };
+static vec8 b = { 2, 4, 8, 16, 32, 64, 128, 8 };
+
+int main (int argc, char *argv[]) {
+
+  if (foo (a, b) != bar ())
+    abort ();
+
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist.c
new file mode 100644
index 000000000..6ecc20aa1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdist.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis" } */
+typedef long long int64_t;
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+int64_t foo (vec8 a, vec8 b) {
+  int64_t d = 0;
+  d = __builtin_vis_pdist (a, b, d);
+  return d;
+}
+
+int64_t bar (vec8 a, vec8 b) {
+  int64_t d = 0;
+  return __builtin_vis_pdist (a, b, d);
+}
+
+int64_t baz (vec8 a, vec8 b, int64_t d) {
+  int64_t e = __builtin_vis_pdist (a, b, d);
+  return e + d;
+}
+
+/* { dg-final { scan-assembler-times "pdist\t%" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdistn-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdistn-2.c
new file mode 100644
index 000000000..008496f9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdistn-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis3 -O1 -fdump-tree-optimized" } */
+
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+#define _(A) (unsigned char)A
+
+long foo () {
+  vec8 a = { _(1), _(2), _(3), _(4), _(5), _(6), _(7), _(255) };
+  vec8 b = { _(2), _(4), _(8), _(16), _(32), _(64), _(128), _(8) };
+  return __builtin_vis_pdistn (a, b);
+}
+
+/* { dg-final { scan-assembler-not "pdistn\t%" } } */
+/* { dg-final { scan-tree-dump "return 473" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdistn.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdistn.c
new file mode 100644
index 000000000..2f534f70b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/pdistn.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=ultrasparc -mvis3" } */
+
+typedef unsigned char vec8 __attribute__((vector_size(8)));
+
+long foo (vec8 a, vec8 b) {
+  return __builtin_vis_pdistn (a, b);
+}
+
+/* { dg-final { scan-assembler-times "pdistn\t%" 1 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/popc.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/popc.c
new file mode 100644
index 000000000..5442a610f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/popc.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=niagara2" } */
+int test_popcount(int a)
+{
+  return __builtin_popcount(a);
+}
+
+long test_popcountl(long a)
+{
+  return __builtin_popcountl(a);
+}
+
+long long test_popcountll(long long a)
+{
+  return __builtin_popcountll(a);
+}
+
+/* { dg-final { scan-assembler-times "popc\t%" 3 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/rdgsr.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/rdgsr.c
new file mode 100644
index 000000000..e67bdaccd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/rdgsr.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+
+long get_gsr (void)
+{
+	return __builtin_vis_read_gsr ();
+}
+
+/* { dg-final { scan-assembler "rd\t%gsr" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-1.c
new file mode 100644
index 000000000..6065bbb13
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-1.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int neq (int a, int b)
+{
+  return a != b;
+}
+
+int eq (int a, int b)
+{
+  return a == b;
+}
+
+int lt (unsigned int a, unsigned int b)
+{
+  return a < b;
+}
+
+int leq (unsigned int a, unsigned int b)
+{
+  return a <= b;
+}
+
+int geq (unsigned int a, unsigned int b)
+{
+  return a >= b;
+}
+
+int gt (unsigned int a, unsigned int b)
+{
+  return a > b;
+}
+
+/* { dg-final { scan-assembler-times "xor\t%" 2 } } */
+/* { dg-final { scan-assembler-times "subcc\t%" 2 } } */
+/* { dg-final { scan-assembler-times "addx\t%" 3 } } */
+/* { dg-final { scan-assembler-times "subx\t%" 3 } } */
+/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */
+/* { dg-final { scan-assembler-not "sra\t%" { target lp64 } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-2.c
new file mode 100644
index 000000000..cc17c65f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-2.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int neq (int a, int b)
+{
+  return -(a != b);
+}
+
+int eq (int a, int b)
+{
+  return -(a == b);
+}
+
+int lt (unsigned int a, unsigned int b)
+{
+  return -(a < b);
+}
+
+int leq (unsigned int a, unsigned int b)
+{
+  return -(a <= b);
+}
+
+int geq (unsigned int a, unsigned int b)
+{
+  return -(a >= b);
+}
+
+int gt (unsigned int a, unsigned int b)
+{
+  return -(a > b);
+}
+
+/* { dg-final { scan-assembler-times "xor\t%" 2 } } */
+/* { dg-final { scan-assembler-times "subcc\t%" 2 } } */
+/* { dg-final { scan-assembler-times "addx\t%" 3 } } */
+/* { dg-final { scan-assembler-times "subx\t%" 3 } } */
+/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */
+/* { dg-final { scan-assembler-not "sra\t%" { target lp64 } } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-3.c
new file mode 100644
index 000000000..8a26b675b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-3.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O1 -mvis3" } */
+
+int neq (long a, long b)
+{
+  return a != b;
+}
+
+int lt (unsigned long a, unsigned long b)
+{
+  return a < b;
+}
+
+int gt (unsigned long a, unsigned long b)
+{
+  return a > b;
+}
+
+/* { dg-final { scan-assembler "xor\t%" } } */
+/* { dg-final { scan-assembler "subcc\t%" } } */
+/* { dg-final { scan-assembler-times "addxc\t%" 3 } } */
+/* { dg-final { scan-assembler-times "cmp\t%" 2 } } */
+/* { dg-final { scan-assembler-not "sra\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-4.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-4.c
new file mode 100644
index 000000000..ffa4ee046
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-4.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O1 -mno-vis3" } */
+
+long neq (long a, long b)
+{
+  return a != b;
+}
+
+long eq (long a, long b)
+{
+  return a == b;
+}
+
+long lt (unsigned long a, unsigned long b)
+{
+  return a < b;
+}
+
+long leq (unsigned long a, unsigned long b)
+{
+  return a <= b;
+}
+
+long geq (unsigned long a, unsigned long b)
+{
+  return a >= b;
+}
+
+long gt (unsigned long a, unsigned long b)
+{
+  return a > b;
+}
+
+/* { dg-final { scan-assembler-times "xor\t%" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */
+/* { dg-final { scan-assembler-times "movrne\t%" 1 } } */
+/* { dg-final { scan-assembler-times "movre\t%" 1 } } */
+/* { dg-final { scan-assembler-times "movlu\t%" 1 } } */
+/* { dg-final { scan-assembler-times "movleu\t%" 1 } } */
+/* { dg-final { scan-assembler-times "movgeu\t%" 1 } } */
+/* { dg-final { scan-assembler-times "movgu\t%" 1 } } */
+/* { dg-final { scan-assembler-not "sra\t%" } } */
+/* { dg-final { scan-assembler-not "and\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-5.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-5.c
new file mode 100644
index 000000000..58f1ee39f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/setcc-5.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O1 -mvis3" } */
+
+long neq (long a, long b)
+{
+  return a != b;
+}
+
+long eq (long a, long b)
+{
+  return a == b;
+}
+
+long lt (unsigned long a, unsigned long b)
+{
+  return a < b;
+}
+
+long leq (unsigned long a, unsigned long b)
+{
+  return a <= b;
+}
+
+long geq (unsigned long a, unsigned long b)
+{
+  return a >= b;
+}
+
+long gt (unsigned long a, unsigned long b)
+{
+  return a > b;
+}
+
+/* { dg-final { scan-assembler-times "xor\t%" 2 } } */
+/* { dg-final { scan-assembler-times "cmp\t%" 4 } } */
+/* { dg-final { scan-assembler-times "addxc\t%" 3 } } */
+/* { dg-final { scan-assembler-times "movre\t%" 1 } } */
+/* { dg-final { scan-assembler-times "movleu\t%" 1 } } */
+/* { dg-final { scan-assembler-times "movgeu\t%" 1 } } */
+/* { dg-final { scan-assembler-not "sra\t%" } } */
+/* { dg-final { scan-assembler-not "and\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sibcall-dslot.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sibcall-dslot.c
new file mode 100644
index 000000000..db3401648
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sibcall-dslot.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+extern int one ();
+
+int some_n ()
+{
+    return one ();
+}
+
+/* { dg-final { scan-assembler-not "nop" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-align-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-align-1.c
new file mode 100644
index 000000000..14c915e1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-align-1.c
@@ -0,0 +1,31 @@
+/* PR target/31100 */
+/* Reported by Erwin Unruh <Erwin.Unruh@fujitsu-siemens.com> */
+
+/* { dg-do run } */
+/* { dg-options "-falign-labels=16" } */
+
+extern void abort(void);
+
+int f(int i)
+{
+  int res;
+
+  switch (i)
+    {
+    case 5:
+      res = i - i;
+      break;
+    default:
+      res = i * 2;
+      break;
+    }
+
+  return res;
+}
+
+int main(void)
+{
+  if (f(2) != 4)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c
new file mode 100644
index 000000000..a882ffbf3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-constant-1.c
@@ -0,0 +1,13 @@
+/* PR optimization/10876 */
+
+/* { dg-do compile } */
+
+/* Verify that adding the constant 4096 is turned
+   into subtracting the constant -4096. */
+
+int foo(int a)
+{
+  return a+4096;
+}
+
+/* { dg-final { scan-assembler "sub" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c
new file mode 100644
index 000000000..819ec3863
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-dwarf2.c
@@ -0,0 +1,32 @@
+/* PR target/10114 */
+/* Originator: James Troup <james@nocrew.org> */
+
+/* { dg-do compile } */
+/* { dg-options "-g -O1" } */
+
+extern __inline double sqrt (double __x)
+{
+  register double __r;
+  __asm ("fsqrtd %1,%0" : "=f" (__r) : "f" (__x));
+  return __r;
+}
+
+static double our_skew, max_update_skew;
+
+static double Sqr(double x)
+{
+  return x*x;
+}
+
+void REF_SetReference(double skew)
+{
+  double previous_skew, new_skew;
+  double old_weight, new_weight, sum_weight;
+  double delta_freq1, delta_freq2;
+  double skew1, skew2;
+
+  previous_skew = our_skew;
+  skew1 = sqrt((Sqr(delta_freq1) * old_weight + Sqr(delta_freq2) * new_weight) / sum_weight);
+  skew2 = (previous_skew * old_weight + new_skew * new_weight) / sum_weight;
+  our_skew = skew1 + skew2;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c
new file mode 100644
index 000000000..7aac1e26e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-frame-1.c
@@ -0,0 +1,13 @@
+/* PR target/24284 */
+
+/* { dg-do compile } */
+/* { dg-options "-O -g" } */
+
+void do_run(void *ip)
+{
+  char dummy[8192];
+
+  __asm__("" : : "g"(dummy));
+
+  goto *ip;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c
new file mode 100644
index 000000000..cd468c562
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-getcontext-1.c
@@ -0,0 +1,118 @@
+/* PR middle-end/22127 */
+/* Testcase by <akr@m17n.org> */
+
+/* { dg-do run { target *-*-solaris2.* } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O" } */
+
+typedef unsigned int size_t;
+extern int printf(const char *, ...);
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+typedef unsigned int uint_t;
+typedef char *caddr_t;
+typedef int greg_t;
+typedef greg_t gregset_t[19];
+struct rwindow {
+ greg_t rw_local[8];
+ greg_t rw_in[8];
+};
+typedef struct gwindows {
+ int wbcnt;
+ greg_t *spbuf[31];
+ struct rwindow wbuf[31];
+} gwindows_t;
+struct fpu {
+ union {
+  uint32_t fpu_regs[32];
+  double fpu_dregs[16];
+ } fpu_fr;
+ struct fq *fpu_q;
+ uint32_t fpu_fsr;
+ uint8_t fpu_qcnt;
+ uint8_t fpu_q_entrysize;
+ uint8_t fpu_en;
+};
+typedef struct fpu fpregset_t;
+typedef struct {
+ unsigned int xrs_id;
+ caddr_t xrs_ptr;
+} xrs_t;
+typedef struct {
+ gregset_t gregs;
+ gwindows_t *gwins;
+ fpregset_t fpregs;
+ xrs_t xrs;
+ long filler[19];
+} mcontext_t;
+typedef struct {
+ unsigned int __sigbits[4];
+} sigset_t;
+typedef struct sigaltstack {
+ void *ss_sp;
+ size_t ss_size;
+ int ss_flags;
+} stack_t;
+typedef struct ucontext ucontext_t;
+struct ucontext {
+ uint_t uc_flags;
+ ucontext_t *uc_link;
+ sigset_t uc_sigmask;
+ stack_t uc_stack;
+ mcontext_t uc_mcontext;
+ long uc_filler[23];
+};
+extern int getcontext(ucontext_t *);
+extern int setcontext(const ucontext_t *);
+
+int flag;
+ucontext_t cont;
+int pad[100];
+typedef void (*fun_t)(int);
+fun_t p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12;
+
+int global;
+
+extern void abort(void);
+
+void h1(int v)
+{
+  global = v;
+}
+
+void h2(int v)
+{
+  if (v != 1)
+    abort();
+}
+
+void f(void)
+{
+  flag = 1;
+  setcontext(&cont);
+}
+
+int g(void)
+{
+  int ret;
+
+  flag = 0;
+  getcontext(&cont);
+  ret = flag;
+  if (ret == 0) {
+    h1 (flag);
+    p0 = p1 = p2 = p3 = p4 = p5 = p6 = p7 = p8 = h1;
+    f();
+    p0(ret); p1(ret); p2(ret); p3(ret); p4(ret); p5(ret); p6(ret); p7(ret); p8(ret);
+  }
+  else {
+    h2 (flag);
+  }
+  return ret;
+}
+
+int main(void)
+{
+  g();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c
new file mode 100644
index 000000000..cb8d00762
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-loop-1.c
@@ -0,0 +1,19 @@
+/* PR optimization/10157 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+/* Verify that the loop optimizer doesn't
+   emit invalid reg-to-reg copy insns. */
+
+void g() {
+  while(1) {
+    int i,n;
+    double p,r;
+    for( i=0; i < n; i++ )
+      if( p > 1. )
+        for( i=0; i < n; i++ )
+          r += 2.;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c
new file mode 100644
index 000000000..0adb4cdca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-reg-1.c
@@ -0,0 +1,11 @@
+/* PR middle-end/20263 */
+
+/* { dg-do assemble } */
+/* { dg-options "" } */
+
+register void *tp __asm__("%g7");
+
+void set_tp(void)
+{
+  tp = 0;
+} 
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-ret.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-ret.c
new file mode 100644
index 000000000..f58b059e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-ret.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-skip-if "no register windows" { *-*-* } { "-mflat" } { "" } } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-mcpu=ultrasparc -O" } */
+
+/* Make sure that Ultrasparc return insn do not read below the stack.  */
+
+int bar (int a, int b, int c, int d, int e, int f, int g, int h)
+{
+  int res;
+
+  toto (&res);
+  return h;
+}
+/* { dg-final { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*ld\[ \t\]*\\\[%sp\\+96\\\]" } } */
+
+int bar2 ()
+{
+  int res;
+
+  toto (&res);
+  return res;
+}
+/* { dg-final { scan-assembler "return\[ \t\]*%i7\\+8\n\[^\n\]*nop" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c
new file mode 100644
index 000000000..82a86fbe1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc-trap-1.c
@@ -0,0 +1,21 @@
+/* PR target/15693 */
+
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+/* This used to fail on SPARC at -O2 because the combiner
+   produces a compare insn that was not rematched by the
+   compare expander.  */
+
+static __inline__ __attribute__ ((always_inline))
+int page_mapping (unsigned flags)
+{
+  if (1u & (flags >> 16))
+    return 1;
+  return 0;
+}
+void install_page (unsigned flags)
+{
+  if (__builtin_expect (!page_mapping (flags), 0))
+    __builtin_trap ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc.exp b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc.exp
new file mode 100644
index 000000000..e8b59fb86
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/sparc.exp
@@ -0,0 +1,52 @@
+# Copyright (C) 1997-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a SPARC target.
+if ![istarget sparc*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Return 1 if vis3 instructions can be compiled.
+proc check_effective_target_vis3 { } {
+    return [check_no_compiler_messages vis3 object {
+	long long
+	_vis3_fpadd64 (long long __X, long long __Y)
+	{
+	    return __builtin_vis_fpadd64 (__X, __Y);
+	}
+    } "-mcpu=niagara3 -mvis" ]
+}
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/struct-ret-check.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/struct-ret-check.c
new file mode 100644
index 000000000..00307fe29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/struct-ret-check.c
@@ -0,0 +1,126 @@
+/* Copyright (C) 2006 Free Software Foundation, Inc. */
+/* Contributed by Carlos O'Donell on 2006-03-14 */
+
+/* Test that GCC follows the SPARC 32-bit psABI with regards to
+   structure return checking in a callee. When -mstd-struct-return 
+   is specificed then gcc will emit code to skip the unimp insn. */ 
+
+/* Origin: Carlos O'Donell <carlos@codesourcery.com> */
+/* { dg-do run { target sparc*-*-solaris* sparc*-*-linux* sparc*-*-*bsd* } } */
+/* { dg-options "-mstd-struct-return" } */
+/* { dg-require-effective-target ilp32 } */
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+
+/* Local declaration of div_t structure */
+struct mydiv_t {
+  int rem;
+  int quot;
+};
+
+/* Global check variable used by signal handler */
+int check = 1;
+struct mydiv_t dcheck;
+
+struct mydiv_t foo (void)
+{
+  struct mydiv_t bar;
+  bar.rem = 3;
+  bar.quot = 4;
+  return bar;
+}
+
+void handle_sigill (int signum)
+{
+  if (signum == SIGILL && check == 2)
+    {
+      /* We expected a SIGILL due to a mismatch in unimp size
+	 and struct mydiv_t size */
+      exit (0);
+    }
+  else
+    abort ();
+}
+
+/* Implement 3 checks to validate SPARC 32-bit psABI callee 
+   returns struct
+   
+   Test1: Save area is valid. unimp size is valid.
+   Success: Save area modified correctly.
+   Failure: Save area unmodified.
+
+   Test2: Save area is valid. unimp size is invalid (invalid insn).
+   Success: Save area unmodified. check == 2.
+   Failure: Save area modified or check == 1.
+
+   Test3: Save area is invalid. unimp size is invalid (invalid size).
+   Success: Will raise a SIGILL. 
+   Failure: SIGSEGV caused by write to invalid save area. */
+
+int main (void)
+{
+  dcheck.rem = 1;
+  dcheck.quot = 2;
+
+  /*** Test1 ***/
+  /* Insert a call, insert unimp by hand */
+  __asm__ ("st %1, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "unimp %2\n\t" 
+	   : "=m" (dcheck)
+	   : "r" (&dcheck), "i" (sizeof(struct mydiv_t)) 
+	   : "memory");
+
+  /* If the caller doesn't adjust the return, then it crashes.
+     Check the result too. */
+
+  if ((dcheck.rem != 3) || (dcheck.quot !=4))
+    abort ();
+  
+
+  /*** Test 2 ***/
+  dcheck.rem = 1;
+  dcheck.quot = 2;
+
+  /* Ignore the return of the function */
+  __asm__ ("st %3, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "mov %2, %0\n\t"
+	   : "+r" (check), "=m" (dcheck) 
+	   : "i" (0x2), "r" (&dcheck)
+	   : "memory");
+
+  /* If the caller does an unconditional adjustment it will skip
+     the mov, and then we can fail the test based on check's value 
+     We pass a valid pointer to a save area in order to check if 
+     caller incorrectly wrote to the save area as well. There may
+     be a case where the unimp check and skip is correct, but the
+     write to the save area still occurs. */
+
+  if (check != 2)
+    abort ();
+
+  if ((dcheck.rem != 1) || (dcheck.quot != 2))
+    abort ();
+
+  /*** Test 3 ***/
+  /* Prepare a test that must SIGILL. According to the spec
+     if the sizes of the save area and return don't match then
+     the copy is ignored and we return to the unimp. */
+
+  signal (SIGILL, handle_sigill);
+
+  __asm__ ("st %%g0, [ %%sp + 0x40 ]\n\t"
+	   "call foo\n\t"
+	   " nop\n\t"
+	   "unimp %0\n\t"
+	   : /* No outputs */ 
+	   : "i" (sizeof(struct mydiv_t)-1) 
+	   : "memory");
+
+  /* NEVER REACHED */
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp1.c
new file mode 100644
index 000000000..7db750589
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp1.c
@@ -0,0 +1,8 @@
+/* Simplified from testcase by David Staepelaere <staapa@ultimatech.com> */
+
+/* { dg-do compile } */
+/* { dg-options -mcpu=ultrasparc } */
+
+int foo(long long y) {
+  return -1 * y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp10.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp10.c
new file mode 100644
index 000000000..d3edaca6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp10.c
@@ -0,0 +1,27 @@
+/* PR target/11965 */
+/* Originator: <jk@tools.de> */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O -mcpu=ultrasparc" } */
+
+/* This used to fail on 32-bit Ultrasparc because GCC emitted
+   an invalid shift instruction.  */
+
+
+static inline unsigned int shift(int n, unsigned int value)
+{
+  return value << n;
+}
+
+unsigned int val = 1;
+
+int main(void)
+{
+  int i;
+
+  for (i = 0; i < 4; i++)
+    val = shift(32, val);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp11.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp11.c
new file mode 100644
index 000000000..91e64782b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp11.c
@@ -0,0 +1,26 @@
+/* PR target/17245 */
+/* Origin: <aaronw@net.com> */
+/* Testcase by Christian Ehrhardt <ehrhardt@mathematik.uni-ulm.de> */
+
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=v9" } */
+
+/* This used to fail on 32-bit Ultrasparc because reload was emitting
+   a move insn that doesn't satisfy its constraints.  */
+
+int n; 
+double range ;
+double bin ;
+double wmean;
+
+double f ()
+{
+  int i ;
+  long double W = 0 ;
+  for ( i = 0 ; i < n ; i ++) {
+    double xi = range;
+    double wi = bin;
+    W += wi ;
+    wmean += ( xi - wmean) * ( wi / W);
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp12.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp12.c
new file mode 100644
index 000000000..6c37f5662
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp12.c
@@ -0,0 +1,64 @@
+/* PR rtl-optimization/48830 */
+/* Testcase by Hans-Peter Nilsson <hp@gcc.gnu.org> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+typedef unsigned char uint8_t;
+typedef unsigned int uint32_t;
+typedef unsigned long int uint64_t;
+typedef unsigned long int uintmax_t;
+typedef unsigned char rc_vec_t __attribute__((__vector_size__(8)));
+typedef short rc_svec_type_ __attribute__((__vector_size__(8)));
+typedef unsigned char rc_vec4_type_ __attribute__((__vector_size__(4)));
+
+void
+rc_stat_xsum_acc(const uint8_t *__restrict src1, int src1_dim,
+                 const uint8_t *__restrict src2, int src2_dim,
+                 int len, int height, uintmax_t sum[5])
+{
+    uint32_t s1 = 0;
+    uint32_t s2 = 0;
+    uintmax_t s11 = 0;
+    uintmax_t s22 = 0;
+    uintmax_t s12 = 0;
+    int full = len / ((1024) < (1024) ? (1024) : (1024));
+    int rem = len % ((1024) < (1024) ? (1024) : (1024));
+    int rem1 = rem / 1;
+    int y;
+    unsigned int rc_gsr_scale_ __attribute__ ((__unused__)) = 7; unsigned int rc_gsr_align_ __attribute__ ((__unused__)) = 4; unsigned int rc_gsr_set_ __attribute__ ((__unused__)) = 0; register unsigned int rc_gsr_fakedep_ __attribute__ ((__unused__)) = 0; unsigned int rc_gsr_ldinit_ __attribute__ ((__unused__)) = 0;
+    for (y = 0; y < height; y++) {
+        rc_vec_t a1, a2, a11, a22, a12;
+        int i1 = (y)*(src1_dim);
+        int i2 = (y)*(src2_dim);
+        int x;
+        ((a1) = ((rc_vec_t) {0}));
+        ((a2) = ((rc_vec_t) {0}));
+        ((a11) = ((rc_vec_t) {0}));
+        ((a22) = ((rc_vec_t) {0}));
+        ((a12) = ((rc_vec_t) {0}));
+        for (x = 0; x < full; x++) {
+            int k;
+            for (k = 0; k < ((1024) < (1024) ? (1024) : (1024)) /
+                            1; k++)
+            {
+                do { rc_vec_t v1, v2; ((v1) = *(const rc_vec_t*)(&(src1)[i1])); ((v2) = *(const rc_vec_t*)(&(src2)[i2])); ((a1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v1, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)))).v)); ((a2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v2, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)))).v)); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v1); rc_vec_t accvin_ = (a11); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a11) = accvout_; } while (0); do { rc_vec_t s1_ = (v2); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a22); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a22) = accvout_; } while (0); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a12); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a12) = accvout_; } while (0); (i1) += 8; (i2) += 8; } while (0);
+
+            }
+            do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
+        }
+        for (x = 0; x < rem1; x++) {
+            do { rc_vec_t v1, v2; ((v1) = *(const rc_vec_t*)(&(src1)[i1])); ((v2) = *(const rc_vec_t*)(&(src2)[i2])); ((a1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v1, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)))).v)); ((a2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(__builtin_vis_pdist (v2, ((rc_vec_t) {0}), (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)))).v)); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v1); rc_vec_t accvin_ = (a11); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a11) = accvout_; } while (0); do { rc_vec_t s1_ = (v2); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a22); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a22) = accvout_; } while (0); do { rc_vec_t s1_ = (v1); rc_vec_t s2_ = (v2); rc_vec_t accvin_ = (a12); rc_vec_t s1lo7_, s1msb_, accvout_; uint32_t maclo_, machi_; rc_svec_type_ masklow_ = (rc_svec_type_){(255), (255), (255), (255)}; rc_svec_type_ s1msbhi_, s1msblo_, s1lo7hi_, s1lo7lo_; rc_svec_type_ s1msbdiv2hi_, s1msbdiv2lo_; rc_vec4_type_ s1lo7hi4_, s1lo7lo4_, s1msbhi4_, s1msblo4_; rc_vec4_type_ s1msbdiv2hi4_, s1msbdiv2lo4_, s2hi4_, s2lo4_; rc_vec4_type_ accvhi4_, accvlo4_; rc_svec_type_ mulhilo7_, mullolo7_, mulhimsbdiv2_, mullomsbdiv2_; rc_svec_type_ mulhi_, mullo_, mulhihi_, mullohi_; rc_svec_type_ mulhilo_, mullolo_; rc_vec4_type_ zero4_ = (((union { rc_vec4_type_ v; uint64_t i; })(uint64_t)(0)).v); rc_vec_t msb_ = (rc_vec_t){(0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80), (0x80)}; ((s1msb_) = (s1_) & (msb_)); ((s1lo7_) = (s1_) & (~msb_)); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1msb_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1msb_) : "0" (s1msb_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1msb_); (s1msbhi4_) = hl_.hilo_.hi_; (s1msblo4_) = hl_.hilo_.lo_; } while (0); s1msbhi_ = __builtin_vis_fexpand(s1msbhi4_); s1msblo_ = __builtin_vis_fexpand(s1msblo4_); s1msbdiv2hi4_ = __builtin_vis_fpack16(s1msbhi_); s1msbdiv2lo4_ = __builtin_vis_fpack16(s1msblo_); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2_); (s2hi4_) = hl_.hilo_.hi_; (s2lo4_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1lo7_); (s1lo7hi4_) = hl_.hilo_.hi_; (s1lo7lo4_) = hl_.hilo_.lo_; } while (0); s1msbdiv2hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2hi4_, zero4_); s1msbdiv2lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1msbdiv2lo4_, zero4_); s1lo7hi_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7hi4_, zero4_); s1lo7lo_ = (rc_svec_type_)__builtin_vis_fpmerge(s1lo7lo4_, zero4_); mulhilo7_ = __builtin_vis_fmul8x16(s2hi4_, s1lo7hi_); mullolo7_ = __builtin_vis_fmul8x16(s2lo4_, s1lo7lo_); mulhimsbdiv2_ = __builtin_vis_fmul8x16(s2hi4_, s1msbdiv2hi_); mullomsbdiv2_ = __builtin_vis_fmul8x16(s2lo4_, s1msbdiv2lo_); mulhi_ = mulhilo7_ + mulhimsbdiv2_ + mulhimsbdiv2_; mullo_ = mullolo7_ + mullomsbdiv2_ + mullomsbdiv2_; mulhihi_ = mulhi_ & ~masklow_; mulhilo_ = mulhi_ & masklow_; mullohi_ = mullo_ & ~masklow_; mullolo_ = mullo_ & masklow_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (accvin_); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); maclo_ = __builtin_vis_pdist ((rc_vec_t)mullolo_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i)); maclo_ = __builtin_vis_pdist ((rc_vec_t)mulhilo_, ((rc_vec_t) {0}), maclo_); machi_ = __builtin_vis_pdist ((rc_vec_t)mullohi_, ((rc_vec_t) {0}), (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i)); machi_ = __builtin_vis_pdist ((rc_vec_t)mulhihi_, ((rc_vec_t) {0}), machi_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)machi_)).v)), ((((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)((uint32_t)maclo_)).v))}}; (accvout_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (accvout_), "0" (rc_gsr_fakedep_)); (a12) = accvout_; } while (0); (i1) += 8; (i2) += 8; } while (0);
+        }
+        do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
+
+        do { uint32_t t1, t2, t11, t22, t12; ((t1) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a1)).i)); ((t2) = (((union { rc_vec_t v; uint64_t i; })(uint64_t)(a2)).i)); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a11); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t11) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a22); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t22) = maclo_ + machi_ * 256; } while (0); do { rc_vec4_type_ accvhi4_, accvlo4_; uint64_t machi_, maclo_; do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (a12); (accvhi4_) = hl_.hilo_.hi_; (accvlo4_) = hl_.hilo_.lo_; } while (0); machi_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvhi4_)).i); maclo_ = (((union { rc_vec4_type_ v; uint32_t i; })(uint32_t)(accvlo4_)).i); (t12) = maclo_ + machi_ * 256; } while (0); ((a1) = ((rc_vec_t) {0})); ((a2) = ((rc_vec_t) {0})); ((a11) = ((rc_vec_t) {0})); ((a22) = ((rc_vec_t) {0})); ((a12) = ((rc_vec_t) {0})); (s1) += t1; (s2) += t2; (s11) += t11; (s22) += t22; (s12) += t12; } while (0);
+    }
+    sum[0] = s1;
+    sum[1] = s2;
+    sum[2] = s11;
+    sum[3] = s22;
+    sum[4] = s12;
+    ;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp13.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp13.c
new file mode 100644
index 000000000..2a068546c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp13.c
@@ -0,0 +1,23 @@
+/* PR rtl-optimization/48840 */
+/* Testcase by Hans-Peter Nilsson <hp@gcc.gnu.org> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */
+
+typedef unsigned char uint8_t;
+
+typedef unsigned char rc_vec_t __attribute__((__vector_size__(8)));
+typedef short rc_svec_type_ __attribute__((__vector_size__(8)));
+
+typedef unsigned char rc_vec4_type_ __attribute__((__vector_size__(4)));
+typedef short rc_svec2_type_ __attribute__((__vector_size__(4)));
+
+void
+rc_filter_sobel_3x3_horz_u8(uint8_t *__restrict dst, int dst_dim,
+                            const uint8_t *__restrict src, int src_dim,
+                            int width, int height)
+{
+    do { int tot = (((width) + (8) - 1) / (8)); int len = tot / 3; int rem = tot % 3; int y; unsigned int rc_gsr_scale_ __attribute__ ((__unused__)) = 7; unsigned int rc_gsr_align_ __attribute__ ((__unused__)) = 4; unsigned int rc_gsr_set_ __attribute__ ((__unused__)) = 0; register unsigned int rc_gsr_fakedep_ __attribute__ ((__unused__)) = 0; unsigned int rc_gsr_ldinit_ __attribute__ ((__unused__)) = 0; for (y = 0; y < (height); y++) { rc_vec_t v11, v12, v13; rc_vec_t v21, v22, v23; rc_vec_t v31, v32, v33; rc_vec_t s1, s2, s3; int j = y*(dst_dim); int i2 = y*(src_dim) + 8; int i1 = i2 - (src_dim); int i3 = i2 + (src_dim); int x; ((s1) = *(const rc_vec_t*)(&(src)[i1 - 2*8])); ((s2) = *(const rc_vec_t*)(&(src)[i2 - 2*8])); ((s3) = *(const rc_vec_t*)(&(src)[i3 - 2*8])); do { do { rc_vec_t s1_ = (s1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v21) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); } while (0); ((s1) = *(const rc_vec_t*)(&(src)[i1 - 8])); ((s2) = *(const rc_vec_t*)(&(src)[i2 - 8])); ((s3) = *(const rc_vec_t*)(&(src)[i3 - 8])); do { do { rc_vec_t s1_ = (s1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v12) = dstv_; } while (0); do { rc_vec_t s1_ = (v12); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v22) = dstv_; } while (0); do { rc_vec_t s1_ = (v12); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v12) = dstv_; } while (0); } while (0); ((v13) = ((rc_vec_t) {0})); ((v23) = ((rc_vec_t) {0})); ((v33) = ((rc_vec_t) {0})); (void)v21, (void)v22; (void)v31, (void)v32; for (x = 0; x < len; x++) { do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v13) = dstv_; } while (0); do { rc_vec_t s1_ = (v13); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v23) = dstv_; } while (0); do { rc_vec_t s1_ = (v13); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v13) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v12); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v11, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v23); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v22, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v21) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v13); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v12, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v21); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v23, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v12) = dstv_; } while (0); do { rc_vec_t s1_ = (v12); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v22) = dstv_; } while (0); do { rc_vec_t s1_ = (v12); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v12) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v11); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v13, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v22); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v21, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); } if (rem > 0) { do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v13) = dstv_; } while (0); do { rc_vec_t s1_ = (v13); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v23) = dstv_; } while (0); do { rc_vec_t s1_ = (v13); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v13) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v12); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v11, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v23); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v22, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); } if (rem > 1) { do { rc_vec_t p1, p2, p3, sum; ((p1) = *(const rc_vec_t*)(&(src)[i1])); ((p2) = *(const rc_vec_t*)(&(src)[i2])); ((p3) = *(const rc_vec_t*)(&(src)[i3])); do { do { rc_vec_t s1_ = (p1); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p3); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_) + (rc_svec_type_){(16), (16), (16), (16)}; los_ = (lo1_) + (lo2_) + (rc_svec_type_){(16), (16), (16), (16)}; hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v21) = dstv_; } while (0); do { rc_vec_t s1_ = (v11); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (p2); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = (hi1_) + (hi2_); los_ = (lo1_) + (lo2_); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (v11) = dstv_; } while (0); } while (0); do { rc_vec_t u12, u23; do { rc_vec_t shv_; do { rc_vec_t v_ = (v13); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(8 - 1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (8 - 1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (8 - 1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v12, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u12) = dstv_; } while (0); } while (0); do { rc_vec_t shv_; do { rc_vec_t v_ = (v21); do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(1) || !__builtin_constant_p(rc_gsr_scale_) || !rc_gsr_set_ || (unsigned) (1) != rc_gsr_align_ || (unsigned) (rc_gsr_scale_) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (1); rc_gsr_scale_ = (rc_gsr_scale_); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (v_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (v_) : "0" (v_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); (shv_) = v_; } while (0); do { rc_vec_t dstv_ = __builtin_vis_faligndatav8qi(v23, shv_); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (u23) = dstv_; } while (0); } while (0); do { rc_vec_t s1_ = (u23); rc_vec_t dstv_; rc_vec4_type_ hi_, lo_; rc_vec4_type_ s1hi_, s1lo_; rc_vec4_type_ s2hi_, s2lo_; rc_svec_type_ hi1_, hi2_, lo1_, lo2_, his_, los_; do { if (rc_gsr_ldinit_) { extern void rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(void); rc_mixing_GSR_setting_with_RC_VEC_LDINIT_(); } if (!__builtin_constant_p(rc_gsr_align_) || !__builtin_constant_p(2) || !rc_gsr_set_ || (unsigned) (rc_gsr_align_) != rc_gsr_align_ || (unsigned) (2) != rc_gsr_scale_) { rc_gsr_set_ = 1; rc_gsr_align_ = (rc_gsr_align_); rc_gsr_scale_ = (2); unsigned int val_ = (rc_gsr_scale_ << 3) | rc_gsr_align_; if (__builtin_constant_p (val_)) { __asm__("wr %%g0,%[gsrval],%%gsr\n" ";# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "i" (val_), "1" (rc_gsr_fakedep_)); } else { __asm__("wr %[gsrval],0,%%gsr" "\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_), [fakegsr] "=rm" (rc_gsr_fakedep_) : "0" (s1_), [gsrval] "r" (val_), "1" (rc_gsr_fakedep_)); } } else { __asm__("\n;# dep %[depvec] on fake GSR %[fakegsr]" : [depvec] "=brm" (s1_) : "0" (s1_), [fakegsr] "g" (rc_gsr_fakedep_)); } } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (s1_); (s1hi_) = hl_.hilo_.hi_; (s1lo_) = hl_.hilo_.lo_; } while (0); do { typedef union { rc_vec_t v_; struct { rc_vec4_type_ hi_, lo_; } hilo_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) (u12); (s2hi_) = hl_.hilo_.hi_; (s2lo_) = hl_.hilo_.lo_; } while (0); hi1_ = __builtin_vis_fexpand(s1hi_); lo1_ = __builtin_vis_fexpand(s1lo_); hi2_ = __builtin_vis_fexpand(s2hi_); lo2_ = __builtin_vis_fexpand(s2lo_); his_ = ((hi1_) - (hi2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); los_ = ((lo1_) - (lo2_) + (rc_svec_type_){(256*16), (256*16), (256*16), (256*16)}); hi_ = __builtin_vis_fpack16(his_); lo_ = __builtin_vis_fpack16(los_); do { typedef union { struct { rc_vec4_type_ hi_, lo_; } hilo_; rc_vec_t v_; } RC_hl_type_; RC_hl_type_ hl_ = (RC_hl_type_) {{(hi_), (lo_)}}; (dstv_) = hl_.v_; } while (0); __asm__("\n;# dep fake GSR %[fakegsr] on %[xdep]" : [fakegsr] "=brm" (rc_gsr_fakedep_) : [xdep] "brm" (dstv_), "0" (rc_gsr_fakedep_)); (sum) = dstv_; } while (0); } while (0); (*(rc_vec_t*)(&(dst)[j]) = (sum)); (i1) += 8; (i2) += 8; (i3) += 8; (j) += 8; } while (0); } } ; } while (0);
+
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp2.c
new file mode 100644
index 000000000..24202ba5a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp2.c
@@ -0,0 +1,11 @@
+/* Copyright (C) 1999 Free Software Foundation
+   by Alexandre Oliva <oliva@lsd.ic.unicamp.br>
+   Simplified from libg++/src/Fix16.cc */
+
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+
+short foo() {
+  short i = (short)(1<<15);
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp3.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp3.c
new file mode 100644
index 000000000..870258813
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp3.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-skip-if "" { ! { ilp32 && ultrasparc_hw } } } */
+/* { dg-options "-mcpu=ultrasparc -mv8plus" } */
+
+extern void abort (void);
+extern void exit (int);
+
+unsigned long long foo (unsigned long long x)
+{
+  return 0x73500000735LL * x;
+}
+
+unsigned long long a, b;
+unsigned long p;
+
+unsigned long long bar (void)  
+{
+  unsigned long long c = a | b;
+  return 0x73500000735LL * c;
+}
+
+unsigned long long baz (void)
+{
+  unsigned long long c = (p + 345) & -2;
+  return c * a;
+}
+
+int main (void)
+{
+  if (foo (0x56789LL) != 0x26f32e5d26f32e5dLL)
+    abort ();
+  a = 0x8000000080000000LL;
+  b = 0x0000000180000001LL;
+  if (bar () != 0x120480000735LL)
+    abort ();
+  p = 0xffffffff;
+  if (baz () != 0xac00000000LL)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp4.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp4.c
new file mode 100644
index 000000000..f3958cbe7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp4.c
@@ -0,0 +1,12 @@
+/* Simplified from PR target/5309.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+extern long bar (unsigned int);
+
+long
+foo (long x, unsigned int y)
+{
+  return *(((long *) (bar (y) - 1)) + 1 + (x >> 2) % 359);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp5.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp5.c
new file mode 100644
index 000000000..feb6cf244
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp5.c
@@ -0,0 +1,13 @@
+/* PR target/10072 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -O1 -mcpu=ultrasparc -ffast-math" } */
+
+void p(int v)
+{
+  int i=v,j;
+  float a,b,c,x[i];
+
+  x[i] = (a/(((b)>(c)) ? (b) : (c)) - (((i) == (j)) ? 1.f : 0.f));
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp6.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp6.c
new file mode 100644
index 000000000..ad341dc16
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp6.c
@@ -0,0 +1,151 @@
+/* PR target/7784 */
+/* Originator: Peter van Hoof <p.van-hoof@qub.ac.uk> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+typedef struct
+{
+  float EnergyErg;
+  float ots;
+} EmLine;
+
+extern const int ipH_LIKE ;
+extern const int ipHYDROGEN ;
+extern const int ipH1s;
+extern const int ipH2s;
+extern const int ipH2p;
+
+extern EmLine ****EmisLines;
+
+typedef struct
+{
+  long n;
+  long s;
+  long l;
+} Elevels;
+
+extern struct t_iso
+{
+  float ***Pop2Ion;
+  long int numLevels[2][30L];
+} iso;
+
+extern struct t_LineSave
+{
+  long int nsum;
+  long int ndsum;
+  long int nComment;
+  long int npxdd;
+  long int ipass;
+  char chHoldComments[10][200];
+} LineSave;
+
+extern struct t_hydro
+{
+  int lgHydEmiss;
+  float **pestrk ;
+} hydro;
+
+extern struct t_dense
+{
+  double DensityLaw[10];
+  float frad[500];
+  float fhden[500];
+  float den0;
+  double eden;
+} dense;
+
+extern struct t_abund
+{
+  float xIonFracs[30L +3][30L +1];
+} abund;
+
+extern struct t_CaseBHS
+{
+  long int nDensity[2][8] , ntemp[2][8] , ncut[2][8] ;
+  int lgHCaseBOK[2][8];
+} CaseBHS ;
+
+extern struct t_smbeta
+{
+  float SimHBeta,
+    cn4861,
+    cn1216,
+    sv4861,
+    sv1216;
+} smbeta;
+
+extern struct t_phycon
+{
+  float te;
+} phycon;
+
+
+extern struct t_sphere
+{
+  int lgSphere;
+  float covgeo;
+} sphere;
+
+void linadd(double xInten, float wavelength, char *chLab, char chInfo);
+
+extern struct t_radiusVar
+{
+  int lgDrNeg;
+  double dVeff;
+} radius;
+
+void lines_hydro(void)
+{
+  long int i, nelem, ipHi, ipLo;
+  double hbetab, em , EmisFac, pump;
+  char chLabel[5];
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][3]*hydro.pestrk[3][2]*3.025e-12, 6563,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][4]*hydro.pestrk[4][2]*4.084e-12, 4861,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][4]*hydro.pestrk[4][3]*1.059e-12, 18751,"Strk",'i');
+
+  linadd(abund.xIonFracs[ipHYDROGEN][1]*iso.Pop2Ion[ipH_LIKE][ipHYDROGEN][5]*hydro.pestrk[5][4]*4.900e-13, 40512,"Strk",'i');
+
+  ((void)((LineSave.ipass <1 || EmisLines[ipH_LIKE][ipHYDROGEN][ipH2p][ipH1s].ots>= 0.) || (__assert("LineSave.ipass <1 || EmisLines[ipH_LIKE][ipHYDROGEN][ipH2p][ipH1s].ots>= 0.", "lines_hydro.c", 118), 0)));
+
+  linadd(EmisLines[ipH_LIKE][ipHYDROGEN][3][ipH2s].ots*EmisLines[ipH_LIKE][ipHYDROGEN][3][ipH2s].EnergyErg, 6563,"Dest",'i');
+
+  linadd(EmisLines[ipH_LIKE][ipHYDROGEN][5][4].ots*EmisLines[ipH_LIKE][ipHYDROGEN][5][4].EnergyErg,40516, "Dest",'i');
+
+  smbeta.SimHBeta = smbeta.SimHBeta/(float)radius.dVeff*sphere.covgeo;
+
+  linadd(smbeta.SimHBeta,4861,"Q(H)",'i');
+
+  smbeta.SimHBeta = smbeta.SimHBeta*(float)radius.dVeff/sphere.covgeo;
+
+  for( nelem=0; nelem < 30L; nelem++ )
+  {
+    int iCase;
+    for( iCase=0; iCase<2; ++iCase )
+    {
+      char chAB[2]={'A','B'};
+      char chLab[5]="Ca  ";
+
+      for( ipLo=1+iCase; ipLo<(((6)<(iso.numLevels[ipH_LIKE][nelem])) ? (6) : (5)); ++ipLo )
+      {
+        for( ipHi=ipLo+1; ipHi< (((ipLo+5)<(iso.numLevels[ipH_LIKE][nelem])) ? (ipLo+5) : (iso.numLevels[ipH_LIKE][nelem])); ++ipHi )
+        {
+          float wl;
+
+          hbetab = HSRate( ipHi,ipLo , nelem+1, phycon.te , dense.eden, chAB[iCase] );
+          if( hbetab<=0. )
+            CaseBHS.lgHCaseBOK[iCase][nelem] = 0;
+
+          if( !hydro.lgHydEmiss )
+            hbetab *= abund.xIonFracs[nelem][nelem+1]*dense.eden;
+
+         linadd(hbetab,wl,chLab,'i' );
+        }
+      }
+    }
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp7.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp7.c
new file mode 100644
index 000000000..b5a17b448
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp7.c
@@ -0,0 +1,51 @@
+/* PR c/8281 */
+/* Originator: TANIGUCHI Yasuaki <yasuaki@k8.dion.ne.jp> */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target fpic } */
+/* { dg-options "-O2 -mcpu=ultrasparc -fPIC" } */
+
+static const double bp = 1.0, dp_l[] = { 0.0 };
+
+double __ieee754_pow(double x, double y)
+{
+  union {
+    int lo;
+    double d;
+  }uz;
+
+  double y1,t1,p_h,t,z;
+  double z_h,z_l,p_l;
+  double t2,r,s,u,v,w;
+  int i = 0;
+ 
+  double s_h,t_h;
+  double s2,s_l,t_l;
+ 
+ 
+  v = 1.0/(v+bp);
+  uz.d = s_h = s = u*v;
+  uz.lo = 0;
+  s_h = uz.d;
+  uz.d = t_h;
+  uz.lo = 3;
+  t_h = uz.d;
+  s_l = v*((u-s_h*t_h)-s_h*t_l);
+  s2 = s*s;
+  r = s2* s2* (1.1+s2*(1.2+s2*(1.3+s2*(1.4+s2*(1.5+s2*1.6)))));
+  s2 = s_h*s_h;
+  uz.lo = 0;
+  t_h = uz.d;
+  t_l = r-((t_h-3.0)-s2);
+  v = s_l*t_h+t_l*s;
+  p_l = v-(p_h-u);
+  z_h = bp *p_h;
+  z_l = bp*p_h+p_l*1.0+dp_l[i];
+  t = (double)i;
+  t1 = (((bp+z_l)+bp)+t);
+  t2 = z_l-(((t1-t)-bp)-z_h);
+  p_l = (y-y1)*t1+y*t2;
+  z = p_l+p_h;
+
+  return s*z;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp8.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp8.c
new file mode 100644
index 000000000..a8bfefee5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp8.c
@@ -0,0 +1,40 @@
+/* PR target/10067 */
+/* Originator: <dat94ali@ludat.lth.se> */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -mtune=supersparc" } */
+
+struct _reent;
+
+extern unsigned long __malloc_trim_threshold;
+extern unsigned long __malloc_top_pad;
+
+int _mallopt_r(struct _reent *reent_ptr, int param_number, int value)
+{
+  __malloc_lock(reent_ptr);
+
+  switch(param_number)
+  {
+    case -1:
+      __malloc_trim_threshold = value;
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -2:
+      __malloc_top_pad = value;
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -3:
+      __malloc_unlock(reent_ptr);
+      return 1;
+
+    case -4:
+      __malloc_unlock(reent_ptr);
+      return value == 0;
+
+    default:
+      __malloc_unlock(reent_ptr);
+      return 0;
+  }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp9.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp9.c
new file mode 100644
index 000000000..b26d7dce1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/ultrasp9.c
@@ -0,0 +1,41 @@
+/* PR optimization/11018 */
+/* Originator: <partain@dcs.gla.ac.uk> */
+
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-O2 -mcpu=ultrasparc" } */
+
+/* This used to fail on 32-bit Ultrasparc because
+   of broken DImode shift patterns.  */
+
+extern void abort(void);
+
+typedef unsigned long long uint64_t;
+typedef unsigned int size_t;
+
+
+void to_octal (uint64_t value, char *where, size_t size)
+{
+  uint64_t v = value;
+  size_t i = size;
+
+  do
+    {
+      where[--i] = '0' + (v & ((1 << 3) - 1));
+      v >>= 3;
+    }
+  while (i);
+}
+
+
+int main (void)
+{
+  char buf[8];
+
+  to_octal(010644, buf, 6);
+
+  if (buf[1] != '1')
+     abort();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis1.c
new file mode 100644
index 000000000..4202bfa6e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis1.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O2" } */
+
+#include "vec-init-1.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis2.c
new file mode 100644
index 000000000..a5c213239
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis2.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_vis2_hw } */
+/* { dg-options "-mcpu=ultrasparc3 -O2" } */
+
+#include "vec-init-1.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis3.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis3.c
new file mode 100644
index 000000000..ab916e052
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1-vis3.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_vis3_hw } */
+/* { dg-options "-mcpu=niagara3 -O2" } */
+
+#include "vec-init-1.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1.inc b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1.inc
new file mode 100644
index 000000000..e27bb6e29
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-1.inc
@@ -0,0 +1,85 @@
+typedef int __v1si __attribute__ ((__vector_size__ (4)));
+typedef int __v2si __attribute__ ((__vector_size__ (8)));
+typedef short __v2hi __attribute__ ((__vector_size__ (4)));
+typedef short __v4hi __attribute__ ((__vector_size__ (8)));
+typedef unsigned char __v4qi __attribute__ ((__vector_size__ (4)));
+typedef unsigned char __v8qi __attribute__ ((__vector_size__ (8)));
+
+extern void abort (void);
+
+static void
+compare64 (void *p, unsigned long long val)
+{
+  if (*(unsigned long long *)p != val)
+    abort();
+}
+
+static void
+compare32 (void *p, unsigned int val)
+{
+  if (*(unsigned int *)p != val)
+    abort();
+}
+
+static void
+test_v8qi (unsigned char x)
+{
+  __v8qi v = { x, x, x, x, x, x, x, x };
+
+  compare64(&v, 0x4444444444444444ULL);
+}
+
+static void
+test_v4qi (unsigned char x)
+{
+  __v4qi v = { x, x, x, x };
+
+  compare32(&v, 0x44444444);
+}
+
+static void
+test_v4hi (unsigned short x)
+{
+  __v4hi v = { x, x, x, x, };
+
+  compare64(&v, 0x3344334433443344ULL);
+}
+
+static void
+test_v2hi (unsigned short x)
+{
+  __v2hi v = { x, x, };
+
+  compare32(&v, 0x33443344);
+}
+
+static void
+test_v2si (unsigned int x)
+{
+  __v2si v = { x, x, };
+
+  compare64(&v, 0x1122334411223344ULL);
+}
+
+static void
+test_v1si (unsigned int x)
+{
+  __v1si v = { x };
+
+  compare32(&v, 0x11223344);
+}
+
+unsigned char x8 = 0x44;
+unsigned short x16 = 0x3344;
+unsigned int x32 = 0x11223344;
+
+int main(void)
+{
+  test_v8qi (x8);
+  test_v4qi (x8);
+  test_v4hi (x16);
+  test_v2hi (x16);
+  test_v2si (x32);
+  test_v1si (x32);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis1.c
new file mode 100644
index 000000000..efa08fa24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis1.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O2" } */
+
+#include "vec-init-2.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c
new file mode 100644
index 000000000..3aa0f5159
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis2.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_vis2_hw } */
+/* { dg-options "-mcpu=ultrasparc3 -O2" } */
+
+#include "vec-init-2.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis3.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis3.c
new file mode 100644
index 000000000..5f0c65860
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2-vis3.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_vis3_hw } */
+/* { dg-options "-mcpu=niagara3 -O2" } */
+
+#include "vec-init-2.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2.inc b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2.inc
new file mode 100644
index 000000000..13685a100
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-2.inc
@@ -0,0 +1,94 @@
+typedef short __v2hi __attribute__ ((__vector_size__ (4)));
+typedef short __v4hi __attribute__ ((__vector_size__ (8)));
+
+extern void abort (void);
+
+static void
+compare64 (int n, void *p, unsigned long long val)
+{
+  unsigned long long *x = (unsigned long long *) p;
+
+  if (*x != val)
+    abort();
+}
+
+static void
+compare32 (int n, void *p, unsigned int val)
+{
+  unsigned int *x = (unsigned int *) p;
+  if (*x != val)
+    abort();
+}
+
+#define V2HI_TEST(N, elt0, elt1) \
+static void \
+test_v2hi_##N (unsigned short x, unsigned short y) \
+{ \
+  __v2hi v = { (elt0), (elt1) }; \
+  compare32(N, &v, ((int)(elt0) << 16) | (elt1)); \
+}
+
+V2HI_TEST(1, x, y)
+V2HI_TEST(2, y, x)
+V2HI_TEST(3, x, x)
+V2HI_TEST(4, x, 0)
+V2HI_TEST(5, 0, x)
+V2HI_TEST(6, y, 1)
+V2HI_TEST(7, 1, y)
+V2HI_TEST(8, 2, 3)
+V2HI_TEST(9, 0x400, x)
+V2HI_TEST(10, y, 0x8000)
+
+#define V4HI_TEST(N, elt0, elt1, elt2, elt3)	\
+static void \
+test_v4hi_##N (unsigned short a, unsigned short b, unsigned short c, unsigned short d) \
+{ \
+  __v4hi v = { (elt0), (elt1), (elt2), (elt3) }; \
+  compare64(N, &v, \
+            ((long long)(elt0) << 48) | \
+	    ((long long)(elt1) << 32) | \
+            ((long long)(elt2) << 16) | \
+            ((long long)(elt3))); \
+}
+
+V4HI_TEST(1, a, a, a, a)
+V4HI_TEST(2, a, b, c, d)
+V4HI_TEST(3, a, a, b, b)
+V4HI_TEST(4, d, c, b, a)
+V4HI_TEST(5, a, 0, 0, 0)
+V4HI_TEST(6, a, 0, b, 0)
+V4HI_TEST(7, c, 5, 5, 5)
+V4HI_TEST(8, d, 6, a, 6)
+V4HI_TEST(9, 0x200, 0x300, 0x500, 0x8800)
+V4HI_TEST(10, 0x600, a, a, a)
+
+unsigned short a16 = 0x3344;
+unsigned short b16 = 0x5566;
+unsigned short c16 = 0x7788;
+unsigned short d16 = 0x9911;
+
+int main(void)
+{
+  test_v2hi_1 (a16, b16);
+  test_v2hi_2 (a16, b16);
+  test_v2hi_3 (a16, b16);
+  test_v2hi_4 (a16, b16);
+  test_v2hi_5 (a16, b16);
+  test_v2hi_6 (a16, b16);
+  test_v2hi_7 (a16, b16);
+  test_v2hi_8 (a16, b16);
+  test_v2hi_9 (a16, b16);
+  test_v2hi_10 (a16, b16);
+
+  test_v4hi_1 (a16, b16, c16, d16);
+  test_v4hi_2 (a16, b16, c16, d16);
+  test_v4hi_3 (a16, b16, c16, d16);
+  test_v4hi_4 (a16, b16, c16, d16);
+  test_v4hi_5 (a16, b16, c16, d16);
+  test_v4hi_6 (a16, b16, c16, d16);
+  test_v4hi_7 (a16, b16, c16, d16);
+  test_v4hi_8 (a16, b16, c16, d16);
+  test_v4hi_9 (a16, b16, c16, d16);
+  test_v4hi_10 (a16, b16, c16, d16);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis1.c
new file mode 100644
index 000000000..6c826108c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis1.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_hw } */
+/* { dg-options "-mcpu=ultrasparc -mvis -O2" } */
+
+#include "vec-init-3.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis2.c
new file mode 100644
index 000000000..6424e2f15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis2.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_vis2_hw } */
+/* { dg-options "-mcpu=ultrasparc3 -O2" } */
+
+#include "vec-init-3.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis3.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis3.c
new file mode 100644
index 000000000..226c108c5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3-vis3.c
@@ -0,0 +1,5 @@
+/* { dg-do run } */
+/* { dg-require-effective-target ultrasparc_vis3_hw } */
+/* { dg-options "-mcpu=niagara3 -O2" } */
+
+#include "vec-init-3.inc"
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3.inc b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3.inc
new file mode 100644
index 000000000..8a3db2600
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vec-init-3.inc
@@ -0,0 +1,105 @@
+typedef unsigned char __v4qi __attribute__ ((__vector_size__ (4)));
+typedef unsigned char __v8qi __attribute__ ((__vector_size__ (8)));
+
+extern void abort (void);
+
+static void
+compare64 (int n, void *p, unsigned long long val)
+{
+  unsigned long long *x = (unsigned long long *) p;
+
+  if (*x != val)
+    abort();
+}
+
+static void
+compare32 (int n, void *p, unsigned int val)
+{
+  unsigned int *x = (unsigned int *) p;
+  if (*x != val)
+    abort();
+}
+
+#define V4QI_TEST(N, elt0, elt1, elt2, elt3)	\
+static void \
+test_v4qi_##N (unsigned char a, unsigned char b, unsigned char c, unsigned char d) \
+{ \
+  __v4qi v = { (elt0), (elt1), (elt2), (elt3) };	\
+  compare32(N, &v, ((int)(elt0) << 24) | \
+	           ((int)(elt1) << 16) | \
+	           ((int)(elt2) << 8) | ((int)(elt3)));	\
+}
+
+V4QI_TEST(1, a, a, a, a)
+V4QI_TEST(2, b, b, b, b)
+V4QI_TEST(3, a, b, c, d)
+V4QI_TEST(4, d, c, b, a)
+V4QI_TEST(5, a, 0, 0, 0)
+V4QI_TEST(6, b, 1, 1, b)
+V4QI_TEST(7, c, 5, d, 5)
+V4QI_TEST(8, 0x20, 0x30, b, a)
+V4QI_TEST(9, 0x40, 0x50, 0x60, 0x70)
+V4QI_TEST(10, 0x40, 0x50, 0x60, c)
+
+#define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
+static void \
+test_v8qi_##N (unsigned char a, unsigned char b, unsigned char c, unsigned char d, \
+               unsigned char e, unsigned char f, unsigned char g, unsigned char h) \
+{ \
+  __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
+	       (elt4), (elt5), (elt6), (elt7) }; \
+  compare64(N, &v, ((long long)(elt0) << 56) | \
+	           ((long long)(elt1) << 48) | \
+	           ((long long)(elt2) << 40) | \
+	           ((long long)(elt3) << 32) | \
+	           ((long long)(elt4) << 24) | \
+	           ((long long)(elt5) << 16) | \
+	           ((long long)(elt6) << 8) | \
+	           ((long long)(elt7) << 0)); \
+}
+
+V8QI_TEST(1, a, a, a, a, a, a, a, a)
+V8QI_TEST(2, a, b, c, d, e, f, g, h)
+V8QI_TEST(3, h, g, f, e, d, c, b, a)
+V8QI_TEST(4, a, b, a, b, a, b, a, b)
+V8QI_TEST(5, c, b, c, b, c, b, c, a)
+V8QI_TEST(6, a, 0, 0, 0, 0, 0, 0, 0)
+V8QI_TEST(7, b, 1, b, 1, b, 1, b, 1)
+V8QI_TEST(8, c, d, 0x20, a, 0x21, b, 0x23, c)
+V8QI_TEST(9, 1, 2, 3, 4, 5, 6, 7, 8)
+V8QI_TEST(10, a, a, b, b, c, c, d, d)
+
+unsigned char a8 = 0x33;
+unsigned char b8 = 0x55;
+unsigned char c8 = 0x77;
+unsigned char d8 = 0x99;
+unsigned char e8 = 0x11;
+unsigned char f8 = 0x22;
+unsigned char g8 = 0x44;
+unsigned char h8 = 0x66;
+
+int main(void)
+{
+  test_v4qi_1 (a8, b8, c8, d8);
+  test_v4qi_2 (a8, b8, c8, d8);
+  test_v4qi_3 (a8, b8, c8, d8);
+  test_v4qi_4 (a8, b8, c8, d8);
+  test_v4qi_5 (a8, b8, c8, d8);
+  test_v4qi_6 (a8, b8, c8, d8);
+  test_v4qi_7 (a8, b8, c8, d8);
+  test_v4qi_8 (a8, b8, c8, d8);
+  test_v4qi_9 (a8, b8, c8, d8);
+  test_v4qi_10 (a8, b8, c8, d8);
+
+  test_v8qi_1 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_2 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_3 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_4 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_5 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_6 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_7 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_8 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_9 (a8, b8, c8, d8, e8, f8, g8, h8);
+  test_v8qi_10 (a8, b8, c8, d8, e8, f8, g8, h8);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3misc.c
new file mode 100644
index 000000000..7286d705d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3misc.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
+typedef int __v2si __attribute__((vector_size(8)));
+typedef short __v4hi __attribute__((vector_size(8)));
+typedef unsigned char __v8qi __attribute__((vector_size(8)));
+typedef long long int64_t;
+
+__v4hi test_fchksm16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fchksm16 (x, y);
+}
+
+long test_pdistn (__v8qi x, __v8qi y)
+{
+  return __builtin_vis_pdistn (x, y);
+}
+
+__v4hi test_fmean16 (__v4hi x, __v4hi y)
+{
+  return __builtin_vis_fmean16 (x, y);
+}
+
+int64_t test_fpadd64 (int64_t x, int64_t y)
+{
+  return __builtin_vis_fpadd64 (x, y);
+}
+
+int64_t test_fpsub64 (int64_t x, int64_t y)
+{
+  return __builtin_vis_fpsub64 (x, y);
+}
+
+/* { dg-final { scan-assembler "fchksm16\t%" } } */
+/* { dg-final { scan-assembler "pdistn\t%" } } */
+/* { dg-final { scan-assembler "fmean16\t%" } } */
+/* { dg-final { scan-assembler "fpadd64\t%" } } */
+/* { dg-final { scan-assembler "fpsub64\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-1.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-1.c
new file mode 100644
index 000000000..1265d8866
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -mvis3" } */
+
+double d;
+float f;
+
+int test_convert_from_float(void)
+{
+  return f;
+}
+
+int test_convert_from_double(void)
+{
+  return d;
+}
+
+float test_convert_to_float(int x)
+{
+  return x;
+}
+
+double test_convert_to_double(int x)
+{
+  return x;
+}
+
+/* { dg-final { scan-assembler-times "movstouw\t%" 2 } } */
+/* { dg-final { scan-assembler-times "movwtos\t%" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-2.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-2.c
new file mode 100644
index 000000000..de7930765
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-2.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O1 -mvis3" } */
+
+double d;
+float f;
+
+long test_convert_from_float(void)
+{
+  return f;
+}
+
+long test_convert_from_double(void)
+{
+  return d;
+}
+
+float test_convert_to_float(long x)
+{
+  return x;
+}
+
+double test_convert_to_double(long x)
+{
+  return x;
+}
+
+/* { dg-final { scan-assembler-times "movdtox\t%" 2 } } */
+/* { dg-final { scan-assembler-times "movxtod\t%" 2 } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-3.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-3.c
new file mode 100644
index 000000000..3b2116eec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/vis3move-3.c
@@ -0,0 +1,41 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ilp32 } */
+/* { dg-options "-O1 -mvis3" } */
+
+float fnegs (float a)
+{
+  return -a;
+}
+
+double fnegd (double a)
+{
+  return -a;
+}
+
+float fmuls (float a, float b)
+{
+  return a * b;
+}
+
+double fmuld (double a, double b)
+{
+  return a * b;
+}
+
+double fsmuld (float a, float b)
+{
+  return (double)a * (double)b;
+}
+
+double fnsmuld (float a, float b)
+{
+  return -((double)a * (double)b);
+}
+
+/* { dg-final { scan-assembler-times "movwtos\t%" 13 } } */
+/* { dg-final { scan-assembler "fnegs\t%" } } */
+/* { dg-final { scan-assembler "fnegd\t%" } } */
+/* { dg-final { scan-assembler "fmuls\t%" } } */
+/* { dg-final { scan-assembler "fmuld\t%" } } */
+/* { dg-final { scan-assembler "fsmuld\t%" } } */
+/* { dg-final { scan-assembler "fnsmuld\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/wrgsr.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/wrgsr.c
new file mode 100644
index 000000000..6cfa0603a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/wrgsr.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O -mcpu=ultrasparc -mvis" } */
+
+void set_gsr (void)
+{
+	__builtin_vis_write_gsr (2 << 3);
+}
+
+void set_gsr2 (long x)
+{
+	__builtin_vis_write_gsr (x);
+}
+
+/* { dg-final { scan-assembler "wr\t%g0, 16, %gsr" } } */
+/* { dg-final { scan-assembler "wr\t%g0, %" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/sparc/xmul.c b/gcc-4.9/gcc/testsuite/gcc.target/sparc/xmul.c
new file mode 100644
index 000000000..a432ee1fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/sparc/xmul.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-mvis3" } */
+typedef long long int64_t;
+
+int64_t test_umulxhi (int64_t x, int64_t y)
+{
+  return __builtin_vis_umulxhi (x, y);
+}
+
+int64_t test_xmulx (int64_t x, int64_t y)
+{
+  return __builtin_vis_xmulx (x, y);
+}
+
+int64_t test_xmulxhi (int64_t x, int64_t y)
+{
+  return __builtin_vis_xmulxhi (x, y);
+}
+
+/* { dg-final { scan-assembler "umulxhi\t%" } } */
+/* { dg-final { scan-assembler "xmulx\t%" } } */
+/* { dg-final { scan-assembler "xmulxhi\t%" } } */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/Wmain.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/Wmain.c
new file mode 100644
index 000000000..58eca021b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/Wmain.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-Wmain -mstdmain" } */
+
+int main (void *wrong)/* { dg-warning "first argument of 'main' should be 'int'" "" } */
+{ 
+  /* { dg-warning "'main' takes only zero or two arguments" "" { target *-*-* } 4 } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/abi.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/abi.c
new file mode 100644
index 000000000..b435f1ede
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/abi.c
@@ -0,0 +1,474 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+/* Test that arguments are passed in the correct location according to the ABI.  */
+
+#include <stdlib.h>
+
+/* Hack to allow calling func_asm which takes 84 arguments that are scalars.
+   The function func_call takes 84 union quadword arguments, so we can check to
+   see if each scalar is passed in the correct location.  This asm glues the
+   two functions together, so that the compiler is not aware of the
+   aliasing.  */
+__asm__ ("func_asm = func_call");
+
+typedef unsigned int uqword __attribute__((mode(TI)));
+typedef int qword __attribute__((mode(TI)));
+
+union u
+{
+  uqword		uq;
+  qword			sq;
+  double		d[2];
+  float			f[4];
+  unsigned long long	ull[2];
+  long long		sll[2];
+  unsigned long		ul[4];
+  long			sl[4];
+  unsigned int		ui[4];
+  int			si[4];
+  unsigned short	us[8];
+  short			ss[8];
+  unsigned char		uc[16];
+  signed char		sc[16];
+};
+
+
+extern void func_asm(signed char a1,
+		     unsigned char a2,
+		     short a3,
+		     unsigned short a4,
+		     int a5,
+		     unsigned int a6,
+		     long a7,
+		     unsigned long a8,
+		     long long a9,
+		     unsigned long long a10,
+		     float a11,
+		     double a12,
+		     int a13,
+		     int a14,
+		     int a15,
+		     int a16,
+		     int a17,
+		     int a18,
+		     int a19,
+		     int a20,
+		     int a21,
+		     int a22,
+		     int a23,
+		     int a24,
+		     int a25,
+		     int a26,
+		     int a27,
+		     int a28,
+		     int a29,
+		     int a30,
+		     int a31,
+		     int a32,
+		     int a33,
+		     int a34,
+		     int a35,
+		     int a36,
+		     int a37,
+		     int a38,
+		     int a39,
+		     int a40,
+		     int a41,
+		     int a42,
+		     int a43,
+		     int a44,
+		     int a45,
+		     int a46,
+		     int a47,
+		     int a48,
+		     int a49,
+		     int a50,
+		     int a51,
+		     int a52,
+		     int a53,
+		     int a54,
+		     int a55,
+		     int a56,
+		     int a57,
+		     int a58,
+		     int a59,
+		     int a60,
+		     int a61,
+		     int a62,
+		     int a63,
+		     int a64,
+		     int a65,
+		     int a66,
+		     int a67,
+		     int a68,
+		     int a69,
+		     int a70,
+		     int a71,
+		     int a72,
+		     signed char a73,
+		     unsigned char a74,
+		     short a75,
+		     unsigned short a76,
+		     int a77,
+		     unsigned int a78,
+		     long a79,
+		     unsigned long a80,
+		     long long a81,
+		     unsigned long long a82,
+		     float a83,
+		     double a84);
+
+void func_call(union u a1,
+	       union u a2,
+	       union u a3,
+	       union u a4,
+	       union u a5,
+	       union u a6,
+	       union u a7,
+	       union u a8,
+	       union u a9,
+	       union u a10,
+	       union u a11,
+	       union u a12,
+	       union u a13,
+	       union u a14,
+	       union u a15,
+	       union u a16,
+	       union u a17,
+	       union u a18,
+	       union u a19,
+	       union u a20,
+	       union u a21,
+	       union u a22,
+	       union u a23,
+	       union u a24,
+	       union u a25,
+	       union u a26,
+	       union u a27,
+	       union u a28,
+	       union u a29,
+	       union u a30,
+	       union u a31,
+	       union u a32,
+	       union u a33,
+	       union u a34,
+	       union u a35,
+	       union u a36,
+	       union u a37,
+	       union u a38,
+	       union u a39,
+	       union u a40,
+	       union u a41,
+	       union u a42,
+	       union u a43,
+	       union u a44,
+	       union u a45,
+	       union u a46,
+	       union u a47,
+	       union u a48,
+	       union u a49,
+	       union u a50,
+	       union u a51,
+	       union u a52,
+	       union u a53,
+	       union u a54,
+	       union u a55,
+	       union u a56,
+	       union u a57,
+	       union u a58,
+	       union u a59,
+	       union u a60,
+	       union u a61,
+	       union u a62,
+	       union u a63,
+	       union u a64,
+	       union u a65,
+	       union u a66,
+	       union u a67,
+	       union u a68,
+	       union u a69,
+	       union u a70,
+	       union u a71,
+	       union u a72,
+	       union u a73,
+	       union u a74,
+	       union u a75,
+	       union u a76,
+	       union u a77,
+	       union u a78,
+	       union u a79,
+	       union u a80,
+	       union u a81,
+	       union u a82,
+	       union u a83,
+	       union u a84)
+{
+  /* arguments passed in registers */
+  if (a1.sc[3] != -1)			/* signed char */
+    abort ();
+
+  if (a2.uc[3] != +2)			/* unsigned char */
+    abort ();
+
+  if (a3.ss[1] != -3)			/* short */
+    abort ();
+
+  if (a4.us[1] != +4)			/* unsigned short */
+    abort ();
+
+  if (a5.si[0] != -5)			/* int */
+    abort ();
+
+  if (a6.ui[0] != +6)			/* unsigned int */
+    abort ();
+
+  if (a7.sl[0] != -7)			/* long */
+    abort ();
+
+  if (a8.ul[0] != +8)			/* unsigned long */
+    abort ();
+
+  if (a9.sll[0] != -9)			/* long long */
+    abort ();
+
+  if (a10.ull[0] != +10)		/* unsigned long long */
+    abort ();
+
+  if (a11.f[0] != -11.0f)		/* float */
+    abort ();
+
+  if (a12.d[0] != +12.0)		/* double */
+    abort ();
+
+  if (a13.si[0] != -13)			/* int */
+    abort ();
+
+  if (a14.si[0] != +14)			/* int */
+    abort ();
+
+  if (a15.si[0] != -15)			/* int */
+    abort ();
+
+  if (a16.si[0] != +16)			/* int */
+    abort ();
+
+  if (a17.si[0] != -17)			/* int */
+    abort ();
+
+  if (a18.si[0] != +18)			/* int */
+    abort ();
+
+  if (a19.si[0] != -19)			/* int */
+    abort ();
+
+  if (a20.si[0] != +20)			/* int */
+    abort ();
+
+  if (a21.si[0] != -21)			/* int */
+    abort ();
+
+  if (a22.si[0] != +22)			/* int */
+    abort ();
+
+  if (a23.si[0] != -23)			/* int */
+    abort ();
+
+  if (a24.si[0] != +24)			/* int */
+    abort ();
+
+  if (a25.si[0] != -25)			/* int */
+    abort ();
+
+  if (a26.si[0] != +26)			/* int */
+    abort ();
+
+  if (a27.si[0] != -27)			/* int */
+    abort ();
+
+  if (a28.si[0] != +28)			/* int */
+    abort ();
+
+  if (a29.si[0] != -29)			/* int */
+    abort ();
+
+  if (a30.si[0] != +30)			/* int */
+    abort ();
+
+  if (a31.si[0] != -31)			/* int */
+    abort ();
+
+  if (a32.si[0] != +32)			/* int */
+    abort ();
+
+  if (a33.si[0] != -33)			/* int */
+    abort ();
+
+  if (a34.si[0] != +34)			/* int */
+    abort ();
+
+  if (a35.si[0] != -35)			/* int */
+    abort ();
+
+  if (a36.si[0] != +36)			/* int */
+    abort ();
+
+  if (a37.si[0] != -37)			/* int */
+    abort ();
+
+  if (a38.si[0] != +38)			/* int */
+    abort ();
+
+  if (a39.si[0] != -39)			/* int */
+    abort ();
+
+  if (a40.si[0] != +40)			/* int */
+    abort ();
+
+  if (a41.si[0] != -41)			/* int */
+    abort ();
+
+  if (a42.si[0] != +42)			/* int */
+    abort ();
+
+  if (a43.si[0] != -43)			/* int */
+    abort ();
+
+  if (a44.si[0] != +44)			/* int */
+    abort ();
+
+  if (a45.si[0] != -45)			/* int */
+    abort ();
+
+  if (a46.si[0] != +46)			/* int */
+    abort ();
+
+  if (a47.si[0] != -47)			/* int */
+    abort ();
+
+  if (a48.si[0] != +48)			/* int */
+    abort ();
+
+  if (a49.si[0] != -49)			/* int */
+    abort ();
+
+  if (a50.si[0] != +50)			/* int */
+    abort ();
+
+  if (a51.si[0] != -51)			/* int */
+    abort ();
+
+  if (a52.si[0] != +52)			/* int */
+    abort ();
+
+  if (a53.si[0] != -53)			/* int */
+    abort ();
+
+  if (a54.si[0] != +54)			/* int */
+    abort ();
+
+  if (a55.si[0] != -55)			/* int */
+    abort ();
+
+  if (a56.si[0] != +56)			/* int */
+    abort ();
+
+  if (a57.si[0] != -57)			/* int */
+    abort ();
+
+  if (a58.si[0] != +58)			/* int */
+    abort ();
+
+  if (a59.si[0] != -59)			/* int */
+    abort ();
+
+  if (a60.si[0] != +60)			/* int */
+    abort ();
+
+  if (a61.si[0] != -61)			/* int */
+    abort ();
+
+  if (a62.si[0] != +62)			/* int */
+    abort ();
+
+  if (a63.si[0] != -63)			/* int */
+    abort ();
+
+  if (a64.si[0] != +64)			/* int */
+    abort ();
+
+  if (a65.si[0] != -65)			/* int */
+    abort ();
+
+  if (a66.si[0] != +66)			/* int */
+    abort ();
+
+  if (a67.si[0] != -67)			/* int */
+    abort ();
+
+  if (a68.si[0] != +68)			/* int */
+    abort ();
+
+  if (a69.si[0] != -69)			/* int */
+    abort ();
+
+  if (a70.si[0] != +70)			/* int */
+    abort ();
+
+  if (a71.si[0] != -71)			/* int */
+    abort ();
+
+  if (a72.si[0] != +72)			/* int */
+    abort ();
+
+  /* arguments passed on the stack */
+  if (a73.sc[3] != -73)			/* signed char */
+    abort ();
+
+  if (a74.uc[3] != 74)			/* unsigned char */
+    abort ();
+
+  if (a75.ss[1] != -75)			/* short */
+    abort ();
+
+  if (a76.us[1] != +76)			/* unsigned short */
+    abort ();
+
+  if (a77.si[0] != -77)			/* int */
+    abort ();
+
+  if (a78.ui[0] != +78)			/* unsigned int */
+    abort ();
+
+  if (a79.sl[0] != -79)			/* long */
+    abort ();
+
+  if (a80.ul[0] != +80)			/* unsigned long */
+    abort ();
+
+  if (a81.sll[0] != -81)		/* long long */
+    abort ();
+
+  if (a82.ull[0] != +82)		/* unsigned long long */
+    abort ();
+
+  if (a83.f[0] != -83.0f)		/* float */
+    abort ();
+
+  if (a84.d[0] != +84.0)		/* double */
+    abort ();
+}
+
+int main(void)
+{
+  func_asm(-1,   +2,  -3,  +4,  -5,  +6,  -7,  +8,  -9, +10,
+	   -11, +12, -13, +14, -15, +16, -17, +18, -19, +20,
+	   -21, +22, -23, +24, -25, +26, -27, +28, -29, +30,
+	   -31, +32, -33, +34, -35, +36, -37, +38, -39, +40,
+	   -41, +42, -43, +44, -45, +46, -47, +48, -49, +50,
+	   -51, +52, -53, +54, -55, +56, -57, +58, -59, +60,
+	   -61, +62, -63, +64, -65, +66, -67, +68, -69, +70,
+	   -71, +72, -73, +74, -75, +76, -77, +78, -79, +80,
+	   -81, +82, -83, +84);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/compare-dp.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/compare-dp.c
new file mode 100644
index 000000000..cbc7663b9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/compare-dp.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-not "__eqdf2" } } */
+
+/* Ensure double precision comparisons are always inlined.  */
+
+int test (double a, double b) __attribute__((noinline));
+int test (double a, double b)
+{
+  return a == b;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-1.c
new file mode 100644
index 000000000..6fe292562
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "lqr\t.3,.LC" 4 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,1\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,3\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,5\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,6\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,7\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,8\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,9\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,10\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,11\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,12\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,13\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,14\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd\t.3,15\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,6\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,8\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,10\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,12\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd\t.3,14\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd\t.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd\t.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd\t.3,8\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd\t.3,12\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cdd\t.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cdd\t.3,8\\(.sp\\)" 1 } } */
+
+__vector unsigned char
+not_cpat0()
+{
+  /* Contains no runs */
+  return (__vector unsigned char) {
+	    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+	    0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F};
+}
+
+__vector unsigned char
+not_cpat1()
+{
+  /* Includes 1 run but not in the right place. */
+  return (__vector unsigned char) {
+	    0x10, 0x02, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17,
+	    0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F};
+}
+
+__vector unsigned char
+not_cpat2()
+{
+  /* Includes 2 runs. */
+  return (__vector unsigned char) {
+	    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+	    0x00, 0x01, 0x02, 0x03, 0x00, 0x01, 0x02, 0x03};
+}
+
+__vector unsigned char
+not_cpat3()
+{
+  /* Includes 1 incorrect run. */
+  return (__vector unsigned char) {
+	    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+	    0x00, 0x01, 0x02, 0x03, 0x05, 0x06, 0x07, 0x1F};
+}
+
+__vector unsigned char cbd_0() { return (__vector unsigned char) { 0x03, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_1() { return (__vector unsigned char) { 0x10, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_2() { return (__vector unsigned char) { 0x10, 0x11, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_3() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_4() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x03, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_5() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_6() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x03, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_7() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_8() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x03, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_9() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_a() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x03, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_b() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x03, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_c() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x03, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cbd_d() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x03, 0x1E, 0x1F}; }
+__vector unsigned char cbd_e() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x03, 0x1F}; }
+__vector unsigned char cbd_f() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x03}; }
+
+__vector unsigned char chd_0() { return (__vector unsigned char) { 0x02, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_2() { return (__vector unsigned char) { 0x10, 0x11, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_4() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x02, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_6() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_8() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x02, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_a() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char chd_c() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x02, 0x03, 0x1E, 0x1F}; }
+__vector unsigned char chd_e() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x02, 0x03}; }
+
+__vector unsigned char cwd_0() { return (__vector unsigned char) { 0x00, 0x01, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cwd_4() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x00, 0x01, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cwd_8() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cwd_c() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03}; }
+
+__vector unsigned char cdd_0() { return (__vector unsigned char) { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}; }
+__vector unsigned char cdd_8() { return (__vector unsigned char) { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07}; }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-2.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-2.c
new file mode 100644
index 000000000..d5f86ed30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-2.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "cbd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,1\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,3\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,15\\(.sp\\)" 22 } } */
+/* { dg-final { scan-assembler-times "chd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd	.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "ila	.3,66051" 2 } } */
+
+#define MAKE_UINT(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,aA,aB,aC,aD,aE,aF) ((unsigned int)(a0 << 24 | a1 << 16 | a2 << 8 | a3))
+
+unsigned int cbd_0() { return MAKE_UINT( 0x03, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_1() { return MAKE_UINT( 0x10, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_2() { return MAKE_UINT( 0x10, 0x11, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_3() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_4() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x03, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_5() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_6() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x03, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_7() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_8() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x03, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_9() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_a() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x03, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_b() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_c() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x03, 0x1D, 0x1E, 0x1F); }
+unsigned int cbd_d() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x03, 0x1E, 0x1F); }
+unsigned int cbd_e() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x03, 0x1F); }
+unsigned int cbd_f() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x03); }
+unsigned int chd_0() { return MAKE_UINT( 0x02, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_2() { return MAKE_UINT( 0x10, 0x11, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_4() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x02, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_6() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_8() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x02, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_a() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int chd_c() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x02, 0x03, 0x1E, 0x1F); }
+unsigned int chd_e() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x02, 0x03); }
+unsigned int cwd_0() { return MAKE_UINT( 0x00, 0x01, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cwd_4() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x00, 0x01, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cwd_8() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cwd_c() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03); }
+unsigned int cdd_0() { return MAKE_UINT( 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned int cdd_8() { return MAKE_UINT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-3.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-3.c
new file mode 100644
index 000000000..ced50111f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-3.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "cbd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,1\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,3\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,5\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,6\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,7\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cbd	.3,15\\(.sp\\)" 15 } } */
+/* { dg-final { scan-assembler-times "chd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd	.3,2\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd	.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "chd	.3,6\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd	.3,0\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cwd	.3,4\\(.sp\\)" 1 } } */
+/* { dg-final { scan-assembler-times "cdd	.3,0\\(.sp\\)" 1 } } */
+
+#define MAKE_ULLONG(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,aA,aB,aC,aD,aE,aF) \
+  ((unsigned long long) \
+    (a0##ull << 56 \
+     | a1##ull << 48 \
+     | a2##ull << 40 \
+     | a3##ull << 32\
+     | a4##ull << 24\
+     | a5##ull << 16 \
+     | a6##ull << 8 \
+     | a7##ull ))
+
+unsigned long long cbd_0() { return MAKE_ULLONG( 0x03, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_1() { return MAKE_ULLONG( 0x10, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_2() { return MAKE_ULLONG( 0x10, 0x11, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_3() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_4() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x03, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_5() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_6() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x03, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_7() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_8() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x03, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_9() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_a() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x03, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_b() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_c() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x03, 0x1D, 0x1E, 0x1F); }
+unsigned long long cbd_d() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x03, 0x1E, 0x1F); }
+unsigned long long cbd_e() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x03, 0x1F); }
+unsigned long long cbd_f() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x03); }
+unsigned long long chd_0() { return MAKE_ULLONG( 0x02, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_2() { return MAKE_ULLONG( 0x10, 0x11, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_4() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x02, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_6() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_8() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x02, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_a() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long chd_c() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x02, 0x03, 0x1E, 0x1F); }
+unsigned long long chd_e() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x02, 0x03); }
+unsigned long long cwd_0() { return MAKE_ULLONG( 0x00, 0x01, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cwd_4() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x00, 0x01, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cwd_8() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cwd_c() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03); }
+unsigned long long cdd_0() { return MAKE_ULLONG( 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned long long cdd_8() { return MAKE_ULLONG( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-4.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-4.c
new file mode 100644
index 000000000..89110a66d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/cpat-4.c
@@ -0,0 +1,40 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+/* { dg-final { scan-assembler-times "il\t.3,4611" 1 } } */
+/* { dg-final { scan-assembler-times "il\t.3,4627" 25 } } */
+/* { dg-final { scan-assembler-times "il\t.3,515" 3 } } */
+/* { dg-final { scan-assembler-times "il\t.3,787" 1 } } */
+
+#define MAKE_USHORT(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,aA,aB,aC,aD,aE,aF) ((unsigned short)(a2 << 8 | a3))
+
+unsigned short cbd_0() { return MAKE_USHORT( 0x03, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_1() { return MAKE_USHORT( 0x10, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_2() { return MAKE_USHORT( 0x10, 0x11, 0x03, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_3() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_4() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x03, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_5() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_6() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x03, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_7() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_8() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x03, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_9() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_a() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x03, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_b() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_c() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x03, 0x1D, 0x1E, 0x1F); }
+unsigned short cbd_d() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x03, 0x1E, 0x1F); }
+unsigned short cbd_e() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x03, 0x1F); }
+unsigned short cbd_f() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x03); }
+unsigned short chd_0() { return MAKE_USHORT( 0x02, 0x03, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_2() { return MAKE_USHORT( 0x10, 0x11, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_4() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x02, 0x03, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_6() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_8() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x02, 0x03, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_a() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short chd_c() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x02, 0x03, 0x1E, 0x1F); }
+unsigned short chd_e() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x02, 0x03); }
+unsigned short cwd_0() { return MAKE_USHORT( 0x00, 0x01, 0x02, 0x03, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cwd_4() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x00, 0x01, 0x02, 0x03, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cwd_8() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cwd_c() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x00, 0x01, 0x02, 0x03); }
+unsigned short cdd_0() { return MAKE_USHORT( 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F); }
+unsigned short cdd_8() { return MAKE_USHORT( 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); }
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcgt-nan.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcgt-nan.c
new file mode 100644
index 000000000..18ce01356
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcgt-nan.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=celledp -O1" } */
+/* { dg-final { scan-assembler "dfceq" } } */
+
+/* GCC previously transformed an "a <= b" test into "! (a > b)" when
+   compiling with -march=celledp, so that the dfcgt instruction can be
+   used to implement the comparison.
+
+   However, this transformation violates the IEEE-754 standard in the
+   presence of NaN values.  If either a or b is a NaN, a <= b should
+   evaluate to false according to IEEE rules.  However, after the
+   transformation, a > b as implemented by dfcgt itself returns false,
+   so the transformed test returns true.
+
+   Note that the equivalent transformation is valid for single-
+   precision floating-point values on the Cell SPU, because the format
+   does not have NaNs.  It is invalid for double-precision, even on
+   Cell, however.  */
+
+int test (double a, double b) __attribute__ ((noinline));
+int test (double a, double b)
+{
+  return a <= b;
+}
+
+int main (void)
+{
+  double x = 0.0;
+  double y = 0.0/0.0;
+  return test (x, y);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcmeq.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcmeq.c
new file mode 100644
index 000000000..9286361b3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcmeq.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=celledp -O1" } */
+/* { dg-final { scan-assembler "dfcmeq" } } */
+
+int foo(double x, double y)
+{
+  if (__builtin_fabs(x) == __builtin_fabs(y))
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcmgt.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcmgt.c
new file mode 100644
index 000000000..ef7ef5899
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/dfcmgt.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=celledp -O1" } */
+/* { dg-final { scan-assembler "dfcmgt" } } */
+
+int foo(double x, double y)
+{
+  if (__builtin_fabs(x) > __builtin_fabs(y))
+    return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cache1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cache1.c
new file mode 100644
index 000000000..3487ce980
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cache1.c
@@ -0,0 +1,195 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target "ealib" } */
+
+#include <stdlib.h>
+#include <string.h>
+#include <ea.h>
+#include <spu_cache.h>
+
+#ifdef __EA64__
+#define addr unsigned long long
+#else
+#define addr unsigned long
+#endif
+
+static __ea void *bigblock;
+static __ea void *block;
+static int *ls_block;
+
+extern char __cache_tag_array_size[];
+#define CACHE_SIZE (4 * (int) &__cache_tag_array_size[0])
+#define LINE_SIZE ((addr)128)
+
+void
+init_mem (void)
+{
+  bigblock = malloc_ea (CACHE_SIZE + 2 * LINE_SIZE);
+  block = malloc_ea (2 * LINE_SIZE);
+  ls_block = malloc (LINE_SIZE);
+
+  memset_ea (bigblock, 0, CACHE_SIZE + 2 * LINE_SIZE);
+  memset_ea (block, -1, 2 * LINE_SIZE);
+  memset (ls_block, -1, LINE_SIZE);
+  cache_flush ();
+}
+
+/* Test 1: Simple cache fetching.  */
+void
+test1 (void)
+{
+  addr aligned = ((((addr) block) + LINE_SIZE - 1) & -LINE_SIZE);
+  int *p1 = NULL;
+  int *p2 = NULL;
+  int i = 0;
+
+  /* First, check if the same addr give the same cache ptr.  */
+  p1 = cache_fetch ((__ea void *) aligned);
+  p2 = cache_fetch ((__ea void *) aligned);
+
+  if (p1 != p2)
+    abort ();
+
+  /* Check that the data actually is in the cache. */
+  for (i = 0; i < LINE_SIZE / sizeof (int); i++)
+    {
+      if (p1[i] != -1)
+	abort ();
+    }
+
+  /* Check returning within the cache line. */
+  p2 = cache_fetch ((__ea void *) (aligned + sizeof (int)));
+
+  if (p2 - p1 != 1)
+    abort ();
+
+  /* Finally, check that fetching an LS pointer returns that pointer.  */
+  p1 = cache_fetch ((__ea char *) ls_block);
+  if (p1 != ls_block)
+    abort ();
+}
+
+/* Test 2: Eviction testing. */
+void
+test2 (void)
+{
+  addr aligned = ((((addr) block) + LINE_SIZE - 1) & -LINE_SIZE);
+  int *p = NULL;
+  int i = 0;
+
+  /* First check that clean evictions don't write back.  */
+  p = cache_fetch ((__ea void *) aligned);
+  for (i = 0; i < LINE_SIZE / sizeof (int); i++)
+    p[i] = 0;
+
+  cache_evict ((__ea void *) aligned);
+  memcpy_ea ((__ea char *) ls_block, (__ea void *) aligned, LINE_SIZE);
+
+  for (i = 0; i < LINE_SIZE / sizeof (int); i++)
+    {
+      if (ls_block[i] == 0)
+	abort ();
+    }
+
+  /* Now check that dirty evictions do write back.  */
+  p = cache_fetch_dirty ((__ea void *) aligned, LINE_SIZE);
+  for (i = 0; i < LINE_SIZE / sizeof (int); i++)
+    p[i] = 0;
+
+  cache_evict ((__ea void *) aligned);
+  memcpy_ea ((__ea char *) ls_block, (__ea void *) aligned, LINE_SIZE);
+
+  for (i = 0; i < LINE_SIZE / sizeof (int); i++)
+    {
+      if (ls_block[i] != 0)
+	abort ();
+    }
+
+  /* Finally, check that non-atomic writeback only writes dirty bytes.  */
+
+  for (i = 0; i < LINE_SIZE / sizeof (int); i++)
+    {
+      p = cache_fetch_dirty ((__ea void *) (aligned + i * sizeof (int)),
+			     (i % 2) * sizeof (int));
+      p[0] = -1;
+    }
+
+  cache_evict ((__ea void *) aligned);
+  memcpy_ea ((__ea char *) ls_block, (__ea void *) aligned, LINE_SIZE);
+
+  for (i = 0; i < LINE_SIZE / sizeof (int); i++)
+    {
+      if ((ls_block[i] == -1) && (i % 2 == 0))
+	abort ();
+      if ((ls_block[i] == 0) && (i % 2 == 1))
+	abort ();
+    }
+}
+
+/* Test LS forced-eviction. */
+void
+test3 (void)
+{
+  addr aligned = ((((addr) bigblock) + LINE_SIZE - 1) & -LINE_SIZE);
+  char *test = NULL;
+  char *ls = NULL;
+  int i = 0;
+
+  /* Init memory, fill the cache to capacity.  */
+  ls = cache_fetch_dirty ((__ea void *) aligned, LINE_SIZE);
+  for (i = 1; i < (CACHE_SIZE / LINE_SIZE); i++)
+    cache_fetch_dirty ((__ea void *) (aligned + i * LINE_SIZE), LINE_SIZE);
+
+  memset (ls, -1, LINE_SIZE);
+  test = cache_fetch ((__ea void *) (aligned + CACHE_SIZE));
+
+  /* test == ls indicates cache collision.  */
+  if (test != ls)
+    abort ();
+
+  /* Make sure it actually wrote the cache line.  */
+  for (i = 0; i < LINE_SIZE; i++)
+    {
+      if (ls[i] != 0)
+	abort ();
+    }
+
+  ls = cache_fetch ((__ea void *) aligned);
+
+  /* test != ls indicates another entry was evicted.  */
+  if (test == ls)
+    abort ();
+
+  /* Make sure that the previous eviction actually wrote back.  */
+  for (i = 0; i < LINE_SIZE; i++)
+    {
+      if (ls[i] != 0xFF)
+	abort ();
+    }
+}
+
+int
+main (int argc, char **argv)
+{
+  init_mem ();
+  test1 ();
+  test2 ();
+  test3 ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cast1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cast1.c
new file mode 100644
index 000000000..9ec4e1546
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cast1.c
@@ -0,0 +1,43 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+
+extern void abort (void);
+extern unsigned long long __ea_local_store;
+
+__ea int *ppu;
+int x, *spu = &x, *spu2;
+
+int
+main (int argc, char **argv)
+{
+  ppu = (__ea int *) spu;
+  spu2 = (int *) ppu;
+
+#ifdef __EA32__
+  if ((int) ppu != (int) __ea_local_store + (int) spu)
+#else
+  if ((unsigned long long) ppu != __ea_local_store + (unsigned long long)(int) spu)
+#endif
+
+    abort ();
+
+  if (spu != spu2)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cast2.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cast2.c
new file mode 100644
index 000000000..6ce57dc4d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cast2.c
@@ -0,0 +1,74 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+
+extern void abort (void);
+
+int array[128];
+
+__ea int *ea;
+int *lm;
+
+void verify_ea (void) __attribute__ ((noinline));
+void
+verify_ea (void)
+{
+  if (ea != (__ea int *)lm)
+    abort ();
+}
+
+void verify_lm (void) __attribute__ ((noinline));
+void
+verify_lm (void)
+{
+  if ((int *)ea != lm)
+    abort ();
+}
+
+void verify_diff (int x) __attribute__ ((noinline));
+void
+verify_diff (int x)
+{
+  if (ea - lm != x)
+    abort ();
+}
+
+int
+main (int argc, char **argv)
+{
+  ea = 0;
+  lm = 0;
+  verify_ea ();
+  verify_lm ();
+  verify_diff (0);
+
+  ea = &array[64];
+  lm = &array[64];
+  verify_ea ();
+  verify_lm ();
+  verify_diff (0);
+
+  ea = &array[0];
+  lm = &array[64];
+  verify_diff (-64);
+
+  ea = &array[64];
+  lm = &array[0];
+  verify_diff (64);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/compile1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/compile1.c
new file mode 100644
index 000000000..ee7a32ad2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/compile1.c
@@ -0,0 +1,109 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* Valid __ea declarations.  */
+
+/* { dg-do compile } */
+
+/* Typedefs.  */
+typedef __ea int ea_int_t;
+typedef __ea int *ea_int_star_t;
+typedef int outer_t;
+
+/* Externs.  */
+
+__ea extern int i1;
+extern __ea int i2;
+extern int __ea i3;
+extern __ea ea_int_t i4;		/* __ea qualifier permitted via typedef.  */
+extern int __ea __ea __ea dupe;		/* __ea duplicate permitted directly.  */
+extern int __ea *ppu;
+
+/* Pointers.  */
+__ea int *i4p;
+
+/* Structs.  */
+struct st {
+  __ea int *p;
+};
+
+/* Variable definitions.  */
+__ea int ii0;
+int *__ea ii1;
+static int __ea ii2;
+
+void
+f1 ()
+{
+  int *spu;
+  ppu = (ea_int_t *) spu;
+  ppu = (ea_int_star_t) spu;
+}
+
+void
+f2 ()
+{
+  int *spu;
+  spu = (int *) ppu;
+  ppu = (__ea int *) spu;
+}
+
+void
+f3 ()
+{
+  int i = sizeof (__ea int);
+}
+
+__ea int *f4 (void)
+{
+  return 0;
+}
+
+int f5 (__ea int *parm)
+{
+  static __ea int local4;
+  int tmp = local4;
+  local4 = *parm;
+  return tmp;
+}
+
+static inline __ea void *f6 (__ea void *start)
+{
+  return 0;
+}
+
+void f7 (void)
+{
+  __ea void *s1;
+  auto __ea void *s2;
+}
+
+__ea int *f8 (__ea int *x)
+{
+  register __ea int *y = x;
+  __ea int *z = y;
+  return z;
+}
+
+long long f9 (__ea long long x[2])
+{
+  return x[0] + x[1];
+}
+
+void f10 ()
+{
+  static __ea outer_t o;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/compile2.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/compile2.c
new file mode 100644
index 000000000..58e64890e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/compile2.c
@@ -0,0 +1,43 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* Make sure __ea structure references work.  */
+
+/* { dg-do compile } */
+
+typedef unsigned long int uintptr_t;
+
+struct tostruct
+{
+  uintptr_t selfpc;
+  long count;
+  unsigned short link;
+};
+
+/* froms are indexing tos */
+static __ea unsigned short *froms;
+static __ea struct tostruct *tos = 0;
+
+void
+foo (uintptr_t frompc, uintptr_t selfpc)
+{
+  __ea unsigned short *frompcindex;
+
+  frompcindex = &froms[(frompc) / (4 * sizeof (*froms))];
+  *frompcindex = tos[0].link;
+
+  return;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cppdefine.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cppdefine.c
new file mode 100644
index 000000000..583635734
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/cppdefine.c
@@ -0,0 +1,36 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* Test default __EA32__/__EA64__ define.  */
+
+/* { dg-do compile } */
+
+#if !defined (__EA32__) && !defined (__EA64__)
+#error both __EA32__ and __EA64__ undefined
+#endif
+
+#if defined (__EA32__) && defined (__EA64__)
+#error both __EA32__ and __EA64__ defined
+#endif
+
+#ifdef __EA32__
+int x [ sizeof (__ea char *) == 4 ? 1 : -1 ];
+#endif
+
+#ifdef __EA64__
+int x [ sizeof (__ea char *) == 8 ? 1 : -1 ];
+#endif
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ea.exp b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ea.exp
new file mode 100644
index 000000000..2e04f9d77
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ea.exp
@@ -0,0 +1,54 @@
+#   Copyright (C) 2008-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a SPU target.
+if { ![istarget spu-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Return 1 if target __ea library functions are available
+proc check_effective_target_ealib { } {
+    return [check_no_compiler_messages ealib executable {
+	#include <ea.h>
+	int main (void)
+	{
+	    __ea void *ptr = malloc_ea (1024);
+	    return 0;
+	}
+    }]
+}
+
+# If a testcase doesn't have special options, use these.
+# We do not use the global DEFAULT_CFLAGS as all test cases
+# in this directory use the __ea address space qualifier
+# extension and thus will not compile with -ansi.
+set DEFAULT_EA_CFLAGS "-std=gnu99 -pedantic-errors -O2"
+
+# Initialize `dg'.
+dg-init
+
+# Run all tests in both -mea32 and -mea64 mode.
+set tests [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]]
+dg-runtest $tests "-mea32" $DEFAULT_EA_CFLAGS
+dg-runtest $tests "-mea64" $DEFAULT_EA_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/errors1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/errors1.c
new file mode 100644
index 000000000..7d0b5a11c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/errors1.c
@@ -0,0 +1,67 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* Invalid __ea declarations.  */
+
+/* { dg-do compile } */
+
+typedef __ea int eaint;
+
+void func ()
+{
+  register __ea int local1; /* { dg-error "'__ea' combined with 'register' qualifier for 'local1'" } */
+  auto __ea int local2;     /* { dg-error "'__ea' combined with 'auto' qualifier for 'local2'" } */
+  __ea int local3;	    /* { dg-error "'__ea' specified for auto variable 'local3'" } */
+  register int *__ea p1;    /* { dg-error "'__ea' combined with 'register' qualifier for 'p1'" } */
+  auto char *__ea p2;       /* { dg-error "'__ea' combined with 'auto' qualifier for 'p2'" } */
+  void *__ea p3;            /* { dg-error "'__ea' specified for auto variable 'p3'" } */
+  register __ea int a1[2];  /* { dg-error "'__ea' combined with 'register' qualifier for 'a1'" } */
+  auto __ea char a2[1];     /* { dg-error "'__ea' combined with 'auto' qualifier for 'a2'" } */
+  __ea char a3[5];          /* { dg-error "'__ea' specified for auto variable 'a3'" } */
+  register eaint td1;       /* { dg-error "'__ea' combined with 'register' qualifier for 'td1'" } */
+  auto eaint td2;           /* { dg-error "'__ea' combined with 'auto' qualifier for 'td2'" } */
+  eaint td3;	            /* { dg-error "'__ea' specified for auto variable 'td3'" } */
+}
+
+void func2 (__ea int x)	    /* { dg-error "'__ea' specified for parameter 'x'" } */
+{ }
+
+void func2td (eaint x)	    /* { dg-error "'__ea' specified for parameter 'x'" } */
+{ }
+
+struct st {
+  __ea int x;		    /* { dg-error "'__ea' specified for structure field 'x'" } */
+  eaint td;		    /* { dg-error "'__ea' specified for structure field 'td'" } */
+  int *__ea q;		    /* { dg-error "'__ea' specified for structure field 'q'" } */
+  int __ea b : 7;	    /* { dg-error "'__ea' specified for structure field 'b'" } */
+  int __ea : 1;		    /* { dg-error "'__ea' specified for structure field" } */
+} s;
+
+struct A { int a; };
+
+int func3 (int *__ea);	    /* { dg-error "'__ea' specified for unnamed parameter" } */
+int func3 (int *__ea x)	    /* { dg-error "'__ea' specified for parameter 'x'" } */
+{
+  struct A i = (__ea struct A) { 1 };	/* { dg-error "compound literal qualified by address-space qualifier" } */
+  return i.a;
+}
+
+extern __ea int ea_var;		/* { dg-message "note: previous declaration of 'ea_var' was here" } */
+int ea_var;			/* { dg-error "conflicting named address spaces \\(generic vs __ea\\) for 'ea_var'" } */
+
+extern eaint ea_var_td;		/* { dg-message "note: previous declaration of 'ea_var_td' was here" } */
+int ea_var_td;			/* { dg-error "conflicting named address spaces \\(generic vs __ea\\) for 'ea_var_td'" } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/errors2.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/errors2.c
new file mode 100644
index 000000000..74a32ff5e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/errors2.c
@@ -0,0 +1,107 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* Invalid __ea declarations.  */
+
+/* { dg-do compile } */
+
+__ea char ea_str[] = "abc";
+char lm_str[] = "abc";
+
+__ea char *lm_ea_ptr1 = "abc";				/* { dg-error "initializer element is not computable at load time" } */
+__ea char *lm_ea_ptr2 = (__ea char *)"abc";		/* { dg-error "initializer element is not constant" } */
+__ea char *lm_ea_ptr3 = ea_str;
+__ea char *lm_ea_ptr4 = (__ea char *)ea_str;
+__ea char *lm_ea_ptr5 = lm_str;				/* { dg-error "initializer element is not computable at load time" } */
+__ea char *lm_ea_ptr6 = (__ea char *)lm_str;		/* { dg-error "initializer element is not constant" } */
+
+__ea char * __ea ea_ea_ptr1 = ea_str;
+__ea char * __ea ea_ea_ptr2 = (__ea char *)ea_str;
+
+char * __ea ea_lm_ptr1 = lm_str;
+char * __ea ea_lm_ptr2 = (char *)lm_str;
+
+struct foo {
+  int first;
+  __ea char *ptr;
+  int last;
+};
+
+__ea struct foo ea_struct1 = {
+  10,
+  (__ea char *)0,
+  11,
+};
+
+__ea struct foo ea_struct2 = {
+  20,
+  0,
+  21,
+};
+
+struct foo ea_struct3 = {
+  30,
+  ea_str,
+  31,
+};
+
+struct foo ea_struct4 = {
+  40,
+  (__ea char *)lm_str,	/* { dg-error "(initializer element is not constant)|(near initialization)" "" } */
+  41,
+};
+
+struct bar {
+  int first;
+  char *ptr;
+  int last;
+};
+
+__ea struct bar ea_struct5 = {
+  50,
+  0,
+  51,
+};
+
+__ea struct bar ea_struct6 = {
+  60,
+  (char *)0,
+  61,
+};
+
+__ea struct bar ea_struct7 = {
+  70,
+  lm_str,
+  71,
+};
+
+struct bar lm_struct8 = {
+  80,
+  0,
+  81,
+};
+
+struct bar lm_struct9 = {
+  90,
+  (char *)0,
+  91,
+};
+
+struct bar lm_struct10 = {
+  100,
+  lm_str,
+  101,
+};
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute1.c
new file mode 100644
index 000000000..99d6d6918
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute1.c
@@ -0,0 +1,41 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do compile } */
+
+#include <stdlib.h>
+
+__ea char str[] = "abc";
+
+int
+main (void)
+{
+  __ea char *p = str;
+
+  if (*p++ != 'a')
+    abort ();
+
+  if (*p++ != 'b')
+    abort ();
+
+  if (*p++ != 'c')
+    abort ();
+
+  if (*p++ != '\0')
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute2.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute2.c
new file mode 100644
index 000000000..5fce4e673
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute2.c
@@ -0,0 +1,41 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+
+#include <stdlib.h>
+
+char str[] = "abc";
+
+int
+main (void)
+{
+  __ea char *p = (__ea char *)str;
+
+  if (*p++ != 'a')
+    abort ();
+
+  if (*p++ != 'b')
+    abort ();
+
+  if (*p++ != 'c')
+    abort ();
+
+  if (*p++ != '\0')
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute3.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute3.c
new file mode 100644
index 000000000..1b8c139d7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/execute3.c
@@ -0,0 +1,39 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+
+#include <stdlib.h>
+
+int
+main (void)
+{
+  __ea char *p = (__ea char *)"abc";
+
+  if (*p++ != 'a')
+    abort ();
+
+  if (*p++ != 'b')
+    abort ();
+
+  if (*p++ != 'c')
+    abort ();
+
+  if (*p++ != '\0')
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ops1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ops1.c
new file mode 100644
index 000000000..0d162f218
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ops1.c
@@ -0,0 +1,94 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* This is the same as ops2.c except for the compile option.
+   If you modify this code, please modify ops2.c as well.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -std=gnu99 -pedantic-errors -maddress-space-conversion" } */
+
+#define __lm
+
+__ea int ea_var = 1;
+__lm int lm_var = 2;
+
+typedef __ea int *ea_ptr_t;
+typedef __lm int *lm_ptr_t;
+
+typedef __ea void *ea_vptr_t;
+typedef __lm void *lm_vptr_t;
+
+ea_ptr_t ea, ea2;
+lm_ptr_t lm, lm2;
+
+ea_vptr_t eav;
+lm_vptr_t lmv;
+
+extern void call_ea (ea_ptr_t);
+extern void call_lm (lm_ptr_t);
+
+/* Assignment, initialization, argument passing, and return.  */
+void to_ea (void) { ea = lm; }
+void to_lm (void) { lm = ea; }			/* { dg-error "assignment from pointer to non-enclosed address space" } */
+void init_ea (void) { ea_ptr_t l_ea = lm; }
+void init_lm (void) { lm_ptr_t l_lm = ea; }	/* { dg-error "initialization from pointer to non-enclosed address space" } */
+ea_ptr_t ret_ea (void) { return lm; }
+lm_ptr_t ret_lm (void) { return ea; }		/* { dg-error "return from pointer to non-enclosed address space" } */
+void call_ea2 (void) { call_ea (lm); }
+void call_lm2 (void) { call_lm (ea); }		/* { dg-error "passing argument 1 of 'call_lm' from pointer to non-enclosed address space" } */
+
+/* Explicit casts.  */
+void to_ea_with_cast (void) { ea = (ea_ptr_t)lm; }
+void to_lm_with_cast (void) { lm = (lm_ptr_t)ea; }
+void init_ea_with_cast (void) { ea_ptr_t l_ea = (ea_ptr_t)lm; }
+void init_lm_with_cast (void) { lm_ptr_t l_lm = (lm_ptr_t)ea; }
+ea_ptr_t ret_ea_with_cast (void) { return (ea_ptr_t)lm; }
+lm_ptr_t ret_lm_with_cast (void) { return (lm_ptr_t)ea; }
+void call_ea2_with_cast (void) { call_ea ((ea_ptr_t)lm); }
+void call_lm2_with_cast (void) { call_lm ((lm_ptr_t)ea); }
+
+/* Arithmetic operators.  */
+int sub_eaea (void) { return ea - ea2; }
+int sub_ealm (void) { return ea - lm2; }
+int sub_lmea (void) { return lm - ea2; }
+int sub_lmlm (void) { return lm - lm2; }
+ea_ptr_t if_eaea1 (int test) { return test? ea : ea2; }
+lm_ptr_t if_eaea2 (int test) { return test? ea : ea2; }	/* { dg-error "return from pointer to non-enclosed address space" } */
+ea_ptr_t if_ealm1 (int test) { return test? ea : lm2; }
+lm_ptr_t if_ealm2 (int test) { return test? ea : lm2; }	/* { dg-error "return from pointer to non-enclosed address space" } */
+ea_ptr_t if_lmea1 (int test) { return test? lm : ea2; }
+lm_ptr_t if_lmea2 (int test) { return test? lm : ea2; }	/* { dg-error "return from pointer to non-enclosed address space" } */
+ea_ptr_t if_lmlm1 (int test) { return test? lm : lm2; }
+lm_ptr_t if_lmlm2 (int test) { return test? lm : lm2; }
+
+/* Relational operators.  */
+int eq_eaea (void) { return ea == ea2; }
+int eq_ealm (void) { return ea == lm2; }
+int eq_lmea (void) { return lm == ea2; }
+int eq_lmlm (void) { return lm == lm2; }
+int lt_eaea (void) { return ea < ea2; }
+int lt_ealm (void) { return ea < lm2; }
+int lt_lmea (void) { return lm < ea2; }
+int lt_lmlm (void) { return lm < lm2; }
+
+/* Null pointer.  */
+void null_ea1 (void) { ea = 0; }
+void null_ea2 (void) { ea = (void *)0; }
+void null_ea3 (void) { ea = (__ea void *)0; }
+void null_lm1 (void) { lm = 0; }
+void null_lm2 (void) { lm = (void *)0; }
+void null_lm3 (void) { lm = (__ea void *)0; }	/* { dg-error "assignment from pointer to non-enclosed address space" } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ops2.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ops2.c
new file mode 100644
index 000000000..2514e6b20
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/ops2.c
@@ -0,0 +1,94 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* This is the same as ops1.c except for the compile option.
+   If you modify this code, please modify ops1.c as well.  */
+
+/* { dg-do compile } */
+/* { dg-options "-O2 -std=gnu99 -pedantic-errors -mno-address-space-conversion" } */
+
+#define __lm
+
+__ea int ea_var = 1;
+__lm int lm_var = 2;
+
+typedef __ea int *ea_ptr_t;
+typedef __lm int *lm_ptr_t;
+
+typedef __ea void *ea_vptr_t;
+typedef __lm void *lm_vptr_t;
+
+ea_ptr_t ea, ea2;
+lm_ptr_t lm, lm2;
+
+ea_vptr_t eav;
+lm_vptr_t lmv;
+
+extern void call_ea (ea_ptr_t);
+extern void call_lm (lm_ptr_t);
+
+/* Assignment, initialization, argument passing, and return.  */
+void to_ea (void) { ea = lm; }			/* { dg-error "assignment from pointer to non-enclosed address space" } */
+void to_lm (void) { lm = ea; }			/* { dg-error "assignment from pointer to non-enclosed address space" } */
+void init_ea (void) { ea_ptr_t l_ea = lm; }	/* { dg-error "initialization from pointer to non-enclosed address space" } */
+void init_lm (void) { lm_ptr_t l_lm = ea; }	/* { dg-error "initialization from pointer to non-enclosed address space" } */
+ea_ptr_t ret_ea (void) { return lm; }		/* { dg-error "return from pointer to non-enclosed address space" } */
+lm_ptr_t ret_lm (void) { return ea; }		/* { dg-error "return from pointer to non-enclosed address space" } */
+void call_ea2 (void) { call_ea (lm); }		/* { dg-error "passing argument 1 of 'call_ea' from pointer to non-enclosed address space" } */
+void call_lm2 (void) { call_lm (ea); }		/* { dg-error "passing argument 1 of 'call_lm' from pointer to non-enclosed address space" } */
+
+/* Explicit casts.  */
+void to_ea_with_cast (void) { ea = (ea_ptr_t)lm; }		/* { dg-warning "cast to __ea address space pointer" } */
+void to_lm_with_cast (void) { lm = (lm_ptr_t)ea; }		/* { dg-warning "cast to generic address space pointer" } */
+void init_ea_with_cast (void) { ea_ptr_t l_ea = (ea_ptr_t)lm; }	/* { dg-warning "cast to __ea address space pointer" } */
+void init_lm_with_cast (void) { lm_ptr_t l_lm = (lm_ptr_t)ea; }	/* { dg-warning "cast to generic address space pointer" } */
+ea_ptr_t ret_ea_with_cast (void) { return (ea_ptr_t)lm; }	/* { dg-warning "cast to __ea address space pointer" } */
+lm_ptr_t ret_lm_with_cast (void) { return (lm_ptr_t)ea; }	/* { dg-warning "cast to generic address space pointer" } */
+void call_ea2_with_cast (void) { call_ea ((ea_ptr_t)lm); }	/* { dg-warning "cast to __ea address space pointer" } */
+void call_lm2_with_cast (void) { call_lm ((lm_ptr_t)ea); }	/* { dg-warning "cast to generic address space pointer" } */
+
+/* Arithmetic operators.  */
+int sub_eaea (void) { return ea - ea2; }
+int sub_ealm (void) { return ea - lm2; }		/* { dg-error "invalid operands to binary -" } */
+int sub_lmea (void) { return lm - ea2; }		/* { dg-error "invalid operands to binary -" } */
+int sub_lmlm (void) { return lm - lm2; }
+ea_ptr_t if_eaea1 (int test) { return test? ea : ea2; }
+lm_ptr_t if_eaea2 (int test) { return test? ea : ea2; }	/* { dg-error "return from pointer to non-enclosed address space" } */
+ea_ptr_t if_ealm1 (int test) { return test? ea : lm2; } /* { dg-error "pointers to disjoint address spaces used in conditional expression" } */
+lm_ptr_t if_ealm2 (int test) { return test? ea : lm2; } /* { dg-error "pointers to disjoint address spaces used in conditional expression" } */
+ea_ptr_t if_lmea1 (int test) { return test? lm : ea2; } /* { dg-error "pointers to disjoint address spaces used in conditional expression" } */
+lm_ptr_t if_lmea2 (int test) { return test? lm : ea2; } /* { dg-error "pointers to disjoint address spaces used in conditional expression" } */
+ea_ptr_t if_lmlm1 (int test) { return test? lm : lm2; }	/* { dg-error "return from pointer to non-enclosed address space" } */
+lm_ptr_t if_lmlm2 (int test) { return test? lm : lm2; }
+
+/* Relational operators.  */
+int eq_eaea (void) { return ea == ea2; }
+int eq_ealm (void) { return ea == lm2; }	/* { dg-error "comparison of pointers to disjoint address spaces" } */
+int eq_lmea (void) { return lm == ea2; }	/* { dg-error "comparison of pointers to disjoint address spaces" } */
+int eq_lmlm (void) { return lm == lm2; }
+int lt_eaea (void) { return ea < ea2; }
+int lt_ealm (void) { return ea < lm2; }		/* { dg-error "comparison of pointers to disjoint address spaces" } */
+int lt_lmea (void) { return lm < ea2; }		/* { dg-error "comparison of pointers to disjoint address spaces" } */
+int lt_lmlm (void) { return lm < lm2; }
+
+/* Null pointer.  */
+void null_ea1 (void) { ea = 0; }
+void null_ea2 (void) { ea = (void *)0; }
+void null_ea3 (void) { ea = (__ea void *)0; }
+void null_lm1 (void) { lm = 0; }
+void null_lm2 (void) { lm = (void *)0; }
+void null_lm3 (void) { lm = (__ea void *)0; }	/* { dg-error "assignment from pointer to non-enclosed address space" } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/options1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/options1.c
new file mode 100644
index 000000000..190400902
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/options1.c
@@ -0,0 +1,22 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* Test -mcache-size.  */
+
+/* { dg-do compile } */
+/* { dg-options "-mcache-size=128" } */
+
+int x;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/pr41857.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/pr41857.c
new file mode 100644
index 000000000..17710674c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/pr41857.c
@@ -0,0 +1,29 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do compile } */
+
+__ea char *strchr_ea (__ea const char *s, int c);
+__ea char *foo (__ea char *s)
+{
+  __ea char *ret = s;
+  int i;
+
+  for (i = 0; i < 3; i++)
+    ret = strchr_ea (ret, s[i]);
+ 
+  return ret;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/test-sizes.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/test-sizes.c
new file mode 100644
index 000000000..e467616b6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/ea/test-sizes.c
@@ -0,0 +1,608 @@
+/* Copyright (C) 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+
+#ifdef __EA32__
+#define EA_PTRSIZE 4
+#endif
+#ifdef __EA64__
+#define EA_PTRSIZE 8
+#endif
+
+#if !defined(LEVEL1) && !defined(LEVEL2) && !defined(LEVEL3)
+#define LEVEL1 1		/* single pointer indirection */
+#define LEVEL2 1		/* 2 levels of pointer indirection */
+#define LEVEL3 1		/* 3 levels of pointer indirection */
+
+#else
+#ifndef LEVEL1
+#define LEVEL1 0
+#endif
+
+#ifndef LEVEL2
+#define LEVEL2 0
+#endif
+
+#ifndef LEVEL3
+#define LEVEL3 0
+#endif
+#endif
+
+#if !defined(USE_SIMPLE) && !defined(USE_COMPLEX)
+#define USE_SIMPLE  1		/* build up pointers via multiple typedefs */
+#define USE_COMPLEX 1		/* single typedef for pointer indirections */
+
+#else
+#ifndef USE_SIMPLE
+#define USE_SIMPLE 0
+#endif
+
+#ifndef USE_COMPLEX
+#define USE_COMPLEX 0
+#endif
+#endif
+
+#if !defined(USE_LOCAL_VAR) && !defined(USE_EA_VAR)
+#define USE_LOCAL_VAR 1		/* use variables declared locally */
+#define USE_EA_VAR    1		/* use variables on the host */
+
+#else
+#ifndef USE_LOCAL_VAR
+#define USE_LOCAL_VAR 0
+#endif
+
+#ifndef USE_EA_VAR
+#define USE_EA_VAR    0
+#endif
+#endif
+
+static int errors;
+
+#ifdef USE_PRINTF		/* print results via printf */
+#include <stdio.h>
+#include <stdlib.h>
+
+static int num_tests;
+
+#define TEST_SIZE(EXPR, EXPECTED)					\
+do {									\
+  char *msg;								\
+									\
+  if (sizeof (EXPR) != EXPECTED)					\
+    {									\
+      msg = ", FAIL";							\
+      errors++;								\
+    }									\
+  else									\
+    msg = "";								\
+									\
+  num_tests++;								\
+  printf ("sizeof %-20s = %2u, expected = %2u%s\n",			\
+	  #EXPR,							\
+	  (unsigned) sizeof (EXPR),					\
+	  (unsigned) EXPECTED,						\
+	  msg);								\
+} while (0)
+
+#define PRINT1(FMT)	  printf (FMT)
+#define PRINT2(FMT,A1)	  printf (FMT,A1)
+#define PRINT3(FMT,A1,A2) printf (FMT,A1,A2)
+
+#else	/* standalone */
+extern void abort (void);
+
+#define TEST_SIZE(EXPR, EXPECTED)					\
+do {									\
+  if (sizeof (EXPR) != EXPECTED)					\
+    abort ();								\
+} while (0)
+
+#define PRINT1(FMT)
+#define PRINT2(FMT,ARG)
+#define PRINT3(FMT,A1,A2)
+#endif
+
+/* 'local memory' hack to keep the same spacing.  */
+#define __lm
+
+#if USE_SIMPLE
+#if (LEVEL1 || LEVEL2 || LEVEL3)
+typedef __lm char *lm_ptr_t;
+typedef __ea char *ea_ptr_t;
+#endif
+
+#if LEVEL1
+#if USE_LOCAL_VAR
+__lm lm_ptr_t lm_ptr;
+__lm ea_ptr_t ea_ptr;
+#endif
+
+#if USE_EA_VAR
+__ea lm_ptr_t lm_ptr_ea;
+__ea ea_ptr_t ea_ptr_ea;
+#endif
+#endif
+
+#if (LEVEL2 || LEVEL3)
+typedef __lm lm_ptr_t *lm_lm_ptr_t;
+typedef __ea lm_ptr_t *ea_lm_ptr_t;
+typedef __lm ea_ptr_t *lm_ea_ptr_t;
+typedef __ea ea_ptr_t *ea_ea_ptr_t;
+#endif
+
+#if LEVEL2
+#if USE_LOCAL_VAR
+__lm lm_lm_ptr_t lm_lm_ptr;
+__lm ea_lm_ptr_t ea_lm_ptr;
+__lm lm_ea_ptr_t lm_ea_ptr;
+__lm ea_ea_ptr_t ea_ea_ptr;
+#endif
+
+#if USE_EA_VAR
+__ea lm_lm_ptr_t lm_lm_ptr_ea;
+__ea ea_lm_ptr_t ea_lm_ptr_ea;
+__ea lm_ea_ptr_t lm_ea_ptr_ea;
+__ea ea_ea_ptr_t ea_ea_ptr_ea;
+#endif
+#endif
+
+#if LEVEL3
+typedef __lm lm_lm_ptr_t *lm_lm_lm_ptr_t;
+typedef __ea lm_lm_ptr_t *ea_lm_lm_ptr_t;
+typedef __lm ea_lm_ptr_t *lm_ea_lm_ptr_t;
+typedef __ea ea_lm_ptr_t *ea_ea_lm_ptr_t;
+typedef __lm lm_ea_ptr_t *lm_lm_ea_ptr_t;
+typedef __ea lm_ea_ptr_t *ea_lm_ea_ptr_t;
+typedef __lm ea_ea_ptr_t *lm_ea_ea_ptr_t;
+typedef __ea ea_ea_ptr_t *ea_ea_ea_ptr_t;
+
+#if USE_LOCAL_VAR
+__lm lm_lm_lm_ptr_t lm_lm_lm_ptr;
+__lm ea_lm_lm_ptr_t ea_lm_lm_ptr;
+__lm lm_ea_lm_ptr_t lm_ea_lm_ptr;
+__lm ea_ea_lm_ptr_t ea_ea_lm_ptr;
+__lm lm_lm_ea_ptr_t lm_lm_ea_ptr;
+__lm ea_lm_ea_ptr_t ea_lm_ea_ptr;
+__lm lm_ea_ea_ptr_t lm_ea_ea_ptr;
+__lm ea_ea_ea_ptr_t ea_ea_ea_ptr;
+#endif
+
+#if USE_EA_VAR
+__ea lm_lm_lm_ptr_t lm_lm_lm_ptr_ea;
+__ea ea_lm_lm_ptr_t ea_lm_lm_ptr_ea;
+__ea lm_ea_lm_ptr_t lm_ea_lm_ptr_ea;
+__ea ea_ea_lm_ptr_t ea_ea_lm_ptr_ea;
+__ea lm_lm_ea_ptr_t lm_lm_ea_ptr_ea;
+__ea ea_lm_ea_ptr_t ea_lm_ea_ptr_ea;
+__ea lm_ea_ea_ptr_t lm_ea_ea_ptr_ea;
+__ea ea_ea_ea_ptr_t ea_ea_ea_ptr_ea;
+#endif
+#endif
+#endif
+
+#if USE_COMPLEX
+#if LEVEL1
+#if USE_LOCAL_VAR
+__lm char *__lm lm_cptr;
+__ea char *__lm ea_cptr;
+#endif
+
+#if USE_EA_VAR
+__lm char *__ea lm_cptr_ea;
+__ea char *__ea ea_cptr_ea;
+#endif
+#endif
+
+#if LEVEL2
+#if USE_LOCAL_VAR
+__lm char *__lm *__lm lm_lm_cptr;
+__lm char *__ea *__lm ea_lm_cptr;
+__ea char *__lm *__lm lm_ea_cptr;
+__ea char *__ea *__lm ea_ea_cptr;
+#endif
+
+#if USE_EA_VAR
+__lm char *__lm *__ea lm_lm_cptr_ea;
+__lm char *__ea *__ea ea_lm_cptr_ea;
+__ea char *__lm *__ea lm_ea_cptr_ea;
+__ea char *__ea *__ea ea_ea_cptr_ea;
+#endif
+#endif
+
+#if LEVEL3
+#if USE_LOCAL_VAR
+__lm char *__lm *__lm *__lm lm_lm_lm_cptr;
+__lm char *__ea *__lm *__lm lm_ea_lm_cptr;
+__ea char *__lm *__lm *__lm lm_lm_ea_cptr;
+__ea char *__ea *__lm *__lm lm_ea_ea_cptr;
+__lm char *__lm *__ea *__lm ea_lm_lm_cptr;
+__lm char *__ea *__ea *__lm ea_ea_lm_cptr;
+__ea char *__lm *__ea *__lm ea_lm_ea_cptr;
+__ea char *__ea *__ea *__lm ea_ea_ea_cptr;
+#endif
+
+#if USE_EA_VAR
+__lm char *__lm *__lm *__ea lm_lm_lm_cptr_ea;
+__lm char *__ea *__lm *__ea lm_ea_lm_cptr_ea;
+__ea char *__lm *__lm *__ea lm_lm_ea_cptr_ea;
+__ea char *__ea *__lm *__ea lm_ea_ea_cptr_ea;
+__lm char *__lm *__ea *__ea ea_lm_lm_cptr_ea;
+__lm char *__ea *__ea *__ea ea_ea_lm_cptr_ea;
+__ea char *__lm *__ea *__ea ea_lm_ea_cptr_ea;
+__ea char *__ea *__ea *__ea ea_ea_ea_cptr_ea;
+#endif
+#endif
+#endif
+
+int
+main ()
+{
+  PRINT2 ("LEVEL1        = %d\n", LEVEL1);
+  PRINT2 ("LEVEL2        = %d\n", LEVEL2);
+  PRINT2 ("LEVEL3        = %d\n", LEVEL3);
+  PRINT2 ("USE_SIMPLE    = %d\n", USE_SIMPLE);
+  PRINT2 ("USE_COMPLEX   = %d\n", USE_COMPLEX);
+  PRINT2 ("USE_LOCAL_VAR = %d\n", USE_LOCAL_VAR);
+  PRINT2 ("USE_EA_VAR    = %d\n", USE_EA_VAR);
+  PRINT1 ("\n");
+
+#if USE_SIMPLE
+#if LEVEL1
+#if USE_LOCAL_VAR
+  TEST_SIZE ( lm_ptr, 4);
+  TEST_SIZE (*lm_ptr, 1);
+  TEST_SIZE ( ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (*ea_ptr, 1);
+  PRINT1 ("\n");
+#endif
+
+#if USE_EA_VAR
+  TEST_SIZE ( lm_ptr_ea, 4);
+  TEST_SIZE (*lm_ptr_ea, 1);
+  TEST_SIZE ( ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (*ea_ptr_ea, 1);
+  PRINT1 ("\n");
+#endif
+#endif
+
+#if LEVEL2
+#if USE_LOCAL_VAR
+  TEST_SIZE (  lm_lm_ptr, 4);
+  TEST_SIZE ( *lm_lm_ptr, 4);
+  TEST_SIZE (**lm_lm_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  lm_ea_ptr, 4);
+  TEST_SIZE ( *lm_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (**lm_ea_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  ea_lm_ptr, EA_PTRSIZE);
+  TEST_SIZE ( *ea_lm_ptr, 4);
+  TEST_SIZE (**ea_lm_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  ea_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE ( *ea_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (**ea_ea_ptr, 1);
+  PRINT1 ("\n");
+#endif
+
+#if USE_EA_VAR
+  TEST_SIZE (  lm_lm_ptr_ea, 4);
+  TEST_SIZE ( *lm_lm_ptr_ea, 4);
+  TEST_SIZE (**lm_lm_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  lm_ea_ptr_ea, 4);
+  TEST_SIZE ( *lm_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (**lm_ea_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  ea_lm_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( *ea_lm_ptr_ea, 4);
+  TEST_SIZE (**ea_lm_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  ea_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( *ea_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (**ea_ea_ptr_ea, 1);
+  PRINT1 ("\n");
+#endif
+#endif
+
+#if LEVEL3
+#if USE_LOCAL_VAR
+  TEST_SIZE (   lm_lm_lm_ptr, 4);
+  TEST_SIZE (  *lm_lm_lm_ptr, 4);
+  TEST_SIZE ( **lm_lm_lm_ptr, 4);
+  TEST_SIZE (***lm_lm_lm_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_lm_ea_ptr, 4);
+  TEST_SIZE (  *lm_lm_ea_ptr, 4);
+  TEST_SIZE ( **lm_lm_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (***lm_lm_ea_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_ea_lm_ptr, 4);
+  TEST_SIZE (  *lm_ea_lm_ptr, EA_PTRSIZE);
+  TEST_SIZE ( **lm_ea_lm_ptr, 4);
+  TEST_SIZE (***lm_ea_lm_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_ea_ea_ptr, 4);
+  TEST_SIZE (  *lm_ea_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE ( **lm_ea_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (***lm_ea_ea_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_lm_lm_ptr, EA_PTRSIZE);
+  TEST_SIZE (  *ea_lm_lm_ptr, 4);
+  TEST_SIZE ( **ea_lm_lm_ptr, 4);
+  TEST_SIZE (***ea_lm_lm_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_lm_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (  *ea_lm_ea_ptr, 4);
+  TEST_SIZE ( **ea_lm_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (***ea_lm_ea_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_ea_lm_ptr, EA_PTRSIZE);
+  TEST_SIZE (  *ea_ea_lm_ptr, EA_PTRSIZE);
+  TEST_SIZE ( **ea_ea_lm_ptr, 4);
+  TEST_SIZE (***ea_ea_lm_ptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_ea_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (  *ea_ea_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE ( **ea_ea_ea_ptr, EA_PTRSIZE);
+  TEST_SIZE (***ea_ea_ea_ptr, 1);
+  PRINT1 ("\n");
+#endif
+
+#if USE_EA_VAR
+  TEST_SIZE (   lm_lm_lm_ptr_ea, 4);
+  TEST_SIZE (  *lm_lm_lm_ptr_ea, 4);
+  TEST_SIZE ( **lm_lm_lm_ptr_ea, 4);
+  TEST_SIZE (***lm_lm_lm_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_lm_ea_ptr_ea, 4);
+  TEST_SIZE (  *lm_lm_ea_ptr_ea, 4);
+  TEST_SIZE ( **lm_lm_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (***lm_lm_ea_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_ea_lm_ptr_ea, 4);
+  TEST_SIZE (  *lm_ea_lm_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( **lm_ea_lm_ptr_ea, 4);
+  TEST_SIZE (***lm_ea_lm_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_ea_ea_ptr_ea, 4);
+  TEST_SIZE (  *lm_ea_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( **lm_ea_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (***lm_ea_ea_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_lm_lm_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (  *ea_lm_lm_ptr_ea, 4);
+  TEST_SIZE ( **ea_lm_lm_ptr_ea, 4);
+  TEST_SIZE (***ea_lm_lm_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_lm_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (  *ea_lm_ea_ptr_ea, 4);
+  TEST_SIZE ( **ea_lm_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (***ea_lm_ea_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_ea_lm_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (  *ea_ea_lm_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( **ea_ea_lm_ptr_ea, 4);
+  TEST_SIZE (***ea_ea_lm_ptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_ea_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (  *ea_ea_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( **ea_ea_ea_ptr_ea, EA_PTRSIZE);
+  TEST_SIZE (***ea_ea_ea_ptr_ea, 1);
+  PRINT1 ("\n");
+#endif
+#endif
+#endif
+
+#if USE_COMPLEX
+#if LEVEL1
+#if USE_LOCAL_VAR
+  TEST_SIZE ( lm_cptr, 4);
+  TEST_SIZE (*lm_cptr, 1);
+  TEST_SIZE ( ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (*ea_cptr, 1);
+  PRINT1 ("\n");
+#endif
+
+#if USE_EA_VAR
+  TEST_SIZE ( lm_cptr_ea, 4);
+  TEST_SIZE (*lm_cptr_ea, 1);
+  TEST_SIZE ( ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (*ea_cptr_ea, 1);
+  PRINT1 ("\n");
+#endif
+#endif
+
+#if LEVEL2
+#if USE_LOCAL_VAR
+  TEST_SIZE (  lm_lm_cptr, 4);
+  TEST_SIZE ( *lm_lm_cptr, 4);
+  TEST_SIZE (**lm_lm_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  lm_ea_cptr, 4);
+  TEST_SIZE ( *lm_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (**lm_ea_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  ea_lm_cptr, EA_PTRSIZE);
+  TEST_SIZE ( *ea_lm_cptr, 4);
+  TEST_SIZE (**ea_lm_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  ea_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE ( *ea_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (**ea_ea_cptr, 1);
+  PRINT1 ("\n");
+#endif
+
+#if USE_EA_VAR
+  TEST_SIZE (  lm_lm_cptr_ea, 4);
+  TEST_SIZE ( *lm_lm_cptr_ea, 4);
+  TEST_SIZE (**lm_lm_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  lm_ea_cptr_ea, 4);
+  TEST_SIZE ( *lm_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (**lm_ea_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  ea_lm_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( *ea_lm_cptr_ea, 4);
+  TEST_SIZE (**ea_lm_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (  ea_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( *ea_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (**ea_ea_cptr_ea, 1);
+  PRINT1 ("\n");
+#endif
+#endif
+
+#if LEVEL3
+#if USE_LOCAL_VAR
+  TEST_SIZE (   lm_lm_lm_cptr, 4);
+  TEST_SIZE (  *lm_lm_lm_cptr, 4);
+  TEST_SIZE ( **lm_lm_lm_cptr, 4);
+  TEST_SIZE (***lm_lm_lm_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_lm_ea_cptr, 4);
+  TEST_SIZE (  *lm_lm_ea_cptr, 4);
+  TEST_SIZE ( **lm_lm_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (***lm_lm_ea_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_ea_lm_cptr, 4);
+  TEST_SIZE (  *lm_ea_lm_cptr, EA_PTRSIZE);
+  TEST_SIZE ( **lm_ea_lm_cptr, 4);
+  TEST_SIZE (***lm_ea_lm_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_ea_ea_cptr, 4);
+  TEST_SIZE (  *lm_ea_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE ( **lm_ea_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (***lm_ea_ea_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_lm_lm_cptr, EA_PTRSIZE);
+  TEST_SIZE (  *ea_lm_lm_cptr, 4);
+  TEST_SIZE ( **ea_lm_lm_cptr, 4);
+  TEST_SIZE (***ea_lm_lm_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_lm_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (  *ea_lm_ea_cptr, 4);
+  TEST_SIZE ( **ea_lm_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (***ea_lm_ea_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_ea_lm_cptr, EA_PTRSIZE);
+  TEST_SIZE (  *ea_ea_lm_cptr, EA_PTRSIZE);
+  TEST_SIZE ( **ea_ea_lm_cptr, 4);
+  TEST_SIZE (***ea_ea_lm_cptr, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_ea_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (  *ea_ea_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE ( **ea_ea_ea_cptr, EA_PTRSIZE);
+  TEST_SIZE (***ea_ea_ea_cptr, 1);
+  PRINT1 ("\n");
+#endif
+
+#if USE_EA_VAR
+  TEST_SIZE (   lm_lm_lm_cptr_ea, 4);
+  TEST_SIZE (  *lm_lm_lm_cptr_ea, 4);
+  TEST_SIZE ( **lm_lm_lm_cptr_ea, 4);
+  TEST_SIZE (***lm_lm_lm_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_lm_ea_cptr_ea, 4);
+  TEST_SIZE (  *lm_lm_ea_cptr_ea, 4);
+  TEST_SIZE ( **lm_lm_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (***lm_lm_ea_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_ea_lm_cptr_ea, 4);
+  TEST_SIZE (  *lm_ea_lm_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( **lm_ea_lm_cptr_ea, 4);
+  TEST_SIZE (***lm_ea_lm_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   lm_ea_ea_cptr_ea, 4);
+  TEST_SIZE (  *lm_ea_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( **lm_ea_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (***lm_ea_ea_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_lm_lm_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (  *ea_lm_lm_cptr_ea, 4);
+  TEST_SIZE ( **ea_lm_lm_cptr_ea, 4);
+  TEST_SIZE (***ea_lm_lm_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_lm_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (  *ea_lm_ea_cptr_ea, 4);
+  TEST_SIZE ( **ea_lm_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (***ea_lm_ea_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_ea_lm_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (  *ea_ea_lm_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( **ea_ea_lm_cptr_ea, 4);
+  TEST_SIZE (***ea_ea_lm_cptr_ea, 1);
+  PRINT1 ("\n");
+
+  TEST_SIZE (   ea_ea_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (  *ea_ea_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE ( **ea_ea_ea_cptr_ea, EA_PTRSIZE);
+  TEST_SIZE (***ea_ea_ea_cptr_ea, 1);
+  PRINT1 ("\n");
+#endif
+#endif
+#endif
+
+  if (errors)
+    {
+      PRINT3 ("%d error(s), %d test(s)\n", errors, num_tests);
+      abort ();
+    }
+  else
+    PRINT2 ("No errors, %d test(s)\n", num_tests);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/fixed-range-bad.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/fixed-range-bad.c
new file mode 100644
index 000000000..099328378
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/fixed-range-bad.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-mfixed-range=1-x" } */
+/* { dg-warning "unknown register name" "" { target spu-*-* } 0 } */
+
+int i;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/fixed-range.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/fixed-range.c
new file mode 100644
index 000000000..8dcb7fe4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/fixed-range.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mfixed-range=1-20" } */
+/* { dg-final { scan-assembler "lqd.*21" } } */
+
+int foo (int i)
+{
+  return i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-1.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-1.c
new file mode 100644
index 000000000..2720889f0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99 -pedantic-errors" } */
+#include <spu_intrinsics.h>
+/* With this intrinsics section, we used to ICE as we would try
+   to convert from an vector to an integer type.  */
+void f(void)
+{
+  vec_uint4 gt, N;
+  vec_int4 a;
+  int *a1;
+  _Complex double b;
+  gt = spu_cmpgt(a, N); /* { dg-error "parameter list" } */
+  gt = spu_cmpgt(a, a1); /* { dg-error "integer from pointer without a cast" } */
+  gt = spu_cmpgt(a, b); /* { dg-error "parameter list" } */
+  gt = spu_cmpgt(a, a);
+  a = spu_cmpgt(a, a); /* { dg-message "note: use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts" } */ 
+/* { dg-message "note: expected 'int'" "" { target *-*-* } 13 } */
+/* { dg-error "incompatible types when assigning" "" { target *-*-* } 16 } */
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-2.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-2.c
new file mode 100644
index 000000000..43a272b91
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-2.c
@@ -0,0 +1,305 @@
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+#include <vec_types.h>
+extern void abort (void);
+extern void exit (int);
+
+typedef union {
+  vec_ullong2   vull;
+  vec_double2   vd;
+  unsigned int  ui[4];
+  unsigned long long ull[2];
+  double        d[2];
+} v128;
+
+static v128 a, b, c, d, a0, b0, a1, b1;
+static int samples = 10;
+unsigned int seed = 0;
+
+unsigned int rand_local()
+{
+  seed = seed * 69607 + 54329;
+  return (seed);
+}
+
+double rand_double(double min, double max)
+{
+  union {
+    unsigned int ui[2];
+    double d;
+  } x;
+
+  x.ui[0] = (rand_local() & 0x000FFFFF) | 0x3FF00000;
+  x.ui[1] = rand_local();
+  x.d -= 1.0;
+  x.d *= max - min;
+  x.d += min;
+  return (x.d);
+}
+
+vec_double2 rand_vd(double min, double max)
+{
+  int i;
+  static v128 val;
+
+  for (i=0; i<2; i++) val.d[i] = rand_double(min, max);
+  return (val.vd);
+}
+
+int test_spu_cmpeq()
+{
+  int i, j;
+  unsigned long long exp;
+
+  /* double */
+  for (i=0; i<samples; i++) {
+    a.vd = rand_vd(-4.0, 4.0);
+    b.vd = rand_vd(-4.0, 4.0);
+    d.vull = spu_cmpeq(a.vd, b.vd);
+    for (j=0; j<2; j++) {
+      exp = (a.d[j] == b.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  }
+
+  /* compare zeros  */
+    d.vull = spu_cmpeq(a0.vd, b0.vd);
+    for (j=0; j<2; j++) {
+      exp = (a0.d[j] == b0.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+
+  /* compare NaNs  */
+    d.vull = spu_cmpeq(a1.vd, b1.vd);
+    for (j=0; j<2; j++) {
+      exp = (a1.d[j] == b1.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  return 0;
+}
+
+int test_spu_cmpgt()
+{   
+  int i, j;
+  unsigned long long exp;
+
+  /* double */
+  for (i=0; i<samples; i++) {
+    a.vd = rand_vd(-4.0, 4.0);
+    b.vd = rand_vd(-4.0, 4.0);
+    d.vull = spu_cmpgt(a.vd, b.vd);
+    for (j=0; j<2; j++) {
+      exp = (a.d[j] > b.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    } 
+  }
+
+  /* compare zeros  */
+    d.vull = spu_cmpgt(a0.vd, b0.vd);
+    for (j=0; j<2; j++) {
+      exp = (a0.d[j] > b0.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  /* compare NaNs  */
+    d.vull = spu_cmpgt(a1.vd, b1.vd);
+    for (j=0; j<2; j++) {
+      exp = (a1.d[j] > b1.d[j]) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  return 0;
+}
+
+int test_spu_cmpabseq()
+{   
+  int i, j;
+  unsigned long long exp;
+
+  /* double */
+  for (i=0; i<samples; i++) {
+    a.vd = rand_vd(-4.0, 4.0);
+    b.vd = rand_vd(-4.0, 4.0);
+    d.vull = spu_cmpabseq(a.vd, b.vd);
+    for (j=0; j<2; j++) {
+      exp = ((a.d[j] == b.d[j]) || (-a.d[j] == b.d[j]) || (a.d[j] == -b.d[j])) ?
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    } 
+  }
+
+  /* compare zeros  */
+    d.vull = spu_cmpabseq(a0.vd, b0.vd);
+    for (j=0; j<2; j++) {
+      exp = ((a0.d[j] == b0.d[j]) || (-a0.d[j] == b0.d[j]) || (a0.d[j] == -b0.d[j])) ?
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+
+  /* compare NaNs  */
+    d.vull = spu_cmpabseq(a1.vd, b1.vd);
+    for (j=0; j<2; j++) {
+      exp = ((a1.d[j] == b1.d[j]) || (-a1.d[j] == b1.d[j]) || (a1.d[j] == -b1.d[j])) ?
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  return 0;
+}
+
+int test_spu_cmpabsgt()
+{
+  int i, j;
+  unsigned long long exp;
+  double abs_a, abs_b;
+  
+  /* double */
+  for (i=0; i<samples; i++) {
+    a.vd = rand_vd(-4.0, 4.0);
+    b.vd = rand_vd(-4.0, 4.0);
+    d.vull = spu_cmpabsgt(a.vd, b.vd);
+    for (j=0; j<2; j++) {
+      double abs_a = (a.d[j] < 0.0) ? -a.d[j] : a.d[j];
+      double abs_b = (b.d[j] < 0.0) ? -b.d[j] : b.d[j];
+      exp = (abs_a > abs_b) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  }
+
+  /* compare zeros  */
+    d.vull = spu_cmpabsgt(a0.vd, b0.vd);
+    for (j=0; j<2; j++) {
+      abs_a = (a0.d[j] < 0.0) ? -a0.d[j] : a0.d[j];
+      abs_b = (b0.d[j] < 0.0) ? -b0.d[j] : b0.d[j];
+      exp = (abs_a > abs_b) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  /* compare NaNs  */
+    d.vull = spu_cmpabsgt(a1.vd, b1.vd);
+    for (j=0; j<2; j++) {
+      abs_a = (a1.d[j] < 0.0) ? -a1.d[j] : a1.d[j];
+      abs_b = (b1.d[j] < 0.0) ? -b1.d[j] : b1.d[j];
+      exp = (abs_a > abs_b) ? 
+	    (((unsigned long long)(0xFFFFFFFF) << 32) 
+	     | (unsigned long long)(0xFFFFFFFF)) : 0;
+      if (exp != d.ull[j]) abort();
+    }
+  return 0;
+}
+
+int test_spu_testsv()
+{
+  int i, j;
+  unsigned long long exp;
+  struct _samples {
+    unsigned long long v;
+    unsigned int sv;
+ } samples[] = {
+  {0x0000000000000000ULL, SPU_SV_POS_ZERO},
+  {0x8000000000000000ULL, SPU_SV_NEG_ZERO},
+  {0x0000000000000001ULL, SPU_SV_POS_DENORM},
+  {0x0000000080000000ULL, SPU_SV_POS_DENORM},
+  {0x0000000100000000ULL, SPU_SV_POS_DENORM},
+  {0x0008000000000000ULL, SPU_SV_POS_DENORM},
+  {0x000FFFFFFFFFFFFFULL, SPU_SV_POS_DENORM},
+  {0x00000000FFF00000ULL, SPU_SV_POS_DENORM},
+  {0x8000000000000001ULL, SPU_SV_NEG_DENORM},
+  {0x8000000080000000ULL, SPU_SV_NEG_DENORM},
+  {0x8000000100000000ULL, SPU_SV_NEG_DENORM},
+  {0x8008000000000000ULL, SPU_SV_NEG_DENORM},
+  {0x800FFFFFFFFFFFFFULL, SPU_SV_NEG_DENORM},
+  {0x80000000FFF00000ULL, SPU_SV_NEG_DENORM},
+  {0x0010000000000000ULL, 0},
+  {0x0010000000000001ULL, 0},
+  {0x3FF0000000000000ULL, 0},
+  {0x3FF00000FFF00000ULL, 0},
+  {0xBFF0000000000000ULL, 0},
+  {0xBFF00000FFF00000ULL, 0},
+  {0x7FE0000000000000ULL, 0},
+  {0x7FEFFFFFFFFFFFFFULL, 0},
+  {0x8010000000000000ULL, 0},
+  {0x8010000000000001ULL, 0},
+  {0xFFE0000000000000ULL, 0},
+  {0xFFEFFFFFFFFFFFFFULL, 0},
+  {0x7FF0000000000000ULL, SPU_SV_POS_INFINITY},
+  {0xFFF0000000000000ULL, SPU_SV_NEG_INFINITY},
+  {0x7FF0000000000001ULL, SPU_SV_NAN},
+  {0x7FF0000080000000ULL, SPU_SV_NAN},
+  {0x7FF0000100000000ULL, SPU_SV_NAN},
+  {0x7FFFFFFFFFFFFFFFULL, SPU_SV_NAN},
+  {0xFFF0000000000001ULL, SPU_SV_NAN},
+  {0xFFF0000080000000ULL, SPU_SV_NAN},
+  {0xFFF0000100000000ULL, SPU_SV_NAN},
+  {0xFFFFFFFFFFFFFFFFULL, SPU_SV_NAN}
+ };
+
+  unsigned char cnt = sizeof(samples)/sizeof(struct _samples);
+  int e0;
+    for (e0=0; e0<cnt; e0++)
+    {   
+      a.ull[0] = samples[e0].v;
+      a.d[1] = rand_double(-1, -4);
+
+      d.vull = spu_testsv(a.vd, SPU_SV_NEG_DENORM);
+      exp = (SPU_SV_NEG_DENORM & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_POS_DENORM);
+      exp = (SPU_SV_POS_DENORM & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_NEG_ZERO);
+      exp = (SPU_SV_NEG_ZERO & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_POS_ZERO);
+      exp = (SPU_SV_POS_ZERO & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_NEG_INFINITY);
+      exp = (SPU_SV_NEG_INFINITY & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_POS_INFINITY);
+      exp = (SPU_SV_POS_INFINITY & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+    
+      d.vull = spu_testsv(a.vd, SPU_SV_NAN);
+      exp = (SPU_SV_NAN & samples[e0].sv) ? 0xFFFFFFFFFFFFFFFFULL : 0ULL;
+      if (exp != d.ull[0] || d.ull[1] != 0) abort();
+   }  
+  return 0;
+}
+
+int main()
+{
+  /* +0.0 and -0.0  */
+  a0.d[0] = 0.0; a0.d[1] = -0.0; b0.d[0] = -0.0; b0.d[1] = 0.0;
+  /* NaN  */
+  a1.d[0] = 0.0/0.0; a1.d[1] = 0.0/-0.0; b1.d[0] = -0.0/0.0;  b1.d[1] = -0.0/-0.0;
+
+  test_spu_cmpeq();
+  test_spu_cmpabseq();
+  test_spu_cmpgt();
+  test_spu_cmpabsgt();
+  test_spu_testsv();
+  return 0;
+}
+
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-3.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-3.c
new file mode 100644
index 000000000..3d3946641
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-3.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+#include <spu_intrinsics.h>
+void f0 (vec_uint4 *in)
+{
+  vec_float4 out = spu_convtf (in[0], 128); /* { dg-error "expects an integer literal in the range" "0, 127"  }*/
+}
+
+void f1 (vec_int4 *in)
+{
+  vec_float4 out = spu_convtf (in[0], 128); /* { dg-error "expects an integer literal in the range" "0, 127"  }*/
+}
+
+void f2 (vec_float4 *in)
+{
+  vec_int4 out = spu_convts (in[0], 128); /* { dg-error "expects an integer literal in the range" "0, 127"  }*/
+}
+
+void f3 (vec_float4 *in)
+{
+  vec_uint4 out = spu_convtu (in[0], 128); /* { dg-error "expects an integer literal in the range" "0, 127"  }*/
+}
+
+/* Test that these intrinsics accept non-literal arguments */
+void f4 (vec_uint4 *in, int n)
+{
+  vec_float4 out = spu_convtf (in[0], n); 
+}
+
+void f5 (vec_int4 *in, int n)
+{
+  vec_float4 out = spu_convtf (in[0], n);
+}
+
+void f6 (vec_float4 *in, int n)
+{
+  vec_int4 out = spu_convts (in[0], n);
+}
+
+void f7 (vec_float4 *in, int n)
+{
+  vec_uint4 out = spu_convtu (in[0], n);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-sr.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-sr.c
new file mode 100644
index 000000000..f7c62ddcb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/intrinsics-sr.c
@@ -0,0 +1,496 @@
+/* { dg-do compile } */
+/* { dg-options "-std=c99" } */
+
+#include <spu_intrinsics.h>
+
+/* spu_sr */
+
+vector unsigned short test_sr_1 (vector unsigned short ra, vector unsigned short count)
+{
+  return spu_sr (ra, count);
+}
+
+vector signed short test_sr_2 (vector signed short ra, vector unsigned short count)
+{
+  return spu_sr (ra, count);
+}
+
+vector unsigned int test_sr_3 (vector unsigned int ra, vector unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector signed int test_sr_4 (vector signed int ra, vector unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector unsigned short test_sr_5 (vector unsigned short ra)
+{
+  return spu_sr (ra, 11);
+}
+
+vector signed short test_sr_6 (vector signed short ra)
+{
+  return spu_sr (ra, 11);
+}
+
+vector unsigned short test_sr_7 (vector unsigned short ra, unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector signed short test_sr_8 (vector signed short ra, unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector unsigned int test_sr_9 (vector unsigned int ra)
+{
+  return spu_sr (ra, 11);
+}
+
+vector signed int test_sr_10 (vector signed int ra)
+{
+  return spu_sr (ra, 11);
+}
+
+vector unsigned int test_sr_11 (vector unsigned int ra, unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+vector signed int test_sr_12 (vector signed int ra, unsigned int count)
+{
+  return spu_sr (ra, count);
+}
+
+
+/* spu_sra */
+
+vector unsigned short test_sra_1 (vector unsigned short ra, vector unsigned short count)
+{
+  return spu_sra (ra, count);
+}
+
+vector signed short test_sra_2 (vector signed short ra, vector unsigned short count)
+{
+  return spu_sra (ra, count);
+}
+
+vector unsigned int test_sra_3 (vector unsigned int ra, vector unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector signed int test_sra_4 (vector signed int ra, vector unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector unsigned short test_sra_5 (vector unsigned short ra)
+{
+  return spu_sra (ra, 11);
+}
+
+vector signed short test_sra_6 (vector signed short ra)
+{
+  return spu_sra (ra, 11);
+}
+
+vector unsigned short test_sra_7 (vector unsigned short ra, unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector signed short test_sra_8 (vector signed short ra, unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector unsigned int test_sra_9 (vector unsigned int ra)
+{
+  return spu_sra (ra, 11);
+}
+
+vector signed int test_sra_10 (vector signed int ra)
+{
+  return spu_sra (ra, 11);
+}
+
+vector unsigned int test_sra_11 (vector unsigned int ra, unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+vector signed int test_sra_12 (vector signed int ra, unsigned int count)
+{
+  return spu_sra (ra, count);
+}
+
+/* spu_srqw */
+
+vector unsigned char test_srqw_1 (vector unsigned char ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed char test_srqw_2 (vector signed char ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned short test_srqw_3 (vector unsigned short ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed short test_srqw_4 (vector signed short ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned int test_srqw_5 (vector unsigned int ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed int test_srqw_6 (vector signed int ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned long test_srqw_7 (vector unsigned long ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed long test_srqw_8 (vector signed long ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned long long test_srqw_9 (vector unsigned long long ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector signed long long test_srqw_10 (vector signed long long ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector float test_srqw_11 (vector float ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector double test_srqw_12 (vector double ra)
+{
+  return spu_srqw (ra, 5);
+}
+
+vector unsigned char test_srqw_13 (vector unsigned char ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed char test_srqw_14 (vector signed char ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector unsigned short test_srqw_15 (vector unsigned short ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed short test_srqw_16 (vector signed short ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector unsigned int test_srqw_17 (vector unsigned int ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed int test_srqw_18 (vector signed int ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector unsigned long test_srqw_19 (vector unsigned long ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed long test_srqw_20 (vector signed long ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector unsigned long long test_srqw_21 (vector unsigned long long ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector signed long long test_srqw_22 (vector signed long long ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector float test_srqw_23 (vector float ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+vector double test_srqw_24 (vector double ra, unsigned int count)
+{
+  return spu_srqw (ra, count);
+}
+
+/* spu_srqwbyte */
+
+vector unsigned char test_srqwbyte_1 (vector unsigned char ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed char test_srqwbyte_2 (vector signed char ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned short test_srqwbyte_3 (vector unsigned short ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed short test_srqwbyte_4 (vector signed short ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned int test_srqwbyte_5 (vector unsigned int ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed int test_srqwbyte_6 (vector signed int ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned long test_srqwbyte_7 (vector unsigned long ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed long test_srqwbyte_8 (vector signed long ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned long long test_srqwbyte_9 (vector unsigned long long ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector signed long long test_srqwbyte_10 (vector signed long long ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector float test_srqwbyte_11 (vector float ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector double test_srqwbyte_12 (vector double ra)
+{
+  return spu_srqwbyte (ra, 5);
+}
+
+vector unsigned char test_srqwbyte_13 (vector unsigned char ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed char test_srqwbyte_14 (vector signed char ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector unsigned short test_srqwbyte_15 (vector unsigned short ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed short test_srqwbyte_16 (vector signed short ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector unsigned int test_srqwbyte_17 (vector unsigned int ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed int test_srqwbyte_18 (vector signed int ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector unsigned long test_srqwbyte_19 (vector unsigned long ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed long test_srqwbyte_20 (vector signed long ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector unsigned long long test_srqwbyte_21 (vector unsigned long long ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector signed long long test_srqwbyte_22 (vector signed long long ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector float test_srqwbyte_23 (vector float ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+vector double test_srqwbyte_24 (vector double ra, unsigned int count)
+{
+  return spu_srqwbyte (ra, count);
+}
+
+/* spu_srqwbytebc */
+
+vector unsigned char test_srqwbytebc_1 (vector unsigned char ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed char test_srqwbytebc_2 (vector signed char ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned short test_srqwbytebc_3 (vector unsigned short ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed short test_srqwbytebc_4 (vector signed short ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned int test_srqwbytebc_5 (vector unsigned int ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed int test_srqwbytebc_6 (vector signed int ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned long test_srqwbytebc_7 (vector unsigned long ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed long test_srqwbytebc_8 (vector signed long ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned long long test_srqwbytebc_9 (vector unsigned long long ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector signed long long test_srqwbytebc_10 (vector signed long long ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector float test_srqwbytebc_11 (vector float ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector double test_srqwbytebc_12 (vector double ra)
+{
+  return spu_srqwbytebc (ra, 40);
+}
+
+vector unsigned char test_srqwbytebc_13 (vector unsigned char ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed char test_srqwbytebc_14 (vector signed char ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector unsigned short test_srqwbytebc_15 (vector unsigned short ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed short test_srqwbytebc_16 (vector signed short ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector unsigned int test_srqwbytebc_17 (vector unsigned int ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed int test_srqwbytebc_18 (vector signed int ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector unsigned long test_srqwbytebc_19 (vector unsigned long ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed long test_srqwbytebc_20 (vector signed long ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector unsigned long long test_srqwbytebc_21 (vector unsigned long long ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector signed long long test_srqwbytebc_22 (vector signed long long ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector float test_srqwbytebc_23 (vector float ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
+vector double test_srqwbytebc_24 (vector double ra, unsigned int count)
+{
+  return spu_srqwbytebc (ra, count);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/muldivti3.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/muldivti3.c
new file mode 100644
index 000000000..0363e3420
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/muldivti3.c
@@ -0,0 +1,46 @@
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+#include <stdlib.h>
+typedef unsigned int uqword __attribute__((mode(TI)));
+typedef int qword __attribute__((mode(TI)));
+
+typedef union
+{
+  uqword                uq;
+  qword                 q;
+  unsigned long long    ull[2];
+} u;
+
+int main(void)
+{
+  uqword e, f;
+  qword g, h;
+
+  e = 0x1111111111111111ULL;
+  f = 0xFULL;
+  g = 0x0000000000111100ULL;
+  h = 0x0000000000000000ULL;
+
+  u m, n, o, p, q;
+
+  m.ull[0] = f;
+  m.ull[1] = e;
+  n.ull[0] = h;
+  n.ull[1] = g;
+
+  /* __multi3  */
+  o.q = m.q * n.q;
+
+  o.q = o.q + n.q + 0x1110FF;
+  /* __udivti3, __umodti3  */
+  p.uq = o.uq / n.uq;
+  q.uq = o.uq % n.uq;
+  if (p.uq != (m.uq+1)) abort();
+  if (q.uq != 0x1110FF) abort();
+  /* __divti3, __modti3  */
+  p.q = -o.q / n.q;
+  q.q = -o.q % n.q;
+  if ((-p.q * n.q - q.q) != o.q) abort();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/pr40001.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/pr40001.c
new file mode 100644
index 000000000..442f72d4f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/pr40001.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+void *
+sbrk (unsigned int increment)
+{
+  volatile register
+      __attribute__ ((__spu_vector__)) unsigned int sp_r1 __asm__ ("1");
+  unsigned int sps;
+
+  sps = __builtin_spu_extract (sp_r1, 0);
+  if (sps - 4096 >= increment)
+    return 0;
+  else
+    return ((void *) -1);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/spu.exp b/gcc-4.9/gcc/testsuite/gcc.target/spu/spu.exp
new file mode 100644
index 000000000..ea99c5802
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/spu.exp
@@ -0,0 +1,41 @@
+#   Copyright (C) 2005-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the 'dg.exp' driver.
+
+# Exit immediately if this isn't a SPU target.
+if { ![istarget spu-*-*] } then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize 'dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/subti3.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/subti3.c
new file mode 100644
index 000000000..4112c958c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/subti3.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-std=c99" } */
+#include <stdlib.h>
+typedef int TItype __attribute__ ((mode (TI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+
+struct DIstruct {DItype high, low;};
+typedef union
+{
+  struct DIstruct s;
+  TItype t;
+} TIunion;
+
+static
+void sub_ddmmss (UDItype *sh, UDItype *sl, UDItype ah, UDItype al, UDItype bh, UDItype bl)
+{
+  UDItype x;
+  x = al - bl;
+  *sh = ah - bh - (x > al);
+  *sl = x;
+}
+
+int main(void)
+{
+  TIunion aa, bb, cc;
+  TItype m = 0x1111111111111110ULL;
+  TItype n = 0x1111111111111111ULL;
+  TItype d;
+
+  aa.s.high = m;
+  aa.s.low = m;
+  bb.s.high = n;
+  bb.s.low = n;
+
+
+  sub_ddmmss (&cc.s.high, &cc.s.low, aa.s.high, aa.s.low, bb.s.high, bb.s.low);
+  d = aa.t - bb.t;
+  if (d != cc.t)
+   abort();
+  cc.t = aa.t -d;
+  if (cc.t != bb.t)
+   abort();
+ return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/tag_manager.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/tag_manager.c
new file mode 100644
index 000000000..4b3ab9f8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/tag_manager.c
@@ -0,0 +1,312 @@
+/* Copyright (C) 2007, 2009 Free Software Foundation, Inc.
+
+   This file is free software; you can redistribute it and/or modify it under
+   the terms of the GNU General Public License as published by the Free
+   Software Foundation; either version 3 of the License, or (at your option)
+   any later version.
+
+   This file is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING3.  If not see
+   <http://www.gnu.org/licenses/>.  */
+
+/* { dg-do run } */
+
+#include <spu_mfcio.h>
+#include <stdlib.h>
+
+/* This test directly accesses the internal table used
+   by the MFC tag manager.  */
+extern vector unsigned int __mfc_tag_table;
+
+
+/* This tag tests invalid tag release.  Invalid tag release does
+   nothing to the tag table.  */
+void
+test_tag_release01 (void)
+{
+  unsigned int copy;
+  copy = spu_extract (__mfc_tag_table, 0);
+
+  mfc_tag_release (35);
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+}
+
+/* More invalid release tests.  */
+void
+test_tag_release_invalid (void)
+{
+  unsigned int copy;
+  copy = spu_extract (__mfc_tag_table, 0);
+
+  if (mfc_tag_release (32) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+  if (mfc_tag_release (17) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+}
+
+/* Invalid multiple-tag release tests.  */
+void
+test_tag_group_release_invalid (void)
+{
+  unsigned int copy;
+  copy = spu_extract (__mfc_tag_table, 0);
+
+  if (mfc_multi_tag_release (32, 10) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+  if (mfc_multi_tag_release (28, 10) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+  if (mfc_multi_tag_release (17, 10) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+  if (mfc_multi_tag_release (32, 10) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+}
+
+/* The tag table should be in a pristine mode to run this test.  */
+void
+test_tag_reserve01 (void)
+{
+  unsigned int correct_table[32] =
+    {
+		  0x80000000, 0xC0000000, 0xE0000000,
+      0xF0000000, 0xF8000000, 0xFC000000, 0xFE000000,
+      0xFF000000, 0xFF800000, 0xFFC00000, 0xFFE00000,
+      0xFFF00000, 0xFFF80000, 0xFFFC0000, 0xFFFE0000,
+      0xFFFF0000, 0xFFFF8000, 0xFFFFC000, 0xFFFFE000,
+      0xFFFFF000, 0xFFFFF800, 0xFFFFFC00, 0xFFFFFE00,
+      0xFFFFFF00, 0xFFFFFF80, 0xFFFFFFC0, 0xFFFFFFE0,
+      0xFFFFFFF0, 0xFFFFFFF8, 0xFFFFFFFC, 0xFFFFFFFE,
+      0xFFFFFFFF
+    };
+
+  unsigned int tag;
+  unsigned int i;
+
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != i)
+	abort ();
+    }
+
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != MFC_TAG_INVALID)
+	abort ();
+    }
+
+  for (i = 0; i < 32; i++)
+    {
+      mfc_tag_release (i);
+      if (spu_extract (__mfc_tag_table, 0) != correct_table[i])
+	abort ();
+    }
+}
+
+/* The tag table should be in a pristine mode to run this test.  */
+void
+test_tag_reserve02 (void)
+{
+  unsigned int correct_table[32] =
+    {
+      0x80000000, 0xC0000000, 0xA0000000, 0xF0000000,
+      0xA8000000, 0xFC000000, 0xAA000000, 0xFF000000,
+      0xAA800000, 0xFFC00000, 0xAAA00000, 0xFFF00000,
+      0xAAA80000, 0xFFFC0000, 0xAAAA0000, 0xFFFF0000,
+      0xAAAA8000, 0xFFFFC000, 0xAAAAA000, 0xFFFFF000,
+      0xAAAAA800, 0xFFFFFC00, 0xAAAAAA00, 0xFFFFFF00,
+      0xAAAAAA80, 0xFFFFFFC0, 0xAAAAAAA0, 0xFFFFFFF0,
+      0xAAAAAAA8, 0xFFFFFFFC, 0xAAAAAAAA, 0xFFFFFFFF
+    };
+
+  unsigned int correct_table2[32] =
+    {
+      0x80000000, 0xEAAAAAAA, 0xA0000000, 0xFAAAAAAA,
+      0xA8000000, 0xFEAAAAAA, 0xAA000000, 0xFFAAAAAA,
+      0xAA800000, 0xFFEAAAAA, 0xAAA00000, 0xFFFAAAAA,
+      0xAAA80000, 0xFFFEAAAA, 0xAAAA0000, 0xFFFFAAAA,
+      0xAAAA8000, 0xFFFFEAAA, 0xAAAAA000, 0xFFFFFAAA,
+      0xAAAAA800, 0xFFFFFEAA, 0xAAAAAA00, 0xFFFFFFAA,
+      0xAAAAAA80, 0xFFFFFFEA, 0xAAAAAAA0, 0xFFFFFFFA,
+      0xAAAAAAA8, 0xFFFFFFFE, 0xAAAAAAAA, 0xFFFFFFFF
+    };
+
+  unsigned int tag;
+  unsigned int i;
+
+  /* Reserve all 32 tags.  */
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve();
+      if (tag != i)
+	abort ();
+    }
+
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve();
+      if (tag != MFC_TAG_INVALID)
+	abort ();
+    }
+
+  /* Release only 16 tags with a stride of 2.  */
+  for (i = 0; i < 32; i += 2)
+    {
+      mfc_tag_release (i);
+      if (spu_extract (__mfc_tag_table, 0) != correct_table[i])
+	abort ();
+    }
+
+  /* Release the other 16 tags with a stride of 2.  */
+  for (i = 1; i < 32; i += 2)
+    {
+      mfc_tag_release (i);
+      if (spu_extract (__mfc_tag_table, 0) != correct_table2[i])
+	abort ();
+    }
+}
+
+/* The tag table should be in a pristine mode to run this test.  */
+void
+test_tag_reserve03 (void)
+{
+  unsigned int tag;
+  unsigned int i;
+
+  /* Reserve all 32 tags.  */
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != i)
+	abort ();
+    }
+
+  for (i = 0; i < 32; i++)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != MFC_TAG_INVALID)
+	abort ();
+    }
+
+  /* Release only 16 tags with a stride of 2.  */
+  for (i = 0; i < 32; i += 2)
+    mfc_tag_release (i);
+
+  /* Now let's re-reserve those tags.  */
+  for (i = 0; i < 32; i += 2)
+    {
+      tag = mfc_tag_reserve ();
+      if (tag != i)
+	abort ();
+    }
+
+  /* Release all tags.  */
+  for (i = 0; i < 32; i++)
+    mfc_tag_release (i);
+
+  if (spu_extract (__mfc_tag_table,0) != 0xFFFFFFFF)
+    abort ();
+}
+
+
+void
+test_tag_group_reserve (void)
+{
+  unsigned int tag;
+  unsigned int i;
+  unsigned int copy;
+
+  /* Reserve all tags.  */
+  for (i = 0; i < 32; i++)
+    mfc_tag_reserve();
+
+  /* Release the first 4. */
+  for (i = 0; i < 4; i++)
+    mfc_tag_release (i);
+
+  /* Release tag 5 to 7.  */
+  for (i = 5; i < 8; i++)
+    mfc_tag_release (i);
+
+  /* Release tag 9 to 19.  */
+  for (i = 9; i < 20; i++)
+    mfc_tag_release (i);
+
+  /* Tag table should be 0xF77FF000.  */
+  if (spu_extract (__mfc_tag_table, 0) != 0xF77FF000)
+    abort ();
+
+
+  /* Verify invalid release is detected.  */
+  copy = spu_extract (__mfc_tag_table, 0);
+  if (mfc_multi_tag_release (1, 5) != MFC_TAG_INVALID)
+    abort ();
+  if (copy != spu_extract (__mfc_tag_table, 0))
+    abort ();
+
+
+  /* Reserve multiple tags.  */
+  tag = mfc_multi_tag_reserve (5);
+  if (tag != 9)
+    abort ();
+
+  /* Tag table should be 0xF703F000.  */
+  if (spu_extract (__mfc_tag_table, 0) != 0xF703F000)
+    abort ();
+
+
+  /* Release 5 tags in the group.  */
+  mfc_multi_tag_release (tag, 5);
+
+  /* Tag table should be 0xF77FF000.  */
+  if (spu_extract (__mfc_tag_table, 0) != 0xF77FF000)
+    abort ();
+
+
+  /* This call should not do anything.  */
+  mfc_multi_tag_release (32, 5);
+
+  /* Tag table should be 0xF77FF000.  */
+  if (spu_extract (__mfc_tag_table, 0) != 0xF77FF000)
+    abort ();
+}
+
+
+int
+main (void)
+{
+  test_tag_release01 ();
+  test_tag_release_invalid ();
+  test_tag_group_release_invalid ();
+
+  test_tag_reserve01 ();
+  test_tag_reserve02 ();
+  test_tag_reserve03 ();
+
+  test_tag_group_reserve ();
+
+  return 0;
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/vector-ansi.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/vector-ansi.c
new file mode 100644
index 000000000..3c0861699
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/vector-ansi.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-ansi" } */
+
+/* This is done by spu_internals.h, but we not include it here to keep
+   down the dependencies.  */
+
+#ifndef __VECTOR_KEYWORD_SUPPORTED__
+#define vector __vector
+#endif
+
+/* __vector is expanded unconditionally by the preprocessor.  */
+__vector int vi;
+__vector unsigned char vuc;
+__vector signed char vsc;
+__vector unsigned short vus;
+__vector signed short vss;
+__vector unsigned int vui;
+__vector signed int vsi;
+__vector unsigned long long ull;
+__vector signed long long sll;
+__vector float vf;
+__vector double vd;
+
+/* vector is expanded by the define above, regardless of context.  */
+vector int vi;
+vector unsigned char vuc;
+vector signed char vsc;
+vector unsigned short vus;
+vector signed short vss;
+vector unsigned int vui;
+vector signed int vsi;
+vector unsigned long long ull;
+vector signed long long sll;
+vector float vf;
+vector double vd;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/spu/vector.c b/gcc-4.9/gcc/testsuite/gcc.target/spu/vector.c
new file mode 100644
index 000000000..237f93b7e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/spu/vector.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+#ifndef __VECTOR_KEYWORD_SUPPORTED__
+#error __VECTOR_KEYWORD_SUPPORTED__ is not defined
+#endif
+
+/* __vector is expanded unconditionally.  */
+__vector int vi;
+__vector unsigned char vuc;
+__vector signed char vsc;
+__vector unsigned short vus;
+__vector signed short vss;
+__vector unsigned int vui;
+__vector signed int vsi;
+__vector unsigned long long ull;
+__vector signed long long sll;
+__vector float vf;
+__vector double vd;
+
+/* vector is expanded conditionally, based on the context.  */
+vector int vi;
+vector unsigned char vuc;
+vector signed char vsc;
+vector unsigned short vus;
+vector signed short vss;
+vector unsigned int vui;
+vector signed int vsi;
+vector unsigned long long ull;
+vector signed long long sll;
+vector float vf;
+vector double vd;
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/abi-align-1.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/abi-align-1.c
new file mode 100644
index 000000000..963c2f682
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/abi-align-1.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+
+/* common */
+char c;
+/* arrays must be 8 byte aligned, regardless of size */
+char c_ary[1];
+
+/* data */
+char d = 1;
+char d_ary[1] = {1};
+
+int main ()
+{
+  if (((unsigned long)&c_ary[0] & 7) != 0)
+    return 1;
+  if (((unsigned long)&d_ary[0] & 7) != 0)
+    return 1;
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/bswapl.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/bswapl.c
new file mode 100644
index 000000000..18d6bce7f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/bswapl.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=c64x+" } */
+/* { dg-final { scan-assembler-not "call" } } */
+
+int foo (int x)
+{
+  return __builtin_bswap32 (x);
+}
+
+long long bar (long long x)
+{
+  return __builtin_bswap64 (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtin-math-7.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtin-math-7.c
new file mode 100644
index 000000000..a7deea3e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtin-math-7.c
@@ -0,0 +1,94 @@
+/* Copyright (C) 2009  Free Software Foundation.
+
+   Verify that folding of complex mul and div work correctly.
+   TI C6X specific version, reduced by two tests that fails due to the
+   use of implicit -freciprocal-math.
+
+   Origin: Kaveh R. Ghazi,  August 13, 2009.  */
+
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+/* { dg-add-options ieee } */
+
+extern void link_error(int);
+
+/* Evaluate this expression at compile-time.  */
+#define COMPILETIME_TESTIT(TYPE,X,OP,Y,RES) do { \
+  if ((_Complex TYPE)(X) OP (_Complex TYPE)(Y) != (_Complex TYPE)(RES)) \
+    link_error(__LINE__); \
+} while (0)
+
+/* Use this error function for cases which only evaluate at
+   compile-time when optimizing.  */
+#ifdef __OPTIMIZE__
+# define ERROR_FUNC(X) link_error(X)
+#else
+# define ERROR_FUNC(X) __builtin_abort()
+#endif
+
+/* Evaluate this expression at compile-time using static initializers.  */
+#define STATICINIT_TESTIT(TYPE,X,OP,Y,RES) do { \
+  static const _Complex TYPE foo = (_Complex TYPE)(X) OP (_Complex TYPE)(Y); \
+  if (foo != (_Complex TYPE)(RES)) \
+    ERROR_FUNC (__LINE__); \
+} while (0)
+
+/* Evaluate this expression at runtime.  */
+#define RUNTIME_TESTIT(TYPE,X,OP,Y,RES) do { \
+  volatile _Complex TYPE foo; \
+  foo = (_Complex TYPE)(X); \
+  foo OP##= (_Complex TYPE)(Y); \
+  if (foo != (_Complex TYPE)(RES)) \
+    __builtin_abort(); \
+} while (0)
+
+/* Evaluate this expression at compile-time and runtime.  */
+#define TESTIT(TYPE,X,OP,Y,RES) do { \
+  STATICINIT_TESTIT(TYPE,X,OP,Y,RES); \
+  COMPILETIME_TESTIT(TYPE,X,OP,Y,RES); \
+  RUNTIME_TESTIT(TYPE,X,OP,Y,RES); \
+} while (0)
+
+/* Either the real or imaginary parts should be infinity.  */
+#define TEST_ONE_PART_INF(VAL) do { \
+  static const _Complex double foo = (VAL); \
+  if (! __builtin_isinf(__real foo) && ! __builtin_isinf(__imag foo)) \
+    ERROR_FUNC (__LINE__); \
+  if (! __builtin_isinf(__real (VAL)) && ! __builtin_isinf(__imag (VAL))) \
+    __builtin_abort(); \
+} while (0)
+
+int main()
+{
+  /* Test some regular finite values.  */
+  TESTIT (double, 3.+4.i, *, 2, 6+8i);
+  TESTIT (double, 3.+4.i, /, 2, 1.5+2i);
+  TESTIT (int, 3+4i, *, 2, 6+8i);
+  TESTIT (int, 3+4i, /, 2, 1+2i);
+
+  TESTIT (double, 3.+4.i, *, 2+5i, -14+23i);
+  TESTIT (int, 3+4i, *, 2+5i, -14+23i);
+  TESTIT (int, 30+40i, /, 5i, 8-6i);
+  TESTIT (int, 14+6i, /, 7+3i, 2);
+  TESTIT (int, 8+24i, /, 4+12i, 2);
+
+  /* Test for accuracy.  */
+  COMPILETIME_TESTIT (double,
+		      (1 + __DBL_EPSILON__ + 1i),
+		      *,
+		      (1 - __DBL_EPSILON__ + 1i),
+		      -4.93038065763132378382330353301741393545754021943139377981e-32+2i);
+
+  /* This becomes (NaN + iInf).  */
+#define VAL1 ((_Complex double)__builtin_inf() * 1i)
+
+  /* Test some C99 Annex G special cases.  */
+  TEST_ONE_PART_INF ((VAL1) * (VAL1));
+  TEST_ONE_PART_INF ((_Complex double)1 / (_Complex double)0);
+  TEST_ONE_PART_INF ((VAL1) / (_Complex double)1);
+
+  RUNTIME_TESTIT (double, 1, /, VAL1, 0);
+  STATICINIT_TESTIT (double, 1, /, VAL1, 0);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/arith24.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/arith24.c
new file mode 100644
index 000000000..5e5228446
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/arith24.c
@@ -0,0 +1,83 @@
+/* { dg-require-effective-target ti_c64xp } */
+
+#include <c6x_intrinsics.h>
+
+extern void abort (void);
+
+typedef short  __v2hi __attribute ((vector_size(4)));
+
+int a = 0x5000d000;
+int b = 0xc0002000;
+int c = 0x40009000;
+int d = 0x80000001;
+int e = 0x50002001;
+int f = 0xc0008000;
+
+int a4 = 0x50d03080;
+int b4 = 0xc020f080;
+int c4 = 0xc0202080;
+int d4 = 0x50003080;
+int e4 = 0xc0202180;
+
+int main ()
+{
+  int v;
+  long long vll;
+
+  v = _add2 (a, b);
+  if (v != 0x1000f000)
+    abort ();
+  v = _sub2 (a, b);
+  if (v != 0x9000b000)
+    abort ();
+  v = _sub2 (b, a);
+  if (v != 0x70005000)
+    abort ();
+
+  v = _add4 (a4, b4);
+  if (v != 0x10f02000)
+    abort ();
+  v = _sub4 (a4, b4);
+  if (v != 0x90b04000)
+    abort ();
+  v = _saddu4 (a4, c4);
+  if (v != 0xfff050ff)
+    abort ();
+
+  v = _sadd2 (a, b);
+  if (v != 0x1000f000)
+    abort ();
+  v = _sadd2 (a, c);
+  if (v != 0x7fff8000)
+    abort ();
+
+  v = _ssub2 (a, b);
+  if (v != 0x7fffb000)
+    abort ();
+  v = _ssub2 (b, a);
+  if (v != 0x80005000)
+    abort ();
+
+  vll = _smpy2ll (a, b);
+  if (vll != 0xd8000000f4000000ll)
+    abort ();
+  vll = _smpy2ll (d, d);
+  if (vll != 0x7fffffff00000002ll)
+    abort ();
+
+  v = _avg2 (b, e);
+  if (v != 0x08002001)
+    abort ();
+  v = _avgu4 (d4, e4);
+  if (v != 0x88102980)
+    abort ();
+
+  v = _abs2 (a);
+  if (v != 0x50003000)
+    abort ();
+  v = _abs2 (f);
+  if (v != 0x40007fff)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/c6x-builtins.exp b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/c6x-builtins.exp
new file mode 100644
index 000000000..e3e99acd6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/c6x-builtins.exp
@@ -0,0 +1,29 @@
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `c-torture.exp' driver, looping over
+# optimization options.
+
+load_lib gcc-dg.exp
+
+if { ![istarget tic6x-*-*] } then {
+  return
+}
+
+dg-init
+gcc-dg-runtest [lsort [glob $srcdir/$subdir/*.c]] ""
+dg-finish
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/extclr.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/extclr.c
new file mode 100644
index 000000000..e8e2139dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/extclr.c
@@ -0,0 +1,36 @@
+#include <c6x_intrinsics.h>
+
+extern void abort (void);
+
+#define N 4
+
+int vals[N] = { 0, 0xffffffff, 0x89abcdef, 0xdeadbeef };
+
+int main ()
+{
+  int i;
+  for (i = 0; i < N; i++)
+    {
+      int shf1, shf2;
+      int v = vals[i];
+      unsigned int uv = v;
+
+      for (shf1 = 0; shf1 < 32; shf1++)
+	for (shf2 = 0; shf2 < 32; shf2++)
+	  {
+	    int r = (shf1 << 5) | shf2;
+	    if (shf2 > shf1)
+	      {
+		unsigned int mask = (1u << (shf2 - shf1) << 1) - 1;
+		mask <<= shf1;
+		if (_clrr (v, r) != (v & ~mask))
+		  abort ();
+	      }
+	    if (_extr (v, r) != v << shf1 >> shf2)
+	      abort ();
+	    if (_extru (v, r) != uv << shf1 >> shf2)
+	      abort ();
+	  }
+    }
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/sarith1.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/sarith1.c
new file mode 100644
index 000000000..4ea357003
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/sarith1.c
@@ -0,0 +1,47 @@
+#include <c6x_intrinsics.h>
+
+extern void abort (void);
+
+int a1 = 0x50000000;
+int b1 = 0xc0000000;
+int c1 = 0x40000000;
+int a2 = 0xd0000000;
+int b2 = 0x20000000;
+int c2 = 0x90000000;
+int d = 0x80000000;
+
+int main ()
+{
+  if (_sadd (a1, b1) != 0x10000000)
+    abort ();
+  if (_sadd (a2, b2) != 0xf0000000)
+    abort ();
+  if (_sadd (a1, c1) != 0x7fffffff)
+    abort ();
+  if (_sadd (a2, c2) != 0x80000000)
+    abort ();
+
+  if (_ssub (a1, b1) != 0x7fffffff)
+    abort ();
+  if (_ssub (a2, b2) != 0xb0000000)
+    abort ();
+  if (_ssub (b1, a1) != 0x80000000)
+    abort ();
+  if (_ssub (b2, a2) != 0x50000000)
+    abort ();
+
+  if (_abs (a1) != 0x50000000)
+    abort ();
+  if (_abs (b1) != 0x40000000)
+    abort ();
+  if (_abs (d) != 0x7fffffff)
+    abort ();
+
+  if (_sshl (a1, 1) != 0x7fffffff
+      || _sshl (b2, 1) != 0x40000000
+      || _sshl (a2, 1) != 0xa0000000
+      || _sshl (a2, 4) != 0x80000000)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpy.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpy.c
new file mode 100644
index 000000000..15a993045
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpy.c
@@ -0,0 +1,20 @@
+#include <c6x_intrinsics.h>
+
+extern void abort (void);
+
+int a1 = 0x5000;
+int b1 = 0xc000;
+int a2 = 0xd000;
+int b2 = 0x2000;
+int c = 0x8000;
+int main ()
+{
+  if (_smpy (a1, b1) != 0xd8000000)
+    abort ();
+  if (_smpy (a2, b2) != 0xf4000000)
+    abort ();
+  if (_smpy (c, c) != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpyh.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpyh.c
new file mode 100644
index 000000000..c8864da62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpyh.c
@@ -0,0 +1,19 @@
+#include <c6x_intrinsics.h>
+extern void abort (void);
+
+int a1 = 0x50000000;
+int b1 = 0xc0000000;
+int a2 = 0xd0000000;
+int b2 = 0x20000000;
+int c = 0x80000000;
+int main ()
+{
+  if (_smpyh (a1, b1) != 0xd8000000)
+    abort ();
+  if (_smpyh (a2, b2) != 0xf4000000)
+    abort ();
+  if (_smpyh (c, c) != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpylh.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpylh.c
new file mode 100644
index 000000000..92a50433e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/builtins/smpylh.c
@@ -0,0 +1,26 @@
+#include <c6x_intrinsics.h>
+
+extern void abort (void);
+
+int a1 = 0x5000;
+int b1 = 0xc0000000;
+int a2 = 0xd000;
+int b2 = 0x20000000;
+int c = 0x8000;
+int main ()
+{
+  if (_smpylh (a1, b1) != 0xd8000000)
+    abort ();
+  if (_smpylh (a2, b2) != 0xf4000000)
+    abort ();
+  if (_smpylh (c, 0x80000000) != 0x7fffffff)
+    abort ();
+  if (_smpyhl (b1, a1) != 0xd8000000)
+    abort ();
+  if (_smpyhl (b2, a2) != 0xf4000000)
+    abort ();
+  if (_smpyhl (0x80000000, c) != 0x7fffffff)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/cold-lc.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/cold-lc.c
new file mode 100644
index 000000000..6793f360d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/cold-lc.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-calls" } */
+
+extern void dump_stack (void) __attribute__ ((__cold__));
+struct thread_info {
+    struct task_struct *task;
+};
+extern struct thread_info *current_thread_info (void);
+
+void dump_stack (void)
+{
+    unsigned long stack;
+    show_stack ((current_thread_info ()->task), &stack);
+}
+
+void die (char *str, void *fp, int nr)
+{
+    dump_stack ();
+    while (1);
+}
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/ffsdi.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/ffsdi.c
new file mode 100644
index 000000000..6f61be5ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/ffsdi.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ti_c64xp } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "call" } } */
+
+long long foo (long long x)
+{
+  return __builtin_ffsll (x);
+}
+
+long long bar (long long x)
+{
+  return __builtin_clzll (x);
+}
+
+long long baz (long long x)
+{
+  return __builtin_ctzll (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/ffssi.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/ffssi.c
new file mode 100644
index 000000000..bb8351293
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/ffssi.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=c64x+" } */
+/* { dg-final { scan-assembler-not "call" } } */
+
+int foo (int x)
+{
+  return __builtin_ffsl (x);
+}
+
+int bar (int x)
+{
+  return __builtin_clzl (x);
+}
+
+int baz (int x)
+{
+  return __builtin_ctzl (x);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpcmp-finite.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpcmp-finite.c
new file mode 100644
index 000000000..d7f30165c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpcmp-finite.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ti_c67x } */
+/* { dg-options "-O2 -ffinite-math-only" } */
+/* { dg-final { scan-assembler-not "cmpeq" } } */
+
+double gedf (double x, double y)
+{
+  return x >= y;
+}
+
+double ledf (double x, double y)
+{
+  return x <= y;
+}
+
+float gesf (float x, float y)
+{
+  return x >= y;
+}
+
+float lesf (float x, float y)
+{
+  return x <= y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpcmp.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpcmp.c
new file mode 100644
index 000000000..25eaff410
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpcmp.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ti_c67x } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-times "cmpeq.p" 4 } } */
+
+double gedf (double x, double y)
+{
+  return x >= y;
+}
+
+double ledf (double x, double y)
+{
+  return x <= y;
+}
+
+float gesf (float x, float y)
+{
+  return x >= y;
+}
+
+float lesf (float x, float y)
+{
+  return x <= y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpdiv-lib.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpdiv-lib.c
new file mode 100644
index 000000000..b138865a2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpdiv-lib.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ti_c67x } */
+/* { dg-options "-O2 -fno-reciprocal-math" } */
+/* { dg-final { scan-assembler-not "rcpdp" } } */
+/* { dg-final { scan-assembler-not "rcpsp" } } */
+
+double f (double x, double y)
+{
+  return x / y;
+}
+
+float g (float x, float y)
+{
+  return x / y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpdiv.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpdiv.c
new file mode 100644
index 000000000..e547fb457
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/fpdiv.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ti_c67x } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "rcpdp" } } */
+/* { dg-final { scan-assembler "rcpsp" } } */
+
+double f (double x, double y)
+{
+  return x / y;
+}
+
+float g (float x, float y)
+{
+  return x / y;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/longcalls.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/longcalls.c
new file mode 100644
index 000000000..273433cee
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/longcalls.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlong-calls" } */
+/* { dg-final { scan-assembler-times "\\tcall\[p\]*\[\\t ]*.s" 3 } } */
+/* { dg-final { scan-assembler "call\[p\]*\[\\t ]*.s.\[\\t ]*.f" } } */
+/* { dg-final { scan-assembler-not "call\[p\]*\[\\t ]*.s.\[\\t ]*.g" } } */
+/* { dg-final { scan-assembler-not "call\[p\]*\[\\t ]*.s.\[\\t ]*.h" } } */
+
+int x;
+
+static __attribute__ ((noinline)) void f ()
+{
+  x = 5;
+}
+
+extern void g ();
+
+static __attribute__ ((noinline)) __attribute__((section(".init.text"))) void h ()
+{
+  x = 5;
+}
+
+int bar ()
+{
+  f ();
+  g ();
+  h ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/rotdi16-scan.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/rotdi16-scan.c
new file mode 100644
index 000000000..4d7816c15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/rotdi16-scan.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target ti_c64xp } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "dpackx" } } */
+
+#include <stdlib.h>
+
+unsigned long long z = 0x012389ab4567cdefull;
+
+int main ()
+{
+  unsigned long long z2 = (z << 48) | (z >> 16);
+  if (z2 != 0xcdef012389ab4567ull)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/rotdi16.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/rotdi16.c
new file mode 100644
index 000000000..33b052ad4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/rotdi16.c
@@ -0,0 +1,14 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include <stdlib.h>
+
+unsigned long long z = 0x012389ab4567cdefull;
+
+int main ()
+{
+  unsigned long long z2 = (z << 48) | (z >> 16);
+  if (z2 != 0xcdef012389ab4567ull)
+    abort ();
+  exit (0);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/tic6x.exp b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/tic6x.exp
new file mode 100644
index 000000000..52e5b83fb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/tic6x.exp
@@ -0,0 +1,62 @@
+# Copyright (C) 2010-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+if ![istarget tic6x-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Like dg-options, but treats certain C6X-specific options specially:
+#
+#    -march=*
+#	Select the target architecture. Skip the test if the multilib
+#	flags force a different arch.
+proc dg-c6x-options {args} {
+    upvar dg-extra-tool-flags extra_tool_flags
+    upvar dg-do-what do_what
+
+    set multilib_arch ""
+    set arch ""
+
+    foreach flag [target_info multilib_flags] {
+	regexp "^-march=(.*)" $flag dummy multilib_arch
+    }
+
+    set flags [lindex $args 1]
+
+    foreach flag $flags {
+	regexp "^-march=(.*)" $flag dummy arch
+    }
+
+    if {$multilib_arch == "" || $multilib_cpu == $arch} {
+	set extra_tool_flags $flags
+    } else {
+	set do_what [list [lindex $do_what 0] "N" "P"]
+    }
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]]	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/tic6x/weak-call.c b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/weak-call.c
new file mode 100644
index 000000000..9be930480
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/tic6x/weak-call.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "call\[\\t ]*.s.\[\\t ]*.f" } } */
+/* { dg-final { scan-assembler-not "call\[\\t ]*.s.\[\\t ]*.g" } } */
+
+extern void f () __attribute__ ((weak));
+extern void g () __attribute__ ((weak)) __attribute__ ((noinline));
+
+void g ()
+{
+}
+
+int main ()
+{
+  f ();
+  g ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/vax/pr56875.c b/gcc-4.9/gcc/testsuite/gcc.target/vax/pr56875.c
new file mode 100644
index 000000000..f409afe88
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/vax/pr56875.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O0" } */
+/* { dg-final { scan-assembler     "ashq .*,\\\$0xffffffffffffffff," } } */
+/* { dg-final { scan-assembler-not "ashq .*,\\\$-1," } } */
+
+void
+a (void)
+{
+	unsigned long i = 1;
+	unsigned long long v;
+
+	v = ~ (unsigned long long) 0 << i;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/vax/vax.exp b/gcc-4.9/gcc/testsuite/gcc.target/vax/vax.exp
new file mode 100644
index 000000000..9a6148498
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/vax/vax.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2013-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a VAX target.
+if ![istarget vax-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/README.gcc b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/README.gcc
new file mode 100644
index 000000000..e668a4dd8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/README.gcc
@@ -0,0 +1,25 @@
+This contains a testsuite for the AMD64 psABI.
+The ABI document is at http://www.x86-64.org/documentation/abi.pdf .
+The content of this directory in the GCC tree is just a (partial) copy of the
+ABI testsuite at cvs.x86-64.org.
+
+See http://www.x86-64.org/cvsaccess for accessing the anonymous CVS server.
+The module 'abitest' contains the master copy of this directory.
+
+The whole testsuite is licensed under GPL v2.
+
+Be aware that some of the test_*.c files here are generated, with the
+generators only being in the master copy of the testsuite.
+
+To change anything, please contact discuss@x86-64.org or the current
+maintainer of the testuite directly.
+
+The current maintainer is:
+  matz@suse.de
+
+
+Copyright (C) 2005-2014 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp
new file mode 100644
index 000000000..5ecfe4be8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/abi-x86_64.exp
@@ -0,0 +1,48 @@
+# Copyright (C) 2005-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# The x86-64 ABI testsuite needs one additional assembler file for most
+# testcases.  For simplicity we will just link it into each test.
+
+load_lib c-torture.exp
+load_lib target-supports.exp
+load_lib torture-options.exp
+
+if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
+     || ![is-effective-target lp64] } then {
+  return
+}
+
+
+torture-init
+set-torture-options $C_TORTURE_OPTIONS
+set additional_flags "-W -Wall -Wno-abi"
+
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	if { ([istarget *-*-darwin*]) } then {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support-darwin.s] \
+				    $additional_flags
+	} else {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support.S] \
+				    $additional_flags
+	}
+    }
+}
+
+torture-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/args.h b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/args.h
new file mode 100644
index 000000000..99d7b76f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/args.h
@@ -0,0 +1,186 @@
+#ifndef INCLUDED_ARGS_H
+#define INCLUDED_ARGS_H
+
+#include <string.h>
+
+/* This defines the calling sequences for integers and floats.  */
+#define I0 rdi
+#define I1 rsi
+#define I2 rdx
+#define I3 rcx
+#define I4 r8
+#define I5 r9
+#define F0 xmm0
+#define F1 xmm1
+#define F2 xmm2
+#define F3 xmm3
+#define F4 xmm4
+#define F5 xmm5
+#define F6 xmm6
+#define F7 xmm7
+
+typedef union {
+  float _float[4];
+  double _double[2];
+  long _long[2];
+  int _int[4];
+  unsigned long _ulong[2];
+#ifdef CHECK_M64_M128
+  __m64 _m64[2];
+  __m128 _m128[1];
+#endif
+} XMM_T;
+
+typedef union {
+  float _float;
+  double _double;
+  ldouble _ldouble;
+  ulong _ulong[2];
+} X87_T;
+extern void (*callthis)(void);
+extern unsigned long rax,rbx,rcx,rdx,rsi,rdi,rsp,rbp,r8,r9,r10,r11,r12,r13,r14,r15;
+XMM_T xmm_regs[16];
+X87_T x87_regs[8];
+extern volatile unsigned long volatile_var;
+extern void snapshot (void);
+extern void snapshot_ret (void);
+#define WRAP_CALL(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot)
+#define WRAP_RET(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot_ret)
+
+/* Clear all integer registers.  */
+#define clear_int_hardware_registers \
+  asm __volatile__ ("xor %%rax, %%rax\n\t" \
+		    "xor %%rbx, %%rbx\n\t" \
+		    "xor %%rcx, %%rcx\n\t" \
+		    "xor %%rdx, %%rdx\n\t" \
+		    "xor %%rsi, %%rsi\n\t" \
+		    "xor %%rdi, %%rdi\n\t" \
+		    "xor %%r8, %%r8\n\t" \
+		    "xor %%r9, %%r9\n\t" \
+		    "xor %%r10, %%r10\n\t" \
+		    "xor %%r11, %%r11\n\t" \
+		    "xor %%r12, %%r12\n\t" \
+		    "xor %%r13, %%r13\n\t" \
+		    "xor %%r14, %%r14\n\t" \
+		    "xor %%r15, %%r15\n\t" \
+		    ::: "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "r8", \
+		    "r9", "r10", "r11", "r12", "r13", "r14", "r15");
+
+/* This is the list of registers available for passing arguments. Not all of
+   these are used or even really available.  */
+struct IntegerRegisters
+{
+  unsigned long rax, rbx, rcx, rdx, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
+};
+struct FloatRegisters
+{
+  double mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7;
+  ldouble st0, st1, st2, st3, st4, st5, st6, st7;
+  XMM_T xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9,
+        xmm10, xmm11, xmm12, xmm13, xmm14, xmm15;
+};
+
+/* Implemented in scalarargs.c  */
+extern struct IntegerRegisters iregs;
+extern struct FloatRegisters fregs;
+extern unsigned int num_iregs, num_fregs;
+
+#define check_int_arguments do { \
+  assert (num_iregs <= 0 || iregs.I0 == I0); \
+  assert (num_iregs <= 1 || iregs.I1 == I1); \
+  assert (num_iregs <= 2 || iregs.I2 == I2); \
+  assert (num_iregs <= 3 || iregs.I3 == I3); \
+  assert (num_iregs <= 4 || iregs.I4 == I4); \
+  assert (num_iregs <= 5 || iregs.I5 == I5); \
+  } while (0)
+
+#define check_char_arguments check_int_arguments
+#define check_short_arguments check_int_arguments
+#define check_long_arguments check_int_arguments
+
+/* Clear register struct.  */
+#define clear_struct_registers \
+  rax = rbx = rcx = rdx = rdi = rsi = rbp = rsp \
+    = r8 = r9 = r10 = r11 = r12 = r13 = r14 = r15 = 0; \
+  memset (&iregs, 0, sizeof (iregs)); \
+  memset (&fregs, 0, sizeof (fregs)); \
+  memset (xmm_regs, 0, sizeof (xmm_regs)); \
+  memset (x87_regs, 0, sizeof (x87_regs));
+
+/* Clear both hardware and register structs for integers.  */
+#define clear_int_registers \
+  clear_struct_registers \
+  clear_int_hardware_registers
+
+/* TODO: Do the checking.  */
+#define check_f_arguments(T) do { \
+  assert (num_fregs <= 0 || fregs.xmm0._ ## T [0] == xmm_regs[0]._ ## T [0]); \
+  assert (num_fregs <= 1 || fregs.xmm1._ ## T [0] == xmm_regs[1]._ ## T [0]); \
+  assert (num_fregs <= 2 || fregs.xmm2._ ## T [0] == xmm_regs[2]._ ## T [0]); \
+  assert (num_fregs <= 3 || fregs.xmm3._ ## T [0] == xmm_regs[3]._ ## T [0]); \
+  assert (num_fregs <= 4 || fregs.xmm4._ ## T [0] == xmm_regs[4]._ ## T [0]); \
+  assert (num_fregs <= 5 || fregs.xmm5._ ## T [0] == xmm_regs[5]._ ## T [0]); \
+  assert (num_fregs <= 6 || fregs.xmm6._ ## T [0] == xmm_regs[6]._ ## T [0]); \
+  assert (num_fregs <= 7 || fregs.xmm7._ ## T [0] == xmm_regs[7]._ ## T [0]); \
+  } while (0)
+
+#define check_float_arguments check_f_arguments(float)
+#define check_double_arguments check_f_arguments(double)
+
+#define check_vector_arguments(T,O) do { \
+  assert (num_fregs <= 0 \
+	  || memcmp (((char *) &fregs.xmm0) + (O), \
+		     &xmm_regs[0], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 1 \
+	  || memcmp (((char *) &fregs.xmm1) + (O), \
+		     &xmm_regs[1], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 2 \
+	  || memcmp (((char *) &fregs.xmm2) + (O), \
+		     &xmm_regs[2], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 3 \
+	  || memcmp (((char *) &fregs.xmm3) + (O), \
+		     &xmm_regs[3], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 4 \
+	  || memcmp (((char *) &fregs.xmm4) + (O), \
+		     &xmm_regs[4], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 5 \
+	  || memcmp (((char *) &fregs.xmm5) + (O), \
+		     &xmm_regs[5], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 6 \
+	  || memcmp (((char *) &fregs.xmm6) + (O), \
+		     &xmm_regs[6], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 7 \
+	  || memcmp (((char *) &fregs.xmm7) + (O), \
+		     &xmm_regs[7], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  } while (0)
+
+#define check_m64_arguments check_vector_arguments(m64, 0)
+#define check_m128_arguments check_vector_arguments(m128, 0)
+
+/* ldoubles are not passed in registers */
+#define check_ldouble_arguments
+
+/* TODO: Do the clearing.  */
+#define clear_float_hardware_registers
+#define clear_x87_hardware_registers
+
+#define clear_float_registers \
+  clear_struct_registers \
+  clear_float_hardware_registers
+
+#define clear_x87_registers \
+  clear_struct_registers \
+  clear_x87_hardware_registers
+
+
+#endif /* INCLUDED_ARGS_H  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s
new file mode 100644
index 000000000..b3b88466a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/asm-support-darwin.s
@@ -0,0 +1,77 @@
+	.file	"snapshot.S"
+	.text
+	.p2align 4,,15
+.globl _snapshot
+_snapshot:
+.LFB3:
+	movq	%rax, _rax(%rip)
+	movq	%rbx, _rbx(%rip)
+	movq	%rcx, _rcx(%rip)
+	movq	%rdx, _rdx(%rip)
+	movq	%rdi, _rdi(%rip)
+	movq	%rsi, _rsi(%rip)
+	movq	%rbp, _rbp(%rip)
+	movq	%rsp, _rsp(%rip)
+	movq	%r8, _r8(%rip)
+	movq	%r9, _r9(%rip)
+	movq	%r10, _r10(%rip)
+	movq	%r11, _r11(%rip)
+	movq	%r12, _r12(%rip)
+	movq	%r13, _r13(%rip)
+	movq	%r14, _r14(%rip)
+	movq	%r15, _r15(%rip)
+	movdqu	%xmm0, _xmm_regs+0(%rip)
+	movdqu	%xmm1, _xmm_regs+16(%rip)
+	movdqu	%xmm2, _xmm_regs+32(%rip)
+	movdqu	%xmm3, _xmm_regs+48(%rip)
+	movdqu	%xmm4, _xmm_regs+64(%rip)
+	movdqu	%xmm5, _xmm_regs+80(%rip)
+	movdqu	%xmm6, _xmm_regs+96(%rip)
+	movdqu	%xmm7, _xmm_regs+112(%rip)
+	movdqu	%xmm8, _xmm_regs+128(%rip)
+	movdqu	%xmm9, _xmm_regs+144(%rip)
+	movdqu	%xmm10, _xmm_regs+160(%rip)
+	movdqu	%xmm11, _xmm_regs+176(%rip)
+	movdqu	%xmm12, _xmm_regs+192(%rip)
+	movdqu	%xmm13, _xmm_regs+208(%rip)
+	movdqu	%xmm14, _xmm_regs+224(%rip)
+	movdqu	%xmm15, _xmm_regs+240(%rip)
+	jmp	*_callthis(%rip)
+.LFE3:
+	.p2align 4,,15
+.globl _snapshot_ret
+_snapshot_ret:
+	movq	%rdi, _rdi(%rip)
+	subq	$8, %rsp
+	call	*_callthis(%rip)
+	addq	$8, %rsp
+	movq	%rax, _rax(%rip)
+	movq	%rdx, _rdx(%rip)
+	movdqu	%xmm0, _xmm_regs+0(%rip)
+	movdqu	%xmm1, _xmm_regs+16(%rip)
+	fstpt	_x87_regs(%rip)
+	fstpt	_x87_regs+16(%rip)
+	fldt	_x87_regs+16(%rip)
+	fldt	_x87_regs(%rip)
+	ret
+
+	.comm	_callthis,8
+	.comm	_rax,8
+	.comm	_rbx,8
+	.comm	_rcx,8
+	.comm	_rdx,8
+	.comm	_rsi,8
+	.comm	_rdi,8
+	.comm	_rsp,8
+	.comm	_rbp,8
+	.comm	_r8,8
+	.comm	_r9,8
+	.comm	_r10,8
+	.comm	_r11,8
+	.comm	_r12,8
+	.comm	_r13,8
+	.comm	_r14,8
+	.comm	_r15,8
+	.comm	_xmm_regs,256
+	.comm	_x87_regs,128
+	.comm   _volatile_var,8
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S
new file mode 100644
index 000000000..8e0bffe8b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/asm-support.S
@@ -0,0 +1,85 @@
+	.file	"snapshot.S"
+#ifdef __AVX__
+	.sse_check none
+#endif
+	.text
+	.p2align 4,,15
+.globl snapshot
+	.type	snapshot, @function
+snapshot:
+.LFB3:
+	movq	%rax, rax(%rip)
+	movq	%rbx, rbx(%rip)
+	movq	%rcx, rcx(%rip)
+	movq	%rdx, rdx(%rip)
+	movq	%rdi, rdi(%rip)
+	movq	%rsi, rsi(%rip)
+	movq	%rbp, rbp(%rip)
+	movq	%rsp, rsp(%rip)
+	movq	%r8, r8(%rip)
+	movq	%r9, r9(%rip)
+	movq	%r10, r10(%rip)
+	movq	%r11, r11(%rip)
+	movq	%r12, r12(%rip)
+	movq	%r13, r13(%rip)
+	movq	%r14, r14(%rip)
+	movq	%r15, r15(%rip)
+	movdqu	%xmm0, xmm_regs+0(%rip)
+	movdqu	%xmm1, xmm_regs+16(%rip)
+	movdqu	%xmm2, xmm_regs+32(%rip)
+	movdqu	%xmm3, xmm_regs+48(%rip)
+	movdqu	%xmm4, xmm_regs+64(%rip)
+	movdqu	%xmm5, xmm_regs+80(%rip)
+	movdqu	%xmm6, xmm_regs+96(%rip)
+	movdqu	%xmm7, xmm_regs+112(%rip)
+	movdqu	%xmm8, xmm_regs+128(%rip)
+	movdqu	%xmm9, xmm_regs+144(%rip)
+	movdqu	%xmm10, xmm_regs+160(%rip)
+	movdqu	%xmm11, xmm_regs+176(%rip)
+	movdqu	%xmm12, xmm_regs+192(%rip)
+	movdqu	%xmm13, xmm_regs+208(%rip)
+	movdqu	%xmm14, xmm_regs+224(%rip)
+	movdqu	%xmm15, xmm_regs+240(%rip)
+	jmp	*callthis(%rip)
+.LFE3:
+	.size	snapshot, .-snapshot
+
+	.p2align 4,,15
+.globl snapshot_ret
+	.type	snapshot_ret, @function
+snapshot_ret:
+	movq	%rdi, rdi(%rip)
+	subq	$8, %rsp
+	call	*callthis(%rip)
+	addq	$8, %rsp
+	movq	%rax, rax(%rip)
+	movq	%rdx, rdx(%rip)
+	movdqu	%xmm0, xmm_regs+0(%rip)
+	movdqu	%xmm1, xmm_regs+16(%rip)
+	fstpt	x87_regs(%rip)
+	fstpt	x87_regs+16(%rip)
+	fldt	x87_regs+16(%rip)
+	fldt	x87_regs(%rip)
+	ret
+	.size	snapshot_ret, .-snapshot_ret
+
+	.comm	callthis,8,8
+	.comm	rax,8,8
+	.comm	rbx,8,8
+	.comm	rcx,8,8
+	.comm	rdx,8,8
+	.comm	rsi,8,8
+	.comm	rdi,8,8
+	.comm	rsp,8,8
+	.comm	rbp,8,8
+	.comm	r8,8,8
+	.comm	r9,8,8
+	.comm	r10,8,8
+	.comm	r11,8,8
+	.comm	r12,8,8
+	.comm	r13,8,8
+	.comm	r14,8,8
+	.comm	r15,8,8
+	.comm	xmm_regs,256,32
+	.comm	x87_regs,128,32
+	.comm   volatile_var,8,8
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp
new file mode 100644
index 000000000..d6fc1874f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/abi-avx.exp
@@ -0,0 +1,61 @@
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# The x86-64 AVX ABI testsuite needs one additional assembler file for most
+# testcases.  For simplicity we will just link it into each test.
+
+load_lib c-torture.exp
+load_lib target-supports.exp
+load_lib torture-options.exp
+
+if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
+     || ![is-effective-target lp64]
+     || ![is-effective-target avx] } then {
+  return
+}
+
+
+# If the linker used understands -M <mapfile>, pass it to clear hardware
+# capabilities set by the Sun assembler.
+set flags ""
+set clearcap_ldflags "-Wl,-M,$srcdir/gcc.target/i386/clearcap.map"
+
+if [check_no_compiler_messages mapfile executable {
+	int main (void) { return 0; }
+  } $clearcap_ldflags ] {
+  set flags $clearcap_ldflags
+}
+
+torture-init
+set-torture-options $C_TORTURE_OPTIONS
+set additional_flags "-W -Wall -mavx $flags"
+
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	if { ([istarget *-*-darwin*]) } then {
+	    # FIXME: Darwin isn't tested.
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support-darwin.s] \
+				    $additional_flags
+	} else {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support.S] \
+				    $additional_flags
+	}
+    }
+}
+
+torture-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/args.h b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/args.h
new file mode 100644
index 000000000..5fa4a5e6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/args.h
@@ -0,0 +1,180 @@
+#ifndef INCLUDED_ARGS_H
+#define INCLUDED_ARGS_H
+
+#include <immintrin.h>
+#include <string.h>
+
+/* Assertion macro.  */
+#define assert(test) if (!(test)) abort()
+
+#ifdef __GNUC__
+#define ATTRIBUTE_UNUSED __attribute__((__unused__))
+#else
+#define ATTRIBUTE_UNUSED
+#endif
+
+/* This defines the calling sequences for integers and floats.  */
+#define I0 rdi
+#define I1 rsi
+#define I2 rdx
+#define I3 rcx
+#define I4 r8
+#define I5 r9
+#define F0 ymm0
+#define F1 ymm1
+#define F2 ymm2
+#define F3 ymm3
+#define F4 ymm4
+#define F5 ymm5
+#define F6 ymm6
+#define F7 ymm7
+
+typedef union {
+  float _float[8];
+  double _double[4];
+  long _long[4];
+  int _int[8];
+  unsigned long _ulong[4];
+  __m64 _m64[4];
+  __m128 _m128[2];
+  __m256 _m256[1];
+} YMM_T;
+
+typedef union {
+  float _float;
+  double _double;
+  long double _ldouble;
+  unsigned long _ulong[2];
+} X87_T;
+extern void (*callthis)(void);
+extern unsigned long rax,rbx,rcx,rdx,rsi,rdi,rsp,rbp,r8,r9,r10,r11,r12,r13,r14,r15;
+YMM_T ymm_regs[16];
+X87_T x87_regs[8];
+extern volatile unsigned long volatile_var;
+extern void snapshot (void);
+extern void snapshot_ret (void);
+#define WRAP_CALL(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot)
+#define WRAP_RET(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot_ret)
+
+/* Clear all integer registers.  */
+#define clear_int_hardware_registers \
+  asm __volatile__ ("xor %%rax, %%rax\n\t" \
+		    "xor %%rbx, %%rbx\n\t" \
+		    "xor %%rcx, %%rcx\n\t" \
+		    "xor %%rdx, %%rdx\n\t" \
+		    "xor %%rsi, %%rsi\n\t" \
+		    "xor %%rdi, %%rdi\n\t" \
+		    "xor %%r8, %%r8\n\t" \
+		    "xor %%r9, %%r9\n\t" \
+		    "xor %%r10, %%r10\n\t" \
+		    "xor %%r11, %%r11\n\t" \
+		    "xor %%r12, %%r12\n\t" \
+		    "xor %%r13, %%r13\n\t" \
+		    "xor %%r14, %%r14\n\t" \
+		    "xor %%r15, %%r15\n\t" \
+		    ::: "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "r8", \
+		    "r9", "r10", "r11", "r12", "r13", "r14", "r15");
+
+/* This is the list of registers available for passing arguments. Not all of
+   these are used or even really available.  */
+struct IntegerRegisters
+{
+  unsigned long rax, rbx, rcx, rdx, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
+};
+struct FloatRegisters
+{
+  double mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7;
+  long double st0, st1, st2, st3, st4, st5, st6, st7;
+  YMM_T ymm0, ymm1, ymm2, ymm3, ymm4, ymm5, ymm6, ymm7, ymm8, ymm9,
+        ymm10, ymm11, ymm12, ymm13, ymm14, ymm15;
+};
+
+/* Implemented in scalarargs.c  */
+extern struct IntegerRegisters iregs;
+extern struct FloatRegisters fregs;
+extern unsigned int num_iregs, num_fregs;
+
+#define check_int_arguments do { \
+  assert (num_iregs <= 0 || iregs.I0 == I0); \
+  assert (num_iregs <= 1 || iregs.I1 == I1); \
+  assert (num_iregs <= 2 || iregs.I2 == I2); \
+  assert (num_iregs <= 3 || iregs.I3 == I3); \
+  assert (num_iregs <= 4 || iregs.I4 == I4); \
+  assert (num_iregs <= 5 || iregs.I5 == I5); \
+  } while (0)
+
+#define check_char_arguments check_int_arguments
+#define check_short_arguments check_int_arguments
+#define check_long_arguments check_int_arguments
+
+/* Clear register struct.  */
+#define clear_struct_registers \
+  rax = rbx = rcx = rdx = rdi = rsi = rbp = rsp \
+    = r8 = r9 = r10 = r11 = r12 = r13 = r14 = r15 = 0; \
+  memset (&iregs, 0, sizeof (iregs)); \
+  memset (&fregs, 0, sizeof (fregs)); \
+  memset (ymm_regs, 0, sizeof (ymm_regs)); \
+  memset (x87_regs, 0, sizeof (x87_regs));
+
+/* Clear both hardware and register structs for integers.  */
+#define clear_int_registers \
+  clear_struct_registers \
+  clear_int_hardware_registers
+
+/* TODO: Do the checking.  */
+#define check_f_arguments(T) do { \
+  assert (num_fregs <= 0 || fregs.ymm0._ ## T [0] == ymm_regs[0]._ ## T [0]); \
+  assert (num_fregs <= 1 || fregs.ymm1._ ## T [0] == ymm_regs[1]._ ## T [0]); \
+  assert (num_fregs <= 2 || fregs.ymm2._ ## T [0] == ymm_regs[2]._ ## T [0]); \
+  assert (num_fregs <= 3 || fregs.ymm3._ ## T [0] == ymm_regs[3]._ ## T [0]); \
+  assert (num_fregs <= 4 || fregs.ymm4._ ## T [0] == ymm_regs[4]._ ## T [0]); \
+  assert (num_fregs <= 5 || fregs.ymm5._ ## T [0] == ymm_regs[5]._ ## T [0]); \
+  assert (num_fregs <= 6 || fregs.ymm6._ ## T [0] == ymm_regs[6]._ ## T [0]); \
+  assert (num_fregs <= 7 || fregs.ymm7._ ## T [0] == ymm_regs[7]._ ## T [0]); \
+  } while (0)
+
+#define check_float_arguments check_f_arguments(float)
+#define check_double_arguments check_f_arguments(double)
+
+#define check_vector_arguments(T,O) do { \
+  assert (num_fregs <= 0 \
+	  || memcmp (((char *) &fregs.ymm0) + (O), \
+		     &ymm_regs[0], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 1 \
+	  || memcmp (((char *) &fregs.ymm1) + (O), \
+		     &ymm_regs[1], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 2 \
+	  || memcmp (((char *) &fregs.ymm2) + (O), \
+		     &ymm_regs[2], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 3 \
+	  || memcmp (((char *) &fregs.ymm3) + (O), \
+		     &ymm_regs[3], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 4 \
+	  || memcmp (((char *) &fregs.ymm4) + (O), \
+		     &ymm_regs[4], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 5 \
+	  || memcmp (((char *) &fregs.ymm5) + (O), \
+		     &ymm_regs[5], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 6 \
+	  || memcmp (((char *) &fregs.ymm6) + (O), \
+		     &ymm_regs[6], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 7 \
+	  || memcmp (((char *) &fregs.ymm7) + (O), \
+		     &ymm_regs[7], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  } while (0)
+
+#define check_m64_arguments check_vector_arguments(m64, 0)
+#define check_m128_arguments check_vector_arguments(m128, 0)
+#define check_m256_arguments check_vector_arguments(m256, 0)
+
+#endif /* INCLUDED_ARGS_H  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S
new file mode 100644
index 000000000..d248ef02e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/asm-support.S
@@ -0,0 +1,82 @@
+	.file	"snapshot.S"
+	.text
+	.p2align 4,,15
+.globl snapshot
+	.type	snapshot, @function
+snapshot:
+.LFB3:
+	movq	%rax, rax(%rip)
+	movq	%rbx, rbx(%rip)
+	movq	%rcx, rcx(%rip)
+	movq	%rdx, rdx(%rip)
+	movq	%rdi, rdi(%rip)
+	movq	%rsi, rsi(%rip)
+	movq	%rbp, rbp(%rip)
+	movq	%rsp, rsp(%rip)
+	movq	%r8, r8(%rip)
+	movq	%r9, r9(%rip)
+	movq	%r10, r10(%rip)
+	movq	%r11, r11(%rip)
+	movq	%r12, r12(%rip)
+	movq	%r13, r13(%rip)
+	movq	%r14, r14(%rip)
+	movq	%r15, r15(%rip)
+	vmovdqu	%ymm0, ymm_regs+0(%rip)
+	vmovdqu	%ymm1, ymm_regs+32(%rip)
+	vmovdqu	%ymm2, ymm_regs+64(%rip)
+	vmovdqu	%ymm3, ymm_regs+96(%rip)
+	vmovdqu	%ymm4, ymm_regs+128(%rip)
+	vmovdqu	%ymm5, ymm_regs+160(%rip)
+	vmovdqu	%ymm6, ymm_regs+192(%rip)
+	vmovdqu	%ymm7, ymm_regs+224(%rip)
+	vmovdqu	%ymm8, ymm_regs+256(%rip)
+	vmovdqu	%ymm9, ymm_regs+288(%rip)
+	vmovdqu	%ymm10, ymm_regs+320(%rip)
+	vmovdqu	%ymm11, ymm_regs+352(%rip)
+	vmovdqu	%ymm12, ymm_regs+384(%rip)
+	vmovdqu	%ymm13, ymm_regs+416(%rip)
+	vmovdqu	%ymm14, ymm_regs+448(%rip)
+	vmovdqu	%ymm15, ymm_regs+480(%rip)
+	jmp	*callthis(%rip)
+.LFE3:
+	.size	snapshot, .-snapshot
+
+	.p2align 4,,15
+.globl snapshot_ret
+	.type	snapshot_ret, @function
+snapshot_ret:
+	movq	%rdi, rdi(%rip)
+	subq	$8, %rsp
+	call	*callthis(%rip)
+	addq	$8, %rsp
+	movq	%rax, rax(%rip)
+	movq	%rdx, rdx(%rip)
+	vmovdqu	%ymm0, ymm_regs+0(%rip)
+	vmovdqu	%ymm1, ymm_regs+32(%rip)
+	fstpt	x87_regs(%rip)
+	fstpt	x87_regs+16(%rip)
+	fldt	x87_regs+16(%rip)
+	fldt	x87_regs(%rip)
+	ret
+	.size	snapshot_ret, .-snapshot_ret
+
+	.comm	callthis,8,8
+	.comm	rax,8,8
+	.comm	rbx,8,8
+	.comm	rcx,8,8
+	.comm	rdx,8,8
+	.comm	rsi,8,8
+	.comm	rdi,8,8
+	.comm	rsp,8,8
+	.comm	rbp,8,8
+	.comm	r8,8,8
+	.comm	r9,8,8
+	.comm	r10,8,8
+	.comm	r11,8,8
+	.comm	r12,8,8
+	.comm	r13,8,8
+	.comm	r14,8,8
+	.comm	r15,8,8
+	.comm	ymm_regs,512,32
+	.comm	x87_regs,128,32
+	.comm   volatile_var,8,8
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h
new file mode 100644
index 000000000..e66a27e9a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/avx-check.h
@@ -0,0 +1,28 @@
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void avx_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+ 
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+  /* Run AVX test only if host has AVX support.  */
+  if ((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE))
+    {
+      avx_test ();
+#ifdef DEBUG
+      printf ("PASSED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_m256_returning.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_m256_returning.c
new file mode 100644
index 000000000..072d83962
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_m256_returning.c
@@ -0,0 +1,32 @@
+#include <stdio.h>
+#include "avx-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+__m256
+fun_test_returning___m256 (void)
+{
+  volatile_var++;
+  return (__m256){73,0,0,0,0,0,0,0};
+}
+
+__m256 test_256;
+
+static void
+avx_test (void)
+{
+  unsigned failed = 0;
+  YMM_T ymmt1, ymmt2;
+
+  clear_struct_registers;
+  test_256 = (__m256){73,0,0,0,0,0,0,0};
+  ymmt1._m256[0] = test_256;
+  ymmt2._m256[0] = WRAP_RET (fun_test_returning___m256)();
+  if (memcmp (&ymmt1, &ymmt2, sizeof (ymmt2)) != 0)
+    printf ("fail m256\n"), failed++;
+  if (failed)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_m256.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_m256.c
new file mode 100644
index 000000000..ffc3ec36b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_m256.c
@@ -0,0 +1,168 @@
+#include <stdio.h>
+#include "avx-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct 
+{
+  YMM_T i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values;
+
+char *pass;
+int failed = 0;
+
+#undef assert
+#define assert(c) do { \
+  if (!(c)) {failed++; printf ("failed %s\n", pass); } \
+} while (0)
+
+#define compare(X1,X2,T) do { \
+  assert (memcmp (&X1, &X2, sizeof (T)) == 0); \
+} while (0)
+
+fun_check_passing_m256_8_values (__m256 i0 ATTRIBUTE_UNUSED, __m256 i1 ATTRIBUTE_UNUSED, __m256 i2 ATTRIBUTE_UNUSED, __m256 i3 ATTRIBUTE_UNUSED, __m256 i4 ATTRIBUTE_UNUSED, __m256 i5 ATTRIBUTE_UNUSED, __m256 i6 ATTRIBUTE_UNUSED, __m256 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m256);
+  compare (values.i1, i1, __m256);
+  compare (values.i2, i2, __m256);
+  compare (values.i3, i3, __m256);
+  compare (values.i4, i4, __m256);
+  compare (values.i5, i5, __m256);
+  compare (values.i6, i6, __m256);
+  compare (values.i7, i7, __m256);
+}
+
+void
+fun_check_passing_m256_8_regs (__m256 i0 ATTRIBUTE_UNUSED, __m256 i1 ATTRIBUTE_UNUSED, __m256 i2 ATTRIBUTE_UNUSED, __m256 i3 ATTRIBUTE_UNUSED, __m256 i4 ATTRIBUTE_UNUSED, __m256 i5 ATTRIBUTE_UNUSED, __m256 i6 ATTRIBUTE_UNUSED, __m256 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m256_arguments;
+}
+
+void
+fun_check_passing_m256_20_values (__m256 i0 ATTRIBUTE_UNUSED, __m256 i1 ATTRIBUTE_UNUSED, __m256 i2 ATTRIBUTE_UNUSED, __m256 i3 ATTRIBUTE_UNUSED, __m256 i4 ATTRIBUTE_UNUSED, __m256 i5 ATTRIBUTE_UNUSED, __m256 i6 ATTRIBUTE_UNUSED, __m256 i7 ATTRIBUTE_UNUSED, __m256 i8 ATTRIBUTE_UNUSED, __m256 i9 ATTRIBUTE_UNUSED, __m256 i10 ATTRIBUTE_UNUSED, __m256 i11 ATTRIBUTE_UNUSED, __m256 i12 ATTRIBUTE_UNUSED, __m256 i13 ATTRIBUTE_UNUSED, __m256 i14 ATTRIBUTE_UNUSED, __m256 i15 ATTRIBUTE_UNUSED, __m256 i16 ATTRIBUTE_UNUSED, __m256 i17 ATTRIBUTE_UNUSED, __m256 i18 ATTRIBUTE_UNUSED, __m256 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m256);
+  compare (values.i1, i1, __m256);
+  compare (values.i2, i2, __m256);
+  compare (values.i3, i3, __m256);
+  compare (values.i4, i4, __m256);
+  compare (values.i5, i5, __m256);
+  compare (values.i6, i6, __m256);
+  compare (values.i7, i7, __m256);
+  compare (values.i8, i8, __m256);
+  compare (values.i9, i9, __m256);
+  compare (values.i10, i10, __m256);
+  compare (values.i11, i11, __m256);
+  compare (values.i12, i12, __m256);
+  compare (values.i13, i13, __m256);
+  compare (values.i14, i14, __m256);
+  compare (values.i15, i15, __m256);
+  compare (values.i16, i16, __m256);
+  compare (values.i17, i17, __m256);
+  compare (values.i18, i18, __m256);
+  compare (values.i19, i19, __m256);
+}
+
+void
+fun_check_passing_m256_20_regs (__m256 i0 ATTRIBUTE_UNUSED, __m256 i1 ATTRIBUTE_UNUSED, __m256 i2 ATTRIBUTE_UNUSED, __m256 i3 ATTRIBUTE_UNUSED, __m256 i4 ATTRIBUTE_UNUSED, __m256 i5 ATTRIBUTE_UNUSED, __m256 i6 ATTRIBUTE_UNUSED, __m256 i7 ATTRIBUTE_UNUSED, __m256 i8 ATTRIBUTE_UNUSED, __m256 i9 ATTRIBUTE_UNUSED, __m256 i10 ATTRIBUTE_UNUSED, __m256 i11 ATTRIBUTE_UNUSED, __m256 i12 ATTRIBUTE_UNUSED, __m256 i13 ATTRIBUTE_UNUSED, __m256 i14 ATTRIBUTE_UNUSED, __m256 i15 ATTRIBUTE_UNUSED, __m256 i16 ATTRIBUTE_UNUSED, __m256 i17 ATTRIBUTE_UNUSED, __m256 i18 ATTRIBUTE_UNUSED, __m256 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m256_arguments;
+}
+
+
+#define def_check_passing8(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7); \
+  \
+  clear_struct_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7);
+
+#define def_check_passing20(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  values.i8.TYPE[0] = _i8; \
+  values.i9.TYPE[0] = _i9; \
+  values.i10.TYPE[0] = _i10; \
+  values.i11.TYPE[0] = _i11; \
+  values.i12.TYPE[0] = _i12; \
+  values.i13.TYPE[0] = _i13; \
+  values.i14.TYPE[0] = _i14; \
+  values.i15.TYPE[0] = _i15; \
+  values.i16.TYPE[0] = _i16; \
+  values.i17.TYPE[0] = _i17; \
+  values.i18.TYPE[0] = _i18; \
+  values.i19.TYPE[0] = _i19; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19); \
+  \
+  clear_struct_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19);
+
+void
+test_m256_on_stack ()
+{
+  __m256 x[8];
+  int i;
+  for (i = 0; i < 8; i++)
+    x[i] = (__m256){32+i, 0, 0, 0, 0, 0, 0, 0};
+  pass = "m256-8";
+  def_check_passing8(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], fun_check_passing_m256_8_values, fun_check_passing_m256_8_regs, _m256);
+}
+
+void
+test_too_many_m256 ()
+{
+  __m256 x[20];
+  int i;
+  for (i = 0; i < 20; i++)
+    x[i] = (__m256){32+i, 0, 0, 0, 0, 0, 0, 0};
+  pass = "m256-20";
+  def_check_passing20(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[10], x[11], x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], fun_check_passing_m256_20_values, fun_check_passing_m256_20_regs, _m256);
+}
+
+static void
+avx_test (void)
+{
+  test_m256_on_stack ();
+  test_too_many_m256 ();
+  if (failed)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_structs.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_structs.c
new file mode 100644
index 000000000..7dbf6a59b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_structs.c
@@ -0,0 +1,61 @@
+#include "avx-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct m256_struct
+{
+  __m256 x;
+};
+
+struct m256_2_struct
+{
+  __m256 x1, x2;
+};
+
+/* Check that the struct is passed as the individual members in fregs.  */
+void
+check_struct_passing1 (struct m256_struct ms1 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms2 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms3 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms4 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms5 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms6 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms7 ATTRIBUTE_UNUSED,
+		       struct m256_struct ms8 ATTRIBUTE_UNUSED)
+{
+  check_m256_arguments;
+}
+
+void
+check_struct_passing2 (struct m256_2_struct ms ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ms.x1 == rsp+8);
+  assert ((unsigned long)&ms.x2 == rsp+40);
+}
+
+static void
+avx_test (void)
+{
+  struct m256_struct m256s [8];
+  struct m256_2_struct m256_2s = { 
+      { 48.394, 39.3, -397.9, 3484.9, -8.394, -93.3, 7.9, 84.94 },
+      { -8.394, -3.3, -39.9, 34.9, 7.9, 84.94, -48.394, 39.3 }
+  };
+  int i;
+
+  for (i = 0; i < 8; i++)
+    m256s[i].x = (__m256){32+i, 0, i, 0, -i, 0, i - 12, i + 8};
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    (&fregs.ymm0)[i]._m256[0] = m256s[i].x;
+  num_fregs = 8;
+  WRAP_CALL (check_struct_passing1)(m256s[0], m256s[1], m256s[2], m256s[3],
+				    m256s[4], m256s[5], m256s[6], m256s[7]);
+  WRAP_CALL (check_struct_passing2)(m256_2s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_unions.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_unions.c
new file mode 100644
index 000000000..127dd5f30
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx/test_passing_unions.c
@@ -0,0 +1,143 @@
+#include "avx-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+union un1
+{
+  __m256 x;
+  float f;
+};
+
+union un2
+{
+  __m256 x;
+  double d;
+};
+
+union un3
+{
+  __m256 x;
+  __m128 v;
+};
+
+union un4
+{
+  __m256 x;
+  long double ld;
+};
+
+union un5
+{
+  __m256 x;
+  int i;
+};
+
+void
+check_union_passing1(union un1 u1 ATTRIBUTE_UNUSED,
+		     union un1 u2 ATTRIBUTE_UNUSED,
+		     union un1 u3 ATTRIBUTE_UNUSED,
+		     union un1 u4 ATTRIBUTE_UNUSED,
+		     union un1 u5 ATTRIBUTE_UNUSED,
+		     union un1 u6 ATTRIBUTE_UNUSED,
+		     union un1 u7 ATTRIBUTE_UNUSED,
+		     union un1 u8 ATTRIBUTE_UNUSED)
+{
+  check_m256_arguments;
+}
+
+void
+check_union_passing2(union un2 u1 ATTRIBUTE_UNUSED,
+		     union un2 u2 ATTRIBUTE_UNUSED,
+		     union un2 u3 ATTRIBUTE_UNUSED,
+		     union un2 u4 ATTRIBUTE_UNUSED,
+		     union un2 u5 ATTRIBUTE_UNUSED,
+		     union un2 u6 ATTRIBUTE_UNUSED,
+		     union un2 u7 ATTRIBUTE_UNUSED,
+		     union un2 u8 ATTRIBUTE_UNUSED)
+{
+  check_m256_arguments;
+}
+
+void
+check_union_passing3(union un3 u1 ATTRIBUTE_UNUSED,
+		     union un3 u2 ATTRIBUTE_UNUSED,
+		     union un3 u3 ATTRIBUTE_UNUSED,
+		     union un3 u4 ATTRIBUTE_UNUSED,
+		     union un3 u5 ATTRIBUTE_UNUSED,
+		     union un3 u6 ATTRIBUTE_UNUSED,
+		     union un3 u7 ATTRIBUTE_UNUSED,
+		     union un3 u8 ATTRIBUTE_UNUSED)
+{
+  check_m256_arguments;
+}
+
+void
+check_union_passing4(union un4 u ATTRIBUTE_UNUSED)
+{
+   /* Check the passing on the stack by comparing the address of the
+      stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&u.x == rsp+8);
+  assert ((unsigned long)&u.ld == rsp+8);
+}
+
+void
+check_union_passing5(union un5 u ATTRIBUTE_UNUSED)
+{
+   /* Check the passing on the stack by comparing the address of the
+      stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&u.x == rsp+8);
+  assert ((unsigned long)&u.i == rsp+8);
+}
+
+#define check_union_passing1 WRAP_CALL(check_union_passing1)
+#define check_union_passing2 WRAP_CALL(check_union_passing2)
+#define check_union_passing3 WRAP_CALL(check_union_passing3)
+#define check_union_passing4 WRAP_CALL(check_union_passing4)
+#define check_union_passing5 WRAP_CALL(check_union_passing5)
+
+static void
+avx_test (void)
+{
+  union un1 u1[8];
+  union un2 u2[8];
+  union un3 u3[8];
+  union un4 u4;
+  union un5 u5;
+  int i;
+
+  for (i = 0; i < 8; i++)
+    u1[i].x = (__m256){32+i, 0, i, 0, -i, 0, i - 12, i + 8};
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    (&fregs.ymm0)[i]._m256[0] = u1[i].x;
+  num_fregs = 8;
+  check_union_passing1(u1[0], u1[1], u1[2], u1[3],
+		       u1[4], u1[5], u1[6], u1[7]);
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u2[i].x = u1[i].x;
+      (&fregs.ymm0)[i]._m256[0] = u2[i].x;
+    }
+  num_fregs = 8;
+  check_union_passing2(u2[0], u2[1], u2[2], u2[3],
+		       u2[4], u2[5], u2[6], u2[7]);
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u3[i].x = u1[i].x;
+      (&fregs.ymm0)[i]._m256[0] = u3[i].x;
+    }
+  num_fregs = 8;
+  check_union_passing3(u3[0], u3[1], u3[2], u3[3],
+		       u3[4], u3[5], u3[6], u3[7]);
+
+  check_union_passing4(u4);
+  check_union_passing5(u5);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/abi-avx512f.exp b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/abi-avx512f.exp
new file mode 100644
index 000000000..cef6fa141
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/abi-avx512f.exp
@@ -0,0 +1,61 @@
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# The x86-64 AVX512F ABI testsuite needs one additional assembler file for most
+# testcases.  For simplicity we will just link it into each test.
+
+load_lib c-torture.exp
+load_lib target-supports.exp
+load_lib torture-options.exp
+
+if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
+     || ![is-effective-target lp64]
+     || ![is-effective-target avx512f] } then {
+  return
+}
+
+
+# If the linker used understands -M <mapfile>, pass it to clear hardware
+# capabilities set by the Sun assembler.
+set flags ""
+set clearcap_ldflags "-Wl,-M,$srcdir/gcc.target/i386/clearcap.map"
+
+if [check_no_compiler_messages mapfile executable {
+	int main (void) { return 0; }
+  } $clearcap_ldflags ] {
+  set flags $clearcap_ldflags
+}
+
+torture-init
+set-torture-options $C_TORTURE_OPTIONS
+set additional_flags "-W -Wall -mavx512f $flags"
+
+foreach src [lsort [glob -nocomplain $srcdir/$subdir/test_*.c]] {
+    if {[runtest_file_p $runtests $src]} {
+	if { ([istarget *-*-darwin*]) } then {
+	    # FIXME: Darwin isn't tested.
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support-darwin.s] \
+				    $additional_flags
+	} else {
+	    c-torture-execute [list $src \
+				    $srcdir/$subdir/asm-support.S] \
+				    $additional_flags
+	}
+    }
+}
+
+torture-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/args.h b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/args.h
new file mode 100644
index 000000000..5e3b265ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/args.h
@@ -0,0 +1,184 @@
+#ifndef INCLUDED_ARGS_H
+#define INCLUDED_ARGS_H
+
+#include <immintrin.h>
+#include <string.h>
+
+/* Assertion macro.  */
+#define assert(test) if (!(test)) abort()
+
+#ifdef __GNUC__
+#define ATTRIBUTE_UNUSED __attribute__((__unused__))
+#else
+#define ATTRIBUTE_UNUSED
+#endif
+
+/* This defines the calling sequences for integers and floats.  */
+#define I0 rdi
+#define I1 rsi
+#define I2 rdx
+#define I3 rcx
+#define I4 r8
+#define I5 r9
+#define F0 zmm0
+#define F1 zmm1
+#define F2 zmm2
+#define F3 zmm3
+#define F4 zmm4
+#define F5 zmm5
+#define F6 zmm6
+#define F7 zmm7
+
+typedef union {
+  float _float[16];
+  double _double[8];
+  long _long[8];
+  int _int[16];
+  unsigned long _ulong[8];
+  __m64 _m64[8];
+  __m128 _m128[4];
+  __m256 _m256[2];
+  __m512 _m512[1];
+} ZMM_T;
+
+typedef union {
+  float _float;
+  double _double;
+  long double _ldouble;
+  unsigned long _ulong[2];
+} X87_T;
+extern void (*callthis)(void);
+extern unsigned long rax,rbx,rcx,rdx,rsi,rdi,rsp,rbp,r8,r9,r10,r11,r12,r13,r14,r15;
+ZMM_T zmm_regs[32];
+X87_T x87_regs[8];
+extern volatile unsigned long volatile_var;
+extern void snapshot (void);
+extern void snapshot_ret (void);
+#define WRAP_CALL(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot)
+#define WRAP_RET(N) \
+  (callthis = (void (*)()) (N), (typeof (&N)) snapshot_ret)
+
+/* Clear all integer registers.  */
+#define clear_int_hardware_registers \
+  asm __volatile__ ("xor %%rax, %%rax\n\t" \
+		    "xor %%rbx, %%rbx\n\t" \
+		    "xor %%rcx, %%rcx\n\t" \
+		    "xor %%rdx, %%rdx\n\t" \
+		    "xor %%rsi, %%rsi\n\t" \
+		    "xor %%rdi, %%rdi\n\t" \
+		    "xor %%r8, %%r8\n\t" \
+		    "xor %%r9, %%r9\n\t" \
+		    "xor %%r10, %%r10\n\t" \
+		    "xor %%r11, %%r11\n\t" \
+		    "xor %%r12, %%r12\n\t" \
+		    "xor %%r13, %%r13\n\t" \
+		    "xor %%r14, %%r14\n\t" \
+		    "xor %%r15, %%r15\n\t" \
+		    ::: "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "r8", \
+		    "r9", "r10", "r11", "r12", "r13", "r14", "r15");
+
+/* This is the list of registers available for passing arguments. Not all of
+   these are used or even really available.  */
+struct IntegerRegisters
+{
+  unsigned long rax, rbx, rcx, rdx, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15;
+};
+struct FloatRegisters
+{
+  double mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7;
+  long double st0, st1, st2, st3, st4, st5, st6, st7;
+  ZMM_T zmm0, zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm7, zmm8, zmm9,
+        zmm10, zmm11, zmm12, zmm13, zmm14, zmm15, zmm16, zmm17, zmm18,
+	zmm19, zmm20, zmm21, zmm22, zmm23, zmm24, zmm25, zmm26, zmm27,
+	zmm28, zmm29, zmm30, zmm31;
+};
+
+/* Implemented in scalarargs.c  */
+extern struct IntegerRegisters iregs;
+extern struct FloatRegisters fregs;
+extern unsigned int num_iregs, num_fregs;
+
+#define check_int_arguments do { \
+  assert (num_iregs <= 0 || iregs.I0 == I0); \
+  assert (num_iregs <= 1 || iregs.I1 == I1); \
+  assert (num_iregs <= 2 || iregs.I2 == I2); \
+  assert (num_iregs <= 3 || iregs.I3 == I3); \
+  assert (num_iregs <= 4 || iregs.I4 == I4); \
+  assert (num_iregs <= 5 || iregs.I5 == I5); \
+  } while (0)
+
+#define check_char_arguments check_int_arguments
+#define check_short_arguments check_int_arguments
+#define check_long_arguments check_int_arguments
+
+/* Clear register struct.  */
+#define clear_struct_registers \
+  rax = rbx = rcx = rdx = rdi = rsi = rbp = rsp \
+    = r8 = r9 = r10 = r11 = r12 = r13 = r14 = r15 = 0; \
+  memset (&iregs, 0, sizeof (iregs)); \
+  memset (&fregs, 0, sizeof (fregs)); \
+  memset (zmm_regs, 0, sizeof (zmm_regs)); \
+  memset (x87_regs, 0, sizeof (x87_regs));
+
+/* Clear both hardware and register structs for integers.  */
+#define clear_int_registers \
+  clear_struct_registers \
+  clear_int_hardware_registers
+
+/* TODO: Do the checking.  */
+#define check_f_arguments(T) do { \
+  assert (num_fregs <= 0 || fregs.zmm0._ ## T [0] == zmm_regs[0]._ ## T [0]); \
+  assert (num_fregs <= 1 || fregs.zmm1._ ## T [0] == zmm_regs[1]._ ## T [0]); \
+  assert (num_fregs <= 2 || fregs.zmm2._ ## T [0] == zmm_regs[2]._ ## T [0]); \
+  assert (num_fregs <= 3 || fregs.zmm3._ ## T [0] == zmm_regs[3]._ ## T [0]); \
+  assert (num_fregs <= 4 || fregs.zmm4._ ## T [0] == zmm_regs[4]._ ## T [0]); \
+  assert (num_fregs <= 5 || fregs.zmm5._ ## T [0] == zmm_regs[5]._ ## T [0]); \
+  assert (num_fregs <= 6 || fregs.zmm6._ ## T [0] == zmm_regs[6]._ ## T [0]); \
+  assert (num_fregs <= 7 || fregs.zmm7._ ## T [0] == zmm_regs[7]._ ## T [0]); \
+  } while (0)
+
+#define check_float_arguments check_f_arguments(float)
+#define check_double_arguments check_f_arguments(double)
+
+#define check_vector_arguments(T,O) do { \
+  assert (num_fregs <= 0 \
+	  || memcmp (((char *) &fregs.zmm0) + (O), \
+		     &zmm_regs[0], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 1 \
+	  || memcmp (((char *) &fregs.zmm1) + (O), \
+		     &zmm_regs[1], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 2 \
+	  || memcmp (((char *) &fregs.zmm2) + (O), \
+		     &zmm_regs[2], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 3 \
+	  || memcmp (((char *) &fregs.zmm3) + (O), \
+		     &zmm_regs[3], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 4 \
+	  || memcmp (((char *) &fregs.zmm4) + (O), \
+		     &zmm_regs[4], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 5 \
+	  || memcmp (((char *) &fregs.zmm5) + (O), \
+		     &zmm_regs[5], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 6 \
+	  || memcmp (((char *) &fregs.zmm6) + (O), \
+		     &zmm_regs[6], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  assert (num_fregs <= 7 \
+	  || memcmp (((char *) &fregs.zmm7) + (O), \
+		     &zmm_regs[7], \
+		     sizeof (__ ## T) - (O)) == 0); \
+  } while (0)
+
+#define check_m64_arguments check_vector_arguments(m64, 0)
+#define check_m128_arguments check_vector_arguments(m128, 0)
+#define check_m256_arguments check_vector_arguments(m256, 0)
+#define check_m512_arguments check_vector_arguments(m512, 0)
+
+#endif /* INCLUDED_ARGS_H  */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/asm-support.S b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/asm-support.S
new file mode 100644
index 000000000..e0309aeac
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/asm-support.S
@@ -0,0 +1,98 @@
+	.file	"snapshot.S"
+	.text
+	.p2align 4,,15
+.globl snapshot
+	.type	snapshot, @function
+snapshot:
+.LFB3:
+	movq	%rax, rax(%rip)
+	movq	%rbx, rbx(%rip)
+	movq	%rcx, rcx(%rip)
+	movq	%rdx, rdx(%rip)
+	movq	%rdi, rdi(%rip)
+	movq	%rsi, rsi(%rip)
+	movq	%rbp, rbp(%rip)
+	movq	%rsp, rsp(%rip)
+	movq	%r8, r8(%rip)
+	movq	%r9, r9(%rip)
+	movq	%r10, r10(%rip)
+	movq	%r11, r11(%rip)
+	movq	%r12, r12(%rip)
+	movq	%r13, r13(%rip)
+	movq	%r14, r14(%rip)
+	movq	%r15, r15(%rip)
+	vmovdqu32 %zmm0, zmm_regs+0(%rip)
+	vmovdqu32 %zmm1, zmm_regs+64(%rip)
+	vmovdqu32 %zmm2, zmm_regs+128(%rip)
+	vmovdqu32 %zmm3, zmm_regs+192(%rip)
+	vmovdqu32 %zmm4, zmm_regs+256(%rip)
+	vmovdqu32 %zmm5, zmm_regs+320(%rip)
+	vmovdqu32 %zmm6, zmm_regs+384(%rip)
+	vmovdqu32 %zmm7, zmm_regs+448(%rip)
+	vmovdqu32 %zmm8, zmm_regs+512(%rip)
+	vmovdqu32 %zmm9, zmm_regs+576(%rip)
+	vmovdqu32 %zmm10, zmm_regs+640(%rip)
+	vmovdqu32 %zmm11, zmm_regs+704(%rip)
+	vmovdqu32 %zmm12, zmm_regs+768(%rip)
+	vmovdqu32 %zmm13, zmm_regs+832(%rip)
+	vmovdqu32 %zmm14, zmm_regs+896(%rip)
+	vmovdqu32 %zmm15, zmm_regs+960(%rip)
+	vmovdqu32 %zmm16, zmm_regs+1024(%rip)
+	vmovdqu32 %zmm17, zmm_regs+1088(%rip)
+	vmovdqu32 %zmm18, zmm_regs+1152(%rip)
+	vmovdqu32 %zmm19, zmm_regs+1216(%rip)
+	vmovdqu32 %zmm20, zmm_regs+1280(%rip)
+	vmovdqu32 %zmm21, zmm_regs+1344(%rip)
+	vmovdqu32 %zmm22, zmm_regs+1408(%rip)
+	vmovdqu32 %zmm23, zmm_regs+1472(%rip)
+	vmovdqu32 %zmm24, zmm_regs+1536(%rip)
+	vmovdqu32 %zmm25, zmm_regs+1600(%rip)
+	vmovdqu32 %zmm26, zmm_regs+1664(%rip)
+	vmovdqu32 %zmm27, zmm_regs+1728(%rip)
+	vmovdqu32 %zmm28, zmm_regs+1792(%rip)
+	vmovdqu32 %zmm29, zmm_regs+1856(%rip)
+	vmovdqu32 %zmm30, zmm_regs+1920(%rip)
+	vmovdqu32 %zmm31, zmm_regs+1984(%rip)
+	jmp	*callthis(%rip)
+.LFE3:
+	.size	snapshot, .-snapshot
+
+	.p2align 4,,15
+.globl snapshot_ret
+	.type	snapshot_ret, @function
+snapshot_ret:
+	movq	%rdi, rdi(%rip)
+	subq	$8, %rsp
+	call	*callthis(%rip)
+	addq	$8, %rsp
+	movq	%rax, rax(%rip)
+	movq	%rdx, rdx(%rip)
+	vmovdqu32	%zmm0, zmm_regs+0(%rip)
+	vmovdqu32	%zmm1, zmm_regs+64(%rip)
+	fstpt	x87_regs(%rip)
+	fstpt	x87_regs+16(%rip)
+	fldt	x87_regs+16(%rip)
+	fldt	x87_regs(%rip)
+	ret
+	.size	snapshot_ret, .-snapshot_ret
+
+	.comm	callthis,8,8
+	.comm	rax,8,8
+	.comm	rbx,8,8
+	.comm	rcx,8,8
+	.comm	rdx,8,8
+	.comm	rsi,8,8
+	.comm	rdi,8,8
+	.comm	rsp,8,8
+	.comm	rbp,8,8
+	.comm	r8,8,8
+	.comm	r9,8,8
+	.comm	r10,8,8
+	.comm	r11,8,8
+	.comm	r12,8,8
+	.comm	r13,8,8
+	.comm	r14,8,8
+	.comm	r15,8,8
+	.comm	zmm_regs,2048,64
+	.comm	x87_regs,128,32
+	.comm   volatile_var,8,8
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/avx512f-check.h b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/avx512f-check.h
new file mode 100644
index 000000000..25ce544c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/avx512f-check.h
@@ -0,0 +1,41 @@
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void avx512f_test (void);
+
+int
+main ()
+{
+  unsigned int eax, ebx, ecx, edx;
+
+  if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+    return 0;
+
+#define DEBUG
+  /* Run AVX test only if host has AVX support.  */
+  if ((ecx & bit_OSXSAVE) == bit_OSXSAVE)
+    {
+      if (__get_cpuid_max (0, NULL) < 7)
+	return 0;
+
+      __cpuid_count (7, 0, eax, ebx, ecx, edx);
+
+      if ((ebx & bit_AVX512F) == bit_AVX512F)
+	{
+	  avx512f_test ();
+#ifdef DEBUG
+	  printf ("PASSED\n");
+#endif
+	}
+#ifdef DEBUG
+      else
+	printf ("SKIPPED\n");
+#endif
+    }
+#ifdef DEBUG
+  else
+    printf ("SKIPPED\n");
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_m512_returning.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_m512_returning.c
new file mode 100644
index 000000000..ee126b551
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_m512_returning.c
@@ -0,0 +1,32 @@
+#include <stdio.h>
+#include "avx512f-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+__m512
+fun_test_returning___m512 (void)
+{
+  volatile_var++;
+  return (__m512){73,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+}
+
+__m512 test_512;
+
+static void
+avx512f_test (void)
+{
+  unsigned failed = 0;
+  ZMM_T zmmt1, zmmt2;
+
+  clear_struct_registers;
+  test_512 = (__m512){73,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  zmmt1._m512[0] = test_512;
+  zmmt2._m512[0] = WRAP_RET (fun_test_returning___m512)();
+  if (memcmp (&zmmt1, &zmmt2, sizeof (zmmt2)) != 0)
+    printf ("fail m512\n"), failed++;
+  if (failed)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_m512.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_m512.c
new file mode 100644
index 000000000..ead9c6797
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_m512.c
@@ -0,0 +1,168 @@
+#include <stdio.h>
+#include "avx512f-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct
+{
+  ZMM_T i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values;
+
+char *pass;
+int failed = 0;
+
+#undef assert
+#define assert(c) do { \
+  if (!(c)) {failed++; printf ("failed %s\n", pass); } \
+} while (0)
+
+#define compare(X1,X2,T) do { \
+  assert (memcmp (&X1, &X2, sizeof (T)) == 0); \
+} while (0)
+
+fun_check_passing_m512_8_values (__m512 i0 ATTRIBUTE_UNUSED, __m512 i1 ATTRIBUTE_UNUSED, __m512 i2 ATTRIBUTE_UNUSED, __m512 i3 ATTRIBUTE_UNUSED, __m512 i4 ATTRIBUTE_UNUSED, __m512 i5 ATTRIBUTE_UNUSED, __m512 i6 ATTRIBUTE_UNUSED, __m512 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m512);
+  compare (values.i1, i1, __m512);
+  compare (values.i2, i2, __m512);
+  compare (values.i3, i3, __m512);
+  compare (values.i4, i4, __m512);
+  compare (values.i5, i5, __m512);
+  compare (values.i6, i6, __m512);
+  compare (values.i7, i7, __m512);
+}
+
+void
+fun_check_passing_m512_8_regs (__m512 i0 ATTRIBUTE_UNUSED, __m512 i1 ATTRIBUTE_UNUSED, __m512 i2 ATTRIBUTE_UNUSED, __m512 i3 ATTRIBUTE_UNUSED, __m512 i4 ATTRIBUTE_UNUSED, __m512 i5 ATTRIBUTE_UNUSED, __m512 i6 ATTRIBUTE_UNUSED, __m512 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m512_arguments;
+}
+
+void
+fun_check_passing_m512_20_values (__m512 i0 ATTRIBUTE_UNUSED, __m512 i1 ATTRIBUTE_UNUSED, __m512 i2 ATTRIBUTE_UNUSED, __m512 i3 ATTRIBUTE_UNUSED, __m512 i4 ATTRIBUTE_UNUSED, __m512 i5 ATTRIBUTE_UNUSED, __m512 i6 ATTRIBUTE_UNUSED, __m512 i7 ATTRIBUTE_UNUSED, __m512 i8 ATTRIBUTE_UNUSED, __m512 i9 ATTRIBUTE_UNUSED, __m512 i10 ATTRIBUTE_UNUSED, __m512 i11 ATTRIBUTE_UNUSED, __m512 i12 ATTRIBUTE_UNUSED, __m512 i13 ATTRIBUTE_UNUSED, __m512 i14 ATTRIBUTE_UNUSED, __m512 i15 ATTRIBUTE_UNUSED, __m512 i16 ATTRIBUTE_UNUSED, __m512 i17 ATTRIBUTE_UNUSED, __m512 i18 ATTRIBUTE_UNUSED, __m512 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m512);
+  compare (values.i1, i1, __m512);
+  compare (values.i2, i2, __m512);
+  compare (values.i3, i3, __m512);
+  compare (values.i4, i4, __m512);
+  compare (values.i5, i5, __m512);
+  compare (values.i6, i6, __m512);
+  compare (values.i7, i7, __m512);
+  compare (values.i8, i8, __m512);
+  compare (values.i9, i9, __m512);
+  compare (values.i10, i10, __m512);
+  compare (values.i11, i11, __m512);
+  compare (values.i12, i12, __m512);
+  compare (values.i13, i13, __m512);
+  compare (values.i14, i14, __m512);
+  compare (values.i15, i15, __m512);
+  compare (values.i16, i16, __m512);
+  compare (values.i17, i17, __m512);
+  compare (values.i18, i18, __m512);
+  compare (values.i19, i19, __m512);
+}
+
+void
+fun_check_passing_m512_20_regs (__m512 i0 ATTRIBUTE_UNUSED, __m512 i1 ATTRIBUTE_UNUSED, __m512 i2 ATTRIBUTE_UNUSED, __m512 i3 ATTRIBUTE_UNUSED, __m512 i4 ATTRIBUTE_UNUSED, __m512 i5 ATTRIBUTE_UNUSED, __m512 i6 ATTRIBUTE_UNUSED, __m512 i7 ATTRIBUTE_UNUSED, __m512 i8 ATTRIBUTE_UNUSED, __m512 i9 ATTRIBUTE_UNUSED, __m512 i10 ATTRIBUTE_UNUSED, __m512 i11 ATTRIBUTE_UNUSED, __m512 i12 ATTRIBUTE_UNUSED, __m512 i13 ATTRIBUTE_UNUSED, __m512 i14 ATTRIBUTE_UNUSED, __m512 i15 ATTRIBUTE_UNUSED, __m512 i16 ATTRIBUTE_UNUSED, __m512 i17 ATTRIBUTE_UNUSED, __m512 i18 ATTRIBUTE_UNUSED, __m512 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m512_arguments;
+}
+
+
+#define def_check_passing8(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7); \
+  \
+  clear_struct_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7);
+
+#define def_check_passing20(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  values.i8.TYPE[0] = _i8; \
+  values.i9.TYPE[0] = _i9; \
+  values.i10.TYPE[0] = _i10; \
+  values.i11.TYPE[0] = _i11; \
+  values.i12.TYPE[0] = _i12; \
+  values.i13.TYPE[0] = _i13; \
+  values.i14.TYPE[0] = _i14; \
+  values.i15.TYPE[0] = _i15; \
+  values.i16.TYPE[0] = _i16; \
+  values.i17.TYPE[0] = _i17; \
+  values.i18.TYPE[0] = _i18; \
+  values.i19.TYPE[0] = _i19; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19); \
+  \
+  clear_struct_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19);
+
+void
+test_m512_on_stack ()
+{
+  __m512 x[8];
+  int i;
+  for (i = 0; i < 8; i++)
+    x[i] = (__m512){32+i, 0, 0, 0, 0, 0, 0, 0};
+  pass = "m512-8";
+  def_check_passing8(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], fun_check_passing_m512_8_values, fun_check_passing_m512_8_regs, _m512);
+}
+
+void
+test_too_many_m512 ()
+{
+  __m512 x[20];
+  int i;
+  for (i = 0; i < 20; i++)
+    x[i] = (__m512){32+i, 0, 0, 0, 0, 0, 0, 0};
+  pass = "m512-20";
+  def_check_passing20(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[10], x[11], x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], fun_check_passing_m512_20_values, fun_check_passing_m512_20_regs, _m512);
+}
+
+static void
+avx512f_test (void)
+{
+  test_m512_on_stack ();
+  test_too_many_m512 ();
+  if (failed)
+    abort ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_structs.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_structs.c
new file mode 100644
index 000000000..8daa676e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_structs.c
@@ -0,0 +1,65 @@
+#include "avx512f-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct m512_struct
+{
+  __m512 x;
+};
+
+struct m512_2_struct
+{
+  __m512 x1, x2;
+};
+
+/* Check that the struct is passed as the individual members in fregs.  */
+void
+check_struct_passing1 (struct m512_struct ms1 ATTRIBUTE_UNUSED,
+		       struct m512_struct ms2 ATTRIBUTE_UNUSED,
+		       struct m512_struct ms3 ATTRIBUTE_UNUSED,
+		       struct m512_struct ms4 ATTRIBUTE_UNUSED,
+		       struct m512_struct ms5 ATTRIBUTE_UNUSED,
+		       struct m512_struct ms6 ATTRIBUTE_UNUSED,
+		       struct m512_struct ms7 ATTRIBUTE_UNUSED,
+		       struct m512_struct ms8 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m512_arguments;
+}
+
+void
+check_struct_passing2 (struct m512_2_struct ms ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ms.x1 == rsp+8);
+  assert ((unsigned long)&ms.x2 == rsp+72);
+}
+
+static void
+avx512f_test (void)
+{
+  struct m512_struct m512s [8];
+  struct m512_2_struct m512_2s = {
+      { 48.394, 39.3, -397.9, 3484.9, -8.394, -93.3, 7.9, 84.94,
+	48.3941, 39.31, -397.91, 3484.91, -8.3941, -93.31, 7.91, 84.941 },
+      { -8.394, -3.3, -39.9, 34.9, 7.9, 84.94, -48.394, 39.3,
+	-8.3942, -3.32, -39.92, 34.92, 7.92, 84.942, -48.3942, 39.32 }
+  };
+  int i;
+
+  for (i = 0; i < 8; i++)
+    m512s[i].x = (__m512){32+i, 0, i, 0, -i, 0, i - 12, i + 8,
+			  32+i, 0, i, 0, -i, 0, i - 12, i + 8};
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    (&fregs.zmm0)[i]._m512[0] = m512s[i].x;
+  num_fregs = 8;
+  WRAP_CALL (check_struct_passing1)(m512s[0], m512s[1], m512s[2], m512s[3],
+				    m512s[4], m512s[5], m512s[6], m512s[7]);
+  WRAP_CALL (check_struct_passing2)(m512_2s);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_unions.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_unions.c
new file mode 100644
index 000000000..370d15b62
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/avx512f/test_passing_unions.c
@@ -0,0 +1,180 @@
+#include "avx512f-check.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+union un1
+{
+  __m512 x;
+  float f;
+};
+
+union un2
+{
+  __m512 x;
+  double d;
+};
+
+union un3
+{
+  __m512 x;
+  __m128 v;
+};
+
+union un4
+{
+  __m512 x;
+  long double ld;
+};
+
+union un5
+{
+  __m512 x;
+  int i;
+};
+
+union un6
+{
+  __m512 x;
+  __m256 v;
+};
+
+
+void
+check_union_passing1(union un1 u1 ATTRIBUTE_UNUSED,
+		     union un1 u2 ATTRIBUTE_UNUSED,
+		     union un1 u3 ATTRIBUTE_UNUSED,
+		     union un1 u4 ATTRIBUTE_UNUSED,
+		     union un1 u5 ATTRIBUTE_UNUSED,
+		     union un1 u6 ATTRIBUTE_UNUSED,
+		     union un1 u7 ATTRIBUTE_UNUSED,
+		     union un1 u8 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m512_arguments;
+}
+
+void
+check_union_passing2(union un2 u1 ATTRIBUTE_UNUSED,
+		     union un2 u2 ATTRIBUTE_UNUSED,
+		     union un2 u3 ATTRIBUTE_UNUSED,
+		     union un2 u4 ATTRIBUTE_UNUSED,
+		     union un2 u5 ATTRIBUTE_UNUSED,
+		     union un2 u6 ATTRIBUTE_UNUSED,
+		     union un2 u7 ATTRIBUTE_UNUSED,
+		     union un2 u8 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m512_arguments;
+}
+
+void
+check_union_passing3(union un3 u1 ATTRIBUTE_UNUSED,
+		     union un3 u2 ATTRIBUTE_UNUSED,
+		     union un3 u3 ATTRIBUTE_UNUSED,
+		     union un3 u4 ATTRIBUTE_UNUSED,
+		     union un3 u5 ATTRIBUTE_UNUSED,
+		     union un3 u6 ATTRIBUTE_UNUSED,
+		     union un3 u7 ATTRIBUTE_UNUSED,
+		     union un3 u8 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m512_arguments;
+}
+
+void
+check_union_passing4(union un4 u ATTRIBUTE_UNUSED)
+{
+   /* Check the passing on the stack by comparing the address of the
+      stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&u.x == rsp+8);
+  assert ((unsigned long)&u.ld == rsp+8);
+}
+
+void
+check_union_passing5(union un5 u ATTRIBUTE_UNUSED)
+{
+   /* Check the passing on the stack by comparing the address of the
+      stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&u.x == rsp+8);
+  assert ((unsigned long)&u.i == rsp+8);
+}
+
+void
+check_union_passing6(union un6 u1 ATTRIBUTE_UNUSED,
+		     union un6 u2 ATTRIBUTE_UNUSED,
+		     union un6 u3 ATTRIBUTE_UNUSED,
+		     union un6 u4 ATTRIBUTE_UNUSED,
+		     union un6 u5 ATTRIBUTE_UNUSED,
+		     union un6 u6 ATTRIBUTE_UNUSED,
+		     union un6 u7 ATTRIBUTE_UNUSED,
+		     union un6 u8 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m512_arguments;
+}
+
+#define check_union_passing1 WRAP_CALL(check_union_passing1)
+#define check_union_passing2 WRAP_CALL(check_union_passing2)
+#define check_union_passing3 WRAP_CALL(check_union_passing3)
+#define check_union_passing4 WRAP_CALL(check_union_passing4)
+#define check_union_passing5 WRAP_CALL(check_union_passing5)
+#define check_union_passing6 WRAP_CALL(check_union_passing6)
+
+static void
+avx512f_test (void)
+{
+  union un1 u1[8];
+  union un2 u2[8];
+  union un3 u3[8];
+  union un4 u4;
+  union un5 u5;
+  union un6 u6[8];
+  int i;
+
+  for (i = 0; i < 8; i++)
+    u1[i].x = (__m512){32+i, 0, i, 0, -i, 0, i - 12, i + 8,
+		       32+i, 0, i, 0, -i, 0, i - 12, i + 8};
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    (&fregs.zmm0)[i]._m512[0] = u1[i].x;
+  num_fregs = 8;
+  check_union_passing1(u1[0], u1[1], u1[2], u1[3],
+		       u1[4], u1[5], u1[6], u1[7]);
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u2[i].x = u1[i].x;
+      (&fregs.zmm0)[i]._m512[0] = u2[i].x;
+    }
+  num_fregs = 8;
+  check_union_passing2(u2[0], u2[1], u2[2], u2[3],
+		       u2[4], u2[5], u2[6], u2[7]);
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u3[i].x = u1[i].x;
+      (&fregs.zmm0)[i]._m512[0] = u3[i].x;
+    }
+  num_fregs = 8;
+  check_union_passing3(u3[0], u3[1], u3[2], u3[3],
+		       u3[4], u3[5], u3[6], u3[7]);
+
+  check_union_passing4(u4);
+  check_union_passing5(u5);
+
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u6[i].x = u1[i].x;
+      (&fregs.zmm0)[i]._m512[0] = u6[i].x;
+    }
+  num_fregs = 8;
+  check_union_passing6(u6[0], u6[1], u6[2], u6[3],
+		       u6[4], u6[5], u6[6], u6[7]);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.exp b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.exp
new file mode 100644
index 000000000..930942b04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.exp
@@ -0,0 +1,36 @@
+#   Copyright (C) 2009-2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+if { (![istarget x86_64-*-*] && ![istarget i?86-*-*])
+     || [is-effective-target ilp32] } then {
+  return
+}
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+dg-init
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+    "" $DEFAULT_CFLAGS
+dg-finish
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.h b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.h
new file mode 100644
index 000000000..d008ad659
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/callabi.h
@@ -0,0 +1,50 @@
+/* First the default target definition.  */
+#ifndef __GNUC_VA_LIST
+#define __GNUC_VA_LIST
+  typedef __builtin_va_list __gnuc_va_list;
+#endif
+
+#ifndef _VA_LIST_DEFINED
+#define _VA_LIST_DEFINED
+  typedef __gnuc_va_list va_list;
+#endif
+
+#define __va_copy(d,s)	__builtin_va_copy(d,s)
+#define __va_start(v,l)	__builtin_va_start(v,l)
+#define __va_arg(v,l)	__builtin_va_arg(v,l)
+#define __va_end(v)	__builtin_va_end(v)
+
+#define __ms_va_copy(d,s) __builtin_ms_va_copy(d,s)
+#define __ms_va_start(v,l) __builtin_ms_va_start(v,l)
+#define __ms_va_arg(v,l)	__builtin_va_arg(v,l)
+#define __ms_va_end(v) __builtin_ms_va_end(v)
+
+#define __sysv_va_copy(d,s) __builtin_sysv_va_copy(d,s)
+#define __sysv_va_start(v,l) __builtin_sysv_va_start(v,l)
+#define __sysv_va_arg(v,l)	__builtin_va_arg(v,l)
+#define __sysv_va_end(v) __builtin_sysv_va_end(v)
+
+#define CALLABI_NATIVE
+
+#ifdef _WIN64
+#define CALLABI_CROSS __attribute__ ((sysv_abi))
+
+#define CROSS_VA_LIST	__builtin_sysv_va_list
+
+#define CROSS_VA_COPY(d,s) __sysv_va_copy(d,s)
+#define CROSS_VA_START(v,l) __sysv_va_start(v,l)
+#define CROSS_VA_ARG(v,l) __sysv_va_arg(v,l)
+#define CROSS_VA_END(v)  __sysv_va_end(v)
+
+#else
+
+#define CALLABI_CROSS __attribute__ ((ms_abi))
+
+#define CROSS_VA_LIST	__builtin_ms_va_list
+
+#define CROSS_VA_COPY(d,s) __ms_va_copy(d,s)
+#define CROSS_VA_START(v,l) __ms_va_start(v,l)
+#define CROSS_VA_ARG(v,l) __ms_va_arg(v,l)
+#define CROSS_VA_END(v)  __ms_va_end(v)
+
+#endif
\ No newline at end of file
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c
new file mode 100644
index 000000000..7d0b50636
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-1.c
@@ -0,0 +1,40 @@
+/* Test for cross x86_64<->w64 abi standard calls.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -ffast-math" } */
+#include "callabi.h"
+
+extern void abort (void);
+
+long double
+CALLABI_CROSS func_cross (long double a, double b, float c, long d, int e,
+			  char f)
+{
+  long double ret;
+  ret = a + (long double) b + (long double) c;
+  ret *= (long double) (d + (long) e);
+  if (f>0)
+    ret += func_cross (a,b,c,d,e,-f);
+  return ret;
+}
+
+long double
+CALLABI_NATIVE func_native (long double a, double b, float c, long d, int e,
+			    char f)
+{
+  long double ret;
+  ret = a + (long double) b + (long double) c;
+  ret *= (long double) (d + (long) e);
+  if (f>0)
+    ret += func_native (a,b,c,d,e,-f);
+  return ret;
+}
+
+int main ()
+{
+  if (func_cross (1.0,2.0,3.0,1,2,3)
+      != func_native (1.0,2.0,3.0,1,2,3))
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c
new file mode 100644
index 000000000..513f5619a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c
@@ -0,0 +1,27 @@
+/* Test for cross x86_64<->w64 abi standard calls.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
+/* { dg-additional-sources "func-2b.c" } */
+
+extern void __attribute__ ((sysv_abi)) abort (void);
+long double func_cross (long double, double, float, long, int, char);
+
+long double __attribute__ ((sysv_abi))
+func_native (long double a, double b, float c, long d, int e, char f)
+{
+  long double ret;
+  ret = a + (long double) b + (long double) c;
+  ret *= (long double) (d + (long) e);
+  if (f>0)
+    ret += func_native (a,b,c,d,e,-f);
+  return ret;
+}
+
+int __attribute__ ((sysv_abi))
+main ()
+{
+  if (func_cross (1.0,2.0,3.0,1,2,3)
+      != func_native (1.0,2.0,3.0,1,2,3))
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c
new file mode 100644
index 000000000..fe85dd186
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c
@@ -0,0 +1,13 @@
+/* Test for cross x86_64<->w64 abi standard calls.  */
+/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
+
+long double func_cross (long double a, double b, float c, long d, int e,
+			char f)
+{
+  long double ret;
+  ret = a + (long double) b + (long double) c;
+  ret *= (long double) (d + (long) e);
+  if (f>0)
+    ret += func_cross (a,b,c,d,e,-f);
+  return ret;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c
new file mode 100644
index 000000000..e1ff8f833
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c
@@ -0,0 +1,17 @@
+/* Test for cross x86_64<->w64 abi standard calls via variable.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
+/* { dg-additional-sources "func-indirect-2b.c" } */
+
+extern void __attribute__ ((sysv_abi)) abort (void);
+typedef int (*func)(void *, char *, char *, short, long long);
+extern func get_callback (void);
+
+int __attribute__ ((sysv_abi))
+main ()
+{
+  func callme = get_callback ();
+  if (callme (0, 0, 0, 0x1234, 0x1234567890abcdefLL))
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c
new file mode 100644
index 000000000..1a9fccd97
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c
@@ -0,0 +1,24 @@
+/* Test for cross x86_64<->w64 abi standard calls via variable.  */
+/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
+
+typedef int (*func)(void *, char *, char *, short, long long);
+
+static int
+callback (void *ptr, char *string1, char *string2, short number,
+	  long long rand)
+{
+  if (ptr != 0
+      || string1 != 0
+      || string2 != 0
+      || number != 0x1234
+      || rand != 0x1234567890abcdefLL)
+    return 1;
+  else
+    return 0;
+}
+
+func
+get_callback (void)
+{
+  return callback;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c
new file mode 100644
index 000000000..0c0cbb271
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect.c
@@ -0,0 +1,24 @@
+/* Test for cross x86_64<->w64 abi standard calls via variable.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99 -ffast-math" } */
+#include "callabi.h"
+
+extern void abort (void);
+
+typedef int (CALLABI_CROSS *func)(void *, char *, char *, short, long long);
+
+int CALLABI_CROSS
+callback(void * ptr, char *string1, char *string2, short number, long long rand)
+{
+    return (rand != 0x1234567890abcdefLL);
+}
+
+int main()
+{
+    volatile func callme = callback;
+    if(callme(0, 0, 0, 0, 0x1234567890abcdefLL))
+     abort();
+    return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c
new file mode 100644
index 000000000..35f8b53ca
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=sysv" } */
+
+__attribute__ ((ms_abi))
+int foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler-not "%rsp" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c
new file mode 100644
index 000000000..2a54bc89c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/leaf-2.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=sysv" } */
+
+extern int glb1, gbl2, gbl3;
+
+__attribute__ ((ms_abi))
+int foo (void)
+{
+  int r = 1;
+  int i, j, k;
+  for (i = 0; i < glb1; i++)
+  {
+     r *= (i + 1);
+     for (j = gbl2; j > 0; --j)
+       {
+	 for (k = 0; k < gbl3; k++)
+	   r += (i + k * j);
+       }
+  }
+
+  return r;
+}
+
+/* { dg-final { scan-assembler-not "%rsp" } } */
+
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c
new file mode 100644
index 000000000..d31b8c377
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/pr38891.c
@@ -0,0 +1,10 @@
+/* Test for cross x86_64<->w64 abi standard calls.
+*/
+/* { dg-do compile } */
+/* { dg-options "-mno-sse" } */
+#include "callabi.h"
+
+long double
+CALLABI_CROSS func_cross ()
+{
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c
new file mode 100644
index 000000000..a6d8463ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-1.c
@@ -0,0 +1,47 @@
+/* Test for cross x86_64<->w64 abi va_list calls.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99" } */
+#include "callabi.h"
+
+extern __SIZE_TYPE__ strlen (const char *);
+extern int sprintf (char *,const char *, ...);
+extern void abort (void);
+
+static
+void CALLABI_CROSS vdo_cpy (char *s, CROSS_VA_LIST argp)
+{
+  __SIZE_TYPE__ len;
+  char *r = s;
+  char *e;
+  *r = 0;
+  for (;;) {
+    e = CROSS_VA_ARG (argp,char *);
+    if (*e == 0) break;
+    sprintf (r,"%s", e);
+    r += strlen (r);
+  }
+}
+
+static
+void CALLABI_CROSS do_cpy (char *s, ...)
+{
+  CROSS_VA_LIST argp;
+  CROSS_VA_START (argp, s);
+  vdo_cpy (s, argp);
+  CROSS_VA_END (argp);
+}
+
+int main ()
+{
+  char s[256];
+
+  do_cpy (s, "1","2","3","4", "5", "6", "7", "");
+
+  if (s[0] != '1' || s[1] !='2' || s[2] != '3' || s[3] != '4'
+      || s[4] != '5' || s[5] != '6' || s[6] != '7' || s[7] != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c
new file mode 100644
index 000000000..e281e860f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-2.c
@@ -0,0 +1,47 @@
+/* Test for cross x86_64<->w64 abi va_list calls.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99" } */
+#include "callabi.h"
+
+extern void abort (void);
+
+#define SZ_ARGS	1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll
+
+static
+int CALLABI_CROSS fct1 (va_list argp, ...)
+{
+  long long p1,p2;
+  int ret = 1;
+  CROSS_VA_LIST argp_2;
+  CROSS_VA_START (argp_2,argp);
+
+  do {
+    p1 = CROSS_VA_ARG (argp_2, long long);
+    p2 = __va_arg (argp, long long);
+    if (p1 != p2)
+      ret = 0;
+  } while (ret && p1 != 0);
+  CROSS_VA_END (argp_2);
+  return ret;
+}
+
+static
+int fct2 (int dummy, ...)
+{
+  va_list argp;
+  int ret = dummy;
+
+  __va_start (argp, dummy);
+  ret += fct1 (argp, SZ_ARGS);
+  __va_end (argp);
+  return ret;
+}
+
+int main()
+{
+  if (fct2 (-1, SZ_ARGS) != 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c
new file mode 100644
index 000000000..7cca7ac87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-3.c
@@ -0,0 +1,47 @@
+/* Test for cross x86_64<->w64 abi va_list calls.
+*/
+/* Origin: Kai Tietz <kai.tietz@onevision.com> */
+/* { dg-do run } */
+/* { dg-options "-std=gnu99" } */
+#include "callabi.h"
+
+extern void abort (void);
+
+#define SZ_ARGS	1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll
+
+static
+int fct1 (CROSS_VA_LIST argp, ...)
+{
+  long long p1,p2;
+  int ret = 1;
+  va_list argp_2;
+
+    __va_start (argp_2,argp);
+  do {
+    p1 = __va_arg (argp_2, long long);
+    p2 = CROSS_VA_ARG (argp, long long);
+    if (p1 != p2)
+      ret = 0;
+  } while (ret && p1 != 0);
+  __va_end (argp_2);
+  return ret;
+}
+
+static
+int CALLABI_CROSS fct2 (int dummy, ...)
+{
+  CROSS_VA_LIST argp;
+  int ret = dummy;
+
+  CROSS_VA_START (argp, dummy);
+  ret += fct1 (argp, SZ_ARGS);
+  CROSS_VA_END (argp);
+  return ret;
+}
+
+int main()
+{
+  if (fct2 (-1, SZ_ARGS) != 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c
new file mode 100644
index 000000000..36bd3483f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c
@@ -0,0 +1,24 @@
+/* Test for cross x86_64<->w64 abi va_list calls.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
+/* { dg-additional-sources "vaarg-4b.c" } */
+
+extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);
+extern int __attribute__ ((sysv_abi)) sprintf (char *,const char *, ...);
+extern void __attribute__ ((sysv_abi)) abort (void);
+
+extern void do_cpy (char *, ...);
+
+int __attribute__ ((sysv_abi))
+main ()
+{
+  char s[256];
+
+  do_cpy (s, "1","2","3","4", "5", "6", "7", "");
+
+  if (s[0] != '1' || s[1] !='2' || s[2] != '3' || s[3] != '4'
+      || s[4] != '5' || s[5] != '6' || s[6] != '7' || s[7] != 0)
+    abort ();
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c
new file mode 100644
index 000000000..f33906bd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c
@@ -0,0 +1,31 @@
+/* Test for cross x86_64<->w64 abi va_list calls.  */
+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
+
+#include <stdarg.h>
+
+extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);
+extern int __attribute__ ((sysv_abi)) sprintf (char *, const char *, ...);
+
+static void
+vdo_cpy (char *s, va_list argp)
+{
+  __SIZE_TYPE__ len;
+  char *r = s;
+  char *e;
+  *r = 0;
+  for (;;) {
+    e = va_arg (argp, char *);
+    if (*e == 0) break;
+    sprintf (r,"%s", e);
+    r += strlen (r);
+  }
+}
+
+void
+do_cpy (char *s, ...)
+{
+  va_list argp;
+  va_start (argp, s);
+  vdo_cpy (s, argp);
+  va_end (argp);
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c
new file mode 100644
index 000000000..fa8567779
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c
@@ -0,0 +1,17 @@
+/* Test for cross x86_64<->w64 abi va_list calls.  */
+/* { dg-do run } */
+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
+/* { dg-additional-sources "vaarg-5b.c" } */
+
+extern void __attribute__ ((sysv_abi)) abort (void);
+extern int fct2 (int, ...);
+
+#define SZ_ARGS	1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll
+
+int __attribute__ ((sysv_abi))
+main()
+{
+  if (fct2 (-1, SZ_ARGS) != 0)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c
new file mode 100644
index 000000000..e5dd4727b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c
@@ -0,0 +1,37 @@
+/* Test for cross x86_64<->w64 abi va_list calls.  */
+/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
+
+#include <stdarg.h>
+
+#define SZ_ARGS	1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll
+
+static int __attribute__ ((sysv_abi))
+fct1 (va_list argp, ...)
+{
+  long long p1,p2;
+  int ret = 1;
+  __builtin_sysv_va_list argp_2;
+
+  __builtin_sysv_va_start (argp_2, argp);
+  do {
+    p1 = va_arg (argp_2, long long);
+    p2 = va_arg (argp, long long);
+    if (p1 != p2)
+      ret = 0;
+  } while (ret && p1 != 0);
+  __builtin_sysv_va_end (argp_2);
+
+  return ret;
+}
+
+int
+fct2 (int dummy, ...)
+{
+  va_list argp;
+  int ret = dummy;
+
+  va_start (argp, dummy);
+  ret += fct1 (argp, SZ_ARGS);
+  va_end (argp);
+  return ret;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/defines.h b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/defines.h
new file mode 100644
index 000000000..a32daf694
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/defines.h
@@ -0,0 +1,148 @@
+#ifndef DEFINED_DEFINES_H
+#define DEFINED_DEFINES_H
+
+/* Get __m64 and __m128. */
+#include <xmmintrin.h>
+
+typedef unsigned long ulong;
+typedef long double ldouble;
+
+/* These defines determines what part of the test should be run.  When
+   GCC implements these parts, the defines should be uncommented to
+   enable testing.  */
+
+/* Scalar type __int128.  */
+/* #define CHECK_INT128 */
+
+/* Scalar type long double.  */
+#define CHECK_LONG_DOUBLE
+
+/* Scalar type __float128.  */
+/* #define CHECK_FLOAT128 */
+
+/* Scalar types __m64 and __m128.  */
+#define CHECK_M64_M128
+
+/* Returning of complex type.  */
+#define CHECK_COMPLEX
+
+/* Structs with size >= 16.  */
+#define CHECK_LARGER_STRUCTS
+
+/* Checks for passing floats and doubles.  */
+#define CHECK_FLOAT_DOUBLE_PASSING
+
+/* Union passing with not-extremely-simple unions.  */
+#define CHECK_LARGER_UNION_PASSING
+
+/* Variable args.  */
+#define CHECK_VARARGS
+
+/* Check argument passing and returning for scalar types with sizeof = 16.  */
+/* TODO: Implement these tests. Don't activate them for now.  */
+#define CHECK_LARGE_SCALAR_PASSING
+
+/* Defines for sizing and alignment.  */
+
+#define TYPE_SIZE_CHAR         1
+#define TYPE_SIZE_SHORT        2
+#define TYPE_SIZE_INT          4
+#define TYPE_SIZE_LONG         8
+#define TYPE_SIZE_LONG_LONG    8
+#define TYPE_SIZE_INT128       16
+#define TYPE_SIZE_FLOAT        4
+#define TYPE_SIZE_DOUBLE       8
+#define TYPE_SIZE_LONG_DOUBLE  16
+#define TYPE_SIZE_FLOAT128     16
+#define TYPE_SIZE_M64          8
+#define TYPE_SIZE_M128         16
+#define TYPE_SIZE_ENUM         4
+#define TYPE_SIZE_POINTER      8
+
+#define TYPE_ALIGN_CHAR        1
+#define TYPE_ALIGN_SHORT       2
+#define TYPE_ALIGN_INT         4
+#define TYPE_ALIGN_LONG        8
+#define TYPE_ALIGN_LONG_LONG   8
+#define TYPE_ALIGN_INT128      16
+#define TYPE_ALIGN_FLOAT       4
+#define TYPE_ALIGN_DOUBLE      8
+#define TYPE_ALIGN_LONG_DOUBLE 16
+#define TYPE_ALIGN_FLOAT128    16
+#define TYPE_ALIGN_M64         8
+#define TYPE_ALIGN_M128        16
+#define TYPE_ALIGN_ENUM        4
+#define TYPE_ALIGN_POINTER     8
+
+/* These defines control the building of the list of types to check. There
+   is a string identifying the type (with a comma after), a size of the type
+   (also with a comma and an integer for adding to the total amount of types)
+   and an alignment of the type (which is currently not really needed since
+   the abi specifies that alignof == sizeof for all scalar types).  */
+#ifdef CHECK_INT128
+#define CI128_STR "__int128",
+#define CI128_SIZ TYPE_SIZE_INT128,
+#define CI128_ALI TYPE_ALIGN_INT128,
+#define CI128_RET "???",
+#else
+#define CI128_STR
+#define CI128_SIZ
+#define CI128_ALI
+#define CI128_RET
+#endif
+#ifdef CHECK_LONG_DOUBLE
+#define CLD_STR "long double",
+#define CLD_SIZ TYPE_SIZE_LONG_DOUBLE,
+#define CLD_ALI TYPE_ALIGN_LONG_DOUBLE,
+#define CLD_RET "x87_regs[0]._ldouble",
+#else
+#define CLD_STR
+#define CLD_SIZ
+#define CLD_ALI
+#define CLD_RET
+#endif
+#ifdef CHECK_FLOAT128
+#define CF128_STR "__float128",
+#define CF128_SIZ TYPE_SIZE_FLOAT128,
+#define CF128_ALI TYPE_ALIGN_FLOAT128, 
+#define CF128_RET "???",
+#else
+#define CF128_STR
+#define CF128_SIZ
+#define CF128_ALI
+#define CF128_RET
+#endif
+#ifdef CHECK_M64_M128
+#define CMM_STR "__m64", "__m128",
+#define CMM_SIZ TYPE_SIZE_M64, TYPE_SIZE_M128,
+#define CMM_ALI TYPE_ALIGN_M64, TYPE_ALIGN_M128,
+#define CMM_RET "???", "???",
+#else
+#define CMM_STR
+#define CMM_SIZ
+#define CMM_ALI
+#define CMM_RET
+#endif
+
+/* Used in size and alignment tests.  */
+enum dummytype { enumtype };
+
+extern void abort (void);
+
+/* Assertion macro.  */
+#define assert(test) if (!(test)) abort()
+
+#ifdef __GNUC__
+#define ATTRIBUTE_UNUSED __attribute__((__unused__))
+#else
+#define ATTRIBUTE_UNUSED
+#endif
+
+#ifdef __GNUC__
+#define PACKED __attribute__((__packed__))
+#else
+#warning Some tests will fail due to missing __packed__ support
+#define PACKED
+#endif
+
+#endif /* DEFINED_DEFINES_H */
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/macros.h b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/macros.h
new file mode 100644
index 000000000..98fbc660f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/macros.h
@@ -0,0 +1,53 @@
+#ifndef MACROS_H
+
+#define check_size(_t, _size) assert(sizeof(_t) == (_size))
+
+#define check_align(_t, _align) assert(__alignof__(_t) == (_align))
+
+#define check_align_lv(_t, _align) assert(__alignof__(_t) == (_align) \
+					  && (((unsigned long)&(_t)) & ((_align) - 1) ) == 0)
+
+#define check_basic_struct_size_and_align(_type, _size, _align) { \
+  struct _str { _type dummy; } _t; \
+  check_size(_t, _size); \
+  check_align_lv(_t, _align); \
+}
+
+#define check_array_size_and_align(_type, _size, _align) { \
+  _type _a[1]; _type _b[2]; _type _c[16]; \
+  struct _str { _type _a[1]; } _s; \
+  check_align_lv(_a[0], _align); \
+  check_size(_a, _size); \
+  check_size(_b, (_size*2)); \
+  check_size(_c, (_size*16)); \
+  check_size(_s, _size); \
+  check_align_lv(_s._a[0], _align); \
+}
+
+#define check_basic_union_size_and_align(_type, _size, _align) { \
+  union _union { _type dummy; } _u; \
+  check_size(_u, _size); \
+  check_align_lv(_u, _align); \
+}
+
+#define run_signed_tests2(_function, _arg1, _arg2) \
+  _function(_arg1, _arg2); \
+  _function(signed _arg1, _arg2); \
+  _function(unsigned _arg1, _arg2);
+
+#define run_signed_tests3(_function, _arg1, _arg2, _arg3) \
+  _function(_arg1, _arg2, _arg3); \
+  _function(signed _arg1, _arg2, _arg3); \
+  _function(unsigned _arg1, _arg2, _arg3);
+
+/* Check size of a struct and a union of three types.  */
+
+#define check_struct_and_union3(type1, type2, type3, struct_size, align_size) \
+{ \
+  struct _str { type1 t1; type2 t2; type3 t3; } _t; \
+  union _uni { type1 t1; type2 t2; type3 t3; } _u; \
+  check_size(_t, struct_size); \
+  check_size(_u, align_size); \
+}
+
+#endif // MACROS_H
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_3_element_struct_and_unions.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_3_element_struct_and_unions.c
new file mode 100644
index 000000000..5227c6087
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_3_element_struct_and_unions.c
@@ -0,0 +1,523 @@
+/* This is an autogenerated file. Do not edit.  */
+
+#include "defines.h"
+#include "macros.h"
+
+/* Check structs and unions of all permutations of 3 basic types.  */
+int
+main (void)
+{
+  check_struct_and_union3(char, char, char, 3, 1);
+  check_struct_and_union3(char, char, short, 4, 2);
+  check_struct_and_union3(char, char, int, 8, 4);
+  check_struct_and_union3(char, char, long, 16, 8);
+  check_struct_and_union3(char, char, long long, 16, 8);
+  check_struct_and_union3(char, char, float, 8, 4);
+  check_struct_and_union3(char, char, double, 16, 8);
+  check_struct_and_union3(char, char, long double, 32, 16);
+  check_struct_and_union3(char, short, char, 6, 2);
+  check_struct_and_union3(char, short, short, 6, 2);
+  check_struct_and_union3(char, short, int, 8, 4);
+  check_struct_and_union3(char, short, long, 16, 8);
+  check_struct_and_union3(char, short, long long, 16, 8);
+  check_struct_and_union3(char, short, float, 8, 4);
+  check_struct_and_union3(char, short, double, 16, 8);
+  check_struct_and_union3(char, short, long double, 32, 16);
+  check_struct_and_union3(char, int, char, 12, 4);
+  check_struct_and_union3(char, int, short, 12, 4);
+  check_struct_and_union3(char, int, int, 12, 4);
+  check_struct_and_union3(char, int, long, 16, 8);
+  check_struct_and_union3(char, int, long long, 16, 8);
+  check_struct_and_union3(char, int, float, 12, 4);
+  check_struct_and_union3(char, int, double, 16, 8);
+  check_struct_and_union3(char, int, long double, 32, 16);
+  check_struct_and_union3(char, long, char, 24, 8);
+  check_struct_and_union3(char, long, short, 24, 8);
+  check_struct_and_union3(char, long, int, 24, 8);
+  check_struct_and_union3(char, long, long, 24, 8);
+  check_struct_and_union3(char, long, long long, 24, 8);
+  check_struct_and_union3(char, long, float, 24, 8);
+  check_struct_and_union3(char, long, double, 24, 8);
+  check_struct_and_union3(char, long, long double, 32, 16);
+  check_struct_and_union3(char, long long, char, 24, 8);
+  check_struct_and_union3(char, long long, short, 24, 8);
+  check_struct_and_union3(char, long long, int, 24, 8);
+  check_struct_and_union3(char, long long, long, 24, 8);
+  check_struct_and_union3(char, long long, long long, 24, 8);
+  check_struct_and_union3(char, long long, float, 24, 8);
+  check_struct_and_union3(char, long long, double, 24, 8);
+  check_struct_and_union3(char, long long, long double, 32, 16);
+  check_struct_and_union3(char, float, char, 12, 4);
+  check_struct_and_union3(char, float, short, 12, 4);
+  check_struct_and_union3(char, float, int, 12, 4);
+  check_struct_and_union3(char, float, long, 16, 8);
+  check_struct_and_union3(char, float, long long, 16, 8);
+  check_struct_and_union3(char, float, float, 12, 4);
+  check_struct_and_union3(char, float, double, 16, 8);
+  check_struct_and_union3(char, float, long double, 32, 16);
+  check_struct_and_union3(char, double, char, 24, 8);
+  check_struct_and_union3(char, double, short, 24, 8);
+  check_struct_and_union3(char, double, int, 24, 8);
+  check_struct_and_union3(char, double, long, 24, 8);
+  check_struct_and_union3(char, double, long long, 24, 8);
+  check_struct_and_union3(char, double, float, 24, 8);
+  check_struct_and_union3(char, double, double, 24, 8);
+  check_struct_and_union3(char, double, long double, 32, 16);
+  check_struct_and_union3(char, long double, char, 48, 16);
+  check_struct_and_union3(char, long double, short, 48, 16);
+  check_struct_and_union3(char, long double, int, 48, 16);
+  check_struct_and_union3(char, long double, long, 48, 16);
+  check_struct_and_union3(char, long double, long long, 48, 16);
+  check_struct_and_union3(char, long double, float, 48, 16);
+  check_struct_and_union3(char, long double, double, 48, 16);
+  check_struct_and_union3(char, long double, long double, 48, 16);
+  check_struct_and_union3(short, char, char, 4, 2);
+  check_struct_and_union3(short, char, short, 6, 2);
+  check_struct_and_union3(short, char, int, 8, 4);
+  check_struct_and_union3(short, char, long, 16, 8);
+  check_struct_and_union3(short, char, long long, 16, 8);
+  check_struct_and_union3(short, char, float, 8, 4);
+  check_struct_and_union3(short, char, double, 16, 8);
+  check_struct_and_union3(short, char, long double, 32, 16);
+  check_struct_and_union3(short, short, char, 6, 2);
+  check_struct_and_union3(short, short, short, 6, 2);
+  check_struct_and_union3(short, short, int, 8, 4);
+  check_struct_and_union3(short, short, long, 16, 8);
+  check_struct_and_union3(short, short, long long, 16, 8);
+  check_struct_and_union3(short, short, float, 8, 4);
+  check_struct_and_union3(short, short, double, 16, 8);
+  check_struct_and_union3(short, short, long double, 32, 16);
+  check_struct_and_union3(short, int, char, 12, 4);
+  check_struct_and_union3(short, int, short, 12, 4);
+  check_struct_and_union3(short, int, int, 12, 4);
+  check_struct_and_union3(short, int, long, 16, 8);
+  check_struct_and_union3(short, int, long long, 16, 8);
+  check_struct_and_union3(short, int, float, 12, 4);
+  check_struct_and_union3(short, int, double, 16, 8);
+  check_struct_and_union3(short, int, long double, 32, 16);
+  check_struct_and_union3(short, long, char, 24, 8);
+  check_struct_and_union3(short, long, short, 24, 8);
+  check_struct_and_union3(short, long, int, 24, 8);
+  check_struct_and_union3(short, long, long, 24, 8);
+  check_struct_and_union3(short, long, long long, 24, 8);
+  check_struct_and_union3(short, long, float, 24, 8);
+  check_struct_and_union3(short, long, double, 24, 8);
+  check_struct_and_union3(short, long, long double, 32, 16);
+  check_struct_and_union3(short, long long, char, 24, 8);
+  check_struct_and_union3(short, long long, short, 24, 8);
+  check_struct_and_union3(short, long long, int, 24, 8);
+  check_struct_and_union3(short, long long, long, 24, 8);
+  check_struct_and_union3(short, long long, long long, 24, 8);
+  check_struct_and_union3(short, long long, float, 24, 8);
+  check_struct_and_union3(short, long long, double, 24, 8);
+  check_struct_and_union3(short, long long, long double, 32, 16);
+  check_struct_and_union3(short, float, char, 12, 4);
+  check_struct_and_union3(short, float, short, 12, 4);
+  check_struct_and_union3(short, float, int, 12, 4);
+  check_struct_and_union3(short, float, long, 16, 8);
+  check_struct_and_union3(short, float, long long, 16, 8);
+  check_struct_and_union3(short, float, float, 12, 4);
+  check_struct_and_union3(short, float, double, 16, 8);
+  check_struct_and_union3(short, float, long double, 32, 16);
+  check_struct_and_union3(short, double, char, 24, 8);
+  check_struct_and_union3(short, double, short, 24, 8);
+  check_struct_and_union3(short, double, int, 24, 8);
+  check_struct_and_union3(short, double, long, 24, 8);
+  check_struct_and_union3(short, double, long long, 24, 8);
+  check_struct_and_union3(short, double, float, 24, 8);
+  check_struct_and_union3(short, double, double, 24, 8);
+  check_struct_and_union3(short, double, long double, 32, 16);
+  check_struct_and_union3(short, long double, char, 48, 16);
+  check_struct_and_union3(short, long double, short, 48, 16);
+  check_struct_and_union3(short, long double, int, 48, 16);
+  check_struct_and_union3(short, long double, long, 48, 16);
+  check_struct_and_union3(short, long double, long long, 48, 16);
+  check_struct_and_union3(short, long double, float, 48, 16);
+  check_struct_and_union3(short, long double, double, 48, 16);
+  check_struct_and_union3(short, long double, long double, 48, 16);
+  check_struct_and_union3(int, char, char, 8, 4);
+  check_struct_and_union3(int, char, short, 8, 4);
+  check_struct_and_union3(int, char, int, 12, 4);
+  check_struct_and_union3(int, char, long, 16, 8);
+  check_struct_and_union3(int, char, long long, 16, 8);
+  check_struct_and_union3(int, char, float, 12, 4);
+  check_struct_and_union3(int, char, double, 16, 8);
+  check_struct_and_union3(int, char, long double, 32, 16);
+  check_struct_and_union3(int, short, char, 8, 4);
+  check_struct_and_union3(int, short, short, 8, 4);
+  check_struct_and_union3(int, short, int, 12, 4);
+  check_struct_and_union3(int, short, long, 16, 8);
+  check_struct_and_union3(int, short, long long, 16, 8);
+  check_struct_and_union3(int, short, float, 12, 4);
+  check_struct_and_union3(int, short, double, 16, 8);
+  check_struct_and_union3(int, short, long double, 32, 16);
+  check_struct_and_union3(int, int, char, 12, 4);
+  check_struct_and_union3(int, int, short, 12, 4);
+  check_struct_and_union3(int, int, int, 12, 4);
+  check_struct_and_union3(int, int, long, 16, 8);
+  check_struct_and_union3(int, int, long long, 16, 8);
+  check_struct_and_union3(int, int, float, 12, 4);
+  check_struct_and_union3(int, int, double, 16, 8);
+  check_struct_and_union3(int, int, long double, 32, 16);
+  check_struct_and_union3(int, long, char, 24, 8);
+  check_struct_and_union3(int, long, short, 24, 8);
+  check_struct_and_union3(int, long, int, 24, 8);
+  check_struct_and_union3(int, long, long, 24, 8);
+  check_struct_and_union3(int, long, long long, 24, 8);
+  check_struct_and_union3(int, long, float, 24, 8);
+  check_struct_and_union3(int, long, double, 24, 8);
+  check_struct_and_union3(int, long, long double, 32, 16);
+  check_struct_and_union3(int, long long, char, 24, 8);
+  check_struct_and_union3(int, long long, short, 24, 8);
+  check_struct_and_union3(int, long long, int, 24, 8);
+  check_struct_and_union3(int, long long, long, 24, 8);
+  check_struct_and_union3(int, long long, long long, 24, 8);
+  check_struct_and_union3(int, long long, float, 24, 8);
+  check_struct_and_union3(int, long long, double, 24, 8);
+  check_struct_and_union3(int, long long, long double, 32, 16);
+  check_struct_and_union3(int, float, char, 12, 4);
+  check_struct_and_union3(int, float, short, 12, 4);
+  check_struct_and_union3(int, float, int, 12, 4);
+  check_struct_and_union3(int, float, long, 16, 8);
+  check_struct_and_union3(int, float, long long, 16, 8);
+  check_struct_and_union3(int, float, float, 12, 4);
+  check_struct_and_union3(int, float, double, 16, 8);
+  check_struct_and_union3(int, float, long double, 32, 16);
+  check_struct_and_union3(int, double, char, 24, 8);
+  check_struct_and_union3(int, double, short, 24, 8);
+  check_struct_and_union3(int, double, int, 24, 8);
+  check_struct_and_union3(int, double, long, 24, 8);
+  check_struct_and_union3(int, double, long long, 24, 8);
+  check_struct_and_union3(int, double, float, 24, 8);
+  check_struct_and_union3(int, double, double, 24, 8);
+  check_struct_and_union3(int, double, long double, 32, 16);
+  check_struct_and_union3(int, long double, char, 48, 16);
+  check_struct_and_union3(int, long double, short, 48, 16);
+  check_struct_and_union3(int, long double, int, 48, 16);
+  check_struct_and_union3(int, long double, long, 48, 16);
+  check_struct_and_union3(int, long double, long long, 48, 16);
+  check_struct_and_union3(int, long double, float, 48, 16);
+  check_struct_and_union3(int, long double, double, 48, 16);
+  check_struct_and_union3(int, long double, long double, 48, 16);
+  check_struct_and_union3(long, char, char, 16, 8);
+  check_struct_and_union3(long, char, short, 16, 8);
+  check_struct_and_union3(long, char, int, 16, 8);
+  check_struct_and_union3(long, char, long, 24, 8);
+  check_struct_and_union3(long, char, long long, 24, 8);
+  check_struct_and_union3(long, char, float, 16, 8);
+  check_struct_and_union3(long, char, double, 24, 8);
+  check_struct_and_union3(long, char, long double, 32, 16);
+  check_struct_and_union3(long, short, char, 16, 8);
+  check_struct_and_union3(long, short, short, 16, 8);
+  check_struct_and_union3(long, short, int, 16, 8);
+  check_struct_and_union3(long, short, long, 24, 8);
+  check_struct_and_union3(long, short, long long, 24, 8);
+  check_struct_and_union3(long, short, float, 16, 8);
+  check_struct_and_union3(long, short, double, 24, 8);
+  check_struct_and_union3(long, short, long double, 32, 16);
+  check_struct_and_union3(long, int, char, 16, 8);
+  check_struct_and_union3(long, int, short, 16, 8);
+  check_struct_and_union3(long, int, int, 16, 8);
+  check_struct_and_union3(long, int, long, 24, 8);
+  check_struct_and_union3(long, int, long long, 24, 8);
+  check_struct_and_union3(long, int, float, 16, 8);
+  check_struct_and_union3(long, int, double, 24, 8);
+  check_struct_and_union3(long, int, long double, 32, 16);
+  check_struct_and_union3(long, long, char, 24, 8);
+  check_struct_and_union3(long, long, short, 24, 8);
+  check_struct_and_union3(long, long, int, 24, 8);
+  check_struct_and_union3(long, long, long, 24, 8);
+  check_struct_and_union3(long, long, long long, 24, 8);
+  check_struct_and_union3(long, long, float, 24, 8);
+  check_struct_and_union3(long, long, double, 24, 8);
+  check_struct_and_union3(long, long, long double, 32, 16);
+  check_struct_and_union3(long, long long, char, 24, 8);
+  check_struct_and_union3(long, long long, short, 24, 8);
+  check_struct_and_union3(long, long long, int, 24, 8);
+  check_struct_and_union3(long, long long, long, 24, 8);
+  check_struct_and_union3(long, long long, long long, 24, 8);
+  check_struct_and_union3(long, long long, float, 24, 8);
+  check_struct_and_union3(long, long long, double, 24, 8);
+  check_struct_and_union3(long, long long, long double, 32, 16);
+  check_struct_and_union3(long, float, char, 16, 8);
+  check_struct_and_union3(long, float, short, 16, 8);
+  check_struct_and_union3(long, float, int, 16, 8);
+  check_struct_and_union3(long, float, long, 24, 8);
+  check_struct_and_union3(long, float, long long, 24, 8);
+  check_struct_and_union3(long, float, float, 16, 8);
+  check_struct_and_union3(long, float, double, 24, 8);
+  check_struct_and_union3(long, float, long double, 32, 16);
+  check_struct_and_union3(long, double, char, 24, 8);
+  check_struct_and_union3(long, double, short, 24, 8);
+  check_struct_and_union3(long, double, int, 24, 8);
+  check_struct_and_union3(long, double, long, 24, 8);
+  check_struct_and_union3(long, double, long long, 24, 8);
+  check_struct_and_union3(long, double, float, 24, 8);
+  check_struct_and_union3(long, double, double, 24, 8);
+  check_struct_and_union3(long, double, long double, 32, 16);
+  check_struct_and_union3(long, long double, char, 48, 16);
+  check_struct_and_union3(long, long double, short, 48, 16);
+  check_struct_and_union3(long, long double, int, 48, 16);
+  check_struct_and_union3(long, long double, long, 48, 16);
+  check_struct_and_union3(long, long double, long long, 48, 16);
+  check_struct_and_union3(long, long double, float, 48, 16);
+  check_struct_and_union3(long, long double, double, 48, 16);
+  check_struct_and_union3(long, long double, long double, 48, 16);
+  check_struct_and_union3(long long, char, char, 16, 8);
+  check_struct_and_union3(long long, char, short, 16, 8);
+  check_struct_and_union3(long long, char, int, 16, 8);
+  check_struct_and_union3(long long, char, long, 24, 8);
+  check_struct_and_union3(long long, char, long long, 24, 8);
+  check_struct_and_union3(long long, char, float, 16, 8);
+  check_struct_and_union3(long long, char, double, 24, 8);
+  check_struct_and_union3(long long, char, long double, 32, 16);
+  check_struct_and_union3(long long, short, char, 16, 8);
+  check_struct_and_union3(long long, short, short, 16, 8);
+  check_struct_and_union3(long long, short, int, 16, 8);
+  check_struct_and_union3(long long, short, long, 24, 8);
+  check_struct_and_union3(long long, short, long long, 24, 8);
+  check_struct_and_union3(long long, short, float, 16, 8);
+  check_struct_and_union3(long long, short, double, 24, 8);
+  check_struct_and_union3(long long, short, long double, 32, 16);
+  check_struct_and_union3(long long, int, char, 16, 8);
+  check_struct_and_union3(long long, int, short, 16, 8);
+  check_struct_and_union3(long long, int, int, 16, 8);
+  check_struct_and_union3(long long, int, long, 24, 8);
+  check_struct_and_union3(long long, int, long long, 24, 8);
+  check_struct_and_union3(long long, int, float, 16, 8);
+  check_struct_and_union3(long long, int, double, 24, 8);
+  check_struct_and_union3(long long, int, long double, 32, 16);
+  check_struct_and_union3(long long, long, char, 24, 8);
+  check_struct_and_union3(long long, long, short, 24, 8);
+  check_struct_and_union3(long long, long, int, 24, 8);
+  check_struct_and_union3(long long, long, long, 24, 8);
+  check_struct_and_union3(long long, long, long long, 24, 8);
+  check_struct_and_union3(long long, long, float, 24, 8);
+  check_struct_and_union3(long long, long, double, 24, 8);
+  check_struct_and_union3(long long, long, long double, 32, 16);
+  check_struct_and_union3(long long, long long, char, 24, 8);
+  check_struct_and_union3(long long, long long, short, 24, 8);
+  check_struct_and_union3(long long, long long, int, 24, 8);
+  check_struct_and_union3(long long, long long, long, 24, 8);
+  check_struct_and_union3(long long, long long, long long, 24, 8);
+  check_struct_and_union3(long long, long long, float, 24, 8);
+  check_struct_and_union3(long long, long long, double, 24, 8);
+  check_struct_and_union3(long long, long long, long double, 32, 16);
+  check_struct_and_union3(long long, float, char, 16, 8);
+  check_struct_and_union3(long long, float, short, 16, 8);
+  check_struct_and_union3(long long, float, int, 16, 8);
+  check_struct_and_union3(long long, float, long, 24, 8);
+  check_struct_and_union3(long long, float, long long, 24, 8);
+  check_struct_and_union3(long long, float, float, 16, 8);
+  check_struct_and_union3(long long, float, double, 24, 8);
+  check_struct_and_union3(long long, float, long double, 32, 16);
+  check_struct_and_union3(long long, double, char, 24, 8);
+  check_struct_and_union3(long long, double, short, 24, 8);
+  check_struct_and_union3(long long, double, int, 24, 8);
+  check_struct_and_union3(long long, double, long, 24, 8);
+  check_struct_and_union3(long long, double, long long, 24, 8);
+  check_struct_and_union3(long long, double, float, 24, 8);
+  check_struct_and_union3(long long, double, double, 24, 8);
+  check_struct_and_union3(long long, double, long double, 32, 16);
+  check_struct_and_union3(long long, long double, char, 48, 16);
+  check_struct_and_union3(long long, long double, short, 48, 16);
+  check_struct_and_union3(long long, long double, int, 48, 16);
+  check_struct_and_union3(long long, long double, long, 48, 16);
+  check_struct_and_union3(long long, long double, long long, 48, 16);
+  check_struct_and_union3(long long, long double, float, 48, 16);
+  check_struct_and_union3(long long, long double, double, 48, 16);
+  check_struct_and_union3(long long, long double, long double, 48, 16);
+  check_struct_and_union3(float, char, char, 8, 4);
+  check_struct_and_union3(float, char, short, 8, 4);
+  check_struct_and_union3(float, char, int, 12, 4);
+  check_struct_and_union3(float, char, long, 16, 8);
+  check_struct_and_union3(float, char, long long, 16, 8);
+  check_struct_and_union3(float, char, float, 12, 4);
+  check_struct_and_union3(float, char, double, 16, 8);
+  check_struct_and_union3(float, char, long double, 32, 16);
+  check_struct_and_union3(float, short, char, 8, 4);
+  check_struct_and_union3(float, short, short, 8, 4);
+  check_struct_and_union3(float, short, int, 12, 4);
+  check_struct_and_union3(float, short, long, 16, 8);
+  check_struct_and_union3(float, short, long long, 16, 8);
+  check_struct_and_union3(float, short, float, 12, 4);
+  check_struct_and_union3(float, short, double, 16, 8);
+  check_struct_and_union3(float, short, long double, 32, 16);
+  check_struct_and_union3(float, int, char, 12, 4);
+  check_struct_and_union3(float, int, short, 12, 4);
+  check_struct_and_union3(float, int, int, 12, 4);
+  check_struct_and_union3(float, int, long, 16, 8);
+  check_struct_and_union3(float, int, long long, 16, 8);
+  check_struct_and_union3(float, int, float, 12, 4);
+  check_struct_and_union3(float, int, double, 16, 8);
+  check_struct_and_union3(float, int, long double, 32, 16);
+  check_struct_and_union3(float, long, char, 24, 8);
+  check_struct_and_union3(float, long, short, 24, 8);
+  check_struct_and_union3(float, long, int, 24, 8);
+  check_struct_and_union3(float, long, long, 24, 8);
+  check_struct_and_union3(float, long, long long, 24, 8);
+  check_struct_and_union3(float, long, float, 24, 8);
+  check_struct_and_union3(float, long, double, 24, 8);
+  check_struct_and_union3(float, long, long double, 32, 16);
+  check_struct_and_union3(float, long long, char, 24, 8);
+  check_struct_and_union3(float, long long, short, 24, 8);
+  check_struct_and_union3(float, long long, int, 24, 8);
+  check_struct_and_union3(float, long long, long, 24, 8);
+  check_struct_and_union3(float, long long, long long, 24, 8);
+  check_struct_and_union3(float, long long, float, 24, 8);
+  check_struct_and_union3(float, long long, double, 24, 8);
+  check_struct_and_union3(float, long long, long double, 32, 16);
+  check_struct_and_union3(float, float, char, 12, 4);
+  check_struct_and_union3(float, float, short, 12, 4);
+  check_struct_and_union3(float, float, int, 12, 4);
+  check_struct_and_union3(float, float, long, 16, 8);
+  check_struct_and_union3(float, float, long long, 16, 8);
+  check_struct_and_union3(float, float, float, 12, 4);
+  check_struct_and_union3(float, float, double, 16, 8);
+  check_struct_and_union3(float, float, long double, 32, 16);
+  check_struct_and_union3(float, double, char, 24, 8);
+  check_struct_and_union3(float, double, short, 24, 8);
+  check_struct_and_union3(float, double, int, 24, 8);
+  check_struct_and_union3(float, double, long, 24, 8);
+  check_struct_and_union3(float, double, long long, 24, 8);
+  check_struct_and_union3(float, double, float, 24, 8);
+  check_struct_and_union3(float, double, double, 24, 8);
+  check_struct_and_union3(float, double, long double, 32, 16);
+  check_struct_and_union3(float, long double, char, 48, 16);
+  check_struct_and_union3(float, long double, short, 48, 16);
+  check_struct_and_union3(float, long double, int, 48, 16);
+  check_struct_and_union3(float, long double, long, 48, 16);
+  check_struct_and_union3(float, long double, long long, 48, 16);
+  check_struct_and_union3(float, long double, float, 48, 16);
+  check_struct_and_union3(float, long double, double, 48, 16);
+  check_struct_and_union3(float, long double, long double, 48, 16);
+  check_struct_and_union3(double, char, char, 16, 8);
+  check_struct_and_union3(double, char, short, 16, 8);
+  check_struct_and_union3(double, char, int, 16, 8);
+  check_struct_and_union3(double, char, long, 24, 8);
+  check_struct_and_union3(double, char, long long, 24, 8);
+  check_struct_and_union3(double, char, float, 16, 8);
+  check_struct_and_union3(double, char, double, 24, 8);
+  check_struct_and_union3(double, char, long double, 32, 16);
+  check_struct_and_union3(double, short, char, 16, 8);
+  check_struct_and_union3(double, short, short, 16, 8);
+  check_struct_and_union3(double, short, int, 16, 8);
+  check_struct_and_union3(double, short, long, 24, 8);
+  check_struct_and_union3(double, short, long long, 24, 8);
+  check_struct_and_union3(double, short, float, 16, 8);
+  check_struct_and_union3(double, short, double, 24, 8);
+  check_struct_and_union3(double, short, long double, 32, 16);
+  check_struct_and_union3(double, int, char, 16, 8);
+  check_struct_and_union3(double, int, short, 16, 8);
+  check_struct_and_union3(double, int, int, 16, 8);
+  check_struct_and_union3(double, int, long, 24, 8);
+  check_struct_and_union3(double, int, long long, 24, 8);
+  check_struct_and_union3(double, int, float, 16, 8);
+  check_struct_and_union3(double, int, double, 24, 8);
+  check_struct_and_union3(double, int, long double, 32, 16);
+  check_struct_and_union3(double, long, char, 24, 8);
+  check_struct_and_union3(double, long, short, 24, 8);
+  check_struct_and_union3(double, long, int, 24, 8);
+  check_struct_and_union3(double, long, long, 24, 8);
+  check_struct_and_union3(double, long, long long, 24, 8);
+  check_struct_and_union3(double, long, float, 24, 8);
+  check_struct_and_union3(double, long, double, 24, 8);
+  check_struct_and_union3(double, long, long double, 32, 16);
+  check_struct_and_union3(double, long long, char, 24, 8);
+  check_struct_and_union3(double, long long, short, 24, 8);
+  check_struct_and_union3(double, long long, int, 24, 8);
+  check_struct_and_union3(double, long long, long, 24, 8);
+  check_struct_and_union3(double, long long, long long, 24, 8);
+  check_struct_and_union3(double, long long, float, 24, 8);
+  check_struct_and_union3(double, long long, double, 24, 8);
+  check_struct_and_union3(double, long long, long double, 32, 16);
+  check_struct_and_union3(double, float, char, 16, 8);
+  check_struct_and_union3(double, float, short, 16, 8);
+  check_struct_and_union3(double, float, int, 16, 8);
+  check_struct_and_union3(double, float, long, 24, 8);
+  check_struct_and_union3(double, float, long long, 24, 8);
+  check_struct_and_union3(double, float, float, 16, 8);
+  check_struct_and_union3(double, float, double, 24, 8);
+  check_struct_and_union3(double, float, long double, 32, 16);
+  check_struct_and_union3(double, double, char, 24, 8);
+  check_struct_and_union3(double, double, short, 24, 8);
+  check_struct_and_union3(double, double, int, 24, 8);
+  check_struct_and_union3(double, double, long, 24, 8);
+  check_struct_and_union3(double, double, long long, 24, 8);
+  check_struct_and_union3(double, double, float, 24, 8);
+  check_struct_and_union3(double, double, double, 24, 8);
+  check_struct_and_union3(double, double, long double, 32, 16);
+  check_struct_and_union3(double, long double, char, 48, 16);
+  check_struct_and_union3(double, long double, short, 48, 16);
+  check_struct_and_union3(double, long double, int, 48, 16);
+  check_struct_and_union3(double, long double, long, 48, 16);
+  check_struct_and_union3(double, long double, long long, 48, 16);
+  check_struct_and_union3(double, long double, float, 48, 16);
+  check_struct_and_union3(double, long double, double, 48, 16);
+  check_struct_and_union3(double, long double, long double, 48, 16);
+  check_struct_and_union3(long double, char, char, 32, 16);
+  check_struct_and_union3(long double, char, short, 32, 16);
+  check_struct_and_union3(long double, char, int, 32, 16);
+  check_struct_and_union3(long double, char, long, 32, 16);
+  check_struct_and_union3(long double, char, long long, 32, 16);
+  check_struct_and_union3(long double, char, float, 32, 16);
+  check_struct_and_union3(long double, char, double, 32, 16);
+  check_struct_and_union3(long double, char, long double, 48, 16);
+  check_struct_and_union3(long double, short, char, 32, 16);
+  check_struct_and_union3(long double, short, short, 32, 16);
+  check_struct_and_union3(long double, short, int, 32, 16);
+  check_struct_and_union3(long double, short, long, 32, 16);
+  check_struct_and_union3(long double, short, long long, 32, 16);
+  check_struct_and_union3(long double, short, float, 32, 16);
+  check_struct_and_union3(long double, short, double, 32, 16);
+  check_struct_and_union3(long double, short, long double, 48, 16);
+  check_struct_and_union3(long double, int, char, 32, 16);
+  check_struct_and_union3(long double, int, short, 32, 16);
+  check_struct_and_union3(long double, int, int, 32, 16);
+  check_struct_and_union3(long double, int, long, 32, 16);
+  check_struct_and_union3(long double, int, long long, 32, 16);
+  check_struct_and_union3(long double, int, float, 32, 16);
+  check_struct_and_union3(long double, int, double, 32, 16);
+  check_struct_and_union3(long double, int, long double, 48, 16);
+  check_struct_and_union3(long double, long, char, 32, 16);
+  check_struct_and_union3(long double, long, short, 32, 16);
+  check_struct_and_union3(long double, long, int, 32, 16);
+  check_struct_and_union3(long double, long, long, 32, 16);
+  check_struct_and_union3(long double, long, long long, 32, 16);
+  check_struct_and_union3(long double, long, float, 32, 16);
+  check_struct_and_union3(long double, long, double, 32, 16);
+  check_struct_and_union3(long double, long, long double, 48, 16);
+  check_struct_and_union3(long double, long long, char, 32, 16);
+  check_struct_and_union3(long double, long long, short, 32, 16);
+  check_struct_and_union3(long double, long long, int, 32, 16);
+  check_struct_and_union3(long double, long long, long, 32, 16);
+  check_struct_and_union3(long double, long long, long long, 32, 16);
+  check_struct_and_union3(long double, long long, float, 32, 16);
+  check_struct_and_union3(long double, long long, double, 32, 16);
+  check_struct_and_union3(long double, long long, long double, 48, 16);
+  check_struct_and_union3(long double, float, char, 32, 16);
+  check_struct_and_union3(long double, float, short, 32, 16);
+  check_struct_and_union3(long double, float, int, 32, 16);
+  check_struct_and_union3(long double, float, long, 32, 16);
+  check_struct_and_union3(long double, float, long long, 32, 16);
+  check_struct_and_union3(long double, float, float, 32, 16);
+  check_struct_and_union3(long double, float, double, 32, 16);
+  check_struct_and_union3(long double, float, long double, 48, 16);
+  check_struct_and_union3(long double, double, char, 32, 16);
+  check_struct_and_union3(long double, double, short, 32, 16);
+  check_struct_and_union3(long double, double, int, 32, 16);
+  check_struct_and_union3(long double, double, long, 32, 16);
+  check_struct_and_union3(long double, double, long long, 32, 16);
+  check_struct_and_union3(long double, double, float, 32, 16);
+  check_struct_and_union3(long double, double, double, 32, 16);
+  check_struct_and_union3(long double, double, long double, 48, 16);
+  check_struct_and_union3(long double, long double, char, 48, 16);
+  check_struct_and_union3(long double, long double, short, 48, 16);
+  check_struct_and_union3(long double, long double, int, 48, 16);
+  check_struct_and_union3(long double, long double, long, 48, 16);
+  check_struct_and_union3(long double, long double, long long, 48, 16);
+  check_struct_and_union3(long double, long double, float, 48, 16);
+  check_struct_and_union3(long double, long double, double, 48, 16);
+  check_struct_and_union3(long double, long double, long double, 48, 16);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_alignment.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_alignment.c
new file mode 100644
index 000000000..d3d57d788
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_alignment.c
@@ -0,0 +1,42 @@
+/* This checks alignment of basic types.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests2(check_align, char, TYPE_ALIGN_CHAR);
+  run_signed_tests2(check_align, short, TYPE_ALIGN_SHORT);
+  run_signed_tests2(check_align, int, TYPE_ALIGN_INT);
+  run_signed_tests2(check_align, long, TYPE_ALIGN_LONG);
+  run_signed_tests2(check_align, long long, TYPE_ALIGN_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests2(check_align, __int128, TYPE_ALIGN_INT128);
+#endif
+  check_align(enumtype, TYPE_ALIGN_ENUM);
+
+  /* Floating point types.  */
+  check_align(float, TYPE_ALIGN_FLOAT);
+  check_align(double, TYPE_ALIGN_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_align(long double, TYPE_ALIGN_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_align(__float128, TYPE_ALIGN_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_align(__m64, TYPE_ALIGN_M64);
+  check_align(__m128, TYPE_ALIGN_M128);
+#endif
+
+  /* Pointer types.  */
+  check_align(void *, TYPE_ALIGN_POINTER);
+  check_align(void (*)(), TYPE_ALIGN_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_array_size_and_align.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_array_size_and_align.c
new file mode 100644
index 000000000..09c737f05
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_array_size_and_align.c
@@ -0,0 +1,41 @@
+/* This checks .  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests3(check_array_size_and_align, char, TYPE_SIZE_CHAR, TYPE_ALIGN_CHAR);
+  run_signed_tests3(check_array_size_and_align, short, TYPE_SIZE_SHORT, TYPE_ALIGN_SHORT);
+  run_signed_tests3(check_array_size_and_align, int, TYPE_SIZE_INT, TYPE_ALIGN_INT);
+  run_signed_tests3(check_array_size_and_align, long, TYPE_SIZE_LONG, TYPE_ALIGN_LONG);
+  run_signed_tests3(check_array_size_and_align, long long, TYPE_SIZE_LONG_LONG, TYPE_ALIGN_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests3(check_array_size_and_align, __int128, TYPE_SIZE_INT128, TYPE_ALIGN_INT128);
+#endif
+  check_array_size_and_align(enum dummytype, TYPE_SIZE_ENUM, TYPE_ALIGN_ENUM);
+
+  /* Floating point types.  */
+  check_array_size_and_align(float, TYPE_SIZE_FLOAT, TYPE_ALIGN_FLOAT);
+  check_array_size_and_align(double, TYPE_SIZE_DOUBLE, TYPE_ALIGN_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_array_size_and_align(long double, TYPE_SIZE_LONG_DOUBLE, TYPE_ALIGN_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_array_size_and_align(__float128, TYPE_SIZE_FLOAT128, TYPE_ALIGN_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_array_size_and_align(__m64, TYPE_SIZE_M64, TYPE_ALIGN_M64);
+  check_array_size_and_align(__m128, TYPE_SIZE_M128, TYPE_ALIGN_M128);
+#endif
+
+  /* Pointer types. The function pointer doesn't work with these macros.  */
+  check_array_size_and_align(void *, TYPE_SIZE_POINTER, TYPE_ALIGN_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_returning.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_returning.c
new file mode 100644
index 000000000..92c906fc8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_returning.c
@@ -0,0 +1,78 @@
+/* This is an autogenerated file. Do not edit.  */
+
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+char
+fun_test_returning_char (void)
+{
+  volatile_var++;
+  return 64;
+}
+
+short
+fun_test_returning_short (void)
+{
+  volatile_var++;
+  return 65;
+}
+
+int
+fun_test_returning_int (void)
+{
+  volatile_var++;
+  return 66;
+}
+
+long
+fun_test_returning_long (void)
+{
+  volatile_var++;
+  return 67;
+}
+
+long long
+fun_test_returning_long_long (void)
+{
+  volatile_var++;
+  return 68;
+}
+
+float
+fun_test_returning_float (void)
+{
+  volatile_var++;
+  return 69;
+}
+
+double
+fun_test_returning_double (void)
+{
+  volatile_var++;
+  return 70;
+}
+
+long double
+fun_test_returning_long_double (void)
+{
+  volatile_var++;
+  return 71;
+}
+
+#define def_test_returning_type_xmm(fun, type, ret, reg) \
+  { type var = WRAP_RET (fun) (); \
+  assert (ret == (type) reg && ret == var); }
+int
+main (void)
+{
+  def_test_returning_type_xmm(fun_test_returning_char, char, 64, rax);
+  def_test_returning_type_xmm(fun_test_returning_short, short, 65, rax);
+  def_test_returning_type_xmm(fun_test_returning_int, int, 66, rax);
+  def_test_returning_type_xmm(fun_test_returning_long, long, 67, rax);
+  def_test_returning_type_xmm(fun_test_returning_long_long, long long, 68, rax);
+  def_test_returning_type_xmm(fun_test_returning_float, float, 69, xmm_regs[0]._float[0]);
+  def_test_returning_type_xmm(fun_test_returning_double, double, 70, xmm_regs[0]._double[0]);
+  def_test_returning_type_xmm(fun_test_returning_long_double, long double, 71, x87_regs[0]._ldouble);
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_sizes.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_sizes.c
new file mode 100644
index 000000000..74427c694
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_sizes.c
@@ -0,0 +1,42 @@
+/* This checks sizes of basic types.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests2(check_size, char, TYPE_SIZE_CHAR);
+  run_signed_tests2(check_size, short, TYPE_SIZE_SHORT);
+  run_signed_tests2(check_size, int, TYPE_SIZE_INT);
+  run_signed_tests2(check_size, long, TYPE_SIZE_LONG);
+  run_signed_tests2(check_size, long long, TYPE_SIZE_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests2(check_size, __int128, TYPE_SIZE_INT128);
+#endif
+  check_size(enumtype, TYPE_SIZE_ENUM);
+
+  /* Floating point types.  */
+  check_size(float, TYPE_SIZE_FLOAT);
+  check_size(double, TYPE_SIZE_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_size(long double, TYPE_SIZE_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_size(__float128, TYPE_SIZE_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_size(__m64, TYPE_SIZE_M64);
+  check_size(__m128, TYPE_SIZE_M128);
+#endif
+
+  /* Pointer types.  */
+  check_size(void *, TYPE_SIZE_POINTER);
+  check_size(void (*)(), TYPE_SIZE_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_struct_size_and_align.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_struct_size_and_align.c
new file mode 100644
index 000000000..783da6ff5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_struct_size_and_align.c
@@ -0,0 +1,42 @@
+/* This checks size and alignment of structs with a single basic type
+   element. All basic types are checked.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests3(check_basic_struct_size_and_align, char, TYPE_SIZE_CHAR, TYPE_ALIGN_CHAR);
+  run_signed_tests3(check_basic_struct_size_and_align, short, TYPE_SIZE_SHORT, TYPE_ALIGN_SHORT);
+  run_signed_tests3(check_basic_struct_size_and_align, int, TYPE_SIZE_INT, TYPE_ALIGN_INT);
+  run_signed_tests3(check_basic_struct_size_and_align, long, TYPE_SIZE_LONG, TYPE_ALIGN_LONG);
+  run_signed_tests3(check_basic_struct_size_and_align, long long, TYPE_SIZE_LONG_LONG, TYPE_ALIGN_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests3(check_basic_struct_size_and_align, __int128, TYPE_SIZE_INT128, TYPE_ALIGN_INT128);
+#endif
+  check_basic_struct_size_and_align(enum dummytype, TYPE_SIZE_ENUM, TYPE_ALIGN_ENUM);
+
+  /* Floating point types.  */
+  check_basic_struct_size_and_align(float, TYPE_SIZE_FLOAT, TYPE_ALIGN_FLOAT);
+  check_basic_struct_size_and_align(double, TYPE_SIZE_DOUBLE, TYPE_ALIGN_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_basic_struct_size_and_align(long double, TYPE_SIZE_LONG_DOUBLE, TYPE_ALIGN_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_basic_struct_size_and_align(__float128, TYPE_SIZE_FLOAT128, TYPE_ALIGN_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_basic_struct_size_and_align(__m64, TYPE_SIZE_M64, TYPE_ALIGN_M64);
+  check_basic_struct_size_and_align(__m128, TYPE_SIZE_M128, TYPE_ALIGN_M128);
+#endif
+
+  /* Pointer types. The function pointer doesn't work with these macros.  */
+  check_basic_struct_size_and_align(void *, TYPE_SIZE_POINTER, TYPE_ALIGN_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_union_size_and_align.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_union_size_and_align.c
new file mode 100644
index 000000000..a5a51f290
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_basic_union_size_and_align.c
@@ -0,0 +1,41 @@
+/* Test of simple unions, size and alignment.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+int
+main (void)
+{
+  /* Integral types.  */
+  run_signed_tests3(check_basic_union_size_and_align, char, TYPE_SIZE_CHAR, TYPE_ALIGN_CHAR);
+  run_signed_tests3(check_basic_union_size_and_align, short, TYPE_SIZE_SHORT, TYPE_ALIGN_SHORT);
+  run_signed_tests3(check_basic_union_size_and_align, int, TYPE_SIZE_INT, TYPE_ALIGN_INT);
+  run_signed_tests3(check_basic_union_size_and_align, long, TYPE_SIZE_LONG, TYPE_ALIGN_LONG);
+  run_signed_tests3(check_basic_union_size_and_align, long long, TYPE_SIZE_LONG_LONG, TYPE_ALIGN_LONG_LONG);
+#ifdef CHECK_INT128
+  run_signed_tests3(check_basic_union_size_and_align, __int128, TYPE_SIZE_INT128, TYPE_ALIGN_INT128);
+#endif
+  check_basic_union_size_and_align(enum dummytype, TYPE_SIZE_ENUM, TYPE_ALIGN_ENUM);
+
+  /* Floating point types.  */
+  check_basic_union_size_and_align(float, TYPE_SIZE_FLOAT, TYPE_ALIGN_FLOAT);
+  check_basic_union_size_and_align(double, TYPE_SIZE_DOUBLE, TYPE_ALIGN_DOUBLE);
+#ifdef CHECK_LONG_DOUBLE
+  check_basic_union_size_and_align(long double, TYPE_SIZE_LONG_DOUBLE, TYPE_ALIGN_LONG_DOUBLE);
+#endif
+#ifdef CHECK_FLOAT128
+  check_basic_union_size_and_align(__float128, TYPE_SIZE_FLOAT128, TYPE_ALIGN_FLOAT128);
+#endif
+
+  /* Packed types - MMX, 3DNow!, SSE and SSE2.  */
+#ifdef CHECK_M64_M128
+  check_basic_union_size_and_align(__m64, TYPE_SIZE_M64, TYPE_ALIGN_M64);
+  check_basic_union_size_and_align(__m128, TYPE_SIZE_M128, TYPE_ALIGN_M128);
+#endif
+
+  /* Pointer types. The function pointer doesn't work with these macros.  */
+  check_basic_union_size_and_align(void *, TYPE_SIZE_POINTER, TYPE_ALIGN_POINTER);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_bitfields.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_bitfields.c
new file mode 100644
index 000000000..27ab1c6aa
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_bitfields.c
@@ -0,0 +1,162 @@
+/* This is a small test to see if bitfields are working.  It is only a
+   few structs and a union and a test to see if they have the correct
+   size, if values can be read and written and a couple of argument
+   passing tests.  No alignment testing is done.  */
+
+#include "defines.h"
+#include "macros.h"
+
+
+/* These five bitfields are taken from the System V ABI, Intel 386
+   architecture supplement.  */
+
+/* Word aligned, sizeof is 4.  */
+struct RightToLeft
+{
+  int j:5;
+  int k:6;
+  int m:7;
+};
+
+/* Word aligned, sizeof is 12.  */
+struct BoundaryAlignment
+{
+  short s:9;
+  int   j:9;
+  char  c;
+  short t:9;
+  short u:9;
+  char  d;
+};
+
+/* Halfword aligned, sizeof is 2.  */
+struct StorageUnitSharing
+{
+  char  c;
+  short s:8;
+};
+
+/* Halfword aligned, sizeof is 2.  */
+union Allocation
+{
+  char  c;
+  short s:8;
+};
+
+/* Byte aligned, sizeof is 9.  */
+struct Unnamed
+{
+  char  c;
+  int    :0;
+  char  d;
+  short  :9;
+  char  e;
+  char   :0;
+};
+
+/* Extra struct testing bitfields in larger types.
+   Doubleword aligned, sizeof is 8.  */
+struct LargerTypes
+{
+  long long l:33;
+  int       i:31;
+};
+
+
+void
+passing1 (struct RightToLeft str, int j, int k, int m)
+{
+  assert (str.j == j);
+  assert (str.k == k);
+  assert (str.m == m);
+}
+
+void
+passing2 (struct BoundaryAlignment str, short s, int j, char c, short t,
+	  short u, char d)
+{
+  assert (str.s == s);
+  assert (str.j == j);
+  assert (str.c == c);
+  assert (str.t == t);
+  assert (str.u == u);
+  assert (str.d == d);
+}
+
+void
+passing3 (struct StorageUnitSharing str, char c, short s)
+{
+  assert (str.c == c);
+  assert (str.s == s);
+}
+
+void
+passing4 (struct Unnamed str, char c, char d, char e)
+{
+  assert (str.c == c);
+  assert (str.d == d);
+  assert (str.e == e);
+}
+
+void
+passing5 (struct LargerTypes str, long long l, int i)
+{
+  assert (str.l == l);
+  assert (str.i == i);
+}
+
+
+void
+passingU (union Allocation u, char c)
+{
+  assert (u.c == c);
+  assert (u.s == c);
+}
+
+
+int
+main (void)
+{
+  struct RightToLeft str1;
+  struct BoundaryAlignment str2;
+  struct StorageUnitSharing str3;
+  struct Unnamed str4;
+  struct LargerTypes str5;
+  union Allocation u;
+
+  /* Check sizeof's.  */
+  check_size(str1, 4);
+  check_size(str2, 12);
+  check_size(str3, 2);
+  check_size(str4, 9);
+  check_size(str5, 8);
+  check_size(u, 2);
+
+  /* Check alignof's.  */
+  check_align_lv(str1, 4);
+  check_align_lv(str2, 4);
+  check_align_lv(str3, 2);
+  check_align_lv(str4, 1);
+  check_align_lv(str5, 8);
+  check_align_lv(u, 2);
+
+  /* Check passing.  */
+  str1.j = str2.s = str3.c = str4.c = str5.l = 4;
+  str1.k = str2.j = str3.s = str4.d = str5.i = 5;
+  str1.m = str2.c = str4.e = 6;
+  str2.t = 7;
+  str2.u = 8;
+  str2.d = 9;
+  passing1 (str1, 4, 5, 6);
+  passing2 (str2, 4, 5, 6, 7, 8, 9);
+  passing3 (str3, 4, 5);
+  passing4 (str4, 4, 5, 6);
+  passing5 (str5, 4, 5);
+
+  u.c = 5;
+  passingU (u, 5);
+  u.s = 6;
+  passingU (u, 6);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_complex_returning.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_complex_returning.c
new file mode 100644
index 000000000..9e9678d7b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_complex_returning.c
@@ -0,0 +1,83 @@
+/* This is a small test case for returning a complex number. Written by
+   Andreas Jaeger.  */
+
+#include "defines.h"
+
+
+#define BUILD_F_COMPLEX(real, imag) \
+  ({ __complex__ float __retval; \
+     __real__ __retval = (real); \
+     __imag__ __retval = (imag); \
+     __retval; })
+
+#define BUILD_D_COMPLEX(real, imag) \
+  ({ __complex__ double __retval; \
+     __real__ __retval = (real); \
+     __imag__ __retval = (imag); \
+     __retval; })
+
+#define BUILD_LD_COMPLEX(real, imag) \
+  ({ __complex__ long double __retval; \
+     __real__ __retval = (real); \
+     __imag__ __retval = (imag); \
+     __retval; })
+
+__complex__ float
+aj_f_times2 (__complex__ float x)
+{
+  __complex__ float res;
+
+  __real__ res = (2.0 * __real__ x);
+  __imag__ res = (2.0 * __imag__ x);
+
+  return res;
+}
+
+__complex__ double
+aj_d_times2 (__complex__ double x)
+{
+  __complex__ double res;
+
+  __real__ res = (2.0 * __real__ x);
+  __imag__ res = (2.0 * __imag__ x);
+
+  return res;
+}
+
+__complex__ long double
+aj_ld_times2 (__complex__ long double x)
+{
+  __complex__ long double res;
+
+  __real__ res = (2.0 * __real__ x);
+  __imag__ res = (2.0 * __imag__ x);
+
+  return res;
+}
+
+int
+main (void)
+{
+#ifdef CHECK_COMPLEX
+  _Complex float fc, fd;
+  _Complex double dc, dd;
+  _Complex long double ldc, ldd;
+
+  fc = BUILD_LD_COMPLEX (2.0f, 3.0f);
+  fd = aj_f_times2 (fc);
+
+  assert (__real__ fd == 4.0f && __imag__ fd == 6.0f);
+
+  dc = BUILD_LD_COMPLEX (2.0, 3.0);
+  dd = aj_ld_times2 (dc);
+
+  assert (__real__ dd == 4.0 && __imag__ dd == 6.0);
+
+  ldc = BUILD_LD_COMPLEX (2.0L, 3.0L);
+  ldd = aj_ld_times2 (ldc);
+
+  assert (__real__ ldd == 4.0L && __imag__ ldd == 6.0L);
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_m64m128_returning.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_m64m128_returning.c
new file mode 100644
index 000000000..cde034693
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_m64m128_returning.c
@@ -0,0 +1,54 @@
+#include <stdio.h>
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+__m64
+fun_test_returning___m64 (void)
+{
+  volatile_var++;
+  return (__m64){72,0};
+}
+
+__m128
+fun_test_returning___m128 (void)
+{
+  volatile_var++;
+  return (__m128){73,0,0,0};
+}
+
+__m64 test_64;
+__m128 test_128;
+
+int
+main (void)
+{
+  unsigned failed = 0;
+  XMM_T xmmt1, xmmt2;
+
+  /* We jump through hoops to compare the results as gcc 3.3 does throw
+     an ICE when trying to generate a compare for a == b, when a and b
+     are of __m64 or __m128 type :-(  */
+  clear_struct_registers;
+  test_64 = (__m64){72,0};
+  xmmt1._m64[0] = test_64;
+  xmmt2._m64[0] = WRAP_RET (fun_test_returning___m64)();
+  if (xmmt1._long[0] != xmmt2._long[0]
+      || xmmt1._long[0] != xmm_regs[0]._long[0])
+    printf ("fail m64\n"), failed++;
+
+  clear_struct_registers;
+  test_128 = (__m128){73,0};
+  xmmt1._m128[0] = test_128;
+  xmmt2._m128[0] = WRAP_RET (fun_test_returning___m128)();
+  if (xmmt1._long[0] != xmmt2._long[0]
+      || xmmt1._long[0] != xmm_regs[0]._long[0])
+    printf ("fail m128\n"), failed++;
+  if (failed)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_floats.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_floats.c
new file mode 100644
index 000000000..42fff97b0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_floats.c
@@ -0,0 +1,502 @@
+/* This is an autogenerated file. Do not edit.  */
+
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct 
+{
+  float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23;
+} values_float;
+
+struct 
+{
+  double f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23;
+} values_double;
+
+struct 
+{
+  ldouble f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23;
+} values_ldouble;
+
+void
+fun_check_float_passing_float8_values (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_float.f0 == f0);
+  assert (values_float.f1 == f1);
+  assert (values_float.f2 == f2);
+  assert (values_float.f3 == f3);
+  assert (values_float.f4 == f4);
+  assert (values_float.f5 == f5);
+  assert (values_float.f6 == f6);
+  assert (values_float.f7 == f7);
+
+}
+
+void
+fun_check_float_passing_float8_regs (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_float_arguments;
+}
+
+void
+fun_check_float_passing_float16_values (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED, float f8 ATTRIBUTE_UNUSED, float f9 ATTRIBUTE_UNUSED, float f10 ATTRIBUTE_UNUSED, float f11 ATTRIBUTE_UNUSED, float f12 ATTRIBUTE_UNUSED, float f13 ATTRIBUTE_UNUSED, float f14 ATTRIBUTE_UNUSED, float f15 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_float.f0 == f0);
+  assert (values_float.f1 == f1);
+  assert (values_float.f2 == f2);
+  assert (values_float.f3 == f3);
+  assert (values_float.f4 == f4);
+  assert (values_float.f5 == f5);
+  assert (values_float.f6 == f6);
+  assert (values_float.f7 == f7);
+  assert (values_float.f8 == f8);
+  assert (values_float.f9 == f9);
+  assert (values_float.f10 == f10);
+  assert (values_float.f11 == f11);
+  assert (values_float.f12 == f12);
+  assert (values_float.f13 == f13);
+  assert (values_float.f14 == f14);
+  assert (values_float.f15 == f15);
+
+}
+
+void
+fun_check_float_passing_float16_regs (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED, float f8 ATTRIBUTE_UNUSED, float f9 ATTRIBUTE_UNUSED, float f10 ATTRIBUTE_UNUSED, float f11 ATTRIBUTE_UNUSED, float f12 ATTRIBUTE_UNUSED, float f13 ATTRIBUTE_UNUSED, float f14 ATTRIBUTE_UNUSED, float f15 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_float_arguments;
+}
+
+void
+fun_check_float_passing_float20_values (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED, float f8 ATTRIBUTE_UNUSED, float f9 ATTRIBUTE_UNUSED, float f10 ATTRIBUTE_UNUSED, float f11 ATTRIBUTE_UNUSED, float f12 ATTRIBUTE_UNUSED, float f13 ATTRIBUTE_UNUSED, float f14 ATTRIBUTE_UNUSED, float f15 ATTRIBUTE_UNUSED, float f16 ATTRIBUTE_UNUSED, float f17 ATTRIBUTE_UNUSED, float f18 ATTRIBUTE_UNUSED, float f19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_float.f0 == f0);
+  assert (values_float.f1 == f1);
+  assert (values_float.f2 == f2);
+  assert (values_float.f3 == f3);
+  assert (values_float.f4 == f4);
+  assert (values_float.f5 == f5);
+  assert (values_float.f6 == f6);
+  assert (values_float.f7 == f7);
+  assert (values_float.f8 == f8);
+  assert (values_float.f9 == f9);
+  assert (values_float.f10 == f10);
+  assert (values_float.f11 == f11);
+  assert (values_float.f12 == f12);
+  assert (values_float.f13 == f13);
+  assert (values_float.f14 == f14);
+  assert (values_float.f15 == f15);
+  assert (values_float.f16 == f16);
+  assert (values_float.f17 == f17);
+  assert (values_float.f18 == f18);
+  assert (values_float.f19 == f19);
+
+}
+
+void
+fun_check_float_passing_float20_regs (float f0 ATTRIBUTE_UNUSED, float f1 ATTRIBUTE_UNUSED, float f2 ATTRIBUTE_UNUSED, float f3 ATTRIBUTE_UNUSED, float f4 ATTRIBUTE_UNUSED, float f5 ATTRIBUTE_UNUSED, float f6 ATTRIBUTE_UNUSED, float f7 ATTRIBUTE_UNUSED, float f8 ATTRIBUTE_UNUSED, float f9 ATTRIBUTE_UNUSED, float f10 ATTRIBUTE_UNUSED, float f11 ATTRIBUTE_UNUSED, float f12 ATTRIBUTE_UNUSED, float f13 ATTRIBUTE_UNUSED, float f14 ATTRIBUTE_UNUSED, float f15 ATTRIBUTE_UNUSED, float f16 ATTRIBUTE_UNUSED, float f17 ATTRIBUTE_UNUSED, float f18 ATTRIBUTE_UNUSED, float f19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_float_arguments;
+}
+
+void
+fun_check_float_passing_double8_values (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_double.f0 == f0);
+  assert (values_double.f1 == f1);
+  assert (values_double.f2 == f2);
+  assert (values_double.f3 == f3);
+  assert (values_double.f4 == f4);
+  assert (values_double.f5 == f5);
+  assert (values_double.f6 == f6);
+  assert (values_double.f7 == f7);
+
+}
+
+void
+fun_check_float_passing_double8_regs (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_double_arguments;
+}
+
+void
+fun_check_float_passing_double16_values (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED, double f8 ATTRIBUTE_UNUSED, double f9 ATTRIBUTE_UNUSED, double f10 ATTRIBUTE_UNUSED, double f11 ATTRIBUTE_UNUSED, double f12 ATTRIBUTE_UNUSED, double f13 ATTRIBUTE_UNUSED, double f14 ATTRIBUTE_UNUSED, double f15 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_double.f0 == f0);
+  assert (values_double.f1 == f1);
+  assert (values_double.f2 == f2);
+  assert (values_double.f3 == f3);
+  assert (values_double.f4 == f4);
+  assert (values_double.f5 == f5);
+  assert (values_double.f6 == f6);
+  assert (values_double.f7 == f7);
+  assert (values_double.f8 == f8);
+  assert (values_double.f9 == f9);
+  assert (values_double.f10 == f10);
+  assert (values_double.f11 == f11);
+  assert (values_double.f12 == f12);
+  assert (values_double.f13 == f13);
+  assert (values_double.f14 == f14);
+  assert (values_double.f15 == f15);
+
+}
+
+void
+fun_check_float_passing_double16_regs (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED, double f8 ATTRIBUTE_UNUSED, double f9 ATTRIBUTE_UNUSED, double f10 ATTRIBUTE_UNUSED, double f11 ATTRIBUTE_UNUSED, double f12 ATTRIBUTE_UNUSED, double f13 ATTRIBUTE_UNUSED, double f14 ATTRIBUTE_UNUSED, double f15 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_double_arguments;
+}
+
+void
+fun_check_float_passing_double20_values (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED, double f8 ATTRIBUTE_UNUSED, double f9 ATTRIBUTE_UNUSED, double f10 ATTRIBUTE_UNUSED, double f11 ATTRIBUTE_UNUSED, double f12 ATTRIBUTE_UNUSED, double f13 ATTRIBUTE_UNUSED, double f14 ATTRIBUTE_UNUSED, double f15 ATTRIBUTE_UNUSED, double f16 ATTRIBUTE_UNUSED, double f17 ATTRIBUTE_UNUSED, double f18 ATTRIBUTE_UNUSED, double f19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_double.f0 == f0);
+  assert (values_double.f1 == f1);
+  assert (values_double.f2 == f2);
+  assert (values_double.f3 == f3);
+  assert (values_double.f4 == f4);
+  assert (values_double.f5 == f5);
+  assert (values_double.f6 == f6);
+  assert (values_double.f7 == f7);
+  assert (values_double.f8 == f8);
+  assert (values_double.f9 == f9);
+  assert (values_double.f10 == f10);
+  assert (values_double.f11 == f11);
+  assert (values_double.f12 == f12);
+  assert (values_double.f13 == f13);
+  assert (values_double.f14 == f14);
+  assert (values_double.f15 == f15);
+  assert (values_double.f16 == f16);
+  assert (values_double.f17 == f17);
+  assert (values_double.f18 == f18);
+  assert (values_double.f19 == f19);
+
+}
+
+void
+fun_check_float_passing_double20_regs (double f0 ATTRIBUTE_UNUSED, double f1 ATTRIBUTE_UNUSED, double f2 ATTRIBUTE_UNUSED, double f3 ATTRIBUTE_UNUSED, double f4 ATTRIBUTE_UNUSED, double f5 ATTRIBUTE_UNUSED, double f6 ATTRIBUTE_UNUSED, double f7 ATTRIBUTE_UNUSED, double f8 ATTRIBUTE_UNUSED, double f9 ATTRIBUTE_UNUSED, double f10 ATTRIBUTE_UNUSED, double f11 ATTRIBUTE_UNUSED, double f12 ATTRIBUTE_UNUSED, double f13 ATTRIBUTE_UNUSED, double f14 ATTRIBUTE_UNUSED, double f15 ATTRIBUTE_UNUSED, double f16 ATTRIBUTE_UNUSED, double f17 ATTRIBUTE_UNUSED, double f18 ATTRIBUTE_UNUSED, double f19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_double_arguments;
+}
+
+void
+fun_check_x87_passing_ldouble8_values (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_ldouble.f0 == f0);
+  assert (values_ldouble.f1 == f1);
+  assert (values_ldouble.f2 == f2);
+  assert (values_ldouble.f3 == f3);
+  assert (values_ldouble.f4 == f4);
+  assert (values_ldouble.f5 == f5);
+  assert (values_ldouble.f6 == f6);
+  assert (values_ldouble.f7 == f7);
+
+}
+
+void
+fun_check_x87_passing_ldouble8_regs (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_ldouble_arguments;
+}
+
+void
+fun_check_x87_passing_ldouble16_values (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED, ldouble f8 ATTRIBUTE_UNUSED, ldouble f9 ATTRIBUTE_UNUSED, ldouble f10 ATTRIBUTE_UNUSED, ldouble f11 ATTRIBUTE_UNUSED, ldouble f12 ATTRIBUTE_UNUSED, ldouble f13 ATTRIBUTE_UNUSED, ldouble f14 ATTRIBUTE_UNUSED, ldouble f15 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_ldouble.f0 == f0);
+  assert (values_ldouble.f1 == f1);
+  assert (values_ldouble.f2 == f2);
+  assert (values_ldouble.f3 == f3);
+  assert (values_ldouble.f4 == f4);
+  assert (values_ldouble.f5 == f5);
+  assert (values_ldouble.f6 == f6);
+  assert (values_ldouble.f7 == f7);
+  assert (values_ldouble.f8 == f8);
+  assert (values_ldouble.f9 == f9);
+  assert (values_ldouble.f10 == f10);
+  assert (values_ldouble.f11 == f11);
+  assert (values_ldouble.f12 == f12);
+  assert (values_ldouble.f13 == f13);
+  assert (values_ldouble.f14 == f14);
+  assert (values_ldouble.f15 == f15);
+
+}
+
+void
+fun_check_x87_passing_ldouble16_regs (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED, ldouble f8 ATTRIBUTE_UNUSED, ldouble f9 ATTRIBUTE_UNUSED, ldouble f10 ATTRIBUTE_UNUSED, ldouble f11 ATTRIBUTE_UNUSED, ldouble f12 ATTRIBUTE_UNUSED, ldouble f13 ATTRIBUTE_UNUSED, ldouble f14 ATTRIBUTE_UNUSED, ldouble f15 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_ldouble_arguments;
+}
+
+void
+fun_check_x87_passing_ldouble20_values (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED, ldouble f8 ATTRIBUTE_UNUSED, ldouble f9 ATTRIBUTE_UNUSED, ldouble f10 ATTRIBUTE_UNUSED, ldouble f11 ATTRIBUTE_UNUSED, ldouble f12 ATTRIBUTE_UNUSED, ldouble f13 ATTRIBUTE_UNUSED, ldouble f14 ATTRIBUTE_UNUSED, ldouble f15 ATTRIBUTE_UNUSED, ldouble f16 ATTRIBUTE_UNUSED, ldouble f17 ATTRIBUTE_UNUSED, ldouble f18 ATTRIBUTE_UNUSED, ldouble f19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_ldouble.f0 == f0);
+  assert (values_ldouble.f1 == f1);
+  assert (values_ldouble.f2 == f2);
+  assert (values_ldouble.f3 == f3);
+  assert (values_ldouble.f4 == f4);
+  assert (values_ldouble.f5 == f5);
+  assert (values_ldouble.f6 == f6);
+  assert (values_ldouble.f7 == f7);
+  assert (values_ldouble.f8 == f8);
+  assert (values_ldouble.f9 == f9);
+  assert (values_ldouble.f10 == f10);
+  assert (values_ldouble.f11 == f11);
+  assert (values_ldouble.f12 == f12);
+  assert (values_ldouble.f13 == f13);
+  assert (values_ldouble.f14 == f14);
+  assert (values_ldouble.f15 == f15);
+  assert (values_ldouble.f16 == f16);
+  assert (values_ldouble.f17 == f17);
+  assert (values_ldouble.f18 == f18);
+  assert (values_ldouble.f19 == f19);
+
+}
+
+void
+fun_check_x87_passing_ldouble20_regs (ldouble f0 ATTRIBUTE_UNUSED, ldouble f1 ATTRIBUTE_UNUSED, ldouble f2 ATTRIBUTE_UNUSED, ldouble f3 ATTRIBUTE_UNUSED, ldouble f4 ATTRIBUTE_UNUSED, ldouble f5 ATTRIBUTE_UNUSED, ldouble f6 ATTRIBUTE_UNUSED, ldouble f7 ATTRIBUTE_UNUSED, ldouble f8 ATTRIBUTE_UNUSED, ldouble f9 ATTRIBUTE_UNUSED, ldouble f10 ATTRIBUTE_UNUSED, ldouble f11 ATTRIBUTE_UNUSED, ldouble f12 ATTRIBUTE_UNUSED, ldouble f13 ATTRIBUTE_UNUSED, ldouble f14 ATTRIBUTE_UNUSED, ldouble f15 ATTRIBUTE_UNUSED, ldouble f16 ATTRIBUTE_UNUSED, ldouble f17 ATTRIBUTE_UNUSED, ldouble f18 ATTRIBUTE_UNUSED, ldouble f19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_ldouble_arguments;
+}
+
+#define def_check_float_passing8(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7); \
+  \
+  clear_float_registers; \
+  fregs.F0._ ## TYPE [0] = _f0; \
+  fregs.F1._ ## TYPE [0] = _f1; \
+  fregs.F2._ ## TYPE [0] = _f2; \
+  fregs.F3._ ## TYPE [0] = _f3; \
+  fregs.F4._ ## TYPE [0] = _f4; \
+  fregs.F5._ ## TYPE [0] = _f5; \
+  fregs.F6._ ## TYPE [0] = _f6; \
+  fregs.F7._ ## TYPE [0] = _f7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7);
+
+#define def_check_float_passing16(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  values_ ## TYPE .f8 = _f8; \
+  values_ ## TYPE .f9 = _f9; \
+  values_ ## TYPE .f10 = _f10; \
+  values_ ## TYPE .f11 = _f11; \
+  values_ ## TYPE .f12 = _f12; \
+  values_ ## TYPE .f13 = _f13; \
+  values_ ## TYPE .f14 = _f14; \
+  values_ ## TYPE .f15 = _f15; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15); \
+  \
+  clear_float_registers; \
+  fregs.F0._ ## TYPE [0] = _f0; \
+  fregs.F1._ ## TYPE [0] = _f1; \
+  fregs.F2._ ## TYPE [0] = _f2; \
+  fregs.F3._ ## TYPE [0] = _f3; \
+  fregs.F4._ ## TYPE [0] = _f4; \
+  fregs.F5._ ## TYPE [0] = _f5; \
+  fregs.F6._ ## TYPE [0] = _f6; \
+  fregs.F7._ ## TYPE [0] = _f7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15);
+
+#define def_check_float_passing20(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  values_ ## TYPE .f8 = _f8; \
+  values_ ## TYPE .f9 = _f9; \
+  values_ ## TYPE .f10 = _f10; \
+  values_ ## TYPE .f11 = _f11; \
+  values_ ## TYPE .f12 = _f12; \
+  values_ ## TYPE .f13 = _f13; \
+  values_ ## TYPE .f14 = _f14; \
+  values_ ## TYPE .f15 = _f15; \
+  values_ ## TYPE .f16 = _f16; \
+  values_ ## TYPE .f17 = _f17; \
+  values_ ## TYPE .f18 = _f18; \
+  values_ ## TYPE .f19 = _f19; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19); \
+  \
+  clear_float_registers; \
+  fregs.F0._ ## TYPE [0] = _f0; \
+  fregs.F1._ ## TYPE [0] = _f1; \
+  fregs.F2._ ## TYPE [0] = _f2; \
+  fregs.F3._ ## TYPE [0] = _f3; \
+  fregs.F4._ ## TYPE [0] = _f4; \
+  fregs.F5._ ## TYPE [0] = _f5; \
+  fregs.F6._ ## TYPE [0] = _f6; \
+  fregs.F7._ ## TYPE [0] = _f7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19);
+
+#define def_check_x87_passing8(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7); \
+  \
+  clear_x87_registers; \
+  num_fregs = 0; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7);
+
+#define def_check_x87_passing16(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  values_ ## TYPE .f8 = _f8; \
+  values_ ## TYPE .f9 = _f9; \
+  values_ ## TYPE .f10 = _f10; \
+  values_ ## TYPE .f11 = _f11; \
+  values_ ## TYPE .f12 = _f12; \
+  values_ ## TYPE .f13 = _f13; \
+  values_ ## TYPE .f14 = _f14; \
+  values_ ## TYPE .f15 = _f15; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15); \
+  \
+  clear_x87_registers; \
+  num_fregs = 0; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15);
+
+#define def_check_x87_passing20(_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19, _func1, _func2, TYPE) \
+  values_ ## TYPE .f0 = _f0; \
+  values_ ## TYPE .f1 = _f1; \
+  values_ ## TYPE .f2 = _f2; \
+  values_ ## TYPE .f3 = _f3; \
+  values_ ## TYPE .f4 = _f4; \
+  values_ ## TYPE .f5 = _f5; \
+  values_ ## TYPE .f6 = _f6; \
+  values_ ## TYPE .f7 = _f7; \
+  values_ ## TYPE .f8 = _f8; \
+  values_ ## TYPE .f9 = _f9; \
+  values_ ## TYPE .f10 = _f10; \
+  values_ ## TYPE .f11 = _f11; \
+  values_ ## TYPE .f12 = _f12; \
+  values_ ## TYPE .f13 = _f13; \
+  values_ ## TYPE .f14 = _f14; \
+  values_ ## TYPE .f15 = _f15; \
+  values_ ## TYPE .f16 = _f16; \
+  values_ ## TYPE .f17 = _f17; \
+  values_ ## TYPE .f18 = _f18; \
+  values_ ## TYPE .f19 = _f19; \
+  WRAP_CALL(_func1) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19); \
+  \
+  clear_x87_registers; \
+  num_fregs = 0; \
+  WRAP_CALL(_func2) (_f0, _f1, _f2, _f3, _f4, _f5, _f6, _f7, _f8, _f9, _f10, _f11, _f12, _f13, _f14, _f15, _f16, _f17, _f18, _f19);
+
+void
+test_floats_on_stack ()
+{
+  def_check_float_passing8(32, 33, 34, 35, 36, 37, 38, 39, fun_check_float_passing_float8_values, fun_check_float_passing_float8_regs, float);
+
+  def_check_float_passing16(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, fun_check_float_passing_float16_values, fun_check_float_passing_float16_regs, float);
+}
+
+void
+test_too_many_floats ()
+{
+  def_check_float_passing20(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, fun_check_float_passing_float20_values, fun_check_float_passing_float20_regs, float);
+}
+
+void
+test_doubles_on_stack ()
+{
+  def_check_float_passing8(32, 33, 34, 35, 36, 37, 38, 39, fun_check_float_passing_double8_values, fun_check_float_passing_double8_regs, double);
+
+  def_check_float_passing16(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, fun_check_float_passing_double16_values, fun_check_float_passing_double16_regs, double);
+}
+
+void
+test_too_many_doubles ()
+{
+  def_check_float_passing20(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, fun_check_float_passing_double20_values, fun_check_float_passing_double20_regs, double);
+}
+
+void
+test_long_doubles_on_stack ()
+{
+  def_check_x87_passing8(32, 33, 34, 35, 36, 37, 38, 39, fun_check_x87_passing_ldouble8_values, fun_check_x87_passing_ldouble8_regs, ldouble);
+}
+
+void
+test_too_many_long_doubles ()
+{
+  def_check_x87_passing20(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, fun_check_x87_passing_ldouble20_values, fun_check_x87_passing_ldouble20_regs, ldouble);
+}
+
+void
+test_float128s_on_stack ()
+{
+}
+
+void
+test_too_many_float128s ()
+{
+}
+
+
+int
+main (void)
+{
+  test_floats_on_stack ();
+  test_too_many_floats ();
+  test_doubles_on_stack ();
+  test_too_many_doubles ();
+  test_long_doubles_on_stack ();
+  test_too_many_long_doubles ();
+  test_float128s_on_stack ();
+  test_too_many_float128s ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_integers.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_integers.c
new file mode 100644
index 000000000..d0d0f1fd2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_integers.c
@@ -0,0 +1,203 @@
+/* This is an autogenerated file. Do not edit.  */
+
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct 
+{
+  int i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values_int;
+
+struct 
+{
+  long i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values_long;
+
+void
+fun_check_int_passing_int6_values (int i0 ATTRIBUTE_UNUSED, int i1 ATTRIBUTE_UNUSED, int i2 ATTRIBUTE_UNUSED, int i3 ATTRIBUTE_UNUSED, int i4 ATTRIBUTE_UNUSED, int i5 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_int.i0 == i0);
+  assert (values_int.i1 == i1);
+  assert (values_int.i2 == i2);
+  assert (values_int.i3 == i3);
+  assert (values_int.i4 == i4);
+  assert (values_int.i5 == i5);
+
+}
+
+void
+fun_check_int_passing_int6_regs (int i0 ATTRIBUTE_UNUSED, int i1 ATTRIBUTE_UNUSED, int i2 ATTRIBUTE_UNUSED, int i3 ATTRIBUTE_UNUSED, int i4 ATTRIBUTE_UNUSED, int i5 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_int_arguments;
+}
+
+void
+fun_check_int_passing_int12_values (int i0 ATTRIBUTE_UNUSED, int i1 ATTRIBUTE_UNUSED, int i2 ATTRIBUTE_UNUSED, int i3 ATTRIBUTE_UNUSED, int i4 ATTRIBUTE_UNUSED, int i5 ATTRIBUTE_UNUSED, int i6 ATTRIBUTE_UNUSED, int i7 ATTRIBUTE_UNUSED, int i8 ATTRIBUTE_UNUSED, int i9 ATTRIBUTE_UNUSED, int i10 ATTRIBUTE_UNUSED, int i11 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_int.i0 == i0);
+  assert (values_int.i1 == i1);
+  assert (values_int.i2 == i2);
+  assert (values_int.i3 == i3);
+  assert (values_int.i4 == i4);
+  assert (values_int.i5 == i5);
+  assert (values_int.i6 == i6);
+  assert (values_int.i7 == i7);
+  assert (values_int.i8 == i8);
+  assert (values_int.i9 == i9);
+  assert (values_int.i10 == i10);
+  assert (values_int.i11 == i11);
+
+}
+
+void
+fun_check_int_passing_int12_regs (int i0 ATTRIBUTE_UNUSED, int i1 ATTRIBUTE_UNUSED, int i2 ATTRIBUTE_UNUSED, int i3 ATTRIBUTE_UNUSED, int i4 ATTRIBUTE_UNUSED, int i5 ATTRIBUTE_UNUSED, int i6 ATTRIBUTE_UNUSED, int i7 ATTRIBUTE_UNUSED, int i8 ATTRIBUTE_UNUSED, int i9 ATTRIBUTE_UNUSED, int i10 ATTRIBUTE_UNUSED, int i11 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_int_arguments;
+}
+
+void
+fun_check_int_passing_long6_values (long i0 ATTRIBUTE_UNUSED, long i1 ATTRIBUTE_UNUSED, long i2 ATTRIBUTE_UNUSED, long i3 ATTRIBUTE_UNUSED, long i4 ATTRIBUTE_UNUSED, long i5 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_long.i0 == i0);
+  assert (values_long.i1 == i1);
+  assert (values_long.i2 == i2);
+  assert (values_long.i3 == i3);
+  assert (values_long.i4 == i4);
+  assert (values_long.i5 == i5);
+
+}
+
+void
+fun_check_int_passing_long6_regs (long i0 ATTRIBUTE_UNUSED, long i1 ATTRIBUTE_UNUSED, long i2 ATTRIBUTE_UNUSED, long i3 ATTRIBUTE_UNUSED, long i4 ATTRIBUTE_UNUSED, long i5 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_long_arguments;
+}
+
+void
+fun_check_int_passing_long12_values (long i0 ATTRIBUTE_UNUSED, long i1 ATTRIBUTE_UNUSED, long i2 ATTRIBUTE_UNUSED, long i3 ATTRIBUTE_UNUSED, long i4 ATTRIBUTE_UNUSED, long i5 ATTRIBUTE_UNUSED, long i6 ATTRIBUTE_UNUSED, long i7 ATTRIBUTE_UNUSED, long i8 ATTRIBUTE_UNUSED, long i9 ATTRIBUTE_UNUSED, long i10 ATTRIBUTE_UNUSED, long i11 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  assert (values_long.i0 == i0);
+  assert (values_long.i1 == i1);
+  assert (values_long.i2 == i2);
+  assert (values_long.i3 == i3);
+  assert (values_long.i4 == i4);
+  assert (values_long.i5 == i5);
+  assert (values_long.i6 == i6);
+  assert (values_long.i7 == i7);
+  assert (values_long.i8 == i8);
+  assert (values_long.i9 == i9);
+  assert (values_long.i10 == i10);
+  assert (values_long.i11 == i11);
+
+}
+
+void
+fun_check_int_passing_long12_regs (long i0 ATTRIBUTE_UNUSED, long i1 ATTRIBUTE_UNUSED, long i2 ATTRIBUTE_UNUSED, long i3 ATTRIBUTE_UNUSED, long i4 ATTRIBUTE_UNUSED, long i5 ATTRIBUTE_UNUSED, long i6 ATTRIBUTE_UNUSED, long i7 ATTRIBUTE_UNUSED, long i8 ATTRIBUTE_UNUSED, long i9 ATTRIBUTE_UNUSED, long i10 ATTRIBUTE_UNUSED, long i11 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_long_arguments;
+}
+
+#define def_check_int_passing6(_i0, _i1, _i2, _i3, _i4, _i5, _func1, _func2, TYPE) \
+  values_ ## TYPE .i0 = _i0; \
+  values_ ## TYPE .i1 = _i1; \
+  values_ ## TYPE .i2 = _i2; \
+  values_ ## TYPE .i3 = _i3; \
+  values_ ## TYPE .i4 = _i4; \
+  values_ ## TYPE .i5 = _i5; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5); \
+  \
+  clear_int_registers; \
+  iregs.I0 = _i0; \
+  iregs.I1 = _i1; \
+  iregs.I2 = _i2; \
+  iregs.I3 = _i3; \
+  iregs.I4 = _i4; \
+  iregs.I5 = _i5; \
+  num_iregs = 6; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5);
+
+#define def_check_int_passing12(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _func1, _func2, TYPE) \
+  values_ ## TYPE .i0 = _i0; \
+  values_ ## TYPE .i1 = _i1; \
+  values_ ## TYPE .i2 = _i2; \
+  values_ ## TYPE .i3 = _i3; \
+  values_ ## TYPE .i4 = _i4; \
+  values_ ## TYPE .i5 = _i5; \
+  values_ ## TYPE .i6 = _i6; \
+  values_ ## TYPE .i7 = _i7; \
+  values_ ## TYPE .i8 = _i8; \
+  values_ ## TYPE .i9 = _i9; \
+  values_ ## TYPE .i10 = _i10; \
+  values_ ## TYPE .i11 = _i11; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11); \
+  \
+  clear_int_registers; \
+  iregs.I0 = _i0; \
+  iregs.I1 = _i1; \
+  iregs.I2 = _i2; \
+  iregs.I3 = _i3; \
+  iregs.I4 = _i4; \
+  iregs.I5 = _i5; \
+  num_iregs = 6; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11);
+
+void
+test_ints_on_stack ()
+{
+  def_check_int_passing6(32, 33, 34, 35, 36, 37, fun_check_int_passing_int6_values, fun_check_int_passing_int6_regs, int);
+}
+
+void
+test_too_many_ints ()
+{
+  def_check_int_passing12(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, fun_check_int_passing_int12_values, fun_check_int_passing_int12_regs, int);
+}
+
+void
+test_longs_on_stack ()
+{
+  def_check_int_passing6(32, 33, 34, 35, 36, 37, fun_check_int_passing_long6_values, fun_check_int_passing_long6_regs, long);
+}
+
+void
+test_too_many_longs ()
+{
+  def_check_int_passing12(32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, fun_check_int_passing_long12_values, fun_check_int_passing_long12_regs, long);
+}
+
+void
+test_int128s_on_stack ()
+{
+}
+
+void
+test_too_many_int128s ()
+{
+}
+
+
+int
+main (void)
+{
+  test_ints_on_stack ();
+  test_too_many_ints ();
+  test_longs_on_stack ();
+  test_too_many_longs ();
+  test_int128s_on_stack ();
+  test_too_many_int128s ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_m64m128.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_m64m128.c
new file mode 100644
index 000000000..237435c4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_m64m128.c
@@ -0,0 +1,249 @@
+#include <stdio.h>
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+/* This struct holds values for argument checking.  */
+struct 
+{
+  XMM_T i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23;
+} values;
+
+char *pass;
+int failed = 0;
+
+#undef assert
+#define assert(c) do { \
+  if (!(c)) {failed++; printf ("failed %s\n", pass); } \
+} while (0)
+
+#define compare(X1,X2,T) do { \
+  assert (memcmp (&X1, &X2, sizeof (T)) == 0); \
+} while (0)
+
+void
+fun_check_passing_m64_8_values (__m64 i0 ATTRIBUTE_UNUSED, __m64 i1 ATTRIBUTE_UNUSED, __m64 i2 ATTRIBUTE_UNUSED, __m64 i3 ATTRIBUTE_UNUSED, __m64 i4 ATTRIBUTE_UNUSED, __m64 i5 ATTRIBUTE_UNUSED, __m64 i6 ATTRIBUTE_UNUSED, __m64 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m64);
+  compare (values.i1, i1, __m64);
+  compare (values.i2, i2, __m64);
+  compare (values.i3, i3, __m64);
+  compare (values.i4, i4, __m64);
+  compare (values.i5, i5, __m64);
+  compare (values.i6, i6, __m64);
+  compare (values.i7, i7, __m64);
+}
+
+void
+fun_check_passing_m64_8_regs (__m64 i0 ATTRIBUTE_UNUSED, __m64 i1 ATTRIBUTE_UNUSED, __m64 i2 ATTRIBUTE_UNUSED, __m64 i3 ATTRIBUTE_UNUSED, __m64 i4 ATTRIBUTE_UNUSED, __m64 i5 ATTRIBUTE_UNUSED, __m64 i6 ATTRIBUTE_UNUSED, __m64 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m64_arguments;
+}
+
+void
+fun_check_passing_m64_20_values (__m64 i0 ATTRIBUTE_UNUSED, __m64 i1 ATTRIBUTE_UNUSED, __m64 i2 ATTRIBUTE_UNUSED, __m64 i3 ATTRIBUTE_UNUSED, __m64 i4 ATTRIBUTE_UNUSED, __m64 i5 ATTRIBUTE_UNUSED, __m64 i6 ATTRIBUTE_UNUSED, __m64 i7 ATTRIBUTE_UNUSED, __m64 i8 ATTRIBUTE_UNUSED, __m64 i9 ATTRIBUTE_UNUSED, __m64 i10 ATTRIBUTE_UNUSED, __m64 i11 ATTRIBUTE_UNUSED, __m64 i12 ATTRIBUTE_UNUSED, __m64 i13 ATTRIBUTE_UNUSED, __m64 i14 ATTRIBUTE_UNUSED, __m64 i15 ATTRIBUTE_UNUSED, __m64 i16 ATTRIBUTE_UNUSED, __m64 i17 ATTRIBUTE_UNUSED, __m64 i18 ATTRIBUTE_UNUSED, __m64 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0 , i0, __m64);
+  compare (values.i1 , i1, __m64);
+  compare (values.i2 , i2, __m64);
+  compare (values.i3 , i3, __m64);
+  compare (values.i4 , i4, __m64);
+  compare (values.i5 , i5, __m64);
+  compare (values.i6 , i6, __m64);
+  compare (values.i7 , i7, __m64);
+  compare (values.i8 , i8, __m64);
+  compare (values.i9 , i9, __m64);
+  compare (values.i10 , i10, __m64);
+  compare (values.i11 , i11, __m64);
+  compare (values.i12 , i12, __m64);
+  compare (values.i13 , i13, __m64);
+  compare (values.i14 , i14, __m64);
+  compare (values.i15 , i15, __m64);
+  compare (values.i16 , i16, __m64);
+  compare (values.i17 , i17, __m64);
+  compare (values.i18 , i18, __m64);
+  compare (values.i19 , i19, __m64);
+}
+
+void
+fun_check_passing_m64_20_regs (__m64 i0 ATTRIBUTE_UNUSED, __m64 i1 ATTRIBUTE_UNUSED, __m64 i2 ATTRIBUTE_UNUSED, __m64 i3 ATTRIBUTE_UNUSED, __m64 i4 ATTRIBUTE_UNUSED, __m64 i5 ATTRIBUTE_UNUSED, __m64 i6 ATTRIBUTE_UNUSED, __m64 i7 ATTRIBUTE_UNUSED, __m64 i8 ATTRIBUTE_UNUSED, __m64 i9 ATTRIBUTE_UNUSED, __m64 i10 ATTRIBUTE_UNUSED, __m64 i11 ATTRIBUTE_UNUSED, __m64 i12 ATTRIBUTE_UNUSED, __m64 i13 ATTRIBUTE_UNUSED, __m64 i14 ATTRIBUTE_UNUSED, __m64 i15 ATTRIBUTE_UNUSED, __m64 i16 ATTRIBUTE_UNUSED, __m64 i17 ATTRIBUTE_UNUSED, __m64 i18 ATTRIBUTE_UNUSED, __m64 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m64_arguments;
+}
+
+void
+fun_check_passing_m128_8_values (__m128 i0 ATTRIBUTE_UNUSED, __m128 i1 ATTRIBUTE_UNUSED, __m128 i2 ATTRIBUTE_UNUSED, __m128 i3 ATTRIBUTE_UNUSED, __m128 i4 ATTRIBUTE_UNUSED, __m128 i5 ATTRIBUTE_UNUSED, __m128 i6 ATTRIBUTE_UNUSED, __m128 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0, i0, __m128);
+  compare (values.i1, i1, __m128);
+  compare (values.i2, i2, __m128);
+  compare (values.i3, i3, __m128);
+  compare (values.i4, i4, __m128);
+  compare (values.i5, i5, __m128);
+  compare (values.i6, i6, __m128);
+  compare (values.i7, i7, __m128);
+}
+
+void
+fun_check_passing_m128_8_regs (__m128 i0 ATTRIBUTE_UNUSED, __m128 i1 ATTRIBUTE_UNUSED, __m128 i2 ATTRIBUTE_UNUSED, __m128 i3 ATTRIBUTE_UNUSED, __m128 i4 ATTRIBUTE_UNUSED, __m128 i5 ATTRIBUTE_UNUSED, __m128 i6 ATTRIBUTE_UNUSED, __m128 i7 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m128_arguments;
+}
+
+void
+fun_check_passing_m128_20_values (__m128 i0 ATTRIBUTE_UNUSED, __m128 i1 ATTRIBUTE_UNUSED, __m128 i2 ATTRIBUTE_UNUSED, __m128 i3 ATTRIBUTE_UNUSED, __m128 i4 ATTRIBUTE_UNUSED, __m128 i5 ATTRIBUTE_UNUSED, __m128 i6 ATTRIBUTE_UNUSED, __m128 i7 ATTRIBUTE_UNUSED, __m128 i8 ATTRIBUTE_UNUSED, __m128 i9 ATTRIBUTE_UNUSED, __m128 i10 ATTRIBUTE_UNUSED, __m128 i11 ATTRIBUTE_UNUSED, __m128 i12 ATTRIBUTE_UNUSED, __m128 i13 ATTRIBUTE_UNUSED, __m128 i14 ATTRIBUTE_UNUSED, __m128 i15 ATTRIBUTE_UNUSED, __m128 i16 ATTRIBUTE_UNUSED, __m128 i17 ATTRIBUTE_UNUSED, __m128 i18 ATTRIBUTE_UNUSED, __m128 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check argument values.  */
+  compare (values.i0 , i0, __m128);
+  compare (values.i1 , i1, __m128);
+  compare (values.i2 , i2, __m128);
+  compare (values.i3 , i3, __m128);
+  compare (values.i4 , i4, __m128);
+  compare (values.i5 , i5, __m128);
+  compare (values.i6 , i6, __m128);
+  compare (values.i7 , i7, __m128);
+  compare (values.i8 , i8, __m128);
+  compare (values.i9 , i9, __m128);
+  compare (values.i10 , i10, __m128);
+  compare (values.i11 , i11, __m128);
+  compare (values.i12 , i12, __m128);
+  compare (values.i13 , i13, __m128);
+  compare (values.i14 , i14, __m128);
+  compare (values.i15 , i15, __m128);
+  compare (values.i16 , i16, __m128);
+  compare (values.i17 , i17, __m128);
+  compare (values.i18 , i18, __m128);
+  compare (values.i19 , i19, __m128);
+}
+
+void
+fun_check_passing_m128_20_regs (__m128 i0 ATTRIBUTE_UNUSED, __m128 i1 ATTRIBUTE_UNUSED, __m128 i2 ATTRIBUTE_UNUSED, __m128 i3 ATTRIBUTE_UNUSED, __m128 i4 ATTRIBUTE_UNUSED, __m128 i5 ATTRIBUTE_UNUSED, __m128 i6 ATTRIBUTE_UNUSED, __m128 i7 ATTRIBUTE_UNUSED, __m128 i8 ATTRIBUTE_UNUSED, __m128 i9 ATTRIBUTE_UNUSED, __m128 i10 ATTRIBUTE_UNUSED, __m128 i11 ATTRIBUTE_UNUSED, __m128 i12 ATTRIBUTE_UNUSED, __m128 i13 ATTRIBUTE_UNUSED, __m128 i14 ATTRIBUTE_UNUSED, __m128 i15 ATTRIBUTE_UNUSED, __m128 i16 ATTRIBUTE_UNUSED, __m128 i17 ATTRIBUTE_UNUSED, __m128 i18 ATTRIBUTE_UNUSED, __m128 i19 ATTRIBUTE_UNUSED)
+{
+  /* Check register contents.  */
+  check_m128_arguments;
+}
+
+
+#define def_check_int_passing8(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7); \
+  \
+  clear_float_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7);
+
+#define def_check_int_passing20(_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19, _func1, _func2, TYPE) \
+  values.i0.TYPE[0] = _i0; \
+  values.i1.TYPE[0] = _i1; \
+  values.i2.TYPE[0] = _i2; \
+  values.i3.TYPE[0] = _i3; \
+  values.i4.TYPE[0] = _i4; \
+  values.i5.TYPE[0] = _i5; \
+  values.i6.TYPE[0] = _i6; \
+  values.i7.TYPE[0] = _i7; \
+  values.i8.TYPE[0] = _i8; \
+  values.i9.TYPE[0] = _i9; \
+  values.i10.TYPE[0] = _i10; \
+  values.i11.TYPE[0] = _i11; \
+  values.i12.TYPE[0] = _i12; \
+  values.i13.TYPE[0] = _i13; \
+  values.i14.TYPE[0] = _i14; \
+  values.i15.TYPE[0] = _i15; \
+  values.i16.TYPE[0] = _i16; \
+  values.i17.TYPE[0] = _i17; \
+  values.i18.TYPE[0] = _i18; \
+  values.i19.TYPE[0] = _i19; \
+  WRAP_CALL(_func1) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19); \
+  \
+  clear_float_registers; \
+  fregs.F0.TYPE[0] = _i0; \
+  fregs.F1.TYPE[0] = _i1; \
+  fregs.F2.TYPE[0] = _i2; \
+  fregs.F3.TYPE[0] = _i3; \
+  fregs.F4.TYPE[0] = _i4; \
+  fregs.F5.TYPE[0] = _i5; \
+  fregs.F6.TYPE[0] = _i6; \
+  fregs.F7.TYPE[0] = _i7; \
+  num_fregs = 8; \
+  WRAP_CALL(_func2) (_i0, _i1, _i2, _i3, _i4, _i5, _i6, _i7, _i8, _i9, _i10, _i11, _i12, _i13, _i14, _i15, _i16, _i17, _i18, _i19);
+
+void
+test_m64_on_stack ()
+{
+  __m64 x[8];
+  int i;
+  for (i = 0; i < 8; i++)
+    x[i] = (__m64){32+i, 0};
+  pass = "m64-8";
+  def_check_int_passing8(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], fun_check_passing_m64_8_values, fun_check_passing_m64_8_regs, _m64);
+}
+
+void
+test_too_many_m64 ()
+{
+  __m64 x[20];
+  int i;
+  for (i = 0; i < 20; i++)
+    x[i] = (__m64){32+i, 0};
+  pass = "m64-20";
+  def_check_int_passing20(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[10], x[11], x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], fun_check_passing_m64_20_values, fun_check_passing_m64_20_regs, _m64);
+}
+
+void
+test_m128_on_stack ()
+{
+  __m128 x[8];
+  int i;
+  for (i = 0; i < 8; i++)
+    x[i] = (__m128){32+i, 0, 0, 0};
+  pass = "m128-8";
+  def_check_int_passing8(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], fun_check_passing_m128_8_values, fun_check_passing_m128_8_regs, _m128);
+}
+
+void
+test_too_many_m128 ()
+{
+  __m128 x[20];
+  int i;
+  for (i = 0; i < 20; i++)
+    x[i] = (__m128){32+i, 0, 0, 0};
+  pass = "m128-20";
+  def_check_int_passing20(x[0], x[1], x[2], x[3], x[4], x[5], x[6], x[7], x[8], x[9], x[10], x[11], x[12], x[13], x[14], x[15], x[16], x[17], x[18], x[19], fun_check_passing_m128_20_values, fun_check_passing_m128_20_regs, _m128);
+}
+
+int
+main (void)
+{
+  test_m64_on_stack ();
+  test_too_many_m64 ();
+  test_m128_on_stack ();
+  test_too_many_m128 ();
+  if (failed)
+    abort ();
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs.c
new file mode 100644
index 000000000..ad6d835ba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs.c
@@ -0,0 +1,261 @@
+/* This tests passing of structs. */
+
+#include "defines.h"
+#include "args.h"
+#include <complex.h>
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct int_struct
+{
+  int i;
+};
+
+struct long_struct
+{
+  long l;
+};
+
+struct long2_struct
+{
+  long l1, l2;
+};
+
+struct long3_struct
+{
+  long l1, l2, l3;
+};
+
+
+/* Check that the struct is passed as the individual members in iregs.  */
+void
+check_struct_passing1 (struct int_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_struct_passing2 (struct long_struct ls ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_struct_passing3 (struct long2_struct ls ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_struct_passing4 (struct long3_struct ls ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ls.l1 == rsp+8);
+  assert ((unsigned long)&ls.l2 == rsp+16);
+  assert ((unsigned long)&ls.l3 == rsp+24);
+}
+
+#ifdef CHECK_M64_M128
+struct m128_struct
+{
+  __m128 x;
+};
+
+struct m128_2_struct
+{
+  __m128 x1, x2;
+};
+
+/* Check that the struct is passed as the individual members in fregs.  */
+void
+check_struct_passing5 (struct m128_struct ms1 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms2 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms3 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms4 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms5 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms6 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms7 ATTRIBUTE_UNUSED,
+		       struct m128_struct ms8 ATTRIBUTE_UNUSED)
+{
+  check_m128_arguments;
+}
+
+void
+check_struct_passing6 (struct m128_2_struct ms ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ms.x1 == rsp+8);
+  assert ((unsigned long)&ms.x2 == rsp+24);
+}
+#endif
+
+struct flex1_struct
+{
+  long i;
+  long flex[];
+};
+
+struct flex2_struct
+{
+  long i;
+  long flex[0];
+};
+
+void
+check_struct_passing7 (struct flex1_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_struct_passing8 (struct flex2_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+struct complex1_struct
+{
+  int c;
+  __complex__ float x;
+};
+
+struct complex1a_struct
+{
+  long l;
+  float f;
+};
+
+struct complex2_struct
+{
+  int c;
+  __complex__ float x;
+  float y;
+};
+
+struct complex2a_struct
+{
+  long l;
+  double d;
+};
+
+void
+check_struct_passing9 (struct complex1_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+  check_float_arguments;
+}
+
+void
+check_struct_passing10 (struct complex2_struct is ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+  check_double_arguments;
+}
+
+static struct flex1_struct f1s = { 60, { } };
+static struct flex2_struct f2s = { 61, { } };
+
+int
+main (void)
+{
+  struct int_struct is = { 48 };
+  struct long_struct ls = { 49 };
+#ifdef CHECK_LARGER_STRUCTS
+  struct long2_struct l2s = { 50, 51 };
+  struct long3_struct l3s = { 52, 53, 54 };
+#endif
+#ifdef CHECK_M64_M128
+  struct m128_struct m128s[8];
+  struct m128_2_struct m128_2s = { 
+      { 48.394, 39.3, -397.9, 3484.9 },
+      { -8.394, -93.3, 7.9, 84.94 }
+  };
+  int i;
+#endif
+  struct complex1_struct c1s = { 4, ( -13.4 + 3.5*I ) };
+  union
+    {
+      struct complex1_struct c;
+      struct complex1a_struct u;
+    } c1u;
+  struct complex2_struct c2s = { 4, ( -13.4 + 3.5*I ), -34.5 };
+  union
+    {
+      struct complex2_struct c;
+      struct complex2a_struct u;
+    } c2u;
+
+  clear_struct_registers;
+  iregs.I0 = is.i;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing1)(is);
+
+  clear_struct_registers;
+  iregs.I0 = ls.l;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing2)(ls);
+
+#ifdef CHECK_LARGER_STRUCTS
+  clear_struct_registers;
+  iregs.I0 = l2s.l1;
+  iregs.I1 = l2s.l2;
+  num_iregs = 2;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing3)(l2s);
+  WRAP_CALL (check_struct_passing4)(l3s);
+#endif
+
+#ifdef CHECK_M64_M128
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      m128s[i].x = (__m128){32+i, 0, i, 0};
+      (&fregs.xmm0)[i]._m128[0] = m128s[i].x;
+    }
+  num_fregs = 8;
+  clear_float_hardware_registers;
+  WRAP_CALL (check_struct_passing5)(m128s[0], m128s[1], m128s[2], m128s[3],
+				    m128s[4], m128s[5], m128s[6], m128s[7]);
+  WRAP_CALL (check_struct_passing6)(m128_2s);
+#endif
+
+  clear_struct_registers;
+  iregs.I0 = f1s.i;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing7)(f1s);
+
+  clear_struct_registers;
+  iregs.I0 = f2s.i;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_struct_passing8)(f2s);
+
+  clear_struct_registers;
+  c1u.c = c1s;
+  iregs.I0 = c1u.u.l;
+  num_iregs = 1;
+  fregs.xmm0._float [0] = c1u.u.f;
+  num_fregs = 1;
+  clear_int_hardware_registers;
+  clear_float_hardware_registers;
+  WRAP_CALL (check_struct_passing9)(c1s);
+
+  clear_struct_registers;
+  c2u.c = c2s;
+  iregs.I0 = c2u.u.l;
+  num_iregs = 1;
+  fregs.xmm0._double[0] = c2u.u.d;
+  num_fregs = 1;
+  clear_int_hardware_registers;
+  clear_float_hardware_registers;
+  WRAP_CALL (check_struct_passing10)(c2s);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs_and_unions.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs_and_unions.c
new file mode 100644
index 000000000..5b40196d4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_structs_and_unions.c
@@ -0,0 +1,95 @@
+/* This tests passing of structs. Only integers are tested.  */
+
+#include "defines.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct int_struct
+{
+  int i;
+};
+
+struct long_struct
+{
+  long l;
+};
+
+struct long2_struct
+{
+  long l1, l2;
+};
+
+struct long3_struct
+{
+  long l1, l2, l3;
+};
+
+union un1
+{
+  char c;
+  int i;
+};
+
+union un2
+{
+  char c1;
+  long l;
+  char c2;
+};
+
+union un3
+{
+  struct int_struct is;
+  struct long_struct ls;
+  union un1 un;
+};
+
+
+void
+check_mixed_passing1 (char c1 ATTRIBUTE_UNUSED, struct int_struct is ATTRIBUTE_UNUSED, char c2 ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_mixed_passing2 (char c1 ATTRIBUTE_UNUSED, struct long3_struct ls ATTRIBUTE_UNUSED, char c2 ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&ls.l1 == rsp+8);
+  assert ((unsigned long)&ls.l2 == rsp+16);
+  assert ((unsigned long)&ls.l3 == rsp+24);
+}
+
+int
+main (void)
+{
+  struct int_struct is = { 64 };
+#ifdef CHECK_LARGER_STRUCTS
+  struct long3_struct l3s = { 65, 66, 67 };
+#endif
+
+  clear_struct_registers;
+  iregs.I0 = 8;
+  iregs.I1 = 64;
+  iregs.I2 = 9;
+  num_iregs = 3;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_mixed_passing1)(8, is, 9);
+
+#ifdef CHECK_LARGER_STRUCTS 
+  clear_struct_registers;
+  iregs.I0 = 10;
+  iregs.I1 = 11;
+  num_iregs = 2;
+  clear_int_hardware_registers;
+  WRAP_CALL (check_mixed_passing2)(10, l3s, 11);
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_unions.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_unions.c
new file mode 100644
index 000000000..cff244abb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_passing_unions.c
@@ -0,0 +1,229 @@
+/* This tests passing of structs.  */
+
+#include "defines.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+struct int_struct
+{
+  int i;
+};
+
+struct long_struct
+{
+  long l;
+};
+
+union un1
+{
+  char c;
+  int i;
+};
+
+union un2
+{
+  char c1;
+  long l;
+  char c2;
+};
+
+union un3
+{
+  struct int_struct is;
+  struct long_struct ls;
+  union un1 un;
+};
+
+
+void
+check_union_passing1(union un1 u ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_union_passing2(union un2 u1 ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+void
+check_union_passing3(union un3 u ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+}
+
+#define check_union_passing1 WRAP_CALL(check_union_passing1)
+#define check_union_passing2 WRAP_CALL(check_union_passing2)
+#define check_union_passing3 WRAP_CALL(check_union_passing3)
+
+#ifdef CHECK_M64_M128
+union un4
+{
+  __m128 x;
+  float f;
+};
+
+union un5
+{
+  __m128 x;
+  long i;
+};
+
+void
+check_union_passing4(union un4 u1 ATTRIBUTE_UNUSED,
+		     union un4 u2 ATTRIBUTE_UNUSED,
+		     union un4 u3 ATTRIBUTE_UNUSED,
+		     union un4 u4 ATTRIBUTE_UNUSED,
+		     union un4 u5 ATTRIBUTE_UNUSED,
+		     union un4 u6 ATTRIBUTE_UNUSED,
+		     union un4 u7 ATTRIBUTE_UNUSED,
+		     union un4 u8 ATTRIBUTE_UNUSED)
+{
+  check_m128_arguments;
+}
+
+void
+check_union_passing5(union un5 u ATTRIBUTE_UNUSED)
+{
+  check_int_arguments;
+  check_vector_arguments(m128, 8);
+}
+
+#define check_union_passing4 WRAP_CALL(check_union_passing4)
+#define check_union_passing5 WRAP_CALL(check_union_passing5)
+#endif
+
+union un6
+{
+  long double ld;
+  int i;
+};
+
+
+void
+check_union_passing6(union un6 u ATTRIBUTE_UNUSED)
+{
+  /* Check the passing on the stack by comparing the address of the
+     stack elements to the expected place on the stack.  */
+  assert ((unsigned long)&u.ld == rsp+8);
+  assert ((unsigned long)&u.i == rsp+8);
+}
+
+#define check_union_passing6 WRAP_CALL(check_union_passing6)
+
+int
+main (void)
+{
+  union un1 u1;
+#ifdef CHECK_LARGER_UNION_PASSING
+  union un2 u2;
+  union un3 u3;
+  struct int_struct is;
+  struct long_struct ls;
+#endif /* CHECK_LARGER_UNION_PASSING */
+#ifdef CHECK_M64_M128
+  union un4 u4[8];
+  union un5 u5 = { { 48.394, 39.3, -397.9, 3484.9 } };
+  int i;
+#endif
+  union un6 u6;
+
+  /* Check a union with char, int.  */
+  clear_struct_registers;
+  u1.i = 0;  /* clear the struct to not have high bits left */
+  u1.c = 32;
+  iregs.I0 = 32;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing1(u1);
+  u1.i = 0;  /* clear the struct to not have high bits left */
+  u1.i = 33;
+  iregs.I0 = 33;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing1(u1);
+
+  /* Check a union with char, long, char.  */
+#ifdef CHECK_LARGER_UNION_PASSING
+  clear_struct_registers;
+  u2.l = 0;  /* clear the struct to not have high bits left */
+  u2.c1 = 34;
+  iregs.I0 = 34;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing2(u2);
+  u2.l = 0;  /* clear the struct to not have high bits left */
+  u2.l = 35;
+  iregs.I0 = 35;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing2(u2);
+  u2.l = 0;  /* clear the struct to not have high bits left */
+  u2.c2 = 36;
+  iregs.I0 = 36;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing2(u2);
+
+  /* check a union containing two structs and a union.  */
+  clear_struct_registers;
+  is.i = 37;
+  u3.ls.l = 0;  /* clear the struct to not have high bits left */
+  u3.is = is;
+  iregs.I0 = 37;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing3(u3);
+  ls.l = 38;
+  u3.ls.l = 0;  /* clear the struct to not have high bits left */
+  u3.ls = ls;
+  iregs.I0 = 38;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing3(u3);
+  u1.c = 39;
+  u3.ls.l = 0;  /* clear the struct to not have high bits left */
+  u3.un = u1;
+  iregs.I0 = 39;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing3(u3);
+  u1.i = 40;
+  u3.ls.l = 0;  /* clear the struct to not have high bits left */
+  u3.un = u1;
+  iregs.I0 = 40;
+  num_iregs = 1;
+  clear_int_hardware_registers;
+  check_union_passing3(u3);
+#endif /* CHECK_LARGER_UNION_PASSING */
+
+#ifdef CHECK_M64_M128
+  clear_struct_registers;
+  for (i = 0; i < 8; i++)
+    {
+      u4[i].x = (__m128){32+i, 0, i, 0};
+      (&fregs.xmm0)[i]._m128[0] = u4[i].x;
+    }
+  num_fregs = 8;
+  clear_float_hardware_registers;
+  check_union_passing4(u4[0], u4[1], u4[2], u4[3],
+		       u4[4], u4[5], u4[6], u4[7]);
+
+  clear_struct_registers;
+  fregs.xmm0._m128[0] = u5.x;
+  num_fregs = 1;
+  num_iregs = 1;
+  iregs.I0 = u5.i;
+  clear_float_hardware_registers;
+  check_union_passing5(u5);
+#endif
+
+  u6.i = 2;
+  check_union_passing6(u6);
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_struct_returning.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_struct_returning.c
new file mode 100644
index 000000000..2881f8ec8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_struct_returning.c
@@ -0,0 +1,230 @@
+/* This tests returning of structures.  */
+
+#include <stdio.h>
+#include "defines.h"
+#include "macros.h"
+#include "args.h"
+
+struct IntegerRegisters iregs;
+struct FloatRegisters fregs;
+unsigned int num_iregs, num_fregs;
+
+int current_test;
+int num_failed = 0;
+
+#undef assert
+#define assert(test) do { if (!(test)) {fprintf (stderr, "failed in test %d\n", current_test); num_failed++; } } while (0)
+
+#define xmm0f xmm_regs[0]._float
+#define xmm0d xmm_regs[0]._double
+#define xmm1f xmm_regs[1]._float
+#define xmm1d xmm_regs[1]._double
+
+typedef enum {
+  INT = 0,
+  SSE_F,
+  SSE_D,
+  X87,
+  MEM,
+  INT_SSE,
+  SSE_INT,
+  SSE_F_V
+} Type;
+
+/* Structures which should be returned in INTEGER.  */
+#define D(I,MEMBERS,B) struct S_ ## I { MEMBERS ; }; Type class_ ## I = INT; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s; memset (&s, 0, sizeof(s)); B; return s; }
+
+D(1,char m1, s.m1=42)
+D(2,short m1, s.m1=42)
+D(3,int m1, s.m1=42)
+D(4,long m1, s.m1=42)
+D(5,long long m1, s.m1=42)
+D(6,char m1;short s, s.m1=42)
+D(7,char m1;int i, s.m1=42)
+D(8,char m1; long l, s.m1=42)
+D(9,char m1; long long l, s.m1=42)
+D(10,char m1[16], s.m1[0]=42)
+D(11,short m1[8], s.m1[0]=42)
+D(12,int m1[4], s.m1[0]=42)
+D(13,long m1[2], s.m1[0]=42)
+D(14,long long m1[2], s.m1[0]=42)
+
+#undef D
+
+/* Structures which should be returned in SSE.  */
+#define D(I,MEMBERS,C,B) struct S_ ## I { MEMBERS ; }; Type class_ ## I = C; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s; memset (&s, 0, sizeof(s)); B; return s; }
+
+D(100,float f,SSE_F, s.f=42)
+D(101,double d,SSE_D, s.d=42)
+D(102,float f;float f2,SSE_F, s.f=42)
+D(103,float f;double d,SSE_F, s.f=42)
+D(104,double d; float f,SSE_D, s.d=42)
+D(105,double d; double d2,SSE_D, s.d=42)
+D(106,float f[2],SSE_F, s.f[0]=42)
+D(107,float f[3],SSE_F, s.f[0]=42)
+D(108,float f[4],SSE_F, s.f[0]=42)
+D(109,double d[2],SSE_D, s.d[0]=42)
+D(110,float f[2]; double d,SSE_F, s.f[0]=42)
+D(111,double d;float f[2],SSE_D, s.d=42)
+
+#undef D
+
+/* Structures which should be returned on x87 stack.  */
+#define D(I,MEMBERS) struct S_ ## I { MEMBERS ; }; Type class_ ## I = X87; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s = { 42 }; return s; }
+
+/* The only struct containing a long double, which is returned in
+   registers at all, is the singleton struct.  All others are too large.
+   This includes a struct containing complex long double, which is passed
+   in memory, although a complex long double type itself is returned in
+   two registers.  */
+D(200,long double ld)
+
+#undef D
+
+/* Structures which should be returned in INT (low) and SSE (high).  */
+#define D(I,MEMBERS) struct S_ ## I { MEMBERS ; }; Type class_ ## I = INT_SSE; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s = { 42,43 }; return s; }
+
+D(300,char m1; float m2)
+D(301,char m1; double m2)
+D(302,short m1; float m2)
+D(303,short m1; double m2)
+D(304,int m1; float m2)
+D(305,int m1; double m2)
+D(306,long m1; float m2)
+D(307,long m1; double m2)
+
+#undef D
+
+void check_300 (void)
+{
+  XMM_T x;
+  x._ulong[0] = rax;
+  switch (current_test) {
+    case 300: assert ((rax & 0xff) == 42 && x._float[1] == 43); break;
+    case 301: assert ((rax & 0xff) == 42 && xmm0d[0] == 43); break;
+    case 302: assert ((rax & 0xffff) == 42 && x._float[1] == 43); break;
+    case 303: assert ((rax & 0xffff) == 42 && xmm0d[0] == 43); break;
+    case 304: assert ((rax & 0xffffffff) == 42 && x._float[1] == 43); break;
+    case 305: assert ((rax & 0xffffffff) == 42 && xmm0d[0] == 43); break;
+    case 306: assert (rax == 42 && xmm0f[0] == 43); break;
+    case 307: assert (rax == 42 && xmm0d[0] == 43); break;
+    default: assert (0); break;
+  }
+}
+
+/* Structures which should be returned in SSE (low) and INT (high).  */
+#define D(I,MEMBERS,B) struct S_ ## I { MEMBERS ; }; Type class_ ## I = SSE_INT; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s; memset (&s, 0, sizeof(s));  B; return s; }
+
+D(400,float f[2];char c, s.f[0]=42; s.c=43)
+D(401,double d;char c, s.d=42; s.c=43)
+
+#undef D
+
+void check_400 (void)
+{
+  switch (current_test) {
+    case 400: assert (xmm0f[0] == 42 && (rax & 0xff) == 43); break;
+    case 401: assert (xmm0d[0] == 42 && (rax & 0xff) == 43); break;
+    default: assert (0); break;
+  }
+}
+
+/* Structures which should be returned in MEM.  */
+void *struct_addr;
+#define D(I,MEMBERS) struct S_ ## I { MEMBERS ; }; Type class_ ## I = MEM; \
+struct S_ ## I f_ ## I (void) { union {unsigned char c; struct S_ ## I s;} u; memset (&u.s, 0, sizeof(u.s)); u.c = 42; return u.s; }
+
+/* Too large.  */
+D(500,char m1[17])
+D(501,short m1[9])
+D(502,int m1[5])
+D(503,long m1[3])
+D(504,short m1[8];char c)
+D(505,char m1[1];int i[4])
+D(506,float m1[5])
+D(507,double m1[3])
+D(508,char m1[1];float f[4])
+D(509,char m1[1];double d[2])
+D(510,__complex long double m1[1])
+
+/* Too large due to padding.  */
+D(520,char m1[1];int i;char c2; int i2; char c3)
+
+/* Unnaturally aligned members.  */
+D(530,short m1[1];int i PACKED)
+
+#undef D
+
+
+/* Special tests.  */
+#define D(I,MEMBERS,C,B) struct S_ ## I { MEMBERS ; }; Type class_ ## I = C; \
+struct S_ ## I f_ ## I (void) { struct S_ ## I s; B; return s; }
+D(600,float f[4], SSE_F_V, s.f[0] = s.f[1] = s.f[2] = s.f[3] = 42)
+#undef D
+
+void clear_all (void)
+{
+  clear_int_registers;
+  clear_float_registers;
+  clear_x87_registers;
+}
+
+void check_all (Type class, unsigned long size)
+{
+  switch (class) {
+    case INT: if (size < 8) rax &= ~0UL >> (64-8*size); assert (rax == 42); break;
+    case SSE_F: assert (xmm0f[0] == 42); break;
+    case SSE_D: assert (xmm0d[0] == 42); break;
+    case SSE_F_V: assert (xmm0f[0] == 42 && xmm0f[1]==42 && xmm1f[0] == 42 && xmm1f[1] == 42); break;
+    case X87: assert (x87_regs[0]._ldouble == 42); break;
+    case INT_SSE: check_300(); break;
+    case SSE_INT: check_400(); break;
+    /* Ideally we would like to check that rax == struct_addr.
+       Unfortunately the address of the target struct escapes (for setting
+       struct_addr), so the return struct is a temporary one whose address
+       is given to the f_* functions, otherwise a conforming program
+       could notice the struct changing already before the function returns.
+       This temporary struct could be anywhere.  For GCC it will be on
+       stack, but no one is forbidding that it could be a static variable
+       if there's no threading or proper locking.  Nobody in his right mind
+       will not use the stack for that.  */
+    case MEM: assert (*(unsigned char*)struct_addr == 42 && rdi == rax); break;
+  }
+}
+
+#define D(I) { struct S_ ## I s; current_test = I; struct_addr = (void*)&s; \
+  clear_all(); \
+  s = WRAP_RET(f_ ## I) (); \
+  check_all(class_ ## I, sizeof(s)); \
+}
+
+int
+main (void)
+{
+  D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14)
+  
+  D(100) D(101) D(102) D(103) D(104) D(105) D(106) D(107) D(108) D(109) D(110)
+  D(111)
+
+  D(200)
+
+  D(300) D(301) D(302) D(303) D(304) D(305) D(306) D(307)
+
+  D(400) D(401)
+
+  D(500) D(501) D(502) D(503) D(504) D(505) D(506) D(507) D(508) D(509)
+  D(520)
+  D(530)
+
+  D(600)
+  if (num_failed)
+    abort ();
+
+  return 0;
+}
+#undef D
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_varargs.c b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_varargs.c
new file mode 100644
index 000000000..e6d99461d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/x86_64/abi/test_varargs.c
@@ -0,0 +1,97 @@
+/* Test variable number of arguments passed to functions. For now this is
+   just a simple test to see if it's working.  */
+
+#include <stdarg.h>
+#include "defines.h"
+
+
+#define ARG_INT     1
+#define ARG_DOUBLE  2
+#define ARG_POINTER 3
+
+union types
+{
+  int ivalue;
+  double dvalue;
+  void *pvalue;
+};
+
+struct arg
+{
+  int type;
+  union types value;
+};
+
+struct arg *arglist;
+
+/* This tests the argumentlist to see if it matches the format string which
+   is printf-like. Nothing will be printed of course. It can handle ints,
+   doubles and void pointers. The given value will be tested against the
+   values given in arglist.  
+   This test only assures that the variable argument passing is working.
+   No attempt is made to see if argument passing is done the right way.
+   Since the ABI doesn't say how it's done, checking this is not really
+   relevant.  */
+void
+my_noprintf (char *format, ...)
+{
+  va_list va_arglist;
+  char *c;
+
+  int ivalue;
+  double dvalue;
+  void *pvalue;
+  struct arg *argp = arglist;
+
+  va_start (va_arglist, format);
+  for (c = format; *c; c++)
+    if (*c == '%')
+      {
+	switch (*++c)
+	  {
+	  case 'd':
+	    assert (argp->type == ARG_INT);
+	    ivalue = va_arg (va_arglist, int);
+	    assert (argp->value.ivalue == ivalue);
+	    break;
+	  case 'f':
+	    assert (argp->type == ARG_DOUBLE);
+	    dvalue = va_arg (va_arglist, double);
+	    assert (argp->value.dvalue == dvalue);
+	    break;
+	  case 'p':
+	    assert (argp->type == ARG_POINTER);
+	    pvalue = va_arg (va_arglist, void *);
+	    assert (argp->value.pvalue == pvalue);
+	    break;
+	  default:
+	    abort ();
+	  }
+
+	argp++;
+      }
+}
+
+int
+main (void)
+{
+#ifdef CHECK_VARARGS
+  struct arg al[5];
+
+  al[0].type = ARG_INT;
+  al[0].value.ivalue = 256;
+  al[1].type = ARG_DOUBLE;
+  al[1].value.dvalue = 257.0;
+  al[2].type = ARG_POINTER;
+  al[2].value.pvalue = al;
+  al[3].type = ARG_DOUBLE;
+  al[3].value.dvalue = 258.0;
+  al[4].type = ARG_INT;
+  al[4].value.ivalue = 259;
+
+  arglist = al;
+  my_noprintf("%d%f%p%f%d", 256, 257.0, al, 258.0, 259);
+#endif
+
+  return 0;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below100.S b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below100.S
new file mode 100644
index 000000000..27faa2ef4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below100.S
@@ -0,0 +1,188 @@
+/******************************************************************
+***                                                             ***
+***     crt0 for __BELOW100__ attribute test with SID           ***
+***                                                             ***
+******************************************************************/
+
+                                /*************************************/
+                                /** Interrupt vectors at 0x8000     **/
+                                /*************************************/
+        .section .int_vec,"ax"
+        .global _start
+        .align 1
+_start:
+        jmpf _int_reset
+        //jmpf _int_basetimer
+        //jmpf _int_timer0
+        //jmpf _int_timer1
+        //jmpf _int_irq_4
+        //jmpf _int_irq_5
+        //jmpf _int_port0
+        //jmpf _int_port1
+        //jmpf _int_irq_8
+        //jmpf _int_irq_9
+        //jmpf _int_irq_a
+        //jmpf _int_irq_b
+        //jmpf _int_irq_c
+        //jmpf _int_irq_d
+        //jmpf _int_irq_e
+        //jmpf _int_irq_f
+                                /*************************************/
+                                /** reset code                      **/
+                                /*************************************/
+        .text
+_int_reset:
+                                /*************************************/
+                                /** setup stack pointer             **/
+                                /*************************************/
+        mov sp,#__stack
+                                /*************************************/
+                                /** zero .bss section               **/
+                                /*************************************/
+        mov r0,#__bss_start
+        mov r1,#__bss_end
+        mov r2,#0
+1:      mov.w (r0++),r2
+        blt r0,r1,1b
+                                /*************************************/
+                                /** copy inital value for .data     **/
+                                /*************************************/
+        mov r1,#__data_start
+        mov r3,#__data_end
+        mov r0,#@lo(__rdata)
+        mov r8,#@hi(__rdata)
+2:      movf.w r2,(r0++)
+        bnz r0,#0,3f
+        add r8,#1
+3:      mov.w (r1++),r2
+        blt r1,r3,2b
+                                /*************************************/
+                                /** call hardware init routine      **/
+                                /*************************************/
+        callf _hwinit
+                                /*************************************/
+                                /** call initializaton routines     **/
+                                /*************************************/
+        callf _init
+                                /*************************************/
+                                /** setup fini routines to be       **/
+                                /**  called from exit               **/
+                                /*************************************/
+        mov r2,#@fptr(_fini)
+        callf atexit
+                                /*************************************/
+                                /** call main() with empty          **/
+                                /**  argc/argv/envp                 **/
+                                /*************************************/
+        mov r2,#0
+        mov r3,#0
+        mov r4,#0
+        callf main
+                                /*************************************/
+                                /** return from main()              **/
+                                /*************************************/
+        callf exit
+                                /*************************************/
+                                /** should never reach this code    **/
+                                /*************************************/
+        jmpf _start
+                                /*************************************/
+                                /** default h/w initialize routine  **/
+                                /** and default _init/_finit for    **/
+                                /**  -nostartfiles option           **/
+                                /*************************************/
+        .globl _hwinit
+        .weak _hwinit
+_hwinit:
+        .globl _init
+        .weak _init
+_init:
+        .globl _fini
+        .weak _fini
+_fini:
+        ret
+
+/******************************************************************
+*******************************************************************
+***                                                             ***
+***       Chip information data for LC59_32K                    ***
+***                 Written by T.Matsukawa                      ***
+***                                                             ***
+*******************************************************************
+******************************************************************/
+
+                                /*************************************/
+                                /** Define convenient macros        **/
+                                /*************************************/
+#define BCD(x)  (((x)/10)%10)*0x10+((x)%10)
+#define BCD4(x) BCD((x)/100),BCD(x)
+#define BCD6(x) BCD((x)/10000),BCD((x)/100),BCD(x)
+                                /*************************************/
+                                /** Define memory sizes             **/
+                                /*************************************/
+#define RAM_SIZE 0x7E00
+#define ROM_SIZE 0x78000
+#define VRAM_SIZE 0x0000
+#define VRAM_ROW 0
+#define VRAM_COLUMN 0
+#define CGROM_SIZE 0x0000
+#define PROTECT_SIZE 0x0000
+
+                                /*************************************/
+                                /** section ".chip_info"            **/
+                                /*************************************/
+        .section .chip_info,"a"
+        .space  0xb8,0x00
+                                /*************************************/
+                                /** B8-BB : User option address     **/
+                                /*************************************/
+        .word   0x00000
+        .global __reset_vector
+#if 0x00000==0
+        .equ    __reset_vector,0x08000
+#else
+        .equ    __reset_vector,0x00000
+#endif
+                                /*************************************/
+                                /** BC-BF : Flash Protect address   **/
+                                /*************************************/
+#if PROTECT_SIZE==0
+        .word   0x00000000
+#else
+        .word   0x08000+ROM_SIZE-PROTECT_SIZE
+#endif
+                                /*************************************/
+                                /** C0-CF : Fixed string            **/
+                                /*************************************/
+1:	.ascii  "CHIPINFORMATION"
+2:	.space  (0x10-(2b-1b)),0x00
+                                /*************************************/
+                                /** D0-DF : Chipname                **/
+                                /*************************************/
+1:	.ascii  "LC59_32K"
+2:	.space  (0x10-(2b-1b)),0x00
+                                /*************************************/
+                                /** E0-E1 : Format version(BCD4)    **/
+                                /*************************************/
+        .byte   0x10, 0x00
+        .space  6, 0x00
+                                /*************************************/
+                                /** E8-F5 : Memory sizes            **/
+                                /*************************************/
+        .byte   BCD4(ROM_SIZE/1024)
+        .byte   BCD6(RAM_SIZE)
+        .byte   BCD6(VRAM_SIZE)
+        .byte   BCD4(VRAM_ROW)
+        .byte   BCD4(VRAM_COLUMN)
+        .byte   BCD4(CGROM_SIZE/1024)
+        .space  3, 0x00
+                                /*************************************/
+                                /** F9 : Package type               **/
+                                /*************************************/
+        .byte   0xff
+        .space  6, 0x00
+
+                                /*************************************/
+                                /** In order to link BIOS in library**/
+                                /*************************************/
+        .equ    dummy,__bios_entry
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below100.ld b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below100.ld
new file mode 100644
index 000000000..91c3e43f7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below100.ld
@@ -0,0 +1,192 @@
+/******************************************************************
+*******************************************************************
+***                                                             ***
+***     Linker script for xstormy16-elf-gcc                     ***
+***           For SID   RAM=0x7E00                              ***
+***                     ROM=0x78000                             ***
+***                                                             ***
+*******************************************************************
+******************************************************************/
+
+OUTPUT_FORMAT("elf32-xstormy16", "elf32-xstormy16", "elf32-xstormy16")
+OUTPUT_ARCH(xstormy16)
+ENTRY(_start)
+SEARCH_DIR( . )
+GROUP(-lc -lsim -lgcc)
+PROVIDE( __target_package = 0xff);
+
+__malloc_start = 0x7E00;
+
+MEMORY
+{
+	RAM (w)    : ORIGIN = 0x00000, LENGTH = 0x07E00
+	CHIP (r)   : ORIGIN = 0x07f00, LENGTH = 0x00100
+	ROM (!w)   : ORIGIN = 0x08000, LENGTH = 0x78000
+}
+
+SECTIONS
+{
+	/* Zero initialized data with the below100 attribute.  */
+	.bss_below100 : {
+		SHORT(0)
+		__bss_start = .;
+		*(.bss_below100)
+		*(.bss_below100.*)
+		. = ALIGN(2);
+	} > RAM
+	
+	/* Non-zero initialized data with the below100 attribute.  */
+	.data_below100 : AT ( __rdata ) {
+		__data_start = . ;
+	        *(.data_0)
+		*(.data_below100)
+		*(.data_below100.*)
+		. = ALIGN(2);
+	} > RAM = 0
+	
+        /* Normal non-zero initialized data.  */
+       .data : AT ( __rdata + SIZEOF(.data_below100) ) {
+		*(.data)
+		*(.data.*)
+		*(.gnu.linkonce.d.*)
+		SORT(CONSTRUCTORS)
+		. = ALIGN(2);
+		__data_end = . ;
+	} > RAM =0
+	
+        /* Normal zero initialized data.  */
+	.bss : AT (LOADADDR(.data) + SIZEOF(.data)) {
+        	*(.dynbss)
+		*(.bss)
+		*(.bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(2);
+		__bss_end = .;
+	} > RAM
+	
+        /* The top of stack.  */
+	__stack = .;
+
+        /* Target chip info.  */
+	.chip_info : {
+		KEEP(*(.chip_info))
+	} > CHIP =0
+	
+        /* Reset and interrupt vectors at 8000.  */
+	.int_vec : {
+	        KEEP(*(.int_vec))
+	} > ROM =0
+	
+        /* Read only data.  */
+	.rodata : {
+        	*(.rodata)
+		*(.rodata.*)
+		*(.gnu.linkonce.r.*)
+	} > ROM =0
+	
+        /* C++ Construcrtors and destructors.  */
+	.ctors : {
+		KEEP (*crtbegin.o(.ctors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+		KEEP (*(SORT(.ctors.*)))
+		KEEP (*(.ctors))
+	} > ROM =0
+	
+	.dtors : {
+        	KEEP (*crtbegin.o(.dtors))
+		KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+		KEEP (*(SORT(.dtors.*)))
+		KEEP (*(.dtors))
+	} > ROM =0
+
+        /* Pointer lookup table.. */
+	.plt : {
+	        *(.plt)
+	} > ROM =0
+
+        /* Other information.  */
+	.jcr : {
+	        KEEP (*(.jcr))
+	} > ROM =0
+	
+	.eh_frame : {
+	        KEEP (*(.eh_frame))
+	} > ROM =0
+
+	.gcc_except_table : {
+	        KEEP (*(.gcc_except_table))
+	} > ROM =0
+
+        /* Initialization values for data.  */
+	.data_init (NOLOAD) : {
+		__rdata = .;
+		. += SIZEOF(.data_below100);
+		. += SIZEOF(.data);
+		. += SIZEOF(.bss);
+	} > ROM
+
+        /* Executable code.  */
+	.text : {
+		*(.text)
+		*(.text.*)
+		*(.stub)
+		*(.gnu.warning)
+		*(.gnu.linkonce.t.*)
+	} > ROM =0
+
+        /* Startup/finish code.  */
+	.init : {
+        	KEEP (*crti.o(.init))
+		KEEP (*(EXCLUDE_FILE (*crtn.o ) .init))
+		KEEP (*(SORT(.init.*)))
+		KEEP (*(.init))
+	} > ROM =0
+	
+	.fini : {
+        	KEEP (*crti.o(.fini))
+		KEEP (*(EXCLUDE_FILE (*crtn.o ) .fini))
+		KEEP (*(SORT(.fini.*)))
+		KEEP (*(.fini))
+	} > ROM =0
+
+        /* Stab debugging sections.  */
+	.stab          0 : { *(.stab) }
+	.stabstr       0 : { *(.stabstr) }
+	.stab.excl     0 : { *(.stab.excl) }
+	.stab.exclstr  0 : { *(.stab.exclstr) }
+	.stab.index    0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment       0 : { *(.comment) }
+
+        /* DWARF debug sections.  */	
+	/* Symbols in the DWARF debugging sections are relative to
+	   the beginning of the section so we begin them at 0.  */
+
+   	/* DWARF 1.  */
+	.debug 0 : { *(.debug) }
+	.line 0 : { *(.line) }
+
+	/* GNU DWARF 1 extensions.  */
+	.debug_srcinfo 0 : { *(.debug_srcinfo) }
+	.debug_sfnames 0 : { *(.debug_sfnames) }
+
+	/* DWARF 1.1 and DWARF 2.  */
+	.debug_aranges  0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+
+	/* DWARF 2.  */
+	.debug_info     0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
+	.debug_abbrev   0 : { *(.debug_abbrev) }
+	.debug_line     0 : { *(.debug_line) }
+	.debug_frame    0 : { *(.debug_frame) }
+	.debug_str      0 : { *(.debug_str) }
+	.debug_loc      0 : { *(.debug_loc) }
+	.debug_macinfo  0 : { *(.debug_macinfo) }
+
+        /* SGI/MIPS DWARF 2 extensions.  */
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below_100.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below_100.c
new file mode 100644
index 000000000..9433f2ad8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/below_100.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "bn " } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+unsigned short   a_below __attribute__((__BELOW100__));
+unsigned short   b_below __attribute__((__BELOW100__));
+unsigned short * a_ptr = & a_below;
+unsigned short * b_ptr = & b_below;
+
+char *
+foo (void)
+{
+  if (a_below & 0x0100)
+    {
+      if (b_below & 0x0100)
+	return "Fail";
+      return "Success";
+    }
+
+  return "Fail";
+}
+
+char *
+bar (void)
+{
+  *a_ptr = 0x0100;
+  *b_ptr = 0xfeff;
+  return foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bp.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bp.c
new file mode 100644
index 000000000..26ca6a3b4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bp.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define a_val (*((volatile unsigned char *) 0x7f14))
+#define b_val (*((volatile unsigned char *) 0x7f10))
+
+unsigned char * a_ptr = (unsigned char *) 0x7f14;
+unsigned char * b_ptr = (unsigned char *) 0x7f10;
+
+int
+foo (void)
+{
+  if (a_val & 0x08)
+    {
+      if (b_val & 0x08)
+	return -1;
+
+      return 0;
+    }
+
+  return -1;
+}
+
+int
+bar (void)
+{
+  *a_ptr = 0x08;
+  *b_ptr = 0xf7;
+
+  return foo ();
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/01_const_to_b100b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/01_const_to_b100b.c
new file mode 100644
index 000000000..2b4438c4c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/01_const_to_b100b.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b B100,#18" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 = 0x12;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/02_const_to_b100w.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/02_const_to_b100w.c
new file mode 100644
index 000000000..d011ffd66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/02_const_to_b100w.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w B100,#4660" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 = 0x1234;
+}
+
+int
+main (void)
+{
+  *p = 0x9876;
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/03_var_to_b100b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/03_var_to_b100b.c
new file mode 100644
index 000000000..bcc991189
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/03_var_to_b100b.c
@@ -0,0 +1,22 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b B100,r" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  B100 = yData;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/04_var_to_b100w.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/04_var_to_b100w.c
new file mode 100644
index 000000000..ab4748871
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/04_var_to_b100w.c
@@ -0,0 +1,22 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w B100,r" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  B100 = wData;
+}
+
+int
+main (void)
+{
+  *p = 0x9876;
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/05_b100b_to_var.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/05_b100b_to_var.c
new file mode 100644
index 000000000..e5f57e803
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/05_b100b_to_var.c
@@ -0,0 +1,22 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *B100" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  yData = B100;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (yData == 0x34) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/06_b100w_to_var.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/06_b100w_to_var.c
new file mode 100644
index 000000000..b19d9bcf4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/06_b100w_to_var.c
@@ -0,0 +1,22 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,B100" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  wData = B100;
+}
+
+int
+main (void)
+{
+  *p = 0x3456;
+  Do ();
+  return (wData == 0x3456) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_0.c
new file mode 100644
index 000000000..f0965f110
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_0.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x01;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_7.c
new file mode 100644
index 000000000..8b14c4308
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/10_set_b100b_bit_7.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x80;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_0.c
new file mode 100644
index 000000000..79c265a24
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_0.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x01;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_7.c
new file mode 100644
index 000000000..d40e68f55
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/11_clr_b100b_bit_7.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__));
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x80;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_0.c
new file mode 100644
index 000000000..26b3711ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x01)
+    {
+      if (B100B & 0x01)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_3.c
new file mode 100644
index 000000000..865ec549b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_3.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x08)
+    {
+      if (B100B & 0x08)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_7.c
new file mode 100644
index 000000000..efbe1243c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/12_if1_b100b_bit_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x80)
+    {
+      if (B100B & 0x80)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_0.c
new file mode 100644
index 000000000..81873954c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x01))
+    {
+      if (!(B100B & 0x01))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_3.c
new file mode 100644
index 000000000..3fc566aa9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_3.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x08))
+    {
+      if (!(B100B & 0x08))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_7.c
new file mode 100644
index 000000000..bc90eaf95
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/13_if0_b100b_bit_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x80))
+    {
+      if (!(B100B & 0x80))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_0.c
new file mode 100644
index 000000000..9164d05df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_0.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0001;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_7.c
new file mode 100644
index 000000000..848c3241f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_7.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0080;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_8.c
new file mode 100644
index 000000000..f843d12af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_8.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0100;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_f.c
new file mode 100644
index 000000000..bba6dc9f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/14_set_b100w_bit_f.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x8000;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_0.c
new file mode 100644
index 000000000..634f2fc65
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_0.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0001;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_7.c
new file mode 100644
index 000000000..4b7d1bd72
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_7.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0080;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_8.c
new file mode 100644
index 000000000..1c5d4c402
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_8.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0100;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_f.c
new file mode 100644
index 000000000..5140c6caf
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/15_clr_b100w_bit_f.c
@@ -0,0 +1,20 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__));
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x8000;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_0.c
new file mode 100644
index 000000000..fb6a1ba31
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0001)
+    {
+      if (B100B & 0x0001)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_3.c
new file mode 100644
index 000000000..c62462914
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_3.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0008)
+    {
+      if (B100B & 0x0008)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_7.c
new file mode 100644
index 000000000..d1c3fbf56
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0080)
+    {
+      if (B100B & 0x0080)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_8.c
new file mode 100644
index 000000000..b10454203
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_8.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0100)
+    {
+      if (B100B & 0x0100)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_b.c
new file mode 100644
index 000000000..8fbded125
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_b.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0800)
+    {
+      if (B100B & 0x0800)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_f.c
new file mode 100644
index 000000000..ae97d96a8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/16_if1_b100w_bit_f.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x8000)
+    {
+      if (B100B & 0x8000)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_0.c
new file mode 100644
index 000000000..07c6e94d5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0001))
+    {
+      if (!(B100B & 0x0001))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_3.c
new file mode 100644
index 000000000..f2dd3fba6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_3.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0008))
+    {
+      if (!(B100B & 0x0008))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_7.c
new file mode 100644
index 000000000..af6eb6e17
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0080))
+    {
+      if (!(B100B & 0x0080))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_8.c
new file mode 100644
index 000000000..d50f8f82b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_8.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0100))
+    {
+      if (!(B100B & 0x0100))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_b.c
new file mode 100644
index 000000000..28d5a39bb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_b.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0800))
+    {
+      if (!(B100B & 0x0800))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_f.c
new file mode 100644
index 000000000..6a3f7025f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/17_if0_b100w_bit_f.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x8000))
+    {
+      if (!(B100B & 0x8000))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_0.c
new file mode 100644
index 000000000..240e47299
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_0.c
@@ -0,0 +1,32 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_7.c
new file mode 100644
index 000000000..674e51a64
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/20_set_b100b_bitfield_7.c
@@ -0,0 +1,32 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_0.c
new file mode 100644
index 000000000..3846a96d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_0.c
@@ -0,0 +1,32 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_7.c
new file mode 100644
index 000000000..10174576f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/21_clr_b100b_bitfield_7.c
@@ -0,0 +1,32 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_0.c
new file mode 100644
index 000000000..9c4135776
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_0.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b0)
+    {
+      if (B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_3.c
new file mode 100644
index 000000000..86f0f22f1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_3.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b3)
+    {
+      if (B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_7.c
new file mode 100644
index 000000000..0df2f55dd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/22_if1_b100b_bitfield_7.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b7)
+    {
+      if (B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_0.c
new file mode 100644
index 000000000..9acd8a6f9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_0.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b0)
+    {
+      if (!B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_3.c
new file mode 100644
index 000000000..3ddbc1a10
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_3.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b3)
+    {
+      if (!B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_7.c
new file mode 100644
index 000000000..3c0802e1e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/23_if0_b100b_bitfield_7.c
@@ -0,0 +1,43 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b7)
+    {
+      if (!B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_0.c
new file mode 100644
index 000000000..d2fb58096
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_0.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_7.c
new file mode 100644
index 000000000..148253440
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_7.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_8.c
new file mode 100644
index 000000000..ce495b3ec
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_8.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b8 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_f.c
new file mode 100644
index 000000000..057f2d023
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/24_set_b100w_bitfield_f.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b15 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_0.c
new file mode 100644
index 000000000..f32a16bd9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_0.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_7.c
new file mode 100644
index 000000000..b123c5e3e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_7.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_8.c
new file mode 100644
index 000000000..ed923a1d0
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_8.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b8 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_f.c
new file mode 100644
index 000000000..2e0411519
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/25_clr_b100w_bitfield_f.c
@@ -0,0 +1,40 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__));
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b15 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_0.c
new file mode 100644
index 000000000..223de1284
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_0.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b0)
+    {
+      if (B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_3.c
new file mode 100644
index 000000000..83b0a8a15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_3.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b3)
+    {
+      if (B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_7.c
new file mode 100644
index 000000000..89e71b89f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_7.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b7)
+    {
+      if (B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_8.c
new file mode 100644
index 000000000..044541bfe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_8.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b8)
+    {
+      if (B100B.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_b.c
new file mode 100644
index 000000000..e36934f8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_b.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b11)
+    {
+      if (B100B.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_f.c
new file mode 100644
index 000000000..90d0bbd9b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/26_if1_b100w_bitfield_f.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b15)
+    {
+      if (B100B.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_0.c
new file mode 100644
index 000000000..a81359ca3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_0.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b0)
+    {
+      if (!B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_3.c
new file mode 100644
index 000000000..d9eff1abb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_3.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b3)
+    {
+      if (!B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_7.c
new file mode 100644
index 000000000..1d643ea02
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_7.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b7)
+    {
+      if (!B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_8.c
new file mode 100644
index 000000000..5a2b67863
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_8.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b8)
+    {
+      if (!B100B.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_b.c
new file mode 100644
index 000000000..87f760b22
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_b.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b11)
+    {
+      if (!B100B.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_f.c
new file mode 100644
index 000000000..1950ca27c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/bss_below100/27_if0_b100w_bitfield_f.c
@@ -0,0 +1,51 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__));
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__));
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b15)
+    {
+      if (!B100B.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/01_const_to_b100b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/01_const_to_b100b.c
new file mode 100644
index 000000000..0ffc4bad8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/01_const_to_b100b.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b B100,#18" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 = 0x12;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/02_const_to_b100w.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/02_const_to_b100w.c
new file mode 100644
index 000000000..e2ad793c9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/02_const_to_b100w.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w B100,#4660" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x9876;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 = 0x1234;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/03_var_to_b100b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/03_var_to_b100b.c
new file mode 100644
index 000000000..f78d18ab9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/03_var_to_b100b.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b B100,r" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  B100 = yData;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/04_var_to_b100w.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/04_var_to_b100w.c
new file mode 100644
index 000000000..b9f3c55cd
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/04_var_to_b100w.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w B100,r" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x9876;
+unsigned short *p = &B100;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  B100 = wData;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/05_b100b_to_var.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/05_b100b_to_var.c
new file mode 100644
index 000000000..b2a0bd04c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/05_b100b_to_var.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *B100" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  yData = B100;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (yData == 0x34) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/06_b100w_to_var.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/06_b100w_to_var.c
new file mode 100644
index 000000000..50a6dd2a1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/06_b100w_to_var.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,B100" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x3456;
+unsigned short *p = &B100;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  wData = B100;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (wData == 0x3456) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_0.c
new file mode 100644
index 000000000..f81d26a3c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x01;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_7.c
new file mode 100644
index 000000000..2c519132e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/10_set_b100b_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x80;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_0.c
new file mode 100644
index 000000000..500f9baf4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x01;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_7.c
new file mode 100644
index 000000000..7c71f6789
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/11_clr_b100b_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100 __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x80;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_0.c
new file mode 100644
index 000000000..10dee7151
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x01)
+    {
+      if (B100B & 0x01)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_3.c
new file mode 100644
index 000000000..b36612409
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x08)
+    {
+      if (B100B & 0x08)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_7.c
new file mode 100644
index 000000000..9906a663c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/12_if1_b100b_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x80)
+    {
+      if (B100B & 0x80)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_0.c
new file mode 100644
index 000000000..04cc92913
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x01))
+    {
+      if (!(B100B & 0x01))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_3.c
new file mode 100644
index 000000000..cbda60c27
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x08))
+    {
+      if (!(B100B & 0x08))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_7.c
new file mode 100644
index 000000000..49143469d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/13_if0_b100b_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned char B100A __attribute__ ((__BELOW100__)) = 0x34;
+unsigned char *pA = &B100A;
+unsigned char B100B __attribute__ ((__BELOW100__)) = 0xcb;
+unsigned char *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x80))
+    {
+      if (!(B100B & 0x80))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_0.c
new file mode 100644
index 000000000..acce9e1d9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0001;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_7.c
new file mode 100644
index 000000000..35fe30f5d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0080;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_8.c
new file mode 100644
index 000000000..cc337fc04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_8.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x0100;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_f.c
new file mode 100644
index 000000000..1fce8df53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/14_set_b100w_bit_f.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 |= 0x8000;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_0.c
new file mode 100644
index 000000000..7c1c9b3e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0001;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_7.c
new file mode 100644
index 000000000..fd707dc78
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0080;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_8.c
new file mode 100644
index 000000000..7788de60b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_8.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#0" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x0100;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_f.c
new file mode 100644
index 000000000..8046ee370
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/15_clr_b100w_bit_f.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#7" } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100 __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *p = &B100;
+
+void
+Do (void)
+{
+  B100 &= ~0x8000;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_0.c
new file mode 100644
index 000000000..a5df453ae
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0001)
+    {
+      if (B100B & 0x0001)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_3.c
new file mode 100644
index 000000000..8ff76e19d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0008)
+    {
+      if (B100B & 0x0008)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_7.c
new file mode 100644
index 000000000..8f542f31a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0080)
+    {
+      if (B100B & 0x0080)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_8.c
new file mode 100644
index 000000000..727104cb2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_8.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0100)
+    {
+      if (B100B & 0x0100)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_b.c
new file mode 100644
index 000000000..74fd66961
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_b.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x0800)
+    {
+      if (B100B & 0x0800)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_f.c
new file mode 100644
index 000000000..79b3839d8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/16_if1_b100w_bit_f.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (B100A & 0x8000)
+    {
+      if (B100B & 0x8000)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_0.c
new file mode 100644
index 000000000..94dc08884
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0001))
+    {
+      if (!(B100B & 0x0001))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_3.c
new file mode 100644
index 000000000..7bc005dba
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0008))
+    {
+      if (!(B100B & 0x0008))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_7.c
new file mode 100644
index 000000000..64fcdc251
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0080))
+    {
+      if (!(B100B & 0x0080))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_8.c
new file mode 100644
index 000000000..6a118126e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_8.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0100))
+    {
+      if (!(B100B & 0x0100))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_b.c
new file mode 100644
index 000000000..59a2f3578
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_b.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x0800))
+    {
+      if (!(B100B & 0x0800))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_f.c
new file mode 100644
index 000000000..3b271902b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/17_if0_b100w_bit_f.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+unsigned short B100A __attribute__ ((__BELOW100__)) = 0x1234;
+unsigned short *pA = &B100A;
+unsigned short B100B __attribute__ ((__BELOW100__)) = 0xedcb;
+unsigned short *pB = &B100B;
+
+char *
+Do (void)
+{
+  if (!(B100A & 0x8000))
+    {
+      if (!(B100B & 0x8000))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_0.c
new file mode 100644
index 000000000..fef1f2ed4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_0.c
@@ -0,0 +1,33 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_7.c
new file mode 100644
index 000000000..b3900ca82
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/20_set_b100b_bitfield_7.c
@@ -0,0 +1,33 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_0.c
new file mode 100644
index 000000000..6106f3860
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_0.c
@@ -0,0 +1,33 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_7.c
new file mode 100644
index 000000000..414eec653
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/21_clr_b100b_bitfield_7.c
@@ -0,0 +1,33 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *p = (unsigned char *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_0.c
new file mode 100644
index 000000000..b950c5184
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_0.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b0)
+    {
+      if (B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_3.c
new file mode 100644
index 000000000..b9da6a5e6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_3.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b3)
+    {
+      if (B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_7.c
new file mode 100644
index 000000000..667e892ea
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/22_if1_b100b_bitfield_7.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b7)
+    {
+      if (B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_0.c
new file mode 100644
index 000000000..ebb63f74c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_0.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b0)
+    {
+      if (!B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_3.c
new file mode 100644
index 000000000..a16768e40
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_3.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b3)
+    {
+      if (!B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_7.c
new file mode 100644
index 000000000..6f6d181e5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/23_if0_b100b_bitfield_7.c
@@ -0,0 +1,45 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0};
+unsigned char *pA = (unsigned char *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1};
+unsigned char *pB = (unsigned char *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b7)
+    {
+      if (!B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_0.c
new file mode 100644
index 000000000..7ac5028af
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_0.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_7.c
new file mode 100644
index 000000000..8ba664bed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_7.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_8.c
new file mode 100644
index 000000000..2a43500c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_8.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b8 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_f.c
new file mode 100644
index 000000000..9ae5ce48b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/24_set_b100w_bitfield_f.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 B100\\+1,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b15 = 1;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_0.c
new file mode 100644
index 000000000..94fdf6969
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_0.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b0 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_7.c
new file mode 100644
index 000000000..25f11a603
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_7.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b7 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_8.c
new file mode 100644
index 000000000..d065be146
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_8.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b8 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_f.c
new file mode 100644
index 000000000..4fbe71455
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/25_clr_b100w_bitfield_f.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 B100\\+1,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100 __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *p = (unsigned short *) &B100;
+
+void
+Do (void)
+{
+  B100.b15 = 0;
+}
+
+int
+main (void)
+{
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_0.c
new file mode 100644
index 000000000..054c0f51e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_0.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b0)
+    {
+      if (B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_3.c
new file mode 100644
index 000000000..75ef36b34
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_3.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b3)
+    {
+      if (B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_7.c
new file mode 100644
index 000000000..45df6371c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_7.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b7)
+    {
+      if (B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_8.c
new file mode 100644
index 000000000..187a47761
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_8.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b8)
+    {
+      if (B100B.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_b.c
new file mode 100644
index 000000000..8cf4cfd53
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_b.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b11)
+    {
+      if (B100B.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_f.c
new file mode 100644
index 000000000..235cef7d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/26_if1_b100w_bitfield_f.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (B100A.b15)
+    {
+      if (B100B.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_0.c
new file mode 100644
index 000000000..bb80aca81
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_0.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b0)
+    {
+      if (!B100B.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_3.c
new file mode 100644
index 000000000..5be556426
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_3.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b3)
+    {
+      if (!B100B.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_7.c
new file mode 100644
index 000000000..0725b5542
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_7.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b7)
+    {
+      if (!B100B.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_8.c
new file mode 100644
index 000000000..2ad3642f8
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_8.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#0," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#0," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b8)
+    {
+      if (!B100B.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_b.c
new file mode 100644
index 000000000..e9af02f8e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_b.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#3," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#3," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b11)
+    {
+      if (!B100B.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_f.c
new file mode 100644
index 000000000..a13ec8c2c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/data_below100/27_if0_b100w_bitfield_f.c
@@ -0,0 +1,53 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] B100A\\+1,#7," } } */
+/* { dg-final { scan-assembler "b\[np\] B100B\\+1,#7," } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+char acDummy[0xf0] __attribute__ ((__BELOW100__));
+BitField B100A __attribute__ ((__BELOW100__)) =
+{
+0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+unsigned short *pA = (unsigned short *) &B100A;
+BitField B100B __attribute__ ((__BELOW100__)) =
+{
+1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1};
+unsigned short *pB = (unsigned short *) &B100B;
+
+char *
+Do (void)
+{
+  if (!B100A.b15)
+    {
+      if (!B100B.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/01_const_to_sfrb.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/01_const_to_sfrb.c
new file mode 100644
index 000000000..96e4adcfb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/01_const_to_sfrb.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b 32532,#18" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR = 0x12;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/02_const_to_sfrw.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/02_const_to_sfrw.c
new file mode 100644
index 000000000..930ba4d96
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/02_const_to_sfrw.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w 32532,#4660" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR = 0x1234;
+}
+
+int
+main (void)
+{
+  *p = 0x9876;
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/03_var_to_sfrb.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/03_var_to_sfrb.c
new file mode 100644
index 000000000..8c4b1f1c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/03_var_to_sfrb.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b 32532,r" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  SFR = yData;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x12) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/04_var_to_sfrw.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/04_var_to_sfrw.c
new file mode 100644
index 000000000..c8d4a0e66
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/04_var_to_sfrw.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w 32532,r" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+unsigned short wData = 0x1234;
+
+void
+Do (void)
+{
+  SFR = wData;
+}
+
+int
+main (void)
+{
+  *p = 0x9876;
+  Do ();
+  return (*p == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/05_sfrb_to_var.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/05_sfrb_to_var.c
new file mode 100644
index 000000000..9471e295a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/05_sfrb_to_var.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32532" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+unsigned char yData = 0x12;
+
+void
+Do (void)
+{
+  yData = SFR;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (yData == 0x34) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c
new file mode 100644
index 000000000..39cbab5c3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/06_sfrw_to_var.c
@@ -0,0 +1,21 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r6,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+unsigned short wData = 0x9876;
+
+void
+Do (void)
+{
+  wData = SFR;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (wData == 0x1234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_0.c
new file mode 100644
index 000000000..644afb59c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#0" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x01;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_7.c
new file mode 100644
index 000000000..90cd3c83f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/10_set_sfrb_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#7" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x80;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_0.c
new file mode 100644
index 000000000..59d6153ed
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#0" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x01;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_7.c
new file mode 100644
index 000000000..0cb7e1761
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/11_clr_sfrb_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#7" } } */
+
+#define SFR (*((volatile unsigned char*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x80;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_0.c
new file mode 100644
index 000000000..54b0b1f6d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x01)
+    {
+      if (SFRB & 0x01)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_3.c
new file mode 100644
index 000000000..4a575cc99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x08)
+    {
+      if (SFRB & 0x08)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_7.c
new file mode 100644
index 000000000..747cbdd94
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/12_if1_sfrb_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x80)
+    {
+      if (SFRB & 0x80)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_0.c
new file mode 100644
index 000000000..d14969206
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x01))
+    {
+      if (!(SFRB & 0x01))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_3.c
new file mode 100644
index 000000000..be6112cf1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x08))
+    {
+      if (!(SFRB & 0x08))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_7.c
new file mode 100644
index 000000000..12e68cd5b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/13_if0_sfrb_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+#define SFRA (*((volatile unsigned char*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile unsigned char*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x80))
+    {
+      if (!(SFRB & 0x80))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_0.c
new file mode 100644
index 000000000..00f4f78cc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0001;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_3.c
new file mode 100644
index 000000000..b5741fc48
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_3.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0008;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x123c) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_7.c
new file mode 100644
index 000000000..ffcad45b2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0080;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_8.c
new file mode 100644
index 000000000..3f19329f2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_8.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0100;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_b.c
new file mode 100644
index 000000000..b5e8bb9e2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_b.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x0800;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1a34) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_f.c
new file mode 100644
index 000000000..767e95ff4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/14_set_sfrw_bit_f.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR |= 0x8000;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_0.c
new file mode 100644
index 000000000..fcabe0994
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_0.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0001;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_3.c
new file mode 100644
index 000000000..26281be87
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_3.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0008;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedc3) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_7.c
new file mode 100644
index 000000000..15ff063f4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_7.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0080;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_8.c
new file mode 100644
index 000000000..c44817a73
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_8.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0100;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_b.c
new file mode 100644
index 000000000..9f1c3a5e7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_b.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x0800;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xe5cb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_f.c
new file mode 100644
index 000000000..46eef43c4
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/15_clr_sfrw_bit_f.c
@@ -0,0 +1,19 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFR (*((volatile unsigned short*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR &= ~0x8000;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_0.c
new file mode 100644
index 000000000..287dd7a83
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0001)
+    {
+      if (SFRB & 0x0001)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_3.c
new file mode 100644
index 000000000..719fa58df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0008)
+    {
+      if (SFRB & 0x0008)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_7.c
new file mode 100644
index 000000000..1b361c5fe
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0080)
+    {
+      if (SFRB & 0x0080)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_8.c
new file mode 100644
index 000000000..c8a3ba7cb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_8.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0100)
+    {
+      if (SFRB & 0x0100)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_b.c
new file mode 100644
index 000000000..a0f5742c1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_b.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x0800)
+    {
+      if (SFRB & 0x0800)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_f.c
new file mode 100644
index 000000000..5e91bb23e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/16_if1_sfrw_bit_f.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA & 0x8000)
+    {
+      if (SFRB & 0x8000)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_0.c
new file mode 100644
index 000000000..ac5d87fe3
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_0.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0001))
+    {
+      if (!(SFRB & 0x0001))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_3.c
new file mode 100644
index 000000000..fa77f1bd1
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_3.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0008))
+    {
+      if (!(SFRB & 0x0008))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_7.c
new file mode 100644
index 000000000..cb331f034
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_7.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0080))
+    {
+      if (!(SFRB & 0x0080))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_8.c
new file mode 100644
index 000000000..105bf4d8d
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_8.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0100))
+    {
+      if (!(SFRB & 0x0100))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_b.c
new file mode 100644
index 000000000..768cfb92b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_b.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x0800))
+    {
+      if (!(SFRB & 0x0800))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_f.c
new file mode 100644
index 000000000..533a3c61a
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/17_if0_sfrw_bit_f.c
@@ -0,0 +1,29 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.w r.,32532" } } */
+
+#define SFRA (*((volatile unsigned short*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile unsigned short*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!(SFRA & 0x8000))
+    {
+      if (!(SFRB & 0x8000))
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_0.c
new file mode 100644
index 000000000..3879ed438
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b0 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0x35) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_7.c
new file mode 100644
index 000000000..1b7bb8777
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/20_set_sfrb_bitfield_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b7 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x34;
+  Do ();
+  return (*p == 0xb4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_0.c
new file mode 100644
index 000000000..6f73231c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_0.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#0" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b0 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0xca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_7.c
new file mode 100644
index 000000000..10063e492
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/21_clr_sfrb_bitfield_7.c
@@ -0,0 +1,31 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#7" } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned char *p = (unsigned char *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b7 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xcb;
+  Do ();
+  return (*p == 0x4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_0.c
new file mode 100644
index 000000000..bb8489b6c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_0.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b0)
+    {
+      if (SFRB.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_3.c
new file mode 100644
index 000000000..96b441c04
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_3.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b3)
+    {
+      if (SFRB.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_7.c
new file mode 100644
index 000000000..ad7bebdc6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/22_if1_sfrb_bitfield_7.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b7)
+    {
+      if (SFRB.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xcb;
+  *pB = 0x34;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_0.c
new file mode 100644
index 000000000..dfa59a939
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_0.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b0)
+    {
+      if (!SFRB.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_3.c
new file mode 100644
index 000000000..c311877c7
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_3.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b3)
+    {
+      if (!SFRB.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_7.c
new file mode 100644
index 000000000..2e4eea990
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/23_if0_sfrb_bitfield_7.c
@@ -0,0 +1,41 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "b\[np\] " } } */
+
+typedef struct
+{
+  unsigned char b0:1;
+  unsigned char b1:1;
+  unsigned char b2:1;
+  unsigned char b3:1;
+  unsigned char b4:1;
+  unsigned char b5:1;
+  unsigned char b6:1;
+  unsigned char b7:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned char *pA = (unsigned char *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned char *pB = (unsigned char *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b7)
+    {
+      if (!SFRB.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x34;
+  *pB = 0xcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_0.c
new file mode 100644
index 000000000..d2351681c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_0.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b0 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1235) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_7.c
new file mode 100644
index 000000000..6f1cf87df
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_7.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32532,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b7 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x12b4) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_8.c
new file mode 100644
index 000000000..9de4c0def
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_8.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32533,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b8 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x1334) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_f.c
new file mode 100644
index 000000000..e89757fb6
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/24_set_sfrw_bitfield_f.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "set1 32533,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b15 = 1;
+}
+
+int
+main (void)
+{
+  *p = 0x1234;
+  Do ();
+  return (*p == 0x9234) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_0.c
new file mode 100644
index 000000000..5acd858fc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_0.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b0 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xedca) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_7.c
new file mode 100644
index 000000000..112714e99
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_7.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32532,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b7 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xed4b) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_8.c
new file mode 100644
index 000000000..015f9bc15
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_8.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32533,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b8 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0xeccb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_f.c
new file mode 100644
index 000000000..0c85ffaa9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/25_clr_sfrw_bitfield_f.c
@@ -0,0 +1,39 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "clr1 32533,#7" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFR (*((volatile BitField*)0x7f14))
+unsigned short *p = (unsigned short *) 0x7f14;
+
+void
+Do (void)
+{
+  SFR.b15 = 0;
+}
+
+int
+main (void)
+{
+  *p = 0xedcb;
+  Do ();
+  return (*p == 0x6dcb) ? 0 : 1;
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_0.c
new file mode 100644
index 000000000..d4861b21b
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_0.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bn 32532,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b0)
+    {
+      if (SFRB.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_3.c
new file mode 100644
index 000000000..5318305db
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_3.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bn 32532,#3" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b3)
+    {
+      if (SFRB.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_7.c
new file mode 100644
index 000000000..85b86a0e9
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_7.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32532" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b7)
+    {
+      if (SFRB.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_8.c
new file mode 100644
index 000000000..65412e3f5
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_8.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bn 32533,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b8)
+    {
+      if (SFRB.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_b.c
new file mode 100644
index 000000000..951db3f2f
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_b.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bn 32533,#3" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b11)
+    {
+      if (SFRB.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_f.c
new file mode 100644
index 000000000..b51daa862
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/26_if1_sfrw_bitfield_f.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32533" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (SFRA.b15)
+    {
+      if (SFRB.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0xedcb;
+  *pB = 0x1234;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_0.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_0.c
new file mode 100644
index 000000000..0680d4f03
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_0.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bp 32532,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b0)
+    {
+      if (!SFRB.b0)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_3.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_3.c
new file mode 100644
index 000000000..17f07f907
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_3.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bp 32532,#3" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b3)
+    {
+      if (!SFRB.b3)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_7.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_7.c
new file mode 100644
index 000000000..2c1cab89c
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_7.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32532" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b7)
+    {
+      if (!SFRB.b7)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_8.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_8.c
new file mode 100644
index 000000000..2353cad4e
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_8.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bp 32533,#0" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b8)
+    {
+      if (!SFRB.b8)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_b.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_b.c
new file mode 100644
index 000000000..123cb0605
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_b.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "bp 32533,#3" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b11)
+    {
+      if (!SFRB.b11)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_f.c b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_f.c
new file mode 100644
index 000000000..daf5090d2
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/sfr/27_if0_sfrw_bitfield_f.c
@@ -0,0 +1,49 @@
+/* { dg-options { -nostartfiles below100.o -Tbelow100.ld -O2 } } */
+/* { dg-final { scan-assembler "mov.b r., *32533" } } */
+
+typedef struct
+{
+  unsigned short b0:1;
+  unsigned short b1:1;
+  unsigned short b2:1;
+  unsigned short b3:1;
+  unsigned short b4:1;
+  unsigned short b5:1;
+  unsigned short b6:1;
+  unsigned short b7:1;
+  unsigned short b8:1;
+  unsigned short b9:1;
+  unsigned short b10:1;
+  unsigned short b11:1;
+  unsigned short b12:1;
+  unsigned short b13:1;
+  unsigned short b14:1;
+  unsigned short b15:1;
+} BitField;
+
+#define SFRA (*((volatile BitField*)0x7f14))
+unsigned short *pA = (unsigned short *) 0x7f14;
+#define SFRB (*((volatile BitField*)0x7f10))
+unsigned short *pB = (unsigned short *) 0x7f10;
+
+char *
+Do (void)
+{
+  if (!SFRA.b15)
+    {
+      if (!SFRB.b15)
+	return "Fail";
+      else
+	return "Success";
+    }
+  else
+    return "Fail";
+}
+
+int
+main (void)
+{
+  *pA = 0x1234;
+  *pB = 0xedcb;
+  return Do ()[0] == 'F';
+}
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/xstormy16.exp b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/xstormy16.exp
new file mode 100644
index 000000000..c6ed370dc
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/xstormy16/xstormy16.exp
@@ -0,0 +1,60 @@
+# Copyright (C) 2004-2014 Free Software Foundation, Inc.
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# Tests for the xstormy16
+
+if {![istarget xstormy16-*-*]} {
+    return 0
+}
+
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Assemble the below100.S file which contains
+# support code for the rest of the tests.
+set old-dg-do-what-default "${dg-do-what-default}"
+set dg-do-what-default assemble
+dg-test -keep-output "$srcdir/$subdir/below100.S" "" ""
+set dg-do-what-default run
+
+
+# Main loop.
+foreach testcase [lsort [find $srcdir/$subdir *.c]] {
+    global test_counts
+
+    set base "[file rootname [file tail $testcase]]"
+
+    if ![runtest_file_p $runtests $testcase] {
+        continue
+    }
+
+    set fails_before $test_counts(FAIL,count)
+    dg-test $testcase "--save-temps -fno-inline-functions -L$srcdir/$subdir" ""
+    set fails_after $test_counts(FAIL,count)
+
+    if { $fails_before == $fails_after } {
+        catch "exec rm -f $base.i $base.s $base.o"
+    }
+}
+
+set dg-do-what-default "${old-dg-do-what-default}"
+
+# All done.
+dg-finish