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Diffstat (limited to 'gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c')
-rw-r--r--gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
new file mode 100644
index 000000000..fde62bcbb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/arm/neon/vqRshrun_ns64.c
@@ -0,0 +1,20 @@
+/* Test the `vqRshrun_ns64' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+void test_vqRshrun_ns64 (void)
+{
+ uint32x2_t out_uint32x2_t;
+ int64x2_t arg0_int64x2_t;
+
+ out_uint32x2_t = vqrshrun_n_s64 (arg0_int64x2_t, 1);
+}
+
+/* { dg-final { scan-assembler "vqrshrun\.s64\[ \]+\[dD\]\[0-9\]+, \[qQ\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */