diff options
Diffstat (limited to 'gcc-4.9/gcc/doc/invoke.texi')
| -rw-r--r-- | gcc-4.9/gcc/doc/invoke.texi | 55 |
1 files changed, 48 insertions, 7 deletions
diff --git a/gcc-4.9/gcc/doc/invoke.texi b/gcc-4.9/gcc/doc/invoke.texi index 0324a8571..a74c6c54e 100644 --- a/gcc-4.9/gcc/doc/invoke.texi +++ b/gcc-4.9/gcc/doc/invoke.texi @@ -766,8 +766,8 @@ Objective-C and Objective-C++ Dialects}. @emph{MIPS Options} @gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol --mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 @gol --mips64 -mips64r2 @gol +-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips32r3 -mips32r5 @gol +-mips32r6 -mips64 -mips64r2 -mips64r3 -mips64r5 -mips64r6 @gol -mips16 -mno-mips16 -mflip-mips16 @gol -minterlink-compressed -mno-interlink-compressed @gol -minterlink-mips16 -mno-interlink-mips16 @gol @@ -775,12 +775,15 @@ Objective-C and Objective-C++ Dialects}. -mshared -mno-shared -mplt -mno-plt -mxgot -mno-xgot @gol -mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol -mno-float -msingle-float -mdouble-float @gol +-modd-spreg -mno-odd-spreg @gol -mabs=@var{mode} -mnan=@var{encoding} @gol -mdsp -mno-dsp -mdspr2 -mno-dspr2 @gol -mmcu -mmno-mcu @gol -meva -mno-eva @gol -mvirt -mno-virt @gol +-mxpa -mno-xpa @gol -mmicromips -mno-micromips @gol +-mmsa -mno-msa @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol -mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol @@ -17035,7 +17038,9 @@ Generate code that runs on @var{arch}, which can be the name of a generic MIPS ISA, or the name of a particular processor. The ISA names are: @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4}, -@samp{mips32}, @samp{mips32r2}, @samp{mips64} and @samp{mips64r2}. +@samp{mips32}, @samp{mips32r2}, @samp{mips32r3}, @samp{mips32r5}, +@samp{mips32r6}, @samp{mips64}, @samp{mips64r2}, @samp{mips64r3}, +@samp{mips64r5} and @samp{mips64r6}. The processor names are: @samp{4kc}, @samp{4km}, @samp{4kp}, @samp{4ksc}, @samp{4kec}, @samp{4kem}, @samp{4kep}, @samp{4ksd}, @@ -17051,6 +17056,7 @@ The processor names are: @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, @samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{orion}, +@samp{p5600}, @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400}, @samp{r4600}, @samp{r4650}, @samp{r4700}, @samp{r6000}, @samp{r8000}, @samp{rm7000}, @samp{rm9000}, @@ -17133,9 +17139,17 @@ Equivalent to @option{-march=mips4}. @opindex mips32 Equivalent to @option{-march=mips32}. -@item -mips32r2 -@opindex mips32r2 -Equivalent to @option{-march=mips32r2}. +@item -mips32r3 +@opindex mips32r3 +Equivalent to @option{-march=mips32r3}. + +@item -mips32r5 +@opindex mips32r5 +Equivalent to @option{-march=mips32r5}. + +@item -mips32r6 +@opindex mips32r6 +Equivalent to @option{-march=mips32r6}. @item -mips64 @opindex mips64 @@ -17145,6 +17159,18 @@ Equivalent to @option{-march=mips64}. @opindex mips64r2 Equivalent to @option{-march=mips64r2}. +@item -mips64r3 +@opindex mips64r3 +Equivalent to @option{-march=mips64r3}. + +@item -mips64r5 +@opindex mips64r5 +Equivalent to @option{-march=mips64r5}. + +@item -mips64r6 +@opindex mips64r6 +Equivalent to @option{-march=mips64r6}. + @item -mips16 @itemx -mno-mips16 @opindex mips16 @@ -17205,7 +17231,7 @@ GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with @option{-mabi=32} @option{-mfp64}. This ABI relies on the @code{mthc1} and @code{mfhc1} instructions and is therefore only supported for -MIPS32R2 processors. +MIPS32R2, MIPS32R3 and MIPS32R5 processors. The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64-bit register @@ -17332,6 +17358,15 @@ operations. Assume that the floating-point coprocessor supports double-precision operations. This is the default. +@item -modd-spreg +@itemx -mno-odd-spreg +@opindex modd-spreg +@opindex mno-odd-spreg +Enable the use of odd-numbered single-precision floating-point registers +for the O32 ABI. This is the default for specific processors that are +known to support these registers. The O32 FPXX extension sets +@code{-mno-odd-spreg} by default when targetting generic architectures. + @item -mabs=2008 @itemx -mabs=legacy @opindex mabs=2008 @@ -17471,6 +17506,12 @@ Use (do not use) the MIPS Enhanced Virtual Addressing instructions. @opindex mno-virt Use (do not use) the MIPS Virtualization Application Specific instructions. +@item -mxpa +@itemx -mno-xpa +@opindex mxpa +@opindex mno-xpa +Use (do not use) the MIPS eXtended Physical Address (XPA) instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for |