diff options
Diffstat (limited to 'gcc-4.9/gcc/config/sparc/sparc.h')
| -rw-r--r-- | gcc-4.9/gcc/config/sparc/sparc.h | 51 |
1 files changed, 25 insertions, 26 deletions
diff --git a/gcc-4.9/gcc/config/sparc/sparc.h b/gcc-4.9/gcc/config/sparc/sparc.h index dd2b5ad9c..87f1d82d6 100644 --- a/gcc-4.9/gcc/config/sparc/sparc.h +++ b/gcc-4.9/gcc/config/sparc/sparc.h @@ -106,17 +106,6 @@ extern enum cmodel sparc_cmodel; #define SPARC_DEFAULT_CMODEL CM_32 -/* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO) - which requires the following macro to be true if enabled. Prior to V9, - there are no instructions to even talk about memory synchronization. - Note that the UltraSPARC III processors don't implement RMO, unlike the - UltraSPARC II processors. Niagara, Niagara-2, and Niagara-3 do not - implement RMO either. - - Default to false; for example, Solaris never enables RMO, only ever uses - total memory ordering (TMO). */ -#define SPARC_RELAXED_ORDERING false - /* Do not use the .note.GNU-stack convention by default. */ #define NEED_INDICATE_EXEC_STACK 0 @@ -137,21 +126,22 @@ extern enum cmodel sparc_cmodel; #define TARGET_CPU_hypersparc 3 #define TARGET_CPU_leon 4 #define TARGET_CPU_leon3 5 -#define TARGET_CPU_sparclite 6 -#define TARGET_CPU_f930 6 /* alias */ -#define TARGET_CPU_f934 6 /* alias */ -#define TARGET_CPU_sparclite86x 7 -#define TARGET_CPU_sparclet 8 -#define TARGET_CPU_tsc701 8 /* alias */ -#define TARGET_CPU_v9 9 /* generic v9 implementation */ -#define TARGET_CPU_sparcv9 9 /* alias */ -#define TARGET_CPU_sparc64 9 /* alias */ -#define TARGET_CPU_ultrasparc 10 -#define TARGET_CPU_ultrasparc3 11 -#define TARGET_CPU_niagara 12 -#define TARGET_CPU_niagara2 13 -#define TARGET_CPU_niagara3 14 -#define TARGET_CPU_niagara4 15 +#define TARGET_CPU_leon3v7 6 +#define TARGET_CPU_sparclite 7 +#define TARGET_CPU_f930 7 /* alias */ +#define TARGET_CPU_f934 7 /* alias */ +#define TARGET_CPU_sparclite86x 8 +#define TARGET_CPU_sparclet 9 +#define TARGET_CPU_tsc701 9 /* alias */ +#define TARGET_CPU_v9 10 /* generic v9 implementation */ +#define TARGET_CPU_sparcv9 10 /* alias */ +#define TARGET_CPU_sparc64 10 /* alias */ +#define TARGET_CPU_ultrasparc 11 +#define TARGET_CPU_ultrasparc3 12 +#define TARGET_CPU_niagara 13 +#define TARGET_CPU_niagara2 14 +#define TARGET_CPU_niagara3 15 +#define TARGET_CPU_niagara4 16 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ @@ -239,6 +229,11 @@ extern enum cmodel sparc_cmodel; #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 +#define CPP_CPU32_DEFAULT_SPEC "-D__leon__" +#define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG +#endif + #endif #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) @@ -285,6 +280,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ +%{mcpu=leon3v7:-D__leon__} \ %{mcpu=v9:-D__sparc_v9__} \ %{mcpu=ultrasparc:-D__sparc_v9__} \ %{mcpu=ultrasparc3:-D__sparc_v9__} \ @@ -334,6 +330,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=hypersparc:-Av8} \ %{mcpu=leon:" AS_LEON_FLAG "} \ %{mcpu=leon3:" AS_LEON_FLAG "} \ +%{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ %{mv8plus:-Av8plus} \ %{mcpu=v9:-Av9} \ %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ @@ -1760,8 +1757,10 @@ extern int sparc_indent_opcode; #ifdef HAVE_AS_LEON #define AS_LEON_FLAG "-Aleon" +#define AS_LEONV7_FLAG "-Aleon" #else #define AS_LEON_FLAG "-Av8" +#define AS_LEONV7_FLAG "-Av7" #endif /* We use gcc _mcount for profiling. */ |