diff options
Diffstat (limited to 'gcc-4.9/gcc/config/sparc/sparc.c')
| -rw-r--r-- | gcc-4.9/gcc/config/sparc/sparc.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/gcc-4.9/gcc/config/sparc/sparc.c b/gcc-4.9/gcc/config/sparc/sparc.c index 5b00cca47..f7fc957b4 100644 --- a/gcc-4.9/gcc/config/sparc/sparc.c +++ b/gcc-4.9/gcc/config/sparc/sparc.c @@ -786,9 +786,6 @@ char sparc_hard_reg_printed[8]; #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table #endif -#undef TARGET_RELAXED_ORDERING -#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING - #undef TARGET_OPTION_OVERRIDE #define TARGET_OPTION_OVERRIDE sparc_option_override @@ -1246,6 +1243,7 @@ sparc_option_override (void) { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC }, { TARGET_CPU_leon, PROCESSOR_LEON }, { TARGET_CPU_leon3, PROCESSOR_LEON3 }, + { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 }, { TARGET_CPU_sparclite, PROCESSOR_F930 }, { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X }, { TARGET_CPU_sparclet, PROCESSOR_TSC701 }, @@ -1274,6 +1272,7 @@ sparc_option_override (void) { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU }, { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU }, { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU }, + { "leon3v7", MASK_ISA, MASK_LEON3|MASK_FPU }, { "sparclite", MASK_ISA, MASK_SPARCLITE }, /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */ { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, @@ -1526,6 +1525,7 @@ sparc_option_override (void) sparc_costs = &leon_costs; break; case PROCESSOR_LEON3: + case PROCESSOR_LEON3V7: sparc_costs = &leon3_costs; break; case PROCESSOR_SPARCLET: @@ -6801,28 +6801,30 @@ function_arg_union_value (int size, enum machine_mode mode, int slotno, } /* Used by function_arg and sparc_function_value_1 to implement the conventions - for passing and returning large (BLKmode) vectors. + for passing and returning BLKmode vectors. Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE. - SIZE is the size in bytes of the vector (at least 8 bytes). + SIZE is the size in bytes of the vector. REGNO is the FP hard register the vector will be passed in. */ static rtx function_arg_vector_value (int size, int regno) { - int i, nregs = size / 8; - rtx regs; - - regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); + const int nregs = MAX (1, size / 8); + rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); - for (i = 0; i < nregs; i++) - { + if (size < 8) + XVECEXP (regs, 0, 0) + = gen_rtx_EXPR_LIST (VOIDmode, + gen_rtx_REG (SImode, regno), + const0_rtx); + else + for (int i = 0; i < nregs; i++) XVECEXP (regs, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (DImode, regno + 2*i), GEN_INT (i*8)); - } return regs; } @@ -6868,10 +6870,9 @@ sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode, || (TARGET_ARCH64 && size <= 16)); if (mode == BLKmode) - return function_arg_vector_value (size, - SPARC_FP_ARG_FIRST + 2*slotno); - else - mclass = MODE_FLOAT; + return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno); + + mclass = MODE_FLOAT; } if (TARGET_ARCH32) @@ -7315,10 +7316,9 @@ sparc_function_value_1 (const_tree type, enum machine_mode mode, || (TARGET_ARCH64 && size <= 32)); if (mode == BLKmode) - return function_arg_vector_value (size, - SPARC_FP_ARG_FIRST); - else - mclass = MODE_FLOAT; + return function_arg_vector_value (size, SPARC_FP_ARG_FIRST); + + mclass = MODE_FLOAT; } if (TARGET_ARCH64 && type) |