diff options
Diffstat (limited to 'gcc-4.9/gcc/config/rs6000/vsx.md')
| -rw-r--r-- | gcc-4.9/gcc/config/rs6000/vsx.md | 331 |
1 files changed, 182 insertions, 149 deletions
diff --git a/gcc-4.9/gcc/config/rs6000/vsx.md b/gcc-4.9/gcc/config/rs6000/vsx.md index 6d20eab11..2cf5e7a94 100644 --- a/gcc-4.9/gcc/config/rs6000/vsx.md +++ b/gcc-4.9/gcc/config/rs6000/vsx.md @@ -86,19 +86,26 @@ (V4SF "wf") (V2DI "wd") (V2DF "wd") + (DI "wi") (DF "ws") - (SF "d") + (SF "ww") (V1TI "v") (TI "wt")]) -;; Map the register class used for float<->int conversions +;; Map the register class used for float<->int conversions (floating point side) +;; VSr2 is the preferred register class, VSr3 is any register class that will +;; hold the data (define_mode_attr VSr2 [(V2DF "wd") (V4SF "wf") - (DF "ws")]) + (DF "ws") + (SF "ww") + (DI "wi")]) (define_mode_attr VSr3 [(V2DF "wa") (V4SF "wa") - (DF "ws")]) + (DF "ws") + (SF "ww") + (DI "wi")]) ;; Map the register class for sp<->dp float conversions, destination (define_mode_attr VSr4 [(SF "ws") @@ -106,12 +113,27 @@ (V2DF "wd") (V4SF "v")]) -;; Map the register class for sp<->dp float conversions, destination +;; Map the register class for sp<->dp float conversions, source (define_mode_attr VSr5 [(SF "ws") (DF "f") (V2DF "v") (V4SF "wd")]) +;; The VSX register class that a type can occupy, even if it is not the +;; preferred register class (VSr is the preferred register class that will get +;; allocated first). +(define_mode_attr VSa [(V16QI "wa") + (V8HI "wa") + (V4SI "wa") + (V4SF "wa") + (V2DI "wa") + (V2DF "wa") + (DI "wi") + (DF "ws") + (SF "ww") + (V1TI "wa") + (TI "wt")]) + ;; Same size integer type for floating point data (define_mode_attr VSi [(V4SF "v4si") (V2DF "v2di") @@ -207,6 +229,16 @@ (V2DF "V4DF") (V1TI "V2TI")]) +;; Map register class for 64-bit element in 128-bit vector for direct moves +;; to/from gprs +(define_mode_attr VS_64dm [(V2DF "wk") + (V2DI "wj")]) + +;; Map register class for 64-bit element in 128-bit vector for normal register +;; to register moves +(define_mode_attr VS_64reg [(V2DF "ws") + (V2DI "wi")]) + ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT @@ -235,7 +267,7 @@ ;; The patterns for LE permuted loads and stores come before the general ;; VSX moves so they match first. (define_insn_and_split "*vsx_le_perm_load_<mode>" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>") (match_operand:VSX_LE 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" @@ -258,7 +290,7 @@ (set_attr "length" "8")]) (define_insn_and_split "*vsx_le_perm_load_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") (match_operand:VSX_W 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" @@ -350,7 +382,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") - (match_operand:VSX_LE 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_LE 1 "vsx_register_operand" "+<VSa>"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" [(set_attr "type" "vecstore") @@ -395,7 +427,7 @@ (define_insn "*vsx_le_perm_store_<mode>" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") - (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_W 1 "vsx_register_operand" "+<VSa>"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" [(set_attr "type" "vecstore") @@ -585,8 +617,8 @@ (define_insn "*vsx_mov<mode>" - [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,<VSr>,?wa,*r,v,wZ, v") - (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] + [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?<VSa>,?<VSa>,wQ,?&r,??Y,??r,??r,<VSr>,?<VSa>,*r,v,wZ, v") + (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,<VSa>,Z,<VSa>,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] "VECTOR_MEM_VSX_P (<MODE>mode) && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" @@ -688,36 +720,36 @@ ;; instructions are now combined with the insn for the traditional floating ;; point unit. (define_insn "*vsx_add<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvadd<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_sub<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvsub<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_mul<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvmul<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_mul>")]) (define_insn "*vsx_div<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvdiv<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_div>") @@ -753,8 +785,8 @@ (define_insn "*vsx_tdiv<mode>3_internal" [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x") - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_VSX_TDIV))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>tdiv<VSs> %0,%x1,%x2" @@ -762,8 +794,8 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_fre<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_FRES))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvre<VSs> %x0,%x1" @@ -771,60 +803,60 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_neg<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvneg<VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_abs<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvabs<VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_nabs<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (neg:VSX_F (abs:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa"))))] + (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>"))))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvnabs<VSs> %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_smax<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvmax<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_smin<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvmin<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_sqrt<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvsqrt<VSs> %x0,%x1" [(set_attr "type" "<VStype_sqrt>") (set_attr "fp_type" "<VSfptype_sqrt>")]) (define_insn "*vsx_rsqrte<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_RSQRT))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvrsqrte<VSs> %x0,%x1" @@ -859,7 +891,7 @@ (define_insn "*vsx_tsqrt<mode>2_internal" [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x") - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_VSX_TSQRT))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>tsqrt<VSs> %0,%x1" @@ -901,12 +933,12 @@ [(set_attr "type" "vecdouble")]) (define_insn "*vsx_fms<mode>4" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>") (fma:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,wa,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,wa,0") + (match_operand:VSX_F 1 "vsx_register_operand" "%<VSr>,<VSr>,<VSa>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0") (neg:VSX_F - (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))] + (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "@ xvmsuba<VSs> %x0,%x1,%x2 @@ -916,12 +948,12 @@ [(set_attr "type" "<VStype_mul>")]) (define_insn "*vsx_nfma<mode>4" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?wa,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,<VSr>,?<VSa>,?<VSa>") (neg:VSX_F (fma:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,wa,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,wa,0") - (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,wa"))))] + (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSr>,<VSa>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,0,<VSa>,0") + (match_operand:VSX_F 3 "vsx_register_operand" "0,<VSr>,0,<VSa>"))))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "@ xvnmadda<VSs> %x0,%x1,%x2 @@ -966,27 +998,27 @@ ;; Vector conditional expressions (no scalar version for these instructions) (define_insn "vsx_eq<mode>" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvcmpeq<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_gt<mode>" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvcmpgt<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_ge<mode>" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvcmpge<VSs> %x0,%x1,%x2" [(set_attr "type" "<VStype_simple>") @@ -997,10 +1029,10 @@ (define_insn "*vsx_eq_<mode>_p" [(set (reg:CC 74) (unspec:CC - [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))] + [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (eq:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1010,10 +1042,10 @@ (define_insn "*vsx_gt_<mode>_p" [(set (reg:CC 74) (unspec:CC - [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))] + [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (gt:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1023,10 +1055,10 @@ (define_insn "*vsx_ge_<mode>_p" [(set (reg:CC 74) (unspec:CC - [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?wa"))] + [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (ge:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (<MODE>mode)" @@ -1035,33 +1067,33 @@ ;; Vector select (define_insn "*vsx_xxsel<mode>" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>") (if_then_else:VSX_L - (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa") + (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>") (match_operand:VSX_L 4 "zero_constant" "")) - (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))] + (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "xxsel %x0,%x3,%x2,%x1" [(set_attr "type" "vecperm")]) (define_insn "*vsx_xxsel<mode>_uns" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?<VSa>") (if_then_else:VSX_L - (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa") + (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,<VSa>") (match_operand:VSX_L 4 "zero_constant" "")) - (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")))] + (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "xxsel %x0,%x3,%x2,%x1" [(set_attr "type" "vecperm")]) ;; Copy sign (define_insn "vsx_copysign<mode>3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (unspec:VSX_F - [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa") - (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,wa")] + [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") + (match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_COPYSIGN))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvcpsgn<VSs> %x0,%x2,%x1" @@ -1074,7 +1106,7 @@ ;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX. ;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md. (define_insn "vsx_float<VSi><mode>2" - [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?<VSa>") (float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cvsx<VSc><VSs> %x0,%x1" @@ -1082,7 +1114,7 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_floatuns<VSi><mode>2" - [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?<VSa>") (unsigned_float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cvux<VSc><VSs> %x0,%x1" @@ -1091,7 +1123,7 @@ (define_insn "vsx_fix_trunc<mode><VSi>2" [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>") - (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))] + (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cv<VSs>sx<VSc>s %x0,%x1" [(set_attr "type" "<VStype_simple>") @@ -1099,7 +1131,7 @@ (define_insn "vsx_fixuns_trunc<mode><VSi>2" [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>") - (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))] + (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>cv<VSs>ux<VSc>s %x0,%x1" [(set_attr "type" "<VStype_simple>") @@ -1107,8 +1139,8 @@ ;; Math rounding functions (define_insn "vsx_x<VSv>r<VSs>i" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_VSX_ROUND_I))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>r<VSs>i %x0,%x1" @@ -1116,8 +1148,8 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_x<VSv>r<VSs>ic" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_VSX_ROUND_IC))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>r<VSs>ic %x0,%x1" @@ -1125,16 +1157,16 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_btrunc<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvr<VSs>iz %x0,%x1" [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "*vsx_b2trunc<mode>2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_FRIZ))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "x<VSv>r<VSs>iz %x0,%x1" @@ -1142,8 +1174,8 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_floor<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_FRIM))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvr<VSs>im %x0,%x1" @@ -1151,8 +1183,8 @@ (set_attr "fp_type" "<VSfptype_simple>")]) (define_insn "vsx_ceil<mode>2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>")] UNSPEC_FRIP))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "xvr<VSs>ip %x0,%x1" @@ -1167,8 +1199,8 @@ ;; scalar single precision instructions internally use the double format. ;; Prefer the altivec registers, since we likely will need to do a vperm (define_insn "vsx_<VS_spdp_insn>" - [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?wa") - (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,wa")] + [(set (match_operand:<VS_spdp_res> 0 "vsx_register_operand" "=<VSr4>,?<VSa>") + (unspec:<VS_spdp_res> [(match_operand:VSX_SPDP 1 "vsx_register_operand" "<VSr5>,<VSa>")] UNSPEC_VSX_CVSPDP))] "VECTOR_UNIT_VSX_P (<MODE>mode)" "<VS_spdp_insn> %x0,%x1" @@ -1176,8 +1208,8 @@ ;; xscvspdp, represent the scalar SF type as V4SF (define_insn "vsx_xscvspdp" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa") - (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] + [(set (match_operand:DF 0 "vsx_register_operand" "=ws") + (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDP))] "VECTOR_UNIT_VSX_P (V4SFmode)" "xscvspdp %x0,%x1" @@ -1204,7 +1236,7 @@ ;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs (define_insn "vsx_xscvdpspn" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa") + [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww,?ww") (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")] UNSPEC_VSX_CVDPSPN))] "TARGET_XSCVDPSPN" @@ -1212,16 +1244,16 @@ [(set_attr "type" "fp")]) (define_insn "vsx_xscvspdpn" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa") - (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] + [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?ws") + (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wf,wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) (define_insn "vsx_xscvdpspn_scalar" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")] + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,?wa") + (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww,ww")] UNSPEC_VSX_CVDPSPN))] "TARGET_XSCVDPSPN" "xscvdpspn %x0,%x1" @@ -1309,10 +1341,10 @@ ;; since the xsrdpiz instruction does not truncate the value if the floating ;; point value is < LONG_MIN or > LONG_MAX. (define_insn "*vsx_float_fix_<mode>2" - [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=<VSr>,?<VSa>") (float:VSX_DF (fix:<VSI> - (match_operand:VSX_DF 1 "vsx_register_operand" "<VSr>,?wa"))))] + (match_operand:VSX_DF 1 "vsx_register_operand" "<VSr>,?<VSa>"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && VECTOR_UNIT_VSX_P (<MODE>mode) && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" @@ -1325,10 +1357,10 @@ ;; Build a V2DF/V2DI vector from two scalars (define_insn "vsx_concat_<mode>" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?wa") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSr>,?<VSa>") (vec_concat:VSX_D - (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,wa") - (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa")))] + (match_operand:<VS_scalar> 1 "vsx_register_operand" "ws,<VSa>") + (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,<VSa>")))] "VECTOR_MEM_VSX_P (<MODE>mode)" { if (BYTES_BIG_ENDIAN) @@ -1359,18 +1391,18 @@ ;; xxpermdi for little endian loads and stores. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_xxpermdi2_le_<mode>" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>") (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "wa") + (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" "xxpermdi %x0,%x1,%x1,2" [(set_attr "type" "vecperm")]) (define_insn "*vsx_xxpermdi4_le_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1408,7 +1440,7 @@ ;; lxvd2x for little endian loads. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_lxvd2x2_le_<mode>" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=<VSa>") (vec_select:VSX_LE (match_operand:VSX_LE 1 "memory_operand" "Z") (parallel [(const_int 1) (const_int 0)])))] @@ -1417,7 +1449,7 @@ [(set_attr "type" "vecload")]) (define_insn "*vsx_lxvd2x4_le_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=<VSa>") (vec_select:VSX_W (match_operand:VSX_W 1 "memory_operand" "Z") (parallel [(const_int 2) (const_int 3) @@ -1459,7 +1491,7 @@ (define_insn "*vsx_stxvd2x2_le_<mode>" [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "wa") + (match_operand:VSX_LE 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" "stxvd2x %x1,%y0" @@ -1468,7 +1500,7 @@ (define_insn "*vsx_stxvd2x4_le_<mode>" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 1 "vsx_register_operand" "<VSa>") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1520,11 +1552,12 @@ ;; Set the element of a V2DI/VD2F mode (define_insn "vsx_set_<mode>" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa") - (unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wd,wa") - (match_operand:<VS_scalar> 2 "vsx_register_operand" "ws,wa") - (match_operand:QI 3 "u5bit_cint_operand" "i,i")] - UNSPEC_VSX_SET))] + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?<VSa>") + (unspec:VSX_D + [(match_operand:VSX_D 1 "vsx_register_operand" "wd,<VSa>") + (match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>") + (match_operand:QI 3 "u5bit_cint_operand" "i,i")] + UNSPEC_VSX_SET))] "VECTOR_MEM_VSX_P (<MODE>mode)" { int idx_first = BYTES_BIG_ENDIAN ? 0 : 1; @@ -1549,11 +1582,11 @@ ;; Optimize cases were we can do a simple or direct move. ;; Or see if we can avoid doing the move at all (define_insn "*vsx_extract_<mode>_internal1" - [(set (match_operand:<VS_scalar> 0 "register_operand" "=d,ws,?wa,r") + [(set (match_operand:<VS_scalar> 0 "register_operand" "=d,<VS_64reg>,r") (vec_select:<VS_scalar> - (match_operand:VSX_D 1 "register_operand" "d,wd,wa,wm") + (match_operand:VSX_D 1 "register_operand" "d,<VS_64reg>,<VS_64dm>") (parallel - [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD,wD")])))] + [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE" { int op0_regno = REGNO (operands[0]); @@ -1570,14 +1603,14 @@ return "xxlor %x0,%x1,%x1"; } - [(set_attr "type" "fp,vecsimple,vecsimple,mftgpr") + [(set_attr "type" "fp,vecsimple,mftgpr") (set_attr "length" "4")]) (define_insn "*vsx_extract_<mode>_internal2" - [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=d,ws,ws,?wa") + [(set (match_operand:<VS_scalar> 0 "vsx_register_operand" "=d,<VS_64reg>,<VS_64reg>") (vec_select:<VS_scalar> - (match_operand:VSX_D 1 "vsx_register_operand" "d,wd,wd,wa") - (parallel [(match_operand:QI 2 "u5bit_cint_operand" "wD,wD,i,i")])))] + (match_operand:VSX_D 1 "vsx_register_operand" "d,wd,wd") + (parallel [(match_operand:QI 2 "u5bit_cint_operand" "wD,wD,i")])))] "VECTOR_MEM_VSX_P (<MODE>mode) && (!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE || INTVAL (operands[2]) != VECTOR_ELEMENT_SCALAR_64BIT)" @@ -1605,7 +1638,7 @@ operands[3] = GEN_INT (fldDM); return "xxpermdi %x0,%x1,%x1,%3"; } - [(set_attr "type" "fp,vecsimple,vecperm,vecperm") + [(set_attr "type" "fp,vecsimple,vecperm") (set_attr "length" "4")]) ;; Optimize extracting a single scalar element from memory if the scalar is in @@ -1643,7 +1676,7 @@ (define_insn "*vsx_extract_<mode>_store" [(set (match_operand:<VS_scalar> 0 "memory_operand" "=m,Z,?Z") (vec_select:<VS_scalar> - (match_operand:VSX_D 1 "register_operand" "d,wd,wa") + (match_operand:VSX_D 1 "register_operand" "d,wd,<VSa>") (parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] "VECTOR_MEM_VSX_P (<MODE>mode)" "@ @@ -1666,7 +1699,7 @@ (define_insn_and_split "vsx_extract_v4sf" [(set (match_operand:SF 0 "vsx_register_operand" "=f,f") (vec_select:SF - (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (match_operand:V4SF 1 "vsx_register_operand" "<VSa>,<VSa>") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "O,i")]))) (clobber (match_scratch:V4SF 3 "=X,0"))] "VECTOR_UNIT_VSX_P (V4SFmode)" @@ -1849,9 +1882,9 @@ ;; V2DF/V2DI splat (define_insn "vsx_splat_<mode>" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?<VSa>,?<VSa>,?<VSa>") (vec_duplicate:VSX_D - (match_operand:<VS_scalar> 1 "splat_input_operand" "ws,f,Z,wa,wa,Z")))] + (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,f,Z,<VSa>,<VSa>,Z")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "@ xxpermdi %x0,%x1,%x1,0 @@ -1864,10 +1897,10 @@ ;; V4SF/V4SI splat (define_insn "vsx_xxspltw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") (vec_duplicate:VSX_W (vec_select:<VS_scalar> - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") + (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1880,8 +1913,8 @@ [(set_attr "type" "vecperm")]) (define_insn "vsx_xxspltw_<mode>_direct" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") - (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") + (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>") (match_operand:QI 2 "u5bit_cint_operand" "i,i")] UNSPEC_VSX_XXSPLTW))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1890,11 +1923,11 @@ ;; V4SF/V4SI interleave (define_insn "vsx_xxmrghw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") (vec_select:VSX_W (vec_concat:<VS_double> - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") - (match_operand:VSX_W 2 "vsx_register_operand" "wf,wa")) + (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>") + (match_operand:VSX_W 2 "vsx_register_operand" "wf,<VSa>")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1907,11 +1940,11 @@ [(set_attr "type" "vecperm")]) (define_insn "vsx_xxmrglw_<mode>" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") (vec_select:VSX_W (vec_concat:<VS_double> - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") - (match_operand:VSX_W 2 "vsx_register_operand" "wf,?wa")) + (match_operand:VSX_W 1 "vsx_register_operand" "wf,<VSa>") + (match_operand:VSX_W 2 "vsx_register_operand" "wf,?<VSa>")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_VSX_P (<MODE>mode)" @@ -1925,9 +1958,9 @@ ;; Shift left double by word immediate (define_insn "vsx_xxsldwi_<mode>" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=wa") - (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "wa") - (match_operand:VSX_L 2 "vsx_register_operand" "wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSa>") + (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "<VSa>") + (match_operand:VSX_L 2 "vsx_register_operand" "<VSa>") (match_operand:QI 3 "u5bit_cint_operand" "i")] UNSPEC_VSX_SLDWI))] "VECTOR_MEM_VSX_P (<MODE>mode)" |