diff options
Diffstat (limited to 'gcc-4.9/gcc/config/mips/predicates.md')
-rw-r--r-- | gcc-4.9/gcc/config/mips/predicates.md | 247 |
1 files changed, 247 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/config/mips/predicates.md b/gcc-4.9/gcc/config/mips/predicates.md index 8ac8e0b6a..cdb989ff5 100644 --- a/gcc-4.9/gcc/config/mips/predicates.md +++ b/gcc-4.9/gcc/config/mips/predicates.md @@ -33,10 +33,38 @@ (ior (match_operand 0 "const_arith_operand") (match_operand 0 "register_operand"))) +(define_predicate "const_immlsa_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 1, 4)"))) + +(define_predicate "const_msa_branch_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -1024, 1023)"))) + +(define_predicate "const_uimm3_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) + +(define_predicate "const_uimm4_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) + +(define_predicate "const_uimm5_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) + (define_predicate "const_uimm6_operand" (and (match_code "const_int") (match_test "UIMM6_OPERAND (INTVAL (op))"))) +(define_predicate "const_uimm8_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 255)"))) + +(define_predicate "const_imm5_operand" + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), -16, 15)"))) + (define_predicate "const_imm10_operand" (and (match_code "const_int") (match_test "IMM10_OPERAND (INTVAL (op))"))) @@ -45,6 +73,22 @@ (ior (match_operand 0 "const_imm10_operand") (match_operand 0 "register_operand"))) +(define_predicate "aq10b_operand" + (and (match_code "const_int") + (match_test "mips_signed_immediate_p (INTVAL (op), 10, 0)"))) + +(define_predicate "aq10h_operand" + (and (match_code "const_int") + (match_test "mips_signed_immediate_p (INTVAL (op), 10, 1)"))) + +(define_predicate "aq10w_operand" + (and (match_code "const_int") + (match_test "mips_signed_immediate_p (INTVAL (op), 10, 2)"))) + +(define_predicate "aq10d_operand" + (and (match_code "const_int") + (match_test "mips_signed_immediate_p (INTVAL (op), 10, 3)"))) + (define_predicate "sle_operand" (and (match_code "const_int") (match_test "SMALL_OPERAND (INTVAL (op) + 1)"))) @@ -57,6 +101,14 @@ (and (match_code "const_int,const_double,const_vector") (match_test "op == CONST0_RTX (GET_MODE (op))"))) +(define_predicate "const_m1_operand" + (and (match_code "const_int,const_double,const_vector") + (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) + +(define_predicate "reg_or_m1_operand" + (ior (match_operand 0 "const_m1_operand") + (match_operand 0 "register_operand"))) + (define_predicate "reg_or_0_operand" (ior (and (match_operand 0 "const_0_operand") (not (match_test "TARGET_MIPS16"))) @@ -492,3 +544,198 @@ (define_predicate "non_volatile_mem_operand" (and (match_operand 0 "memory_operand") (not (match_test "MEM_VOLATILE_P (op)")))) + +(define_predicate "const_vector_same_uimm3_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, 0, 7); +}) + +(define_predicate "const_vector_same_v16qi_set_operand" + (match_code "const_vector") +{ + return mips_const_vector_bitimm_set_p (op, mode); +}) + +(define_predicate "const_vector_same_v16qi_clr_operand" + (match_code "const_vector") +{ + return mips_const_vector_bitimm_clr_p (op, mode); +}) + +(define_predicate "const_vector_same_cmpsimm4_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, -16, 15); +}) + +(define_predicate "const_vector_same_cmpuimm4_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, 0, 31); +}) + +(define_predicate "const_vector_same_simm10_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, -1024, 1023); +}) + +(define_predicate "const_vector_same_uimm4_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, 0, 15); +}) + +(define_predicate "const_vector_same_v8hi_set_operand" + (match_code "const_vector") +{ + return mips_const_vector_bitimm_set_p (op, mode); +}) + +(define_predicate "const_vector_same_v8hi_clr_operand" + (match_code "const_vector") +{ + return mips_const_vector_bitimm_clr_p (op, mode); +}) + +(define_predicate "const_vector_same_v4si_set_operand" + (match_code "const_vector") +{ + return mips_const_vector_bitimm_set_p (op, mode); +}) + +(define_predicate "const_vector_same_v4si_clr_operand" + (match_code "const_vector") +{ + return mips_const_vector_bitimm_clr_p (op, mode); +}) + +(define_predicate "const_vector_same_uimm6_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, 0, 63); +}) + +(define_predicate "const_vector_same_v2di_set_operand" + (match_code "const_vector") +{ + return mips_const_vector_bitimm_set_p (op, mode); +}) + +(define_predicate "const_vector_same_v2di_clr_operand" + (match_code "const_vector") +{ + return mips_const_vector_bitimm_clr_p (op, mode); +}) + +(define_predicate "const_vector_same_ximm5_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, -31, 31); +}) + +(define_predicate "const_vector_same_simm5_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, -32, 0); +}) + +(define_predicate "const_vector_same_uimm5_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, 0, 31); +}) + +(define_predicate "const_vector_same_uimm8_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_int_p (op, mode, 0, 255); +}) + +(define_predicate "const_vector_same_byte_operand" + (match_code "const_vector") +{ + return mips_const_vector_same_byte_p (op, mode); +}) + +(define_predicate "reg_or_vector_same_ximm5_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_ximm5_operand"))) + +(define_predicate "reg_or_vector_same_simm5_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_simm5_operand"))) + +(define_predicate "reg_or_vector_same_uimm5_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm5_operand"))) + +(define_predicate "reg_or_vector_same_uimm3_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm3_operand"))) + +(define_predicate "reg_or_vector_same_v16qi_set_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_v16qi_set_operand"))) + +(define_predicate "reg_or_vector_same_v16qi_clr_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_v16qi_clr_operand"))) + +(define_predicate "reg_or_vector_same_uimm4_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm4_operand"))) + +(define_predicate "reg_or_vector_same_v8hi_set_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_v8hi_set_operand"))) + +(define_predicate "reg_or_vector_same_v8hi_clr_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_v8hi_clr_operand"))) + +(define_predicate "reg_or_vector_same_v4si_set_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_v4si_set_operand"))) + +(define_predicate "reg_or_vector_same_v4si_clr_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_v4si_clr_operand"))) + +(define_predicate "reg_or_vector_same_uimm6_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm6_operand"))) + +(define_predicate "reg_or_vector_same_v2di_set_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_v2di_set_operand"))) + +(define_predicate "reg_or_vector_same_v2di_clr_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_v2di_clr_operand"))) + +(define_predicate "reg_or_vector_same_uimm8_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm8_operand"))) + +(define_predicate "reg_or_vector_same_byte_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_byte_operand"))) + +(define_predicate "reg_or_vector_same_bitumm3_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm3_operand"))) + +(define_predicate "reg_or_vector_same_bituimm4_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm4_operand"))) + +(define_predicate "reg_or_vector_same_bituimm5_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm5_operand"))) + +(define_predicate "reg_or_vector_same_bituimm6_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "const_vector_same_uimm6_operand"))) + |