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-rw-r--r--gcc-4.9/gcc/config/mips/predicates.md41
1 files changed, 39 insertions, 2 deletions
diff --git a/gcc-4.9/gcc/config/mips/predicates.md b/gcc-4.9/gcc/config/mips/predicates.md
index cdb989ff5..3a08e59cf 100644
--- a/gcc-4.9/gcc/config/mips/predicates.md
+++ b/gcc-4.9/gcc/config/mips/predicates.md
@@ -101,6 +101,10 @@
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONST0_RTX (GET_MODE (op))")))
+(define_predicate "const_yi_operand"
+ (and (match_code "const_vector")
+ (match_test "mips_const_vector_same_int_p (op, mode, -1024, 1023)")))
+
(define_predicate "const_m1_operand"
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONSTM1_RTX (GET_MODE (op))")))
@@ -114,6 +118,12 @@
(not (match_test "TARGET_MIPS16")))
(match_operand 0 "register_operand")))
+(define_predicate "reg_or_0yi_operand"
+ (ior (and (ior (match_operand 0 "const_0_operand")
+ (match_operand 0 "const_yi_operand"))
+ (match_test "TARGET_MSA"))
+ (match_operand 0 "register_operand")))
+
(define_predicate "const_1_operand"
(and (match_code "const_int,const_double,const_vector")
(match_test "op == CONST1_RTX (GET_MODE (op))")))
@@ -122,6 +132,23 @@
(ior (match_operand 0 "const_1_operand")
(match_operand 0 "register_operand")))
+;; These are used in vec_merge, hence accept bitmask as const_int.
+(define_predicate "const_exp_2_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 1)")))
+
+(define_predicate "const_exp_4_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 3)")))
+
+(define_predicate "const_exp_8_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 7)")))
+
+(define_predicate "const_exp_16_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 15)")))
+
;; This is used for indexing into vectors, and hence only accepts const_int.
(define_predicate "const_0_or_1_operand"
(and (match_code "const_int")
@@ -523,7 +550,18 @@
(match_code "eq,ne,lt,ltu,ge,geu"))
(define_predicate "order_operator"
- (match_code "lt,ltu,le,leu,ge,geu,gt,gtu"))
+ (match_code "lt,ltu,le,leu,ge,geu,gt,gtu")
+{
+ if (XEXP (op, 1) == const0_rtx)
+ return true;
+
+ if (TARGET_CB_MAYBE
+ && (GET_CODE (op) == LT || GET_CODE (op) == LTU
+ || GET_CODE (op) == GE || GET_CODE (op) == GEU))
+ return true;
+
+ return false;
+})
;; For NE, cstore uses sltu instructions in which the first operand is $0.
;; This isn't possible in mips16 code.
@@ -738,4 +776,3 @@
(define_predicate "reg_or_vector_same_bituimm6_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "const_vector_same_uimm6_operand")))
-