diff options
Diffstat (limited to 'gcc-4.9/gcc/config/mips/mips-msa.md')
| -rw-r--r-- | gcc-4.9/gcc/config/mips/mips-msa.md | 1373 |
1 files changed, 866 insertions, 507 deletions
diff --git a/gcc-4.9/gcc/config/mips/mips-msa.md b/gcc-4.9/gcc/config/mips/mips-msa.md index 37f5fcab5..b2da26ddb 100644 --- a/gcc-4.9/gcc/config/mips/mips-msa.md +++ b/gcc-4.9/gcc/config/mips/mips-msa.md @@ -22,8 +22,6 @@ ;; (define_c_enum "unspec" [ - UNSPEC_MSA_ADDVI - UNSPEC_MSA_ANDI_B UNSPEC_MSA_ASUB_S UNSPEC_MSA_ASUB_U UNSPEC_MSA_AVE_S @@ -52,8 +50,6 @@ UNSPEC_MSA_BZ UNSPEC_MSA_CFCMSA UNSPEC_MSA_CMPI - UNSPEC_MSA_COPY_S - UNSPEC_MSA_COPY_U UNSPEC_MSA_CTCMSA UNSPEC_MSA_DOTP_S UNSPEC_MSA_DOTP_U @@ -72,11 +68,8 @@ UNSPEC_MSA_FFINT_U UNSPEC_MSA_FFQL UNSPEC_MSA_FFQR - UNSPEC_MSA_FILL UNSPEC_MSA_FLOG2 - UNSPEC_MSA_FMAX UNSPEC_MSA_FMAX_A - UNSPEC_MSA_FMIN UNSPEC_MSA_FMIN_A UNSPEC_MSA_FRCP UNSPEC_MSA_FRINT @@ -101,23 +94,12 @@ UNSPEC_MSA_HADD_U UNSPEC_MSA_HSUB_S UNSPEC_MSA_HSUB_U - UNSPEC_MSA_ILVEV - UNSPEC_MSA_ILVL - UNSPEC_MSA_ILVOD - UNSPEC_MSA_ILVR - UNSPEC_MSA_INSERT - UNSPEC_MSA_INSVE - UNSPEC_MSA_LD0 UNSPEC_MSA_MADD_Q UNSPEC_MSA_MADDR_Q UNSPEC_MSA_MAX_A - UNSPEC_MSA_MAX_S - UNSPEC_MSA_MAX_U UNSPEC_MSA_MAXI_S UNSPEC_MSA_MAXI_U UNSPEC_MSA_MIN_A - UNSPEC_MSA_MIN_S - UNSPEC_MSA_MIN_U UNSPEC_MSA_MINI_S UNSPEC_MSA_MINI_U UNSPEC_MSA_MSUB_Q @@ -161,11 +143,15 @@ ]) ;; Attributes to categorize MSA instructions based on execution units -(define_attr "msa_execunit" +(define_attr "msa_execunit" "unknown, msa_eu_div, msa_eu_float2, msa_eu_float2_l, - msa_eu_float4, msa_eu_float5, msa_eu_float8, msa_eu_logic, - msa_eu_logic3, msa_eu_logic_l, msa_eu_mult, msa_eu_cmp, - msa_eu_store4, msa_eu_int_add, msa_eu_fdiv" + msa_eu_float4, msa_eu_float5, msa_eu_float8, msa_eu_logic, + msa_eu_logic3, msa_eu_logic_l, msa_eu_mult, msa_eu_cmp, + msa_eu_store4, msa_eu_int_add, msa_eu_fdiv, msa_eu_logic_l2, msa_eu_logic2" + (const_string "unknown")) + +(define_attr "datafmt" + "unknown, d, w, h, b" (const_string "unknown")) ;; All vector modes with 128 bits. @@ -179,17 +165,16 @@ (define_mode_iterator IMSA [V2DI V4SI V8HI V16QI]) ;; mode that can combine a copy+insert into insve. -;; note V2DI is excluded because it split if !TARGET_64 -(define_mode_iterator INSVE [V4SI V8HI V16QI]) +(define_mode_iterator INSVE [V2DI V4SI]) -;; mode that can be combine copy+inset with subreg info insve. +;; mode that can be combine copy+insert with subreg info insve. (define_mode_iterator INSVE_2 [V8HI V16QI]) -;; As IMSA but excludeds V16QI. +;; As IMSA but excludes V16QI. (define_mode_iterator IMSA_X [V2DI V4SI V8HI]) -;; Only used with insert. -(define_mode_iterator MSA_3 [V16QI V8HI V2DF V4SF]) +;; As IMSA but excludes V2DI +(define_mode_iterator IMSA_X2 [V4SI V8HI V16QI]) ;; Only integer modes for fixed-point madd_q/maddr_q. (define_mode_iterator QMSA [V4SI V8HI]) @@ -203,18 +188,29 @@ ;; Only used in spliters (define_mode_iterator SPLIT [V2DI V2DF]) -;; Only used with SPILT iteraror +(define_mode_attr DMSA + [(V2DI "V4DI") + (V4SI "V8SI") + (V8HI "V16HI") + (V16QI "V32QI")]) + +;; Only used with SPLIT iterator (define_mode_attr predicate [(V2DI "reg_or_0") (V2DF "register")]) -(define_mode_attr VHALFMODE +(define_mode_attr VHALFMODE [(V8HI "V16QI") (V4SI "V8HI") (V2DI "V4SI") (V2DF "V4SF")]) -;; The attribute give the integer vector mode with same size. +(define_mode_attr VDMODE + [(V4SI "V2DI") + (V8HI "V4SI") + (V16QI "V8HI")]) + +;; The attribute gives the integer vector mode with same size. (define_mode_attr VIMODE [(V2DF "V2DI") (V4SF "V4SI") @@ -241,7 +237,7 @@ (V8HI "SI") (V16QI "SI")]) -;; This attribute qives suffix for MSA instructions. +;; This attribute gives suffix for MSA instructions. (define_mode_attr msafmt [(V2DF "d") (V4SF "w") @@ -255,8 +251,8 @@ [(V2DF "d") (V4SF "s")]) -;; This attribute qives define_insn suffix for MSA instructions -;; with need distinction between integer and floating point. +;; This attribute gives define_insn suffix for MSA instructions with need +;; distinction between integer and floating point. (define_mode_attr msafmt_f [(V2DF "d_f") (V4SF "w_f") @@ -272,8 +268,8 @@ (V8HI "15") (V16QI "7")]) -;; This is used to form an immediate operand constraint -;; using "const_<indeximm>_operand". +;; This is used to form an immediate operand constraint using +;; "const_<indeximm>_operand". (define_mode_attr indeximm [(V2DF "0_or_1") (V4SF "0_to_3") @@ -282,19 +278,27 @@ (V8HI "uimm3") (V16QI "uimm4")]) -;; This attribute is used to form the MODE for reg_or_0_operand -;; constraint. -(define_mode_attr REGOR0 - [(V2DF "DF") - (V4SF "SF") - (V2DI "DI") +;; To represent bitmask needed for vec_merge using "const_<bitmask>_operand". +(define_mode_attr bitmask + [(V2DF "exp_2") + (V4SF "exp_4") + (V2DI "exp_2") + (V4SI "exp_4") + (V8HI "exp_8") + (V16QI "exp_16")]) + +;; This attribute is used to form the MODE of an input operand +;; when some builtins (insert snd fill) take an input operand other than +;; UNITMODE mode. See the msa_insert and msa_fill for an examples. +(define_mode_attr EXCEPT + [(V2DI "DI") (V4SI "SI") (V8HI "SI") (V16QI "SI")]) -;; This attribute used to form an immediate operand constraint -;; using "const_<bitimm>_operand" -(define_mode_attr bitimm +;; This attribute used to form an immediate operand constraint using +;; "const_<bitimm>_operand". +(define_mode_attr bitimm [(V16QI "uimm3") (V8HI "uimm4") (V4SI "uimm5") @@ -310,6 +314,117 @@ DONE; }) +(define_mode_attr hmsafmt + [(V2DI "w") + (V4SI "h") + (V8HI "b")]) + +(define_expand "fixuns_trunc<FMSA:mode><mode_i>2" + [(set (match_operand:<VIMODE> 0 "register_operand" "=f") + (unsigned_fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))] + "ISA_HAS_MSA" + { + emit_insn (gen_msa_ftrunc_u_<msafmt> (operands[0], operands[1])); + DONE; + }) + +(define_expand "fix_trunc<FMSA:mode><mode_i>2" + [(set (match_operand:<VIMODE> 0 "register_operand" "=f") + (fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))] + "ISA_HAS_MSA" + { + emit_insn (gen_msa_ftrunc_s_<msafmt> (operands[0], operands[1])); + DONE; + }) + +(define_expand "vec_pack_trunc_v2df" + [(set (match_operand:V4SF 0 "register_operand") + (vec_concat:V4SF + (float_truncate:V2SF (match_operand:V2DF 1 "register_operand")) + (float_truncate:V2SF (match_operand:V2DF 2 "register_operand"))))] + "ISA_HAS_MSA" + "") + +;; pckev pattern with implicit type conversion. +(define_insn "vec_pack_trunc_<mode>" + [(set (match_operand:<VHALFMODE> 0 "register_operand" "=f") + (unspec:<VHALFMODE> [(match_operand:IMSA_X 1 "register_operand" "f") + (match_operand:IMSA_X 2 "register_operand" "f")] + UNSPEC_MSA_PCKEV))] + "ISA_HAS_MSA" + "pckev.<hmsafmt>\t%w0,%w2,%w1" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_expand "vec_unpacks_hi_v4sf" + [(set (match_operand:V2DF 0 "register_operand" "=f") + (float_extend:V2DF + (vec_select:V2SF + (match_operand:V4SF 1 "register_operand" "f") + (parallel [(const_int 0) (const_int 1)]) + )))] + "ISA_HAS_MSA" + { + if (BYTES_BIG_ENDIAN) + emit_insn (gen_msa_fexupr_d (operands[0], operands[1])); + else + emit_insn (gen_msa_fexupl_d (operands[0], operands[1])); + DONE; + }) + +(define_expand "vec_unpacks_lo_v4sf" + [(set (match_operand:V2DF 0 "register_operand" "=f") + (float_extend:V2DF + (vec_select:V2SF + (match_operand:V4SF 1 "register_operand" "f") + (parallel [(const_int 0) (const_int 1)]) + )))] + "ISA_HAS_MSA" + { + if (BYTES_BIG_ENDIAN) + emit_insn (gen_msa_fexupl_d (operands[0], operands[1])); + else + emit_insn (gen_msa_fexupr_d (operands[0], operands[1])); + DONE; + }) + +(define_expand "vec_unpacks_hi_<mode>" + [(set (match_operand:<VDMODE> 0 "register_operand") + (match_operand:IMSA_X2 1 "register_operand"))] + "ISA_HAS_MSA" + { + mips_expand_vec_unpack (operands, false/*unsigned_p*/, true/*high_p*/); + DONE; + }) + +(define_expand "vec_unpacks_lo_<mode>" + [(set (match_operand:<VDMODE> 0 "register_operand") + (match_operand:IMSA_X2 1 "register_operand"))] + "ISA_HAS_MSA" + { + mips_expand_vec_unpack (operands, false/*unsigned_p*/, false/*high_p*/); + DONE; + }) + +(define_expand "vec_unpacku_hi_<mode>" + [(set (match_operand:<VDMODE> 0 "register_operand") + (match_operand:IMSA_X2 1 "register_operand"))] + "ISA_HAS_MSA" + { + mips_expand_vec_unpack (operands, true/*unsigned_p*/, true/*high_p*/); + DONE; + }) + +(define_expand "vec_unpacku_lo_<mode>" + [(set (match_operand:<VDMODE> 0 "register_operand") + (match_operand:IMSA_X2 1 "register_operand"))] + "ISA_HAS_MSA" + { + mips_expand_vec_unpack (operands, true/*unsigned_p*/, false/*high_p*/); + DONE; + }) + (define_expand "vec_extract<mode>" [(match_operand:<UNITMODE> 0 "register_operand") (match_operand:IMSA 1 "register_operand") @@ -358,12 +473,12 @@ (define_expand "vec_set<mode>" [(match_operand:IMSA 0 "register_operand") - (match_operand:<UNITMODE> 1 "register_operand") + (match_operand:<UNITMODE> 1 "reg_or_0_operand") (match_operand 2 "const_<indeximm>_operand")] "ISA_HAS_MSA" { - emit_insn (gen_msa_insert_<msafmt> (operands[0], operands[0], operands[2], - operands[1])); + emit_insn (gen_msa_insert_<msafmt>_insn (operands[0], operands[1], + operands[0], GEN_INT(1 << INTVAL (operands[2])))); DONE; }) @@ -373,8 +488,8 @@ (match_operand 2 "const_<indeximm>_operand")] "ISA_HAS_MSA" { - emit_insn (gen_msa_insve_<msafmt_f>_s (operands[0], operands[0], operands[2], - operands[1])); + emit_insn (gen_msa_insve_<msafmt_f>_s (operands[0], operands[0], + GEN_INT(1 << INTVAL (operands[2])), operands[1])); DONE; }) @@ -391,7 +506,7 @@ == GET_MODE_NUNITS (<IMSA:MODE>mode))" { mips_expand_vec_cond_expr (<MSA_2:MODE>mode, - <MSA_2:VIMODE>mode, + <MSA_2:VIMODE>mode, operands, gen_and<MSA_2:mode_i>3, gen_msa_nor_v_<MSA_2:msafmt>, @@ -420,58 +535,93 @@ DONE; }) -(define_insn "msa_insert_<msafmt>" +;; Note used directly by builtins but via the following define_expand. +(define_insn "msa_insert_<msafmt>_insn" [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") - (match_operand 2 "const_<indeximm>_operand" "") - (match_operand:<REGOR0> 3 "reg_or_0_operand" "dJ")] - UNSPEC_MSA_INSERT))] + (vec_merge:IMSA (vec_duplicate:IMSA + (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ")) + (match_operand:IMSA 2 "register_operand" "0") + (match_operand 3 "const_<bitmask>_operand" "")))] "ISA_HAS_MSA" - "insert.<msafmt>\t%w0[%2],%z3" - [(set_attr "type" "mtc") - (set_attr "mode" "TI") + "insert.<msafmt>\t%w0[%K3],%z1" + [(set_attr "type" "mtc") + (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic_l")]) -; Similar to msa_insert_<msafmt> but with <UNITMODE>mode for operand 3. -;; Note that insert.d and insert.d_f will be split later if !TARGET_64BIT. +;; Expand builtin catoring for HImode and QImode which take SImode. +(define_expand "msa_insert_<msafmt>" + [(match_operand:IMSA 0 "register_operand") + (match_operand:IMSA 1 "register_operand") + (match_operand 2 "const_<indeximm>_operand") + (match_operand:<EXCEPT> 3 "reg_or_0_operand")] + "ISA_HAS_MSA" +{ + if ((GET_MODE_SIZE (<UNITMODE>mode) < GET_MODE_SIZE (<EXCEPT>mode)) + && (REG_P (operands[3]) || (GET_CODE (operands[3]) == SUBREG + && REG_P (SUBREG_REG (operands[3]))))) + { + unsigned int offset = GET_MODE_SIZE (<EXCEPT>mode) + - GET_MODE_SIZE (<UNITMODE>mode); + operands[3] = simplify_gen_subreg (<UNITMODE>mode, operands[3], + GET_MODE (operands[3]), + BYTES_BIG_ENDIAN ? offset : 0); + } + emit_insn (gen_msa_insert_<msafmt>_insn (operands[0], operands[3], + operands[1], GEN_INT(1 << INTVAL (operands[2])))); + DONE; +}) + +(define_expand "msa_insert_<msafmt_f>" + [(match_operand:FMSA 0 "register_operand") + (match_operand:FMSA 1 "register_operand") + (match_operand 2 "const_<indeximm>_operand") + (match_operand:<UNITMODE> 3 "reg_or_0_operand")] + "ISA_HAS_MSA" +{ + emit_insn (gen_msa_insert_<msafmt_f>_insn (operands[0], operands[3], + operands[1], GEN_INT(1 << INTVAL (operands[2])))); + DONE; +}) -(define_insn "*msa_insert_<msafmt_f>" - [(set (match_operand:MSA_3 0 "register_operand" "=f") - (unspec:MSA_3 [(match_operand:MSA_3 1 "register_operand" "0") - (match_operand 2 "const_<indeximm>_operand" "") - (match_operand:<UNITMODE> 3 "reg_or_0_operand" "dJ")] - UNSPEC_MSA_INSERT))] +(define_insn "msa_insert_<msafmt_f>_insn" + [(set (match_operand:FMSA 0 "register_operand" "=f") + (vec_merge:FMSA (vec_duplicate:FMSA + (match_operand:<UNITMODE> 1 "register_operand" "d")) + (match_operand:FMSA 2 "register_operand" "0") + (match_operand 3 "const_<bitmask>_operand" "")))] "ISA_HAS_MSA" - "insert.<msafmt>\t%w0[%2],%z3" + "insert.<msafmt>\t%w0[%K3],%z1" [(set_attr "type" "mtc") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic_l")]) (define_split [(set (match_operand:SPLIT 0 "register_operand") - (unspec:SPLIT [(match_operand:SPLIT 1 "register_operand") - (match_operand 2 "const_0_or_1_operand") - (match_operand:<UNITMODE> 3 "<SPLIT:predicate>_operand")] - UNSPEC_MSA_INSERT))] + (vec_merge:SPLIT + (vec_duplicate:SPLIT + (match_operand:<UNITMODE> 1 "<SPLIT:predicate>_operand")) + (match_operand:SPLIT 2 "register_operand") + (match_operand 3 "const_<bitmask>_operand")))] "reload_completed && TARGET_MSA && !TARGET_64BIT" [(const_int 0)] { - mips_split_msa_insert_d (operands[0], operands[1], operands[2], operands[3]); + mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]); DONE; }) ;; Used by combine to convert a copy_s + insert into an insve (define_insn "msa_insve_s_insn_<msafmt>" [(set (match_operand:INSVE 0 "register_operand" "=f") - (unspec:INSVE [(match_operand:INSVE 1 "register_operand" "0") - (match_operand 2 "const_<indeximm>_operand" "") - (unspec:<RES> - [(match_operand:INSVE 3 "register_operand" "f") - (match_operand 4 "const_0_operand" "") - ] UNSPEC_MSA_COPY_S) - ] UNSPEC_MSA_INSERT))] + (vec_merge:INSVE + (vec_duplicate:INSVE + (sign_extend:<UNITMODE> + (vec_select:<UNITMODE> + (match_operand:INSVE 3 "register_operand" "f") + (parallel [(match_operand 4 "const_0_operand" "")])))) + (match_operand:INSVE 1 "register_operand" "0") + (match_operand 2 "const_<bitmask>_operand" "")))] "ISA_HAS_MSA" - "insve.<msafmt>\t%w0[%2],%w3[0]" + "insve.<msafmt>\t%w0[%K2],%w3[0]" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic_l")]) @@ -479,15 +629,16 @@ ;; Used by combine to convert a copy_u + insert into an insve (define_insn "msa_insve_u_insn_<msafmt>" [(set (match_operand:INSVE 0 "register_operand" "=f") - (unspec:INSVE [(match_operand:INSVE 1 "register_operand" "0") - (match_operand 2 "const_<indeximm>_operand" "") - (unspec:<RES> - [(match_operand:INSVE 3 "register_operand" "f") - (match_operand 4 "const_0_operand" "") - ] UNSPEC_MSA_COPY_U) - ] UNSPEC_MSA_INSERT))] + (vec_merge:INSVE + (vec_duplicate:INSVE + (zero_extend:<UNITMODE> + (vec_select:<UNITMODE> + (match_operand:INSVE 3 "register_operand" "f") + (parallel [(match_operand 4 "const_0_operand" "")])))) + (match_operand:INSVE 1 "register_operand" "0") + (match_operand 2 "const_<bitmask>_operand" "")))] "ISA_HAS_MSA" - "insve.<msafmt>\t%w0[%2],%w3[0]" + "insve.<msafmt>\t%w0[%K2],%w3[0]" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic_l")]) @@ -495,16 +646,17 @@ ;; Used by combine to convert a copy_s + insert with subreg into an insve (define_insn "*msa_insve_sext_insn_<msafmt>" [(set (match_operand:INSVE_2 0 "register_operand" "=f") - (unspec:INSVE_2 [(match_operand:INSVE_2 1 "register_operand" "0") - (match_operand 2 "const_<indeximm>_operand" "") - (subreg:<UNITMODE> - (unspec:<RES> - [(match_operand:INSVE_2 3 "register_operand" "f") - (match_operand 4 "const_0_operand" "") - ] UNSPEC_MSA_COPY_S) 0) - ] UNSPEC_MSA_INSERT))] + (vec_merge:INSVE_2 + (vec_duplicate:INSVE_2 + (subreg:<UNITMODE> + (sign_extend:<RES> + (vec_select:<UNITMODE> + (match_operand:INSVE_2 3 "register_operand" "f") + (parallel [(match_operand 4 "const_0_operand" "")]))) 0)) + (match_operand:INSVE_2 1 "register_operand" "0") + (match_operand 2 "const_<bitmask>_operand" "")))] "ISA_HAS_MSA" - "insve.<msafmt>\t%w0[%2],%w3[0]" + "insve.<msafmt>\t%w0[%K2],%w3[0]" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic_l")]) @@ -512,28 +664,44 @@ ;; Used by combine to convert a copy_u + insert with subreg into an insve (define_insn "*msa_insve_zext_insn_<msafmt>" [(set (match_operand:INSVE_2 0 "register_operand" "=f") - (unspec:INSVE_2 [(match_operand:INSVE_2 1 "register_operand" "0") - (match_operand 2 "const_<indeximm>_operand" "") - (subreg:<UNITMODE> - (unspec:<RES> - [(match_operand:INSVE_2 3 "register_operand" "f") - (match_operand 4 "const_0_operand" "") - ] UNSPEC_MSA_COPY_U) 0) - ] UNSPEC_MSA_INSERT))] + (vec_merge:INSVE_2 + (vec_duplicate:INSVE_2 + (subreg:<UNITMODE> + (zero_extend:<RES> + (vec_select:<RES> + (match_operand:INSVE_2 3 "register_operand" "f") + (parallel [(match_operand 4 "const_0_operand" "")]))) 0)) + (match_operand:INSVE_2 1 "register_operand" "0") + (match_operand 2 "const_<bitmask>_operand" "")))] "ISA_HAS_MSA" - "insve.<msafmt>\t%w0[%2],%w3[%4]" + "insve.<msafmt>\t%w0[%K2],%w3[0]" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic_l")]) -(define_insn "msa_insve_<msafmt_f>" - [(set (match_operand:MSA 0 "register_operand" "=f") - (unspec:MSA [(match_operand:MSA 1 "register_operand" "0") - (match_operand 2 "const_<indeximm>_operand" "") - (match_operand:MSA 3 "register_operand" "f")] - UNSPEC_MSA_INSVE))] +(define_expand "msa_insve_<msafmt_f>" + [(set (match_operand:MSA 0 "register_operand") + (vec_merge:MSA (vec_duplicate:MSA + (vec_select:<UNITMODE> + (match_operand:MSA 3 "register_operand") + (parallel [(const_int 0)]))) + (match_operand:MSA 1 "register_operand") + (match_operand 2 "const_<indeximm>_operand")))] "ISA_HAS_MSA" - "insve.<msafmt>\t%w0[%2],%w3[0]" + { + operands[2] = GEN_INT ((1 << INTVAL (operands[2]))); + }) + +(define_insn "msa_insve_<msafmt_f>_insn" + [(set (match_operand:MSA 0 "register_operand" "=f") + (vec_merge:MSA (vec_duplicate:MSA + (vec_select:<UNITMODE> + (match_operand:MSA 3 "register_operand" "f") + (parallel [(const_int 0)]))) + (match_operand:MSA 1 "register_operand" "0") + (match_operand 2 "const_<bitmask>_operand" "")))] + "ISA_HAS_MSA" + "insve.<msafmt>\t%w0[%K2],%w3[0]" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic_l")]) @@ -541,12 +709,12 @@ ;; operand 3 is a scalar (define_insn "msa_insve_<msafmt>_f_s" [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "0") - (match_operand 2 "const_<indeximm>_operand" "") - (match_operand:<UNITMODE> 3 "register_operand" "f")] - UNSPEC_MSA_INSVE))] + (vec_merge:FMSA (vec_duplicate:FMSA + (match_operand:<UNITMODE> 3 "register_operand" "f")) + (match_operand:FMSA 1 "register_operand" "0") + (match_operand 2 "const_<bitmask>_operand" "")))] "ISA_HAS_MSA" - "insve.<msafmt>\t%w0[%2],%w3[0]" + "insve.<msafmt>\t%w0[%K2],%w3[0]" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic_l")]) @@ -554,9 +722,10 @@ ;; Note that copy_s.d and copy_s.d_f will be split later if !TARGET_64BIT. (define_insn "msa_copy_s_<msafmt_f>" [(set (match_operand:<RES> 0 "register_operand" "=d") - (unspec:<RES> [(match_operand:MSA 1 "register_operand" "f") - (match_operand 2 "const_<indeximm>_operand" "")] - UNSPEC_MSA_COPY_S))] + (sign_extend:<RES> + (vec_select:<UNITMODE> + (match_operand:MSA 1 "register_operand" "f") + (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))] "ISA_HAS_MSA" "copy_s.<msafmt>\t%0,%w1[%2]" [(set_attr "type" "mfc") @@ -565,9 +734,10 @@ (define_split [(set (match_operand:<UNITMODE> 0 "register_operand") - (unspec:<UNITMODE> [(match_operand:SPLIT 1 "register_operand") - (match_operand 2 "const_0_or_1_operand")] - UNSPEC_MSA_COPY_S))] + (sign_extend:<UNITMODE> + (vec_select:<UNITMODE> + (match_operand:SPLIT 1 "register_operand") + (parallel [(match_operand 2 "const_0_or_1_operand")]))))] "reload_completed && TARGET_MSA && !TARGET_64BIT" [(const_int 0)] { @@ -578,9 +748,10 @@ ;; Note that copy_u.d and copy_u.d_f will be split later if !TARGET_64BIT. (define_insn "msa_copy_u_<msafmt_f>" [(set (match_operand:<RES> 0 "register_operand" "=d") - (unspec:<RES> [(match_operand:MSA 1 "register_operand" "f") - (match_operand 2 "const_<indeximm>_operand" "")] - UNSPEC_MSA_COPY_U))] + (zero_extend:<RES> + (vec_select:<UNITMODE> + (match_operand:MSA 1 "register_operand" "f") + (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))] "ISA_HAS_MSA" "copy_u.<msafmt>\t%0,%w1[%2]" [(set_attr "type" "mfc") @@ -589,9 +760,10 @@ (define_split [(set (match_operand:<UNITMODE> 0 "register_operand") - (unspec:<UNITMODE> [(match_operand:SPLIT 1 "register_operand") - (match_operand 2 "const_0_or_1_operand")] - UNSPEC_MSA_COPY_U))] + (zero_extend:<UNITMODE> + (vec_select:<UNITMODE> + (match_operand:SPLIT 1 "register_operand") + (parallel [(match_operand 2 "const_0_or_1_operand")]))))] "reload_completed && TARGET_MSA && !TARGET_64BIT" [(const_int 0)] { @@ -608,14 +780,38 @@ { /* The optab semantics are that index 0 selects the first element of operands[1] and the highest index selects the last element - of operands[2]. This is the oppossite order from "vshf.df wd,rs,wt" - where index 0 selects the first elemnt of wt and the highest index - selects the last element of ws. We therefore swap the operands here. */ + of operands[2]. This is the oppossite order from "vshf.df wd,rs,wt" + where index 0 selects the first element of wt and the highest index + selects the last element of ws. We therefore swap the operands here. */ emit_insn (gen_msa_vshf<mode> (operands[0], operands[3], operands[2], operands[1])); DONE; }) +(define_expand "vec_perm_const<mode>" + [(match_operand:MSA 0 "register_operand") + (match_operand:MSA 1 "register_operand") + (match_operand:MSA 2 "register_operand") + (match_operand:<VIMODE> 3 "")] + "ISA_HAS_MSA" +{ + if (mips_expand_vec_perm_const (operands)) + DONE; + else + FAIL; +}) + +(define_expand "abs<mode>2" + [(set (match_operand:IMSA 0 "register_operand" "=f") + (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")))] + "ISA_HAS_MSA" +{ + rtx reg = gen_reg_rtx (<MODE>mode); + emit_insn (gen_msa_ldi<mode> (reg, const0_rtx)); + emit_insn (gen_msa_add_a_<msafmt> (operands[0], operands[1], reg)); + DONE; +}) + (define_expand "neg<mode>2" [(match_operand:IMSA 0 "register_operand") (match_operand:IMSA 1 "register_operand")] @@ -633,23 +829,11 @@ "ISA_HAS_MSA" { rtx reg = gen_reg_rtx (<MODE>mode); - emit_insn (gen_msa_ld0<mode> (reg, const0_rtx)); + emit_move_insn (reg, CONST0_RTX (<MODE>mode)); emit_insn (gen_sub<mode>3 (operands[0], reg, operands[1])); DONE; }) -(define_insn "msa_ldi<mode>_insn" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (match_operand:IMSA 1 "const_vector_same_simm10_operand" ""))] - "ISA_HAS_MSA" - { - operands[1] = CONST_VECTOR_ELT (operands[1], 0); - return "ldi.<msafmt>\t%w0,%d1"; - } - [(set_attr "type" "arith") - (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) - (define_expand "msa_ldi<mode>" [(match_operand:IMSA 0 "register_operand") (match_operand 1 "const_imm10_operand")] @@ -669,32 +853,12 @@ val = trunc_int_for_mode (val, <UNITMODE>mode); for (i = 0; i < n_elts; i++) - RTVEC_ELT (v, i) = GEN_INT (val); - emit_insn (gen_msa_ldi<mode>_insn (operands[0], - gen_rtx_CONST_VECTOR (<MODE>mode, v))); + RTVEC_ELT (v, i) = GEN_INT (val); + emit_move_insn (operands[0], + gen_rtx_CONST_VECTOR (<MODE>mode, v)); DONE; }) -(define_insn "msa_ld0<mode>" - [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:FMSA [(match_operand 1 "const_0_operand" "")] - UNSPEC_MSA_LD0))] - "ISA_HAS_MSA" - "ldi.<msafmt>\t%w0,%d1" - [(set_attr "type" "arith") - (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) - -(define_insn "msa_lsa" - [(set (match_operand:SI 0 "register_operand" "=d") - (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") - (match_operand:SI 2 "const_immlsa_operand" "")) - (match_operand:SI 3 "register_operand" "d")))] - "ISA_HAS_LSA" - "lsa\t%0,%1,%3,%y2" - [(set_attr "type" "arith") - (set_attr "mode" "SI")]) - (define_insn "msa_vshf<mode>" [(set (match_operand:MSA 0 "register_operand" "=f") (unspec:MSA [(match_operand:<VIMODE> 1 "register_operand" "0") @@ -705,83 +869,38 @@ "vshf.<msafmt>\t%w0,%w2,%w3" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic_l")]) - -;; 128-bit integer/MSA vector registers moves -;; Note that we prefer floating-point loads, stores, and moves by adding * to -;; other register preferences. -;; Note that we combine f and J, so that move_type for J is fmove and its -;; instruction length can be 1. -(define_insn "movti_msa" - [(set (match_operand:TI 0 "nonimmediate_operand" "=*d,*d,*d,*R,*d,*f,f,R,f,*m,*d,*m,*f") - (match_operand:TI 1 "move_operand" "*d,*i,*R,*d*J,*f,*d,R,f,fJ,*d*J,*m,*f,*m"))] - "ISA_HAS_MSA - && !TARGET_64BIT - && (register_operand (operands[0], TImode) - || reg_or_0_operand (operands[1], TImode))" - { return mips_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "move,const,load,store,mfc,mtc,fpload,fpstore,fmove,store,load,fpstore,fpload") - (set_attr "mode" "TI")]) - -;; Note that we prefer floating-point loads, stores, and moves by adding * to -;; other register preferences. -;; Note that we combine f and J, so that move_type for J is fmove and its -;; instruction length can be 1. -(define_insn "movti_msa_64bit" - [(set (match_operand:TI 0 "nonimmediate_operand" "=*d,*d,*d,*R,*a,*d,*d,*f,f,R,f,*m,*d,*m,*f") - (match_operand:TI 1 "move_operand" "*d,*i,*R,*d*J,*d*J,*a,*f,*d,R,f,fJ,*d*J,*m,*f,*m"))] - "ISA_HAS_MSA - && TARGET_64BIT - && (register_operand (operands[0], TImode) - || reg_or_0_operand (operands[1], TImode))" - { return mips_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "move,const,load,store,mtlo,mflo,mfc,mtc,fpload,fpstore,fmove,store,load,fpstore,fpload") - (set_attr "mode" "TI")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic_l2") + (const_string "msa_eu_logic_l")))]) (define_expand "mov<mode>" - [(set (match_operand:MODE128 0) - (match_operand:MODE128 1))] - "TARGET_64BIT || TARGET_MSA" + [(set (match_operand:MSA 0) + (match_operand:MSA 1))] + "TARGET_MSA" { if (mips_legitimize_move (<MODE>mode, operands[0], operands[1])) DONE; }) (define_expand "movmisalign<mode>" - [(set (match_operand:MODE128 0) - (match_operand:MODE128 1))] - "TARGET_64BIT || TARGET_MSA" + [(set (match_operand:MSA 0) + (match_operand:MSA 1))] + "TARGET_MSA" { if (mips_legitimize_move (<MODE>mode, operands[0], operands[1])) DONE; }) -;; 128bit MSA modes only in msa registers or memmory -;; an exception is allowing MSA modes for GP registers for arguments -;; and return values. +;; 128bit MSA modes only in msa registers or memory. An exception is allowing +;; MSA modes for GP registers for arguments and return values. (define_insn "mov<mode>_msa" - [(set (match_operand:MODE128 0 "nonimmediate_operand" "=f,f,R,!d,f") - (match_operand:MODE128 1 "move_operand" "fYG,R,f,f,!d"))] - "ISA_HAS_MSA - && (register_operand (operands[0], <MODE>mode) - || reg_or_0_operand (operands[1], <MODE>mode))" + [(set (match_operand:MSA 0 "nonimmediate_operand" "=f,f,R,*d,*f") + (match_operand:MSA 1 "move_operand" "fYGYI,R,f,*f,*d"))] + "TARGET_MSA" { return mips_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "fmove,fpload,fpstore,fmove,fmove") - (set_attr "mode" "TI")]) - -(define_split - [(set (match_operand:TI 0 "nonimmediate_operand") - (match_operand:TI 1 "move_operand"))] - "reload_completed && TARGET_MSA - && mips_split_move_insn_p (operands[0], operands[1], insn)" - [(const_int 0)] -{ - /* Temporary sanity check */ - gcc_assert (mips_split_128bit_move_p (operands[0], operands[1])); - gcc_assert (mips_split_move_insn_p (operands[0], operands[1], curr_insn)); - mips_split_move_insn (operands[0], operands[1], curr_insn); - DONE; -}) + [(set_attr "move_type" "fmove,fpload,fpstore,mfc,mtc") + (set_attr "mode" "TI")]) (define_split [(set (match_operand:MSA 0 "nonimmediate_operand") @@ -790,8 +909,6 @@ && mips_split_move_insn_p (operands[0], operands[1], insn)" [(const_int 0)] { - /* Temporary sanity check */ - gcc_assert (mips_split_128bit_move_p (operands[0], operands[1])); mips_split_move_insn (operands[0], operands[1], curr_insn); DONE; }) @@ -851,8 +968,9 @@ gcc_unreachable (); } } - [(set_attr "alu_type" "add") + [(set_attr "alu_type" "add, unknown, unknown") (set_attr "mode" "TI") + (set_attr "datafmt" "<msafmt>") (set_attr "msa_execunit" "msa_eu_int_add")]) (define_insn "sub<mode>3" @@ -883,8 +1001,9 @@ gcc_unreachable (); } } - [(set_attr "alu_type" "sub") + [(set_attr "alu_type" "sub, unknown, unknown") (set_attr "mode" "TI") + (set_attr "datafmt" "<msafmt>") (set_attr "msa_execunit" "msa_eu_int_add")]) (define_insn "mul<mode>3" @@ -927,6 +1046,7 @@ { return mips_msa_output_division ("div_s.<msafmt>\t%w0,%w1,%w2", operands); } [(set_attr "type" "idiv3") (set_attr "mode" "TI") + (set_attr "datafmt" "<msafmt>") (set_attr "msa_execunit" "msa_eu_div")]) (define_insn "udiv<mode>3" @@ -937,6 +1057,7 @@ { return mips_msa_output_division ("div_u.<msafmt>\t%w0,%w1,%w2", operands); } [(set_attr "type" "idiv3") (set_attr "mode" "TI") + (set_attr "datafmt" "<msafmt>") (set_attr "msa_execunit" "msa_eu_div")]) (define_insn "mod<mode>3" @@ -947,6 +1068,7 @@ { return mips_msa_output_division ("mod_s.<msafmt>\t%w0,%w1,%w2", operands); } [(set_attr "type" "idiv3") (set_attr "mode" "TI") + (set_attr "datafmt" "<msafmt>") (set_attr "msa_execunit" "msa_eu_div")]) (define_insn "umod<mode>3" @@ -957,6 +1079,7 @@ { return mips_msa_output_division ("mod_u.<msafmt>\t%w0,%w1,%w2", operands); } [(set_attr "type" "idiv3") (set_attr "mode" "TI") + (set_attr "datafmt" "<msafmt>") (set_attr "msa_execunit" "msa_eu_div")]) (define_insn "xorv16qi3" @@ -996,7 +1119,11 @@ } [(set_attr "alu_type" "xor") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (and (eq_attr "cpu" "i6400") + (eq_attr "alternative" "1")) + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "iorv16qi3" [(set (match_operand:V16QI 0 "register_operand" "=f,f") @@ -1035,7 +1162,11 @@ } [(set_attr "alu_type" "or") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (and (eq_attr "cpu" "i6400") + (eq_attr "alternative" "1")) + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "andv16qi3" [(set (match_operand:V16QI 0 "register_operand" "=f,f") @@ -1046,7 +1177,7 @@ if (which_alternative == 1) { operands[2] = CONST_VECTOR_ELT (operands[2], 0); - return "andi.b\t%w0,%w0,%B2"; + return "andi.b\t%w0,%w1,%B2"; } else return "and.v\t%w0,%w1,%w2"; @@ -1074,7 +1205,11 @@ } [(set_attr "alu_type" "and") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (and (eq_attr "cpu" "i6400") + (eq_attr "alternative" "1")) + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "one_cmpl<mode>2" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1087,8 +1222,8 @@ (define_insn "vlshr<mode>3" [(set (match_operand:IMSA 0 "register_operand" "=f,f") - (lshiftrt:<MODE> (match_operand:<MODE> 1 "register_operand" "f,f") - (match_operand:<MODE> 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] + (lshiftrt:IMSA (match_operand:IMSA 1 "register_operand" "f,f") + (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] "ISA_HAS_MSA" { if (which_alternative == 0) @@ -1100,7 +1235,10 @@ } [(set_attr "type" "shift") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "vashr<mode>3" [(set (match_operand:IMSA 0 "register_operand" "=f,f") @@ -1117,7 +1255,10 @@ } [(set_attr "type" "shift") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "vashl<mode>3" [(set (match_operand:IMSA 0 "register_operand" "=f,f") @@ -1134,7 +1275,10 @@ } [(set_attr "type" "shift") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) ;; Floating-point operations (define_insn "add<mode>3" @@ -1249,24 +1393,59 @@ (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_int_add")]) -(define_insn "msa_addvi_<msafmt>" +(define_expand "msa_addvi_<msafmt>" + [(set (match_operand:IMSA 0 "register_operand") + (plus:IMSA (match_operand:IMSA 1 "register_operand") + (match_operand 2 "const_uimm5_operand")))] + "ISA_HAS_MSA" + { + unsigned n_elts = GET_MODE_NUNITS (<MODE>mode); + rtvec v = rtvec_alloc (n_elts); + HOST_WIDE_INT val = INTVAL (operands[2]); + unsigned int i; + + for (i = 0; i < n_elts; i++) + RTVEC_ELT (v, i) = GEN_INT (val); + + emit_insn (gen_msa_addvi_<msafmt>_insn (operands[0], operands[1], + gen_rtx_CONST_VECTOR (<MODE>mode, v))); + DONE; + }) + +(define_expand "msa_andi_b" + [(set (match_operand:V16QI 0 "register_operand") + (and:V16QI (match_operand:V16QI 1 "register_operand") + (match_operand:QI 2 "const_uimm8_operand")))] + "ISA_HAS_MSA" + { + rtvec v = rtvec_alloc (16); + HOST_WIDE_INT val = INTVAL (operands[2]); + unsigned int i; + + for (i = 0; i < 16; i++) + RTVEC_ELT (v, i) = GEN_INT (val); + + emit_insn (gen_msa_andi_b_insn (operands[0], operands[1], + gen_rtx_CONST_VECTOR (V16QImode, v))); + DONE; + }) + +(define_insn "msa_addvi_<msafmt>_insn" [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand 2 "const_uimm5_operand" "")] - UNSPEC_MSA_ADDVI))] + (plus:IMSA (match_operand:IMSA 1 "register_operand" "f") + (match_operand:IMSA 2 "const_vector_same_uimm5_operand" "")))] "ISA_HAS_MSA" - "addvi.<msafmt>\t%w0,%w1,%2" + "addvi.<msafmt>\t%w0,%w1,%E2" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_int_add")]) -(define_insn "msa_andi_b" +(define_insn "msa_andi_b_insn" [(set (match_operand:V16QI 0 "register_operand" "=f") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "f") - (match_operand 2 "const_uimm8_operand" "")] - UNSPEC_MSA_ANDI_B))] + (and:V16QI (match_operand:V16QI 1 "register_operand" "f") + (match_operand:V16QI 2 "const_vector_same_uimm8_operand" "")))] "ISA_HAS_MSA" - "andi.b\t%w0,%w1,%2" + "andi.b\t%w0,%w1,%E2" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic")]) @@ -1346,7 +1525,10 @@ "bclr.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_bclri_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1357,7 +1539,10 @@ "bclri.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_binsl_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1369,7 +1554,10 @@ "binsl.<msafmt>\t%w0,%w2,%w3" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic_l")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic_l2") + (const_string "msa_eu_logic_l")))]) (define_insn "msa_binsli_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1381,7 +1569,10 @@ "binsli.<msafmt>\t%w0,%w2,%3" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic_l")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic_l2") + (const_string "msa_eu_logic_l")))]) (define_insn "msa_binsr_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1393,7 +1584,10 @@ "binsr.<msafmt>\t%w0,%w2,%w3" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic_l")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic_l2") + (const_string "msa_eu_logic_l")))]) (define_insn "msa_binsri_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1405,7 +1599,10 @@ "binsri.<msafmt>\t%w0,%w2,%3" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic_l")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic_l2") + (const_string "msa_eu_logic_l")))]) (define_insn "msa_bmnz_v_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1464,18 +1661,24 @@ "bneg.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_bnegi_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") (match_operand 2 "const_msa_branch_operand" "")] - UNSPEC_MSA_BNEGI))] + UNSPEC_MSA_BNEGI))] "ISA_HAS_MSA" "bnegi.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_bsel_v_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1486,7 +1689,8 @@ "ISA_HAS_MSA" "bsel.v\t%w0,%w2,%w3" [(set_attr "type" "arith") - (set_attr "mode" "TI")]) + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic_l")]) (define_insn "msa_bseli_b" [(set (match_operand:V16QI 0 "register_operand" "=f") @@ -1509,7 +1713,10 @@ "bset.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_bseti_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -1520,7 +1727,10 @@ "bseti.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_code_iterator ICC [eq le leu lt ltu]) @@ -1560,10 +1770,7 @@ (ICC:IMSA (match_operand:IMSA 1 "register_operand" "f") (match_operand:IMSA 2 "const_vector_same_cmp<ICC:cmpi>imm4_operand" "")))] "ISA_HAS_MSA" - { - operands[2] = CONST_VECTOR_ELT (operands[2], 0); - return "c<ICC:icci>.<IMSA:msafmt>\t%w0,%w1,%d2"; - } + "c<ICC:icci>.<IMSA:msafmt>\t%w0,%w1,%E2" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_int_add")]) @@ -1581,9 +1788,9 @@ (define_insn "msa_dotp_s_<msafmt>" [(set (match_operand:IDOTP128 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<VHALFMODE> 1 "register_operand" "f") - (match_operand:<VHALFMODE> 2 "register_operand" "f")] - UNSPEC_MSA_DOTP_S))] + (unspec:IDOTP128 [(match_operand:<VHALFMODE> 1 "register_operand" "f") + (match_operand:<VHALFMODE> 2 "register_operand" "f")] + UNSPEC_MSA_DOTP_S))] "ISA_HAS_MSA" "dotp_s.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") @@ -1592,9 +1799,9 @@ (define_insn "msa_dotp_u_<msafmt>" [(set (match_operand:IDOTP128 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<VHALFMODE> 1 "register_operand" "f") - (match_operand:<VHALFMODE> 2 "register_operand" "f")] - UNSPEC_MSA_DOTP_U))] + (unspec:IDOTP128 [(match_operand:<VHALFMODE> 1 "register_operand" "f") + (match_operand:<VHALFMODE> 2 "register_operand" "f")] + UNSPEC_MSA_DOTP_U))] "ISA_HAS_MSA" "dotp_u.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") @@ -1603,10 +1810,10 @@ (define_insn "msa_dpadd_s_<msafmt>" [(set (match_operand:IDOTP128 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<MODE> 1 "register_operand" "0") - (match_operand:<VHALFMODE> 2 "register_operand" "f") - (match_operand:<VHALFMODE> 3 "register_operand" "f")] - UNSPEC_MSA_DPADD_S))] + (unspec:IDOTP128 [(match_operand:IDOTP128 1 "register_operand" "0") + (match_operand:<VHALFMODE> 2 "register_operand" "f") + (match_operand:<VHALFMODE> 3 "register_operand" "f")] + UNSPEC_MSA_DPADD_S))] "ISA_HAS_MSA" "dpadd_s.<msafmt>\t%w0,%w2,%w3" [(set_attr "type" "arith") @@ -1615,10 +1822,10 @@ (define_insn "msa_dpadd_u_<msafmt>" [(set (match_operand:IDOTP128 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<MODE> 1 "register_operand" "0") - (match_operand:<VHALFMODE> 2 "register_operand" "f") - (match_operand:<VHALFMODE> 3 "register_operand" "f")] - UNSPEC_MSA_DPADD_U))] + (unspec:IDOTP128 [(match_operand:IDOTP128 1 "register_operand" "0") + (match_operand:<VHALFMODE> 2 "register_operand" "f") + (match_operand:<VHALFMODE> 3 "register_operand" "f")] + UNSPEC_MSA_DPADD_U))] "ISA_HAS_MSA" "dpadd_u.<msafmt>\t%w0,%w2,%w3" [(set_attr "type" "arith") @@ -1627,10 +1834,10 @@ (define_insn "msa_dpsub_s_<msafmt>" [(set (match_operand:IDOTP128 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<MODE> 1 "register_operand" "0") - (match_operand:<VHALFMODE> 2 "register_operand" "f") - (match_operand:<VHALFMODE> 3 "register_operand" "f")] - UNSPEC_MSA_DPSUB_S))] + (unspec:IDOTP128 [(match_operand:IDOTP128 1 "register_operand" "0") + (match_operand:<VHALFMODE> 2 "register_operand" "f") + (match_operand:<VHALFMODE> 3 "register_operand" "f")] + UNSPEC_MSA_DPSUB_S))] "ISA_HAS_MSA" "dpsub_s.<msafmt>\t%w0,%w2,%w3" [(set_attr "type" "arith") @@ -1639,10 +1846,10 @@ (define_insn "msa_dpsub_u_<msafmt>" [(set (match_operand:IDOTP128 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<MODE> 1 "register_operand" "0") - (match_operand:<VHALFMODE> 2 "register_operand" "f") - (match_operand:<VHALFMODE> 3 "register_operand" "f")] - UNSPEC_MSA_DPSUB_U))] + (unspec:IDOTP128 [(match_operand:IDOTP128 1 "register_operand" "0") + (match_operand:<VHALFMODE> 2 "register_operand" "f") + (match_operand:<VHALFMODE> 3 "register_operand" "f")] + UNSPEC_MSA_DPSUB_U))] "ISA_HAS_MSA" "dpsub_u.<msafmt>\t%w0,%w2,%w3" [(set_attr "type" "arith") @@ -1694,6 +1901,24 @@ (le "fcle") (lt "fclt")]) +(define_int_iterator FSC_UNS [UNSPEC_MSA_FSAF UNSPEC_MSA_FSUN UNSPEC_MSA_FSOR + UNSPEC_MSA_FSEQ UNSPEC_MSA_FSNE UNSPEC_MSA_FSUEQ + UNSPEC_MSA_FSUNE UNSPEC_MSA_FSULE UNSPEC_MSA_FSULT + UNSPEC_MSA_FSLE UNSPEC_MSA_FSLT]) + +(define_int_attr fsc + [(UNSPEC_MSA_FSAF "fsaf") + (UNSPEC_MSA_FSUN "fsun") + (UNSPEC_MSA_FSOR "fsor") + (UNSPEC_MSA_FSEQ "fseq") + (UNSPEC_MSA_FSNE "fsne") + (UNSPEC_MSA_FSUEQ "fsueq") + (UNSPEC_MSA_FSUNE "fsune") + (UNSPEC_MSA_FSULE "fsule") + (UNSPEC_MSA_FSULT "fsult") + (UNSPEC_MSA_FSLE "fsle") + (UNSPEC_MSA_FSLT "fslt")]) + (define_insn "msa_<FCC:fcc>_<FMSA:msafmt>" [(set (match_operand:<VIMODE> 0 "register_operand" "=f") (FCC:<VIMODE> (match_operand:FMSA 1 "register_operand" "f") @@ -1704,123 +1929,13 @@ (set_attr "mode" "<UNITMODE>") (set_attr "msa_execunit" "msa_eu_cmp")]) -(define_insn "msa_fsaf_<FMSA:msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSAF))] - "ISA_HAS_MSA" - "fsaf.<FMSA:msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fsor_<FMSA:msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSOR))] - "ISA_HAS_MSA" - "fsor.<FMSA:msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fsun_<FMSA:msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSUN))] - "ISA_HAS_MSA" - "fsun.<FMSA:msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fsune_<msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSUNE))] - "ISA_HAS_MSA" - "fsune.<msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fsueq_<msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSUEQ))] - "ISA_HAS_MSA" - "fsueq.<msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fseq_<msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSEQ))] - "ISA_HAS_MSA" - "fseq.<msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fsne_<msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSNE))] - "ISA_HAS_MSA" - "fsne.<msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fslt_<msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSLT))] - "ISA_HAS_MSA" - "fslt.<msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fsult_<msafmt>" +(define_insn "msa_<fsc>_<FMSA:msafmt>" [(set (match_operand:<VIMODE> 0 "register_operand" "=f") (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSULT))] - "ISA_HAS_MSA" - "fsult.<msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fsle_<msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSLE))] + (match_operand:FMSA 2 "register_operand" "f")] + FSC_UNS))] "ISA_HAS_MSA" - "fsle.<msafmt>\t%w0,%w1,%w2" - [(set_attr "type" "fcmp") - (set_attr "mode" "<UNITMODE>") - (set_attr "msa_execunit" "msa_eu_cmp")]) - -(define_insn "msa_fsule_<msafmt>" - [(set (match_operand:<VIMODE> 0 "register_operand" "=f") - (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") - (match_operand:FMSA 2 "register_operand" "f")] - UNSPEC_MSA_FSULE))] - "ISA_HAS_MSA" - "fsule.<msafmt>\t%w0,%w1,%w2" + "<fsc>.<FMSA:msafmt>\t%w0,%w1,%w2" [(set_attr "type" "fcmp") (set_attr "mode" "<UNITMODE>") (set_attr "msa_execunit" "msa_eu_cmp")]) @@ -1844,6 +1959,10 @@ [(V4SF "v4si") (V2DF "v2di")]) +(define_mode_attr FQ + [(V4SF "V8HI") + (V2DF "V4SI")]) + (define_mode_attr FINTCNV [(V4SF "I2S") (V2DF "I2D")]) @@ -1852,9 +1971,9 @@ [(V4SF "S2I") (V2DF "D2I")]) -(define_insn "float<FMSA:mode><fint>2" +(define_insn "float<fint><FMSA:mode>2" [(set (match_operand:FMSA 0 "register_operand" "=f") - (float:<MODE> (match_operand:<FINT> 1 "register_operand" "f")))] + (float:FMSA (match_operand:<FINT> 1 "register_operand" "f")))] "ISA_HAS_MSA" "ffint_s.<msafmt>\t%w0,%w1" [(set_attr "type" "fcvt") @@ -1862,9 +1981,9 @@ (set_attr "mode" "<UNITMODE>") (set_attr "msa_execunit" "msa_eu_float4")]) -(define_insn "floatuns<FMSA:mode><fint>2" +(define_insn "floatuns<fint><FMSA:mode>2" [(set (match_operand:FMSA 0 "register_operand" "=f") - (unsigned_float:<MODE> (match_operand:<FINT> 1 "register_operand" "f")))] + (unsigned_float:FMSA (match_operand:<FINT> 1 "register_operand" "f")))] "ISA_HAS_MSA" "ffint_u.<msafmt>\t%w0,%w1" [(set_attr "type" "fcvt") @@ -1878,8 +1997,8 @@ (define_insn "msa_ffql_<msafmt>" [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<FINT> 1 "register_operand" "f")] - UNSPEC_MSA_FFQL))] + (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")] + UNSPEC_MSA_FFQL))] "ISA_HAS_MSA" "ffql.<msafmt>\t%w0,%w1" [(set_attr "type" "fcvt") @@ -1889,8 +2008,8 @@ (define_insn "msa_ffqr_<msafmt>" [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<FINT> 1 "register_operand" "f")] - UNSPEC_MSA_FFQR))] + (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")] + UNSPEC_MSA_FFQR))] "ISA_HAS_MSA" "ffqr.<msafmt>\t%w0,%w1" [(set_attr "type" "fcvt") @@ -1898,22 +2017,53 @@ (set_attr "mode" "<UNITMODE>") (set_attr "msa_execunit" "msa_eu_float4")]) -(define_insn "msa_fill_<msafmt_f>" - [(set (match_operand:MSA 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<REGOR0> 1 "reg_or_0_operand" "dJ")] - UNSPEC_MSA_FILL))] +;; Note used directly by builtins but via the following define_expand. +(define_insn "msa_fill_<msafmt>_insn" + [(set (match_operand:IMSA 0 "register_operand" "=f") + (vec_duplicate:IMSA + (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ")))] "ISA_HAS_MSA" "fill.<msafmt>\t%w0,%z1" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic")]) -;; Note that fill.d and fill_d_f will be split later if !TARGET_64BIT. +;; Expand builtin catoring for HImode and QImode which take SImode. +(define_expand "msa_fill_<msafmt>" + [(set (match_operand:IMSA 0 "register_operand") + (vec_duplicate:IMSA + (match_operand:<EXCEPT> 1 "reg_or_0_operand")))] + "ISA_HAS_MSA" +{ + if ((GET_MODE_SIZE (<UNITMODE>mode) < GET_MODE_SIZE (<EXCEPT>mode)) + && (REG_P (operands[1]) || (GET_CODE (operands[1]) == SUBREG + && REG_P (SUBREG_REG (operands[1]))))) + { + unsigned int offset = GET_MODE_SIZE (<EXCEPT>mode) + - GET_MODE_SIZE (<UNITMODE>mode); + operands[1] = simplify_gen_subreg (<UNITMODE>mode, operands[1], + GET_MODE (operands[1]), + BYTES_BIG_ENDIAN ? offset : 0); + } + emit_insn (gen_msa_fill_<msafmt>_insn (operands[0], operands[1])); + DONE; + }) + +(define_insn "msa_fill_<msafmt_f>" + [(set (match_operand:FMSA 0 "register_operand" "=f") + (vec_duplicate:FMSA + (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ")))] + "ISA_HAS_MSA" + "fill.<msafmt>\t%w0,%z1" + [(set_attr "type" "arith") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) +;; Note that fill.d and fill.d_f will be split later if !TARGET_64BIT. (define_split [(set (match_operand:V2DI 0 "register_operand") - (unspec:V2DI [(match_operand:DI 1 "reg_or_0_operand")] - UNSPEC_MSA_FILL))] + (vec_duplicate:V2DI + (match_operand:DI 1 "reg_or_0_operand")))] "reload_completed && TARGET_MSA && !TARGET_64BIT" [(const_int 0)] { @@ -1923,8 +2073,8 @@ (define_split [(set (match_operand:V2DF 0 "register_operand") - (unspec:V2DF [(match_operand:DF 1 "register_operand")] - UNSPEC_MSA_FILL))] + (vec_duplicate:V2DF + (match_operand:DF 1 "register_operand")))] "reload_completed && TARGET_MSA && !TARGET_64BIT" [(const_int 0)] { @@ -1945,8 +2095,8 @@ ;;UNSPEC_MSA_FMAX (define_insn "smax<mode>3" [(set (match_operand:FMSA 0 "register_operand" "=f") - (smax:<MODE> (match_operand:<MODE> 1 "register_operand" "f") - (match_operand:<MODE> 2 "register_operand" "f")))] + (smax:FMSA (match_operand:FMSA 1 "register_operand" "f") + (match_operand:FMSA 2 "register_operand" "f")))] "ISA_HAS_MSA" "fmax.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "fadd") @@ -1956,8 +2106,8 @@ ;;UNSPEC_MSA_FMAX_A (define_insn "umax<mode>3" [(set (match_operand:FMSA 0 "register_operand" "=f") - (umax:<MODE> (match_operand:<MODE> 1 "register_operand" "f") - (match_operand:<MODE> 2 "register_operand" "f")))] + (umax:FMSA (match_operand:FMSA 1 "register_operand" "f") + (match_operand:FMSA 2 "register_operand" "f")))] "ISA_HAS_MSA" "fmax_a.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "fadd") @@ -1967,8 +2117,8 @@ ;;UNSPEC_MSA_FMIN (define_insn "smin<mode>3" [(set (match_operand:FMSA 0 "register_operand" "=f") - (smin:<MODE> (match_operand:<MODE> 1 "register_operand" "f") - (match_operand:<MODE> 2 "register_operand" "f")))] + (smin:FMSA (match_operand:FMSA 1 "register_operand" "f") + (match_operand:FMSA 2 "register_operand" "f")))] "ISA_HAS_MSA" "fmin.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "fadd") @@ -1978,8 +2128,8 @@ ;;UNSPEC_MSA_FMIN_A (define_insn "umin<mode>3" [(set (match_operand:FMSA 0 "register_operand" "=f") - (umin:<MODE> (match_operand:<MODE> 1 "register_operand" "f") - (match_operand:<MODE> 2 "register_operand" "f")))] + (umin:FMSA (match_operand:FMSA 1 "register_operand" "f") + (match_operand:FMSA 2 "register_operand" "f")))] "ISA_HAS_MSA" "fmin_a.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "fadd") @@ -1993,7 +2143,8 @@ "ISA_HAS_MSA" "frcp.<msafmt>\t%w0,%w1" [(set_attr "type" "frdiv") - (set_attr "mode" "<UNITMODE>")]) + (set_attr "mode" "<UNITMODE>") + (set_attr "msa_execunit" "msa_eu_fdiv")]) (define_insn "msa_frint_<msafmt>" [(set (match_operand:FMSA 0 "register_operand" "=f") @@ -2012,14 +2163,15 @@ "ISA_HAS_MSA" "frsqrt.<msafmt>\t%w0,%w1" [(set_attr "type" "frsqrt") - (set_attr "mode" "<UNITMODE>")]) + (set_attr "mode" "<UNITMODE>") + (set_attr "msa_execunit" "msa_eu_fdiv")]) (define_insn "msa_ftint_s_<msafmt>" [(set (match_operand:<FINT> 0 "register_operand" "=f") (unspec:<FINT> [(match_operand:FMSA 1 "register_operand" "f")] UNSPEC_MSA_FTINT_S))] "ISA_HAS_MSA" - "ftint_s.<>msafmt>\t%w0,%w1" + "ftint_s.<msafmt>\t%w0,%w1" [(set_attr "type" "fcvt") (set_attr "cnv_mode" "<FINTCNV_2>") (set_attr "mode" "<UNITMODE>") @@ -2083,14 +2235,14 @@ (set_attr "msa_execunit" "msa_eu_float4")]) (define_mode_iterator IZMODE [V8HI V4SI V2DI]) -(define_mode_attr IZDOUBLE +(define_mode_attr IZDOUBLE [(V8HI "V16QI") (V4SI "V8HI") (V2DI "V4SI")]) (define_insn "msa_hadd_s_<msafmt>" [(set (match_operand:IZMODE 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<IZDOUBLE> 1 "register_operand" "f") + (unspec:IZMODE [(match_operand:<IZDOUBLE> 1 "register_operand" "f") (match_operand:<IZDOUBLE> 2 "register_operand" "f")] UNSPEC_MSA_HADD_S))] "ISA_HAS_MSA" @@ -2101,7 +2253,7 @@ (define_insn "msa_hadd_u_<msafmt>" [(set (match_operand:IZMODE 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<IZDOUBLE> 1 "register_operand" "f") + (unspec:IZMODE [(match_operand:<IZDOUBLE> 1 "register_operand" "f") (match_operand:<IZDOUBLE> 2 "register_operand" "f")] UNSPEC_MSA_HADD_U))] "ISA_HAS_MSA" @@ -2112,7 +2264,7 @@ (define_insn "msa_hsub_s_<msafmt>" [(set (match_operand:IZMODE 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<IZDOUBLE> 1 "register_operand" "f") + (unspec:IZMODE [(match_operand:<IZDOUBLE> 1 "register_operand" "f") (match_operand:<IZDOUBLE> 2 "register_operand" "f")] UNSPEC_MSA_HSUB_S))] "ISA_HAS_MSA" @@ -2123,7 +2275,7 @@ (define_insn "msa_hsub_u_<msafmt>" [(set (match_operand:IZMODE 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<IZDOUBLE> 1 "register_operand" "f") + (unspec:IZMODE [(match_operand:<IZDOUBLE> 1 "register_operand" "f") (match_operand:<IZDOUBLE> 2 "register_operand" "f")] UNSPEC_MSA_HSUB_U))] "ISA_HAS_MSA" @@ -2132,46 +2284,214 @@ (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_int_add")]) -(define_insn "msa_ilvev_<msafmt>" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] - UNSPEC_MSA_ILVEV))] +(define_insn "msa_ilvev_b" + [(set (match_operand:V16QI 0 "register_operand" "=f") + (vec_select:V16QI (vec_concat:V32QI + (match_operand:V16QI 1 "register_operand" "f") + (match_operand:V16QI 2 "register_operand" "f")) + (parallel [(const_int 16) (const_int 0) + (const_int 18) (const_int 2) + (const_int 20) (const_int 4) + (const_int 22) (const_int 6) + (const_int 24) (const_int 8) + (const_int 26) (const_int 10) + (const_int 28) (const_int 12) + (const_int 30) (const_int 14)])))] + "ISA_HAS_MSA" + "ilvev.b\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvev_h" + [(set (match_operand:V8HI 0 "register_operand" "=f") + (vec_select:V8HI (vec_concat:V16HI + (match_operand:V8HI 1 "register_operand" "f") + (match_operand:V8HI 2 "register_operand" "f")) + (parallel [(const_int 8) (const_int 0) + (const_int 10) (const_int 2) + (const_int 12) (const_int 4) + (const_int 14) (const_int 6)])))] + "ISA_HAS_MSA" + "ilvev.h\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvev_w" + [(set (match_operand:V4SI 0 "register_operand" "=f") + (vec_select:V4SI (vec_concat:V8SI + (match_operand:V4SI 1 "register_operand" "f") + (match_operand:V4SI 2 "register_operand" "f")) + (parallel [(const_int 4) (const_int 0) + (const_int 6) (const_int 2)])))] "ISA_HAS_MSA" - "ilvev.<msafmt>\t%w0,%w1,%w2" + "ilvev.w\t%w0,%w1,%w2" [(set_attr "alu_type" "add") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic")]) -(define_insn "msa_ilvl_<msafmt>" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] - UNSPEC_MSA_ILVL))] +(define_insn "msa_ilvl_b" + [(set (match_operand:V16QI 0 "register_operand" "=f") + (vec_select:V16QI (vec_concat:V32QI + (match_operand:V16QI 1 "register_operand" "f") + (match_operand:V16QI 2 "register_operand" "f")) + (parallel [(const_int 24) (const_int 8) + (const_int 25) (const_int 9) + (const_int 26) (const_int 10) + (const_int 27) (const_int 11) + (const_int 28) (const_int 12) + (const_int 29) (const_int 13) + (const_int 30) (const_int 14) + (const_int 31) (const_int 15)])))] + "ISA_HAS_MSA" + "ilvl.b\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvl_h" + [(set (match_operand:V8HI 0 "register_operand" "=f") + (vec_select:V8HI (vec_concat:V16HI + (match_operand:V8HI 1 "register_operand" "f") + (match_operand:V8HI 2 "register_operand" "f")) + (parallel [(const_int 12) (const_int 4) + (const_int 13) (const_int 5) + (const_int 14) (const_int 6) + (const_int 15) (const_int 7)])))] + "ISA_HAS_MSA" + "ilvl.h\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvl_w" + [(set (match_operand:V4SI 0 "register_operand" "=f") + (vec_select:V4SI (vec_concat:V8SI + (match_operand:V4SI 1 "register_operand" "f") + (match_operand:V4SI 2 "register_operand" "f")) + (parallel [(const_int 6) (const_int 2) + (const_int 7) (const_int 3)])))] "ISA_HAS_MSA" - "ilvl.<msafmt>\t%w0,%w1,%w2" + "ilvl.w\t%w0,%w1,%w2" [(set_attr "alu_type" "add") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic")]) -(define_insn "msa_ilvod_<msafmt>" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] - UNSPEC_MSA_ILVOD))] +(define_insn "msa_ilvl_d" + [(set (match_operand:V2DI 0 "register_operand" "=f") + (vec_select:V2DI (vec_concat:V4DI + (match_operand:V2DI 1 "register_operand" "f") + (match_operand:V2DI 2 "register_operand" "f")) + (parallel [(const_int 3) (const_int 1)])))] "ISA_HAS_MSA" - "ilvod.<msafmt>\t%w0,%w1,%w2" + "ilvl.d\t%w0,%w1,%w2" [(set_attr "alu_type" "add") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic")]) -(define_insn "msa_ilvr_<msafmt>" - [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] - UNSPEC_MSA_ILVR))] +(define_insn "msa_ilvod_b" + [(set (match_operand:V16QI 0 "register_operand" "=f") + (vec_select:V16QI (vec_concat:V32QI + (match_operand:V16QI 1 "register_operand" "f") + (match_operand:V16QI 2 "register_operand" "f")) + (parallel [(const_int 17) (const_int 1) + (const_int 19) (const_int 3) + (const_int 21) (const_int 5) + (const_int 23) (const_int 7) + (const_int 25) (const_int 9) + (const_int 27) (const_int 11) + (const_int 29) (const_int 13) + (const_int 31) (const_int 15)])))] + "ISA_HAS_MSA" + "ilvod.b\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvod_h" + [(set (match_operand:V8HI 0 "register_operand" "=f") + (vec_select:V8HI (vec_concat:V16HI + (match_operand:V8HI 1 "register_operand" "f") + (match_operand:V8HI 2 "register_operand" "f")) + (parallel [(const_int 9) (const_int 1) + (const_int 11) (const_int 3) + (const_int 13) (const_int 5) + (const_int 15) (const_int 7)])))] + "ISA_HAS_MSA" + "ilvod.h\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvod_w" + [(set (match_operand:V4SI 0 "register_operand" "=f") + (vec_select:V4SI (vec_concat:V8SI + (match_operand:V4SI 1 "register_operand" "f") + (match_operand:V4SI 2 "register_operand" "f")) + (parallel [(const_int 5) (const_int 1) + (const_int 7) (const_int 3)])))] + "ISA_HAS_MSA" + "ilvod.w\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvr_b" + [(set (match_operand:V16QI 0 "register_operand" "=f") + (vec_select:V16QI (vec_concat:V32QI + (match_operand:V16QI 1 "register_operand" "f") + (match_operand:V16QI 2 "register_operand" "f")) + (parallel [(const_int 16) (const_int 0) + (const_int 17) (const_int 1) + (const_int 18) (const_int 2) + (const_int 19) (const_int 3) + (const_int 20) (const_int 4) + (const_int 21) (const_int 5) + (const_int 22) (const_int 6) + (const_int 23) (const_int 7)])))] + "ISA_HAS_MSA" + "ilvr.b\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvr_h" + [(set (match_operand:V8HI 0 "register_operand" "=f") + (vec_select:V8HI (vec_concat:V16HI + (match_operand:V8HI 1 "register_operand" "f") + (match_operand:V8HI 2 "register_operand" "f")) + (parallel [(const_int 8) (const_int 0) + (const_int 9) (const_int 1) + (const_int 10) (const_int 2) + (const_int 11) (const_int 3)])))] + "ISA_HAS_MSA" + "ilvr.h\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvr_w" + [(set (match_operand:V4SI 0 "register_operand" "=f") + (vec_select:V4SI (vec_concat:V8SI + (match_operand:V4SI 1 "register_operand" "f") + (match_operand:V4SI 2 "register_operand" "f")) + (parallel [(const_int 4) (const_int 0) + (const_int 5) (const_int 1)])))] "ISA_HAS_MSA" - "ilvr.<msafmt>\t%w0,%w1,%w2" + "ilvr.w\t%w0,%w1,%w2" + [(set_attr "alu_type" "add") + (set_attr "mode" "TI") + (set_attr "msa_execunit" "msa_eu_logic")]) + +(define_insn "msa_ilvr_d" + [(set (match_operand:V2DI 0 "register_operand" "=f") + (vec_select:V2DI (vec_concat:V4DI + (match_operand:V2DI 1 "register_operand" "f") + (match_operand:V2DI 2 "register_operand" "f")) + (parallel [(const_int 2) (const_int 0)])))] + "ISA_HAS_MSA" + "ilvr.d\t%w0,%w1,%w2" [(set_attr "alu_type" "add") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_logic")]) @@ -2211,22 +2531,20 @@ (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_int_add")]) -(define_insn "msa_max_s_<msafmt>" +(define_insn "smax<mode>3" [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] - UNSPEC_MSA_MAX_S))] + (smax:IMSA (match_operand:IMSA 1 "register_operand" "f") + (match_operand:IMSA 2 "register_operand" "f")))] "ISA_HAS_MSA" "max_s.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_int_add")]) -(define_insn "msa_max_u_<msafmt>" +(define_insn "umax<mode>3" [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] - UNSPEC_MSA_MAX_U))] + (umax:IMSA (match_operand:IMSA 1 "register_operand" "f") + (match_operand:IMSA 2 "register_operand" "f")))] "ISA_HAS_MSA" "max_u.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") @@ -2266,22 +2584,20 @@ (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_int_add")]) -(define_insn "msa_min_s_<msafmt>" +(define_insn "smin<mode>3" [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] - UNSPEC_MSA_MIN_S))] + (smin:IMSA (match_operand:IMSA 1 "register_operand" "f") + (match_operand:IMSA 2 "register_operand" "f")))] "ISA_HAS_MSA" "min_s.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_int_add")]) -(define_insn "msa_min_u_<msafmt>" +(define_insn "umin<mode>3" [(set (match_operand:IMSA 0 "register_operand" "=f") - (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") - (match_operand:IMSA 2 "register_operand" "f")] - UNSPEC_MSA_MIN_U))] + (umin:IMSA (match_operand:IMSA 1 "register_operand" "f") + (match_operand:IMSA 2 "register_operand" "f")))] "ISA_HAS_MSA" "min_u.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") @@ -2364,7 +2680,10 @@ "nloc.<msafmt>\t%w0,%w1" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "clz<mode>2" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2373,7 +2692,10 @@ "nlzc.<msafmt>\t%w0,%w1" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_nor_v_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2435,7 +2757,10 @@ "pcnt.<msafmt>\t%w0,%w1" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic3") + (const_string "msa_eu_logic")))]) (define_insn "msa_sat_s_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2468,7 +2793,11 @@ "shf.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set_attr "datafmt" "<msafmt>") + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_shf_w_f" [(set (match_operand:V4SF 0 "register_operand" "=f") @@ -2479,7 +2808,10 @@ "shf.w\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_slli_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2490,7 +2822,10 @@ "slli.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_srai_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2501,7 +2836,10 @@ "srai.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_srar_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2512,7 +2850,10 @@ "srar.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_srari_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2523,7 +2864,10 @@ "srari.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_srli_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2534,7 +2878,10 @@ "srli.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_srlr_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2545,7 +2892,10 @@ "srlr.<msafmt>\t%w0,%w1,%w2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_srlri_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2556,7 +2906,10 @@ "srlri.<msafmt>\t%w0,%w1,%2" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic2") + (const_string "msa_eu_logic")))]) (define_insn "msa_subs_s_<msafmt>" [(set (match_operand:IMSA 0 "register_operand" "=f") @@ -2634,7 +2987,10 @@ "sld.<msafmt>\t%w0,%w2[%z3]" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic_l")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic_l2") + (const_string "msa_eu_logic_l")))]) (define_insn "msa_sldi_<msafmt_f>" [(set (match_operand:MSA 0 "register_operand" "=f") @@ -2646,7 +3002,10 @@ "sldi.<msafmt>\t%w0,%w2[%3]" [(set_attr "type" "arith") (set_attr "mode" "TI") - (set_attr "msa_execunit" "msa_eu_logic_l")]) + (set (attr "msa_execunit") + (if_then_else (eq_attr "cpu" "i6400") + (const_string "msa_eu_logic_l2") + (const_string "msa_eu_logic_l")))]) (define_insn "msa_splat_<msafmt_f>" [(set (match_operand:MSA 0 "register_operand" "=f") @@ -2673,9 +3032,9 @@ ;; operand 1 is a scalar (define_insn "msa_splati_<msafmt_f>_s" [(set (match_operand:FMSA 0 "register_operand" "=f") - (unspec:<MODE> [(match_operand:<UNITMODE> 1 "register_operand" "f") - (match_operand 2 "const_<indeximm>_operand" "")] - UNSPEC_MSA_SPLATI))] + (unspec:FMSA [(match_operand:<UNITMODE> 1 "register_operand" "f") + (match_operand 2 "const_<indeximm>_operand" "")] + UNSPEC_MSA_SPLATI))] "ISA_HAS_MSA" "splati.<msafmt>\t%w0,%w1[%2]" [(set_attr "type" "arith") @@ -2715,11 +3074,11 @@ (define_insn "msa_fexdo_w" [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V2DF 1 "register_operand" "f") - (match_operand:V2DF 2 "register_operand" "f")] - UNSPEC_MSA_FEXDO))] + (vec_concat:V4SF + (float_truncate:V2SF (match_operand:V2DF 1 "register_operand" "f")) + (float_truncate:V2SF (match_operand:V2DF 2 "register_operand" "f"))))] "ISA_HAS_MSA" - "fexdo.w\t%w0,%w1,%w2" + "fexdo.w\t%w0,%w2,%w1" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_float4")]) @@ -2746,8 +3105,8 @@ (define_insn "msa_fexupr_w" [(set (match_operand:V4SF 0 "register_operand" "=f") - (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")] - UNSPEC_MSA_FEXUPR))] + (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")] + UNSPEC_MSA_FEXUPR))] "ISA_HAS_MSA" "fexupr.w\t%w0,%w1" [(set_attr "type" "arith") @@ -2756,15 +3115,15 @@ (define_insn "msa_fexupr_d" [(set (match_operand:V2DF 0 "register_operand" "=f") - (unspec:V2DF [(match_operand:V4SF 1 "register_operand" "f")] - UNSPEC_MSA_FEXUPR))] + (unspec:V2DF [(match_operand:V4SF 1 "register_operand" "f")] + UNSPEC_MSA_FEXUPR))] "ISA_HAS_MSA" "fexupr.d\t%w0,%w1" [(set_attr "type" "arith") (set_attr "mode" "TI") (set_attr "msa_execunit" "msa_eu_float4")]) -(define_insn "msa_branch_nz_v_<msafmt_f>" +(define_insn "msa_branch_nz_v_<msafmt_f>" [(set (pc) (if_then_else (ne (unspec:SI [(match_operand:MSA 1 "register_operand" "f")] UNSPEC_MSA_BNZ_V) @@ -2830,7 +3189,7 @@ return mips_output_conditional_branch (insn, operands, MIPS_BRANCH ("bnz.<msafmt>", "%w1,%0"), MIPS_BRANCH ("bz.<msafmt>", "%w1,%0")); - + } [(set_attr "type" "branch") |