diff options
Diffstat (limited to 'gcc-4.9/gcc/config/mips/i6400.md')
| -rw-r--r-- | gcc-4.9/gcc/config/mips/i6400.md | 335 |
1 files changed, 335 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/config/mips/i6400.md b/gcc-4.9/gcc/config/mips/i6400.md new file mode 100644 index 000000000..1950f3a7c --- /dev/null +++ b/gcc-4.9/gcc/config/mips/i6400.md @@ -0,0 +1,335 @@ +;; DFA-based pipeline description for i6400. + +;; Copyright (C) 2007-2014 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +(define_automaton "i6400_int_pipe, i6400_mdu_pipe, i6400_fpu_short_pipe, + i6400_fpu_long_pipe") + +(define_cpu_unit "i6400_gpmuldiv" "i6400_mdu_pipe") + +(define_cpu_unit "i6400_agen, i6400_alu1, i6400_lsu" "i6400_int_pipe") + +(define_cpu_unit "i6400_control, i6400_ctu, i6400_alu0" "i6400_int_pipe") + +;; The floating-point-unit queue (FPQ) has short and long pipes + +;; Short FPU pipeline. +(define_cpu_unit "i6400_fpu_short, i6400_fpu_intadd, i6400_fpu_logic, + i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, i6400_fpu_store" + "i6400_fpu_short_pipe") + +;; Long FPU pipeline. +(define_cpu_unit "i6400_fpu_long, i6400_fpu_logic_l, i6400_fpu_float_l, + i6400_fpu_mult, i6400_fpu_apu" "i6400_fpu_long_pipe") + +(define_reservation "i6400_control_ctu" "i6400_control, i6400_ctu") +(define_reservation "i6400_control_alu0" "i6400_control, i6400_alu0") +(define_reservation "i6400_agen_lsu" "i6400_agen, i6400_lsu") +(define_reservation "i6400_agen_alu1" "i6400_agen, i6400_alu1") + +;; +;; FPU-MSA pipe +;; + +;; Short pipe + +;; addv, subv +(define_insn_reservation "i6400_msa_add_d" 1 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "datafmt" "!d") + (and (eq_attr "alu_type" "add, sub") + (eq_attr "msa_execunit" "msa_eu_int_add")))) + "i6400_fpu_short, i6400_fpu_intadd") + +;; add, hadd, sub, hsub, average, min, max, compare +(define_insn_reservation "i6400_msa_int_add" 2 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_int_add")) + "i6400_fpu_short, i6400_fpu_intadd") + +;; sat, pcnt +(define_insn_reservation "i6400_msa_short_logic3" 3 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_logic3")) + "i6400_fpu_short, i6400_fpu_logic") + +;; shf.d +(define_insn_reservation "i6400_msa_shf_d" 1 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "datafmt" "d") + (eq_attr "msa_execunit" "msa_eu_logic2"))) + "i6400_fpu_short, i6400_fpu_logic") + +;; shifts, nloc, nlzc, bneg, bclr, shf +(define_insn_reservation "i6400_msa_short_logic2" 2 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_logic2")) + "i6400_fpu_short, i6400_fpu_logic") + +;; and, or, xor, ilv, pck, move.v, fill, splat +(define_insn_reservation "i6400_msa_short_logic" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_logic")) + "i6400_fpu_short, i6400_fpu_logic") + +;; move.v, ldi +(define_insn_reservation "i6400_msa_move" 1 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "type" "fmove") + (eq_attr "mode" "TI"))) + "i6400_fpu_short, i6400_fpu_logic") + +;; Float compare New: CMP.cond.fmt +(define_insn_reservation "i6400_msa_cmp" 2 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_cmp")) + "i6400_fpu_short, i6400_fpu_cmp") + +;; Float min, max, class +(define_insn_reservation "i6400_msa_short_float2" 2 + (and (eq_attr "cpu" "i6400") + (ior (and (eq_attr "msa_execunit" "msa_eu_float2") + (eq_attr "type" "!fmul")) + (and (eq_attr "msa_execunit" "msa_eu_float2_l") + (eq_attr "type" "fcmp")))) + "i6400_fpu_short, i6400_fpu_float") + +;; div.d, mod.d (non-pipelined) +(define_insn_reservation "i6400_msa_div_d" 36 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "datafmt" "d") + (eq_attr "msa_execunit" "msa_eu_div"))) + "i6400_fpu_short+i6400_fpu_div*36") + +;; div.w, mod.w (non-pipelined) +(define_insn_reservation "i6400_msa_div_w" 20 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "datafmt" "w") + (eq_attr "msa_execunit" "msa_eu_div"))) + "i6400_fpu_short+i6400_fpu_div*20") + +;; div.h, mod.h (non-pipelined) +(define_insn_reservation "i6400_msa_div_h" 12 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "datafmt" "h") + (eq_attr "msa_execunit" "msa_eu_div"))) + "i6400_fpu_short+i6400_fpu_div*12") + +;; div.b, mod.b (non-pipelined) +(define_insn_reservation "i6400_msa_div_b" 8 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "datafmt" "b") + (eq_attr "msa_execunit" "msa_eu_div"))) + "i6400_fpu_short+i6400_fpu_div*8") + +;; Vector copy +(define_insn_reservation "i6400_msa_copy" 1 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "msa_execunit" "msa_eu_store4") + (eq_attr "type" "mfc, mtc"))) + "i6400_fpu_short, i6400_fpu_store") + +;; Vector bz, bnz +(define_insn_reservation "i6400_msa_branch" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_store4")) + "i6400_control_ctu") + +;; Vector store, sdc1, swc1 +(define_insn_reservation "i6400_fpu_msa_store" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fpstore")) + "i6400_agen_lsu") + +;; Vector load, ldc1, lwc1 +(define_insn_reservation "i6400_fpu_msa_load" 3 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fpload")) + "i6400_agen_lsu") + +;; mfc, mtc +(define_insn_reservation "i6400_fpu_move" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "move_type" "mfc, mtc")) + "i6400_control_alu0 | i6400_agen_alu1") + +;; Long pipe + +;; bmz, bmnz, bsel, insert, insve +(define_insn_reservation "i6400_msa_long_logic1" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_logic_l")) + "i6400_fpu_long, i6400_fpu_logic_l") + +;; binsl, binsr, vshf, sld +(define_insn_reservation "i6400_msa_long_logic2" 2 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_logic_l2")) + "i6400_fpu_long, i6400_fpu_logic_l") + +;; Vector mul, dotp, madd, msub +(define_insn_reservation "i6400_msa_mult" 5 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_mult")) + "i6400_fpu_long, i6400_fpu_mult") + +;; Float flog2 +(define_insn_reservation "i6400_msa_long_float2" 2 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "msa_execunit" "msa_eu_float2_l") + (eq_attr "type" "fmul"))) + "i6400_fpu_long, i6400_fpu_float_l") + +;; fadd, fsub +(define_insn_reservation "i6400_msa_long_float4" 4 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_float4")) + "i6400_fpu_long, i6400_fpu_float_l") + +;; fmul, fexp2 +(define_insn_reservation "i6400_msa_long_float5" 5 + (and (eq_attr "cpu" "i6400") + (ior (eq_attr "msa_execunit" "msa_eu_float5") + (and (eq_attr "msa_execunit" "msa_eu_float2") + (eq_attr "type" "fmul")))) + "i6400_fpu_long, i6400_fpu_float_l") + +;; fmadd, fmsub +(define_insn_reservation "i6400_msa_long_float8" 8 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_float8")) + "i6400_fpu_long, i6400_fpu_float_l") + +;; fdiv.d +(define_insn_reservation "i6400_msa_fdiv_df" 30 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "mode" "DF") + (eq_attr "msa_execunit" "msa_eu_fdiv"))) + "i6400_fpu_long+i6400_fpu_float_l*30") + +;; fdiv.w +(define_insn_reservation "i6400_msa_fdiv_sf" 22 + (and (eq_attr "cpu" "i6400") + (eq_attr "msa_execunit" "msa_eu_fdiv")) + "i6400_fpu_long+i6400_fpu_float_l*22") + +;; +;; FPU pipe +;; + +;; fabs, fneg +(define_insn_reservation "i6400_fpu_fabs" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fabs,fneg,fmove")) + "i6400_fpu_short, i6400_fpu_apu") + +;; fadd, fsub, fcvt +(define_insn_reservation "i6400_fpu_fadd" 4 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fadd, fcvt")) + "i6400_fpu_long, i6400_fpu_apu") + +;; fmul +(define_insn_reservation "i6400_fpu_fmul" 5 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fmul")) + "i6400_fpu_long, i6400_fpu_apu") + +;; div, sqrt (Double Precision) +(define_insn_reservation "i6400_fpu_div_df" 30 + (and (eq_attr "cpu" "i6400") + (and (eq_attr "mode" "DF") + (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt"))) + "i6400_fpu_long+i6400_fpu_apu*30") + +;; div, sqrt (Single Precision) +(define_insn_reservation "i6400_fpu_div_sf" 22 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")) + "i6400_fpu_long+i6400_fpu_apu*22") + +;; +;; Integer pipe +;; + +;; and, lui, shifts, seb, seh +(define_insn_reservation "i6400_int_logical" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "move_type" "logical,const,andi,sll0,signext")) + "i6400_control_alu0 | i6400_agen_alu1") + +;; addi, addiu, ori, xori, add, addu, sub, nor +(define_insn_reservation "i6400_int_add" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "alu_type" "add,sub,or,xor,nor")) + "i6400_control_alu0 | i6400_agen_alu1") + +;; shifts, clo, clz, cond move, arith +(define_insn_reservation "i6400_int_arith" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "shift,slt,move,clz,condmove,arith")) + "i6400_control_alu0 | i6400_agen_alu1") + +;; nop +(define_insn_reservation "i6400_int_nop" 0 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "nop")) + "nothing") + +;; mult, multu, mul +(define_insn_reservation "i6400_int_mult" 4 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "imul3,imul")) + "i6400_gpmuldiv") + +;; divide +(define_insn_reservation "i6400_int_div" 32 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "idiv")) + "i6400_gpmuldiv*32") + +;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs +(define_insn_reservation "i6400_int_load" 3 + (and (eq_attr "cpu" "i6400") + (eq_attr "move_type" "load")) + "i6400_agen_lsu") + +;; store +(define_insn_reservation "i6400_int_store" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "move_type" "store")) + "i6400_agen_lsu") + +;; prefetch +(define_insn_reservation "i6400_int_prefetch" 3 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "prefetch")) + "i6400_agen_lsu") + +;; branch and jump +(define_insn_reservation "i6400_int_branch" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "type" "branch,jump")) + "i6400_control_ctu") + +;; call +(define_insn_reservation "i6400_int_call" 1 + (and (eq_attr "cpu" "i6400") + (eq_attr "jal" "indirect,direct")) + "i6400_control_ctu") |