diff options
Diffstat (limited to 'gcc-4.9/gcc/config/mips/constraints.md')
| -rw-r--r-- | gcc-4.9/gcc/config/mips/constraints.md | 70 |
1 files changed, 64 insertions, 6 deletions
diff --git a/gcc-4.9/gcc/config/mips/constraints.md b/gcc-4.9/gcc/config/mips/constraints.md index 49e48954f..92ab2dee5 100644 --- a/gcc-4.9/gcc/config/mips/constraints.md +++ b/gcc-4.9/gcc/config/mips/constraints.md @@ -19,7 +19,7 @@ ;; Register constraints -(define_register_constraint "d" "BASE_REG_CLASS" +(define_register_constraint "d" "TARGET_MIPS16 ? M16_REGS : GR_REGS" "An address register. This is equivalent to @code{r} unless generating MIPS16 code.") @@ -92,6 +92,9 @@ ;; but the DSP version allows any accumulator target. (define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS") +(define_register_constraint "kb" "M16_STORE_REGS" + "@internal") + (define_constraint "kf" "@internal" (match_operand 0 "force_to_mem_operand")) @@ -305,6 +308,61 @@ "@internal" (match_operand 0 "low_bitmask_operand")) +(define_constraint "YI" + "@internal + A replicated vector const in which the replicated is a 10-bit signed + value." + (and (match_code "const_vector") + (match_test "mips_const_vector_same_int_p (op, mode, -1024, 1023)"))) + +(define_constraint "YC" + "@internal + A replicated vector const in which the replicated value has a single + bit set." + (and (match_code "const_vector") + (match_test "mips_const_vector_bitimm_set_p (op, mode)"))) + +(define_constraint "YZ" + "@internal + A replicated vector const in which the replicated value has a single + bit clear." + (and (match_code "const_vector") + (match_test "mips_const_vector_bitimm_clr_p (op, mode)"))) + +(define_constraint "Unv5" + "@internal + A replicated vector const in which the replicated value is negative + integer number in range [-31,0]." + (and (match_code "const_vector") + (match_test "mips_const_vector_same_int_p (op, mode, -31, 0)"))) + +(define_constraint "Uuv5" + "@internal + A replicated vector const in which the replicated value is positive + integer number in range [0,31]." + (and (match_code "const_vector") + (match_test "mips_const_vector_same_int_p (op, mode, 0, 31)"))) + +(define_constraint "Uuv6" + "@internal + A replicated vector const in which the replicated value is a unsigned + 6-bit integer number." + (and (match_code "const_vector") + (match_test "mips_const_vector_same_int_p (op, mode, 0, 63)"))) + +(define_constraint "Uuv8" + "@internal + A replicated vector const in which the replicated value is a unsigned + 8-bit integer number." + (and (match_code "const_vector") + (match_test "mips_const_vector_same_int_p (op, mode, 0, 255)"))) + +(define_constraint "Ubv8" + "@internal + A replicated vector const in which the replicated value is a 8-bit byte." + (and (match_code "const_vector") + (match_test "mips_const_vector_same_byte_p (op, mode)"))) + (define_memory_constraint "ZC" "When compiling microMIPS code, this constraint matches a memory operand whose address is formed from a base register and a 12-bit offset. These @@ -318,13 +376,13 @@ (match_test "mips_address_insns (XEXP (op, 0), mode, false)")))) (define_address_constraint "ZD" - "When compiling microMIPS code, this constraint matches an address operand - that is formed from a base register and a 12-bit offset. These operands - can be used for microMIPS instructions such as @code{prefetch}. When - not compiling for microMIPS code, @code{ZD} is equivalent to @code{p}." + "An address suitable for a @code{prefetch} instruction, or for any other + instruction with the same addressing mode as @code{prefetch}." (if_then_else (match_test "TARGET_MICROMIPS") (match_test "umips_12bit_offset_address_p (op, mode)") - (match_test "mips_address_insns (op, mode, false)"))) + (if_then_else (match_test "ISA_HAS_PREFETCH_9BIT") + (match_test "mips_9bit_offset_address_p (op, mode)") + (match_test "mips_address_insns (op, mode, false)")))) (define_memory_constraint "ZR" "@internal |