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Diffstat (limited to 'gcc-4.9/gcc/config/arm/arm.opt')
| -rw-r--r-- | gcc-4.9/gcc/config/arm/arm.opt | 277 |
1 files changed, 277 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/config/arm/arm.opt b/gcc-4.9/gcc/config/arm/arm.opt new file mode 100644 index 000000000..d80f1f13b --- /dev/null +++ b/gcc-4.9/gcc/config/arm/arm.opt @@ -0,0 +1,277 @@ +; Options for the ARM port of the compiler. + +; Copyright (C) 2005-2014 Free Software Foundation, Inc. +; +; This file is part of GCC. +; +; GCC is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License as published by the Free +; Software Foundation; either version 3, or (at your option) any later +; version. +; +; GCC is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +; for more details. +; +; You should have received a copy of the GNU General Public License +; along with GCC; see the file COPYING3. If not see +; <http://www.gnu.org/licenses/>. + +HeaderInclude +config/arm/arm-opts.h + +Enum +Name(tls_type) Type(enum arm_tls_type) +TLS dialect to use: + +EnumValue +Enum(tls_type) String(gnu) Value(TLS_GNU) + +EnumValue +Enum(tls_type) String(gnu2) Value(TLS_GNU2) + +mabi= +Target RejectNegative Joined Enum(arm_abi_type) Var(arm_abi) Init(ARM_DEFAULT_ABI) +Specify an ABI + +Enum +Name(arm_abi_type) Type(enum arm_abi_type) +Known ARM ABIs (for use with the -mabi= option): + +EnumValue +Enum(arm_abi_type) String(apcs-gnu) Value(ARM_ABI_APCS) + +EnumValue +Enum(arm_abi_type) String(atpcs) Value(ARM_ABI_ATPCS) + +EnumValue +Enum(arm_abi_type) String(aapcs) Value(ARM_ABI_AAPCS) + +EnumValue +Enum(arm_abi_type) String(iwmmxt) Value(ARM_ABI_IWMMXT) + +EnumValue +Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) + +mabort-on-noreturn +Target Report Mask(ABORT_NORETURN) +Generate a call to abort if a noreturn function returns + +mapcs +Target RejectNegative Mask(APCS_FRAME) Undocumented + +mapcs-float +Target Report Mask(APCS_FLOAT) +Pass FP arguments in FP registers + +mapcs-frame +Target Report Mask(APCS_FRAME) +Generate APCS conformant stack frames + +mapcs-reentrant +Target Report Mask(APCS_REENT) +Generate re-entrant, PIC code + +mapcs-stack-check +Target Report Mask(APCS_STACK) Undocumented + +march= +Target RejectNegative ToLower Joined Enum(arm_arch) Var(arm_arch_option) +Specify the name of the target architecture + +; Other arm_arch values are loaded from arm-tables.opt +; but that is a generated file and this is an odd-one-out. +EnumValue +Enum(arm_arch) String(native) Value(-1) DriverOnly + +marm +Target Report RejectNegative InverseMask(THUMB) +Generate code in 32 bit ARM state. + +mbig-endian +Target Report RejectNegative Mask(BIG_END) +Assume target CPU is configured as big endian + +mcallee-super-interworking +Target Report Mask(CALLEE_INTERWORKING) +Thumb: Assume non-static functions may be called from ARM code + +mcaller-super-interworking +Target Report Mask(CALLER_INTERWORKING) +Thumb: Assume function pointers may go to non-Thumb aware code + +mcpu= +Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_cpu_option) Init(arm_none) +Specify the name of the target CPU + +mfloat-abi= +Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI) +Specify if floating point hardware should be used + +Enum +Name(float_abi_type) Type(enum float_abi_type) +Known floating-point ABIs (for use with the -mfloat-abi= option): + +EnumValue +Enum(float_abi_type) String(soft) Value(ARM_FLOAT_ABI_SOFT) + +EnumValue +Enum(float_abi_type) String(softfp) Value(ARM_FLOAT_ABI_SOFTFP) + +EnumValue +Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD) + +mfp16-format= +Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE) +Specify the __fp16 floating-point format + +Enum +Name(arm_fp16_format_type) Type(enum arm_fp16_format_type) +Known __fp16 formats (for use with the -mfp16-format= option): + +EnumValue +Enum(arm_fp16_format_type) String(none) Value(ARM_FP16_FORMAT_NONE) + +EnumValue +Enum(arm_fp16_format_type) String(ieee) Value(ARM_FP16_FORMAT_IEEE) + +EnumValue +Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE) + +mfpu= +Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) +Specify the name of the target floating point hardware/format + +mlra +Target Report Var(arm_lra_flag) Init(1) Save +Use LRA instead of reload (transitional) + +mhard-float +Target RejectNegative Alias(mfloat-abi=, hard) Undocumented + +mlittle-endian +Target Report RejectNegative InverseMask(BIG_END) +Assume target CPU is configured as little endian + +mlong-calls +Target Report Mask(LONG_CALLS) +Generate call insns as indirect calls, if necessary + +mpic-data-is-text-relative +Target Report Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) +Assume data segments are relative to text segment. + +mpic-register= +Target RejectNegative Joined Var(arm_pic_register_string) +Specify the register to be used for PIC addressing + +mpoke-function-name +Target Report Mask(POKE_FUNCTION_NAME) +Store function names in object code + +msched-prolog +Target Report Mask(SCHED_PROLOG) +Permit scheduling of a function's prologue sequence + +msingle-pic-base +Target Report Mask(SINGLE_PIC_BASE) +Do not load the PIC register in function prologues + +msoft-float +Target RejectNegative Alias(mfloat-abi=, soft) Undocumented + +mstructure-size-boundary= +Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFAULT_STRUCTURE_SIZE_BOUNDARY) +Specify the minimum bit alignment of structures + +mthumb +Target Report RejectNegative Mask(THUMB) +Generate code for Thumb state + +mthumb-interwork +Target Report Mask(INTERWORK) +Support calls between Thumb and ARM instruction sets + +mtls-dialect= +Target RejectNegative Joined Enum(tls_type) Var(target_tls_dialect) Init(TLS_GNU) +Specify thread local storage scheme + +mtp= +Target RejectNegative Joined Enum(arm_tp_type) Var(target_thread_pointer) Init(TP_AUTO) +Specify how to access the thread pointer + +Enum +Name(arm_tp_type) Type(enum arm_tp_type) +Valid arguments to -mtp=: + +EnumValue +Enum(arm_tp_type) String(soft) Value(TP_SOFT) + +EnumValue +Enum(arm_tp_type) String(auto) Value(TP_AUTO) + +EnumValue +Enum(arm_tp_type) String(cp15) Value(TP_CP15) + +mtpcs-frame +Target Report Mask(TPCS_FRAME) +Thumb: Generate (non-leaf) stack frames even if not needed + +mtpcs-leaf-frame +Target Report Mask(TPCS_LEAF_FRAME) +Thumb: Generate (leaf) stack frames even if not needed + +mtune= +Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_tune_option) Init(arm_none) +Tune code for the given processor + +; Other processor_type values are loaded from arm-tables.opt +; but that is a generated file and this is an odd-one-out. +EnumValue +Enum(processor_type) String(native) Value(-1) DriverOnly + +mwords-little-endian +Target Report RejectNegative Mask(LITTLE_WORDS) +Assume big endian bytes, little endian words. This option is deprecated. + +mvectorize-with-neon-quad +Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE) +Use Neon quad-word (rather than double-word) registers for vectorization + +mvectorize-with-neon-double +Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE) +Use Neon double-word (rather than quad-word) registers for vectorization + +mword-relocations +Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) +Only generate absolute relocations on word sized values. + +mrestrict-it +Target Report Var(arm_restrict_it) Init(2) +Generate IT blocks appropriate for ARMv8. + +mold-rtx-costs +Target Report Mask(OLD_RTX_COSTS) +Use the old RTX costing tables (transitional). + +mnew-generic-costs +Target Report Mask(NEW_GENERIC_COSTS) +Use the new generic RTX cost tables if new core-specific cost table not available (transitional). + +mfix-cortex-m3-ldrd +Target Report Var(fix_cm3_ldrd) Init(2) +Avoid overlapping destination and address registers on LDRD instructions +that may trigger Cortex-M3 errata. + +munaligned-access +Target Report Var(unaligned_access) Init(2) +Enable unaligned word and halfword accesses to packed data. + +mneon-for-64bits +Target Report RejectNegative Var(use_neon_for_64bits) Init(0) +Use Neon to perform 64-bits operations rather than core registers. + +mslow-flash-data +Target Report Var(target_slow_flash_data) Init(0) +Assume loading data from flash is slower than fetching instructions. |