diff options
Diffstat (limited to 'gcc-4.9/gcc/config/arm/arm.md')
| -rw-r--r-- | gcc-4.9/gcc/config/arm/arm.md | 121 |
1 files changed, 11 insertions, 110 deletions
diff --git a/gcc-4.9/gcc/config/arm/arm.md b/gcc-4.9/gcc/config/arm/arm.md index 2ddda0208..4b81ee272 100644 --- a/gcc-4.9/gcc/config/arm/arm.md +++ b/gcc-4.9/gcc/config/arm/arm.md @@ -262,105 +262,6 @@ ; initialized by arm_option_override() (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))) -; YES if the "type" attribute assigned to the insn denotes an -; Advanced SIMD instruction, NO otherwise. -(define_attr "is_neon_type" "yes,no" - (if_then_else (eq_attr "type" - "neon_add, neon_add_q, neon_add_widen, neon_add_long,\ - neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\ - neon_add_halve_narrow_q,\ - neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\ - neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\ - neon_sub_halve_narrow_q,\ - neon_abs, neon_abs_q, neon_neg, neon_neg_q, neon_qneg,\ - neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\ - neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\ - neon_compare_q, neon_compare_zero, neon_compare_zero_q,\ - neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\ - neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\ - neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\ - neon_logic, neon_logic_q, neon_tst, neon_tst_q,\ - neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\ - neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\ - neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\ - neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\ - neon_sat_shift_reg, neon_sat_shift_reg_q,\ - neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\ - neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\ - neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\ - neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\ - neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\ - neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\ - neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\ - neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\ - neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\ - neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\ - neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\ - neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\ - neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\ - neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\ - neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\ - neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\ - neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\ - neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\ - neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\ - neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\ - neon_mla_h_scalar_long, neon_mla_s_scalar_long,\ - neon_sat_mla_b_long, neon_sat_mla_h_long,\ - neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\ - neon_sat_mla_s_scalar_long,\ - neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\ - neon_ldr, neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\ - neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\ - neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\ - neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\ - neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\ - neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\ - neon_load2_one_lane, neon_load2_one_lane_q,\ - neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\ - neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\ - neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\ - neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\ - neon_str, neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\ - neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\ - neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\ - neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\ - neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\ - neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\ - neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\ - neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\ - neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\ - neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\ - neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\ - neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\ - neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\ - neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\ - neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s, - neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\ - neon_fp_reduc_minmax_d_q,\ - neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\ - neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\ - neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\ - neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\ - neon_fp_recpe_s_q,\ - neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\ - neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\ - neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\ - neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\ - neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\ - neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\ - neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\ - neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\ - neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\ - neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\ - neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\ - neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\ - neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aes,\ - crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow, crypto_sha256_fast,\ - crypto_sha256_slow") - (const_string "yes") - (const_string "no"))) - ; condition codes: this one is used by final_prescan_insn to speed up ; conditionalizing instructions. It saves having to scan the rtl to see if ; it uses or alters the condition codes. @@ -2883,8 +2784,8 @@ (define_insn "insv_zero" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") - (match_operand:SI 1 "const_int_operand" "M") - (match_operand:SI 2 "const_int_operand" "M")) + (match_operand:SI 1 "const_int_M_operand" "M") + (match_operand:SI 2 "const_int_M_operand" "M")) (const_int 0))] "arm_arch_thumb2" "bfc%?\t%0, %2, %1" @@ -2896,8 +2797,8 @@ (define_insn "insv_t2" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") - (match_operand:SI 1 "const_int_operand" "M") - (match_operand:SI 2 "const_int_operand" "M")) + (match_operand:SI 1 "const_int_M_operand" "M") + (match_operand:SI 2 "const_int_M_operand" "M")) (match_operand:SI 3 "s_register_operand" "r"))] "arm_arch_thumb2" "bfi%?\t%0, %3, %2, %1" @@ -4579,8 +4480,8 @@ (define_insn "*extv_reg" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_operand" "M") - (match_operand:SI 3 "const_int_operand" "M")))] + (match_operand:SI 2 "const_int_M_operand" "M") + (match_operand:SI 3 "const_int_M_operand" "M")))] "arm_arch_thumb2" "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") @@ -4592,8 +4493,8 @@ (define_insn "extzv_t2" [(set (match_operand:SI 0 "s_register_operand" "=r") (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_operand" "M") - (match_operand:SI 3 "const_int_operand" "M")))] + (match_operand:SI 2 "const_int_M_operand" "M") + (match_operand:SI 3 "const_int_M_operand" "M")))] "arm_arch_thumb2" "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") @@ -12172,7 +12073,7 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:SI 3 "s_register_operand" "=rk") (mem:SI (match_dup 1))) ])] @@ -12201,7 +12102,7 @@ [(return) (set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:SI 3 "s_register_operand" "=rk") (mem:SI (match_dup 1))) ])] @@ -12254,7 +12155,7 @@ [(match_parallel 0 "pop_multiple_fp" [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" |