diff options
Diffstat (limited to 'gcc-4.9/gcc/config/aarch64')
| -rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64-cores.def | 2 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64-elf-raw.h | 6 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64-linux.h | 7 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64-tune.md | 2 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64.c | 12 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64.md | 6 | ||||
| -rw-r--r-- | gcc-4.9/gcc/config/aarch64/aarch64.opt | 4 |
7 files changed, 30 insertions, 9 deletions
diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-cores.def b/gcc-4.9/gcc/config/aarch64/aarch64-cores.def index 9319249e6..56d312e8e 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64-cores.def +++ b/gcc-4.9/gcc/config/aarch64/aarch64-cores.def @@ -35,7 +35,7 @@ /* V8 Architecture Processors. */ AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8, AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa53) -AARCH64_CORE("cortex-a57", cortexa15, cortexa15, 8, AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57) +AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8, AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57) /* V8 big.LITTLE implementations. */ diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-elf-raw.h b/gcc-4.9/gcc/config/aarch64/aarch64-elf-raw.h index bb5c88d53..67271b29d 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64-elf-raw.h +++ b/gcc-4.9/gcc/config/aarch64/aarch64-elf-raw.h @@ -41,10 +41,14 @@ " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}" #endif +#define CA53_ERR_843419_SPEC \ + " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}" + #ifndef LINK_SPEC #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \ -maarch64elf%{mabi=ilp32*:32}%{mbig-endian:b}" \ - CA53_ERR_835769_SPEC + CA53_ERR_835769_SPEC \ + CA53_ERR_843419_SPEC #endif #endif /* GCC_AARCH64_ELF_RAW_H */ diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-linux.h b/gcc-4.9/gcc/config/aarch64/aarch64-linux.h index 651abe3ce..f42ea1afc 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64-linux.h +++ b/gcc-4.9/gcc/config/aarch64/aarch64-linux.h @@ -48,7 +48,12 @@ " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}" #endif -#define LINUX_TARGET_LINK_SPEC LINUX_TARGET_LINK_SPEC0 CA53_ERR_835769_SPEC +#define CA53_ERR_843419_SPEC \ + " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}" + +#define LINUX_TARGET_LINK_SPEC LINUX_TARGET_LINK_SPEC0 \ + CA53_ERR_835769_SPEC \ + CA53_ERR_843419_SPEC #ifdef TARGET_FIX_ERR_A53_835769_DEFAULT #define CA53_ERR_835769_SPEC \ diff --git a/gcc-4.9/gcc/config/aarch64/aarch64-tune.md b/gcc-4.9/gcc/config/aarch64/aarch64-tune.md index b7e40e0b5..ac7b7741b 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64-tune.md +++ b/gcc-4.9/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa53,cortexa15,cortexa57cortexa53" + "cortexa53,cortexa57,cortexa57cortexa53" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.c b/gcc-4.9/gcc/config/aarch64/aarch64.c index 6b2717471..f9e8c4067 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64.c +++ b/gcc-4.9/gcc/config/aarch64/aarch64.c @@ -184,8 +184,10 @@ __extension__ static const struct cpu_regmove_cost generic_regmove_cost = { NAMED_PARAM (GP2GP, 1), - NAMED_PARAM (GP2FP, 2), - NAMED_PARAM (FP2GP, 2), + /* Avoid the use of slow int<->fp moves for spilling by setting + their cost higher than memmov_cost. */ + NAMED_PARAM (GP2FP, 5), + NAMED_PARAM (FP2GP, 5), /* We currently do not provide direct support for TFmode Q->Q move. Therefore we need to raise the cost above 2 in order to have reload handle the situation. */ @@ -4481,6 +4483,7 @@ aarch64_strip_shift_or_extend (rtx x) /* Zero and sign extraction of a widened value. */ if ((GET_CODE (op) == ZERO_EXTRACT || GET_CODE (op) == SIGN_EXTRACT) && XEXP (op, 2) == const0_rtx + && GET_CODE (XEXP (op, 0)) == MULT && aarch64_is_extend_from_extract (GET_MODE (op), XEXP (XEXP (op, 0), 1), XEXP (op, 1))) return XEXP (XEXP (op, 0), 0); @@ -5275,6 +5278,11 @@ aarch64_override_options (void) #endif } + if (aarch64_fix_a53_err843419 == 2) + { + aarch64_fix_a53_err843419 = 1; + } + aarch64_override_options_after_change (); if (TARGET_ANDROID) diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.md b/gcc-4.9/gcc/config/aarch64/aarch64.md index 05f5e1b35..dc88f8b10 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64.md +++ b/gcc-4.9/gcc/config/aarch64/aarch64.md @@ -163,13 +163,13 @@ (define_attr "generic_sched" "yes,no" (const (if_then_else - (eq_attr "tune" "cortexa53,cortexa15") + (eq_attr "tune" "cortexa53,cortexa57") (const_string "no") (const_string "yes")))) ;; Scheduling (include "../arm/cortex-a53.md") -(include "../arm/cortex-a15.md") +(include "../arm/cortex-a57.md") ;; ------------------------------------------------------------------- ;; Jumps and other miscellaneous insns @@ -3494,7 +3494,7 @@ (define_insn "aarch64_movtilow_tilow" [(set (match_operand:TI 0 "register_operand" "=w") - (zero_extend:TI + (zero_extend:TI (truncate:DI (match_operand:TI 1 "register_operand" "w"))))] "reload_completed || reload_in_progress" "fmov\\t%d0, %d1" diff --git a/gcc-4.9/gcc/config/aarch64/aarch64.opt b/gcc-4.9/gcc/config/aarch64/aarch64.opt index fc0307e28..ca27f50e1 100644 --- a/gcc-4.9/gcc/config/aarch64/aarch64.opt +++ b/gcc-4.9/gcc/config/aarch64/aarch64.opt @@ -71,6 +71,10 @@ mfix-cortex-a53-835769 Target Report Var(aarch64_fix_a53_err835769) Init(2) Workaround for ARM Cortex-A53 Erratum number 835769 +mfix-cortex-a53-843419 +Target Report Var(aarch64_fix_a53_err843419) Init(2) +Workaround for ARM Cortex-A53 Erratum number 843419 + mlittle-endian Target Report RejectNegative InverseMask(BIG_END) Assume target CPU is configured as little endian |