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Diffstat (limited to 'gcc-4.9/gcc/ChangeLog')
| -rw-r--r-- | gcc-4.9/gcc/ChangeLog | 412 |
1 files changed, 412 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/ChangeLog b/gcc-4.9/gcc/ChangeLog index df98072de..44fa3612c 100644 --- a/gcc-4.9/gcc/ChangeLog +++ b/gcc-4.9/gcc/ChangeLog @@ -1,3 +1,415 @@ +2014-08-26 Joel Sherrill <joel.sherrill@oarcorp.com> + + * doc/invoke.texi: -fno-cxa-atexit should be -fno-use-cxa-atexit. + +2014-08-26 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-08-26 Marek Polacek <polacek@redhat.com> + + PR c/61271 + * tree-vectorizer.h (LOOP_REQUIRES_VERSIONING_FOR_ALIGNMENT, + LOOP_REQUIRES_VERSIONING_FOR_ALIAS): Wrap in parens. + +2014-08-24 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-08-24 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/61996 + * config/sh/sh.opt (musermode): Allow negative form. + * config/sh/sh.c (sh_option_override): Disable TARGET_USERMODE for + targets that don't support it. + * doc/invoke.texi (SH Options): Rename sh-*-linux* to sh*-*-linux*. + Document -mno-usermode option. + +2014-08-23 John David Anglin <danglin@gcc.gnu.org> + + PR target/62038 + * config/pa/pa.c (pa_output_function_epilogue): Don't set + last_address when the current function is a thunk. + (pa_asm_output_mi_thunk): When we don't have named sections or they + are not being used, check that thunk can reach the stub table with a + short branch. + +2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport from mainline + 2014-08-22 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/62195 + * doc/md.texi (Machine Constraints): Update PowerPC wi constraint + documentation to state it is only for VSX operations. + + * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Make wi + constraint only active if VSX. + + * config/rs6000/rs6000.md (lfiwax): Use wj constraint instead of + wi cosntraint for ISA 2.07 lxsiwax/lxsiwzx instructions. + (lfiwzx): Likewise. + +2014-08-21 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2014-08-19 H.J. Lu <hongjiu.lu@intel.com> + + * config/i386/i386.md (*ctz<mode>2_falsedep_1): Don't clear + destination if it is used in source. + (*clz<mode>2_lzcnt_falsedep_1): Likewise. + (*popcount<mode>2_falsedep_1): Likewise. + + Backport from mainline + 2014-08-18 Uros Bizjak <ubizjak@gmail.com> + + PR target/62011 + * config/i386/x86-tune.def (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): + New tune flag. + * config/i386/i386.h (TARGET_AVOID_FALSE_DEP_FOR_BMI): New define. + * config/i386/i386.md (unspec) <UNSPEC_INSN_FALSE_DEP>: New unspec. + (ffs<mode>2): Do not expand with tzcnt for + TARGET_AVOID_FALSE_DEP_FOR_BMI. + (ffssi2_no_cmove): Ditto. + (*tzcnt<mode>_1): Disable for TARGET_AVOID_FALSE_DEP_FOR_BMI. + (ctz<mode>2): New expander. + (*ctz<mode>2_falsedep_1): New insn_and_split pattern. + (*ctz<mode>2_falsedep): New insn. + (*ctz<mode>2): Rename from ctz<mode>2. + (clz<mode>2_lzcnt): New expander. + (*clz<mode>2_lzcnt_falsedep_1): New insn_and_split pattern. + (*clz<mode>2_lzcnt_falsedep): New insn. + (*clz<mode>2): Rename from ctz<mode>2. + (popcount<mode>2): New expander. + (*popcount<mode>2_falsedep_1): New insn_and_split pattern. + (*popcount<mode>2_falsedep): New insn. + (*popcount<mode>2): Rename from ctz<mode>2. + (*popcount<mode>2_cmp): Remove. + (*popcountsi2_cmp_zext): Ditto. + +2014-08-20 Martin Jambor <mjambor@suse.cz> + Wei Mi <wmi@google.com> + + PR ipa/60449 + PR middle-end/61776 + * tree-ssa-operands.c (update_stmt_operands): Remove + MODIFIED_NORETURN_CALLS. + * tree-cfgcleanup.c (cleanup_call_ctrl_altering_flag): New func. + (cleanup_control_flow_bb): Use cleanup_call_ctrl_altering_flag. + (split_bb_on_noreturn_calls): Renamed from split_bbs_on_noreturn_calls. + (cleanup_tree_cfg_1): Use split_bb_on_noreturn_calls. + * tree-ssanames.h: Remove MODIFIED_NORETURN_CALLS. + * gimple.h (enum gf_mask): Add GF_CALL_CTRL_ALTERING. + (gimple_call_set_ctrl_altering): New func. + (gimple_call_ctrl_altering_p): Ditto. + * tree-cfg.c (gimple_call_initialize_ctrl_altering): Ditto. + (make_blocks): Use gimple_call_initialize_ctrl_altering. + (is_ctrl_altering_stmt): Use gimple_call_ctrl_altering_p. + (execute_fixup_cfg): Use gimple_call_ctrl_altering_p and + remove MODIFIED_NORETURN_CALLS. + +2014-08-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + Backport from mainline. + 2014-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + PR target/62098 + * config/arm/vfp.md (*combine_vcvtf2i): Fix constraint. + Remove unnecessary attributes. + +2014-08-16 John David Anglin <danglin@gcc.gnu.org> + + PR target/61641 + * config/pa/pa-protos.h (pa_output_addr_vec, pa_output_addr_diff_vec): + Declare. + * config/pa/pa.c (pa_reorg): Remove code to insert brtab marker insns. + (pa_output_addr_vec, pa_output_addr_diff_vec): New. + * config/pa/pa.h (ASM_OUTPUT_ADDR_VEC, ASM_OUTPUT_ADDR_DIFF_VEC): + Define. + * config/pa/pa.md (begin_brtab): Delete insn. + (end_brtab): Likewise. + +2014-08-15 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline: + 2014-08-15 Oleg Endo <olegendo@gcc.gnu.org> + + * doc/invoke.texi (SH options): Document missing processor variant + options. Remove references to Hitachi. Undocument deprecated mspace + option. + +2014-08-15 Tom de Vries <tom@codesourcery.com> + + Backport from mainline: + 2014-08-14 Tom de Vries <tom@codesourcery.com> + + PR rtl-optimization/62004 + PR rtl-optimization/62030 + * ifcvt.c (rtx_interchangeable_p): New function. + (noce_try_move, noce_process_if_block): Use rtx_interchangeable_p. + + 2014-08-05 Richard Biener <rguenther@suse.de> + + * emit-rtl.h (mem_attrs_eq_p): Declare. + * emit-rtl.c (mem_attrs_eq_p): Export. + +2014-08-15 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/62092 + * gimplify.c (gimplify_adjust_omp_clauses_1): Don't remove + OMP_CLAUSE_SHARED for global vars if the global var is mentioned + in OMP_CLAUSE_MAP in some outer target region. + +>>>>>>> .r214216 +2014-08-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + Backport from mainline + 2014-08-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/61713 + * gcc/optabs.c (expand_atomic_test_and_set): Do not try to emit + move to subtarget in serial version if result is ignored. + +2014-08-14 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2014-08-12 Thomas Preud'homme <thomas.preudhomme@arm.com> + + PR middle-end/62103 + * gimple-fold.c (fold_ctor_reference): Don't fold in presence of + bitfields, that is when size doesn't match the size of type or the + size of the constructor. + +2014-08-12 Felix Yang <fei.yang0953@gmail.com> + + PR tree-optimization/62073 + * tree-vect-loop.c (vect_is_simple_reduction_1): Check that DEF1 has + a basic block. + +2014-08-12 Jakub Jelinek <jakub@redhat.com> + + PR target/62025 + * sched-deps.c (find_inc): Check if inc_insn doesn't clobber + any registers that are used in mem_insn. + +2014-08-12 Michael Meissner <meissner@linux.vnet.ibm.com> + + Backport patch from mainline + 2014-08-11 Michael Meissner <meissner@linux.vnet.ibm.com> + + * config/rs6000/constraints.md (wh constraint): New constraint, + for FP registers if direct move is available. + (wi constraint): New constraint, for VSX/FP registers that can + handle 64-bit integers. + (wj constraint): New constraint for VSX/FP registers that can + handle 64-bit integers for direct moves. + (wk constraint): New constraint for VSX/FP registers that can + handle 64-bit doubles for direct moves. + (wy constraint): Make documentation match implementation. + + * config/rs6000/rs6000.c (struct rs6000_reg_addr): Add + scalar_in_vmx_p field to simplify tests of whether SFmode or + DFmode can go in the Altivec registers. + (rs6000_hard_regno_mode_ok): Use scalar_in_vmx_p field. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_debug_print_mode): Add debug support for scalar_in_vmx_p + field, and wh/wi/wj/wk constraints. + (rs6000_init_hard_regno_mode_ok): Setup scalar_in_vmx_p field, and + the wh/wi/wj/wk constraints. + (rs6000_preferred_reload_class): If SFmode/DFmode can go in the + upper registers, prefer VSX registers unless the operation is a + memory operation with REG+OFFSET addressing. + + * config/rs6000/vsx.md (VSr mode attribute): Add support for + DImode. Change SFmode to use ww constraint instead of d to allow + SF registers in the upper registers. + (VSr2): Likewise. + (VSr3): Likewise. + (VSr5): Fix thinko in comment. + (VSa): New mode attribute that is an alternative to wa, that + returns the VSX register class that a mode can go in, but may not + be the preferred register class. + (VS_64dm): New mode attribute for appropriate register classes for + referencing 64-bit elements of vectors for direct moves and normal + moves. + (VS_64reg): Likewise. + (vsx_mov<mode>): Change wa constraint to <VSa> to limit the + register allocator to only registers the data type can handle. + (vsx_le_perm_load_<mode>): Likewise. + (vsx_le_perm_store_<mode>): Likewise. + (vsx_xxpermdi2_le_<mode>): Likewise. + (vsx_xxpermdi4_le_<mode>): Likewise. + (vsx_lxvd2x2_le_<mode>): Likewise. + (vsx_lxvd2x4_le_<mode>): Likewise. + (vsx_stxvd2x2_le_<mode>): Likewise. + (vsx_add<mode>3): Likewise. + (vsx_sub<mode>3): Likewise. + (vsx_mul<mode>3): Likewise. + (vsx_div<mode>3): Likewise. + (vsx_tdiv<mode>3_internal): Likewise. + (vsx_fre<mode>2): Likewise. + (vsx_neg<mode>2): Likewise. + (vsx_abs<mode>2): Likewise. + (vsx_nabs<mode>2): Likewise. + (vsx_smax<mode>3): Likewise. + (vsx_smin<mode>3): Likewise. + (vsx_sqrt<mode>2): Likewise. + (vsx_rsqrte<mode>2): Likewise. + (vsx_tsqrt<mode>2_internal): Likewise. + (vsx_fms<mode>4): Likewise. + (vsx_nfma<mode>4): Likewise. + (vsx_eq<mode>): Likewise. + (vsx_gt<mode>): Likewise. + (vsx_ge<mode>): Likewise. + (vsx_eq<mode>_p): Likewise. + (vsx_gt<mode>_p): Likewise. + (vsx_ge<mode>_p): Likewise. + (vsx_xxsel<mode>): Likewise. + (vsx_xxsel<mode>_uns): Likewise. + (vsx_copysign<mode>3): Likewise. + (vsx_float<VSi><mode>2): Likewise. + (vsx_floatuns<VSi><mode>2): Likewise. + (vsx_fix_trunc<mode><VSi>2): Likewise. + (vsx_fixuns_trunc<mode><VSi>2): Likewise. + (vsx_x<VSv>r<VSs>i): Likewise. + (vsx_x<VSv>r<VSs>ic): Likewise. + (vsx_btrunc<mode>2): Likewise. + (vsx_b2trunc<mode>2): Likewise. + (vsx_floor<mode>2): Likewise. + (vsx_ceil<mode>2): Likewise. + (vsx_<VS_spdp_insn>): Likewise. + (vsx_xscvspdp): Likewise. + (vsx_xvcvspuxds): Likewise. + (vsx_float_fix_<mode>2): Likewise. + (vsx_set_<mode>): Likewise. + (vsx_extract_<mode>_internal1): Likewise. + (vsx_extract_<mode>_internal2): Likewise. + (vsx_extract_<mode>_load): Likewise. + (vsx_extract_<mode>_store): Likewise. + (vsx_splat_<mode>): Likewise. + (vsx_xxspltw_<mode>): Likewise. + (vsx_xxspltw_<mode>_direct): Likewise. + (vsx_xxmrghw_<mode>): Likewise. + (vsx_xxmrglw_<mode>): Likewise. + (vsx_xxsldwi_<mode>): Likewise. + (vsx_xscvdpspn): Tighten constraints to only use register classes + the types use. + (vsx_xscvspdpn): Likewise. + (vsx_xscvdpspn_scalar): Likewise. + + * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wh, wi, + wj, and wk constraints. + (GPR_REG_CLASS_P): New helper macro for register classes targeting + general purpose registers. + + * config/rs6000/rs6000.md (f32_dm): Use wh constraint for SDmode + direct moves. + (zero_extendsidi2_lfiwz): Use wj constraint for direct move of + DImode instead of wm. Use wk constraint for direct move of DFmode + instead of wm. + (extendsidi2_lfiwax): Likewise. + (lfiwax): Likewise. + (lfiwzx): Likewise. + (movdi_internal64): Likewise. + + * doc/md.texi (PowerPC and IBM RS6000): Document wh, wi, wj, and + wk constraints. Make the wy constraint documentation match them + implementation. + +2014-08-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> + + Backport from mainline + 2014-08-04 Ganesh Gopalasubramanian + <Ganesh.Gopalasubramanian@amd.com> + + * config/i386/i386.c (ix86_option_override_internal): Add + PTA_RDRND and PTA_MOVBE for bdver4. + +2014-08-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> + + Backport from mainline + 2014-08-04 Ganesh Gopalasubramanian + <Ganesh.Gopalasubramanian@amd.com> + + * config/i386/driver-i386.c (host_detect_local_cpu): Handle AMD's extended + family information. Handle BTVER2 cpu with cpuid family value. + +2014-08-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> + + Backport from mainline + 2014-06-16 Ganesh Gopalasubramanian + <Ganesh.Gopalasubramanian@amd.com> + + * config/i386/i386.c (ix86_expand_sse2_mulvxdi3): Issue + instructions "vpmuludq" and "vpaddq" instead of "vpmacsdql" for + handling 32-bit multiplication. + +2014-08-08 Guozhi Wei <carrot@google.com> + + * config/rs6000/rs6000.md (*movdi_internal64): Add a new constraint. + +2014-08-07 Ilya Tocar <ilya.tocar@intel.com> + + * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Fix + constraint. + +2014-08-06 Vladimir Makarov <vmakarov@redhat.com> + + PR debug/61923 + * haifa-sched.c (advance_one_cycle): Fix dump. + (schedule_block): Don't advance cycle if we are already at the + beginning of the cycle. + +2014-08-06 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61320 + * tree-ssa-loop-ivopts.c (may_be_unaligned_p): Properly + handle misaligned loads. + +2014-08-04 Rohit <rohitarulraj@freescale.com> + + PR target/60102 + * config/rs6000/rs6000.c + (rs6000_reg_names): Add SPE high register names. + (alt_reg_names): Likewise. + (rs6000_dwarf_register_span): For SPE high registers, replace + dwarf register numbers with GCC hard register numbers. + (rs6000_init_dwarf_reg_sizes_extra): Likewise. + (rs6000_dbx_register_number): For SPE high registers, return dwarf + register number for the corresponding GCC hard register number. + * config/rs6000/rs6000.h + (FIRST_PSEUDO_REGISTER): Update based on 32 newly added GCC hard + register numbers for SPE high registers. + (DWARF_FRAME_REGISTERS): Likewise. + (DWARF_REG_TO_UNWIND_COLUMN): Likewise. + (DWARF_FRAME_REGNUM): Likewise. + (FIXED_REGISTERS): Likewise. + (CALL_USED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Likewise. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (SPE_HIGH_REGNO_P): New macro to identify SPE high registers. + +2014-08-01 Vladimir Makarov <vmakarov@redhat.com> + + * lra-constraints.c (remove_inheritance_pseudos): Process + destination pseudo too. + +2014-08-01 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2014-06-13 Thomas Preud'homme <thomas.preudhomme@arm.com> + + PR tree-optimization/61375 + * tree-ssa-math-opts.c (find_bswap_or_nop_1): Cancel optimization if + symbolic number cannot be represented in an unsigned HOST_WIDE_INT. + (execute_optimize_bswap): Cancel optimization if CHAR_BIT != 8. + +2014-08-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61964 + * tree-ssa-tail-merge.c (gimple_equal_p): Handle non-SSA LHS solely + by structural equality. + 2014-07-31 Oleg Endo <olegendo@gcc.gnu.org> Backport from mainline |