diff options
Diffstat (limited to 'gcc-4.8/gcc/testsuite/gcc.target/powerpc')
79 files changed, 4681 insertions, 27 deletions
diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c index ee5c5eee9..c3cf67e44 100644 --- a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/altivec-perm-1.c @@ -19,19 +19,6 @@ V b4(V x) return __builtin_shuffle(x, (V){ 4,5,6,7, 4,5,6,7, 4,5,6,7, 4,5,6,7, }); } -V p2(V x, V y) -{ - return __builtin_shuffle(x, y, - (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 }); - -} - -V p4(V x, V y) -{ - return __builtin_shuffle(x, y, - (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 }); -} - V h1(V x, V y) { return __builtin_shuffle(x, y, @@ -72,5 +59,3 @@ V l4(V x, V y) /* { dg-final { scan-assembler "vspltb" } } */ /* { dg-final { scan-assembler "vsplth" } } */ /* { dg-final { scan-assembler "vspltw" } } */ -/* { dg-final { scan-assembler "vpkuhum" } } */ -/* { dg-final { scan-assembler "vpkuwum" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c new file mode 100644 index 000000000..d0b671eac --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ +/* { dg-options "-O -maltivec -mno-vsx" } */ + +typedef unsigned char V __attribute__((vector_size(16))); + +V p2(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 }); + +} + +V p4(V x, V y) +{ + return __builtin_shuffle(x, y, + (V){ 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 }); +} + +/* { dg-final { scan-assembler-not "vperm" } } */ +/* { dg-final { scan-assembler "vpkuhum" } } */ +/* { dg-final { scan-assembler "vpkuwum" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic-p7.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic-p7.c new file mode 100644 index 000000000..3442bfba4 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic-p7.c @@ -0,0 +1,207 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2" } */ +/* { dg-final { scan-assembler-not "lbarx" } } */ +/* { dg-final { scan-assembler-not "lharx" } } */ +/* { dg-final { scan-assembler-times "lwarx" 18 } } */ +/* { dg-final { scan-assembler-times "ldarx" 6 } } */ +/* { dg-final { scan-assembler-not "lqarx" } } */ +/* { dg-final { scan-assembler-not "stbcx" } } */ +/* { dg-final { scan-assembler-not "sthcx" } } */ +/* { dg-final { scan-assembler-times "stwcx" 18 } } */ +/* { dg-final { scan-assembler-times "stdcx" 6 } } */ +/* { dg-final { scan-assembler-not "stqcx" } } */ +/* { dg-final { scan-assembler-times "bl __atomic" 6 } } */ +/* { dg-final { scan-assembler-times "isync" 12 } } */ +/* { dg-final { scan-assembler-times "lwsync" 8 } } */ +/* { dg-final { scan-assembler-not "mtvsrd" } } */ +/* { dg-final { scan-assembler-not "mtvsrwa" } } */ +/* { dg-final { scan-assembler-not "mtvsrwz" } } */ +/* { dg-final { scan-assembler-not "mfvsrd" } } */ +/* { dg-final { scan-assembler-not "mfvsrwz" } } */ + +/* Test for the byte atomic operations on power8 using lbarx/stbcx. */ +char +char_fetch_add_relaxed (char *ptr, int value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +char +char_fetch_sub_consume (char *ptr, int value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +char +char_fetch_and_acquire (char *ptr, int value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +char +char_fetch_ior_release (char *ptr, int value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +char +char_fetch_xor_acq_rel (char *ptr, int value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +char +char_fetch_nand_seq_cst (char *ptr, int value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +/* Test for the half word atomic operations on power8 using lharx/sthcx. */ +short +short_fetch_add_relaxed (short *ptr, int value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +short +short_fetch_sub_consume (short *ptr, int value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +short +short_fetch_and_acquire (short *ptr, int value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +short +short_fetch_ior_release (short *ptr, int value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +short +short_fetch_xor_acq_rel (short *ptr, int value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +short +short_fetch_nand_seq_cst (short *ptr, int value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +/* Test for the word atomic operations on power8 using lwarx/stwcx. */ +int +int_fetch_add_relaxed (int *ptr, int value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +int +int_fetch_sub_consume (int *ptr, int value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +int +int_fetch_and_acquire (int *ptr, int value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +int +int_fetch_ior_release (int *ptr, int value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +int +int_fetch_xor_acq_rel (int *ptr, int value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +int +int_fetch_nand_seq_cst (int *ptr, int value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +/* Test for the double word atomic operations on power8 using ldarx/stdcx. */ +long +long_fetch_add_relaxed (long *ptr, long value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +long +long_fetch_sub_consume (long *ptr, long value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +long +long_fetch_and_acquire (long *ptr, long value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +long +long_fetch_ior_release (long *ptr, long value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +long +long_fetch_xor_acq_rel (long *ptr, long value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +long +long_fetch_nand_seq_cst (long *ptr, long value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */ +__int128_t +quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +__int128_t +quad_fetch_sub_consume (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +__int128_t +quad_fetch_and_acquire (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +__int128_t +quad_fetch_ior_release (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +__int128_t +quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +__int128_t +quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic-p8.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic-p8.c new file mode 100644 index 000000000..17460ac4c --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic-p8.c @@ -0,0 +1,237 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler-times "lbarx" 7 } } */ +/* { dg-final { scan-assembler-times "lharx" 7 } } */ +/* { dg-final { scan-assembler-times "lwarx" 7 } } */ +/* { dg-final { scan-assembler-times "ldarx" 7 } } */ +/* { dg-final { scan-assembler-times "lqarx" 7 } } */ +/* { dg-final { scan-assembler-times "stbcx" 7 } } */ +/* { dg-final { scan-assembler-times "sthcx" 7 } } */ +/* { dg-final { scan-assembler-times "stwcx" 7 } } */ +/* { dg-final { scan-assembler-times "stdcx" 7 } } */ +/* { dg-final { scan-assembler-times "stqcx" 7 } } */ +/* { dg-final { scan-assembler-not "bl __atomic" } } */ +/* { dg-final { scan-assembler-times "isync" 20 } } */ +/* { dg-final { scan-assembler-times "lwsync" 10 } } */ +/* { dg-final { scan-assembler-not "mtvsrd" } } */ +/* { dg-final { scan-assembler-not "mtvsrwa" } } */ +/* { dg-final { scan-assembler-not "mtvsrwz" } } */ +/* { dg-final { scan-assembler-not "mfvsrd" } } */ +/* { dg-final { scan-assembler-not "mfvsrwz" } } */ + +/* Test for the byte atomic operations on power8 using lbarx/stbcx. */ +char +char_fetch_add_relaxed (char *ptr, int value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +char +char_fetch_sub_consume (char *ptr, int value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +char +char_fetch_and_acquire (char *ptr, int value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +char +char_fetch_ior_release (char *ptr, int value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +char +char_fetch_xor_acq_rel (char *ptr, int value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +char +char_fetch_nand_seq_cst (char *ptr, int value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +void +char_val_compare_and_swap (char *p, int i, int j, char *q) +{ + *q = __sync_val_compare_and_swap (p, i, j); +} + +/* Test for the half word atomic operations on power8 using lharx/sthcx. */ +short +short_fetch_add_relaxed (short *ptr, int value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +short +short_fetch_sub_consume (short *ptr, int value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +short +short_fetch_and_acquire (short *ptr, int value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +short +short_fetch_ior_release (short *ptr, int value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +short +short_fetch_xor_acq_rel (short *ptr, int value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +short +short_fetch_nand_seq_cst (short *ptr, int value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +void +short_val_compare_and_swap (short *p, int i, int j, short *q) +{ + *q = __sync_val_compare_and_swap (p, i, j); +} + +/* Test for the word atomic operations on power8 using lwarx/stwcx. */ +int +int_fetch_add_relaxed (int *ptr, int value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +int +int_fetch_sub_consume (int *ptr, int value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +int +int_fetch_and_acquire (int *ptr, int value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +int +int_fetch_ior_release (int *ptr, int value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +int +int_fetch_xor_acq_rel (int *ptr, int value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +int +int_fetch_nand_seq_cst (int *ptr, int value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +void +int_val_compare_and_swap (int *p, int i, int j, int *q) +{ + *q = __sync_val_compare_and_swap (p, i, j); +} + +/* Test for the double word atomic operations on power8 using ldarx/stdcx. */ +long +long_fetch_add_relaxed (long *ptr, long value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +long +long_fetch_sub_consume (long *ptr, long value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +long +long_fetch_and_acquire (long *ptr, long value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +long +long_fetch_ior_release (long *ptr, long value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +long +long_fetch_xor_acq_rel (long *ptr, long value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +long +long_fetch_nand_seq_cst (long *ptr, long value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +void +long_val_compare_and_swap (long *p, long i, long j, long *q) +{ + *q = __sync_val_compare_and_swap (p, i, j); +} + +/* Test for the quad word atomic operations on power8 using ldarx/stdcx. */ +__int128_t +quad_fetch_add_relaxed (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_RELAXED); +} + +__int128_t +quad_fetch_sub_consume (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_sub (ptr, value, __ATOMIC_CONSUME); +} + +__int128_t +quad_fetch_and_acquire (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +__int128_t +quad_fetch_ior_release (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_RELEASE); +} + +__int128_t +quad_fetch_xor_acq_rel (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_xor (ptr, value, __ATOMIC_ACQ_REL); +} + +__int128_t +quad_fetch_nand_seq_cst (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_nand (ptr, value, __ATOMIC_SEQ_CST); +} + +void +quad_val_compare_and_swap (__int128_t *p, __int128_t i, __int128_t j, __int128_t *q) +{ + *q = __sync_val_compare_and_swap (p, i, j); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c new file mode 100644 index 000000000..8a5cbfaa3 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler-times "lq" 1 } } */ +/* { dg-final { scan-assembler-times "stq" 1 } } */ +/* { dg-final { scan-assembler-not "bl __atomic" } } */ +/* { dg-final { scan-assembler-not "lqarx" } } */ +/* { dg-final { scan-assembler-not "stqcx" } } */ + +__int128 +atomic_load_128_relaxed (__int128 *ptr) +{ + return __atomic_load_n (ptr, __ATOMIC_RELAXED); +} + +void +atomic_store_128_relaxed (__int128 *ptr, __int128 val) +{ + __atomic_store_n (ptr, val, __ATOMIC_RELAXED); +} + diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-1.c new file mode 100644 index 000000000..c7496c235 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2" } */ +/* { dg-final { scan-assembler-times "cdtbcd " 1 } } */ +/* { dg-final { scan-assembler-times "cbcdtd " 1 } } */ +/* { dg-final { scan-assembler-times "addg6s " 1 } } */ +/* { dg-final { scan-assembler-not "bl __builtin" } } */ + +unsigned int +to_bcd (unsigned int a) +{ + return __builtin_cdtbcd (a); +} + +unsigned int +from_bcd (unsigned int a) +{ + return __builtin_cbcdtd (a); +} + +unsigned int +bcd_arith (unsigned int a, unsigned int b) +{ + return __builtin_addg6s (a, b); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-2.c new file mode 100644 index 000000000..d330b7423 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-2.c @@ -0,0 +1,44 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler-times "bcdadd\[.\] " 2 } } */ +/* { dg-final { scan-assembler-times "bcdsub\[.\] " 2 } } */ +/* { dg-final { scan-assembler-not "bl __builtin" } } */ +/* { dg-final { scan-assembler-not "mtvsr" } } */ +/* { dg-final { scan-assembler-not "mfvsr" } } */ +/* { dg-final { scan-assembler-not "lvx" } } */ +/* { dg-final { scan-assembler-not "lxvw4x" } } */ +/* { dg-final { scan-assembler-not "lxvd2x" } } */ +/* { dg-final { scan-assembler-not "stvx" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ +/* { dg-final { scan-assembler-not "stxvd2x" } } */ + +typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; +typedef __int128_t scalar_128_t; +typedef unsigned long long scalar_64_t; + +vector_128_t +do_add_0 (vector_128_t a, vector_128_t b) +{ + return __builtin_bcdadd (a, b, 0); +} + +vector_128_t +do_add_1 (vector_128_t a, vector_128_t b) +{ + return __builtin_bcdadd (a, b, 1); +} + +vector_128_t +do_sub_0 (vector_128_t a, vector_128_t b) +{ + return __builtin_bcdsub (a, b, 0); +} + +vector_128_t +do_sub_1 (vector_128_t a, vector_128_t b) +{ + return __builtin_bcdsub (a, b, 1); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-3.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-3.c new file mode 100644 index 000000000..436cecf6f --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-3.c @@ -0,0 +1,103 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler-times "bcdadd\[.\] " 4 } } */ +/* { dg-final { scan-assembler-times "bcdsub\[.\] " 4 } } */ +/* { dg-final { scan-assembler-not "bl __builtin" } } */ +/* { dg-final { scan-assembler-not "mtvsr" } } */ +/* { dg-final { scan-assembler-not "mfvsr" } } */ +/* { dg-final { scan-assembler-not "lvx" } } */ +/* { dg-final { scan-assembler-not "lxvw4x" } } */ +/* { dg-final { scan-assembler-not "lxvd2x" } } */ +/* { dg-final { scan-assembler-not "stvx" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ +/* { dg-final { scan-assembler-not "stxvd2x" } } */ + +typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; +typedef __int128_t scalar_128_t; +typedef unsigned long long scalar_64_t; + +/* Test whether the peephole works to allow folding a bcdadd, with a + bcdadd_<test> into a single instruction. */ + +vector_128_t +do_add_lt (vector_128_t a, vector_128_t b, int *p) +{ + vector_128_t ret = __builtin_bcdadd (a, b, 0); + if (__builtin_bcdadd_lt (a, b, 0)) + *p = 1; + + return ret; +} + +vector_128_t +do_add_eq (vector_128_t a, vector_128_t b, int *p) +{ + vector_128_t ret = __builtin_bcdadd (a, b, 0); + if (__builtin_bcdadd_eq (a, b, 0)) + *p = 1; + + return ret; +} + +vector_128_t +do_add_gt (vector_128_t a, vector_128_t b, int *p) +{ + vector_128_t ret = __builtin_bcdadd (a, b, 0); + if (__builtin_bcdadd_gt (a, b, 0)) + *p = 1; + + return ret; +} + +vector_128_t +do_add_ov (vector_128_t a, vector_128_t b, int *p) +{ + vector_128_t ret = __builtin_bcdadd (a, b, 0); + if (__builtin_bcdadd_ov (a, b, 0)) + *p = 1; + + return ret; +} + +vector_128_t +do_sub_lt (vector_128_t a, vector_128_t b, int *p) +{ + vector_128_t ret = __builtin_bcdsub (a, b, 0); + if (__builtin_bcdsub_lt (a, b, 0)) + *p = 1; + + return ret; +} + +vector_128_t +do_sub_eq (vector_128_t a, vector_128_t b, int *p) +{ + vector_128_t ret = __builtin_bcdsub (a, b, 0); + if (__builtin_bcdsub_eq (a, b, 0)) + *p = 1; + + return ret; +} + +vector_128_t +do_sub_gt (vector_128_t a, vector_128_t b, int *p) +{ + vector_128_t ret = __builtin_bcdsub (a, b, 0); + if (__builtin_bcdsub_gt (a, b, 0)) + *p = 1; + + return ret; +} + +vector_128_t +do_sub_ov (vector_128_t a, vector_128_t b, int *p) +{ + vector_128_t ret = __builtin_bcdsub (a, b, 0); + if (__builtin_bcdsub_ov (a, b, 0)) + *p = 1; + + return ret; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool.c new file mode 100644 index 000000000..f007db4b5 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "eqv" } } */ +/* { dg-final { scan-assembler "nand" } } */ +/* { dg-final { scan-assembler "nor" } } */ + +#ifndef TYPE +#define TYPE unsigned long +#endif + +TYPE op1 (TYPE a, TYPE b) { return ~(a ^ b); } /* eqv */ +TYPE op2 (TYPE a, TYPE b) { return ~(a & b); } /* nand */ +TYPE op3 (TYPE a, TYPE b) { return ~(a | b); } /* nor */ + diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-av.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-av.c new file mode 100644 index 000000000..fc56ce261 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-av.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -mcpu=power6 -maltivec" } */ +/* { dg-final { scan-assembler-not "\[ \t\]and " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]or " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */ +/* { dg-final { scan-assembler "\[ \t\]vand " } } */ +/* { dg-final { scan-assembler "\[ \t\]vandc " } } */ +/* { dg-final { scan-assembler "\[ \t\]vor " } } */ +/* { dg-final { scan-assembler "\[ \t\]vxor " } } */ +/* { dg-final { scan-assembler "\[ \t\]vnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ + +#ifndef TYPE +typedef int v4si __attribute__ ((vector_size (16))); +#define TYPE v4si +#endif + +#include "bool2.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p5.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p5.c new file mode 100644 index 000000000..e4810d00d --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p5.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -mcpu=power5 -mabi=altivec -mno-altivec -mno-vsx" } */ +/* { dg-final { scan-assembler "\[ \t\]and " } } */ +/* { dg-final { scan-assembler "\[ \t\]or " } } */ +/* { dg-final { scan-assembler "\[ \t\]xor " } } */ +/* { dg-final { scan-assembler "\[ \t\]nor " } } */ +/* { dg-final { scan-assembler "\[ \t\]andc " } } */ +/* { dg-final { scan-assembler "\[ \t\]eqv " } } */ +/* { dg-final { scan-assembler "\[ \t\]orc " } } */ +/* { dg-final { scan-assembler "\[ \t\]nand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ + +#ifndef TYPE +typedef int v4si __attribute__ ((vector_size (16))); +#define TYPE v4si +#endif + +#include "bool2.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p7.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p7.c new file mode 100644 index 000000000..274fcb090 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p7.c @@ -0,0 +1,31 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler-not "\[ \t\]and " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]or " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxland " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ + +#ifndef TYPE +typedef int v4si __attribute__ ((vector_size (16))); +#define TYPE v4si +#endif + +#include "bool2.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p8.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p8.c new file mode 100644 index 000000000..34f4d2df8 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p8.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mcpu=power8" } */ +/* { dg-final { scan-assembler-not "\[ \t\]and " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]or " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]nor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]eqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]andc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]orc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]nand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxland " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlor " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlxor " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlnor " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlandc " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxleqv " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlorc " } } */ +/* { dg-final { scan-assembler "\[ \t\]xxlnand " } } */ + +#ifndef TYPE +typedef int v4si __attribute__ ((vector_size (16))); +#define TYPE v4si +#endif + +#include "bool2.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2.h b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2.h new file mode 100644 index 000000000..4513944c2 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2.h @@ -0,0 +1,29 @@ +/* Test various logical operations. */ + +TYPE arg1 (TYPE p, TYPE q) { return p & q; } /* AND */ +TYPE arg2 (TYPE p, TYPE q) { return p | q; } /* OR */ +TYPE arg3 (TYPE p, TYPE q) { return p ^ q; } /* XOR */ +TYPE arg4 (TYPE p) { return ~ p; } /* NOR */ +TYPE arg5 (TYPE p, TYPE q) { return ~(p & q); } /* NAND */ +TYPE arg6 (TYPE p, TYPE q) { return ~(p | q); } /* NOR */ +TYPE arg7 (TYPE p, TYPE q) { return ~(p ^ q); } /* EQV */ +TYPE arg8 (TYPE p, TYPE q) { return (~p) & q; } /* ANDC */ +TYPE arg9 (TYPE p, TYPE q) { return (~p) | q; } /* ORC */ +TYPE arg10(TYPE p, TYPE q) { return (~p) ^ q; } /* EQV */ +TYPE arg11(TYPE p, TYPE q) { return p & (~q); } /* ANDC */ +TYPE arg12(TYPE p, TYPE q) { return p | (~q); } /* ORC */ +TYPE arg13(TYPE p, TYPE q) { return p ^ (~q); } /* EQV */ + +void ptr1 (TYPE *p) { p[0] = p[1] & p[2]; } /* AND */ +void ptr2 (TYPE *p) { p[0] = p[1] | p[2]; } /* OR */ +void ptr3 (TYPE *p) { p[0] = p[1] ^ p[2]; } /* XOR */ +void ptr4 (TYPE *p) { p[0] = ~p[1]; } /* NOR */ +void ptr5 (TYPE *p) { p[0] = ~(p[1] & p[2]); } /* NAND */ +void ptr6 (TYPE *p) { p[0] = ~(p[1] | p[2]); } /* NOR */ +void ptr7 (TYPE *p) { p[0] = ~(p[1] ^ p[2]); } /* EQV */ +void ptr8 (TYPE *p) { p[0] = ~(p[1]) & p[2]; } /* ANDC */ +void ptr9 (TYPE *p) { p[0] = (~p[1]) | p[2]; } /* ORC */ +void ptr10(TYPE *p) { p[0] = (~p[1]) ^ p[2]; } /* EQV */ +void ptr11(TYPE *p) { p[0] = p[1] & (~p[2]); } /* ANDC */ +void ptr12(TYPE *p) { p[0] = p[1] | (~p[2]); } /* ORC */ +void ptr13(TYPE *p) { p[0] = p[1] ^ (~p[2]); } /* EQV */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c new file mode 100644 index 000000000..d4aac786b --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -mcpu=power6 -mabi=altivec -maltivec -mno-vsx" } */ +/* { dg-final { scan-assembler "\[ \t\]and " } } */ +/* { dg-final { scan-assembler "\[ \t\]or " } } */ +/* { dg-final { scan-assembler "\[ \t\]xor " } } */ +/* { dg-final { scan-assembler "\[ \t\]nor " } } */ +/* { dg-final { scan-assembler "\[ \t\]andc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ + +/* On altivec, for 128-bit types, ORC/ANDC/EQV might not show up, since the + vector unit doesn't support these, so the appropriate combine patterns may + not be generated. */ + +#ifndef TYPE +#ifdef _ARCH_PPC64 +#define TYPE __int128_t +#else +typedef int v4si __attribute__ ((vector_size (16))); +#define TYPE v4si +#endif +#endif + +#include "bool3.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-p7.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-p7.c new file mode 100644 index 000000000..34e3c9e79 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-p7.c @@ -0,0 +1,37 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "\[ \t\]and " } } */ +/* { dg-final { scan-assembler "\[ \t\]or " } } */ +/* { dg-final { scan-assembler "\[ \t\]xor " } } */ +/* { dg-final { scan-assembler "\[ \t\]nor " } } */ +/* { dg-final { scan-assembler "\[ \t\]andc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ + +/* On power7, for 128-bit types, ORC/ANDC/EQV might not show up, since the + vector unit doesn't support these, so the appropriate combine patterns may + not be generated. */ + +#ifndef TYPE +#ifdef _ARCH_PPC64 +#define TYPE __int128_t +#else +typedef int v4si __attribute__ ((vector_size (16))); +#define TYPE v4si +#endif +#endif + +#include "bool3.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-p8.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-p8.c new file mode 100644 index 000000000..e1b2dfa7e --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-p8.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mcpu=power8" } */ +/* { dg-final { scan-assembler "\[ \t\]and " } } */ +/* { dg-final { scan-assembler "\[ \t\]or " } } */ +/* { dg-final { scan-assembler "\[ \t\]xor " } } */ +/* { dg-final { scan-assembler "\[ \t\]nor " } } */ +/* { dg-final { scan-assembler "\[ \t\]andc " } } */ +/* { dg-final { scan-assembler "\[ \t\]eqv " } } */ +/* { dg-final { scan-assembler "\[ \t\]orc " } } */ +/* { dg-final { scan-assembler "\[ \t\]nand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vand " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */ +/* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */ + +#ifndef TYPE +#ifdef _ARCH_PPC64 +#define TYPE __int128_t +#else +typedef int v4si __attribute__ ((vector_size (16))); +#define TYPE v4si +#endif +#endif + +#include "bool3.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3.h b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3.h new file mode 100644 index 000000000..7b99a4a61 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3.h @@ -0,0 +1,186 @@ +/* Test forcing 128-bit logical types into GPR registers. */ + +#if defined(NO_ASM) +#define FORCE_REG1(X) +#define FORCE_REG2(X,Y) + +#else +#if defined(USE_ALTIVEC) +#define REG_CLASS "+v" +#define PRINT_REG1 "# altivec reg %0" +#define PRINT_REG2 "# altivec reg %0, %1" + +#elif defined(USE_FPR) +#define REG_CLASS "+d" +#define PRINT_REG1 "# fpr reg %0" +#define PRINT_REG2 "# fpr reg %0, %1" + +#elif defined(USE_VSX) +#define REG_CLASS "+wa" +#define PRINT_REG1 "# vsx reg %x0" +#define PRINT_REG2 "# vsx reg %x0, %x1" + +#else +#define REG_CLASS "+r" +#define PRINT_REG1 "# gpr reg %0" +#define PRINT_REG2 "# gpr reg %0, %1" +#endif + +#define FORCE_REG1(X) __asm__ (PRINT_REG1 : REG_CLASS (X)) +#define FORCE_REG2(X,Y) __asm__ (PRINT_REG2 : REG_CLASS (X), REG_CLASS (Y)) +#endif + +void ptr1 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = a & b; /* AND */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr2 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = a | b; /* OR */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr3 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = a ^ b; /* XOR */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr4 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b; + + FORCE_REG1 (a); + b = ~a; /* NOR */ + FORCE_REG1 (b); + p[0] = b; +} + +void ptr5 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = ~(a & b); /* NAND */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr6 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = ~(a | b); /* AND */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr7 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = ~(a ^ b); /* EQV */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr8 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = (~a) & b; /* ANDC */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr9 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = (~a) | b; /* ORC */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr10 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = (~a) ^ b; /* EQV */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr11 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = a & (~b); /* ANDC */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr12 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = a | (~b); /* ORC */ + FORCE_REG1 (c); + p[0] = c; +} + +void ptr13 (TYPE *p) +{ + TYPE a = p[1]; + TYPE b = p[2]; + TYPE c; + + FORCE_REG2 (a, b); + c = a ^ (~b); /* AND */ + FORCE_REG1 (c); + p[0] = c; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c new file mode 100644 index 000000000..87291954e --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c @@ -0,0 +1,130 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ + +typedef vector unsigned long long crypto_t; +typedef vector unsigned long long v2di_t; +typedef vector unsigned int v4si_t; +typedef vector unsigned short v8hi_t; +typedef vector unsigned char v16qi_t; + +crypto_t crpyto1 (crypto_t a) +{ + return __builtin_crypto_vsbox (a); +} + +crypto_t crypto2 (crypto_t a, crypto_t b) +{ + return __builtin_crypto_vcipher (a, b); +} + +crypto_t crypto3 (crypto_t a, crypto_t b) +{ + return __builtin_crypto_vcipherlast (a, b); +} + +crypto_t crypto4 (crypto_t a, crypto_t b) +{ + return __builtin_crypto_vncipher (a, b); +} + +crypto_t crypto5 (crypto_t a, crypto_t b) +{ + return __builtin_crypto_vncipherlast (a, b); +} + +v16qi_t crypto6a (v16qi_t a, v16qi_t b, v16qi_t c) +{ + return __builtin_crypto_vpermxor (a, b, c); +} + +v8hi_t crypto6b (v8hi_t a, v8hi_t b, v8hi_t c) +{ + return __builtin_crypto_vpermxor (a, b, c); +} + +v4si_t crypto6c (v4si_t a, v4si_t b, v4si_t c) +{ + return __builtin_crypto_vpermxor (a, b, c); +} + +v2di_t crypto6d (v2di_t a, v2di_t b, v2di_t c) +{ + return __builtin_crypto_vpermxor (a, b, c); +} + +v16qi_t crypto7a (v16qi_t a, v16qi_t b) +{ + return __builtin_crypto_vpmsumb (a, b); +} + +v16qi_t crypto7b (v16qi_t a, v16qi_t b) +{ + return __builtin_crypto_vpmsum (a, b); +} + +v8hi_t crypto7c (v8hi_t a, v8hi_t b) +{ + return __builtin_crypto_vpmsumh (a, b); +} + +v8hi_t crypto7d (v8hi_t a, v8hi_t b) +{ + return __builtin_crypto_vpmsum (a, b); +} + +v4si_t crypto7e (v4si_t a, v4si_t b) +{ + return __builtin_crypto_vpmsumw (a, b); +} + +v4si_t crypto7f (v4si_t a, v4si_t b) +{ + return __builtin_crypto_vpmsum (a, b); +} + +v2di_t crypto7g (v2di_t a, v2di_t b) +{ + return __builtin_crypto_vpmsumd (a, b); +} + +v2di_t crypto7h (v2di_t a, v2di_t b) +{ + return __builtin_crypto_vpmsum (a, b); +} + +v2di_t crypto8a (v2di_t a) +{ + return __builtin_crypto_vshasigmad (a, 0, 8); +} + +v2di_t crypto8b (v2di_t a) +{ + return __builtin_crypto_vshasigma (a, 0, 8); +} + +v4si_t crypto8c (v4si_t a) +{ + return __builtin_crypto_vshasigmaw (a, 1, 15); +} + +v4si_t crypto8d (v4si_t a) +{ + return __builtin_crypto_vshasigma (a, 1, 15); +} + +/* Note space is used after the instruction so that vcipherlast does not match + vcipher. */ +/* { dg-final { scan-assembler-times "vcipher " 1 } } */ +/* { dg-final { scan-assembler-times "vcipherlast " 1 } } */ +/* { dg-final { scan-assembler-times "vncipher " 1 } } */ +/* { dg-final { scan-assembler-times "vncipherlast " 1 } } */ +/* { dg-final { scan-assembler-times "vpermxor " 4 } } */ +/* { dg-final { scan-assembler-times "vpmsumb " 2 } } */ +/* { dg-final { scan-assembler-times "vpmsumd " 2 } } */ +/* { dg-final { scan-assembler-times "vpmsumh " 2 } } */ +/* { dg-final { scan-assembler-times "vpmsumw " 2 } } */ +/* { dg-final { scan-assembler-times "vsbox " 1 } } */ +/* { dg-final { scan-assembler-times "vshasigmad " 2 } } */ +/* { dg-final { scan-assembler-times "vshasigmaw " 2 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c index 0692b3d80..14b56d082 100644 --- a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/darwin-longlong.c @@ -11,7 +11,11 @@ int msw(long long in) int i[2]; } ud; ud.ll = in; +#ifdef __LITTLE_ENDIAN__ + return ud.i[1]; +#else return ud.i[0]; +#endif } int main() diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c new file mode 100644 index 000000000..614f27264 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c @@ -0,0 +1,88 @@ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2" } */ +/* { dg-final { scan-assembler-times "ddedpd " 4 } } */ +/* { dg-final { scan-assembler-times "denbcd " 2 } } */ +/* { dg-final { scan-assembler-times "dxex " 1 } } */ +/* { dg-final { scan-assembler-times "diex " 1 } } */ +/* { dg-final { scan-assembler-times "dscli " 2 } } */ +/* { dg-final { scan-assembler-times "dscri " 2 } } */ +/* { dg-final { scan-assembler-not "bl __builtin" } } */ +/* { dg-final { scan-assembler-not "dctqpq" } } */ +/* { dg-final { scan-assembler-not "drdpq" } } */ +/* { dg-final { scan-assembler-not "stfd" } } */ +/* { dg-final { scan-assembler-not "lfd" } } */ + +_Decimal64 +do_dedpd_0 (_Decimal64 a) +{ + return __builtin_ddedpd (0, a); +} + +_Decimal64 +do_dedpd_1 (_Decimal64 a) +{ + return __builtin_ddedpd (1, a); +} + +_Decimal64 +do_dedpd_2 (_Decimal64 a) +{ + return __builtin_ddedpd (2, a); +} + +_Decimal64 +do_dedpd_3 (_Decimal64 a) +{ + return __builtin_ddedpd (3, a); +} + +_Decimal64 +do_enbcd_0 (_Decimal64 a) +{ + return __builtin_denbcd (0, a); +} + +_Decimal64 +do_enbcd_1 (_Decimal64 a) +{ + return __builtin_denbcd (1, a); +} + +_Decimal64 +do_xex (_Decimal64 a) +{ + return __builtin_dxex (a); +} + +_Decimal64 +do_iex (_Decimal64 a, _Decimal64 b) +{ + return __builtin_diex (a, b); +} + +_Decimal64 +do_scli_1 (_Decimal64 a) +{ + return __builtin_dscli (a, 1); +} + +_Decimal64 +do_scli_10 (_Decimal64 a) +{ + return __builtin_dscli (a, 10); +} + +_Decimal64 +do_scri_1 (_Decimal64 a) +{ + return __builtin_dscri (a, 1); +} + +_Decimal64 +do_scri_10 (_Decimal64 a) +{ + return __builtin_dscri (a, 10); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c new file mode 100644 index 000000000..189bc9ad6 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c @@ -0,0 +1,88 @@ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2" } */ +/* { dg-final { scan-assembler-times "ddedpdq " 4 } } */ +/* { dg-final { scan-assembler-times "denbcdq " 2 } } */ +/* { dg-final { scan-assembler-times "dxexq " 1 } } */ +/* { dg-final { scan-assembler-times "diexq " 1 } } */ +/* { dg-final { scan-assembler-times "dscliq " 2 } } */ +/* { dg-final { scan-assembler-times "dscriq " 2 } } */ +/* { dg-final { scan-assembler-not "bl __builtin" } } */ +/* { dg-final { scan-assembler-not "dctqpq" } } */ +/* { dg-final { scan-assembler-not "drdpq" } } */ +/* { dg-final { scan-assembler-not "stfd" } } */ +/* { dg-final { scan-assembler-not "lfd" } } */ + +_Decimal128 +do_dedpdq_0 (_Decimal128 a) +{ + return __builtin_ddedpdq (0, a); +} + +_Decimal128 +do_dedpdq_1 (_Decimal128 a) +{ + return __builtin_ddedpdq (1, a); +} + +_Decimal128 +do_dedpdq_2 (_Decimal128 a) +{ + return __builtin_ddedpdq (2, a); +} + +_Decimal128 +do_dedpdq_3 (_Decimal128 a) +{ + return __builtin_ddedpdq (3, a); +} + +_Decimal128 +do_enbcdq_0 (_Decimal128 a) +{ + return __builtin_denbcdq (0, a); +} + +_Decimal128 +do_enbcdq_1 (_Decimal128 a) +{ + return __builtin_denbcdq (1, a); +} + +_Decimal128 +do_xexq (_Decimal128 a) +{ + return __builtin_dxexq (a); +} + +_Decimal128 +do_iexq (_Decimal128 a, _Decimal128 b) +{ + return __builtin_diexq (a, b); +} + +_Decimal128 +do_scliq_1 (_Decimal128 a) +{ + return __builtin_dscliq (a, 1); +} + +_Decimal128 +do_scliq_10 (_Decimal128 a) +{ + return __builtin_dscliq (a, 10); +} + +_Decimal128 +do_scriq_1 (_Decimal128 a) +{ + return __builtin_dscriq (a, 1); +} + +_Decimal128 +do_scriq_10 (_Decimal128 a) +{ + return __builtin_dscriq (a, 10); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c new file mode 100644 index 000000000..fcb72bdff --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c @@ -0,0 +1,26 @@ +/* Test generation of DFP instructions for POWER6. */ +/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */ + +/* { dg-final { scan-assembler-times "fneg" 1 } } */ +/* { dg-final { scan-assembler-times "fabs" 1 } } */ +/* { dg-final { scan-assembler-times "fnabs" 1 } } */ +/* { dg-final { scan-assembler-times "fmr" 0 } } */ + +_Decimal64 +func1 (_Decimal64 a, _Decimal64 b) +{ + return -b; +} + +_Decimal64 +func2 (_Decimal64 a, _Decimal64 b) +{ + return __builtin_fabsd64 (b); +} + +_Decimal64 +func3 (_Decimal64 a, _Decimal64 b) +{ + return - __builtin_fabsd64 (b); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c new file mode 100644 index 000000000..a078cc469 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c @@ -0,0 +1,29 @@ +/* Test generation of DFP instructions for POWER6. */ +/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */ + +/* { dg-final { scan-assembler-times "fneg" 1 } } */ +/* { dg-final { scan-assembler-times "fabs" 1 } } */ +/* { dg-final { scan-assembler-times "fnabs" 1 } } */ +/* { dg-final { scan-assembler-times "fmr" 0 } } */ + +/* These tests verify we only generate fneg, fabs and fnabs + instructions and no fmr's since these are done in place. */ + +_Decimal128 +func1 (_Decimal128 a) +{ + return -a; +} + +_Decimal128 +func2 (_Decimal128 a) +{ + return __builtin_fabsd128 (a); +} + +_Decimal128 +func3 (_Decimal128 a) +{ + return - __builtin_fabsd128 (a); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c new file mode 100644 index 000000000..e825e5cad --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c @@ -0,0 +1,29 @@ +/* Test generation of DFP instructions for POWER6. */ +/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-std=gnu99 -O1 -mcpu=power6" } */ + +/* { dg-final { scan-assembler-times "fneg" 1 } } */ +/* { dg-final { scan-assembler-times "fabs" 1 } } */ +/* { dg-final { scan-assembler-times "fnabs" 1 } } */ +/* { dg-final { scan-assembler-times "fmr" 3 } } */ + +/* These tests verify we generate fneg, fabs and fnabs and + associated fmr's since these are not done in place. */ + +_Decimal128 +func1 (_Decimal128 a, _Decimal128 b) +{ + return -b; +} + +_Decimal128 +func2 (_Decimal128 a, _Decimal128 b) +{ + return __builtin_fabsd128 (b); +} + +_Decimal128 +func3 (_Decimal128 a, _Decimal128 b) +{ + return - __builtin_fabsd128 (b); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c new file mode 100644 index 000000000..2569ac843 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler "mtvsrd" } } */ +/* { dg-final { scan-assembler "mfvsrd" } } */ + +/* Check code generation for direct move for double types. */ + +#define TYPE double +#define IS_FLOAT 1 +#define NO_ALTIVEC 1 +#define VSX_REG_ATTR "ws" + +#include "direct-move.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c new file mode 100644 index 000000000..c8702204b --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +/* Check whether we get the right bits for direct move at runtime. */ + +#define TYPE double +#define IS_FLOAT 1 +#define NO_ALTIVEC 1 +#define DO_MAIN +#define VSX_REG_ATTR "ws" + +#include "direct-move.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c new file mode 100644 index 000000000..524c0eead --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler "mtvsrd" } } */ +/* { dg-final { scan-assembler "mfvsrd" } } */ +/* { dg-final { scan-assembler "xscvdpspn" } } */ +/* { dg-final { scan-assembler "xscvspdpn" } } */ + +/* Check code generation for direct move for float types. */ + +#define TYPE float +#define IS_FLOAT 1 +#define NO_ALTIVEC 1 +#define VSX_REG_ATTR "ww" + +#include "direct-move.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c new file mode 100644 index 000000000..352e76166 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +/* Check whether we get the right bits for direct move at runtime. */ + +#define TYPE float +#define IS_FLOAT 1 +#define NO_ALTIVEC 1 +#define DO_MAIN +#define VSX_REG_ATTR "ww" + +#include "direct-move.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c new file mode 100644 index 000000000..0a78f9cb2 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler "mtvsrd" } } */ +/* { dg-final { scan-assembler "mfvsrd" } } */ + +/* Check code generation for direct move for long types. */ + +#define TYPE long +#define IS_INT 1 +#define NO_ALTIVEC 1 +#define VSX_REG_ATTR "d" + +#include "direct-move.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c new file mode 100644 index 000000000..cee9e0e0f --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +/* Check whether we get the right bits for direct move at runtime. */ + +#define TYPE long +#define IS_INT 1 +#define NO_ALTIVEC 1 +#define DO_MAIN +#define VSX_REG_ATTR "d" + +#include "direct-move.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c new file mode 100644 index 000000000..3067b9a8e --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ +/* { dg-final { scan-assembler "mtvsrd" } } */ +/* { dg-final { scan-assembler "mfvsrd" } } */ + +/* Check code generation for direct move for vector types. */ + +#define TYPE vector int +#define VSX_REG_ATTR "wa" + +#include "direct-move.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c new file mode 100644 index 000000000..0d8264faf --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c @@ -0,0 +1,13 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +/* Check whether we get the right bits for direct move at runtime. */ + +#define TYPE vector int +#define DO_MAIN +#define VSX_REG_ATTR "wa" + +#include "direct-move.h" diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move.h b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move.h new file mode 100644 index 000000000..6a5b7ba18 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move.h @@ -0,0 +1,188 @@ +/* Test functions for direct move support. */ + +#include <math.h> +extern void abort (void); + +#ifndef VSX_REG_ATTR +#define VSX_REG_ATTR "wa" +#endif + +void __attribute__((__noinline__)) +copy (TYPE *a, TYPE *b) +{ + *b = *a; +} + +#ifndef NO_GPR +void __attribute__((__noinline__)) +load_gpr (TYPE *a, TYPE *b) +{ + TYPE c = *a; + __asm__ ("# gpr, reg = %0" : "+b" (c)); + *b = c; +} +#endif + +#ifndef NO_FPR +void __attribute__((__noinline__)) +load_fpr (TYPE *a, TYPE *b) +{ + TYPE c = *a; + __asm__ ("# fpr, reg = %0" : "+d" (c)); + *b = c; +} +#endif + +#ifndef NO_ALTIVEC +void __attribute__((__noinline__)) +load_altivec (TYPE *a, TYPE *b) +{ + TYPE c = *a; + __asm__ ("# altivec, reg = %0" : "+v" (c)); + *b = c; +} +#endif + +#ifndef NO_VSX +void __attribute__((__noinline__)) +load_vsx (TYPE *a, TYPE *b) +{ + TYPE c = *a; + __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c)); + *b = c; +} +#endif + +#ifndef NO_GPR_TO_VSX +void __attribute__((__noinline__)) +load_gpr_to_vsx (TYPE *a, TYPE *b) +{ + TYPE c = *a; + TYPE d; + __asm__ ("# gpr, reg = %0" : "+b" (c)); + d = c; + __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (d)); + *b = d; +} +#endif + +#ifndef NO_VSX_TO_GPR +void __attribute__((__noinline__)) +load_vsx_to_gpr (TYPE *a, TYPE *b) +{ + TYPE c = *a; + TYPE d; + __asm__ ("# vsx, reg = %x0" : "+" VSX_REG_ATTR (c)); + d = c; + __asm__ ("# gpr, reg = %0" : "+b" (d)); + *b = d; +} +#endif + +#ifdef DO_MAIN +typedef void (fn_type (TYPE *, TYPE *)); + +struct test_struct { + fn_type *func; + const char *name; +}; + +const struct test_struct test_functions[] = { + { copy, "copy" }, +#ifndef NO_GPR + { load_gpr, "load_gpr" }, +#endif +#ifndef NO_FPR + { load_fpr, "load_fpr" }, +#endif +#ifndef NO_ALTIVEC + { load_altivec, "load_altivec" }, +#endif +#ifndef NO_VSX + { load_vsx, "load_vsx" }, +#endif +#ifndef NO_GPR_TO_VSX + { load_gpr_to_vsx, "load_gpr_to_vsx" }, +#endif +#ifndef NO_VSX_TO_GPR + { load_vsx_to_gpr, "load_vsx_to_gpr" }, +#endif +}; + +/* Test a given value for each of the functions. */ +void __attribute__((__noinline__)) +test_value (TYPE a) +{ + long i; + + for (i = 0; i < sizeof (test_functions) / sizeof (test_functions[0]); i++) + { + TYPE b; + + test_functions[i].func (&a, &b); + if (memcmp ((void *)&a, (void *)&b, sizeof (TYPE)) != 0) + abort (); + } +} + +/* Main program. */ +int +main (void) +{ + long i,j; + union { + TYPE value; + unsigned char bytes[sizeof (TYPE)]; + } u; + +#if IS_INT + TYPE value = (TYPE)-5; + for (i = 0; i < 12; i++) + { + test_value (value); + value++; + } + + for (i = 0; i < 8*sizeof (TYPE); i++) + test_value (((TYPE)1) << i); + +#elif IS_UNS + TYPE value = (TYPE)0; + for (i = 0; i < 10; i++) + { + test_value (value); + test_value (~ value); + value++; + } + + for (i = 0; i < 8*sizeof (TYPE); i++) + test_value (((TYPE)1) << i); + +#elif IS_FLOAT + TYPE value = (TYPE)-5; + for (i = 0; i < 12; i++) + { + test_value (value); + value++; + } + + test_value ((TYPE)3.1415926535); + test_value ((TYPE)1.23456); + test_value ((TYPE)(-0.0)); + test_value ((TYPE)NAN); + test_value ((TYPE)+INFINITY); + test_value ((TYPE)-INFINITY); +#else + + for (j = 0; j < 10; j++) + { + for (i = 0; i < sizeof (TYPE); i++) + u.bytes[i] = (unsigned char) (random () >> 4); + + test_value (u.value); + } +#endif + + return 0; +} +#endif diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c new file mode 100644 index 000000000..5f948b721 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2" } */ +/* { dg-final { scan-assembler-times "divwe " 1 } } */ +/* { dg-final { scan-assembler-times "divweo " 1 } } */ +/* { dg-final { scan-assembler-times "divweu " 1 } } */ +/* { dg-final { scan-assembler-times "divweuo " 1 } } */ +/* { dg-final { scan-assembler-not "bl __builtin" } } */ + +int +div_we (int a, int b) +{ + return __builtin_divwe (a, b); +} + +int +div_weo (int a, int b) +{ + return __builtin_divweo (a, b); +} + +unsigned int +div_weu (unsigned int a, unsigned int b) +{ + return __builtin_divweu (a, b); +} + +unsigned int +div_weuo (unsigned int a, unsigned int b) +{ + return __builtin_divweuo (a, b); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c new file mode 100644 index 000000000..8ee6c8cf7 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2" } */ +/* { dg-final { scan-assembler-times "divde " 1 } } */ +/* { dg-final { scan-assembler-times "divdeo " 1 } } */ +/* { dg-final { scan-assembler-times "divdeu " 1 } } */ +/* { dg-final { scan-assembler-times "divdeuo " 1 } } */ +/* { dg-final { scan-assembler-not "bl __builtin" } } */ + +long +div_de (long a, long b) +{ + return __builtin_divde (a, b); +} + +long +div_deo (long a, long b) +{ + return __builtin_divdeo (a, b); +} + +unsigned long +div_deu (unsigned long a, unsigned long b) +{ + return __builtin_divdeu (a, b); +} + +unsigned long +div_deuo (unsigned long a, unsigned long b) +{ + return __builtin_divdeuo (a, b); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/fusion.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/fusion.c new file mode 100644 index 000000000..60e635972 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/fusion.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*le-*-* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power7 -mtune=power8 -O3" } */ + +#define LARGE 0x12345 + +int fusion_uchar (unsigned char *p){ return p[LARGE]; } +int fusion_schar (signed char *p){ return p[LARGE]; } +int fusion_ushort (unsigned short *p){ return p[LARGE]; } +int fusion_short (short *p){ return p[LARGE]; } +int fusion_int (int *p){ return p[LARGE]; } +unsigned fusion_uns (unsigned *p){ return p[LARGE]; } + +vector double fusion_vector (vector double *p) { return p[2]; } + +/* { dg-final { scan-assembler-times "gpr load fusion" 6 } } */ +/* { dg-final { scan-assembler-times "vector load fusion" 1 } } */ +/* { dg-final { scan-assembler-times "lbz" 2 } } */ +/* { dg-final { scan-assembler-times "extsb" 1 } } */ +/* { dg-final { scan-assembler-times "lhz" 2 } } */ +/* { dg-final { scan-assembler-times "extsh" 1 } } */ +/* { dg-final { scan-assembler-times "lwz" 2 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c new file mode 100644 index 000000000..e58816a7f --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c @@ -0,0 +1,51 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_htm_ok } */ +/* { dg-options "-O2 -mhtm" } */ + +/* { dg-final { scan-assembler-times "tbegin\\." 1 } } */ +/* { dg-final { scan-assembler-times "tend\\." 2 } } */ +/* { dg-final { scan-assembler-times "tabort\\." 2 } } */ +/* { dg-final { scan-assembler-times "tabortdc\\." 1 } } */ +/* { dg-final { scan-assembler-times "tabortdci\\." 1 } } */ +/* { dg-final { scan-assembler-times "tabortwc\\." 1 } } */ +/* { dg-final { scan-assembler-times "tabortwci\\." 2 } } */ +/* { dg-final { scan-assembler-times "tcheck\\." 1 } } */ +/* { dg-final { scan-assembler-times "trechkpt\\." 1 } } */ +/* { dg-final { scan-assembler-times "treclaim\\." 1 } } */ +/* { dg-final { scan-assembler-times "tsr\\." 3 } } */ +/* { dg-final { scan-assembler-times "mfspr" 4 } } */ +/* { dg-final { scan-assembler-times "mtspr" 4 } } */ + +void use_builtins (long *p, char code, long *a, long *b) +{ + p[0] = __builtin_tbegin (0); + p[1] = __builtin_tend (0); + p[2] = __builtin_tendall (); + p[3] = __builtin_tabort (0); + p[4] = __builtin_tabort (code); + + p[5] = __builtin_tabortdc (0xf, a[5], b[5]); + p[6] = __builtin_tabortdci (0xf, a[6], 13); + p[7] = __builtin_tabortwc (0xf, a[7], b[7]); + p[8] = __builtin_tabortwci (0xf, a[8], 13); + + p[9] = __builtin_tcheck (5); + p[10] = __builtin_trechkpt (); + p[11] = __builtin_treclaim (0); + p[12] = __builtin_tresume (); + p[13] = __builtin_tsuspend (); + p[14] = __builtin_tsr (0); + p[15] = __builtin_ttest (); /* This expands to a tabortwci. */ + + + p[16] = __builtin_get_texasr (); + p[17] = __builtin_get_texasru (); + p[18] = __builtin_get_tfhar (); + p[19] = __builtin_get_tfiar (); + + __builtin_set_texasr (a[20]); + __builtin_set_texasru (a[21]); + __builtin_set_tfhar (a[22]); + __builtin_set_tfiar (a[23]); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c new file mode 100644 index 000000000..5e92814b7 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c @@ -0,0 +1,32 @@ +/* This checks the availability of the XL compiler intrinsics for + transactional execution with the expected prototypes. */ + +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_htm_ok } */ +/* { dg-options "-O2 -mhtm" } */ + +#include <htmxlintrin.h> + +void +foo (void *TM_buff, long *result, unsigned char *code) +{ + *result++ = __TM_simple_begin (); + *result++ = __TM_begin (TM_buff); + *result++ = __TM_end (); + __TM_abort (); + __TM_named_abort (*code); + __TM_resume (); + __TM_suspend (); + *result++ = __TM_is_user_abort (TM_buff); + *result++ = __TM_is_named_user_abort (TM_buff, code); + *result++ = __TM_is_illegal (TM_buff); + *result++ = __TM_is_footprint_exceeded (TM_buff); + *result++ = __TM_nesting_depth (TM_buff); + *result++ = __TM_is_nested_too_deep (TM_buff); + *result++ = __TM_is_conflict (TM_buff); + *result++ = __TM_is_failure_persistent (TM_buff); + *result++ = __TM_failure_address (TM_buff); + *result++ = __TM_failure_code (TM_buff); +} + diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c new file mode 100644 index 000000000..7f2d3d3ef --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power6x -mmfpgpr" } */ +/* { dg-final { scan-assembler "mffgpr" } } */ +/* { dg-final { scan-assembler "mftgpr" } } */ + +/* Test that we generate the instructions to move between the GPR and FPR + registers under power6x. */ + +extern long return_long (void); +extern double return_double (void); + +double return_double2 (void) +{ + return (double) return_long (); +} + +long return_long2 (void) +{ + return (long) return_double (); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c new file mode 100644 index 000000000..6fd3acc2a --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c @@ -0,0 +1,65 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ + +#ifndef TYPE +#define TYPE long long +#endif + +#ifndef SIGN_TYPE +#define SIGN_TYPE signed TYPE +#endif + +#ifndef UNS_TYPE +#define UNS_TYPE unsigned TYPE +#endif + +typedef vector SIGN_TYPE v_sign; +typedef vector UNS_TYPE v_uns; + +v_sign sign_add (v_sign a, v_sign b) +{ + return a + b; +} + +v_sign sign_sub (v_sign a, v_sign b) +{ + return a - b; +} + +v_sign sign_shift_left (v_sign a, v_sign b) +{ + return a << b; +} + +v_sign sign_shift_right (v_sign a, v_sign b) +{ + return a >> b; +} + +v_uns uns_add (v_uns a, v_uns b) +{ + return a + b; +} + +v_uns uns_sub (v_uns a, v_uns b) +{ + return a - b; +} + +v_uns uns_shift_left (v_uns a, v_uns b) +{ + return a << b; +} + +v_uns uns_shift_right (v_uns a, v_uns b) +{ + return a >> b; +} + +/* { dg-final { scan-assembler-times "vaddudm" 2 } } */ +/* { dg-final { scan-assembler-times "vsubudm" 2 } } */ +/* { dg-final { scan-assembler-times "vsld" 2 } } */ +/* { dg-final { scan-assembler-times "vsrad" 1 } } */ +/* { dg-final { scan-assembler-times "vsrd" 1 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c new file mode 100644 index 000000000..412040bfa --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c @@ -0,0 +1,204 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ + +#include <altivec.h> + +typedef vector long long v_sign; +typedef vector unsigned long long v_uns; +typedef vector bool long long v_bool; + +v_sign sign_add_1 (v_sign a, v_sign b) +{ + return __builtin_altivec_vaddudm (a, b); +} + +v_sign sign_add_2 (v_sign a, v_sign b) +{ + return vec_add (a, b); +} + +v_sign sign_add_3 (v_sign a, v_sign b) +{ + return vec_vaddudm (a, b); +} + +v_sign sign_sub_1 (v_sign a, v_sign b) +{ + return __builtin_altivec_vsubudm (a, b); +} + +v_sign sign_sub_2 (v_sign a, v_sign b) +{ + return vec_sub (a, b); +} + + +v_sign sign_sub_3 (v_sign a, v_sign b) +{ + return vec_vsubudm (a, b); +} + +v_sign sign_min_1 (v_sign a, v_sign b) +{ + return __builtin_altivec_vminsd (a, b); +} + +v_sign sign_min_2 (v_sign a, v_sign b) +{ + return vec_min (a, b); +} + +v_sign sign_min_3 (v_sign a, v_sign b) +{ + return vec_vminsd (a, b); +} + +v_sign sign_max_1 (v_sign a, v_sign b) +{ + return __builtin_altivec_vmaxsd (a, b); +} + +v_sign sign_max_2 (v_sign a, v_sign b) +{ + return vec_max (a, b); +} + +v_sign sign_max_3 (v_sign a, v_sign b) +{ + return vec_vmaxsd (a, b); +} + +v_sign sign_abs (v_sign a) +{ + return vec_abs (a); /* xor, vsubudm, vmaxsd. */ +} + +v_bool sign_eq (v_sign a, v_sign b) +{ + return vec_cmpeq (a, b); +} + +v_bool sign_lt (v_sign a, v_sign b) +{ + return vec_cmplt (a, b); +} + +v_uns uns_add_2 (v_uns a, v_uns b) +{ + return vec_add (a, b); +} + +v_uns uns_add_3 (v_uns a, v_uns b) +{ + return vec_vaddudm (a, b); +} + +v_uns uns_sub_2 (v_uns a, v_uns b) +{ + return vec_sub (a, b); +} + +v_uns uns_sub_3 (v_uns a, v_uns b) +{ + return vec_vsubudm (a, b); +} + +v_uns uns_min_2 (v_uns a, v_uns b) +{ + return vec_min (a, b); +} + +v_uns uns_min_3 (v_uns a, v_uns b) +{ + return vec_vminud (a, b); +} + +v_uns uns_max_2 (v_uns a, v_uns b) +{ + return vec_max (a, b); +} + +v_uns uns_max_3 (v_uns a, v_uns b) +{ + return vec_vmaxud (a, b); +} + +v_bool uns_eq (v_uns a, v_uns b) +{ + return vec_cmpeq (a, b); +} + +v_bool uns_lt (v_uns a, v_uns b) +{ + return vec_cmplt (a, b); +} + +v_sign sign_rl_1 (v_sign a, v_sign b) +{ + return __builtin_altivec_vrld (a, b); +} + +v_sign sign_rl_2 (v_sign a, v_uns b) +{ + return vec_rl (a, b); +} + +v_uns uns_rl_2 (v_uns a, v_uns b) +{ + return vec_rl (a, b); +} + +v_sign sign_sl_1 (v_sign a, v_sign b) +{ + return __builtin_altivec_vsld (a, b); +} + +v_sign sign_sl_2 (v_sign a, v_uns b) +{ + return vec_sl (a, b); +} + +v_sign sign_sl_3 (v_sign a, v_uns b) +{ + return vec_vsld (a, b); +} + +v_uns uns_sl_2 (v_uns a, v_uns b) +{ + return vec_sl (a, b); +} + +v_uns uns_sl_3 (v_uns a, v_uns b) +{ + return vec_vsld (a, b); +} + +v_sign sign_sra_1 (v_sign a, v_sign b) +{ + return __builtin_altivec_vsrad (a, b); +} + +v_sign sign_sra_2 (v_sign a, v_uns b) +{ + return vec_sra (a, b); +} + +v_sign sign_sra_3 (v_sign a, v_uns b) +{ + return vec_vsrad (a, b); +} + +/* { dg-final { scan-assembler-times "vaddudm" 5 } } */ +/* { dg-final { scan-assembler-times "vsubudm" 6 } } */ +/* { dg-final { scan-assembler-times "vmaxsd" 4 } } */ +/* { dg-final { scan-assembler-times "vminsd" 3 } } */ +/* { dg-final { scan-assembler-times "vmaxud" 2 } } */ +/* { dg-final { scan-assembler-times "vminud" 2 } } */ +/* { dg-final { scan-assembler-times "vcmpequd" 2 } } */ +/* { dg-final { scan-assembler-times "vcmpgtsd" 1 } } */ +/* { dg-final { scan-assembler-times "vcmpgtud" 1 } } */ +/* { dg-final { scan-assembler-times "vrld" 3 } } */ +/* { dg-final { scan-assembler-times "vsld" 5 } } */ +/* { dg-final { scan-assembler-times "vsrad" 3 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c new file mode 100644 index 000000000..b3f725f2d --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c @@ -0,0 +1,104 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */ + +#include <altivec.h> + +typedef vector long long vll_sign; +typedef vector unsigned long long vll_uns; +typedef vector bool long long vll_bool; + +typedef vector int vi_sign; +typedef vector unsigned int vi_uns; +typedef vector bool int vi_bool; + +typedef vector short vs_sign; +typedef vector unsigned short vs_uns; +typedef vector bool short vs_bool; + +typedef vector signed char vc_sign; +typedef vector unsigned char vc_uns; +typedef vector bool char vc_bool; + + +vi_sign vi_pack_1 (vll_sign a, vll_sign b) +{ + return __builtin_altivec_vpkudum (a, b); +} + +vi_sign vi_pack_2 (vll_sign a, vll_sign b) +{ + return vec_pack (a, b); +} + +vi_sign vi_pack_3 (vll_sign a, vll_sign b) +{ + return vec_vpkudum (a, b); +} + +vs_sign vs_pack_1 (vi_sign a, vi_sign b) +{ + return __builtin_altivec_vpkuwum (a, b); +} + +vs_sign vs_pack_2 (vi_sign a, vi_sign b) +{ + return vec_pack (a, b); +} + +vs_sign vs_pack_3 (vi_sign a, vi_sign b) +{ + return vec_vpkuwum (a, b); +} + +vc_sign vc_pack_1 (vs_sign a, vs_sign b) +{ + return __builtin_altivec_vpkuhum (a, b); +} + +vc_sign vc_pack_2 (vs_sign a, vs_sign b) +{ + return vec_pack (a, b); +} + +vc_sign vc_pack_3 (vs_sign a, vs_sign b) +{ + return vec_vpkuhum (a, b); +} + +vll_sign vll_unpack_hi_1 (vi_sign a) +{ + return __builtin_altivec_vupkhsw (a); +} + +vll_sign vll_unpack_hi_2 (vi_sign a) +{ + return vec_unpackh (a); +} + +vll_sign vll_unpack_hi_3 (vi_sign a) +{ + return __builtin_vec_vupkhsw (a); +} + +vll_sign vll_unpack_lo_1 (vi_sign a) +{ + return vec_vupklsw (a); +} + +vll_sign vll_unpack_lo_2 (vi_sign a) +{ + return vec_unpackl (a); +} + +vll_sign vll_unpack_lo_3 (vi_sign a) +{ + return vec_vupklsw (a); +} + +/* { dg-final { scan-assembler-times "vpkudum" 3 } } */ +/* { dg-final { scan-assembler-times "vpkuwum" 3 } } */ +/* { dg-final { scan-assembler-times "vpkuhum" 3 } } */ +/* { dg-final { scan-assembler-times "vupklsw" 3 } } */ +/* { dg-final { scan-assembler-times "vupkhsw" 3 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c new file mode 100644 index 000000000..518a6aa5e --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c @@ -0,0 +1,249 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O3 -ftree-vectorize -fvect-cost-model" } */ + +#include <altivec.h> + +typedef vector long long vll_sign; +typedef vector unsigned long long vll_uns; +typedef vector bool long long vll_bool; + +typedef vector int vi_sign; +typedef vector unsigned int vi_uns; +typedef vector bool int vi_bool; + +typedef vector short vs_sign; +typedef vector unsigned short vs_uns; +typedef vector bool short vs_bool; + +typedef vector signed char vc_sign; +typedef vector unsigned char vc_uns; +typedef vector bool char vc_bool; + +vll_sign vll_clz_1 (vll_sign a) +{ + return __builtin_altivec_vclzd (a); +} + +vll_sign vll_clz_2 (vll_sign a) +{ + return vec_vclz (a); +} + +vll_sign vll_clz_3 (vll_sign a) +{ + return vec_vclzd (a); +} + +vll_uns vll_clz_4 (vll_uns a) +{ + return vec_vclz (a); +} + +vll_uns vll_clz_5 (vll_uns a) +{ + return vec_vclzd (a); +} + +vi_sign vi_clz_1 (vi_sign a) +{ + return __builtin_altivec_vclzw (a); +} + +vi_sign vi_clz_2 (vi_sign a) +{ + return vec_vclz (a); +} + +vi_sign vi_clz_3 (vi_sign a) +{ + return vec_vclzw (a); +} + +vi_uns vi_clz_4 (vi_uns a) +{ + return vec_vclz (a); +} + +vi_uns vi_clz_5 (vi_uns a) +{ + return vec_vclzw (a); +} + +vs_sign vs_clz_1 (vs_sign a) +{ + return __builtin_altivec_vclzh (a); +} + +vs_sign vs_clz_2 (vs_sign a) +{ + return vec_vclz (a); +} + +vs_sign vs_clz_3 (vs_sign a) +{ + return vec_vclzh (a); +} + +vs_uns vs_clz_4 (vs_uns a) +{ + return vec_vclz (a); +} + +vs_uns vs_clz_5 (vs_uns a) +{ + return vec_vclzh (a); +} + +vc_sign vc_clz_1 (vc_sign a) +{ + return __builtin_altivec_vclzb (a); +} + +vc_sign vc_clz_2 (vc_sign a) +{ + return vec_vclz (a); +} + +vc_sign vc_clz_3 (vc_sign a) +{ + return vec_vclzb (a); +} + +vc_uns vc_clz_4 (vc_uns a) +{ + return vec_vclz (a); +} + +vc_uns vc_clz_5 (vc_uns a) +{ + return vec_vclzb (a); +} + +vll_sign vll_popcnt_1 (vll_sign a) +{ + return __builtin_altivec_vpopcntd (a); +} + +vll_sign vll_popcnt_2 (vll_sign a) +{ + return vec_vpopcnt (a); +} + +vll_sign vll_popcnt_3 (vll_sign a) +{ + return vec_vpopcntd (a); +} + +vll_uns vll_popcnt_4 (vll_uns a) +{ + return vec_vpopcnt (a); +} + +vll_uns vll_popcnt_5 (vll_uns a) +{ + return vec_vpopcntd (a); +} + +vi_sign vi_popcnt_1 (vi_sign a) +{ + return __builtin_altivec_vpopcntw (a); +} + +vi_sign vi_popcnt_2 (vi_sign a) +{ + return vec_vpopcnt (a); +} + +vi_sign vi_popcnt_3 (vi_sign a) +{ + return vec_vpopcntw (a); +} + +vi_uns vi_popcnt_4 (vi_uns a) +{ + return vec_vpopcnt (a); +} + +vi_uns vi_popcnt_5 (vi_uns a) +{ + return vec_vpopcntw (a); +} + +vs_sign vs_popcnt_1 (vs_sign a) +{ + return __builtin_altivec_vpopcnth (a); +} + +vs_sign vs_popcnt_2 (vs_sign a) +{ + return vec_vpopcnt (a); +} + +vs_sign vs_popcnt_3 (vs_sign a) +{ + return vec_vpopcnth (a); +} + +vs_uns vs_popcnt_4 (vs_uns a) +{ + return vec_vpopcnt (a); +} + +vs_uns vs_popcnt_5 (vs_uns a) +{ + return vec_vpopcnth (a); +} + +vc_sign vc_popcnt_1 (vc_sign a) +{ + return __builtin_altivec_vpopcntb (a); +} + +vc_sign vc_popcnt_2 (vc_sign a) +{ + return vec_vpopcnt (a); +} + +vc_sign vc_popcnt_3 (vc_sign a) +{ + return vec_vpopcntb (a); +} + +vc_uns vc_popcnt_4 (vc_uns a) +{ + return vec_vpopcnt (a); +} + +vc_uns vc_popcnt_5 (vc_uns a) +{ + return vec_vpopcntb (a); +} + +vc_uns vc_gbb_1 (vc_uns a) +{ + return __builtin_altivec_vgbbd (a); +} + +vc_sign vc_gbb_2 (vc_sign a) +{ + return vec_vgbbd (a); +} + +vc_uns vc_gbb_3 (vc_uns a) +{ + return vec_vgbbd (a); +} + +/* { dg-final { scan-assembler-times "vclzd" 5 } } */ +/* { dg-final { scan-assembler-times "vclzw" 5 } } */ +/* { dg-final { scan-assembler-times "vclzh" 5 } } */ +/* { dg-final { scan-assembler-times "vclzb" 5 } } */ + +/* { dg-final { scan-assembler-times "vpopcntd" 5 } } */ +/* { dg-final { scan-assembler-times "vpopcntw" 5 } } */ +/* { dg-final { scan-assembler-times "vpopcnth" 5 } } */ +/* { dg-final { scan-assembler-times "vpopcntb" 5 } } */ + +/* { dg-final { scan-assembler-times "vgbbd" 3 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c new file mode 100644 index 000000000..2e64551ff --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c @@ -0,0 +1,105 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ + +#include <altivec.h> + +#ifndef SIZE +#define SIZE 1024 +#endif + +#ifndef ALIGN +#define ALIGN 32 +#endif + +#ifndef ATTR_ALIGN +#define ATTR_ALIGN __attribute__((__aligned__(ALIGN))) +#endif + +#define DOIT(TYPE, PREFIX) \ +TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \ +{ \ + return vec_eqv (a, b); \ +} \ + \ +TYPE PREFIX ## _eqv_arith (TYPE a, TYPE b) \ +{ \ + return ~(a ^ b); \ +} \ + \ +TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \ +{ \ + return vec_nand (a, b); \ +} \ + \ +TYPE PREFIX ## _nand_arith1 (TYPE a, TYPE b) \ +{ \ + return ~(a & b); \ +} \ + \ +TYPE PREFIX ## _nand_arith2 (TYPE a, TYPE b) \ +{ \ + return (~a) | (~b); \ +} \ + \ +TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \ +{ \ + return vec_orc (a, b); \ +} \ + \ +TYPE PREFIX ## _orc_arith1 (TYPE a, TYPE b) \ +{ \ + return (~ a) | b; \ +} \ + \ +TYPE PREFIX ## _orc_arith2 (TYPE a, TYPE b) \ +{ \ + return a | (~ b); \ +} + +#define DOIT_FLOAT(TYPE, PREFIX) \ +TYPE PREFIX ## _eqv_builtin (TYPE a, TYPE b) \ +{ \ + return vec_eqv (a, b); \ +} \ + \ +TYPE PREFIX ## _nand_builtin (TYPE a, TYPE b) \ +{ \ + return vec_nand (a, b); \ +} \ + \ +TYPE PREFIX ## _orc_builtin (TYPE a, TYPE b) \ +{ \ + return vec_orc (a, b); \ +} + +typedef vector signed char sign_char_vec; +typedef vector short sign_short_vec; +typedef vector int sign_int_vec; +typedef vector long long sign_llong_vec; + +typedef vector unsigned char uns_char_vec; +typedef vector unsigned short uns_short_vec; +typedef vector unsigned int uns_int_vec; +typedef vector unsigned long long uns_llong_vec; + +typedef vector float float_vec; +typedef vector double double_vec; + +DOIT(sign_char_vec, sign_char) +DOIT(sign_short_vec, sign_short) +DOIT(sign_int_vec, sign_int) +DOIT(sign_llong_vec, sign_llong) + +DOIT(uns_char_vec, uns_char) +DOIT(uns_short_vec, uns_short) +DOIT(uns_int_vec, uns_int) +DOIT(uns_llong_vec, uns_llong) + +DOIT_FLOAT(float_vec, float) +DOIT_FLOAT(double_vec, double) + +/* { dg-final { scan-assembler-times "xxleqv" 18 } } */ +/* { dg-final { scan-assembler-times "xxlnand" 26 } } */ +/* { dg-final { scan-assembler-times "xxlorc" 26 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c new file mode 100644 index 000000000..8b81781c6 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +vector float dbl_to_float_p8 (double x) { return __builtin_vsx_xscvdpspn (x); } +double float_to_dbl_p8 (vector float x) { return __builtin_vsx_xscvspdpn (x); } + +/* { dg-final { scan-assembler "xscvdpspn" } } */ +/* { dg-final { scan-assembler "xscvspdpn" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c new file mode 100644 index 000000000..45a300fb9 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c @@ -0,0 +1,32 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +#include <altivec.h> + +typedef vector int v_sign; +typedef vector unsigned int v_uns; + +v_sign even_sign (v_sign a, v_sign b) +{ + return vec_vmrgew (a, b); +} + +v_uns even_uns (v_uns a, v_uns b) +{ + return vec_vmrgew (a, b); +} + +v_sign odd_sign (v_sign a, v_sign b) +{ + return vec_vmrgow (a, b); +} + +v_uns odd_uns (v_uns a, v_uns b) +{ + return vec_vmrgow (a, b); +} + +/* { dg-final { scan-assembler-times "vmrgew" 2 } } */ +/* { dg-final { scan-assembler-times "vmrgow" 2 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c new file mode 100644 index 000000000..3cfd8161d --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c @@ -0,0 +1,139 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf -fno-math-errno" } */ + +float abs_sf (float *p) +{ + float f = *p; + __asm__ ("# reg %x0" : "+v" (f)); + return __builtin_fabsf (f); +} + +float nabs_sf (float *p) +{ + float f = *p; + __asm__ ("# reg %x0" : "+v" (f)); + return - __builtin_fabsf (f); +} + +float neg_sf (float *p) +{ + float f = *p; + __asm__ ("# reg %x0" : "+v" (f)); + return - f; +} + +float add_sf (float *p, float *q) +{ + float f1 = *p; + float f2 = *q; + __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2)); + return f1 + f2; +} + +float sub_sf (float *p, float *q) +{ + float f1 = *p; + float f2 = *q; + __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2)); + return f1 - f2; +} + +float mul_sf (float *p, float *q) +{ + float f1 = *p; + float f2 = *q; + __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2)); + return f1 * f2; +} + +float div_sf (float *p, float *q) +{ + float f1 = *p; + float f2 = *q; + __asm__ ("# reg %x0, %x1" : "+v" (f1), "+v" (f2)); + return f1 / f2; +} + +float sqrt_sf (float *p) +{ + float f = *p; + __asm__ ("# reg %x0" : "+v" (f)); + return __builtin_sqrtf (f); +} + + +double abs_df (double *p) +{ + double d = *p; + __asm__ ("# reg %x0" : "+v" (d)); + return __builtin_fabs (d); +} + +double nabs_df (double *p) +{ + double d = *p; + __asm__ ("# reg %x0" : "+v" (d)); + return - __builtin_fabs (d); +} + +double neg_df (double *p) +{ + double d = *p; + __asm__ ("# reg %x0" : "+v" (d)); + return - d; +} + +double add_df (double *p, double *q) +{ + double d1 = *p; + double d2 = *q; + __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2)); + return d1 + d2; +} + +double sub_df (double *p, double *q) +{ + double d1 = *p; + double d2 = *q; + __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2)); + return d1 - d2; +} + +double mul_df (double *p, double *q) +{ + double d1 = *p; + double d2 = *q; + __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2)); + return d1 * d2; +} + +double div_df (double *p, double *q) +{ + double d1 = *p; + double d2 = *q; + __asm__ ("# reg %x0, %x1" : "+v" (d1), "+v" (d2)); + return d1 / d2; +} + +double sqrt_df (float *p) +{ + double d = *p; + __asm__ ("# reg %x0" : "+v" (d)); + return __builtin_sqrt (d); +} + +/* { dg-final { scan-assembler "xsabsdp" } } */ +/* { dg-final { scan-assembler "xsadddp" } } */ +/* { dg-final { scan-assembler "xsaddsp" } } */ +/* { dg-final { scan-assembler "xsdivdp" } } */ +/* { dg-final { scan-assembler "xsdivsp" } } */ +/* { dg-final { scan-assembler "xsmuldp" } } */ +/* { dg-final { scan-assembler "xsmulsp" } } */ +/* { dg-final { scan-assembler "xsnabsdp" } } */ +/* { dg-final { scan-assembler "xsnegdp" } } */ +/* { dg-final { scan-assembler "xssqrtdp" } } */ +/* { dg-final { scan-assembler "xssqrtsp" } } */ +/* { dg-final { scan-assembler "xssubdp" } } */ +/* { dg-final { scan-assembler "xssubsp" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c new file mode 100644 index 000000000..86bde3241 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c @@ -0,0 +1,85 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O3 -mvsx-timode" } */ + +#include <altivec.h> + +#ifndef TYPE +#define TYPE vector __int128_t +#endif + +TYPE +do_addcuq (TYPE p, TYPE q) +{ + return __builtin_vec_vaddcuq (p, q); +} + +TYPE +do_adduqm (TYPE p, TYPE q) +{ + return __builtin_vec_add (p, q); +} + +TYPE +do_addeuqm (TYPE p, TYPE q, TYPE r) +{ + return __builtin_vec_vaddeuqm (p, q, r); +} + +TYPE +do_addecuq (TYPE p, TYPE q, TYPE r) +{ + return __builtin_vec_vaddecuq (p, q, r); +} + +TYPE +do_subeuqm (TYPE p, TYPE q, TYPE r) +{ + return __builtin_vec_vsubeuqm (p, q, r); +} + +TYPE +do_subecuq (TYPE p, TYPE q, TYPE r) +{ + return __builtin_vec_vsubecuq (p, q, r); +} + +TYPE +do_subcuq (TYPE p, TYPE q) +{ + return __builtin_vec_vsubcuq (p, q); +} + +TYPE +do_subuqm (TYPE p, TYPE q) +{ + return __builtin_vec_vsubuqm (p, q); +} + +TYPE +do_zero (void) +{ + return (TYPE) { 0 }; +} + +TYPE +do_minus_one (void) +{ + return (TYPE) { -1 }; +} + +/* { dg-final { scan-assembler "vaddcuq" } } */ +/* { dg-final { scan-assembler "vadduqm" } } */ +/* { dg-final { scan-assembler "vaddecuq" } } */ +/* { dg-final { scan-assembler "vaddeuqm" } } */ +/* { dg-final { scan-assembler "vsubecuq" } } */ +/* { dg-final { scan-assembler "vsubeuqm" } } */ +/* { dg-final { scan-assembler "vsubcuq" } } */ +/* { dg-final { scan-assembler "vsubuqm" } } */ +/* { dg-final { scan-assembler-not "mtvsrd" } } */ +/* { dg-final { scan-assembler-not "mfvsrd" } } */ +/* { dg-final { scan-assembler-not "ori 2,2,0" } } */ +/* { dg-final { scan-assembler-not "xxpermdi" } } */ +/* { dg-final { scan-assembler-not "stxvd2x" } } */ +/* { dg-final { scan-assembler-not "stxvw4x" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c new file mode 100644 index 000000000..1064894dc --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c @@ -0,0 +1,177 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +#include <stddef.h> +#include <stdlib.h> +#include <altivec.h> + +#ifdef DEBUG +#include <stdio.h> +#define UNUSED + +#ifdef __LITTLE_ENDIAN__ +#define HI_WORD 1 +#define LO_WORD 0 +#else +#define HI_WORD 0 +#define LO_WORD 1 +#endif + +#else +#define UNUSED __attribute__((__unused__)) +#endif + +#ifndef S_TYPE +#define S_TYPE __uint128_t +#endif + +#ifndef V_TYPE +#define V_TYPE vector S_TYPE +#endif + +static int compare (S_TYPE, V_TYPE, const char *, const char *) + __attribute__((__noinline__)); + +static int +compare (S_TYPE scalar, + V_TYPE vect, + const char *nl UNUSED, + const char *which UNUSED) +{ + unsigned long scalar_lo = (unsigned long) scalar; + unsigned long scalar_hi = (unsigned long) (scalar >> 64); + unsigned long vect_lo; + unsigned long vect_hi; + vector long long tmp; + int ret; + + __asm__ ("mfvsrd %0,%x3\n\t" + "xxpermdi %x2,%x3,%x3,3\n\t" + "mfvsrd %1,%x2" + : "=r" (vect_hi), + "=r" (vect_lo), + "=wa" (tmp) + : "wa" (vect)); + + ret = (scalar_lo != vect_lo) || (scalar_hi != vect_hi); + +#ifdef DEBUG + printf ("%s%s: 0x%.16lx %.16lx %s 0x%.16lx %.16lx\n", + nl, which, + scalar_hi, scalar_lo, + (ret) ? "!=" : "==", + vect_hi, vect_lo); + + fflush (stdout); +#endif + + return ret; +} + +static void convert_via_mem (V_TYPE *, S_TYPE *) + __attribute__((__noinline__)); + +static void +convert_via_mem (V_TYPE *v, S_TYPE *s) +{ + *v = (V_TYPE) { *s }; + __asm__ volatile ("nop" + : "+m" (*s), "+m" (*v) + : + : "memory"); + +} + + +/* Check if vadduqm returns the same values as normal 128-bit add. */ + +/* Values to add together. */ +const static struct { + unsigned long hi_1; + unsigned long lo_1; + unsigned long hi_2; + unsigned long lo_2; +} values[] = { + { 0x0000000000000000UL, 0xfffffffffffffffeUL, + 0x0000000000000000UL, 0x0000000000000002UL }, + { 0x0000000000000000UL, 0x0000000000000002UL, + 0x0000000000000000UL, 0xfffffffffffffffeUL }, + { 0xffffffffffffffffUL, 0xfffffffffffffffeUL, + 0x0000000000000000UL, 0x0000000000000002UL }, + { 0xfffffffffffffff2UL, 0xffffffffffffffffUL, + 0x0000000000000002UL, 0x0000000000000000UL }, + { 0x7fffffffffffffffUL, 0xfffffffffffffffeUL, + 0x0000000000000000UL, 0x0000000000000002UL }, + { 0x7ffffffffffffff2UL, 0xffffffffffffffffUL, + 0x0000000000000002UL, 0x0000000000000000UL }, +}; + +int +main (void) +{ + int reg_errors = 0; + int mem_errors = 0; + size_t i; + const char *nl = ""; + + for (i = 0; i < sizeof (values) / sizeof (values[0]); i++) + { + S_TYPE s_reg_res, s_reg_in1, s_reg_in2, s_mem_res, s_mem_in1, s_mem_in2; + V_TYPE v_reg_res, v_reg_in1, v_reg_in2, v_mem_res, v_mem_in1, v_mem_in2; + + s_reg_in1 = ((((S_TYPE)values[i].hi_1 << 64)) + ((S_TYPE)values[i].lo_1)); + reg_errors += compare (s_reg_in1, (V_TYPE) { s_reg_in1 }, nl, "reg, in1"); + + s_reg_in2 = ((((S_TYPE)values[i].hi_2 << 64)) + ((S_TYPE)values[i].lo_2)); + reg_errors += compare (s_reg_in2, (V_TYPE) { s_reg_in2 }, "", "reg, in2"); + + s_reg_res = s_reg_in1 + s_reg_in2; + + v_reg_in1 = (V_TYPE) { s_reg_in1 }; + v_reg_in2 = (V_TYPE) { s_reg_in2 }; + v_reg_res = vec_vadduqm (v_reg_in1, v_reg_in2); + reg_errors += compare (s_reg_res, v_reg_res, "", "reg, res"); + + s_mem_in1 = s_reg_in1; + convert_via_mem (&v_mem_in1, &s_mem_in1); + mem_errors += compare (s_mem_in1, (V_TYPE) { s_mem_in1 }, "\n", "mem, in1"); + + s_mem_in2 = s_reg_in2; + convert_via_mem (&v_mem_in2, &s_mem_in2); + mem_errors += compare (s_mem_in2, (V_TYPE) { s_mem_in2 }, "", "mem, in2"); + + s_mem_res = s_mem_in1 + s_mem_in2; + v_mem_res = vec_vadduqm (v_mem_in1, v_mem_in2); + mem_errors += compare (s_mem_res, v_mem_res, "", "mem, res"); + + nl = "\n"; + } + +#ifdef DEBUG + putchar ('\n'); + + if (!reg_errors) + fputs ("no errors found on register operations\n", stdout); + else + printf ("%d error%s found on register operations\n", + reg_errors, + (reg_errors == 1) ? "s" : ""); + + if (!mem_errors) + fputs ("no errors found on memory operations\n", stdout); + else + printf ("%d error%s found on memory operations\n", + mem_errors, + (mem_errors == 1) ? "s" : ""); + + fflush (stdout); +#endif + + if ((reg_errors + mem_errors) != 0) + abort (); + + return 0; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c new file mode 100644 index 000000000..33f19991f --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -mupper-regs-df -mupper-regs-sf" } */ + +float load_sf (float *p) +{ + float f = *p; + __asm__ ("# reg %x0" : "+v" (f)); + return f; +} + +double load_df (double *p) +{ + double d = *p; + __asm__ ("# reg %x0" : "+v" (d)); + return d; +} + +double load_dfsf (float *p) +{ + double d = (double) *p; + __asm__ ("# reg %x0" : "+v" (d)); + return d; +} + +void store_sf (float *p, float f) +{ + __asm__ ("# reg %x0" : "+v" (f)); + *p = f; +} + +void store_df (double *p, double d) +{ + __asm__ ("# reg %x0" : "+v" (d)); + *p = d; +} + +/* { dg-final { scan-assembler "lxsspx" } } */ +/* { dg-final { scan-assembler "lxsdx" } } */ +/* { dg-final { scan-assembler "stxsspx" } } */ +/* { dg-final { scan-assembler "stxsdx" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c new file mode 100644 index 000000000..d1664985a --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O3 -mcpu=power8" } */ +/* { dg-final { scan-assembler "vbpermq" } } */ +/* { dg-final { scan-assembler "mfvsrd" } } */ +/* { dg-final { scan-assembler-not "stfd" } } */ +/* { dg-final { scan-assembler-not "stxvd2x" } } */ + +#include <altivec.h> + +#if __LITTLE_ENDIAN__ +#define OFFSET 1 +#else +#define OFFSET 0 +#endif + +long foos (vector signed char a, vector signed char b) +{ + return vec_extract (vec_vbpermq (a, b), OFFSET); +} + +long foou (vector unsigned char a, vector unsigned char b) +{ + return vec_extract (vec_vbpermq (a, b), OFFSET); +} + diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c new file mode 100644 index 000000000..9a975bd6f --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c @@ -0,0 +1,200 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +#ifndef ALIGN +#define ALIGN 32 +#endif + +#ifndef TYPE +#define TYPE long long +#endif + +#ifndef SIGN_TYPE +#define SIGN_TYPE signed TYPE +#endif + +#ifndef UNS_TYPE +#define UNS_TYPE unsigned TYPE +#endif + +#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) + +SIGN_TYPE sa[SIZE] ALIGN_ATTR; +SIGN_TYPE sb[SIZE] ALIGN_ATTR; +SIGN_TYPE sc[SIZE] ALIGN_ATTR; + +UNS_TYPE ua[SIZE] ALIGN_ATTR; +UNS_TYPE ub[SIZE] ALIGN_ATTR; +UNS_TYPE uc[SIZE] ALIGN_ATTR; + +void +sign_add (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = sb[i] + sc[i]; +} + +void +sign_sub (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = sb[i] - sc[i]; +} + +void +sign_shift_left (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = sb[i] << sc[i]; +} + +void +sign_shift_right (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = sb[i] >> sc[i]; +} + +void +sign_max (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = (sb[i] > sc[i]) ? sb[i] : sc[i]; +} + +void +sign_min (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = (sb[i] < sc[i]) ? sb[i] : sc[i]; +} + +void +sign_abs (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = (sb[i] < 0) ? -sb[i] : sb[i]; /* xor, vsubudm, vmaxsd. */ +} + +void +sign_eq (SIGN_TYPE val1, SIGN_TYPE val2) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = (sb[i] == sc[i]) ? val1 : val2; +} + +void +sign_lt (SIGN_TYPE val1, SIGN_TYPE val2) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + sa[i] = (sb[i] < sc[i]) ? val1 : val2; +} + +void +uns_add (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + ua[i] = ub[i] + uc[i]; +} + +void +uns_sub (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + ua[i] = ub[i] - uc[i]; +} + +void +uns_shift_left (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + ua[i] = ub[i] << uc[i]; +} + +void +uns_shift_right (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + ua[i] = ub[i] >> uc[i]; +} + +void +uns_max (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + ua[i] = (ub[i] > uc[i]) ? ub[i] : uc[i]; +} + +void +uns_min (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + ua[i] = (ub[i] < uc[i]) ? ub[i] : uc[i]; +} + +void +uns_eq (UNS_TYPE val1, UNS_TYPE val2) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + ua[i] = (ub[i] == uc[i]) ? val1 : val2; +} + +void +uns_lt (UNS_TYPE val1, UNS_TYPE val2) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + ua[i] = (ub[i] < uc[i]) ? val1 : val2; +} + +/* { dg-final { scan-assembler-times "\[\t \]vaddudm\[\t \]" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vsubudm\[\t \]" 3 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vmaxsd\[\t \]" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vmaxud\[\t \]" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vminsd\[\t \]" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vminud\[\t \]" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vsld\[\t \]" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vsrad\[\t \]" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vsrd\[\t \]" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vcmpequd\[\t \]" 2 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vcmpgtsd\[\t \]" 1 } } */ +/* { dg-final { scan-assembler-times "\[\t \]vcmpgtud\[\t \]" 1 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c new file mode 100644 index 000000000..8feba0a13 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */ + +#include <stddef.h> + +#ifndef SIZE +#define SIZE 1024 +#endif + +#ifndef ALIGN +#define ALIGN 32 +#endif + +#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) + +long long sign_ll[SIZE] ALIGN_ATTR; +int sign_i [SIZE] ALIGN_ATTR; + +void copy_int_to_long_long (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + sign_ll[i] = sign_i[i]; +} + +/* { dg-final { scan-assembler "vupkhsw" } } */ +/* { dg-final { scan-assembler "vupklsw" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c new file mode 100644 index 000000000..570f2e599 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c @@ -0,0 +1,29 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model" } */ + +#include <stddef.h> + +#ifndef SIZE +#define SIZE 1024 +#endif + +#ifndef ALIGN +#define ALIGN 32 +#endif + +#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) + +long long sign_ll[SIZE] ALIGN_ATTR; +int sign_i [SIZE] ALIGN_ATTR; + +void copy_long_long_to_int (void) +{ + size_t i; + + for (i = 0; i < SIZE; i++) + sign_i[i] = sign_ll[i]; +} + +/* { dg-final { scan-assembler "vpkudum" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c new file mode 100644 index 000000000..90df88680 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c @@ -0,0 +1,69 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +#ifndef ALIGN +#define ALIGN 32 +#endif + +#define ALIGN_ATTR __attribute__((__aligned__(ALIGN))) + +#define DO_BUILTIN(PREFIX, TYPE, CLZ, POPCNT) \ +TYPE PREFIX ## _a[SIZE] ALIGN_ATTR; \ +TYPE PREFIX ## _b[SIZE] ALIGN_ATTR; \ + \ +void \ +PREFIX ## _clz (void) \ +{ \ + unsigned long i; \ + \ + for (i = 0; i < SIZE; i++) \ + PREFIX ## _a[i] = CLZ (PREFIX ## _b[i]); \ +} \ + \ +void \ +PREFIX ## _popcnt (void) \ +{ \ + unsigned long i; \ + \ + for (i = 0; i < SIZE; i++) \ + PREFIX ## _a[i] = POPCNT (PREFIX ## _b[i]); \ +} + +#if !defined(DO_LONG_LONG) && !defined(DO_LONG) && !defined(DO_INT) && !defined(DO_SHORT) && !defined(DO_CHAR) +#define DO_INT 1 +#endif + +#if DO_LONG_LONG +/* At the moment, only int is auto vectorized. */ +DO_BUILTIN (sll, long long, __builtin_clzll, __builtin_popcountll) +DO_BUILTIN (ull, unsigned long long, __builtin_clzll, __builtin_popcountll) +#endif + +#if defined(_ARCH_PPC64) && DO_LONG +DO_BUILTIN (sl, long, __builtin_clzl, __builtin_popcountl) +DO_BUILTIN (ul, unsigned long, __builtin_clzl, __builtin_popcountl) +#endif + +#if DO_INT +DO_BUILTIN (si, int, __builtin_clz, __builtin_popcount) +DO_BUILTIN (ui, unsigned int, __builtin_clz, __builtin_popcount) +#endif + +#if DO_SHORT +DO_BUILTIN (ss, short, __builtin_clz, __builtin_popcount) +DO_BUILTIN (us, unsigned short, __builtin_clz, __builtin_popcount) +#endif + +#if DO_CHAR +DO_BUILTIN (sc, signed char, __builtin_clz, __builtin_popcount) +DO_BUILTIN (uc, unsigned char, __builtin_clz, __builtin_popcount) +#endif + +/* { dg-final { scan-assembler-times "vclzw" 2 } } */ +/* { dg-final { scan-assembler-times "vpopcntw" 2 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c new file mode 100644 index 000000000..17563bf47 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c @@ -0,0 +1,87 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O2 -ftree-vectorize -fvect-cost-model -fno-unroll-loops -fno-unroll-all-loops" } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +#ifndef ALIGN +#define ALIGN 32 +#endif + +#ifndef ATTR_ALIGN +#define ATTR_ALIGN __attribute__((__aligned__(ALIGN))) +#endif + +#ifndef TYPE +#define TYPE unsigned int +#endif + +TYPE in1 [SIZE] ATTR_ALIGN; +TYPE in2 [SIZE] ATTR_ALIGN; +TYPE eqv [SIZE] ATTR_ALIGN; +TYPE nand1[SIZE] ATTR_ALIGN; +TYPE nand2[SIZE] ATTR_ALIGN; +TYPE orc1 [SIZE] ATTR_ALIGN; +TYPE orc2 [SIZE] ATTR_ALIGN; + +void +do_eqv (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + { + eqv[i] = ~(in1[i] ^ in2[i]); + } +} + +void +do_nand1 (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + { + nand1[i] = ~(in1[i] & in2[i]); + } +} + +void +do_nand2 (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + { + nand2[i] = (~in1[i]) | (~in2[i]); + } +} + +void +do_orc1 (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + { + orc1[i] = (~in1[i]) | in2[i]; + } +} + +void +do_orc2 (void) +{ + unsigned long i; + + for (i = 0; i < SIZE; i++) + { + orc1[i] = in1[i] | (~in2[i]); + } +} + +/* { dg-final { scan-assembler-times "xxleqv" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnand" 2 } } */ +/* { dg-final { scan-assembler-times "xxlorc" 2 } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack01.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack01.c new file mode 100644 index 000000000..efac4087c --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack01.c @@ -0,0 +1,91 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +#include <stddef.h> +#include <stdlib.h> +#include <altivec.h> + +#ifdef DEBUG +#include <stdio.h> +#endif + +typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; +typedef __int128_t scalar_128_t; +typedef unsigned long long scalar_64_t; + +volatile scalar_64_t one = 1; +volatile scalar_64_t two = 2; + +int +main (void) +{ + scalar_128_t a = (((scalar_128_t)one) << 64) | ((scalar_128_t)two); + vector_128_t v1 = (vector_128_t) { a }; + vector_128_t v2 = __builtin_pack_vector_int128 (one, two); + scalar_64_t x0 = __builtin_unpack_vector_int128 (v1, 0); + scalar_64_t x1 = __builtin_unpack_vector_int128 (v1, 1); + vector_128_t v3 = __builtin_pack_vector_int128 (x0, x1); + + size_t i; + union { + scalar_128_t i128; + vector_128_t v128; + scalar_64_t u64; + unsigned char uc[sizeof (scalar_128_t)]; + char c[sizeof (scalar_128_t)]; + } u, u2; + +#ifdef DEBUG + { + printf ("a = 0x"); + u.i128 = a; + for (i = 0; i < sizeof (scalar_128_t); i++) + printf ("%.2x", u.uc[i]); + + printf ("\nv1 = 0x"); + u.v128 = v1; + for (i = 0; i < sizeof (scalar_128_t); i++) + printf ("%.2x", u.uc[i]); + + printf ("\nv2 = 0x"); + u.v128 = v2; + for (i = 0; i < sizeof (scalar_128_t); i++) + printf ("%.2x", u.uc[i]); + + printf ("\nv3 = 0x"); + u.v128 = v3; + for (i = 0; i < sizeof (scalar_128_t); i++) + printf ("%.2x", u.uc[i]); + + printf ("\nx0 = 0x"); + u.u64 = x0; + for (i = 0; i < sizeof (scalar_64_t); i++) + printf ("%.2x", u.uc[i]); + + printf ("\nx1 = 0x"); + u.u64 = x1; + for (i = 0; i < sizeof (scalar_64_t); i++) + printf ("%.2x", u.uc[i]); + + printf ("\n"); + } +#endif + + u2.i128 = a; + u.v128 = v1; + if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0) + abort (); + + u.v128 = v2; + if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0) + abort (); + + u.v128 = v3; + if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0) + abort (); + + return 0; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack02.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack02.c new file mode 100644 index 000000000..584d6c292 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack02.c @@ -0,0 +1,95 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_fprs } */ +/* { dg-options "-O2 -mhard-float" } */ + +#include <stddef.h> +#include <stdlib.h> +#include <math.h> + +#ifdef DEBUG +#include <stdio.h> +#endif + +int +main (void) +{ + double high = pow (2.0, 60); + double low = 2.0; + long double a = ((long double)high) + ((long double)low); + double x0 = __builtin_unpack_longdouble (a, 0); + double x1 = __builtin_unpack_longdouble (a, 1); + long double b = __builtin_pack_longdouble (x0, x1); + +#ifdef DEBUG + { + size_t i; + union { + long double ld; + double d; + unsigned char uc[sizeof (long double)]; + char c[sizeof (long double)]; + } u; + + printf ("a = 0x"); + u.ld = a; + for (i = 0; i < sizeof (long double); i++) + printf ("%.2x", u.uc[i]); + + printf (", %Lg\n", a); + + printf ("b = 0x"); + u.ld = b; + for (i = 0; i < sizeof (long double); i++) + printf ("%.2x", u.uc[i]); + + printf (", %Lg\n", b); + + printf ("hi = 0x"); + u.d = high; + for (i = 0; i < sizeof (double); i++) + printf ("%.2x", u.uc[i]); + + printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", high); + + printf ("lo = 0x"); + u.d = low; + for (i = 0; i < sizeof (double); i++) + printf ("%.2x", u.uc[i]); + + printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", low); + + printf ("x0 = 0x"); + u.d = x0; + for (i = 0; i < sizeof (double); i++) + printf ("%.2x", u.uc[i]); + + printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x0); + + printf ("x1 = 0x"); + u.d = x1; + for (i = 0; i < sizeof (double); i++) + printf ("%.2x", u.uc[i]); + + printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x1); + } +#endif + + if (high != x0) + abort (); + + if (low != x1) + abort (); + + if (a != b) + abort (); + + if (x0 != high) + abort (); + + if (x1 != low) + abort (); + + return 0; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack03.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack03.c new file mode 100644 index 000000000..dfaf2efa0 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack03.c @@ -0,0 +1,88 @@ +/* { dg-do run { target { powerpc*-*-linux* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target dfp_hw } */ +/* { dg-options "-O2 -mhard-dfp" } */ + +#include <stddef.h> +#include <stdlib.h> +#include <math.h> + +#ifdef DEBUG +#include <stdio.h> +#endif + +int +main (void) +{ + _Decimal128 one = (_Decimal128)1.0; + _Decimal128 two = (_Decimal128)2.0; + _Decimal128 ten = (_Decimal128)10.0; + _Decimal128 a = one; + _Decimal128 b; + _Decimal128 c; + unsigned long long x0; + unsigned long long x1; + size_t i; + + for (i = 0; i < 25; i++) + a *= ten; + + a += two; + + x0 = __builtin_unpack_dec128 (a, 0); + x1 = __builtin_unpack_dec128 (a, 1); + b = __builtin_pack_dec128 (x0, x1); + c = __builtin_dscliq (one, 25) + two; + +#ifdef DEBUG + { + union { + _Decimal128 d; + unsigned long long ull; + unsigned char uc[sizeof (_Decimal128)]; + } u; + + printf ("a = 0x"); + u.d = a; + for (i = 0; i < sizeof (_Decimal128); i++) + printf ("%.2x", u.uc[i]); + + printf (", %Lg\n", (long double)a); + + printf ("b = 0x"); + u.d = b; + for (i = 0; i < sizeof (_Decimal128); i++) + printf ("%.2x", u.uc[i]); + + printf (", %Lg\n", (long double)b); + + printf ("c = 0x"); + u.d = c; + for (i = 0; i < sizeof (_Decimal128); i++) + printf ("%.2x", u.uc[i]); + + printf (", %Lg\n", (long double)c); + + printf ("x0 = 0x"); + u.ull = x0; + for (i = 0; i < sizeof (unsigned long long); i++) + printf ("%.2x", u.uc[i]); + + printf ("\nx1 = 0x"); + u.ull = x1; + for (i = 0; i < sizeof (unsigned long long); i++) + printf ("%.2x", u.uc[i]); + + printf ("\n"); + } +#endif + + if (a != b) + abort (); + + if (a != c) + abort (); + + return 0; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c index 8fcb7fd7f..9dc730e0d 100644 --- a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c @@ -89,8 +89,10 @@ typedef struct sf long a1; long a2; long a3; +#if _CALL_ELF != 2 long a4; long a5; +#endif parm_t slot[100]; } stack_frame_t; diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c index a9883d9e3..e4825973b 100644 --- a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c @@ -107,8 +107,10 @@ typedef struct sf long a1; long a2; long a3; +#if _CALL_ELF != 2 long a4; long a5; +#endif parm_t slot[100]; } stack_frame_t; @@ -119,6 +121,12 @@ typedef union vector int v; } vector_int_t; +#ifdef __LITTLE_ENDIAN__ +#define MAKE_SLOT(x, y) ((long)x | ((long)y << 32)) +#else +#define MAKE_SLOT(x, y) ((long)y | ((long)x << 32)) +#endif + /* Paramter passing. s : gpr 3 v : vpr 2 @@ -226,8 +234,8 @@ fcevv (char *s, ...) sp = __builtin_frame_address(0); sp = sp->backchain; - if (sp->slot[2].l != 0x100000002ULL - || sp->slot[4].l != 0x500000006ULL) + if (sp->slot[2].l != MAKE_SLOT (1, 2) + || sp->slot[4].l != MAKE_SLOT (5, 6)) abort(); } @@ -268,8 +276,8 @@ fciievv (char *s, int i, int j, ...) sp = __builtin_frame_address(0); sp = sp->backchain; - if (sp->slot[4].l != 0x100000002ULL - || sp->slot[6].l != 0x500000006ULL) + if (sp->slot[4].l != MAKE_SLOT (1, 2) + || sp->slot[6].l != MAKE_SLOT (5, 6)) abort(); } @@ -296,8 +304,8 @@ fcvevv (char *s, vector int x, ...) sp = __builtin_frame_address(0); sp = sp->backchain; - if (sp->slot[4].l != 0x100000002ULL - || sp->slot[6].l != 0x500000006ULL) + if (sp->slot[4].l != MAKE_SLOT (1, 2) + || sp->slot[6].l != MAKE_SLOT (5, 6)) abort(); } diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c index eb54a653b..9bd5e28e0 100644 --- a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c @@ -33,15 +33,27 @@ reg_parms_t gparms; /* Wrapper to save the GPRs and FPRs and then jump to the real function. */ -#define WRAPPER(NAME) \ -__asm__ ("\t.globl\t" #NAME "_asm\n\t" \ +#if _CALL_ELF != 2 +#define FUNC_START(NAME) \ + "\t.globl\t" NAME "\n\t" \ ".section \".opd\",\"aw\"\n\t" \ ".align 3\n" \ - #NAME "_asm:\n\t" \ - ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \ + NAME ":\n\t" \ + ".quad .L." NAME ",.TOC.@tocbase,0\n\t" \ + ".text\n\t" \ + ".type " NAME ", @function\n" \ + ".L." NAME ":\n\t" +#else +#define FUNC_START(NAME) \ + "\t.globl\t" NAME "\n\t" \ ".text\n\t" \ - ".type " #NAME "_asm, @function\n" \ - ".L." #NAME "_asm:\n\t" \ + NAME ":\n" \ + "0:\taddis 2,12,(.TOC.-0b)@ha\n\t" \ + "addi 2,2,(.TOC.-0b)@l\n\t" \ + ".localentry " NAME ",.-" NAME "\n\t" +#endif +#define WRAPPER(NAME) \ +__asm__ (FUNC_START (#NAME "_asm") \ "ld 11,gparms@got(2)\n\t" \ "std 3,0(11)\n\t" \ "std 4,8(11)\n\t" \ @@ -75,8 +87,10 @@ typedef struct sf long a1; long a2; long a3; +#if _CALL_ELF != 2 long a4; long a5; +#endif unsigned long slot[100]; } stack_frame_t; diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57744.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57744.c new file mode 100644 index 000000000..222fd6abd --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57744.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O3" } */ + +void abort (void); + +typedef unsigned U_16 __attribute__((mode(TI))); + +extern int libat_compare_exchange_16 (U_16 *, U_16 *, U_16, int, int) + __attribute__((__noinline__)); + +/* PR 57744: lqarx/stqcx needs even/odd register pairs. The assembler will + complain if the compiler gets an odd/even register pair. Create a function + which has the 16 byte compare and exchange instructions, but don't actually + execute it, so that we can detect these failures on older machines. */ + +int +libat_compare_exchange_16 (U_16 *mptr, U_16 *eptr, U_16 newval, + int smodel, int fmodel __attribute__((unused))) +{ + if (((smodel) == 0)) + return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 0, 0); + else if (((smodel) != 5)) + return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 4, 0); + else + return __atomic_compare_exchange_n (mptr, eptr, newval, 0, 5, 0); +} + +U_16 a = 1, b = 1, c = -2; +volatile int do_test = 0; + +int main (void) +{ + if (do_test && !libat_compare_exchange_16 (&a, &b, c, 0, 0)) + abort (); + + return 0; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57949-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57949-1.c new file mode 100644 index 000000000..dac305a01 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57949-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7 -mno-compat-align-parm" } */ + +/* Verify that vs is 16-byte aligned with -mcompat-align-parm. */ + +typedef float v4sf __attribute__ ((vector_size (16))); +struct s { long m; v4sf v; }; +long n; +v4sf ve; + +void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6, + long d7, long d8, long d9, struct s vs) { + n = vs.m; + ve = vs.v; +} + +/* { dg-final { scan-assembler "li \.\*,144" } } */ +/* { dg-final { scan-assembler "ld \.\*,128\\(1\\)" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57949-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57949-2.c new file mode 100644 index 000000000..39a24d9e4 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57949-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc_elfv2 } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ + +/* Verify that vs is not 16-byte aligned in the absence of -mno-compat-align-parm. */ + +typedef float v4sf __attribute__ ((vector_size (16))); +struct s { long m; v4sf v; }; +long n; +v4sf ve; + +void pr57949 (long d1, long d2, long d3, long d4, long d5, long d6, + long d7, long d8, long d9, struct s vs) { + n = vs.m; + ve = vs.v; +} + +/* { dg-final { scan-assembler "ld .\*,136\\(1\\)" } } */ +/* { dg-final { scan-assembler "ld .\*,120\\(1\\)" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr58673-1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr58673-1.c new file mode 100644 index 000000000..6f7838f8d --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr58673-1.c @@ -0,0 +1,78 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -m64 -O1" } */ + +enum typecode +{ + QIcode, QUcode, HIcode, HUcode, SIcode, SUcode, DIcode, DUcode, SFcode, + DFcode, XFcode, Pcode, Tcode, LAST_AND_UNUSED_TYPECODE +}; +enum bytecode_opcode +{ + neverneverland, drop, duplicate, over, setstackSI, adjstackSI, constQI, + constHI, constSI, constDI, constSF, constDF, constXF, constP, loadQI, + loadHI, loadSI, loadDI, loadSF, loadDF, loadXF, loadP, storeQI, storeHI, + storeSI, storeDI, storeSF, storeDF, storeXF, storeP, storeBLK, clearBLK, + addconstPSI, newlocalSI, localP, argP, convertQIHI, convertHISI, + convertSIDI, convertQISI, convertQUHU, convertHUSU, convertSUDU, + convertQUSU, convertSFDF, convertDFXF, convertHIQI, convertSIHI, + convertDISI, convertSIQI, convertSUQU, convertDFSF, convertXFDF, + convertSISF, convertSIDF, convertSIXF, convertSUSF, convertSUDF, + convertSUXF, convertDISF, convertDIDF, convertDIXF, convertDUSF, + convertDUDF, convertDUXF, convertSFSI, convertDFSI, convertXFSI, + convertSFSU, convertDFSU, convertXFSU, convertSFDI, convertDFDI, + convertXFDI, convertSFDU, convertDFDU, convertXFDU, convertPSI, + convertSIP, convertSIT, convertDIT, convertSFT, convertDFT, convertXFT, + convertPT, zxloadBI, sxloadBI, sstoreBI, addSI, addDI, addSF, addDF, + addXF, addPSI, subSI, subDI, subSF, subDF, subXF, subPP, mulSI, mulDI, + mulSU, mulDU, mulSF, mulDF, mulXF, divSI, divDI, divSU, divDU, divSF, + divDF, divXF, modSI, modDI, modSU, modDU, andSI, andDI, iorSI, iorDI, + xorSI, xorDI, lshiftSI, lshiftSU, lshiftDI, lshiftDU, rshiftSI, rshiftSU, + rshiftDI, rshiftDU, ltSI, ltSU, ltDI, ltDU, ltSF, ltDF, ltXF, ltP, leSI, + leSU, leDI, leDU, leSF, leDF, leXF, leP, geSI, geSU, geDI, geDU, geSF, + geDF, geXF, geP, gtSI, gtSU, gtDI, gtDU, gtSF, gtDF, gtXF, gtP, eqSI, + eqDI, eqSF, eqDF, eqXF, eqP, neSI, neDI, neSF, neDF, neXF, neP, negSI, + negDI, negSF, negDF, negXF, notSI, notDI, notT, predecQI, predecHI, + predecSI, predecDI, predecP, predecSF, predecDF, predecXF, predecBI, + preincQI, preincHI, preincSI, preincDI, preincP, preincSF, preincDF, + preincXF, preincBI, postdecQI, postdecHI, postdecSI, postdecDI, postdecP, + postdecSF, postdecDF, postdecXF, postdecBI, postincQI, postincHI, + postincSI, postincDI, postincP, postincSF, postincDF, postincXF, + postincBI, xjumpif, xjumpifnot, jump, jumpP, caseSI, caseSU, caseDI, + caseDU, call, returnP, ret, linenote, LAST_AND_UNUSED_OPCODE +}; +struct binary_operator +{ + enum bytecode_opcode opcode; + enum typecode arg0; +}; +static struct conversion_recipe +{ + unsigned char *opcodes; + int cost; +} +conversion_recipe[((int) LAST_AND_UNUSED_TYPECODE)][((int) + LAST_AND_UNUSED_TYPECODE)]; +static struct conversion_recipe +deduce_conversion (from, to) + enum typecode from, to; +{ + (conversion_recipe[(int) from][(int) to]. + opcodes ? 0 : (conversion_recipe[(int) from][(int) to] = + deduce_conversion (from, to), 0)); +} + +void +bc_expand_binary_operation (optab, resulttype, arg0, arg1) + struct binary_operator optab[]; +{ + int i, besti, cost, bestcost; + enum typecode resultcode, arg0code; + for (i = 0; optab[i].opcode != -1; ++i) + { + (conversion_recipe[(int) arg0code][(int) optab[i].arg0]. + opcodes ? 0 : (conversion_recipe[(int) arg0code][(int) optab[i].arg0] = + deduce_conversion (arg0code, optab[i].arg0), 0)); + } +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr58673-2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr58673-2.c new file mode 100644 index 000000000..b70d2eed8 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr58673-2.c @@ -0,0 +1,217 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O3 -m64 -funroll-loops" } */ + +#include <stddef.h> +#include <stdlib.h> +#include <math.h> +#include <string.h> + +typedef long unsigned int size_t; +typedef struct _IO_FILE FILE; +typedef float real; +typedef real rvec[3]; +typedef real matrix[3][3]; +typedef real tensor[3][3]; +enum +{ + F_BONDS, F_G96BONDS, F_MORSE, F_CUBICBONDS, F_CONNBONDS, F_HARMONIC, + F_ANGLES, F_G96ANGLES, F_PDIHS, F_RBDIHS, F_IDIHS, F_LJ14, F_COUL14, F_LJ, + F_BHAM, F_LJLR, F_DISPCORR, F_SR, F_LR, F_WPOL, F_POSRES, F_DISRES, + F_DISRESVIOL, F_ORIRES, F_ORIRESDEV, F_ANGRES, F_ANGRESZ, F_SHAKE, + F_SHAKENC, F_SETTLE, F_DUMMY2, F_DUMMY3, F_DUMMY3FD, F_DUMMY3FAD, + F_DUMMY3OUT, F_DUMMY4FD, F_EQM, F_EPOT, F_EKIN, F_ETOT, F_TEMP, F_PRES, + F_DVDL, F_DVDLKIN, F_NRE +}; +typedef union +{ + struct + { + } + bham; + struct + { + real rA, krA, rB, krB; + } + harmonic; +} +t_iparams; +typedef struct +{ + t_iparams *iparams; +} +t_idef; +typedef struct +{ +} +t_inputrec; +typedef struct +{ +} +t_commrec; +typedef struct +{ +} +t_forcerec; +typedef struct +{ +} +t_mdatoms; +typedef struct +{ +} +t_filenm; +enum +{ + eoPres, eoEpot, eoVir, eoDist, eoMu, eoForce, eoFx, eoFy, eoFz, eoPx, eoPy, + eoPz, eoPolarizability, eoDipole, eoObsNR, eoMemory = + eoObsNR, eoInter, eoUseVirial, eoNR +}; +extern char *eoNames[eoNR]; +typedef struct +{ + int bPrint; +} +t_coupl_LJ; +typedef struct +{ + int eObs; + t_iparams xi; +} +t_coupl_iparams; +typedef struct +{ + real act_value[eoObsNR]; + real av_value[eoObsNR]; + real ref_value[eoObsNR]; + int bObsUsed[eoObsNR]; + int nLJ, nBU, nQ, nIP; + t_coupl_LJ *tcLJ; +} +t_coupl_rec; +static void +pr_ff (t_coupl_rec * tcr, real time, t_idef * idef, t_commrec * cr, int nfile, + t_filenm fnm[]) +{ + static FILE *prop; + static FILE **out = ((void *) 0); + static FILE **qq = ((void *) 0); + static FILE **ip = ((void *) 0); + char buf[256]; + char *leg[] = { + "C12", "C6" + }; + char **raleg; + int i, j, index; + if ((prop == ((void *) 0)) && (out == ((void *) 0)) && (qq == ((void *) 0)) + && (ip == ((void *) 0))) + { + for (i = j = 0; (i < eoObsNR); i++) + { + if (tcr->bObsUsed[i]) + { + raleg[j++] = + (__extension__ + (__builtin_constant_p (eoNames[i]) + && ((size_t) (const void *) ((eoNames[i]) + 1) - + (size_t) (const void *) (eoNames[i]) == + 1) ? (((const char *) (eoNames[i]))[0] == + '\0' ? (char *) calloc ((size_t) 1, + (size_t) 1) : ( + { + size_t + __len + = + strlen + (eoNames + [i]) + + + 1; + char + *__retval + = + (char + *) + malloc + (__len); + __retval;} + )): __strdup (eoNames[i]))); + raleg[j++] = + (__extension__ + (__builtin_constant_p (buf) + && ((size_t) (const void *) ((buf) + 1) - + (size_t) (const void *) (buf) == + 1) ? (((const char *) (buf))[0] == + '\0' ? (char *) calloc ((size_t) 1, + (size_t) 1) : ( + { + size_t + __len + = + strlen + (buf) + + + 1; + char + *__retval + = + (char + *) + malloc + (__len); + __retval;} + )): __strdup (buf))); + } + } + if (tcr->nLJ) + { + for (i = 0; (i < tcr->nLJ); i++) + { + if (tcr->tcLJ[i].bPrint) + { + xvgr_legend (out[i], (sizeof (leg) / sizeof ((leg)[0])), + leg); + } + } + } + } +} + +void +do_coupling (FILE * log, int nfile, t_filenm fnm[], t_coupl_rec * tcr, real t, + int step, real ener[], t_forcerec * fr, t_inputrec * ir, + int bMaster, t_mdatoms * md, t_idef * idef, real mu_aver, + int nmols, t_commrec * cr, matrix box, tensor virial, + tensor pres, rvec mu_tot, rvec x[], rvec f[], int bDoIt) +{ + int i, j, ati, atj, atnr2, type, ftype; + real deviation[eoObsNR], prdev[eoObsNR], epot0, dist, rmsf; + real ff6, ff12, ffa, ffb, ffc, ffq, factor, dt, mu_ind; + int bTest, bPrint; + t_coupl_iparams *tip; + if (bPrint) + { + pr_ff (tcr, t, idef, cr, nfile, fnm); + } + for (i = 0; (i < eoObsNR); i++) + { + deviation[i] = + calc_deviation (tcr->av_value[i], tcr->act_value[i], + tcr->ref_value[i]); + prdev[i] = tcr->ref_value[i] - tcr->act_value[i]; + } + if (bPrint) + pr_dev (tcr, t, prdev, cr, nfile, fnm); + for (i = 0; (i < atnr2); i++) + { + factor = dt * deviation[tip->eObs]; + switch (ftype) + { + case F_BONDS: + if (fabs (tip->xi.harmonic.krA) > 1.2e-38) + idef->iparams[type].harmonic.krA *= + (1 + factor / tip->xi.harmonic.krA); + } + } +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr59054.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr59054.c new file mode 100644 index 000000000..ab2ff6dea --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr59054.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O0 -m64" } */ + +long foo (void) { return 0; } + +/* { dg-final { scan-assembler-not "xxlor" } } */ +/* { dg-final { scan-assembler-not "stfd" } } */ diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60137.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60137.c new file mode 100644 index 000000000..4777a5382 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60137.c @@ -0,0 +1,17 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O3 -mno-vsx" } */ + +/* target/60137, compiler got a 'could not split insn error'. */ + +extern int target_flags; +extern char fixed_regs[53]; +extern char call_used_regs[53]; + +void init_reg_sets_1(void) +{ + int i; + for (i = 0; i < 53; i++) + fixed_regs[i] = call_used_regs[i] = (call_used_regs[i] &((target_flags & 0x02000000) ? 2 : 1)) != 0; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60203.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60203.c new file mode 100644 index 000000000..6a4b4fa1d --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60203.c @@ -0,0 +1,40 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mcpu=power8 -O3" } */ + +union u_ld { long double ld; double d[2]; }; + +long double +pack (double a, double aa) +{ + union u_ld u; + u.d[0] = a; + u.d[1] = aa; + return u.ld; +} + +double +unpack_0 (long double x) +{ + union u_ld u; + u.ld = x; + return u.d[0]; +} + +double +unpack_1 (long double x) +{ + union u_ld u; + u.ld = x; + return u.d[1]; +} + +/* { dg-final { scan-assembler-not "stfd" } } */ +/* { dg-final { scan-assembler-not "lfd" } } */ +/* { dg-final { scan-assembler-not "lxsdx" } } */ +/* { dg-final { scan-assembler-not "stxsdx" } } */ +/* { dg-final { scan-assembler-not "mfvsrd" } } */ +/* { dg-final { scan-assembler-not "mtvsrd" } } */ + + diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60735.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60735.c new file mode 100644 index 000000000..9bac30b51 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60735.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=8548 -mspe -mabi=spe -O2" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ + +/* In PR60735, the type _Decimal64 generated an insn not found message. */ + +void +pr60735 (_Decimal64 *p, _Decimal64 *q) +{ + *p = *q; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/quad-atomic.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/quad-atomic.c new file mode 100644 index 000000000..6cf278852 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/quad-atomic.c @@ -0,0 +1,67 @@ +/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ +/* { dg-require-effective-target p8vector_hw } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +/* Test whether we get the right bits for quad word atomic instructions. */ +#include <stdlib.h> + +static __int128_t quad_fetch_and (__int128_t *, __int128_t value) __attribute__((__noinline__)); +static __int128_t quad_fetch_or (__int128_t *, __int128_t value) __attribute__((__noinline__)); +static __int128_t quad_fetch_add (__int128_t *, __int128_t value) __attribute__((__noinline__)); + +static __int128_t +quad_fetch_and (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_and (ptr, value, __ATOMIC_ACQUIRE); +} + +static __int128_t +quad_fetch_or (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_or (ptr, value, __ATOMIC_ACQUIRE); +} + +static __int128_t +quad_fetch_add (__int128_t *ptr, __int128_t value) +{ + return __atomic_fetch_add (ptr, value, __ATOMIC_ACQUIRE); +} + +int +main (void) +{ + __int128_t result; + __int128_t value; + __int128_t and_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL)); + __int128_t and_value = ((((__int128_t) 0xfffffffffffffff0ULL) << 64) | ((__int128_t) 0xfffffffffffffff0ULL)); + __int128_t and_exp = ((((__int128_t) 0x1234567890abcde0ULL) << 64) | ((__int128_t) 0xfedcba0987654320ULL)); + + __int128_t or_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL)); + __int128_t or_value = ((((__int128_t) 0x0000000000000010ULL) << 64) | ((__int128_t) 0x000000000000000eULL)); + __int128_t or_exp = ((((__int128_t) 0x1234567890abcdffULL) << 64) | ((__int128_t) 0xfedcba098765432fULL)); + + __int128_t add_input = ((((__int128_t) 0x1234567890abcdefULL) << 64) | ((__int128_t) 0xfedcba0987654321ULL)); + __int128_t add_value = ((((__int128_t) 0x0000000001000000ULL) << 64) | ((__int128_t) 0x0000001000000000ULL)); + __int128_t add_exp = ((((__int128_t) 0x1234567891abcdefULL) << 64) | ((__int128_t) 0xfedcba1987654321ULL)); + + + value = and_input; + result = quad_fetch_and (&value, and_value); + if (result != and_input || value != and_exp) + abort (); + + value = or_input; + result = quad_fetch_or (&value, or_value); + if (result != or_input || value != or_exp) + abort (); + + value = add_input; + result = quad_fetch_add (&value, add_value); + if (result != add_input || value != add_exp) + abort (); + + return 0; +} + diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c new file mode 100644 index 000000000..1c78052e6 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c @@ -0,0 +1,21 @@ +/* Test accuracy of long double division (glibc bug 15396). */ +/* { dg-do run { target powerpc*-*-linux* powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* } } */ +/* { dg-options "-mlong-double-128" } */ + +extern void exit (int); +extern void abort (void); + +volatile long double a = 0x1p-1024L; +volatile long double b = 0x3p-53L; +volatile long double r; +volatile long double expected = 0x1.55555555555555555555555555p-973L; + +int +main (void) +{ + r = a / b; + /* Allow error up to 2ulp. */ + if (__builtin_fabsl (r - expected) > 0x1p-1073L) + abort (); + exit (0); +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c new file mode 100644 index 000000000..98f7615da --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power6 -mhard-dfp" } */ +/* { dg-final { scan-assembler-not "lfiwzx" } } */ +/* { dg-final { scan-assembler-times "lfd" 2 } } */ +/* { dg-final { scan-assembler-times "dctdp" 2 } } */ +/* { dg-final { scan-assembler-times "dadd" 1 } } */ +/* { dg-final { scan-assembler-times "drsp" 1 } } */ + +/* Test that for power6 we need to use a bounce buffer on the stack to load + SDmode variables because the power6 does not have a way to directly load + 32-bit values from memory. */ +_Decimal32 a; + +void inc_dec32 (void) +{ + a += (_Decimal32) 1.0; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-vsx.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-vsx.c new file mode 100644 index 000000000..7a3c6d877 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-vsx.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* powerpc-ibm-aix* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7 -mhard-dfp" } */ +/* { dg-final { scan-assembler-times "lfiwzx" 2 } } */ +/* { dg-final { scan-assembler-times "stfiwx" 1 } } */ +/* { dg-final { scan-assembler-not "lfd" } } */ +/* { dg-final { scan-assembler-not "stfd" } } */ +/* { dg-final { scan-assembler-times "dctdp" 2 } } */ +/* { dg-final { scan-assembler-times "dadd" 1 } } */ +/* { dg-final { scan-assembler-times "drsp" 1 } } */ + +/* Test that power7 can directly load/store SDmode variables without using a + bounce buffer. */ +_Decimal32 a; + +void inc_dec32 (void) +{ + a += (_Decimal32) 1.0; +} diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ti_math1.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ti_math1.c new file mode 100644 index 000000000..cdf925100 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ti_math1.c @@ -0,0 +1,20 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-times "addc" 1 } } */ +/* { dg-final { scan-assembler-times "adde" 1 } } */ +/* { dg-final { scan-assembler-times "subfc" 1 } } */ +/* { dg-final { scan-assembler-times "subfe" 1 } } */ +/* { dg-final { scan-assembler-not "subf " } } */ + +__int128 +add_128 (__int128 *ptr, __int128 val) +{ + return (*ptr + val); +} + +__int128 +sub_128 (__int128 *ptr, __int128 val) +{ + return (*ptr - val); +} + diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ti_math2.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ti_math2.c new file mode 100644 index 000000000..b9c03300d --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/ti_math2.c @@ -0,0 +1,73 @@ +/* { dg-do run { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2 -fno-inline" } */ + +union U { + __int128 i128; + struct { + long l1; + long l2; + } s; +}; + +union U u1,u2; + +__int128 +create_128 (long most_sig, long least_sig) +{ + union U u; + +#if __LITTLE_ENDIAN__ + u.s.l1 = least_sig; + u.s.l2 = most_sig; +#else + u.s.l1 = most_sig; + u.s.l2 = least_sig; +#endif + return u.i128; +} + +long most_sig (union U * u) +{ +#if __LITTLE_ENDIAN__ + return (*u).s.l2; +#else + return (*u).s.l1; +#endif +} + +long least_sig (union U * u) +{ +#if __LITTLE_ENDIAN__ + return (*u).s.l1; +#else + return (*u).s.l2; +#endif +} + +__int128 +add_128 (__int128 *ptr, __int128 val) +{ + return (*ptr + val); +} + +__int128 +sub_128 (__int128 *ptr, __int128 val) +{ + return (*ptr - val); +} + +int +main (void) +{ + /* Do a simple add/sub to make sure carry is happening between the dwords + and that dwords are in correct endian order. */ + u1.i128 = create_128 (1, -1); + u2.i128 = add_128 (&u1.i128, 1); + if ((most_sig (&u2) != 2) || (least_sig (&u2) != 0)) + __builtin_abort (); + u2.i128 = sub_128 (&u2.i128, 1); + if ((most_sig (&u2) != 1) || (least_sig (&u2) != -1)) + __builtin_abort (); + return 0; +} + diff --git a/gcc-4.8/gcc/testsuite/gcc.target/powerpc/vsx-float0.c b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/vsx-float0.c new file mode 100644 index 000000000..7e4fea689 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/gcc.target/powerpc/vsx-float0.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xxlxor" } } */ + +/* Test that we generate xxlor to clear a SFmode register. */ + +float sum (float *p, unsigned long n) +{ + float sum = 0.0f; /* generate xxlxor instead of load */ + while (n-- > 0) + sum += *p++; + + return sum; +} |